diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml
index 082cd01807..91a3f88a1a 100644
--- a/.github/workflows/action.yml
+++ b/.github/workflows/action.yml
@@ -35,10 +35,15 @@ jobs:
- {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
+ - {RTT_BSP: "gd32/gd32103c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
+ - {RTT_BSP: "gd32/gd32105c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32/gd32105r-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+ - {RTT_BSP: "gd32/gd32107c-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32/gd32205r-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+ - {RTT_BSP: "gd32/gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32/gd32305r-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32/gd32407v-start", RTT_TOOL_CHAIN: "sourcery-arm"}
+ - {RTT_BSP: "gd32/gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"}
- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
diff --git a/.github/workflows/action_tools.yml b/.github/workflows/action_tools.yml
new file mode 100644
index 0000000000..7c59ae7b37
--- /dev/null
+++ b/.github/workflows/action_tools.yml
@@ -0,0 +1,82 @@
+name: ToolsCI
+
+# Controls when the action will run. Triggers the workflow on push or pull request
+# events but only for the master branch
+on:
+ # Runs at 16:00 UTC (BeiJing 00:00) on the 1st of every month
+ schedule:
+ - cron: '0 16 1 * *'
+ push:
+ branches:
+ - master
+ paths-ignore:
+ - documentation/**
+ - '**/README.md'
+ - '**/README_zh.md'
+ - '**/*.c'
+ - '**/*.h'
+ - '**/*.cpp'
+ pull_request:
+ branches:
+ - master
+ paths-ignore:
+ - documentation/**
+ - '**/README.md'
+ - '**/README_zh.md'
+ - '**/*.c'
+ - '**/*.h'
+ - '**/*.cpp'
+
+jobs:
+ test:
+ runs-on: ubuntu-latest
+ name: Tools
+ strategy:
+ fail-fast: false
+ env:
+ TEST_BSP_ROOT: bsp/stm32/stm32f407-atk-explorer
+ steps:
+ - uses: actions/checkout@v1
+
+ - name: Install Tools
+ shell: bash
+ run: |
+ sudo apt-get update
+ sudo apt-get -yqq install scons
+
+ - name: Install Arm ToolChains
+ if: ${{ success() }}
+ shell: bash
+ run: |
+ wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.3/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2
+ sudo tar xjf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C /opt
+ /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc --version
+ echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-10-2020-q4-major/bin" >> $GITHUB_ENV
+
+ - name: Build Tools
+ run: |
+ scons --pyconfig-silent -C $TEST_BSP_ROOT
+ scons -j$(nproc) -C $TEST_BSP_ROOT
+
+ - name: Project generate Tools
+ if: ${{ success() }}
+ run: |
+ echo "Test to generate mdk project"
+ scons --target=mdk -s -C $TEST_BSP_ROOT
+ scons --target=mdk4 -s -C $TEST_BSP_ROOT
+ scons --target=mdk5 -s -C $TEST_BSP_ROOT
+ echo "Test to generate iar project"
+ scons --target=iar -s -C $TEST_BSP_ROOT
+ echo "Test to generate eclipse project"
+ scons --target=eclipse -s -C $TEST_BSP_ROOT
+ echo "Test to generate cmake project"
+ scons --target=cmake -s -C $TEST_BSP_ROOT
+ echo "Test to generate makefile project"
+ scons --target=makefile -s -C $TEST_BSP_ROOT
+
+ - name: Project dist Tools
+ if: ${{ success() }}
+ run: |
+ echo "Test to dist project"
+ scons --dist -C $TEST_BSP_ROOT
+ scons --dist-ide -C $TEST_BSP_ROOT
diff --git a/.github/workflows/action_utest.yml b/.github/workflows/action_utest.yml
index b83fd21bdd..cb7707059b 100644
--- a/.github/workflows/action_utest.yml
+++ b/.github/workflows/action_utest.yml
@@ -1,7 +1,25 @@
name: AutoTestCI
# Controls when the action will run. Triggers the workflow on push or pull request
-on: [push, pull_request]
+# events but only for the master branch
+on:
+ # Runs at 16:00 UTC (BeiJing 00:00) on the 1st of every month
+ schedule:
+ - cron: '0 16 1 * *'
+ push:
+ branches:
+ - master
+ paths-ignore:
+ - documentation/**
+ - '**/README.md'
+ - '**/README_zh.md'
+ pull_request:
+ branches:
+ - master
+ paths-ignore:
+ - documentation/**
+ - '**/README.md'
+ - '**/README_zh.md'
jobs:
test:
diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c
index dc98fe7c4d..60c4d0790b 100644
--- a/bsp/at91sam9260/platform/interrupt.c
+++ b/bsp/at91sam9260/platform/interrupt.c
@@ -396,6 +396,28 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
at91_sys_write(AT91_AIC_EOICR, 0x0);
}
+void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
+{
+ rt_isr_handler_t isr_func;
+ rt_uint32_t irq;
+ void *param;
+
+ /* get irq number */
+ irq = rt_hw_interrupt_get_active(fiq_irq);
+
+ /* get interrupt service routine */
+ isr_func = irq_desc[irq].handler;
+ param = irq_desc[irq].param;
+
+ /* turn to interrupt service routine */
+ isr_func(irq, param);
+
+ rt_hw_interrupt_ack(fiq_irq, irq);
+#ifdef RT_USING_INTERRUPT_INFO
+ irq_desc[irq].counter ++;
+#endif
+}
+
#ifdef RT_USING_FINSH
#ifdef RT_USING_INTERRUPT_INFO
void list_irq(void)
diff --git a/bsp/at91sam9260/template.uvopt b/bsp/at91sam9260/template.uvopt
index 2dca5102b8..7454a3661d 100644
--- a/bsp/at91sam9260/template.uvopt
+++ b/bsp/at91sam9260/template.uvopt
@@ -13,6 +13,7 @@
*.txt; *.h; *.inc
*.plm
*.cpp
+ 0
@@ -31,6 +32,7 @@
1
1
0
+ 0
1
@@ -108,10 +110,10 @@
1
1
1
- 1
0
0
- 5
+ 1
+ 18
@@ -168,6 +170,13 @@
+ 0
+ 0
+ 0
+
+
+
+
diff --git a/bsp/at91sam9260/template.uvproj b/bsp/at91sam9260/template.uvproj
index c644bc5440..6e4ee85615 100644
--- a/bsp/at91sam9260/template.uvproj
+++ b/bsp/at91sam9260/template.uvproj
@@ -72,14 +72,18 @@
0
0
+ 0
+ 0
- 0
+ 1
0
-
+ fromelf.exe --bin -o $L@L.bin #L
0
0
+ 0
+ 0
0
@@ -141,10 +145,9 @@
1
1
1
- 1
0
- 5
+ 18
@@ -224,6 +227,7 @@
0
0
0
+ 0
3
3
0
@@ -356,8 +360,15 @@
2
0
0
- 0
+ 1
0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
RT_USING_INTERRUPT_INFO
@@ -375,6 +386,7 @@
0
0
0
+ 0
diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c b/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c
index 50681e7bc6..317dd4c862 100644
--- a/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c
+++ b/bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c
@@ -14,7 +14,11 @@
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#include "drv_gpio.h"
// #define DRV_DEBUG
diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript
index 3321a76d91..625f186203 100644
--- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript
+++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript
@@ -18,12 +18,14 @@ DEPENDS = [""]
# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
#
# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
-# LOCAL_CCFLAGS: Local compilation parameter
+# LOCAL_CFLAGS: Local c compilation parameter
+# LOCAL_CCFLAGS: Local c/c++ compilation parameter
+# LOCAL_CXXFLAGS: Local c++ compilation parameter
# LOCAL_ASFLAGS: Local assembly parameters
#
# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH
# is empty # no pass!!!
-# CCFLAGS: Global compilation parameter
+# CFLAGS : Global compilation parameter
# ASFLAGS: Global assembly parameters
#
# CPPDEFINES: Global macro definition
@@ -37,12 +39,16 @@ DEPENDS = [""]
CWD = GetCurrentDir()
SOURCES = Glob("./source/*.c")
-LOCAL_CPPPATH = []
-LOCAL_CCFLAGS = ""
+LOCAL_CPPPATH = []
+LOCAL_CFLAGS = ""
+LOCAL_CCFLAGS = ""
+LOCAL_CXXFLAGS = ""
LOCAL_ASFLAGS = ""
CPPPATH = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')]
-CCFLAGS = ""
+CFLAGS = ""
+CCFLAGS = ""
+CXXFLAGS = ""
ASFLAGS = ""
CPPDEFINES = []
@@ -61,10 +67,14 @@ CPPPATH_IGNORE = []
#---------------------------------------------------------------------------------
objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS,
CPPPATH = CPPPATH,
+ CFLAGS = CFLAGS,
CCFLAGS = CCFLAGS,
+ CXXFLAGS = CXXFLAGS,
ASFLAGS = ASFLAGS,
LOCAL_CPPPATH = LOCAL_CPPPATH,
+ LOCAL_CFLAGS = LOCAL_CFLAGS,
LOCAL_CCFLAGS = LOCAL_CCFLAGS,
+ LOCAL_CXXFLAGS = LOCAL_CXXFLAGS,
LOCAL_ASFLAGS = LOCAL_ASFLAGS,
CPPDEFINES = CPPDEFINES,
LOCAL_CPPDEFINES = LOCAL_CPPDEFINES,
diff --git a/bsp/bluetrum/libraries/hal_libraries/bmsis/SConscript b/bsp/bluetrum/libraries/hal_libraries/bmsis/SConscript
index 9a82897032..a395e0acf8 100644
--- a/bsp/bluetrum/libraries/hal_libraries/bmsis/SConscript
+++ b/bsp/bluetrum/libraries/hal_libraries/bmsis/SConscript
@@ -19,12 +19,14 @@ DEPENDS = [""]
# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
#
# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
-# LOCAL_CCFLAGS: Local compilation parameter
+# LOCAL_CFLAGS: Local c compilation parameter
+# LOCAL_CCFLAGS: Local c/c++ compilation parameter
+# LOCAL_CXXFLAGS: Local c++ compilation parameter
# LOCAL_ASFLAGS: Local assembly parameters
#
# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH
# is empty # no pass!!!
-# CCFLAGS: Global compilation parameter
+# CFLAGS : Global compilation parameter
# ASFLAGS: Global assembly parameters
#
# CPPDEFINES: Global macro definition
@@ -35,22 +37,26 @@ DEPENDS = [""]
#
# LINKFLAGS: Link options
#---------------------------------------------------------------------------------
+CWD = GetCurrentDir()
SOURCES = Glob("./source/*.c")
-SOURCES += Glob("./source/*.S")
-LOCAL_CPPPATH = []
-LOCAL_CCFLAGS = ""
+LOCAL_CPPPATH = []
+LOCAL_CFLAGS = ""
+LOCAL_CCFLAGS = ""
+LOCAL_CXXFLAGS = ""
LOCAL_ASFLAGS = ""
CPPPATH = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')]
-CCFLAGS = ""
+CFLAGS = ""
+CCFLAGS = ""
+CXXFLAGS = ""
ASFLAGS = ""
CPPDEFINES = []
LOCAL_CPPDEFINES = []
LIBS = []
-LIBPATH = []
+LIBPATH = []
LINKFLAGS = ""
@@ -62,10 +68,14 @@ CPPPATH_IGNORE = []
#---------------------------------------------------------------------------------
objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS,
CPPPATH = CPPPATH,
+ CFLAGS = CFLAGS,
CCFLAGS = CCFLAGS,
+ CXXFLAGS = CXXFLAGS,
ASFLAGS = ASFLAGS,
LOCAL_CPPPATH = LOCAL_CPPPATH,
+ LOCAL_CFLAGS = LOCAL_CFLAGS,
LOCAL_CCFLAGS = LOCAL_CCFLAGS,
+ LOCAL_CXXFLAGS = LOCAL_CXXFLAGS,
LOCAL_ASFLAGS = LOCAL_ASFLAGS,
CPPDEFINES = CPPDEFINES,
LOCAL_CPPDEFINES = LOCAL_CPPDEFINES,
diff --git a/bsp/ck802/applications/SConscript b/bsp/ck802/applications/SConscript
index 78698e4ad3..8cffec4949 100644
--- a/bsp/ck802/applications/SConscript
+++ b/bsp/ck802/applications/SConscript
@@ -6,8 +6,8 @@ cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
-CCFLAGS = ' -c -mistack -ffunction-sections'
+CFLAGS = ' -c -mistack -ffunction-sections'
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CFLAGS=CFLAGS)
Return('group')
diff --git a/bsp/efm32/application.c b/bsp/efm32/application.c
index 332dcc6ba8..5f2ad9866c 100644
--- a/bsp/efm32/application.c
+++ b/bsp/efm32/application.c
@@ -65,10 +65,18 @@
#include
#include
-#if defined(RTGUI_USING_DFS_FILERW)
+ #if defined(RTGUI_USING_DFS_FILERW)
#include
#define PATH_SEPARATOR '/'
#endif
+#if defined(RTGUI_USING_DFS_FILERW)
+#include
+#include
+#include
+#include
+#include
+#define PATH_SEPARATOR '/'
+#endif
#endif
/* Private typedef -----------------------------------------------------------*/
diff --git a/bsp/ft2004/drivers/drv_sdcard.c b/bsp/ft2004/drivers/drv_sdcard.c
index a6494089f6..753a70b606 100644
--- a/bsp/ft2004/drivers/drv_sdcard.c
+++ b/bsp/ft2004/drivers/drv_sdcard.c
@@ -14,7 +14,11 @@
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#include "drv_sdctrl.h"
#define DBG_TAG "app.card"
diff --git a/bsp/gd32/README.md b/bsp/gd32/README.md
index fb706c2723..5937be20aa 100644
--- a/bsp/gd32/README.md
+++ b/bsp/gd32/README.md
@@ -6,13 +6,18 @@ GD32 系列 BSP 目前支持情况如下表所示：
| **BSP 文件夹名称** | **开发板名称** |
|:------------------------- |:-------------------------- |
| **F1 系列** | |
-| [gd32105r-start](gd32105r-start) | 兆易创新 官方 GD32105r-START 开发板 |
+| [gd32103c-eval](gd32103c-eval) | 兆易创新 官方 GD32103C-EVAL 开发板 |
+| [gd32105c-eval](gd32105c-eval) | 兆易创新 官方 GD32105C-EVAL 开发板 |
+| [gd32105r-start](gd32105r-start) | 兆易创新 官方 GD32105R-START 开发板 |
+| [gd32107c-eval](gd32107c-eval) | 兆易创新 官方 GD32107C-EVAL 开发板 |
| **F2 系列** | |
-| [gd32205r-start](gd32205r-start) | 兆易创新 官方 GD32205r-START 开发板 |
+| [gd32205r-start](gd32205r-start) | 兆易创新 官方 GD32205R-START 开发板 |
| **F3 系列** | |
-| [gd32305r-start](gd32305r-start) | 兆易创新 官方 GD32305r-START 开发板 |
+| [gd32303e-eval](gd32303e-eval) | 兆易创新 官方 GD32303E-EVAL 开发板 |
+| [gd32305r-start](gd32305r-start) | 兆易创新 官方 GD32305R-START 开发板 |
| **F4 系列** | |
| [gd32407v-start](gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 |
+| [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
diff --git a/bsp/gd32/docs/GD32系列BSP制作教程.md b/bsp/gd32/docs/GD32系列BSP制作教程.md
index 6f0a4427f7..4e517348b5 100644
--- a/bsp/gd32/docs/GD32系列BSP制作教程.md
+++ b/bsp/gd32/docs/GD32系列BSP制作教程.md
@@ -145,14 +145,14 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
- CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
- env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
diff --git a/bsp/gd32/gd32103c-eval/.config b/bsp/gd32/gd32103c-eval/.config
new file mode 100644
index 0000000000..2b86e3f13b
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/.config
@@ -0,0 +1,636 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_BIG_ENDIAN is not set
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_RT_USING_ARDUINO is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_USB_STACK is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_SERIES_GD32F10x=y
+CONFIG_SOC_GD32103V=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/gd32/gd32103c-eval/Kconfig b/bsp/gd32/gd32103c-eval/Kconfig
new file mode 100644
index 0000000000..8cbc7b71a8
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/gd32/gd32103c-eval/README.md b/bsp/gd32/gd32103c-eval/README.md
new file mode 100644
index 0000000000..bb7e51279b
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/README.md
@@ -0,0 +1,94 @@
+# GD32103C-EVAL开发板BSP说明
+
+## 简介
+
+GD3103C-EVAL是-兆易创新推出的一款GD32F10X系列的评估板，最高主频高达108M，该开发板具有丰富的板载资源，可以充分发挥 GD32103VCT6的芯片性能。
+
+该开发板常用 **板载资源** 如下：
+
+- GD32103VCT6，主频 108MHz，256KB FLASH ，48KB RAM
+
+- 常用外设
+
+ - LED ：5个，LED1 (电源指示灯），LED2（PC0），LED3（PC2），LED4（PE0），LED5（PE1）
+ - 按键：3个，K1（用户按键，PA0），K2（用户按键，PC13），K3（用户按键，PB14）
+
+- 常用接口：USB 接口
+
+- 调试接口：GD-LINK
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+|:--------- |:--------:|:------------------------------------- |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART0 - UART7 |
+| I2C | 支持 | I2C1 |
+| SPI | 支持 | SPI0 - SPI2 |
+| SPI FLASH | 支持 | |
+| **扩展模块** | **支持情况** | **备注** |
+| 暂无 | 暂不支持 | 暂不支持 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.4 build Dec 19 2021 10:00:27
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [BruceOu](https://github.com/Ouxiaolong/), 邮箱：
\ No newline at end of file
diff --git a/components/libc/compilers/gcc/newlib/legacy/SConscript b/bsp/gd32/gd32103c-eval/SConscript
similarity index 86%
rename from components/libc/compilers/gcc/newlib/legacy/SConscript
rename to bsp/gd32/gd32103c-eval/SConscript
index 4c815c49b8..20f7689c53 100644
--- a/components/libc/compilers/gcc/newlib/legacy/SConscript
+++ b/bsp/gd32/gd32103c-eval/SConscript
@@ -1,6 +1,6 @@
-# RT-Thread building script for bridge
-
+# for module compiling
import os
+Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
diff --git a/bsp/gd32/gd32103c-eval/SConstruct b/bsp/gd32/gd32103c-eval/SConstruct
new file mode 100644
index 0000000000..49074397d0
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+gd32_library = 'GD32F10x_Firmware_Library'
+rtconfig.BSP_LIBRARY_TYPE = gd32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32103c-eval/applications/SConscript b/bsp/gd32/gd32103c-eval/applications/SConscript
similarity index 60%
rename from bsp/gd32103c-eval/applications/SConscript
rename to bsp/gd32/gd32103c-eval/applications/SConscript
index ca2395451a..01eb940dfb 100644
--- a/bsp/gd32103c-eval/applications/SConscript
+++ b/bsp/gd32/gd32103c-eval/applications/SConscript
@@ -2,9 +2,9 @@ Import('RTT_ROOT')
Import('rtconfig')
from building import *
-cwd = GetCurrentDir()
-src = Glob('*.c')
-CPPPATH = [cwd]
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
diff --git a/bsp/gd32/gd32103c-eval/applications/main.c b/bsp/gd32/gd32103c-eval/applications/main.c
new file mode 100644
index 0000000000..d13b24ab50
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/applications/main.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+
+#include
+#include
+#include
+#include
+
+/* defined the LED2 pin: PC0 */
+#define LED2_PIN GET_PIN(C, 0)
+
+int main(void)
+{
+ int count = 1;
+
+ /* set LED2 pin mode to output */
+ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED2_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED2_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/gd32103c-eval/Kconfig b/bsp/gd32/gd32103c-eval/board/Kconfig
similarity index 54%
rename from bsp/gd32103c-eval/Kconfig
rename to bsp/gd32/gd32103c-eval/board/Kconfig
index 97fb8f2b2c..354d212994 100644
--- a/bsp/gd32103c-eval/Kconfig
+++ b/bsp/gd32/gd32103c-eval/board/Kconfig
@@ -1,71 +1,90 @@
-mainmenu "RT-Thread Configuration"
+menu "Hardware Drivers Config"
-config BSP_DIR
- string
- option env="BSP_ROOT"
- default "."
-
-config RTT_DIR
- string
- option env="RTT_ROOT"
- default "../.."
-
-# you can change the RTT_ROOT default: "rt-thread"
-# example : default "F:/git_repositories/rt-thread"
-
-config PKGS_DIR
- string
- option env="PKGS_ROOT"
- default "packages"
-
-source "$RTT_DIR/Kconfig"
-source "$PKGS_DIR/Kconfig"
-
-config SOC_SERIES_GD32F1
+config SOC_SERIES_GD32F10x
bool
default y
-
-config SOC_GD32103C
+
+config SOC_GD32103V
bool
+ select SOC_SERIES_GD32F10x
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
- select SOC_SERIES_GD32F1
default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
- config BSP_USING_UART0
- bool "using uart0"
- default n
config BSP_USING_UART1
- bool "using uart1"
- default n
- config BSP_USING_UART2
- bool "using uart2"
+ bool "Enable UART1"
default y
- config BSP_USING_UART3
- bool "using uart3"
- default n
- config BSP_USING_UART4
- bool "using uart4"
+
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
- menuconfig BSP_USING_ADC
- bool "Enable ADC"
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
default n
- select RT_USING_ADC
- if BSP_USING_ADC
- config BSP_USING_ADC0
- bool "using adc0"
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
default n
- config BSP_USING_ADC1
- bool "using adc1"
+
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ depends on BSP_USING_SPI1
+ default n
+
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ depends on BSP_USING_SPI1
+ select BSP_SPI1_TX_USING_DMA
default n
endif
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 216
+ default 24
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 216
+ default 25
+ endif
+
+ config BSP_USING_WDT
+ bool "Enable Watchdog Timer"
+ select RT_USING_WDT
+ default n
+
+ config BSP_USING_RTC
+ bool "Enable Internal RTC"
+ select RT_USING_RTC
+ default n
+
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
@@ -96,14 +115,25 @@ menu "On-chip Peripheral Drivers"
bool "using hwtimer7"
default n
endif
- config BSP_USING_WDT
- bool "Enable Watchdog Timer"
- select RT_USING_WDT
- default n
- config BSP_USING_RTC
- bool "using internal rtc"
+ menuconfig BSP_USING_ADC
+ bool "Enable ADC"
default n
- select RT_USING_RTC
+ select RT_USING_ADC
+ if BSP_USING_ADC
+ config BSP_USING_ADC0
+ bool "using adc0"
+ default n
+ config BSP_USING_ADC1
+ bool "using adc1"
+ default n
+ endif
+ source "../libraries/gd32_drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
endmenu
diff --git a/bsp/gd32/gd32103c-eval/board/SConscript b/bsp/gd32/gd32103c-eval/board/SConscript
new file mode 100644
index 0000000000..95b0a6e9ac
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/board/SConscript
@@ -0,0 +1,28 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path = [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_hd.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s']
+
+CPPDEFINES = ['GD32F10X_HD']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/gd32103c-eval/drivers/board.c b/bsp/gd32/gd32103c-eval/board/board.c
similarity index 73%
rename from bsp/gd32103c-eval/drivers/board.c
rename to bsp/gd32/gd32103c-eval/board/board.c
index 0e4d1a1305..c409645b37 100644
--- a/bsp/gd32103c-eval/drivers/board.c
+++ b/bsp/gd32/gd32103c-eval/board/board.c
@@ -4,29 +4,40 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
- * Date Author Notes
- * 2021-01-04 iysheng first version
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
*/
-
#include
#include
#include
-
-#include
#include
-#include
-/*
- * System Clock Configuration
- */
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @param None
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler */
+ /* User can add his own implementation to report the HAL error return state */
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
void SystemClock_Config(void)
{
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
}
-/*
+/**
* This is the timer interrupt service routine.
+ *
*/
void SysTick_Handler(void)
{
@@ -60,7 +71,7 @@ void rt_hw_board_init()
rt_components_board_init();
#endif
-#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
diff --git a/bsp/gd32/gd32103c-eval/board/board.h b/bsp/gd32/gd32103c-eval/board/board.h
new file mode 100644
index 0000000000..2eb804a9af
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/board/board.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "gd32f10x.h"
+#include "drv_usart.h"
+#include "drv_gpio.h"
+
+#include "gd32f10x_exti.h"
+
+#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
+#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
+
+// Internal SRAM memory size[Kbytes] <8-48>
+// Default: 48
+#ifdef __ICCARM__
+// Use *.icf ram symbal, to avoid hardcode.
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE 48
+#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END GD32_SRAM_END
+
+#endif
+
diff --git a/bsp/gd32/gd32103c-eval/board/gd32f10x_libopt.h b/bsp/gd32/gd32103c-eval/board/gd32f10x_libopt.h
new file mode 100644
index 0000000000..5292c8eca7
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/board/gd32f10x_libopt.h
@@ -0,0 +1,64 @@
+/*!
+ \file gd32f10x_libopt.h
+ \brief library optional for gd32f10x
+
+ \version 2014-12-26, V1.0.0, demo for GD32F10x
+ \version 2017-06-30, V2.0.0, demo for GD32F10x
+ \version 2021-04-30, V2.1.0, demo for GD32F10x
+*/
+
+/*
+ Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_LIBOPT_H
+#define GD32F10X_LIBOPT_H
+
+#include "gd32f10x_fmc.h"
+#include "gd32f10x_pmu.h"
+#include "gd32f10x_bkp.h"
+#include "gd32f10x_rcu.h"
+#include "gd32f10x_exti.h"
+#include "gd32f10x_gpio.h"
+#include "gd32f10x_crc.h"
+#include "gd32f10x_dma.h"
+#include "gd32f10x_dbg.h"
+#include "gd32f10x_adc.h"
+#include "gd32f10x_dac.h"
+#include "gd32f10x_fwdgt.h"
+#include "gd32f10x_wwdgt.h"
+#include "gd32f10x_rtc.h"
+#include "gd32f10x_timer.h"
+#include "gd32f10x_usart.h"
+#include "gd32f10x_i2c.h"
+#include "gd32f10x_spi.h"
+#include "gd32f10x_sdio.h"
+#include "gd32f10x_exmc.h"
+#include "gd32f10x_can.h"
+#include "gd32f10x_enet.h"
+#include "gd32f10x_misc.h"
+
+#endif /* GD32F10X_LIBOPT_H */
diff --git a/bsp/gd32/gd32103c-eval/board/linker_scripts/link.icf b/bsp/gd32/gd32103c-eval/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..c1b7bfa182
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/board/linker_scripts/link.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__ = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
\ No newline at end of file
diff --git a/bsp/gd32103c-eval/gd32_rom.ld b/bsp/gd32/gd32103c-eval/board/linker_scripts/link.ld
similarity index 94%
rename from bsp/gd32103c-eval/gd32_rom.ld
rename to bsp/gd32/gd32103c-eval/board/linker_scripts/link.ld
index 875d239e58..7bacb5ab4a 100644
--- a/bsp/gd32103c-eval/gd32_rom.ld
+++ b/bsp/gd32/gd32103c-eval/board/linker_scripts/link.ld
@@ -1,10 +1,6 @@
/*
- * linker script for GD32F1xx with GNU ld
- *
- * Change Logs:
- * Date Author Notes
- * 2009-10-14 bernard.xiong first implementation
- * 2021-01-02 iysheng modify to suite gd32f103c
+ * linker script for GD32F30x with GNU ld
+ * BruceOu 2021-12-18
*/
/* Program Entry, set to mark it as "used" and avoid gc */
diff --git a/bsp/gd32/gd32103c-eval/board/linker_scripts/link.sct b/bsp/gd32/gd32103c-eval/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..99f1f72a75
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x0000C000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/gd32/gd32103c-eval/project.uvoptx b/bsp/gd32/gd32103c-eval/project.uvoptx
new file mode 100644
index 0000000000..3cd7319e9d
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/project.uvoptx
@@ -0,0 +1,748 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
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+ 0x4
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+
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+
+
+
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+
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+ gd32f10x_usart.c
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+
+
+
+ ::CMSIS
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+
diff --git a/bsp/gd32/gd32103c-eval/project.uvproj b/bsp/gd32/gd32103c-eval/project.uvproj
new file mode 100644
index 0000000000..a9b71eca4c
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/project.uvproj
@@ -0,0 +1,737 @@
+
+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F103VC
+ GigaDevice
+ IRAM(0x20000000-0x20018000) IROM(0x08000000-0x08040000) CLOCK(10800000) CPUTYPE("Cortex-M3")
+
+ "Startup\GD\GD32F10x\startup_gd32f10x.s" ("GD32F10x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F10x_3MB -FS08000000 -FL0100000)
+ 0
+ gd32f10x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F10x\GD32F10x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F10x\
+ GD\GD32F10x\
+
+ 0
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+ .\output\
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+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
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+
+
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+ "" ()
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+ 0
+
+
+ GD32F10X_HD, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\libraries\GD32F10x_Firmware_Library\CMSIS;..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
+
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+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
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+
+
+
+
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+
+
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+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
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+
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+
+
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+
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+
+
+
+
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+ 2
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+
+
+
+
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+
+
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+ 1
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+
+
+
+
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+
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+
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+
+
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+
+
+
+
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+ 1
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+
+
+
+
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+ 1
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+
+
+
+
+ waitqueue.c
+ 1
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+
+
+
+
+ Drivers
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+
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+ 2
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+
+
+
+
+ board.c
+ 1
+ board\board.c
+
+
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\gd32_drivers\drv_gpio.c
+
+
+
+
+ drv_usart.c
+ 1
+ ..\libraries\gd32_drivers\drv_usart.c
+
+
+
+
+ Finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+
+
+ msh.c
+ 1
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+
+
+
+
+ cmd.c
+ 1
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+
+
+
+
+ Kernel
+
+
+ kservice.c
+ 1
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+
+
+
+
+ ipc.c
+ 1
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+
+
+
+
+ mem.c
+ 1
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+
+
+
+
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+ 1
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+
+
+
+
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+ 1
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+
+
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+
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+
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+
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+
+
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+
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+ 1
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+
+
+
+
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+ 1
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+
+
+
+
+ irq.c
+ 1
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+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+ libc
+
+
+ time.c
+ 1
+ ..\..\..\components\libc\compilers\common\time.c
+
+
+
+
+ Libraries
+
+
+ gd32f10x_exti.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+
+
+ gd32f10x_misc.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+
+
+ system_gd32f10x.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+
+
+ gd32f10x_usart.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32103c-eval/project.uvprojx b/bsp/gd32/gd32103c-eval/project.uvprojx
new file mode 100644
index 0000000000..297c9fc433
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/project.uvprojx
@@ -0,0 +1,668 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F103VC
+ GigaDevice
+ GigaDevice.GD32F10x_DFP.2.0.1
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x0000C000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(10800000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F103VC$Flash\GD32F10x_CL.FLM))
+ 0
+ $$Device:GD32F103VC$Device\Include\gd32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F103VC$SVD\GD32F10x\GD32F10x_CL.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rtthread
+ 1
+ 0
+ 0
+ 1
+ 0
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 0
+ fromelf --bin !L --output rtthread.bin
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 8
+ 0
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0xc000
+
+
+ 1
+ 0x8000000
+ 0x40000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x40000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x18000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+ GD32F10X_HD, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\libraries\GD32F10x_Firmware_Library\CMSIS;..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 4
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ CPU
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+
+
+ Drivers
+
+
+ startup_gd32f10x_hd.s
+ 2
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_hd.s
+
+
+ board.c
+ 1
+ board\board.c
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\gd32_drivers\drv_gpio.c
+
+
+ drv_usart.c
+ 1
+ ..\libraries\gd32_drivers\drv_usart.c
+
+
+
+
+ Finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+ msh.c
+ 1
+ ..\..\..\components\finsh\msh.c
+
+
+ cmd.c
+ 1
+ ..\..\..\components\finsh\cmd.c
+
+
+
+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+ libc
+
+
+ time.c
+ 1
+ ..\..\..\components\libc\compilers\common\time.c
+
+
+
+
+ Libraries
+
+
+ gd32f10x_exti.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+ gd32f10x_misc.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+ system_gd32f10x.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+ gd32f10x_usart.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/nuvoton/numaker-m032ki/rtconfig.h b/bsp/gd32/gd32103c-eval/rtconfig.h
similarity index 54%
rename from bsp/nuvoton/numaker-m032ki/rtconfig.h
rename to bsp/gd32/gd32103c-eval/rtconfig.h
index f2184d36fa..c461a768e1 100644
--- a/bsp/nuvoton/numaker-m032ki/rtconfig.h
+++ b/bsp/gd32/gd32103c-eval/rtconfig.h
@@ -10,20 +10,17 @@
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
+#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 512
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 512
+#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_DEBUG
+#define RT_DEBUG_COLOR
/* Inter-Thread communication */
@@ -37,19 +34,15 @@
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
-#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-#define ARCH_ARM
-#define ARCH_ARM_CORTEX_M
-#define ARCH_ARM_CORTEX_M0
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
/* RT-Thread Components */
@@ -79,54 +72,28 @@
/* Device virtual file system */
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_HWTIMER
#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_PM
-#define PM_TICKLESS_THRESHOLD_TIME 2
-#define RT_USING_RTC
-#define RT_USING_WDT
/* Using USB */
-#define RT_USING_USB
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define RT_USB_DEVICE_COMPOSITE
-#define RT_USB_DEVICE_NONE
-#define RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID_MOUSE
/* POSIX layer and C standard library */
+#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
-/* POSIX (Portable Operating System Interface) layer */
-
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
/* Network */
/* Socket abstraction layer */
@@ -146,24 +113,9 @@
/* Utilities */
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
/* RT-Thread Utestcases */
-#define RT_USING_UTESTCASES
-
-/* Utest Self Testcase */
-
-#define UTEST_SELF_PASS_TC
-
-/* Kernel Testcase */
-
-#define UTEST_SMALL_MEM_TC
-
-/* Utest Serial Testcase */
-
/* RT-Thread online packages */
@@ -206,9 +158,6 @@
/* enhanced kernel services */
-/* POSIX extension functions */
-
-
/* acceleration: Assembly language or algorithmic acceleration packages */
@@ -232,55 +181,20 @@
/* entertainment: terminal games and other interesting software packages */
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_DEMO
-
/* Hardware Drivers Config */
+#define SOC_SERIES_GD32F10x
+#define SOC_GD32103V
+
+/* Onboard Peripheral Drivers */
+
/* On-chip Peripheral Drivers */
-#define SOC_SERIES_M032
-#define BSP_USE_STDDRIVER_SOURCE
-#define BSP_USING_PDMA
-#define NU_PDMA_MEMFUN_ACTOR_MAX 4
-#define NU_PDMA_SGTBL_POOL_SIZE 16
#define BSP_USING_GPIO
-#define BSP_USING_CLK
-#define NU_CLK_INVOKE_WKTMR
-#define BSP_USING_RTC
-#define NU_RTC_SUPPORT_IO_RW
-#define NU_RTC_SUPPORT_MSH_CMD
-#define BSP_USING_ADC
-#define BSP_USING_ADC0
-#define BSP_USING_TMR
-#define BSP_USING_TIMER
-#define BSP_USING_TMR0
-#define BSP_USING_TIMER0
-#define BSP_USING_TMR1
-#define BSP_USING_TIMER1
-#define BSP_USING_TMR2
-#define BSP_USING_TIMER2
#define BSP_USING_UART
-#define BSP_USING_UART0
#define BSP_USING_UART1
-#define BSP_USING_UART1_TX_DMA
-#define BSP_USING_UART1_RX_DMA
-#define BSP_USING_UART2
-#define BSP_USING_UART3
-#define BSP_USING_UART4
-#define BSP_USING_UART5
-#define BSP_USING_UART6
-#define BSP_USING_UART7
-#define BSP_USING_WDT
-#define BSP_USING_USBD
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_NULINKME
-
-/* Board extended module drivers */
+/* Board extended module Drivers */
#endif
diff --git a/bsp/gd32103c-eval/rtconfig.py b/bsp/gd32/gd32103c-eval/rtconfig.py
similarity index 54%
rename from bsp/gd32103c-eval/rtconfig.py
rename to bsp/gd32/gd32103c-eval/rtconfig.py
index 7e8934c873..4285e6b03c 100644
--- a/bsp/gd32103c-eval/rtconfig.py
+++ b/bsp/gd32/gd32103c-eval/rtconfig.py
@@ -3,22 +3,27 @@ import os
# toolchains options
ARCH='arm'
CPU='cortex-m3'
-CROSS_TOOL='gcc'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
- EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
- PLATFORM = 'armcc'
- EXEC_PATH = r'C:/Keil_v5'
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
- PLATFORM = 'iar'
- EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -26,21 +31,22 @@ if os.getenv('RTT_EXEC_PATH'):
BUILD = 'debug'
if PLATFORM == 'gcc':
- # tool-chains
+ # toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
-
+
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
- CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE
+ CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
- LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld'
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
CPATH = ''
LPATH = ''
@@ -51,27 +57,30 @@ if PLATFORM == 'gcc':
else:
CFLAGS += ' -O2'
+ CXXFLAGS = CFLAGS
+
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
+ CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
- DEVICE = ' --cpu Cortex-M4'
- CFLAGS = DEVICE + ' --apcs=interwork'
- AFLAGS = DEVICE
- LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct'
+ DEVICE = ' --cpu Cortex-M3.fp '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
- LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
-
- EXEC_PATH += '/ARM/ARMCC/bin'
- print(EXEC_PATH)
-
- CFLAGS += ' --c99'
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
@@ -79,17 +88,21 @@ elif PLATFORM == 'armcc':
else:
CFLAGS += ' -O2'
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
+ CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
- DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD'
+ DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
@@ -100,27 +113,38 @@ elif PLATFORM == 'iar':
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
- CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
- CFLAGS += ' --cpu=Cortex-M4'
+ CFLAGS += ' --cpu=Cortex-M3'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
- CFLAGS += ' -Ol'
- CFLAGS += ' --use_c++_inline'
+ CFLAGS += ' --silent'
- AFLAGS = ''
+ AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
- AFLAGS += ' --cpu Cortex-M4'
+ AFLAGS += ' --cpu Cortex-M3'
AFLAGS += ' --fpu None'
+ AFLAGS += ' -S'
- LFLAGS = ' --config gd32_rom.icf'
- LFLAGS += ' --redirect _Printf=_PrintfTiny'
- LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
- EXEC_PATH += '/arm/bin/'
- POST_ACTION = ''
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/gd32/gd32103c-eval/template.uvoptx b/bsp/gd32/gd32103c-eval/template.uvoptx
new file mode 100644
index 0000000000..e99a756fe7
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/template.uvoptx
@@ -0,0 +1,180 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
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+
+
+ 1
+ 65535
+ 0
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+
+
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+ .\build\
+
+
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+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F105RC$Flash\GD32F10x_CL.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
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+ 0
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+ 0
+ 0
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+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32103c-eval/template.uvproj b/bsp/gd32/gd32103c-eval/template.uvproj
new file mode 100644
index 0000000000..33458e05f7
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/template.uvproj
@@ -0,0 +1,628 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F103VC
+ GigaDevice
+ IRAM(0x20000000-0x20018000) IROM(0x08000000-0x08040000) CLOCK(10800000) CPUTYPE("Cortex-M3")
+
+ "Startup\GD\GD32F10x\startup_gd32f10x.s" ("GD32F10x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F10x_3MB -FS08000000 -FL0100000)
+ 0
+ gd32f10x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F10x\GD32F10x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F10x\
+ GD\GD32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
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+ 0
+
+ 0
+ 0
+
+
+ 0
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+
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+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
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+
+
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+
+ 0
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
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+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+ "Cortex-M3"
+
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+ 0
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+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Include;..\..\..\Library\Utilities;..\
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
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+
+
+
+
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+
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+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Application
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+ gd32f10x_it.c
+ 1
+ ..\gd32f10x_it.c
+
+
+
+
+ CMSIS
+
+
+ system_gd32f10x.c
+ 1
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+
+
+ GD32F10x_Peripherals
+
+
+ gd32f10x_adc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c
+
+
+ gd32f10x_can.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_can.c
+
+
+ gd32f10x_crc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c
+
+
+ gd32f10x_ctc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_ctc.c
+
+
+ gd32f10x_dac.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c
+
+
+ gd32f10x_dbg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c
+
+
+ gd32f10x_dci.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dci.c
+
+
+ gd32f10x_dma.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c
+
+
+ gd32f10x_enet.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c
+
+
+ gd32f10x_exmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c
+
+
+ gd32f10x_exti.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+ gd32f10x_fmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c
+
+
+ gd32f10x_fwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+ gd32f10x_i2c.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c
+
+
+ gd32f10x_ipa.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_ipa.c
+
+
+ gd32f10x_iref.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_iref.c
+
+
+ gd32f10x_misc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+ gd32f10x_pmu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+ gd32f10x_rtc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c
+
+
+ gd32f10x_sdio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c
+
+
+ gd32f10x_spi.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c
+
+
+ gd32f10x_syscfg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_syscfg.c
+
+
+ gd32f10x_timer.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c
+
+
+ gd32f10x_tli.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_tli.c
+
+
+ gd32f10x_trng.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_trng.c
+
+
+ gd32f10x_usart.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+ gd32f10x_wwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c
+
+
+
+
+ GD32F10x_EVAL
+
+
+ gd32f103c_eval.c
+ 1
+ ..\..\..\Library\Utilities\gd32f103c_eval.c
+
+
+
+
+ Startup
+
+
+ startup_gd32f10x.s
+ 2
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x.s
+
+
+
+
+ Doc
+
+
+ readme.txt
+ 5
+ ..\readme.txt
+
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32103c-eval/template.uvprojx b/bsp/gd32/gd32103c-eval/template.uvprojx
new file mode 100644
index 0000000000..efc072e87e
--- /dev/null
+++ b/bsp/gd32/gd32103c-eval/template.uvprojx
@@ -0,0 +1,418 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F103VC
+ GigaDevice
+ GigaDevice.GD32F10x_DFP.2.0.1
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x0000C000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(10800000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F103VC$Flash\GD32F10x_CL.FLM))
+ 0
+ $$Device:GD32F103VC$Device\Include\gd32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F103VC$SVD\GD32F10x\GD32F10x_CL.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rtthread
+ 1
+ 0
+ 0
+ 1
+ 0
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 0
+ fromelf --bin !L --output rtthread.bin
+
+ 0
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+
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+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
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+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
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+ 0
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+ 1
+ 1
+ 1
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+ "Cortex-M3"
+
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+
+
+
+
+
+
+
+ 1
+ 0
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+ 0
+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32/gd32105c-eval/.config b/bsp/gd32/gd32105c-eval/.config
new file mode 100644
index 0000000000..84090ac74e
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/.config
@@ -0,0 +1,636 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_BIG_ENDIAN is not set
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_RT_USING_ARDUINO is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_USB_STACK is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_SERIES_GD32F10x=y
+CONFIG_SOC_GD32105V=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/gd32/gd32105c-eval/Kconfig b/bsp/gd32/gd32105c-eval/Kconfig
new file mode 100644
index 0000000000..8cbc7b71a8
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/gd32/gd32105c-eval/README.md b/bsp/gd32/gd32105c-eval/README.md
new file mode 100644
index 0000000000..623501ef26
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/README.md
@@ -0,0 +1,98 @@
+# GD32105C-EVAL开发板BSP说明
+
+## 简介
+
+GD3105C-EVAL是-兆易创新推出的一款GD32F10X系列的评估板，最高主频高达108M，该开发板具有丰富的板载资源，可以充分发挥 GD32105VCT6 的芯片性能。
+
+开发板外观如下图所示：
+
+
+
+该开发板常用 **板载资源** 如下：
+
+- GD32105VCT6，主频 108MHz，256KB FLASH ，96KB RAM
+
+- 常用外设
+
+ - LED ：5个，LED1 (电源指示灯），LED2（PC0），LED3（PC2），LED4（PE0），LED5（PE1）
+ - 按键：3个，K1（用户按键，PA0），K2（用户按键，PC13），K3（用户按键，PB14）
+
+- 常用接口：USB 接口
+
+- 调试接口：GD-LINK
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+|:--------- |:--------:|:------------------------------------- |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART0 - UART7 |
+| I2C | 支持 | I2C1 |
+| SPI | 支持 | SPI0 - SPI2 |
+| SPI FLASH | 支持 | |
+| **扩展模块** | **支持情况** | **备注** |
+| 暂无 | 暂不支持 | 暂不支持 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.4 build Dec 19 2021 10:00:27
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [BruceOu](https://github.com/Ouxiaolong/), 邮箱：
\ No newline at end of file
diff --git a/bsp/gd32103c-eval/SConscript b/bsp/gd32/gd32105c-eval/SConscript
similarity index 85%
rename from bsp/gd32103c-eval/SConscript
rename to bsp/gd32/gd32105c-eval/SConscript
index fe0ae941ae..20f7689c53 100644
--- a/bsp/gd32103c-eval/SConscript
+++ b/bsp/gd32/gd32105c-eval/SConscript
@@ -1,8 +1,9 @@
# for module compiling
import os
Import('RTT_ROOT')
+from building import *
-cwd = str(Dir('#'))
+cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
diff --git a/bsp/gd32/gd32105c-eval/SConstruct b/bsp/gd32/gd32105c-eval/SConstruct
new file mode 100644
index 0000000000..49074397d0
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+gd32_library = 'GD32F10x_Firmware_Library'
+rtconfig.BSP_LIBRARY_TYPE = gd32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32/gd32105c-eval/applications/SConscript b/bsp/gd32/gd32105c-eval/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32/gd32105c-eval/applications/main.c b/bsp/gd32/gd32105c-eval/applications/main.c
new file mode 100644
index 0000000000..4a528128b4
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/applications/main.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-08-20 BruceOu first implementation
+ */
+
+#include
+#include
+#include
+#include
+
+/* defined the LED2 pin: PC6 */
+#define LED2_PIN GET_PIN(C, 6)
+
+int main(void)
+{
+ int count = 1;
+
+ /* set LED2 pin mode to output */
+ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED2_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED2_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/gd32/gd32105c-eval/board/Kconfig b/bsp/gd32/gd32105c-eval/board/Kconfig
new file mode 100644
index 0000000000..72f7f9634a
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/Kconfig
@@ -0,0 +1,85 @@
+menu "Hardware Drivers Config"
+
+config SOC_SERIES_GD32F10x
+ bool
+ default y
+
+config SOC_GD32105V
+ bool
+ select SOC_SERIES_GD32F10x
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default y
+
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ depends on BSP_USING_SPI1
+ default n
+
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ depends on BSP_USING_SPI1
+ select BSP_SPI1_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 216
+ default 24
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 216
+ default 25
+ endif
+ source "../libraries/gd32_drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/gd32/gd32105c-eval/board/SConscript b/bsp/gd32/gd32105c-eval/board/SConscript
new file mode 100644
index 0000000000..c1f4a6001b
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/SConscript
@@ -0,0 +1,28 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path = [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_cl.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s']
+
+CPPDEFINES = ['GD32F10X_CL']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/gd32/gd32105c-eval/board/board.c b/bsp/gd32/gd32105c-eval/board/board.c
new file mode 100644
index 0000000000..c409645b37
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/board.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#include
+#include
+#include
+#include
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @param None
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler */
+ /* User can add his own implementation to report the HAL error return state */
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+ NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+ /* NVIC Configuration */
+#define NVIC_VTOR_MASK 0x3FFFFF80
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x10000000 */
+ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
+#endif
+
+ SystemClock_Config();
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef BSP_USING_SDRAM
+ rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
+#else
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/gd32/gd32105c-eval/board/board.h b/bsp/gd32/gd32105c-eval/board/board.h
new file mode 100644
index 0000000000..11fb4fa084
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/board.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "gd32f10x.h"
+#include "drv_usart.h"
+#include "drv_gpio.h"
+
+#include "gd32f10x_exti.h"
+
+#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
+#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
+
+// Internal SRAM memory size[Kbytes] <8-96>
+// Default: 96
+#ifdef __ICCARM__
+// Use *.icf ram symbal, to avoid hardcode.
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE 96
+#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END GD32_SRAM_END
+
+#endif
+
diff --git a/bsp/gd32/gd32105c-eval/board/gd32f10x_libopt.h b/bsp/gd32/gd32105c-eval/board/gd32f10x_libopt.h
new file mode 100644
index 0000000000..5292c8eca7
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/gd32f10x_libopt.h
@@ -0,0 +1,64 @@
+/*!
+ \file gd32f10x_libopt.h
+ \brief library optional for gd32f10x
+
+ \version 2014-12-26, V1.0.0, demo for GD32F10x
+ \version 2017-06-30, V2.0.0, demo for GD32F10x
+ \version 2021-04-30, V2.1.0, demo for GD32F10x
+*/
+
+/*
+ Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_LIBOPT_H
+#define GD32F10X_LIBOPT_H
+
+#include "gd32f10x_fmc.h"
+#include "gd32f10x_pmu.h"
+#include "gd32f10x_bkp.h"
+#include "gd32f10x_rcu.h"
+#include "gd32f10x_exti.h"
+#include "gd32f10x_gpio.h"
+#include "gd32f10x_crc.h"
+#include "gd32f10x_dma.h"
+#include "gd32f10x_dbg.h"
+#include "gd32f10x_adc.h"
+#include "gd32f10x_dac.h"
+#include "gd32f10x_fwdgt.h"
+#include "gd32f10x_wwdgt.h"
+#include "gd32f10x_rtc.h"
+#include "gd32f10x_timer.h"
+#include "gd32f10x_usart.h"
+#include "gd32f10x_i2c.h"
+#include "gd32f10x_spi.h"
+#include "gd32f10x_sdio.h"
+#include "gd32f10x_exmc.h"
+#include "gd32f10x_can.h"
+#include "gd32f10x_enet.h"
+#include "gd32f10x_misc.h"
+
+#endif /* GD32F10X_LIBOPT_H */
diff --git a/bsp/gd32/gd32105c-eval/board/linker_scripts/link.icf b/bsp/gd32/gd32105c-eval/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..283881a728
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/linker_scripts/link.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__ = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
\ No newline at end of file
diff --git a/bsp/gd32/gd32105c-eval/board/linker_scripts/link.ld b/bsp/gd32/gd32105c-eval/board/linker_scripts/link.ld
new file mode 100644
index 0000000000..8ba4a0e9f2
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/linker_scripts/link.ld
@@ -0,0 +1,142 @@
+/*
+ * linker script for GD32F30x with GNU ld
+ * BruceOu 2021-12-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */
+ DATA (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } > CODE = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > CODE
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >DATA
+
+ .stack :
+ {
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >DATA
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > DATA
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/gd32/gd32105c-eval/board/linker_scripts/link.sct b/bsp/gd32/gd32105c-eval/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..0529ba2b9c
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00018000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/gd32/gd32105c-eval/figures/board.jpg b/bsp/gd32/gd32105c-eval/figures/board.jpg
new file mode 100644
index 0000000000..3cec090a59
Binary files /dev/null and b/bsp/gd32/gd32105c-eval/figures/board.jpg differ
diff --git a/bsp/gd32/gd32105c-eval/project.uvoptx b/bsp/gd32/gd32105c-eval/project.uvoptx
new file mode 100644
index 0000000000..d691bf54c0
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/project.uvoptx
@@ -0,0 +1,180 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32105c-eval/project.uvproj b/bsp/gd32/gd32105c-eval/project.uvproj
new file mode 100644
index 0000000000..e93bac770b
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/project.uvproj
@@ -0,0 +1,737 @@
+
+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F105VC
+ GigaDevice
+ IRAM(0x20000000-0x20018000) IROM(0x08000000-0x08040000) CLOCK(10800000) CPUTYPE("Cortex-M3")
+
+ "Startup\GD\GD32F10x\startup_gd32f10x.s" ("GD32F10x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F10x_3MB -FS08000000 -FL0100000)
+ 0
+ gd32f10x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F10x\GD32F10x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F10x\
+ GD\GD32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 1
+
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 2
+ 1
+ 0
+ 8
+ 1
+ 0
+ 0
+ 0
+ 3
+ 3
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x10000
+
+
+ 1
+ 0x8000000
+ 0x100000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x100000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x10000
+
+
+ 0
+ 0x10000000
+ 0x10000
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+ GD32F10X_CL, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\libraries\GD32F10x_Firmware_Library\CMSIS;..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ CPU
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+
+
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ board\board.c
+
+
+
+
+ startup_gd32f10x_cl.s
+ 2
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s
+
+
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\gd32_drivers\drv_gpio.c
+
+
+
+
+ drv_usart.c
+ 1
+ ..\libraries\gd32_drivers\drv_usart.c
+
+
+
+
+ Finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+
+
+ msh.c
+ 1
+ ..\..\..\components\finsh\msh.c
+
+
+
+
+ cmd.c
+ 1
+ ..\..\..\components\finsh\cmd.c
+
+
+
+
+ Kernel
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+
+
+ libc
+
+
+ time.c
+ 1
+ ..\..\..\components\libc\compilers\common\time.c
+
+
+
+
+ Libraries
+
+
+ gd32f10x_exti.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+
+
+ gd32f10x_misc.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+
+
+ system_gd32f10x.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+
+
+ gd32f10x_usart.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32105c-eval/project.uvprojx b/bsp/gd32/gd32105c-eval/project.uvprojx
new file mode 100644
index 0000000000..2600998e70
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/project.uvprojx
@@ -0,0 +1,727 @@
+
+
+ 2.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F105VC
+ GigaDevice
+ GigaDevice.GD32F10x_DFP.2.0.1
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(10800000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM))
+ 0
+ $$Device:GD32F105VC$Device\Include\gd32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F105VC$SVD\GD32F10x\GD32F10x_CL.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rtthread
+ 1
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+ 0
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+ .\build\
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+ 0
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+
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+
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+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
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+
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+ 0
+ 0x20000000
+ 0x18000
+
+
+ 1
+ 0x8000000
+ 0x40000
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+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+ GD32F10X_CL, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\libraries\GD32F10x_Firmware_Library\CMSIS;..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
+
+
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+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ CPU
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ board\board.c
+
+
+
+
+ startup_gd32f10x_cl.s
+ 2
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s
+
+
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\gd32_drivers\drv_gpio.c
+
+
+
+
+ drv_usart.c
+ 1
+ ..\libraries\gd32_drivers\drv_usart.c
+
+
+
+
+ Finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+
+
+ msh.c
+ 1
+ ..\..\..\components\finsh\msh.c
+
+
+
+
+ cmd.c
+ 1
+ ..\..\..\components\finsh\cmd.c
+
+
+
+
+ Kernel
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+ libc
+
+
+ time.c
+ 1
+ ..\..\..\components\libc\compilers\common\time.c
+
+
+
+
+ Libraries
+
+
+ gd32f10x_exti.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+
+
+ gd32f10x_misc.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+
+
+ system_gd32f10x.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+
+
+ gd32f10x_usart.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
diff --git a/bsp/gd32/gd32105c-eval/rtconfig.h b/bsp/gd32/gd32105c-eval/rtconfig.h
new file mode 100644
index 0000000000..67fb740e3b
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/rtconfig.h
@@ -0,0 +1,200 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_LIBC_USING_TIME
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_SERIES_GD32F10x
+#define SOC_GD32105V
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/gd32/gd32105c-eval/rtconfig.py b/bsp/gd32/gd32105c-eval/rtconfig.py
new file mode 100644
index 0000000000..4285e6b03c
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/rtconfig.py
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M3.fp '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M3'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M3'
+ AFLAGS += ' --fpu None'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/gd32/gd32105c-eval/template.uvoptx b/bsp/gd32/gd32105c-eval/template.uvoptx
new file mode 100644
index 0000000000..d691bf54c0
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/template.uvoptx
@@ -0,0 +1,180 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM)
+
+
+
+
+ 0
+
+
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+
+
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+
+
+
+
+
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+
+
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32105c-eval/template.uvproj b/bsp/gd32/gd32105c-eval/template.uvproj
new file mode 100644
index 0000000000..8ad9e1c662
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/template.uvproj
@@ -0,0 +1,628 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F105VC
+ GigaDevice
+ IRAM(0x20000000-0x20018000) IROM(0x08000000-0x08040000) CLOCK(10800000) CPUTYPE("Cortex-M3")
+
+ "Startup\GD\GD32F10x\startup_gd32f10x.s" ("GD32F10x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F10x_3MB -FS08000000 -FL0100000)
+ 0
+ gd32f10x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F10x\GD32F10x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F10x\
+ GD\GD32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
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+
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+
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+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
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+
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+
+ 0
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
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+
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+ 1
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+ "Cortex-M3"
+
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+ 0x10000
+
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+ 0
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+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Include;..\..\..\Library\Utilities;..\
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
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+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Application
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+ gd32f10x_it.c
+ 1
+ ..\gd32f10x_it.c
+
+
+
+
+ CMSIS
+
+
+ system_gd32f10x.c
+ 1
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+
+
+ GD32F10x_Peripherals
+
+
+ gd32f10x_adc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c
+
+
+ gd32f10x_can.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_can.c
+
+
+ gd32f10x_crc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c
+
+
+ gd32f10x_ctc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_ctc.c
+
+
+ gd32f10x_dac.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c
+
+
+ gd32f10x_dbg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c
+
+
+ gd32f10x_dci.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dci.c
+
+
+ gd32f10x_dma.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c
+
+
+ gd32f10x_enet.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c
+
+
+ gd32f10x_exmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c
+
+
+ gd32f10x_exti.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+ gd32f10x_fmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c
+
+
+ gd32f10x_fwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+ gd32f10x_i2c.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c
+
+
+ gd32f10x_ipa.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_ipa.c
+
+
+ gd32f10x_iref.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_iref.c
+
+
+ gd32f10x_misc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+ gd32f10x_pmu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+ gd32f10x_rtc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c
+
+
+ gd32f10x_sdio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c
+
+
+ gd32f10x_spi.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c
+
+
+ gd32f10x_syscfg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_syscfg.c
+
+
+ gd32f10x_timer.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c
+
+
+ gd32f10x_tli.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_tli.c
+
+
+ gd32f10x_trng.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_trng.c
+
+
+ gd32f10x_usart.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+ gd32f10x_wwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c
+
+
+
+
+ GD32F10x_EVAL
+
+
+ gd32f105c_eval.c
+ 1
+ ..\..\..\Library\Utilities\gd32f105c_eval.c
+
+
+
+
+ Startup
+
+
+ startup_gd32f10x.s
+ 2
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x.s
+
+
+
+
+ Doc
+
+
+ readme.txt
+ 5
+ ..\readme.txt
+
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32105c-eval/template.uvprojx b/bsp/gd32/gd32105c-eval/template.uvprojx
new file mode 100644
index 0000000000..2b0da81501
--- /dev/null
+++ b/bsp/gd32/gd32105c-eval/template.uvprojx
@@ -0,0 +1,418 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F105VC
+ GigaDevice
+ GigaDevice.GD32F10x_DFP.2.0.1
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(10800000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM))
+ 0
+ $$Device:GD32F105VC$Device\Include\gd32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F105VC$SVD\GD32F10x\GD32F10x_CL.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rtthread
+ 1
+ 0
+ 0
+ 1
+ 0
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 0
+ fromelf --bin !L --output rtthread.bin
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
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+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
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+ 0
+ 0
+ 0
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+ 0
+ 0
+ 8
+ 0
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+ 0x18000
+
+
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+
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+
+
+
+
+
+
+ 1
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+ 0
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+ 4
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32103c-eval/.config b/bsp/gd32/gd32107c-eval/.config
similarity index 93%
rename from bsp/gd32103c-eval/.config
rename to bsp/gd32/gd32107c-eval/.config
index de1ea1ac0c..595bf9bc01 100644
--- a/bsp/gd32103c-eval/.config
+++ b/bsp/gd32/gd32107c-eval/.config
@@ -18,13 +18,10 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
-CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
-CONFIG_RT_USING_TIMER_SOFT=y
-CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
@@ -34,7 +31,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_DEBUG=y
-# CONFIG_RT_DEBUG_COLOR is not set
+CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
@@ -80,7 +77,7 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40100
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -121,23 +118,15 @@ CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_POSIX=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
@@ -157,7 +146,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@@ -177,7 +171,8 @@ CONFIG_RT_USING_PIN=y
#
# POSIX layer and C standard library
#
-# CONFIG_RT_USING_MODULE is not set
+# CONFIG_RT_USING_LIBC is not set
+CONFIG_RT_LIBC_USING_TIME=y
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
@@ -186,6 +181,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_PTHREADS is not set
#
@@ -302,7 +298,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@@ -351,7 +346,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# language packages
#
-# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
@@ -442,6 +436,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# system packages
#
+# CONFIG_PKG_USING_LUATOS_SOC is not set
#
# enhanced kernel services
@@ -450,13 +445,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
-#
-# POSIX extension functions
-#
-# CONFIG_PKG_USING_POSIX_GETLINE is not set
-# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
-# CONFIG_PKG_USING_POSIX_ITOA is not set
-
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@@ -508,6 +496,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_USB_STACK is not set
@@ -584,11 +573,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
-# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
-# CONFIG_PKG_USING_CW2015 is not set
#
# AI packages
@@ -654,19 +641,30 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
-CONFIG_SOC_SERIES_GD32F1=y
-CONFIG_SOC_GD32103C=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_SERIES_GD32F10x=y
+CONFIG_SOC_GD32107V=y
+
+#
+# Onboard Peripheral Drivers
+#
#
# On-chip Peripheral Drivers
#
+CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
-CONFIG_BSP_USING_UART0=y
-# CONFIG_BSP_USING_UART1 is not set
-# CONFIG_BSP_USING_UART2 is not set
-# CONFIG_BSP_USING_UART3 is not set
-# CONFIG_BSP_USING_UART4 is not set
-# CONFIG_BSP_USING_ADC is not set
-# CONFIG_BSP_USING_HWTIMER is not set
-# CONFIG_BSP_USING_WDT is not set
-# CONFIG_BSP_USING_RTC is not set
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+CONFIG_BSP_USING_SPI=y
+CONFIG_BSP_USING_SPI1=y
+# CONFIG_BSP_SPI1_TX_USING_DMA is not set
+# CONFIG_BSP_SPI1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/gd32/gd32107c-eval/Kconfig b/bsp/gd32/gd32107c-eval/Kconfig
new file mode 100644
index 0000000000..8cbc7b71a8
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/gd32/gd32107c-eval/README.md b/bsp/gd32/gd32107c-eval/README.md
new file mode 100644
index 0000000000..a5dd4a3132
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/README.md
@@ -0,0 +1,98 @@
+# GD32107C-EVAL开发板BSP说明
+
+## 简介
+
+GD3107C-EVAL是-兆易创新推出的一款GD32F10X系列的评估板，最高主频高达108M，该开发板具有丰富的板载资源，可以充分发挥 GD32107VCT6 的芯片性能。
+
+开发板外观如下图所示：
+
+
+
+该开发板常用 **板载资源** 如下：
+
+- GD32107VCT6，主频 108MHz，256KB FLASH ，96KB RAM
+
+- 常用外设
+
+ - LED ：5个，LED1 (电源指示灯），LED2（PC0），LED3（PC2），LED4（PE0），LED5（PE1）
+ - 按键：3个，K1（用户按键，PA0），K2（用户按键，PC13），K3（用户按键，PB14）
+
+- 常用接口：USB 接口
+
+- 调试接口：GD-LINK
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+|:--------- |:--------:|:------------------------------------- |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART0 - UART7 |
+| I2C | 支持 | I2C1 |
+| SPI | 支持 | SPI0 - SPI2 |
+| SPI FLASH | 支持 | |
+| **扩展模块** | **支持情况** | **备注** |
+| 暂无 | 暂不支持 | 暂不支持 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.4 build Dec 19 2021 10:00:27
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [BruceOu](https://github.com/Ouxiaolong/), 邮箱：
\ No newline at end of file
diff --git a/bsp/gd32/gd32107c-eval/SConscript b/bsp/gd32/gd32107c-eval/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/gd32/gd32107c-eval/SConstruct b/bsp/gd32/gd32107c-eval/SConstruct
new file mode 100644
index 0000000000..49074397d0
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+gd32_library = 'GD32F10x_Firmware_Library'
+rtconfig.BSP_LIBRARY_TYPE = gd32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32/gd32107c-eval/applications/SConscript b/bsp/gd32/gd32107c-eval/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32/gd32107c-eval/applications/main.c b/bsp/gd32/gd32107c-eval/applications/main.c
new file mode 100644
index 0000000000..4a528128b4
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/applications/main.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-08-20 BruceOu first implementation
+ */
+
+#include
+#include
+#include
+#include
+
+/* defined the LED2 pin: PC6 */
+#define LED2_PIN GET_PIN(C, 6)
+
+int main(void)
+{
+ int count = 1;
+
+ /* set LED2 pin mode to output */
+ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED2_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED2_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/gd32/gd32107c-eval/board/Kconfig b/bsp/gd32/gd32107c-eval/board/Kconfig
new file mode 100644
index 0000000000..c20447d8e7
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/Kconfig
@@ -0,0 +1,85 @@
+menu "Hardware Drivers Config"
+
+config SOC_SERIES_GD32F10x
+ bool
+ default y
+
+config SOC_GD32107V
+ bool
+ select SOC_SERIES_GD32F10x
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default y
+
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ depends on BSP_USING_SPI1
+ default n
+
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ depends on BSP_USING_SPI1
+ select BSP_SPI1_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 216
+ default 24
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 216
+ default 25
+ endif
+ source "../libraries/gd32_drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/gd32/gd32107c-eval/board/SConscript b/bsp/gd32/gd32107c-eval/board/SConscript
new file mode 100644
index 0000000000..c1f4a6001b
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/SConscript
@@ -0,0 +1,28 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path = [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_cl.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/GD32F10x_Firmware_Library/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s']
+
+CPPDEFINES = ['GD32F10X_CL']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/gd32/gd32107c-eval/board/board.c b/bsp/gd32/gd32107c-eval/board/board.c
new file mode 100644
index 0000000000..c409645b37
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/board.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#include
+#include
+#include
+#include
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @param None
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler */
+ /* User can add his own implementation to report the HAL error return state */
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+ NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+ /* NVIC Configuration */
+#define NVIC_VTOR_MASK 0x3FFFFF80
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x10000000 */
+ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
+#endif
+
+ SystemClock_Config();
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef BSP_USING_SDRAM
+ rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
+#else
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/gd32/gd32107c-eval/board/board.h b/bsp/gd32/gd32107c-eval/board/board.h
new file mode 100644
index 0000000000..11fb4fa084
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/board.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "gd32f10x.h"
+#include "drv_usart.h"
+#include "drv_gpio.h"
+
+#include "gd32f10x_exti.h"
+
+#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
+#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
+
+// Internal SRAM memory size[Kbytes] <8-96>
+// Default: 96
+#ifdef __ICCARM__
+// Use *.icf ram symbal, to avoid hardcode.
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE 96
+#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END GD32_SRAM_END
+
+#endif
+
diff --git a/bsp/gd32/gd32107c-eval/board/gd32f10x_libopt.h b/bsp/gd32/gd32107c-eval/board/gd32f10x_libopt.h
new file mode 100644
index 0000000000..5292c8eca7
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/gd32f10x_libopt.h
@@ -0,0 +1,64 @@
+/*!
+ \file gd32f10x_libopt.h
+ \brief library optional for gd32f10x
+
+ \version 2014-12-26, V1.0.0, demo for GD32F10x
+ \version 2017-06-30, V2.0.0, demo for GD32F10x
+ \version 2021-04-30, V2.1.0, demo for GD32F10x
+*/
+
+/*
+ Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_LIBOPT_H
+#define GD32F10X_LIBOPT_H
+
+#include "gd32f10x_fmc.h"
+#include "gd32f10x_pmu.h"
+#include "gd32f10x_bkp.h"
+#include "gd32f10x_rcu.h"
+#include "gd32f10x_exti.h"
+#include "gd32f10x_gpio.h"
+#include "gd32f10x_crc.h"
+#include "gd32f10x_dma.h"
+#include "gd32f10x_dbg.h"
+#include "gd32f10x_adc.h"
+#include "gd32f10x_dac.h"
+#include "gd32f10x_fwdgt.h"
+#include "gd32f10x_wwdgt.h"
+#include "gd32f10x_rtc.h"
+#include "gd32f10x_timer.h"
+#include "gd32f10x_usart.h"
+#include "gd32f10x_i2c.h"
+#include "gd32f10x_spi.h"
+#include "gd32f10x_sdio.h"
+#include "gd32f10x_exmc.h"
+#include "gd32f10x_can.h"
+#include "gd32f10x_enet.h"
+#include "gd32f10x_misc.h"
+
+#endif /* GD32F10X_LIBOPT_H */
diff --git a/bsp/gd32/gd32107c-eval/board/linker_scripts/link.icf b/bsp/gd32/gd32107c-eval/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..283881a728
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/linker_scripts/link.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__ = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
\ No newline at end of file
diff --git a/bsp/gd32/gd32107c-eval/board/linker_scripts/link.ld b/bsp/gd32/gd32107c-eval/board/linker_scripts/link.ld
new file mode 100644
index 0000000000..8ba4a0e9f2
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/linker_scripts/link.ld
@@ -0,0 +1,142 @@
+/*
+ * linker script for GD32F30x with GNU ld
+ * BruceOu 2021-12-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */
+ DATA (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } > CODE = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > CODE
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >DATA
+
+ .stack :
+ {
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >DATA
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > DATA
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/gd32/gd32107c-eval/board/linker_scripts/link.sct b/bsp/gd32/gd32107c-eval/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..0529ba2b9c
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00018000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/gd32/gd32107c-eval/figures/board.jpg b/bsp/gd32/gd32107c-eval/figures/board.jpg
new file mode 100644
index 0000000000..7eec2d53d5
Binary files /dev/null and b/bsp/gd32/gd32107c-eval/figures/board.jpg differ
diff --git a/bsp/gd32/gd32107c-eval/project.uvoptx b/bsp/gd32/gd32107c-eval/project.uvoptx
new file mode 100644
index 0000000000..a78b865bc5
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/project.uvoptx
@@ -0,0 +1,796 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
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+
+
+
+
+
+
+
+
+
+
+
+ Applications
+ 0
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ applications\main.c
+ main.c
+ 0
+ 0
+
+
+
+
+ CPU
+ 0
+ 0
+ 0
+ 0
+
+ 2
+ 2
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\common\backtrace.c
+ backtrace.c
+ 0
+ 0
+
+
+ 2
+ 3
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\common\showmem.c
+ showmem.c
+ 0
+ 0
+
+
+ 2
+ 4
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\common\div0.c
+ div0.c
+ 0
+ 0
+
+
+ 2
+ 5
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+ cpuport.c
+ 0
+ 0
+
+
+ 2
+ 6
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+ context_rvds.S
+ 0
+ 0
+
+
+
+
+ DeviceDrivers
+ 0
+ 0
+ 0
+ 0
+
+ 3
+ 7
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\misc\pin.c
+ pin.c
+ 0
+ 0
+
+
+ 3
+ 8
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\serial\serial.c
+ serial.c
+ 0
+ 0
+
+
+ 3
+ 9
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\spi\spi_core.c
+ spi_core.c
+ 0
+ 0
+
+
+ 3
+ 10
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\spi\spi_dev.c
+ spi_dev.c
+ 0
+ 0
+
+
+ 3
+ 11
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\src\waitqueue.c
+ waitqueue.c
+ 0
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+
+
+ 3
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+ 1
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+ 0
+ ..\..\..\components\drivers\src\pipe.c
+ pipe.c
+ 0
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+
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+ ..\..\..\components\drivers\src\workqueue.c
+ workqueue.c
+ 0
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+
+
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+ 1
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+ ..\..\..\components\drivers\src\dataqueue.c
+ dataqueue.c
+ 0
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+
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+ completion.c
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+
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+ ..\..\..\components\drivers\src\ringbuffer.c
+ ringbuffer.c
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+
+
+ 3
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+ 1
+ 0
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+ 0
+ ..\..\..\components\drivers\src\ringblk_buf.c
+ ringblk_buf.c
+ 0
+ 0
+
+
+
+
+ Drivers
+ 0
+ 0
+ 0
+ 0
+
+ 4
+ 18
+ 1
+ 0
+ 0
+ 0
+ board\board.c
+ board.c
+ 0
+ 0
+
+
+ 4
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+ 2
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s
+ startup_gd32f10x_cl.s
+ 0
+ 0
+
+
+ 4
+ 20
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\gd32_drivers\drv_gpio.c
+ drv_gpio.c
+ 0
+ 0
+
+
+ 4
+ 21
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\gd32_drivers\drv_usart.c
+ drv_usart.c
+ 0
+ 0
+
+
+ 4
+ 22
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\gd32_drivers\drv_spi.c
+ drv_spi.c
+ 0
+ 0
+
+
+
+
+ Finsh
+ 0
+ 0
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+
+ 5
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+ ..\..\..\components\finsh\shell.c
+ shell.c
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+ msh.c
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+ ..\..\..\components\finsh\cmd.c
+ cmd.c
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+
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+
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+ mempool.c
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+ device.c
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+ scheduler.c
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+
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+ clock.c
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+
+
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+ ..\..\..\src\idle.c
+ idle.c
+ 0
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+
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+ timer.c
+ 0
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+
+
+ 6
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+ 1
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+ 0
+ ..\..\..\src\object.c
+ object.c
+ 0
+ 0
+
+
+
+
+ libc
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+ 0
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+ 0
+
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+ 39
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\libc\compilers\common\time.c
+ time.c
+ 0
+ 0
+
+
+
+
+ Libraries
+ 0
+ 0
+ 0
+ 0
+
+ 8
+ 40
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c
+ gd32f10x_spi.c
+ 0
+ 0
+
+
+ 8
+ 41
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+ gd32f10x_exti.c
+ 0
+ 0
+
+
+ 8
+ 42
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+ gd32f10x_gpio.c
+ 0
+ 0
+
+
+ 8
+ 43
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+ gd32f10x_misc.c
+ 0
+ 0
+
+
+ 8
+ 44
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+ system_gd32f10x.c
+ 0
+ 0
+
+
+ 8
+ 45
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+ gd32f10x_rcu.c
+ 0
+ 0
+
+
+ 8
+ 46
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+ gd32f10x_usart.c
+ 0
+ 0
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32107c-eval/project.uvproj b/bsp/gd32/gd32107c-eval/project.uvproj
new file mode 100644
index 0000000000..695885d4ba
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/project.uvproj
@@ -0,0 +1,777 @@
+
+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F107VC
+ GigaDevice
+ IRAM(0x20000000-0x20018000) IROM(0x08000000-0x08040000) CLOCK(12000000) CPUTYPE("Cortex-M3")
+
+ "Startup\GD\GD32F10x\startup_gd32f10x.s" ("GD32F10x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F10x_3MB -FS08000000 -FL0100000)
+ 0
+ gd32f10x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F10x\GD32F10x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F10x\
+ GD\GD32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
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+ GD32F10X_CL, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\libraries\GD32F10x_Firmware_Library\CMSIS;..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
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+
+
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+
+
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+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32107c-eval/project.uvprojx b/bsp/gd32/gd32107c-eval/project.uvprojx
new file mode 100644
index 0000000000..3d5ae39245
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/project.uvprojx
@@ -0,0 +1,757 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F107VC
+ GigaDevice
+ GigaDevice.GD32F10x_DFP.2.0.1
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(10800000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))
+ 0
+ $$Device:GD32F107VC$Device\Include\gd32f10x.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F107VC$SVD\GD32F10x\GD32F10x_CL.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
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+ 0
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+
+ .\build\
+ rtthread
+ 1
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+ .\build\
+ 1
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+ 0
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+
+ 0
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+
+
+ 0
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+
+ 1
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+ fromelf --bin !L --output rtthread.bin
+
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+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
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+
+
+
+
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+
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+
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+ 0
+ 0
+ 0
+
+
+ GD32F10X_CL, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\libraries\GD32F10x_Firmware_Library\CMSIS;..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
+
+
+
+ 1
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+
+
+
+
+
+
+
+
+ 1
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+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ CPU
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+
+
+
+
+ DeviceDrivers
+
+
+ 0
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+
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+
+
+
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+ spi_core.c
+ 1
+ ..\..\..\components\drivers\spi\spi_core.c
+
+
+ spi_dev.c
+ 1
+ ..\..\..\components\drivers\spi\spi_dev.c
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ board\board.c
+
+
+ startup_gd32f10x_cl.s
+ 2
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\gd32_drivers\drv_gpio.c
+
+
+ drv_usart.c
+ 1
+ ..\libraries\gd32_drivers\drv_usart.c
+
+
+ drv_spi.c
+ 1
+ ..\libraries\gd32_drivers\drv_spi.c
+
+
+
+
+ Finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+ msh.c
+ 1
+ ..\..\..\components\finsh\msh.c
+
+
+ cmd.c
+ 1
+ ..\..\..\components\finsh\cmd.c
+
+
+
+
+ Kernel
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+
+
+ libc
+
+
+ time.c
+ 1
+ ..\..\..\components\libc\compilers\common\time.c
+
+
+
+
+ Libraries
+
+
+ gd32f10x_spi.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c
+
+
+ gd32f10x_exti.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+ gd32f10x_misc.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+ system_gd32f10x.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+ gd32f10x_usart.c
+ 1
+ ..\libraries\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32103c-eval/rtconfig.h b/bsp/gd32/gd32107c-eval/rtconfig.h
similarity index 87%
rename from bsp/gd32103c-eval/rtconfig.h
rename to bsp/gd32/gd32107c-eval/rtconfig.h
index 8f2fc9739e..21caecd9ee 100644
--- a/bsp/gd32103c-eval/rtconfig.h
+++ b/bsp/gd32/gd32107c-eval/rtconfig.h
@@ -13,17 +13,14 @@
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_DEBUG
+#define RT_DEBUG_COLOR
/* Inter-Thread communication */
@@ -45,7 +42,7 @@
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40100
/* RT-Thread Components */
@@ -76,28 +73,26 @@
/* Device virtual file system */
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
+#define RT_USING_SPI
/* Using USB */
/* POSIX layer and C standard library */
+#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
@@ -169,12 +164,10 @@
/* system packages */
+
/* enhanced kernel services */
-/* POSIX extension functions */
-
-
/* acceleration: Assembly language or algorithmic acceleration packages */
@@ -197,12 +190,23 @@
/* entertainment: terminal games and other interesting software packages */
-#define SOC_SERIES_GD32F1
-#define SOC_GD32103C
+
+/* Hardware Drivers Config */
+
+#define SOC_SERIES_GD32F10x
+#define SOC_GD32107V
+
+/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
+#define BSP_USING_GPIO
#define BSP_USING_UART
-#define BSP_USING_UART0
+#define BSP_USING_UART1
+#define BSP_USING_SPI
+#define BSP_USING_SPI1
+
+/* Board extended module Drivers */
+
#endif
diff --git a/bsp/gd32/gd32107c-eval/rtconfig.py b/bsp/gd32/gd32107c-eval/rtconfig.py
new file mode 100644
index 0000000000..4285e6b03c
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/rtconfig.py
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M3.fp '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M3'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M3'
+ AFLAGS += ' --fpu None'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/gd32/gd32107c-eval/template.uvoptx b/bsp/gd32/gd32107c-eval/template.uvoptx
new file mode 100644
index 0000000000..4dfb02c5ad
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/template.uvoptx
@@ -0,0 +1,180 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM)
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32107c-eval/template.uvproj b/bsp/gd32/gd32107c-eval/template.uvproj
new file mode 100644
index 0000000000..a165464790
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/template.uvproj
@@ -0,0 +1,628 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F107VC
+ GigaDevice
+ IRAM(0x20000000-0x20018000) IROM(0x08000000-0x08040000) CLOCK(12000000) CPUTYPE("Cortex-M3")
+
+ "Startup\GD\GD32F10x\startup_gd32f10x.s" ("GD32F10x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F10x_3MB -FS08000000 -FL0100000)
+ 0
+ gd32f10x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F10x\GD32F10x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F10x\
+ GD\GD32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 1
+
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 2
+ 1
+ 0
+ 8
+ 1
+ 0
+ 0
+ 0
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+ 3
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+ 0
+ 0
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+ 0
+ 0
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+ 0
+ 1
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+ 0
+ 0
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+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
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+ 0x0
+
+
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+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x10000
+
+
+ 1
+ 0x8000000
+ 0x100000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x100000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x10000
+
+
+ 0
+ 0x10000000
+ 0x10000
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
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+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Include;..\..\..\Library\Utilities;..\
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Application
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+ gd32f10x_it.c
+ 1
+ ..\gd32f10x_it.c
+
+
+
+
+ CMSIS
+
+
+ system_gd32f10x.c
+ 1
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c
+
+
+
+
+ GD32F10x_Peripherals
+
+
+ gd32f10x_adc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c
+
+
+ gd32f10x_can.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_can.c
+
+
+ gd32f10x_crc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c
+
+
+ gd32f10x_ctc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_ctc.c
+
+
+ gd32f10x_dac.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c
+
+
+ gd32f10x_dbg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c
+
+
+ gd32f10x_dci.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dci.c
+
+
+ gd32f10x_dma.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c
+
+
+ gd32f10x_enet.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c
+
+
+ gd32f10x_exmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c
+
+
+ gd32f10x_exti.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c
+
+
+ gd32f10x_fmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c
+
+
+ gd32f10x_fwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c
+
+
+ gd32f10x_gpio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c
+
+
+ gd32f10x_i2c.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c
+
+
+ gd32f10x_ipa.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_ipa.c
+
+
+ gd32f10x_iref.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_iref.c
+
+
+ gd32f10x_misc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c
+
+
+ gd32f10x_pmu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c
+
+
+ gd32f10x_rcu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c
+
+
+ gd32f10x_rtc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c
+
+
+ gd32f10x_sdio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c
+
+
+ gd32f10x_spi.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c
+
+
+ gd32f10x_syscfg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_syscfg.c
+
+
+ gd32f10x_timer.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c
+
+
+ gd32f10x_tli.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_tli.c
+
+
+ gd32f10x_trng.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_trng.c
+
+
+ gd32f10x_usart.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c
+
+
+ gd32f10x_wwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c
+
+
+
+
+ GD32F10x_EVAL
+
+
+ gd32f107c_eval.c
+ 1
+ ..\..\..\Library\Utilities\gd32f107c_eval.c
+
+
+
+
+ Startup
+
+
+ startup_gd32f10x.s
+ 2
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x.s
+
+
+
+
+ Doc
+
+
+ readme.txt
+ 5
+ ..\readme.txt
+
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32107c-eval/template.uvprojx b/bsp/gd32/gd32107c-eval/template.uvprojx
new file mode 100644
index 0000000000..a80f13ffb9
--- /dev/null
+++ b/bsp/gd32/gd32107c-eval/template.uvprojx
@@ -0,0 +1,418 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F107VC
+ GigaDevice
+ GigaDevice.GD32F10x_DFP.2.0.1
+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(10800000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM))
+ 0
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diff --git a/bsp/gd32/gd32303e-eval/.config b/bsp/gd32/gd32303e-eval/.config
new file mode 100644
index 0000000000..c8f9feac51
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/.config
@@ -0,0 +1,636 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_BIG_ENDIAN is not set
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_RT_USING_ARDUINO is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_USB_STACK is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_SERIES_GD32F30x=y
+CONFIG_SOC_GD32305R=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/gd32/gd32303e-eval/Kconfig b/bsp/gd32/gd32303e-eval/Kconfig
new file mode 100644
index 0000000000..8cbc7b71a8
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/gd32/gd32303e-eval/README.md b/bsp/gd32/gd32303e-eval/README.md
new file mode 100644
index 0000000000..dd789e8394
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/README.md
@@ -0,0 +1,94 @@
+# GD32303E-EVAL开发板BSP说明
+
+## 简介
+
+GD3303E-EVAL是-兆易创新推出的一款GD32F30X系列的评估板，最高主频高达120M，该开发板具有丰富的板载资源，可以充分发挥 GD32303ZET6 的芯片性能。
+
+该开发板常用 **板载资源** 如下：
+
+- GD32303ZET6，主频 120MHz，512KB FLASH ，64KB RAM
+
+- 常用外设
+
+ - LED ：5个，LED1 (电源指示灯），LED2（PC0），LED3（PC2），LED4（PE0），LED5（PE1）
+ - 按键：3个，K1（用户按键，PA0），K2（用户按键，PC13），K3（用户按键，PB14）
+
+- 常用接口：USB 接口
+
+- 调试接口：GD-LINK
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+|:--------- |:--------:|:------------------------------------- |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART0 - UART7 |
+| I2C | 支持 | I2C1 |
+| SPI | 支持 | SPI0 - SPI2 |
+| SPI FLASH | 支持 | |
+| **扩展模块** | **支持情况** | **备注** |
+| 暂无 | 暂不支持 | 暂不支持 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.4 build Jan 9 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [BruceOu](https://github.com/Ouxiaolong/), 邮箱：
\ No newline at end of file
diff --git a/bsp/gd32/gd32303e-eval/SConscript b/bsp/gd32/gd32303e-eval/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/gd32/gd32303e-eval/SConstruct b/bsp/gd32/gd32303e-eval/SConstruct
new file mode 100644
index 0000000000..f32e96f624
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+gd32_library = 'GD32F30x_Firmware_Library'
+rtconfig.BSP_LIBRARY_TYPE = gd32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32/gd32303e-eval/applications/SConscript b/bsp/gd32/gd32303e-eval/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32/gd32303e-eval/applications/main.c b/bsp/gd32/gd32303e-eval/applications/main.c
new file mode 100644
index 0000000000..3e85fc86ca
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/applications/main.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-08-20 BruceOu first implementation
+ */
+
+#include
+#include
+#include
+#include
+
+/* defined the LED2 pin: PF0 */
+#define LED2_PIN GET_PIN(F, 0)
+
+int main(void)
+{
+ int count = 1;
+
+ /* set LED2 pin mode to output */
+ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED2_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED2_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/gd32/gd32303e-eval/board/Kconfig b/bsp/gd32/gd32303e-eval/board/Kconfig
new file mode 100644
index 0000000000..c4b496f179
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/Kconfig
@@ -0,0 +1,85 @@
+menu "Hardware Drivers Config"
+
+config SOC_SERIES_GD32F30x
+ bool
+ default y
+
+config SOC_GD32303Z
+ bool
+ select SOC_SERIES_GD32F30x
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default y
+
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ depends on BSP_USING_SPI1
+ default n
+
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ depends on BSP_USING_SPI1
+ select BSP_SPI1_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 216
+ default 24
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 216
+ default 25
+ endif
+ source "../libraries/gd32_drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/gd32/gd32303e-eval/board/SConscript b/bsp/gd32/gd32303e-eval/board/SConscript
new file mode 100644
index 0000000000..1d4c0408eb
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/SConscript
@@ -0,0 +1,28 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path = [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/GD32F30x_Firmware_Library/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/GD32F30x_Firmware_Library/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/GD32F30x_Firmware_Library/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s']
+
+CPPDEFINES = ['GD32F30X_HD']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/gd32/gd32303e-eval/board/board.c b/bsp/gd32/gd32303e-eval/board/board.c
new file mode 100644
index 0000000000..c409645b37
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/board.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#include
+#include
+#include
+#include
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @param None
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler */
+ /* User can add his own implementation to report the HAL error return state */
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+ NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+ /* NVIC Configuration */
+#define NVIC_VTOR_MASK 0x3FFFFF80
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x10000000 */
+ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
+#endif
+
+ SystemClock_Config();
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef BSP_USING_SDRAM
+ rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
+#else
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/gd32/gd32303e-eval/board/board.h b/bsp/gd32/gd32303e-eval/board/board.h
new file mode 100644
index 0000000000..aecf8beaad
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/board.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-18 BruceOu first implementation
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "gd32f30x.h"
+#include "drv_usart.h"
+#include "drv_gpio.h"
+
+#include "gd32f30x_exti.h"
+
+#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
+#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
+
+// Internal SRAM memory size[Kbytes] <8-64>
+// Default: 64
+#ifdef __ICCARM__
+// Use *.icf ram symbal, to avoid hardcode.
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE 64
+#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END GD32_SRAM_END
+
+#endif
+
diff --git a/bsp/gd32/gd32303e-eval/board/gd32f30x_libopt.h b/bsp/gd32/gd32303e-eval/board/gd32f30x_libopt.h
new file mode 100644
index 0000000000..e026fd658a
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/gd32f30x_libopt.h
@@ -0,0 +1,65 @@
+/*!
+ \file gd32f30x_libopt.h
+ \brief library optional for gd32f30x
+
+ \version 2021-03-23, V2.0.0, demo for GD32F30x
+*/
+
+/*
+ Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F30X_LIBOPT_H
+#define GD32F30X_LIBOPT_H
+
+#include "gd32f30x_rcu.h"
+#include "gd32f30x_adc.h"
+#include "gd32f30x_can.h"
+#include "gd32f30x_crc.h"
+#include "gd32f30x_ctc.h"
+#include "gd32f30x_dac.h"
+#include "gd32f30x_dbg.h"
+#include "gd32f30x_dma.h"
+#include "gd32f30x_exti.h"
+#include "gd32f30x_fmc.h"
+#include "gd32f30x_fwdgt.h"
+#include "gd32f30x_gpio.h"
+#include "gd32f30x_i2c.h"
+#include "gd32f30x_pmu.h"
+#include "gd32f30x_bkp.h"
+#include "gd32f30x_rtc.h"
+#include "gd32f30x_sdio.h"
+#include "gd32f30x_spi.h"
+#include "gd32f30x_timer.h"
+#include "gd32f30x_usart.h"
+#include "gd32f30x_wwdgt.h"
+#include "gd32f30x_misc.h"
+#include "gd32f30x_exmc.h"
+#ifdef GD32F30X_CL
+#include "gd32f30x_enet.h"
+#endif /* GD32F30X_CL */
+
+#endif /* GD32F30X_LIBOPT_H */
diff --git a/bsp/gd32/gd32303e-eval/board/linker_scripts/link.icf b/bsp/gd32/gd32303e-eval/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..f68fd14425
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/linker_scripts/link.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x200FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__ = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
\ No newline at end of file
diff --git a/bsp/gd32/gd32303e-eval/board/linker_scripts/link.ld b/bsp/gd32/gd32303e-eval/board/linker_scripts/link.ld
new file mode 100644
index 0000000000..357cefe333
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/linker_scripts/link.ld
@@ -0,0 +1,142 @@
+/*
+ * linker script for GD32F30x with GNU ld
+ * BruceOu 2021-12-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
+ DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } > CODE = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > CODE
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >DATA
+
+ .stack :
+ {
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >DATA
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > DATA
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/gd32/gd32303e-eval/board/linker_scripts/link.sct b/bsp/gd32/gd32303e-eval/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..0835abf43e
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/gd32/gd32303e-eval/project.uvoptx b/bsp/gd32/gd32303e-eval/project.uvoptx
new file mode 100644
index 0000000000..904a7c0f0e
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/project.uvoptx
@@ -0,0 +1,748 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
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+ 1
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+
+
+ 1
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+ 0
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+
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+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F305RC$Flash\GD32F30x_CL.FLM))
+
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diff --git a/bsp/gd32/gd32303e-eval/project.uvproj b/bsp/gd32/gd32303e-eval/project.uvproj
new file mode 100644
index 0000000000..aabe6bfeb4
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/project.uvproj
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+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
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+
+ GD32F303ZE
+ GigaDevice
+ IRAM(0x20000000-0x20010000) IROM(0x08000000-0x08080000) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2
+
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diff --git a/bsp/gd32/gd32303e-eval/project.uvprojx b/bsp/gd32/gd32303e-eval/project.uvprojx
new file mode 100644
index 0000000000..126600ce4b
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/project.uvprojx
@@ -0,0 +1,668 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F303ZE
+ GigaDevice
+ GigaDevice.GD32F30x_DFP.2.1.0
+ http://gd32mcu.com/data/documents/pack/
+ IRAM(0x20000000,0x010000) IROM(0x08000000,0x080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F303ZE$Flash\GD32F30x_CL.FLM))
+ 0
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+
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+ system_gd32f30x.c
+ 1
+ ..\libraries\GD32F30x_Firmware_Library\CMSIS\GD\GD32F30x\Source\system_gd32f30x.c
+
+
+ gd32f30x_rcu.c
+ 1
+ ..\libraries\GD32F30x_Firmware_Library\GD32F30x_standard_peripheral\Source\gd32f30x_rcu.c
+
+
+ gd32f30x_usart.c
+ 1
+ ..\libraries\GD32F30x_Firmware_Library\GD32F30x_standard_peripheral\Source\gd32f30x_usart.c
+
+
+ gd32f30x_exti.c
+ 1
+ ..\libraries\GD32F30x_Firmware_Library\GD32F30x_standard_peripheral\Source\gd32f30x_exti.c
+
+
+ gd32f30x_gpio.c
+ 1
+ ..\libraries\GD32F30x_Firmware_Library\GD32F30x_standard_peripheral\Source\gd32f30x_gpio.c
+
+
+ gd32f30x_misc.c
+ 1
+ ..\libraries\GD32F30x_Firmware_Library\GD32F30x_standard_peripheral\Source\gd32f30x_misc.c
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32/gd32303e-eval/rtconfig.h b/bsp/gd32/gd32303e-eval/rtconfig.h
new file mode 100644
index 0000000000..099327af24
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/rtconfig.h
@@ -0,0 +1,200 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_LIBC_USING_TIME
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_SERIES_GD32F30x
+#define SOC_GD32305R
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/gd32/gd32303e-eval/rtconfig.py b/bsp/gd32/gd32303e-eval/rtconfig.py
new file mode 100644
index 0000000000..a91905a233
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/rtconfig.py
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M4.fp '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M4'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=VFPv4_sp'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M4'
+ AFLAGS += ' --fpu VFPv4_sp'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/gd32/gd32303e-eval/template.uvoptx b/bsp/gd32/gd32303e-eval/template.uvoptx
new file mode 100644
index 0000000000..18fdad5165
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/template.uvoptx
@@ -0,0 +1,180 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
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+ 1
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+
+
+ 0
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+
+ 0
+
+ 0
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F305RC$Flash\GD32F30x_CL.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32303e-eval/template.uvproj b/bsp/gd32/gd32303e-eval/template.uvproj
new file mode 100644
index 0000000000..c42d8a33b1
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/template.uvproj
@@ -0,0 +1,628 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F303ZE
+ GigaDevice
+ IRAM(0x20000000-0x20010000) IROM(0x08000000-0x08080000) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2
+
+ "Startup\GD\GD32F30x\startup_gd32f30x.s" ("GD32F30x Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F30x_3MB -FS08000000 -FL0300000)
+ 0
+ gd32f30x0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F30x\GD32F30x.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F30x\
+ GD\GD32F30x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 1
+
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
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+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M4"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
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+ 8
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+
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+
+
+ 0
+ 0x20000000
+ 0x30000
+
+
+ 1
+ 0x8000000
+ 0x300000
+
+
+ 0
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+
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+
+ 1
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+
+ 1
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+
+ 1
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+ 0x300000
+
+
+ 1
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+
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+
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+
+
+ 0
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+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x30000
+
+
+ 0
+ 0x10000000
+ 0x10000
+
+
+
+
+
+ 1
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+ 0
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+ 1
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+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F30x\Include;..\..\..\Library\Utilities;..\
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
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+
+
+
+
+
+
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+
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+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Application
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+ gd32f30x_it.c
+ 1
+ ..\gd32f30x_it.c
+
+
+
+
+ CMSIS
+
+
+ system_gd32f30x.c
+ 1
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F30x\Source\system_gd32f30x.c
+
+
+
+
+ GD32F30x_Peripherals
+
+
+ gd32f30x_adc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_adc.c
+
+
+ gd32f30x_can.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_can.c
+
+
+ gd32f30x_crc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_crc.c
+
+
+ gd32f30x_ctc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_ctc.c
+
+
+ gd32f30x_dac.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_dac.c
+
+
+ gd32f30x_dbg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_dbg.c
+
+
+ gd32f30x_dci.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_dci.c
+
+
+ gd32f30x_dma.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_dma.c
+
+
+ gd32f30x_enet.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_enet.c
+
+
+ gd32f30x_exmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_exmc.c
+
+
+ gd32f30x_exti.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_exti.c
+
+
+ gd32f30x_fmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_fmc.c
+
+
+ gd32f30x_fwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_fwdgt.c
+
+
+ gd32f30x_gpio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_gpio.c
+
+
+ gd32f30x_i2c.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_i2c.c
+
+
+ gd32f30x_ipa.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_ipa.c
+
+
+ gd32f30x_iref.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_iref.c
+
+
+ gd32f30x_misc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_misc.c
+
+
+ gd32f30x_pmu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_pmu.c
+
+
+ gd32f30x_rcu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_rcu.c
+
+
+ gd32f30x_rtc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_rtc.c
+
+
+ gd32f30x_sdio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_sdio.c
+
+
+ gd32f30x_spi.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_spi.c
+
+
+ gd32f30x_syscfg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_syscfg.c
+
+
+ gd32f30x_timer.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_timer.c
+
+
+ gd32f30x_tli.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_tli.c
+
+
+ gd32f30x_trng.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_trng.c
+
+
+ gd32f30x_usart.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_usart.c
+
+
+ gd32f30x_wwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F30x_standard_peripheral\Source\gd32f30x_wwdgt.c
+
+
+
+
+ GD32F30x_EVAL
+
+
+ gd32f303e_eval.c
+ 1
+ ..\..\..\Library\Utilities\gd32f303e_eval.c
+
+
+
+
+ Startup
+
+
+ startup_gd32f30x.s
+ 2
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F30x\Source\ARM\startup_gd32f30x.s
+
+
+
+
+ Doc
+
+
+ readme.txt
+ 5
+ ..\readme.txt
+
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32303e-eval/template.uvprojx b/bsp/gd32/gd32303e-eval/template.uvprojx
new file mode 100644
index 0000000000..7f6137db37
--- /dev/null
+++ b/bsp/gd32/gd32303e-eval/template.uvprojx
@@ -0,0 +1,418 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::.\ARMCC
+ 0
+
+
+ GD32F303ZE
+ GigaDevice
+ GigaDevice.GD32F30x_DFP.2.1.0
+ http://gd32mcu.com/data/documents/pack/
+ IRAM(0x20000000,0x010000) IROM(0x08000000,0x080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F303ZE$Flash\GD32F30x_CL.FLM))
+ 0
+ $$Device:GD32F303ZE$Device\Include\gd32f30x.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F303ZE$SVD\GD32F30x_CL.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rtthread
+ 1
+ 0
+ 0
+ 1
+ 0
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
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+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
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+ fromelf --bin !L --output rtthread.bin
+
+ 0
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+
+ 0
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+ 0
+ 0
+ 0
+ 1
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+ 0
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+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M4"
+
+ 0
+ 0
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+ 0
+ 0
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+ 0
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+ 0
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+
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+ 0
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+
+
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+ 0x8000000
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+
+
+ 0
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+
+ 1
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+ 0x40000
+
+
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+
+
+
+
+
+
+
+ 1
+ 0
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+ 0
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+ 0
+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32/gd32450z-eval/.config b/bsp/gd32/gd32450z-eval/.config
new file mode 100644
index 0000000000..0acca6c304
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/.config
@@ -0,0 +1,636 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_BIG_ENDIAN is not set
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_RT_USING_ARDUINO is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_USB_STACK is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_SERIES_GD32F4xx=y
+CONFIG_SOC_GD32450Z=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/gd32/gd32450z-eval/Kconfig b/bsp/gd32/gd32450z-eval/Kconfig
new file mode 100644
index 0000000000..8cbc7b71a8
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/gd32/gd32450z-eval/README.md b/bsp/gd32/gd32450z-eval/README.md
new file mode 100644
index 0000000000..6b398d8661
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/README.md
@@ -0,0 +1,94 @@
+# GD32450Z-EVAL开发板BSP说明
+
+## 简介
+
+GD32450Z-EVAL是-兆易创新推出的一款GD32F4XX系列的评估板，最高主频高达168M，该开发板具有丰富的板载资源，可以充分发挥 GD32F450ZKT6的芯片性能。
+
+该开发板常用 **板载资源** 如下：
+
+- GD32F450ZKT6，主频 200MHz，3072KB FLASH ，256KB RAM
+
+- 常用外设
+
+ - LED ：3个，LED1 (PD4），LED2（PD5），LED3（PG3）
+ - 按键：2个，K1（PA0），K2（PC13），K3（PB14）
+
+- 常用接口：USB 接口
+
+- 调试接口：GD-LINK
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+|:--------- |:--------:|:------------------------------------- |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART0 - UART7 |
+| I2C | 支持 | I2C1 |
+| SPI | 支持 | SPI0 - SPI2 |
+| SPI FLASH | 支持 | |
+| **扩展模块** | **支持情况** | **备注** |
+| 暂无 | 暂不支持 | 暂不支持 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.4 build Jan 9 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [BruceOu](https://github.com/Ouxiaolong/), 邮箱：
\ No newline at end of file
diff --git a/bsp/gd32/gd32450z-eval/SConscript b/bsp/gd32/gd32450z-eval/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/gd32/gd32450z-eval/SConstruct b/bsp/gd32/gd32450z-eval/SConstruct
new file mode 100644
index 0000000000..71deeebad1
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+gd32_library = 'GD32F4xx_Firmware_Library'
+rtconfig.BSP_LIBRARY_TYPE = gd32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32/gd32450z-eval/applications/SConscript b/bsp/gd32/gd32450z-eval/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32/gd32450z-eval/applications/main.c b/bsp/gd32/gd32450z-eval/applications/main.c
new file mode 100644
index 0000000000..5ce66c9b0c
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/applications/main.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-08-20 BruceOu first implementation
+ */
+
+#include
+#include
+#include
+#include
+
+/* defined the LED1 pin: PD4 */
+#define LED1_PIN GET_PIN(D, 4)
+
+int main(void)
+{
+ int count = 1;
+
+ /* set LED1 pin mode to output */
+ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED1_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED1_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/gd32/gd32450z-eval/board/Kconfig b/bsp/gd32/gd32450z-eval/board/Kconfig
new file mode 100644
index 0000000000..6d37255141
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/Kconfig
@@ -0,0 +1,85 @@
+menu "Hardware Drivers Config"
+
+config SOC_SERIES_GD32F4xx
+ bool
+ default y
+
+config SOC_GD32450Z
+ bool
+ select SOC_SERIES_GD32F4xx
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default y
+
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ depends on BSP_USING_SPI1
+ default n
+
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ depends on BSP_USING_SPI1
+ select BSP_SPI1_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 216
+ default 24
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 216
+ default 25
+ endif
+ source "../libraries/gd32_drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/gd32/gd32450z-eval/board/SConscript b/bsp/gd32/gd32450z-eval/board/SConscript
new file mode 100644
index 0000000000..77a18f74e1
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/SConscript
@@ -0,0 +1,28 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path = [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+ src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s']
+
+CPPDEFINES = ['GD32F450']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/gd32/gd32450z-eval/board/board.c b/bsp/gd32/gd32450z-eval/board/board.c
new file mode 100644
index 0000000000..0e9f89865a
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/board.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-08-20 BruceOu first implementation
+ */
+#include
+#include
+#include
+#include
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @param None
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler */
+ /* User can add his own implementation to report the HAL error return state */
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+ NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+ /* NVIC Configuration */
+#define NVIC_VTOR_MASK 0x3FFFFF80
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x10000000 */
+ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
+#endif
+
+ SystemClock_Config();
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef BSP_USING_SDRAM
+ rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
+#else
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/gd32/gd32450z-eval/board/board.h b/bsp/gd32/gd32450z-eval/board/board.h
new file mode 100644
index 0000000000..59e00a88ca
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/board.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-08-20 BruceOu first implementation
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "gd32f4xx.h"
+#include "drv_usart.h"
+#include "drv_gpio.h"
+
+#include "gd32f4xx_exti.h"
+
+#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
+#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
+
+// Internal SRAM memory size[Kbytes] <8-256>
+// Default: 256
+#ifdef __ICCARM__
+// Use *.icf ram symbal, to avoid hardcode.
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE 256
+#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END GD32_SRAM_END
+
+#endif
+
diff --git a/bsp/gd32/gd32450z-eval/board/gd32f4xx_libopt.h b/bsp/gd32/gd32450z-eval/board/gd32f4xx_libopt.h
new file mode 100644
index 0000000000..d26e3d15ec
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/gd32f4xx_libopt.h
@@ -0,0 +1,45 @@
+/*!
+ \file gd32f4xx_libopt.h
+ \brief library optional for gd32f4xx
+*/
+
+/*
+ Copyright (C) 2016 GigaDevice
+
+ 2016-10-19, V1.0.0, firmware for GD32F4xx
+*/
+
+#ifndef GD32F4XX_LIBOPT_H
+#define GD32F4XX_LIBOPT_H
+#include "gd32f4xx_rcu.h"
+#include "gd32f4xx_adc.h"
+#include "gd32f4xx_can.h"
+#include "gd32f4xx_crc.h"
+#include "gd32f4xx_ctc.h"
+#include "gd32f4xx_dac.h"
+#include "gd32f4xx_dbg.h"
+#include "gd32f4xx_dci.h"
+#include "gd32f4xx_dma.h"
+//#include "gd32f4xx_enet.h"
+#include "gd32f4xx_exmc.h"
+#include "gd32f4xx_exti.h"
+#include "gd32f4xx_fmc.h"
+#include "gd32f4xx_fwdgt.h"
+#include "gd32f4xx_gpio.h"
+#include "gd32f4xx_syscfg.h"
+#include "gd32f4xx_i2c.h"
+#include "gd32f4xx_ipa.h"
+#include "gd32f4xx_iref.h"
+#include "gd32f4xx_pmu.h"
+#include "gd32f4xx_rcu.h"
+#include "gd32f4xx_rtc.h"
+#include "gd32f4xx_sdio.h"
+#include "gd32f4xx_spi.h"
+#include "gd32f4xx_timer.h"
+#include "gd32f4xx_tli.h"
+#include "gd32f4xx_trng.h"
+#include "gd32f4xx_usart.h"
+#include "gd32f4xx_wwdgt.h"
+#include "gd32f4xx_misc.h"
+
+#endif /* GD32F4XX_LIBOPT_H */
diff --git a/bsp/gd32/gd32450z-eval/board/linker_scripts/link.icf b/bsp/gd32/gd32450z-eval/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..be287f2c06
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/linker_scripts/link.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x082FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__ = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+place in RAM1_region { section .sram };
\ No newline at end of file
diff --git a/bsp/gd32/gd32450z-eval/board/linker_scripts/link.ld b/bsp/gd32/gd32450z-eval/board/linker_scripts/link.ld
new file mode 100644
index 0000000000..f39b59d02d
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/linker_scripts/link.ld
@@ -0,0 +1,142 @@
+/*
+ * linker script for GD32F4xx with GNU ld
+ * bernard.xiong 2009-10-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */
+ DATA (rw) : ORIGIN = 0x20000000, LENGTH = 256k /* 256KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } > CODE = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > CODE
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >DATA
+
+ .stack :
+ {
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >DATA
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > DATA
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/gd32/gd32450z-eval/board/linker_scripts/link.sct b/bsp/gd32/gd32450z-eval/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..fd32503883
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00300000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00300000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00040000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/gd32/gd32450z-eval/project.uvoptx b/bsp/gd32/gd32450z-eval/project.uvoptx
new file mode 100644
index 0000000000..8117421f4d
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/project.uvoptx
@@ -0,0 +1,778 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"CMSIS-DAP" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM)
+
+
+ 0
+ JL2CM3
+ -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
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+ 0
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+
+
+
+ 0
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+
+
+
+
+
+
+
+
+
+
+
+
+ Applications
+ 0
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ applications\main.c
+ main.c
+ 0
+ 0
+
+
+
+
+ CPU
+ 0
+ 0
+ 0
+ 0
+
+ 2
+ 2
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\common\backtrace.c
+ backtrace.c
+ 0
+ 0
+
+
+ 2
+ 3
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\common\div0.c
+ div0.c
+ 0
+ 0
+
+
+ 2
+ 4
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\common\showmem.c
+ showmem.c
+ 0
+ 0
+
+
+ 2
+ 5
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\cortex-m4\cpuport.c
+ cpuport.c
+ 0
+ 0
+
+
+ 2
+ 6
+ 2
+ 0
+ 0
+ 0
+ ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
+ context_rvds.S
+ 0
+ 0
+
+
+
+
+ DeviceDrivers
+ 0
+ 0
+ 0
+ 0
+
+ 3
+ 7
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+ ..\..\..\components\drivers\misc\pin.c
+ pin.c
+ 0
+ 0
+
+
+ 3
+ 8
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\serial\serial.c
+ serial.c
+ 0
+ 0
+
+
+ 3
+ 9
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\src\waitqueue.c
+ waitqueue.c
+ 0
+ 0
+
+
+ 3
+ 10
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\src\workqueue.c
+ workqueue.c
+ 0
+ 0
+
+
+ 3
+ 11
+ 1
+ 0
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+ 0
+ ..\..\..\components\drivers\src\ringbuffer.c
+ ringbuffer.c
+ 0
+ 0
+
+
+ 3
+ 12
+ 1
+ 0
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+ 0
+ ..\..\..\components\drivers\src\completion.c
+ completion.c
+ 0
+ 0
+
+
+ 3
+ 13
+ 1
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+ ..\..\..\components\drivers\src\pipe.c
+ pipe.c
+ 0
+ 0
+
+
+ 3
+ 14
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\src\ringblk_buf.c
+ ringblk_buf.c
+ 0
+ 0
+
+
+ 3
+ 15
+ 1
+ 0
+ 0
+ 0
+ ..\..\..\components\drivers\src\dataqueue.c
+ dataqueue.c
+ 0
+ 0
+
+
+
+
+ Drivers
+ 0
+ 0
+ 0
+ 0
+
+ 4
+ 16
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\gd32_drivers\drv_gpio.c
+ drv_gpio.c
+ 0
+ 0
+
+
+ 4
+ 17
+ 1
+ 0
+ 0
+ 0
+ ..\libraries\gd32_drivers\drv_usart.c
+ drv_usart.c
+ 0
+ 0
+
+
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diff --git a/bsp/gd32/gd32450z-eval/project.uvproj b/bsp/gd32/gd32450z-eval/project.uvproj
new file mode 100644
index 0000000000..96217840c7
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/project.uvproj
@@ -0,0 +1,747 @@
+
+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F450ZK
+ GigaDevice
+ IRAM(0x20000000-0x20030000) IROM(0x08000000-0x08300000) CLOCK(20000000) CPUTYPE("Cortex-M4") FPU2
+
+ "Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000)
+ 0
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+ GD32F450, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
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diff --git a/bsp/gd32/gd32450z-eval/project.uvprojx b/bsp/gd32/gd32450z-eval/project.uvprojx
new file mode 100644
index 0000000000..da7049b867
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/project.uvprojx
@@ -0,0 +1,677 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F450ZK
+ GigaDevice
+ GigaDevice.GD32F4xx_DFP.2.1.0
+ http://gd32mcu.com/data/documents/pack/
+ IRAM(0x20000000,0x040000) IROM(0x08000000,0x0300000) CPUTYPE("Cortex-M4") FPU2 CLOCK(20000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM))
+ 0
+ $$Device:GD32F450ZK$Device\Include\gd32f4xx.h
+
+
+
+
+
+
+
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+ -REMAP -MPU
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+ GD32F450, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
+
+ applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\gd32_drivers;..\..\..\components\finsh;board;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Include;..\libraries\GD32F4xx_Firmware_Library\CMSIS;..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel
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+
+
+
+
+
+
+
+ 1
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+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ CPU
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m4\cpuport.c
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+
+
+ Drivers
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\gd32_drivers\drv_gpio.c
+
+
+ drv_usart.c
+ 1
+ ..\libraries\gd32_drivers\drv_usart.c
+
+
+
+
+ Finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+ msh.c
+ 1
+ ..\..\..\components\finsh\msh.c
+
+
+ cmd.c
+ 1
+ ..\..\..\components\finsh\cmd.c
+
+
+
+
+ gd32_drivers
+
+
+ startup_gd32f4xx.s
+ 2
+ ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s
+
+
+ board.c
+ 1
+ board\board.c
+
+
+
+
+ Kernel
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+ libc
+
+
+ time.c
+ 1
+ ..\..\..\components\libc\compilers\common\time.c
+
+
+
+
+ Libraries
+
+
+ gd32f4xx_syscfg.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c
+
+
+ gd32f4xx_exti.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c
+
+
+ gd32f4xx_gpio.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c
+
+
+ gd32f4xx_rcu.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c
+
+
+ gd32f4xx_misc.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c
+
+
+ gd32f4xx_usart.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c
+
+
+ system_gd32f4xx.c
+ 1
+ ..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32/gd32450z-eval/rtconfig.h b/bsp/gd32/gd32450z-eval/rtconfig.h
new file mode 100644
index 0000000000..0fbd373786
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/rtconfig.h
@@ -0,0 +1,200 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_LIBC_USING_TIME
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_SERIES_GD32F4xx
+#define SOC_GD32450Z
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/gd32/gd32450z-eval/rtconfig.py b/bsp/gd32/gd32450z-eval/rtconfig.py
new file mode 100644
index 0000000000..c0c0b203cf
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/rtconfig.py
@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iar'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F450'
+ CFLAGS = DEVICE + ' -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M4.fp '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M4'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=VFPv4_sp'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M4'
+ AFLAGS += ' --fpu VFPv4_sp'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/gd32/gd32450z-eval/template.uvoptx b/bsp/gd32/gd32450z-eval/template.uvoptx
new file mode 100644
index 0000000000..3947c5e208
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/template.uvoptx
@@ -0,0 +1,190 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+ 0
+ CMSIS_AGDI
+ -X"CMSIS-DAP" -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM)
+
+
+ 0
+ JL2CM3
+ -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM)
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM))
+
+
+
+
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
+
diff --git a/bsp/gd32/gd32450z-eval/template.uvproj b/bsp/gd32/gd32450z-eval/template.uvproj
new file mode 100644
index 0000000000..a23ad93c9a
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/template.uvproj
@@ -0,0 +1,628 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F450ZK
+ GigaDevice
+ IRAM(0x20000000-0x20030000) IROM(0x08000000-0x08300000) CLOCK(20000000) CPUTYPE("Cortex-M4") FPU2
+
+ "Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000)
+ 0
+ gd32f4xx0.h
+
+
+
+
+
+
+
+
+
+ SFD\GD\GD32F4xx\GD32F4xx.SFR
+ 0
+ 0
+
+
+
+ GD\GD32F4xx\
+ GD\GD32F4xx\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\output\
+ rtthread
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
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+
+
+ 0
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+
+
+ 0
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+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM3
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM3
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 1
+
+ 0
+ 3
+
+
+
+
+
+
+
+
+
+
+
+
+
+ BIN\CMSIS_AGDI.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
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+ "Cortex-M4"
+
+ 0
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+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\
+
+
+
+ 1
+ 0
+ 0
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+
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+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ Application
+
+
+ main.c
+ 1
+ ..\main.c
+
+
+ gd32f4xx_it.c
+ 1
+ ..\gd32f4xx_it.c
+
+
+
+
+ CMSIS
+
+
+ system_gd32f4xx.c
+ 1
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c
+
+
+
+
+ GD32F4xx_Peripherals
+
+
+ gd32f4xx_adc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c
+
+
+ gd32f4xx_can.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c
+
+
+ gd32f4xx_crc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c
+
+
+ gd32f4xx_ctc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c
+
+
+ gd32f4xx_dac.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c
+
+
+ gd32f4xx_dbg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c
+
+
+ gd32f4xx_dci.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c
+
+
+ gd32f4xx_dma.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c
+
+
+ gd32f4xx_enet.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c
+
+
+ gd32f4xx_exmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c
+
+
+ gd32f4xx_exti.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c
+
+
+ gd32f4xx_fmc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c
+
+
+ gd32f4xx_fwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c
+
+
+ gd32f4xx_gpio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c
+
+
+ gd32f4xx_i2c.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c
+
+
+ gd32f4xx_ipa.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c
+
+
+ gd32f4xx_iref.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c
+
+
+ gd32f4xx_misc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c
+
+
+ gd32f4xx_pmu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c
+
+
+ gd32f4xx_rcu.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c
+
+
+ gd32f4xx_rtc.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c
+
+
+ gd32f4xx_sdio.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c
+
+
+ gd32f4xx_spi.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c
+
+
+ gd32f4xx_syscfg.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c
+
+
+ gd32f4xx_timer.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c
+
+
+ gd32f4xx_tli.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c
+
+
+ gd32f4xx_trng.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c
+
+
+ gd32f4xx_usart.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c
+
+
+ gd32f4xx_wwdgt.c
+ 1
+ ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c
+
+
+
+
+ GD32F4xx_EVAL
+
+
+ gd32f450z_eval.c
+ 1
+ ..\..\..\Library\Utilities\gd32f450z_eval.c
+
+
+
+
+ Startup
+
+
+ startup_gd32f4xx.s
+ 2
+ ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s
+
+
+
+
+ Doc
+
+
+ readme.txt
+ 5
+ ..\readme.txt
+
+
+
+
+
+
+
+
diff --git a/bsp/gd32/gd32450z-eval/template.uvprojx b/bsp/gd32/gd32450z-eval/template.uvprojx
new file mode 100644
index 0000000000..5653f2da1d
--- /dev/null
+++ b/bsp/gd32/gd32450z-eval/template.uvprojx
@@ -0,0 +1,417 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 0
+
+
+ GD32F450ZK
+ GigaDevice
+ GigaDevice.GD32F4xx_DFP.2.1.0
+ http://gd32mcu.com/data/documents/pack/
+ IRAM(0x20000000,0x040000) IROM(0x08000000,0x0300000) CPUTYPE("Cortex-M4") FPU2 CLOCK(20000000) ELITTLE
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM))
+ 0
+ $$Device:GD32F450ZK$Device\Include\gd32f4xx.h
+
+
+
+
+
+
+
+
+
+ $$Device:GD32F450ZK$SVD\GD32F4xx.svd
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\
+ rtthread
+ 1
+ 0
+ 0
+ 1
+ 0
+ .\build\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 0
+ fromelf --bin !L --output rtthread.bin
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
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+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M4"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+ 8
+ 0
+ 0
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+ 0
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+ 0
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+ 0
+ 0
+ 0
+ 1
+ 0
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+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x40000
+
+
+ 1
+ 0x8000000
+ 0x300000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x8000000
+ 0x300000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x30000
+
+
+ 0
+ 0x10000000
+ 0x10000
+
+
+
+
+
+ 1
+ 4
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 4
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+ .\gd32_rom.ld
+
+
+
+
+
+
+
+
+
+
+ ::CMSIS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+
+
+
+
+
+ 0
+ 1
+
+
+
+
+
diff --git a/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript b/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript
index f5004445c0..889e33dd2a 100644
--- a/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript
+++ b/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript
@@ -40,6 +40,7 @@ if GetDepend(['RT_USING_HWTIMER']):
if GetDepend(['RT_USING_RTC']):
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c']
+ src += ['GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c']
if GetDepend(['RT_USING_WDT']):
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c']
diff --git a/bsp/gd32/libraries/gd32_drivers/SConscript b/bsp/gd32/libraries/gd32_drivers/SConscript
index b33b2c5768..16a76e2b0b 100644
--- a/bsp/gd32/libraries/gd32_drivers/SConscript
+++ b/bsp/gd32/libraries/gd32_drivers/SConscript
@@ -27,9 +27,21 @@ if GetDepend('RT_USING_SPI'):
# add spi flash drivers.
if GetDepend('RT_USING_SFUD'):
- src += ['drv_spi_flash.c', 'drv_spi.c']
+ src += ['drv_spi_flash.c', 'drv_spi.c']
-path = [cwd]
+if GetDepend('RT_USING_WDT'):
+ src += ['drv_wdt.c']
+
+if GetDepend('RT_USING_RTC'):
+ src += ['drv_rtc.c']
+
+if GetDepend('RT_USING_HWTIMER'):
+ src += ['drv_hwtimer.c']
+
+if GetDepend('RT_USING_ADC'):
+ src += ['drv_adc.c']
+
+path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
diff --git a/bsp/gd32103c-eval/drivers/drv_adc.c b/bsp/gd32/libraries/gd32_drivers/drv_adc.c
similarity index 63%
rename from bsp/gd32103c-eval/drivers/drv_adc.c
rename to bsp/gd32/libraries/gd32_drivers/drv_adc.c
index 65e781e40c..bd3b2d6b63 100644
--- a/bsp/gd32103c-eval/drivers/drv_adc.c
+++ b/bsp/gd32/libraries/gd32_drivers/drv_adc.c
@@ -1,15 +1,14 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
- * 2021-01-03 iysheng first version
+ * 2021-02-25 iysheng first version
*/
#include
-#include
#include
#define DBG_TAG "drv.adc"
@@ -39,7 +38,7 @@ static gd32_adc_device g_gd32_devs[] = {
GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1),
GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5),
},
- ADC0,
+ (void *)ADC0,
},
#endif
@@ -53,7 +52,7 @@ static gd32_adc_device g_gd32_devs[] = {
GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1),
GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5),
},
- ADC1,
+ (void *)ADC1,
},
#endif
};
@@ -61,53 +60,41 @@ static gd32_adc_device g_gd32_devs[] = {
/*
* static void init_pin4adc
*
- * 初始化指定的管腳爲 analog 模式
* @ rt_uint32_t pin: pin information
* return: N/A
*/
static void init_pin4adc(rt_base_t pin)
{
- GPIO_InitPara GPIO_InitStruct = {0};
-
- GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
- GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_50MHZ;
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_AIN;
- GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct);
+ gpio_init(PIN_GDPORT(pin), GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, PIN_GDPIN(pin));
}
static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
- ADC_TypeDef *ADCx;
- ADC_InitPara ADC_InitParaStruct = {0};
+ uint32_t adc_periph;
gd32_adc_device * gd32_adc = (gd32_adc_device *)device;
if (channel >= MAX_EXTERN_ADC_CHANNEL)
{
LOG_E("invalid channel");
- return -E2BIG;
+ return -RT_EINVAL;
}
- ADCx = (ADC_TypeDef *)(device->parent.user_data);
+ adc_periph = (uint32_t )(device->parent.user_data);
if (enabled == ENABLE)
{
init_pin4adc(gd32_adc->adc_pins[channel]);
- ADC_InitParaStruct.ADC_Trig_External = ADC_EXTERNAL_TRIGGER_MODE_NONE;
- /* Fix the channel number to fit the firmware library */
- ADC_InitParaStruct.ADC_Channel_Number = 1 + channel;
- ADC_InitParaStruct.ADC_Data_Align = ADC_DATAALIGN_RIGHT;
- ADC_InitParaStruct.ADC_Mode_Scan = DISABLE;
- ADC_InitParaStruct.ADC_Mode = ADC_MODE_INDEPENDENT;
- ADC_InitParaStruct.ADC_Mode_Continuous = ENABLE;
- ADC_Init(ADCx, &ADC_InitParaStruct);
-
- ADC_RegularChannel_Config(ADCx, channel, 1, ADC_SAMPLETIME_13POINT5);
- ADC_Enable(ADCx, ENABLE);
- ADC_SoftwareStartConv_Enable(ADCx, ENABLE);
+ adc_deinit(adc_periph);
+ adc_channel_length_config(adc_periph, ADC_REGULAR_CHANNEL, 1);
+ adc_data_alignment_config(adc_periph, ADC_DATAALIGN_RIGHT);
+ adc_external_trigger_source_config(adc_periph, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_INSERTED_NONE);
+ adc_external_trigger_config(adc_periph, ADC_REGULAR_CHANNEL, ENABLE);
+ adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_13POINT5);
+ adc_enable(adc_periph);
}
else
{
- ADC_Enable(ADCx, DISABLE);
+ adc_disable(adc_periph);
}
return 0;
@@ -115,16 +102,17 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
- ADC_TypeDef *ADCx;
+ uint32_t adc_periph;
if (!value)
{
LOG_E("invalid param");
- return -EINVAL;
+ return -RT_EINVAL;
}
- ADCx = (ADC_TypeDef *)(device->parent.user_data);
- *value = ADC_GetConversionValue(ADCx);
+ adc_periph = (uint32_t )(device->parent.user_data);
+ adc_software_trigger_enable(adc_periph, ADC_REGULAR_CHANNEL);
+ *value = adc_regular_data_read(adc_periph);
return 0;
}
@@ -148,11 +136,11 @@ static int rt_hw_adc_init(void)
rcu_periph_clock_enable(RCU_ADC1);
#endif
- for (; i < ARRAY_SIZE(g_gd32_devs); i++)
+ for (; i < sizeof(g_gd32_devs) / sizeof(g_gd32_devs[0]); i++)
{
ret = rt_hw_adc_register(&g_gd32_devs[i].adc_dev, \
(const char *)g_gd32_devs[i].name, \
- &g_gd32_adc_ops, g_gd32_devs[i].private_data);
+ &g_gd32_adc_ops, (void *)g_gd32_devs[i].private_data);
if (ret != RT_EOK)
{
/* TODO err handler */
diff --git a/bsp/gd32/libraries/gd32_drivers/drv_gpio.h b/bsp/gd32/libraries/gd32_drivers/drv_gpio.h
index 9300191198..5258a4f5ac 100644
--- a/bsp/gd32/libraries/gd32_drivers/drv_gpio.h
+++ b/bsp/gd32/libraries/gd32_drivers/drv_gpio.h
@@ -38,7 +38,7 @@ extern "C" {
EXTI_SOURCE_PIN##pin}
#else
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
- GPIO##port, GPIO_PIN_##pin, \
+ GPIO##port, GPIO_PIN_##pin, \
GPIO_PORT_SOURCE_GPIO##port, \
GPIO_PIN_SOURCE_##pin}
@@ -48,6 +48,12 @@ extern "C" {
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN)
+#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
+#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
+
+#define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
+#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
+
struct pin_index
{
rt_int16_t index;
diff --git a/bsp/gd32103c-eval/drivers/drv_hwtimer.c b/bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c
similarity index 75%
rename from bsp/gd32103c-eval/drivers/drv_hwtimer.c
rename to bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c
index 8b5f5010e6..1c22b10467 100644
--- a/bsp/gd32103c-eval/drivers/drv_hwtimer.c
+++ b/bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c
@@ -1,19 +1,32 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
- * 2021-01-28 iysheng first version
+ * 2021-02-25 iysheng first version
*/
#include
-#include
-#include
+#include
+#include
#ifdef BSP_USING_HWTIMER
+typedef struct {
+ uint32_t reg_base;
+ IRQn_Type irqn;
+ rcu_periph_enum rcu;
+} gd32_hwtimer_data;
+
+typedef struct {
+ char dev_name[RT_NAME_MAX];
+ const gd32_hwtimer_data hw_data;
+ rt_hwtimer_t hwtimer_dev;
+ const struct rt_hwtimer_info hwtimer_info;
+} gd32_hwtimer_device;
+
enum timer_index_E {
#ifdef BSP_USING_HWTIMER0
TIM0_INDEX,
@@ -67,49 +80,48 @@ enum timer_index_E {
* @param freq of the timer clock
* @retval None
*/
-static void __set_timerx_freq(TIMER_TypeDef *timerx, uint32_t freq)
+static void __set_timerx_freq(uint32_t timerx, uint32_t freq)
{
- RCC_ClocksPara RCC_Clocks = {0};
+ uint32_t ap1freq, ap2freq;
uint16_t prescaler;
uint32_t temp;
- RCC_GetClocksFreq(&RCC_Clocks);
if (timerx == TIMER0 || timerx == TIMER7 || timerx == TIMER8 \
|| timerx == TIMER9 || timerx == TIMER10)
{
- temp = RCC->GCFGR & RCC_GCFGR_APB2PS;
+ ap2freq = rcu_clock_freq_get(CK_APB2);
+ temp = RCU_CFG0 & RCU_CFG0_APB2PSC;
temp >>= 11;
/* whether should frequency doubling */
temp = (temp < 4) ? 0 : 1;
- prescaler = (RCC_Clocks.APB2_Frequency << temp) / freq - 1;
+ prescaler = (ap2freq << temp) / freq - 1;
}
else
{
- temp = RCC->GCFGR & RCC_GCFGR_APB1PS;
+ ap1freq = rcu_clock_freq_get(CK_APB1);
+ temp = RCU_CFG0 & RCU_CFG0_APB1PSC;
temp >>= 8;
/* whether should frequency doubling */
temp = (temp < 4) ? 0 : 1;
- prescaler = (RCC_Clocks.APB1_Frequency << temp) / freq - 1;
+ prescaler = (ap1freq << temp) / freq - 1;
}
- TIMER_PrescalerConfig(timerx, prescaler, TIMER_PSC_RELOAD_NOW);
+ timer_prescaler_config(timerx, prescaler, TIMER_PSC_RELOAD_NOW);
}
static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
- TIMER_TypeDef * timer_base = timer->parent.user_data;
- TIMER_BaseInitPara TIMER_Init;
-
- RT_ASSERT(timer_base);
+ uint32_t timer_base = (uint32_t)timer->parent.user_data;
+ timer_parameter_struct initpara;
if (state)
{
- TIMER_InternalClockConfig(timer_base);
- TIMER_BaseStructInit(&TIMER_Init);
- TIMER_Init.TIMER_Period = timer->info->maxcnt;
- TIMER_BaseInit(timer_base, &TIMER_Init);
+ timer_internal_clock_config(timer_base);
+ timer_struct_para_init(&initpara);
+ initpara.period = timer->info->maxcnt;
+ timer_init(timer_base, &initpara);
__set_timerx_freq(timer_base, timer->info->maxfreq);
}
}
@@ -117,37 +129,37 @@ static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state
static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \
rt_uint32_t cnt, rt_hwtimer_mode_t mode)
{
- TIMER_TypeDef * timer_base = timer->parent.user_data;
+ uint32_t timer_base = (uint32_t)timer->parent.user_data;
if (mode == HWTIMER_MODE_ONESHOT)
{
- TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_SINGLE);
+ timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_SINGLE);
}
else if (mode == HWTIMER_MODE_PERIOD)
{
- TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_REPETITIVE);
+ timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_REPETITIVE);
}
- TIMER_SetCounter(timer_base, 0);
- TIMER_SetAutoreload(timer_base, cnt - 1);
- TIMER_Enable(timer_base, ENABLE);
+ timer_counter_value_config(timer_base, 0);
+ timer_autoreload_value_config(timer_base, cnt - 1);
+ timer_enable(timer_base);
return 0;
}
static void gd32_hwtimer_stop(struct rt_hwtimer_device *timer)
{
- TIMER_TypeDef * timer_base = timer->parent.user_data;
+ uint32_t timer_base = (uint32_t)timer->parent.user_data;
- TIMER_Enable(timer_base, DISABLE);
+ timer_disable(timer_base);
}
static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer)
{
- TIMER_TypeDef * timer_base = timer->parent.user_data;
+ uint32_t timer_base = (uint32_t)timer->parent.user_data;
rt_uint32_t count;
- count = TIMER_GetCounter(timer_base);
+ count = timer_counter_read(timer_base);
return count;
}
@@ -163,11 +175,11 @@ static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_
{
case HWTIMER_CTRL_FREQ_SET:
freq = *(rt_uint32_t *)args;
- __set_timerx_freq(timer->parent.user_data, freq);
+ __set_timerx_freq((uint32_t)timer->parent.user_data, freq);
break;
default:
rt_kprintf("invalid cmd:%x\n", cmd);
- ret = -EINVAL;
+ ret = -RT_EINVAL;
break;
}
@@ -428,8 +440,8 @@ void TIMER0_UP_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -439,8 +451,8 @@ void TIMER1_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -450,8 +462,8 @@ void TIMER2_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -461,8 +473,8 @@ void TIMER3_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -472,8 +484,8 @@ void TIMER4_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -483,8 +495,8 @@ void TIMER5_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -494,8 +506,8 @@ void TIMER6_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -505,8 +517,8 @@ void TIMER7_UP_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev);
- TIMER_ClearIntBitState(g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \
- TIMER_INT_UPDATE);
+ timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \
+ TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
@@ -515,7 +527,7 @@ static int rt_hwtimer_init(void)
{
int ret = 0, i = 0;
- for (; i < ARRAY_SIZE(g_gd32_hwtimer); i++)
+ for (; i < sizeof(g_gd32_hwtimer) / sizeof(g_gd32_hwtimer[0]); i++)
{
g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops;
g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info;
@@ -523,9 +535,9 @@ static int rt_hwtimer_init(void)
rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu);
NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0);
NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn);
- TIMER_INTConfig(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UPDATE, ENABLE);
+ timer_interrupt_enable(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UP);
ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \
- g_gd32_hwtimer[i].dev_name, g_gd32_hwtimer[i].hw_data.reg_base);
+ g_gd32_hwtimer[i].dev_name, (void *)g_gd32_hwtimer[i].hw_data.reg_base);
if (RT_EOK != ret)
{
rt_kprintf("failed register %s, err=%d\n", g_gd32_hwtimer[i].dev_name, \
diff --git a/bsp/gd32103c-eval/drivers/drv_rtc.c b/bsp/gd32/libraries/gd32_drivers/drv_rtc.c
similarity index 89%
rename from bsp/gd32103c-eval/drivers/drv_rtc.c
rename to bsp/gd32/libraries/gd32_drivers/drv_rtc.c
index 95c6e56e9d..4ed2a31f38 100644
--- a/bsp/gd32103c-eval/drivers/drv_rtc.c
+++ b/bsp/gd32/libraries/gd32_drivers/drv_rtc.c
@@ -1,16 +1,15 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
- * 2021-02-20 iysheng first version
+ * 2022-01-25 iysheng first version
*/
#include
#include
-#include
#define DBG_TAG "drv.rtc"
#define DBG_LVL DBG_INFO
@@ -29,7 +28,7 @@ static time_t get_rtc_timestamp(void)
{
time_t rtc_counter;
- rtc_counter = (time_t)RTC_GetCounter();
+ rtc_counter = (time_t)rtc_counter_get();
return rtc_counter;
}
@@ -41,15 +40,15 @@ static rt_err_t set_rtc_timestamp(time_t time_stamp)
rtc_counter = (uint32_t)time_stamp;
/* wait until LWOFF bit in RTC_CTL to 1 */
- RTC_WaitLWOFF();
+ rtc_lwoff_wait();
/* enter configure mode */
- RTC_EnterConfigMode();
+ rtc_configuration_mode_enter();
/* write data to rtc register */
- RTC_SetCounter(rtc_counter);
+ rtc_counter_set(rtc_counter);
/* exit configure mode */
- RTC_ExitConfigMode();
+ rtc_configuration_mode_exit();
/* wait until LWOFF bit in RTC_CTL to 1 */
- RTC_WaitLWOFF();
+ rtc_lwoff_wait();
return RT_EOK;
}
@@ -94,7 +93,7 @@ static int rt_hw_rtc_init(void)
time_t rtc_counter;
rcu_periph_clock_enable(RCU_PMU);
- PWR_BackupAccess_Enable(ENABLE);
+ pmu_backup_write_enable();
rcu_periph_clock_enable(RCU_BKPI);
rtc_counter = get_rtc_timestamp();
diff --git a/bsp/gd32103c-eval/drivers/drv_iwdt.c b/bsp/gd32/libraries/gd32_drivers/drv_wdt.c
similarity index 69%
rename from bsp/gd32103c-eval/drivers/drv_iwdt.c
rename to bsp/gd32/libraries/gd32_drivers/drv_wdt.c
index f218f46104..8ef5096caf 100644
--- a/bsp/gd32103c-eval/drivers/drv_iwdt.c
+++ b/bsp/gd32/libraries/gd32_drivers/drv_wdt.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
- * 2021-03-03 iysheng first version
+ * 2022-01-25 iysheng first version
*/
#include
@@ -25,13 +25,13 @@ typedef struct {
static gd32_wdt_device_t g_wdt_dev;
-static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
+static rt_err_t gd32_wdt_init(rt_watchdog_t *wdt)
{
rcu_osci_on(RCU_IRC40K);
if (ERROR == rcu_osci_stab_wait(RCU_IRC40K))
{
LOG_E("failed init IRC40K clock for free watchdog.");
- return -EINVAL;
+ return -RT_EINVAL;
}
g_wdt_dev.min_threshold_s = 1;
@@ -39,22 +39,21 @@ static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
LOG_I("threshold section [%u, %d]", \
g_wdt_dev.min_threshold_s, g_wdt_dev.max_threshold_s);
- IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
- IWDG_SetPrescaler(IWDG_PRESCALER_256);
- IWDG_SetReloadValue(0xfff);
- IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
+ fwdgt_write_enable();
+ fwdgt_config(0xfff, FWDGT_PSC_DIV256);
+ fwdgt_enable();
return 0;
}
-static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+static rt_err_t gd32_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint32_t param;
switch (cmd)
{
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
- IWDG_ReloadCounter();
+ fwdgt_counter_reload();
break;
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
param = *(rt_uint32_t *) arg;
@@ -62,21 +61,21 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
(param < g_wdt_dev.min_threshold_s))
{
LOG_E("invalid param@%u.", param);
- return -E2BIG;
+ return -RT_EINVAL;
}
else
{
g_wdt_dev.current_threshold_s = param;
}
- IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
- IWDG_SetReloadValue(param * 40000 >> 8);
- IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
+ fwdgt_write_enable();
+ fwdgt_config(param * 40000 >> 8, FWDGT_PSC_DIV256);
+ fwdgt_write_disable();
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
*(rt_uint32_t *)arg = g_wdt_dev.current_threshold_s;
break;
case RT_DEVICE_CTRL_WDT_START:
- IWDG_Enable();
+ fwdgt_enable();
break;
default:
LOG_W("This command is not supported.");
@@ -87,17 +86,17 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
}
static struct rt_watchdog_ops g_wdt_ops = {
- gd32_iwdt_init,
- gd32_iwdt_control,
+ gd32_wdt_init,
+ gd32_wdt_control,
};
-static int rt_hw_iwdt_init(void)
+static int rt_hw_wdt_init(void)
{
rt_err_t ret;
g_wdt_dev.wdt.ops = &g_wdt_ops;
/* register watchdog device */
- if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "iwdt", \
+ if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "wdt", \
RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
@@ -107,5 +106,5 @@ static int rt_hw_iwdt_init(void)
return ret;
}
-INIT_BOARD_EXPORT(rt_hw_iwdt_init);
+INIT_PREV_EXPORT(rt_hw_wdt_init);
#endif
diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h
deleted file mode 100644
index 1dde2fb596..0000000000
--- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h
+++ /dev/null
@@ -1,8033 +0,0 @@
-/**
- ******************************************************************************
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File..
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup GD32f10X
- * @{
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_H
-#define __GD32F10X_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target gd32f10x device used in your
- application
- */
-
-#if !defined (GD32F10X_MD)&&!defined (GD32F10X_HD)&&!defined (GD32F10X_XD)&&!defined (GD32F10X_CL)
-/* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */
-#define GD32F10X_HD /*!< GD32F10X_HD: GD32 High density Value Line devices */
-/* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */
-/* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */
-#endif
-
-
-#if !defined (GD32F10X_MD)&&!defined (GD32F10X_HD)&&!defined (GD32F10X_XD)&&!defined (GD32F10X_CL)
-#error "Please select first the target gd32f10x device used in your application (in gd32f10x.h file)"
-#endif /* GD32F10X */
-
-#if !defined USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
-/*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if !defined HSE_VALUE
-#ifdef GD32F10X_CL
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#else
-#define HSE_VALUE ((uint32_t)8000000) /* !< From 4M to 16M *!< Value of the External oscillator in Hz*/
-#endif /* HSE_VALUE */
-#endif
-
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0xFFFF) /*!< Time out for HSI start up */
-
-/* define value of high speed crystal oscillator (HXTAL) in Hz */
-#if !defined HXTAL_VALUE
-#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
-#endif /* high speed crystal oscillator value */
-
-/* define startup timeout value of high speed crystal oscillator (HXTAL) */
-#if !defined (HXTAL_STARTUP_TIMEOUT)
-#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
-#endif /* high speed crystal oscillator startup timeout */
-
-/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
-#if !defined (IRC8M_STARTUP_TIMEOUT)
-#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
-#endif /* internal 8MHz RC oscillator startup timeout */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI_VALUE */
-
-/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
-#if !defined (IRC48M_VALUE)
-#define IRC48M_VALUE ((uint32_t)48000000)
-#endif /* internal 48MHz RC oscillator value */
-
-/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
-#if !defined (IRC8M_VALUE)
-#define IRC8M_VALUE ((uint32_t)8000000)
-#endif /* internal 8MHz RC oscillator value */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* LSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief GD32F10X Firmware Library version number V1.0
- */
-#define __GD32F10X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __GD32F10X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __GD32F10X_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
-#define __GD32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __GD32F10X_STDPERIPH_VERSION ((__GD32F10X_STDPERIPH_VERSION_MAIN << 24)\
- |(__GD32F10X_STDPERIPH_VERSION_SUB1 << 16)\
- |(__GD32F10X_STDPERIPH_VERSION_SUB2 << 8)\
- |(__GD32F10X_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#define __MPU_PRESENT 0 /*!< GD32 devices does not provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< GD32F10X uses 4 Bits for the Priority Levels */
-#define __VENDOR_SYSTICKCONFIG 0 /*!< Set to 1 if different SysTick Config is used */
-
-/*!< Interrupt Number Definition */
-typedef enum IRQn {
- /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
- /****** GD32 specific Interrupt Numbers *********************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- LVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */
- RTC_IRQn = 3, /*!< RTC global Interrupt */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
-
-#ifdef GD32F10X_MD
- ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIMER0_BRK_IRQn = 24, /*!< TIMER0 Break Interrupt */
- TIMER0_UP_IRQn = 25, /*!< TIMER0 Update Interrupt */
- TIMER0_TRG_COM_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt */
- TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */
- TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */
- TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */
- TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
- EXMC_IRQn = 48 /*!< EXMC global Interrupt */
-#endif /* GD32F10X_MD */
-
-#ifdef GD32F10X_HD
- ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIMER0_BRK_IRQn = 24, /*!< TIMER0 Break Interrupt */
- TIMER0_UP_IRQn = 25, /*!< TIMER0 Update Interrupt */
- TIMER0_TRG_COM_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt */
- TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */
- TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */
- TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */
- TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART0_IRQn = 37, /*!< USART1 global Interrupt */
- USART1_IRQn = 38, /*!< USART2 global Interrupt */
- USART2_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
- TIMER7_BRK_IRQn = 43, /*!< TIMER7 Break Interrupt */
- TIMER7_UP_IRQn = 44, /*!< TIMER7 Update Interrupt */
- TIMER7_TRG_COM_IRQn = 45, /*!< TIMER7 Trigger and Commutation Interrupt */
- TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare Interrupt */
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
- EXMC_IRQn = 48, /*!< EXMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIMER4_IRQn = 50, /*!< TIMER4 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART3_IRQn = 52, /*!< UART4 global Interrupt */
- UART4_IRQn = 53, /*!< UART5 global Interrupt */
- TIMER5_IRQn = 54, /*!< TIMER5 global Interrupt */
- TIMER6_IRQn = 55, /*!< TIMER6 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
-#endif /* GD32F10X_HD */
-
-#ifdef GD32F10X_XD
- ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break Interrupt and TIMER8 global Interrupt */
- TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update Interrupt and TIMER9 global Interrupt */
- TIMER0_TRG_COM_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt and TIMER10 global interrupt */
- TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */
- TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */
- TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */
- TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
- TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break Interrupt and TIMER11 global Interrupt */
- TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update Interrupt and TIMER12 global Interrupt */
- TIMER7_TRG_COM_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation Interrupt and TIMER13 global interrupt */
- TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare Interrupt */
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
- EXMC_IRQn = 48, /*!< EXMC global Interrupt */
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */
- TIMER4_IRQn = 50, /*!< TIMER4 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIMER5_IRQn = 54, /*!< TIMER5 global Interrupt */
- TIMER6_IRQn = 55, /*!< TIMER6 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
-#endif /* GD32F10X_XD */
-
-#ifdef GD32F10X_CL
- ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break Interrupt and TIMER8 global Interrupt */
- TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update Interrupt and TIMER9 global Interrupt */
- TIMER0_TRG_COM_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt and TIMER10 global interrupt */
- TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */
- TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */
- TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */
- TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
- TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break Interrupt and TIMER11 global Interrupt */
- TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update Interrupt and TIMER12 global Interrupt */
- TIMER7_TRG_COM_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation Interrupt and TIMER13 global interrupt */
- TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare Interrupt */
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
- EXMC_IRQn = 48, /*!< EXMC global Interrupt */
- TIMER4_IRQn = 50, /*!< TIMER4 global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt */
- UART5_IRQn = 53, /*!< UART5 global Interrupt */
- TIMER5_IRQn = 54, /*!< TIMER5 global Interrupt */
- TIMER6_IRQn = 55, /*!< TIMER6 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
- DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
- OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
-#endif /* GD32F10X_CL */
-} IRQn_Type;
-
-
-/**
- * @}
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "core_cm3.h"
-#include "system_gd32f10x.h"
-#include
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum {ERROR = 0, SUCCESS = !ERROR, RESET = 0, SET = !RESET, DISABLE = 0, ENABLE = !DISABLE} TypeState, EventStatus, ControlStatus, FlagStatus, ErrStatus;
-
-#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
-#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
-#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
-#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
-
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef const int32_t sc32; /*!< Read Only */
-typedef const int16_t sc16; /*!< Read Only */
-typedef const int8_t sc8; /*!< Read Only */
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef __I int32_t vsc32; /*!< Read Only */
-typedef __I int16_t vsc16; /*!< Read Only */
-typedef __I int8_t vsc8; /*!< Read Only */
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef const uint32_t uc32; /*!< Read Only */
-typedef const uint16_t uc16; /*!< Read Only */
-typedef const uint8_t uc8; /*!< Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef __I uint32_t vuc32; /*!< Read Only */
-typedef __I uint16_t vuc16; /*!< Read Only */
-typedef __I uint8_t vuc8; /*!< Read Only */
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-typedef struct {
- __IO uint32_t STR;
- __IO uint32_t CTLR1;
- __IO uint32_t CTLR2;
- __IO uint32_t SPT1;
- __IO uint32_t SPT2;
- __IO uint32_t ICOS1;
- __IO uint32_t ICOS2;
- __IO uint32_t ICOS3;
- __IO uint32_t ICOS4;
- __IO uint32_t AWHT;
- __IO uint32_t AWLT;
- __IO uint32_t RSQ1;
- __IO uint32_t RSQ2;
- __IO uint32_t RSQ3;
- __IO uint32_t ISQ;
- __IO uint32_t IDTR1;
- __IO uint32_t IDTR2;
- __IO uint32_t IDTR3;
- __IO uint32_t IDTR4;
- __IO uint32_t RDTR;
-} ADC_TypeDef;
-
-/**
- * @brief Backup Registers
- */
-typedef struct {
- uint32_t RESERVED0;
- __IO uint16_t DR1;
- uint16_t RESERVED1;
- __IO uint16_t DR2;
- uint16_t RESERVED2;
- __IO uint16_t DR3;
- uint16_t RESERVED3;
- __IO uint16_t DR4;
- uint16_t RESERVED4;
- __IO uint16_t DR5;
- uint16_t RESERVED5;
- __IO uint16_t DR6;
- uint16_t RESERVED6;
- __IO uint16_t DR7;
- uint16_t RESERVED7;
- __IO uint16_t DR8;
- uint16_t RESERVED8;
- __IO uint16_t DR9;
- uint16_t RESERVED9;
- __IO uint16_t DR10;
- uint16_t RESERVED10;
- __IO uint16_t RCCR;
- uint16_t RESERVED11;
- __IO uint16_t TPCR;
- uint16_t RESERVED12;
- __IO uint16_t TIER;
- uint16_t RESERVED13[5];
- __IO uint16_t DR11;
- uint16_t RESERVED14;
- __IO uint16_t DR12;
- uint16_t RESERVED15;
- __IO uint16_t DR13;
- uint16_t RESERVED16;
- __IO uint16_t DR14;
- uint16_t RESERVED17;
- __IO uint16_t DR15;
- uint16_t RESERVED18;
- __IO uint16_t DR16;
- uint16_t RESERVED19;
- __IO uint16_t DR17;
- uint16_t RESERVED20;
- __IO uint16_t DR18;
- uint16_t RESERVED21;
- __IO uint16_t DR19;
- uint16_t RESERVED22;
- __IO uint16_t DR20;
- uint16_t RESERVED23;
- __IO uint16_t DR21;
- uint16_t RESERVED24;
- __IO uint16_t DR22;
- uint16_t RESERVED25;
- __IO uint16_t DR23;
- uint16_t RESERVED26;
- __IO uint16_t DR24;
- uint16_t RESERVED27;
- __IO uint16_t DR25;
- uint16_t RESERVED28;
- __IO uint16_t DR26;
- uint16_t RESERVED29;
- __IO uint16_t DR27;
- uint16_t RESERVED30;
- __IO uint16_t DR28;
- uint16_t RESERVED31;
- __IO uint16_t DR29;
- uint16_t RESERVED32;
- __IO uint16_t DR30;
- uint16_t RESERVED33;
- __IO uint16_t DR31;
- uint16_t RESERVED34;
- __IO uint16_t DR32;
- uint16_t RESERVED35;
- __IO uint16_t DR33;
- uint16_t RESERVED36;
- __IO uint16_t DR34;
- uint16_t RESERVED37;
- __IO uint16_t DR35;
- uint16_t RESERVED38;
- __IO uint16_t DR36;
- uint16_t RESERVED39;
- __IO uint16_t DR37;
- uint16_t RESERVED40;
- __IO uint16_t DR38;
- uint16_t RESERVED41;
- __IO uint16_t DR39;
- uint16_t RESERVED42;
- __IO uint16_t DR40;
- uint16_t RESERVED43;
- __IO uint16_t DR41;
- uint16_t RESERVED44;
- __IO uint16_t DR42;
- uint16_t RESERVED45;
-} BKP_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct {
- __IO uint32_t TMIR; /*!< CAN transmit mailbox identifier register, Address offset: 0x180, 0x190, 0x1A0 */
- __IO uint32_t TMPR; /*!< CAN transmit mailbox property register, Address offset: 0x184, 0x194, 0x1A4 */
- __IO uint32_t TMD0R; /*!< CAN transmit mailbox data0 register, Address offset: 0x188, 0x198, 0x1A8 */
- __IO uint32_t TMD1R; /*!< CAN transmit mailbox data1 register, Address offset: 0x18C, 0x19C, 0x1AC */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct {
- __IO uint32_t RFMIR; /*!< CAN receive FIFO mailbox identifier register, Address offset: 0x1B0, 0x1C0 */
- __IO uint32_t RFMPR; /*!< CAN receive FIFO mailbox property register, Address offset: 0x1B4, 0x1C4 */
- __IO uint32_t RFMD0R; /*!< CAN receive FIFO mailbox data0 register, Address offset: 0x1B8, 0x1C8 */
- __IO uint32_t RFMD1R; /*!< CAN receive FIFO mailbox data1 register, Address offset: 0x1BC, 0x1CC */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct {
- __IO uint32_t FD0R; /*!< CAN filter x data 0 register */
- __IO uint32_t FD1R; /*!< CAN filter x data 1 register */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct {
- __IO uint32_t CTLR; /*!< CAN control register, Address offset: 0x00 */
- __IO uint32_t STR; /*!< CAN status register, Address offset: 0x04 */
- __IO uint32_t TSTR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RFR0; /*!< CAN receive FIFO0 register, Address offset: 0x0C */
- __IO uint32_t RFR1; /*!< CAN receive FIFO0 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ER; /*!< CAN error register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88];
- CAN_TxMailBox_TypeDef TxMailBox[3];
- CAN_FIFOMailBox_TypeDef FIFOMailBox[2];
- uint32_t RESERVED1[12];
- __IO uint32_t FCTLR; /*!< CAN filter control register, Address offset: 0x200 */
- __IO uint32_t FMR; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2;
- __IO uint32_t FSR; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3;
- __IO uint32_t FAFR; /*!< CAN filter associated FIFO register, Address offset: 0x214 */
- uint32_t RESERVED4;
- __IO uint32_t FWR; /*!< CAN filter working register, Address offset: 0x21C */
- uint32_t RESERVED5[8];
-#ifndef GD32F10X_CL
- CAN_FilterRegister_TypeDef FilterRegister[14];
-#else
- CAN_FilterRegister_TypeDef FilterRegister[28];
-#endif /* GD32F10X_CL */
-} CAN_TypeDef;
-
-
-/**
- * @brief CRC calculation unit
- */
-typedef struct {
- __IO uint32_t DTR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t FDTR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CTLR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-/**
- * @brief Digital to Analog Converter
- */
-typedef struct {
- __IO uint32_t CTLR;
- __IO uint32_t SWTR;
- __IO uint32_t C1R12DHR;
- __IO uint32_t C1L12DHR;
- __IO uint32_t C1R8DHR;
-
- __IO uint32_t C2R12DHR;
- __IO uint32_t C2L12DHR;
- __IO uint32_t C2R8DHR;
-
- __IO uint32_t DCR12DHR;
- __IO uint32_t DCL12DHR;
- __IO uint32_t DCR8RD;
-
- __IO uint32_t C1ODR;
- __IO uint32_t C2ODR;
-} DAC_TypeDef;
-/**
- * @brief Debug MCU
- */
-typedef struct {
- __IO uint32_t IDR; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CTLR; /*!< Debug MCU CTLR freeze register, Address offset: 0x04 */
-} MCUDBG_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct {
- __IO uint32_t CTLR; /*!< DMA channel x configuration register */
- __IO uint32_t RCNT; /*!< DMA channel x number of data register */
- __IO uint32_t PBAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t MBAR; /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct {
- __IO uint32_t IFR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t ICR; /*!< DMA interrupt flag clear register,Address offset: 0x04 */
-} DMA_TypeDef;
-
-typedef struct {
- __IO uint32_t CFR; /*!< Ethernet MAC configuration register, Address offset: 0x00 */
- __IO uint32_t FRMFR; /*!< Ethernet MAC frame filter register, Address offset: 0x04 */
- __IO uint32_t HLHR; /*!< Ethernet MAC hash list high register, Address offset: 0x08 */
- __IO uint32_t HLLR; /*!< Ethernet MAC hash list low register, Address offset: 0x0C */
- __IO uint32_t PHYAR; /*!< Ethernet MAC PHY address register, Address offset: 0x10 */
- __IO uint32_t PHYDR; /*!< Ethernet MAC PHY data register, Address offset: 0x14 */
- __IO uint32_t FCTLR; /*!< Ethernet MAC flow control register, Address offset: 0x18 */
- __IO uint32_t VLTR; /*!< Ethernet MAC VLAN tag register, Address offset: 0x1C */
- uint32_t RESERVED0[2]; /*!< Reserved, 0x24 */
- __IO uint32_t RWFFR; /*!< Ethernet MAC remote wakeup frame filter register, Address offset: 0x28 */
- __IO uint32_t WUMR; /*!< Ethernet MAC wake up management register, Address offset: 0x2C */
- uint32_t RESERVED1[2]; /*!< Reserved, 0x34 */
- __IO uint32_t ISR; /*!< Ethernet MAC interrupt status register, Address offset: 0x38 */
- __IO uint32_t IMR; /*!< Ethernet MAC interrupt mask register, Address offset: 0x3C */
- __IO uint32_t ADDR0HR; /*!< Ethernet MAC address 0 high register, Address offset: 0x40 */
- __IO uint32_t ADDR0LR; /*!< Ethernet MAC address 0 low register, Address offset: 0x44 */
- __IO uint32_t ADDR1HR; /*!< Ethernet MAC address 1 high register, Address offset: 0x48 */
- __IO uint32_t ADDR1LR; /*!< Ethernet MAC address 1 low register, Address offset: 0x4C */
- __IO uint32_t ADDR2HR; /*!< Ethernet MAC address 2 high register, Address offset: 0x50 */
- __IO uint32_t ADDR2LR; /*!< Ethernet MAC address 2 low register, Address offset: 0x54 */
- __IO uint32_t ADDR3HR; /*!< Ethernet MAC address 3 high register, Address offset: 0x58 */
- __IO uint32_t ADDR3LR; /*!< Ethernet MAC address 3 low register, Address offset: 0x5C */
- uint32_t RESERVED2[1032]; /*!< Reserved, 0x107C */
- __IO uint32_t FCTHR; /*!< Ethernet MAC flow control threshold register, Address offset: 0x1080 */
-} ETH_MAC_TypeDef;
-
-typedef struct {
- __IO uint32_t CTLR; /*!< Ethernet MSC control register, Address offset: 0x100 */
- __IO uint32_t RISR; /*!< Ethernet MSC receive interrupt status register, Address offset: 0x104 */
- __IO uint32_t TISR; /*!< Ethernet MSC transmit interrupt status register, Address offset: 0x108 */
- __IO uint32_t RIMR; /*!< Ethernet MSC receive interrupt mask register, Address offset: 0x10C */
- __IO uint32_t TIMR; /*!< Ethernet MSC transmit interrupt mask register, Address offset: 0x110 */
- uint32_t RESERVED3[14]; /*!< Reserved, 0x148 */
- __IO uint32_t SCCNT; /*!< Ethernet MSC transmitted good frames after a single collision counterregister, Address offset: 0x14C */
- __IO uint32_t MSCCNT; /*!< Ethernet MSC transmitted good frames after more than a single collision counterregister, Address offset: 0x150 */
- uint32_t RESERVED4[5]; /*!< Reserved, 0x164 */
- __IO uint32_t TGFCNT; /*!< Ethernet MSC transmitted good frames counter register, Address offset: 0x168 */
- uint32_t RESERVED5[10]; /*!< Reserved, 0x190 */
- __IO uint32_t RFCECNT; /*!< Ethernet MSC received frames with CRC error counter register, Address offset: 0x194 */
- __IO uint32_t RFAECNT; /*!< Ethernet MSC received frames with alignment error counter register, Address offset: 0x198 */
- uint32_t RESERVED6[10]; /*!< Reserved, 0x1C0 */
- __IO uint32_t RGUFCNT; /*!< Ethernet MSC received good unicast frames counter register, Address offset: 0x1C4 */
-} ETH_MSC_TypeDef;
-
-typedef struct {
- __IO uint32_t TSCTLR; /*!< Ethernet PTP time stamp control register, Address offset: 0x700 */
- __IO uint32_t SSINCR; /*!< Ethernet PTP subsecond increment register, Address offset: 0x704 */
- __IO uint32_t TMSHR; /*!< Ethernet PTP time stamp high register, Address offset: 0x708 */
- __IO uint32_t TMSLR; /*!< Ethernet PTP time stamp low register, Address offset: 0x70C */
- __IO uint32_t TMSHUR; /*!< Ethernet PTP time stamp high update register, Address offset: 0x710 */
- __IO uint32_t TMSLUR; /*!< Ethernet PTP time stamp low update register, Address offset: 0x714 */
- __IO uint32_t TSACNT; /*!< Ethernet PTP time stamp addend register, Address offset: 0x718 */
- __IO uint32_t ETHR; /*!< Ethernet PTP expected time high register, Address offset: 0x71C */
- __IO uint32_t ETLR; /*!< Ethernet PTP expected time low register, Address offset: 0x720 */
-} ETH_PTP_TypeDef;
-
-typedef struct {
- __IO uint32_t BCR; /*!< Ethernet DMA bus control register, Address offset: 0x1000 */
- __IO uint32_t TPER; /*!< Ethernet DMA transmit poll enable register, Address offset: 0x1004 */
- __IO uint32_t RPER; /*!< Ethernet DMA receive poll enable register, Address offset: 0x1008 */
- __IO uint32_t RDTAR; /*!< Ethernet DMA receive descriptor tab address register, Address offset: 0x100C */
- __IO uint32_t TDTAR; /*!< Ethernet DMA transmit descriptor tab address register, Address offset: 0x1010 */
- __IO uint32_t STR; /*!< Ethernet DMA status register, Address offset: 0x1014 */
- __IO uint32_t CTLR; /*!< Ethernet DMA control register, Address offset: 0x1018 */
- __IO uint32_t IER; /*!< Ethernet DMA interrupt enable register, Address offset: 0x1018 */
- __IO uint32_t MFBOCNT; /*!< Ethernet DMA missed frame and buffer overflow counter register, Address offset: 0x101C */
- uint32_t RESERVED7[9]; /*!< Reserved, 0x1044 */
- __IO uint32_t CTDAR; /*!< Ethernet DMA current transmit descriptor address register, Address offset: 0x1048 */
- __IO uint32_t CRDAR; /*!< Ethernet DMA current receive descriptor address register, Address offset: 0x104C */
- __IO uint32_t CTBAR; /*!< Ethernet DMA current transmit buffer address register, Address offset: 0x1050 */
- __IO uint32_t CRBAR; /*!< Ethernet DMA current receive buffer address register, Address offset: 0x1054 */
-} ETH_DMA_Typedef;
-/**
- * @brief External Interrupt/Event Controller
- */
-typedef struct {
- __IO uint32_t IER; /*!GCCR |= SYS_GCCR_HSIEN_SET;
-
- /* Reset SCS[1:0], AHBPS[3:0], APB1PS[2:0],APB2PS[2:0], ADCPS[2:0],CKOTUSEL[2:0] bits */
-#ifdef GD32F10X_CL
- RCC->GCFGR &= SYS_GCFGR_RESET_CL;
-#else
- RCC->GCFGR &= SYS_GCFGR_RESET;
-#endif /* GD32F10X_CL */
-
- /* Reset HSEEN, CKMEN and PLLEN bits */
- RCC->GCCR &= SYS_GCCR_HSEEN_CKMEN_PLLEN_RESET;
-
- /* Reset HSEBPS bit */
- RCC->GCCR &= SYS_GCCR_HSEBPS_RESET;
-
- /* Reset PLLSEL, PLLPREDV and PLLMF[4:0] USBPS/OTGPS bits */
-#ifdef GD32F10X_CL
- RCC->GCFGR &= SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET_CL;
-#else
- RCC->GCFGR &= SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET;
-#endif /* GD32F10X_CL */
-
-#ifdef GD32F10X_CL
- /* Reset PLL2EN and PLL3EN bits */
- RCC->GCCR &= SYS_GCCR_PLL2EN_PLL3EN_RESET;
-
- /* Reset GCFGR2 register */
- RCC->GCFGR2 = SYS_GCFGR2_RESET ;
-
- /* Disable all interrupts and clear flag bits */
- RCC->GCIR = SYS_GCIR_INT_FLAG_RESET_CL;
-#else
- /* Disable all interrupts and clear flag bits */
- RCC->GCIR = SYS_GCIR_INT_FLAG_RESET;
-#endif /* GD32F10X_CL */
-
- /* Configure the System clock frequency, AHB, APB2 and APB1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-}
-
-/**
- * @brief Update SystemCoreClock according to RCC Register Values
- * @note Update the SystemCoreClock variable values, when the core clock (HCLK) changes.
- * Otherwise, any configuration based on this variable will be wrong.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t temp = 0, pllmf = 0, pllmf4 = 0, pllselect = 0, presc = 0;
-
-#ifdef GD32F10X_CL
- uint32_t prediv1select = 0, prediv1factor = 0, prediv2factor = 0, pll2mf = 0;
-#endif /* GD32F10X_CL */
-
- /* Get CK_SYS source -------------------------------------------------------*/
- temp = RCC->GCFGR & RCC_GCFGR_SCSS;
-
- switch (temp) {
- case 0x00: /* HSI used as CK_SYS */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as CK_SYS */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as CK_SYS */
-#ifdef GD32F10X_CL
- /* Get PLL clock source and multiplication factor ----------------------*/
- /* Get PLLMF[3:0] */
- pllmf = RCC->GCFGR & SYS_RCC_GCFGR_PLLMF_3_0;
- /* Get PLLMF[4] */
- pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4;
-
- pllmf4 = ((pllmf4 >> 29) * 15);
-
- pllmf = (pllmf >> 18) + pllmf4;
- if (pllmf != 0x0D) {
- pllmf += 2;
- } else {
- /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmf = 13 / 2;
- }
-
- pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL;
- if (pllselect == 0x00) {
- /* HSI clock divided by 2 selected as PLL clock source */
- SystemCoreClock = (HSI_VALUE >> SYS_HSI_CLOCK_DIVIDED_2) * pllmf;
- } else {
- /* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1select = RCC->GCFGR2 & RCC_GCFGR2_PREDV1SEL;
- prediv1factor = (RCC->GCFGR2 & RCC_GCFGR2_PREDV1) + 1;
-
- if (prediv1select == 0) {
- /* HSE clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmf;
- } else {
- /* PLL2 clock selected as PREDIV1 clock entry */
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->GCFGR2 & RCC_GCFGR2_PREDV2) >> 4) + 1;
- pll2mf = ((RCC->GCFGR2 & RCC_GCFGR2_PLL2MF) >> 8);
- if (pll2mf != 15) {
- pll2mf += 2;
- } else {
- pll2mf += 5;
- }
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mf) / prediv1factor) * pllmf;
- }
- }
-#else
- /* Get PLL clock source and multiplication factor ----------------------*/
- /* Get PLLMF[3:0] */
- pllmf = RCC->GCFGR & SYS_RCC_GCFGR_PLLMF_3_0;
- /* Get PLLMF[4] */
- pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4;
-
- pllmf4 = ((pllmf4 >> 27) * 15);
- pllmf = (pllmf >> 18) + pllmf4 + 2;
-
-
- pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL;
- if (pllselect == 0x00) {
- /* HSI clock divided by 2 selected as PLL clock source */
- SystemCoreClock = (HSI_VALUE >> SYS_HSI_CLOCK_DIVIDED_2) * pllmf;
- } else {
- if ((RCC->GCFGR & RCC_GCFGR_PLLPREDV) != (uint32_t)RESET) {
- /* HSE clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmf;
- } else {
- SystemCoreClock = HSE_VALUE * pllmf;
- }
- }
-#endif
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Get AHB prescaler */
- temp = RCC->GCFGR & RCC_GCFGR_AHBPS;
- temp = temp >> 4;
- presc = AHBPrescTableList[temp];
- /* Get AHB clock frequency */
- SystemCoreClock = SystemCoreClock >> presc;
-}
-
-/**
- * @brief Configure the System clock frequency, AHB, APB2 and APB1 prescalers.
- * @param None
- * @retval None
- */
-
-
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72();
-#elif defined SYSCLK_FREQ_96MHz
- SetSysClockTo96();
-#elif defined SYSCLK_FREQ_108MHz
- SetSysClockTo108();
-#elif defined SYSCLK_FREQ_48MHz_HSI
- SetSysClockTo48HSI();
-#elif defined SYSCLK_FREQ_72MHz_HSI
- SetSysClockTo72HSI();
-#elif defined SYSCLK_FREQ_108MHz_HSI
- SetSysClockTo108HSI();
-#endif
-
-}
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Select HSE as System clock source and configure AHB, APB2
- * and APB1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
- /* Select HSE as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x04) {
- }
- } else {
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Set System clock frequency to 24MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
-
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF6);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV10);
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-#else
- /* PLL configuration: PLLCLK = (HSE /2)* 6 = 24 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF6);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Set System clock frequency to 36MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV10);
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE /2)* 9 = 36 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF9);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Set System clock frequency to 48MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF6);
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
-
-
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-
-#else
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF6);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Set System clock frequency to 56MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF7);
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-
-#else
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF7);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Set System clock frequency to 72MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-
-#else
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF9);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-#elif defined SYSCLK_FREQ_96MHz
-/**
- * @brief Set System clock frequency to 96MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo96(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 12 = 96 MHz */
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF12);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-
-#else
- /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF12);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-
-#elif defined SYSCLK_FREQ_108MHz
-/**
- * @brief Set System clock frequency to 108MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo108(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) {
- HSEStatus = (uint32_t)0x01;
- } else {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01) {
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
-#ifdef GD32F10X_CL
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 108 MHz */
- RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF);
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9);
-
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz */
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 12 MHz */
-
- RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF |
- RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF12 |
- RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5);
-
- /* Enable PLL2 */
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- /* Wait till PLL2 is ready */
- while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) {
- }
-
-#else
- /* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF27);
-
-#endif /* GD32F10X_CL */
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
- } else {
- }
-}
-#elif defined SYSCLK_FREQ_48MHz_HSI
-/**
- * @brief Set System clock frequency to 48MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48HSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
-
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF12);
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
-}
-#elif defined SYSCLK_FREQ_72MHz_HSI
-/**
- * @brief Set System clock frequency to 72MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72HSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
-
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF18);
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
-}
-
-#elif defined SYSCLK_FREQ_108MHz_HSI
-/**
- * @brief Set System clock frequency to 108MHz and configure AHB, APB1, and APB2 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo108HSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/
-
- /* AHB = CK_SYS not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1;
-
- /* APB2 = AHB not divided */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1;
-
- /* APB1 = AHB is divided 2 */
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2;
-
- /* Configure PLLs ------------------------------------------------------*/
-
- /* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF));
- RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF27);
-
- /* Enable PLL */
- RCC->GCCR |= RCC_GCCR_PLLEN;
-
- /* Wait till PLL is ready */
- while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) {
- }
-
- /* Select PLL as system clock source */
- RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS));
- RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) {
- }
-}
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c b/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c
deleted file mode 100644
index f2d043b8d6..0000000000
--- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__((naked));
-uint32_t __get_PSP(void)
-{
- uint32_t result = 0;
-
- __ASM volatile("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r"(result));
- return (result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__((naked));
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r"(topOfProcStack));
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__((naked));
-uint32_t __get_MSP(void)
-{
- uint32_t result = 0;
-
- __ASM volatile("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r"(result));
- return (result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__((naked));
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r"(topOfMainStack));
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result = 0;
-
- __ASM volatile("MRS %0, basepri_max" : "=r"(result));
- return (result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile("MSR basepri, %0" : : "r"(value));
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result = 0;
-
- __ASM volatile("MRS %0, primask" : "=r"(result));
- return (result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile("MSR primask, %0" : : "r"(priMask));
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result = 0;
-
- __ASM volatile("MRS %0, faultmask" : "=r"(result));
- return (result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result = 0;
-
- __ASM volatile("MRS %0, control" : "=r"(result));
- return (result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile("MSR control, %0" : : "r"(control));
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result = 0;
-
- __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result = 0;
-
- __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result = 0;
-
- __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result = 0;
-
- __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result = 0;
-
- __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
- return (result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result = 0;
-
- __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
- return (result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result = 0;
-
- __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
- return (result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result = 0;
-
- __ASM volatile("strexb %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
- return (result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result = 0;
-
- __ASM volatile("strexh %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
- return (result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result = 0;
-
- __ASM volatile("strex %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
- return (result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h b/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h
deleted file mode 100644
index d8ec332d93..0000000000
--- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h
+++ /dev/null
@@ -1,1614 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
- @{
- */
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
-#define __ASM __asm /*!< asm keyword for ARM Compiler */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler */
-#define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
-#define __ASM __asm /*!< asm keyword for IAR Compiler */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-#define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
-#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
-#define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
-#define __ASM __asm /*!< asm keyword for GNU Compiler */
-#define __INLINE inline /*!< inline keyword for GNU Compiler */
-#define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
-#define __ASM __asm /*!< asm keyword for TASKING Compiler */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler */
-#define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TMS470__ )
-#if defined __TI__VFP_SUPPORT____
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-#endif
-
-#include /* standard types definitions */
-#include /* Core Instruction Access */
-#include /* Core Function Access */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM3_REV
-#define __CM3_REV 0x0200
-#warning "__CM3_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT 0
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS 4
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig 0
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define __I volatile /*!< Defines 'read only' permissions */
-#else
-#define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
- struct {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
- uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
- uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
- uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
- struct {
- uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
- struct {
- uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
- uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
- uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
- uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union {
- struct {
- uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct {
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201) /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct {
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
- __O union {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
-#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
-#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if (IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
- } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
- } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if (IRQn < 0) {
- return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
- } /* get priority for Cortex-M system interrupts */
- else {
- return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS)));
- } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits)) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while (1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device.h
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0))) { /* ITM Port #0 enabled */
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar(void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar(void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h
deleted file mode 100644
index 4a6b5d6683..0000000000
--- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h
+++ /dev/null
@@ -1,616 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.01
- * @date 06. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return (__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return (__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return (__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return (__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return (__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return (__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return (__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return (__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return (__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return (__regfpscr);
-#else
- return (0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile("cpsie i");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile("cpsid i");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, control" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile("MSR control, %0" : : "r"(control));
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, ipsr" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, apsr" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, xpsr" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile("MRS %0, psp\n" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack));
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile("MRS %0, msp\n" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack));
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, primask" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile("MSR primask, %0" : : "r"(priMask));
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile("cpsie f");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile("cpsid f");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, basepri_max" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile("MSR basepri, %0" : : "r"(value));
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile("MRS %0, faultmask" : "=r"(result));
- return (result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- __ASM volatile("VMRS %0, fpscr" : "=r"(result));
- return (result);
-#else
- return (0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr));
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h
deleted file mode 100644
index 1c0b6f6b97..0000000000
--- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h
+++ /dev/null
@@ -1,618 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.01
- * @date 06. March 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-#if (__CORTEX_M >= 0x03)
-
- /** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
- #define __RBIT __rbit
-
-
- /** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
- #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
- /** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
- #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
- /** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
- #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
- /** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
- #define __STREXB(value, ptr) __strex(value, ptr)
-
-
- /** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
- #define __STREXH(value, ptr) __strex(value, ptr)
-
-
- /** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
- #define __STREXW(value, ptr) __strex(value, ptr)
-
-
- /** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
- #define __CLREX __clrex
-
-
- /** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
- #define __SSAT __ssat
-
-
- /** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
- #define __USAT __usat
-
-
- /** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
- #define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile("isb");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile("dsb");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile("dmb");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
- uint32_t result;
-
- __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
- __ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2));
- return (op1);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint8_t result;
-
- __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
- return (result);
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint16_t result;
-
- __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
- return (result);
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
- return (result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
- return (result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
- return (result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
- return (result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile("clrex");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint8_t result;
-
- __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value));
- return (result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h
deleted file mode 100644
index b51e596522..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/**
- ******************************************************************************
- * @brief ADC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_ADC_H
-#define __GD32F10X_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum { FALSE = 0, TRUE } BOOL;
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/** @defgroup ADC_Exported_Types
- * @{
- */
-
-/**
- * @brief ADC Init structure definition
- */
-
-typedef struct {
- uint32_t ADC_Trig_External; /*!< AD conversion of regular channels trigger. */
- uint8_t ADC_Channel_Number; /*!< The number of converted ADC channels .
- This parameter must range from 1 to 16. */
- uint32_t ADC_Data_Align; /*!< ADC data alignment,left or right. */
-
- TypeState ADC_Mode_Scan; /*!< AD conversion mode,multichannels mode or Single channel mode.
- This parameter can be ENABLE or DISABLE */
- uint32_t ADC_Mode; /*!< AD operation mode,independent mode or dual mode.
- This parameter can be a value of @ref ADC_mode */
- TypeState ADC_Mode_Continuous; /*!< AD perform mode,continuous mode or single mode.
- This parameter can be ENABLE or DISABLE. */
-} ADC_InitPara;
-
-/**
- * @}
- */
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-
-/** @defgroup ADC_external_trigger
- * @{
- */
-#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC1 ((uint32_t)0x00000000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC2 ((uint32_t)0x00020000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC2 ((uint32_t)0x00060000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T3_TRGO ((uint32_t)0x00080000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T4_CC4 ((uint32_t)0x000A0000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIGGER_MODE_EXT_IT11_T8_TRGO ((uint32_t)0x000C0000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC3 ((uint32_t)0x00040000) /*!< Used in ADC1,ADC2 and ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_NONE ((uint32_t)0x000E0000) /*!< Used in ADC1,ADC2 and ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T3_CC1 ((uint32_t)0x00000000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC3 ((uint32_t)0x00020000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T8_CC1 ((uint32_t)0x00060000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T8_TRGO ((uint32_t)0x00080000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC1 ((uint32_t)0x000A0000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC3 ((uint32_t)0x000C0000) /*!< Only used in ADC3 */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_channels
- * @{
- */
-#define ADC_CHANNEL_0 ((uint8_t)0x00)
-#define ADC_CHANNEL_1 ((uint8_t)0x01)
-#define ADC_CHANNEL_2 ((uint8_t)0x02)
-#define ADC_CHANNEL_3 ((uint8_t)0x03)
-#define ADC_CHANNEL_4 ((uint8_t)0x04)
-#define ADC_CHANNEL_5 ((uint8_t)0x05)
-#define ADC_CHANNEL_6 ((uint8_t)0x06)
-#define ADC_CHANNEL_7 ((uint8_t)0x07)
-#define ADC_CHANNEL_8 ((uint8_t)0x08)
-#define ADC_CHANNEL_9 ((uint8_t)0x09)
-#define ADC_CHANNEL_10 ((uint8_t)0x0A)
-#define ADC_CHANNEL_11 ((uint8_t)0x0B)
-#define ADC_CHANNEL_12 ((uint8_t)0x0C)
-#define ADC_CHANNEL_13 ((uint8_t)0x0D)
-#define ADC_CHANNEL_14 ((uint8_t)0x0E)
-#define ADC_CHANNEL_15 ((uint8_t)0x0F)
-#define ADC_CHANNEL_16 ((uint8_t)0x10)
-#define ADC_CHANNEL_17 ((uint8_t)0x11)
-#define ADC_CHANNEL_TEMPSENSOR ((uint8_t)ADC_CHANNEL_16)
-#define ADC_CHANNEL_VREFINT ((uint8_t)ADC_CHANNEL_17)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_data_align
- * @{
- */
-#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
-#define ADC_DATAALIGN_LEFT ((uint32_t)0x00000800)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_mode
- * @{
- */
-#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
-#define ADC_MODE_REGINSERTSIMULT ((uint32_t)0x00010000)
-#define ADC_MODE_REGSIMULT_ALTERTRIG ((uint32_t)0x00020000)
-#define ADC_MODE_INSERTSIMULT_FASTINTERL ((uint32_t)0x00030000)
-#define ADC_MODE_INSERTSIMULT_SLOWINTERL ((uint32_t)0x00040000)
-#define ADC_MODE_INSERTSIMULT ((uint32_t)0x00050000)
-#define ADC_MODE_REGSIMULT ((uint32_t)0x00060000)
-#define ADC_MODE_FASTINTERL ((uint32_t)0x00070000)
-#define ADC_MODE_SLOWINTERL ((uint32_t)0x00080000)
-#define ADC_MODE_ALTERTRIG ((uint32_t)0x00090000)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_time
- * @{
- */
-#define ADC_SAMPLETIME_1POINT5 ((uint8_t)0x00)
-#define ADC_SAMPLETIME_7POINT5 ((uint8_t)0x01)
-#define ADC_SAMPLETIME_13POINT5 ((uint8_t)0x02)
-#define ADC_SAMPLETIME_28POINT5 ((uint8_t)0x03)
-#define ADC_SAMPLETIME_41POINT5 ((uint8_t)0x04)
-#define ADC_SAMPLETIME_55POINT5 ((uint8_t)0x05)
-#define ADC_SAMPLETIME_71POINT5 ((uint8_t)0x06)
-#define ADC_SAMPLETIME_239POINT5 ((uint8_t)0x07)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_sources_for_inserted_channels_conversion
- * @{
- */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_TRGO ((uint32_t)0x00002000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_CC1 ((uint32_t)0x00003000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T3_CC4 ((uint32_t)0x00004000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_TRGO ((uint32_t)0x00005000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_EXT_IT15_T8_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC1 and ADC2 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_TRIG ((uint32_t)0x00000000) /*!< Used in ADC1,ADC2 and ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_CC4 ((uint32_t)0x00001000) /*!< Used in ADC1,ADC2 and ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_NONE ((uint32_t)0x00007000) /*!< Used in ADC1,ADC2 and ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_CC3 ((uint32_t)0x00002000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC2 ((uint32_t)0x00003000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC4 ((uint32_t)0x00004000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_TRGO ((uint32_t)0x00005000) /*!< Only used in ADC3 */
-#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC3 */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_inserted_channel_selection
- * @{
- */
-#define ADC_INSERTEDCHANNEL_1 ((uint8_t)0x14)
-#define ADC_INSERTEDCHANNEL_2 ((uint8_t)0x18)
-#define ADC_INSERTEDCHANNEL_3 ((uint8_t)0x1C)
-#define ADC_INSERTEDCHANNEL_4 ((uint8_t)0x20)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-#define ADC_ANALOGWATCHDOG_SINGLEREGENABLE ((uint32_t)0x00800200)
-#define ADC_ANALOGWATCHDOG_SINGLEINSERTENABLE ((uint32_t)0x00400200)
-#define ADC_ANALOGWATCHDOG_SINGLEREGORINSERTENABLE ((uint32_t)0x00C00200)
-#define ADC_ANALOGWATCHDOG_ALLREGENABLE ((uint32_t)0x00800000)
-#define ADC_ANALOGWATCHDOG_ALLINSERTENABLE ((uint32_t)0x00400000)
-#define ADC_ANALOGWATCHDOG_ALLREGALLINSERTENABLE ((uint32_t)0x00C00000)
-#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-#define ADC_INT_EOC ((uint16_t)0x0220)
-#define ADC_INT_AWE ((uint16_t)0x0140)
-#define ADC_INT_EOIC ((uint16_t)0x0480)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-#define ADC_FLAG_AWE ((uint8_t)0x01)
-#define ADC_FLAG_EOC ((uint8_t)0x02)
-#define ADC_FLAG_EOIC ((uint8_t)0x04)
-#define ADC_FLAG_STIC ((uint8_t)0x08)
-#define ADC_FLAG_STRC ((uint8_t)0x10)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Exported_Functions
- * @{
- */
-void ADC_DeInit(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct);
-void ADC_Init(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct);
-void ADC_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-void ADC_DMA_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-void ADC_INTConfig(ADC_TypeDef *ADCx, uint16_t ADC_INT, TypeState NewValue);
-void ADC_Calibration(ADC_TypeDef *ADCx);
-void ADC_SoftwareStartConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-TypeState ADC_GetSoftwareStartConvBitState(ADC_TypeDef *ADCx);
-void ADC_DiscModeChannelCount_Config(ADC_TypeDef *ADCx, uint8_t Number);
-void ADC_DiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-void ADC_RegularChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_ExternalTrigConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
-uint32_t ADC_GetDualModeConversionValue(void);
-void ADC_AutoInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-void ADC_InsertedDiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-void ADC_ExternalTrigInsertedConv_Config(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInsertConv);
-void ADC_ExternalTrigInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-void ADC_SoftwareStartInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
-TypeState ADC_GetSoftwareStartInsertedConvCmdBitState(ADC_TypeDef *ADCx);
-void ADC_InsertedChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InsertedSequencerLength_Config(ADC_TypeDef *ADCx, uint8_t Length);
-void ADC_SetInsertedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel, uint16_t Offset);
-uint16_t ADC_GetInsertedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel);
-void ADC_AnalogWatchdog_Enable(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholds_Config(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
-void ADC_TempSensorVrefint_Enable(TypeState NewValue);
-TypeState ADC_GetBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
-void ADC_ClearBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
-TypeState ADC_GetIntState(ADC_TypeDef *ADCx, uint16_t ADC_INT);
-void ADC_ClearIntBitState(ADC_TypeDef *ADCx, uint16_t ADC_INT);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_ADC_H */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h
deleted file mode 100644
index 72784b9557..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- ******************************************************************************
- * @brief BKP header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_BKP_H
-#define __GD32F10X_BKP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup BKP
- * @{
- */
-
-/** @defgroup BKP_Exported_Constants
- * @{
- */
-
-/** @defgroup TAMPER_pin_active_level
- * @{
- */
-#define BKP_TPAL_HIGH ((uint16_t)0x0000)
-#define BKP_TPAL_LOW ((uint16_t)0x0002)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_output_on_the_TAMPER_pin
- * @{
- */
-#define BKP_RTCOUTPUT_NULL ((uint16_t)0x0000)
-#define BKP_RTCOUTPUT_CLKCAL ((uint16_t)0x0080)
-#define BKP_RTCOUTPUT_ALARM ((uint16_t)0x0100)
-#define BKP_RTCOUTPUT_SECOND ((uint16_t)0x0300)
-
-/**
- * @}
- */
-
-/** @defgroup Backup_Data_Register
- * @{
- */
-#define BKP_DR1 ((uint16_t)0x0004)
-#define BKP_DR2 ((uint16_t)0x0008)
-#define BKP_DR3 ((uint16_t)0x000C)
-#define BKP_DR4 ((uint16_t)0x0010)
-#define BKP_DR5 ((uint16_t)0x0014)
-#define BKP_DR6 ((uint16_t)0x0018)
-#define BKP_DR7 ((uint16_t)0x001C)
-#define BKP_DR8 ((uint16_t)0x0020)
-#define BKP_DR9 ((uint16_t)0x0024)
-#define BKP_DR10 ((uint16_t)0x0028)
-#define BKP_DR11 ((uint16_t)0x0040)
-#define BKP_DR12 ((uint16_t)0x0044)
-#define BKP_DR13 ((uint16_t)0x0048)
-#define BKP_DR14 ((uint16_t)0x004C)
-#define BKP_DR15 ((uint16_t)0x0050)
-#define BKP_DR16 ((uint16_t)0x0054)
-#define BKP_DR17 ((uint16_t)0x0058)
-#define BKP_DR18 ((uint16_t)0x005C)
-#define BKP_DR19 ((uint16_t)0x0060)
-#define BKP_DR20 ((uint16_t)0x0064)
-#define BKP_DR21 ((uint16_t)0x0068)
-#define BKP_DR22 ((uint16_t)0x006C)
-#define BKP_DR23 ((uint16_t)0x0070)
-#define BKP_DR24 ((uint16_t)0x0074)
-#define BKP_DR25 ((uint16_t)0x0078)
-#define BKP_DR26 ((uint16_t)0x007C)
-#define BKP_DR27 ((uint16_t)0x0080)
-#define BKP_DR28 ((uint16_t)0x0084)
-#define BKP_DR29 ((uint16_t)0x0088)
-#define BKP_DR30 ((uint16_t)0x008C)
-#define BKP_DR31 ((uint16_t)0x0090)
-#define BKP_DR32 ((uint16_t)0x0094)
-#define BKP_DR33 ((uint16_t)0x0098)
-#define BKP_DR34 ((uint16_t)0x009C)
-#define BKP_DR35 ((uint16_t)0x00A0)
-#define BKP_DR36 ((uint16_t)0x00A4)
-#define BKP_DR37 ((uint16_t)0x00A8)
-#define BKP_DR38 ((uint16_t)0x00AC)
-#define BKP_DR39 ((uint16_t)0x00B0)
-#define BKP_DR40 ((uint16_t)0x00B4)
-#define BKP_DR41 ((uint16_t)0x00B8)
-#define BKP_DR42 ((uint16_t)0x00BC)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup BKP_Exported_Functions
- * @{
- */
-void BKP_DeInit(void);
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT);
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
-void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue);
-void BKP_TamperINT_Enable(TypeState NewValue);
-TypeState BKP_GetBitState(void);
-void BKP_ClearBitState(void);
-TypeState BKP_GetIntBitState(void);
-void BKP_ClearIntBitState(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_BKP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h
deleted file mode 100644
index a13a612566..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h
+++ /dev/null
@@ -1,512 +0,0 @@
-/**
- ******************************************************************************
- * @brief CAN header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_CAN_H
-#define __GD32F10X_CAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/** @defgroup CAN_Exported_Types
- * @{
- */
-
-/**
- * @brief CAN Initial Parameters
- */
-
-typedef struct {
- uint16_t CAN_Prescaler; /*!< Baud rate prescaler.It can be 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Set the CAN operating mode. */
-
- uint8_t CAN_SJW; /*!< Set Resynchronization jump width */
-
- uint8_t CAN_BS1; /*!< Set time segment 1. */
-
- uint8_t CAN_BS2; /*!< Set time segment 2. */
-
- TypeState CAN_TTC; /*!< Set time triggered communication mode. */
-
- TypeState CAN_ABOR; /*!< Set automatic bus-off recovery. */
-
- TypeState CAN_AWK; /*!< Set the automatic wake-up mode. */
-
- TypeState CAN_ARD; /*!< Set the automatic retransmission mode. */
-
- TypeState CAN_RFOD; /*!< Receive FIFO overwrite mode. */
-
- TypeState CAN_TFO; /*!< Set the Transmit FIFO order. */
-} CAN_InitPara;
-
-/**
- * @brief CAN filter Initial Parameters
- */
-
-typedef struct {
- uint16_t CAN_FilterListHigh; /*!< the filter List number.
- If the filter scale is 32-bit,the filter list number is MSBs.
- If the filter scale is 16-bit,the filter list number is first one.
- This value can take from 0x0000 to 0xFFFF */
-
- uint16_t CAN_FilterListLow; /*!< the filter List number.
- If the filter scale is 32-bit,the filter list number is LSBs.
- If the filter scale is 16-bit,the filter list number is second one.
- This value can take from 0x0000 to 0xFFFF */
-
- uint16_t CAN_FilterMaskListHigh; /*!< the filter mask number or list number,according to the filter mode.
- If the filter scale is 32-bit,the filter mask number or list number is MSBs.
- If the filter scale is 16-bit,the filter mask number or list number is first one.
- This value can take from 0x0000 to 0xFFFF */
-
- uint16_t CAN_FilterMaskListLow; /*!< the filter mask number or list number,according to the filter mode.
- If the filter scale is 32-bit,the filter mask number or list number is LSBs.
- If the filter scale is 16-bit,the filter mask number or list number is second one.
- This value can take from 0x0000 to 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssociation; /*!< Set the FIFO (0 or 1) which will be associated with the filter. */
-
- uint8_t CAN_FilterNumber; /*!< Set the which filter to be initialized. It ranges from 0 to 13 or 0 to 27(in GD32F10X_CL). */
-
- uint8_t CAN_FilterMode; /*!< Set the filter mode to be identifier mask or identifier list. */
-
- uint8_t CAN_FilterScale; /*!< Set the filter scale. */
-
- TypeState CAN_FilterWork; /*!< Set the filter to work or not. */
-} CAN_FilterInitPara;
-
-/**
- * @brief CAN Tx message structure definition
- */
-
-typedef struct {
- uint32_t StdId; /*!< Set the standard format frame identifier.
- This value can take from 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Set the extended format frame identifier.
- This value can take from 0 to 0x1FFFFFFF. */
-
- uint8_t FF; /*!< Set the format of Frame , Standard or extended Frame
- for the message that will be transmitted. */
-
- uint8_t FT; /*!< Set the type of frame, Data or remote
- for the message that will be transmitted. */
-
- uint8_t DLC; /*!< Set the length of the frame that will be transmitted.
- This value can take from 0 to 8 */
-
- uint8_t Data[8]; /*!< store the data that will be transmitted.
- This value can take from 0 to 0xFF. */
-} CanTxMessage;
-
-/**
- * @brief CAN Rx message structure definition
- */
-
-typedef struct {
- uint32_t StdId; /*!< Set the standard format frame identifier.
- This value can take from 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Set the extended format frame identifier.
- This value can take from 0 to 0x1FFFFFFF. */
-
- uint8_t FF; /*!< Set the format of Frame , Standard or extended Frame
- for the message that will be received. */
-
- uint8_t FT; /*!< Set the type of frame, Data or remote
- for the message that will be received. */
-
- uint8_t DLC; /*!< Set the length of the frame that will be received.
- This value can take from 0 to 8 */
-
- uint8_t Data[8]; /*!< store the data that will be received.
- This value can take from 0 to 0xFF. */
-
- uint8_t FI; /*!< The index of the filter by which the frame is passed..
- This value can take from 0 to 0xFF */
-} CanRxMessage;
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-#define CAN_INITSTATE_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_INITSTATE_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Communication_Mode
- * @{
- */
-#define CAN_MODE_NORMAL ((uint8_t)0x00) /*!< Normal communication mode */
-#define CAN_MODE_LOOPBACK ((uint8_t)0x01) /*!< Loopback communication mode */
-#define CAN_MODE_SILENT ((uint8_t)0x02) /*!< Silent communication mode */
-#define CAN_MODE_SILENT_LOOPBACK ((uint8_t)0x03) /*!< Loopback and silent communication mode */
-
-/**
- * @}
- */
-
-
-/**
- * @defgroup CAN_Working_Mode
- * @{
- */
-#define CAN_WORKINGMODE_INITIAL ((uint8_t)0x00) /*!< Initial working mode */
-#define CAN_WORKINGMODE_NORMAL ((uint8_t)0x01) /*!< Normal working mode */
-#define CAN_WORKINGMODE_SLEEP ((uint8_t)0x02) /*!< Sleep working mode */
-
-/**
- * @}
- */
-
-
-/**
- * @defgroup CAN_Mode_State
- * @{
- */
-#define CAN_MODESTATE_FAILED ((uint8_t)0x00) /*!< CAN entering the specified mode failed */
-#define CAN_MODESTATE_SUCCESS ((uint8_t)!CAN_MODESTATE_FAILED) /*!< CAN entering the specified mode Succeed */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Synchronisation_Jump_Width
- * @{
- */
-#define CAN_SJW_1TQ ((uint8_t)0x00) /*!< 1 time quanta */
-#define CAN_SJW_2TQ ((uint8_t)0x01) /*!< 2 time quanta */
-#define CAN_SJW_3TQ ((uint8_t)0x02) /*!< 3 time quanta */
-#define CAN_SJW_4TQ ((uint8_t)0x03) /*!< 4 time quanta */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Time_Quanta_In_Bit_Segment_1
- * @{
- */
-#define CAN_BS1_1TQ ((uint8_t)0x00) /*!< 1 time quanta */
-#define CAN_BS1_2TQ ((uint8_t)0x01) /*!< 2 time quanta */
-#define CAN_BS1_3TQ ((uint8_t)0x02) /*!< 3 time quanta */
-#define CAN_BS1_4TQ ((uint8_t)0x03) /*!< 4 time quanta */
-#define CAN_BS1_5TQ ((uint8_t)0x04) /*!< 5 time quanta */
-#define CAN_BS1_6TQ ((uint8_t)0x05) /*!< 6 time quanta */
-#define CAN_BS1_7TQ ((uint8_t)0x06) /*!< 7 time quanta */
-#define CAN_BS1_8TQ ((uint8_t)0x07) /*!< 8 time quanta */
-#define CAN_BS1_9TQ ((uint8_t)0x08) /*!< 9 time quanta */
-#define CAN_BS1_10TQ ((uint8_t)0x09) /*!< 10 time quanta */
-#define CAN_BS1_11TQ ((uint8_t)0x0A) /*!< 11 time quanta */
-#define CAN_BS1_12TQ ((uint8_t)0x0B) /*!< 12 time quanta */
-#define CAN_BS1_13TQ ((uint8_t)0x0C) /*!< 13 time quanta */
-#define CAN_BS1_14TQ ((uint8_t)0x0D) /*!< 14 time quanta */
-#define CAN_BS1_15TQ ((uint8_t)0x0E) /*!< 15 time quanta */
-#define CAN_BS1_16TQ ((uint8_t)0x0F) /*!< 16 time quanta */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Time_Quanta_In_Bit_Segment_2
- * @{
- */
-#define CAN_BS2_1TQ ((uint8_t)0x00) /*!< 1 time quanta */
-#define CAN_BS2_2TQ ((uint8_t)0x01) /*!< 2 time quanta */
-#define CAN_BS2_3TQ ((uint8_t)0x02) /*!< 3 time quanta */
-#define CAN_BS2_4TQ ((uint8_t)0x03) /*!< 4 time quanta */
-#define CAN_BS2_5TQ ((uint8_t)0x04) /*!< 5 time quanta */
-#define CAN_BS2_6TQ ((uint8_t)0x05) /*!< 6 time quanta */
-#define CAN_BS2_7TQ ((uint8_t)0x06) /*!< 7 time quanta */
-#define CAN_BS2_8TQ ((uint8_t)0x07) /*!< 8 time quanta */
-
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Filter_Mode
- * @{
- */
-#define CAN_FILTERMODE_MASK ((uint8_t)0x00) /*!< mask mode */
-#define CAN_FILTERMODE_LIST ((uint8_t)0x01) /*!< List mode */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Filter_Scale
- * @{
- */
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Filter_FIFO
- * @{
- */
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter associated with FIFO0 */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter associated with FIFO1 */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Format_Frame
- * @{
- */
-#define CAN_FF_STANDARD ((uint32_t)0x00000000) /*!< Standard format frame */
-#define CAN_FF_EXTENDED ((uint32_t)0x00000004) /*!< Extended format frame */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Frame_Type
- * @{
- */
-#define CAN_FT_DATA ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_FT_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Transmit_State
- * @{
- */
-#define CAN_TXSTATE_FAILED ((uint8_t)0x00)/*!< CAN transmitted failure */
-#define CAN_TXSTATE_OK ((uint8_t)0x01) /*!< CAN transmitted success */
-#define CAN_TXSTATE_PENDING ((uint8_t)0x02) /*!< CAN transmitted pending */
-#define CAN_TXSTATE_NOMAILBOX ((uint8_t)0x04) /*!< No empty mailbox to be used for CAN */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Receive_FIFO_Number_Constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< Use CAN FIFO 0 to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< Use CAN FIFO 1 to receive */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Sleep_Constants
- * @{
- */
-#define CAN_SLEEP_FAILED ((uint8_t)0x00) /*!< CAN entered the sleep mode failed */
-#define CAN_SLEEP_OK ((uint8_t)0x01) /*!< CAN entered the sleep mode succeeded */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Wake_Wp_Constants
- * @{
- */
-#define CAN_WAKEUP_FAILED ((uint8_t)0x00) /*!< CAN leaved the sleep mode failed */
-#define CAN_WAKEUP_OK ((uint8_t)0x01) /*!< CAN leaved the sleep mode succeeded */
-
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_Error_Type_Constants
- * @{
- */
-#define CAN_ERRORTYPE_NOERR ((uint8_t)0x00) /*!< No Error */
-#define CAN_ERRORTYPE_STUFFERR ((uint8_t)0x10) /*!< Stuff Error */
-#define CAN_ERRORTYPE_FORMERR ((uint8_t)0x20) /*!< Form Error */
-#define CAN_ERRORTYPE_ACKERR ((uint8_t)0x30) /*!< Acknowledgment Error */
-#define CAN_ERRORTYPE_BITRECESSIVEERR ((uint8_t)0x40) /*!< Bit Recessive Error */
-#define CAN_ERRORTYPE_BITDOMINANTERR ((uint8_t)0x50) /*!< Bit Dominant Error */
-#define CAN_ERRORTYPE_CRCERR ((uint8_t)0x60) /*!< CRC Error */
-#define CAN_ERRORTYPE_SOFTWARESETERR ((uint8_t)0x70) /*!< Set by software */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* The flag value of 0x3XXXXXXX is used with CAN_GetBitState()and CAN_ClearBitState() functions. */
-/* The flag value of 0x1XXXXXXX is only used with CAN_GetBitState() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_MTF0 ((uint32_t)0x38000001) /*!< Mailbox 0 transmit finished Flag */
-#define CAN_FLAG_MTF1 ((uint32_t)0x38000100) /*!< Mailbox 1 transmit finished Flag */
-#define CAN_FLAG_MTF2 ((uint32_t)0x38010000) /*!< Mailbox 2 transmit finished Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_RFL0 ((uint32_t)0x12000003) /*!< the length of the receive FIFO0 Flag */
-#define CAN_FLAG_RFF0 ((uint32_t)0x32000008) /*!< Receive FIFO 0 full Flag */
-#define CAN_FLAG_RFO0 ((uint32_t)0x32000010) /*!< Receive FIFO 0 overfull Flag */
-#define CAN_FLAG_RFL1 ((uint32_t)0x14000003) /*!< the length of the receive FIFO1 Flag */
-#define CAN_FLAG_RFF1 ((uint32_t)0x34000008) /*!< Receive FIFO 1 full Flag */
-#define CAN_FLAG_RFO1 ((uint32_t)0x34000010) /*!< Receive FIFO 1 overfull Flag */
-
-/* Working Mode Flags, in CAN status register */
-#define CAN_FLAG_WU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLP ((uint32_t)0x31000012) /*!< Sleep working state Flag */
-
-/* Error Flags, in CAN error register */
-#define CAN_FLAG_WE ((uint32_t)0x10F00001) /*!< Warning error Flag */
-#define CAN_FLAG_PE ((uint32_t)0x10F00002) /*!< Passive error Flag */
-#define CAN_FLAG_BOE ((uint32_t)0x10F00004) /*!< Bus-off error Flag */
-#define CAN_FLAG_ET ((uint32_t)0x30F00070) /*!< Error type Flag */
-
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_INT_RFNE0 ((uint32_t)0x00000002) /*!< FIFO 0 not empty interrupt */
-#define CAN_INT_RFF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_INT_RFO0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_INT_RFNE1 ((uint32_t)0x00000010) /*!< FIFO 1 not empty interrupt*/
-#define CAN_INT_RFF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_INT_RFO1 ((uint32_t)0x00000040) /*!< FIFO 1 overfull Interrupt*/
-
-/* Working Mode Interrupts */
-#define CAN_INT_WU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_INT_SLP ((uint32_t)0x00020000) /*!< Sleep Interrupt*/
-
-/* Error Interrupts */
-#define CAN_INT_WE ((uint32_t)0x00000100) /*!< Warning error Interrupt*/
-#define CAN_INT_PE ((uint32_t)0x00000200) /*!< Passive error Interrupt*/
-#define CAN_INT_BOE ((uint32_t)0x00000400) /*!< Bus-off error Interrupt*/
-#define CAN_INT_ET ((uint32_t)0x00000800) /*!< error type Interrupt*/
-#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-#define CAN_INT_MTF0 CAN_INT_TME
-#define CAN_INT_MTF1 CAN_INT_TME
-#define CAN_INT_MTF2 CAN_INT_TME
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Legacy
- * @{
- */
-#define CANINITFAILED CAN_INITSTATE_FAILED
-#define CANINITOK CAN_INITSTATE_SUCCESS
-#define CAN_FILTERFIFO0 CAN_FILTER_FIFO0
-#define CAN_FILTERFIFO1 CAN_FILTER_FIFO1
-#define CAN_FF_STD CAN_FF_STANDARD
-#define CAN_FF_EXT CAN_FF_EXTENDED
-//#define CAN_FT_DATA CAN_FT_DATA
-//#define CAN_FT_REMOTE CAN_FT_REMOTE
-#define CANTXFAILE CAN_TXSTATE_FAILED
-#define CANTXOK CAN_TXSTATE_OK
-#define CANTXPENDING CAN_TXSTATE_PENDING
-#define CAN_NO_MB CAN_TXSTATE_NOMAILBOX
-#define CANSLEEPFAILED CAN_SLEEP_FAILED
-#define CANSLEEPOK CAN_SLEEP_OK
-#define CANWAKEUPFAILED CAN_WAKEUP_FAILED
-#define CANWAKEUPOK CAN_WAKEUP_OK
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Exported_Functions
- * @{
- */
-void CAN_DeInit(CAN_TypeDef *CANx);
-uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitPara *CAN_InitParaStruct);
-void CAN_FilterInit(CAN_FilterInitPara *CAN_FilterInitParaStruct);
-void CAN_StructInit(CAN_InitPara *CAN_InitParaStruct);
-void CAN_HeaderBank(uint8_t CAN_HeaderBankNumber);
-void CAN_DebugFreeze(CAN_TypeDef *CANx, TypeState NewValue);
-void CAN_TimeTrigComMode_Enable(CAN_TypeDef *CANx, TypeState NewValue);
-
-/* Transmit functions */
-uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMessage *TxMessage);
-uint8_t CAN_TransmitState(CAN_TypeDef *CANx, uint8_t TransmitMailbox);
-void CAN_StopTransmit(CAN_TypeDef *CANx, uint8_t Mailbox);
-
-/* Receive functions */
-void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMessage *RxMessage);
-void CAN_FIFODequeue(CAN_TypeDef *CANx, uint8_t FIFONumber);
-uint8_t CAN_MessageLength(CAN_TypeDef *CANx, uint8_t FIFONumber);
-
-
-/* Working modes functions */
-uint8_t CAN_WorkingMode(CAN_TypeDef *CANx, uint8_t CAN_WorkingMode);
-uint8_t CAN_EnterSleep(CAN_TypeDef *CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef *CANx);
-
-/* Error management functions */
-uint8_t CAN_GetErrorType(CAN_TypeDef *CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx);
-uint8_t CAN_GetTransmitErrorCounter(CAN_TypeDef *CANx);
-
-/* Interrupts and flags management functions */
-void CAN_INTConfig(CAN_TypeDef *CANx, uint32_t CAN_INT, TypeState NewValue);
-TypeState CAN_GetBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG);
-void CAN_ClearBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG);
-TypeState CAN_GetIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT);
-void CAN_ClearIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT);
-static TypeState CheckINTState(uint32_t CAN_Reg, uint32_t Int_Bit);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10x_CAN_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h
deleted file mode 100644
index b4cd5d7e3b..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- ******************************************************************************
- * @brief CRC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_CRC_H
-#define __GD32F10X_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/** @defgroup CRC_Exported_Functions
- * @{
- */
-
-void CRC_ResetDTR(void);
-uint32_t CRC_CalcSingleData(uint32_t CRC_data);
-uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length);
-uint32_t CRC_ReadDTR(void);
-void CRC_WriteFDTR(uint8_t CRC_fdtr);
-uint8_t CRC_ReadFDTR(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_CRC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h
deleted file mode 100644
index 95eccc7b00..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/**
- ******************************************************************************
- * @brief DAC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_DAC_H
-#define __GD32F10X_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/** @defgroup DAC_Exported_Types
- * @{
- */
-
-/**
- * @brief DAC Init structure definition
- */
-typedef struct {
- uint32_t DAC_Trigger; /*!< External trigger of the selected DAC channel.
- This parameter can be a value of @ref DAC_Trigger */
- uint32_t DAC_WaveType; /*!< Wave type of the DAC channel, noise waves or triangle waves.
- This parameter can be a value of @ref DAC_wave_type */
- uint32_t DAC_LFSRNoise_AmplitudeTriangle; /*!< The LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrnoise_amplitudetriangle */
- uint32_t DAC_OutputBuffer; /*!< whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_OutputBuffer */
-} DAC_InitPara;
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-/** @defgroup DAC_Trigger
- * @{
- */
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< no trigger */
-#define DAC_TRIGGER_T2_TRIG ((uint32_t)0x00000024) /*!< TIMER2 TRIG */
-#define DAC_TRIGGER_T3_TRIG ((uint32_t)0x0000000C) /*!< TIMER3 TRIG */
-#define DAC_TRIGGER_T4_TRIG ((uint32_t)0x0000002C) /*!< TIMER4 TRIG */
-#define DAC_TRIGGER_T5_TRIG ((uint32_t)0x0000001C) /*!< TIMER5 TRIG */
-#define DAC_TRIGGER_T6_TRIG ((uint32_t)0x00000004) /*!< TIMER6 TRIG */
-#define DAC_TRIGGER_T7_TRIG ((uint32_t)0x00000014) /*!< TIMER7 TRIG */
-#define DAC_TRIGGER_T8_TRIG ((uint32_t)0x0000000C) /*!< TIMER8 TRIG */
-#define DAC_TRIGGER_T15_TRIG ((uint32_t)0x0000001C) /*!< TIMER15 TRIG */
-#define DAC_TRIGGER_EXTI_LINE9 ((uint32_t)0x00000034) /*!< EXTI Line9 event */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)0x0000003C) /*!< software trigger */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_type
- * @{
- */
-#define DAC_WAVEGENE_NONE ((uint32_t)0x00000000)
-#define DAC_WAVEGENE_NOISE ((uint32_t)0x00000040)
-#define DAC_WAVEGENE_TRIANGLE ((uint32_t)0x00000080)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrnoise_amplitudetriangle
- * @{
- */
-#define DAC_LFSR_BIT0 ((uint32_t)0x00000000) /*!< LFSR bit0 for noise wave generation */
-#define DAC_LFSR_BITS1_0 ((uint32_t)0x00000100) /*!< LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSR_BITS2_0 ((uint32_t)0x00000200) /*!< LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSR_BITS3_0 ((uint32_t)0x00000300) /*!< LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSR_BITS4_0 ((uint32_t)0x00000400) /*!< LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSR_BITS5_0 ((uint32_t)0x00000500) /*!< LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSR_BITS6_0 ((uint32_t)0x00000600) /*!< LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSR_BITS7_0 ((uint32_t)0x00000700) /*!< LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSR_BITS8_0 ((uint32_t)0x00000800) /*!< LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSR_BITS9_0 ((uint32_t)0x00000900) /*!< LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSR_BITS10_0 ((uint32_t)0x00000A00) /*!< LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSR_BITS11_0 ((uint32_t)0x00000B00) /*!< LFSR bit[11:0] for noise wave generation */
-#define DAC_AMPLITUDETRIANGLE_1 ((uint32_t)0x00000000) /*!< max triangle amplitude: 1 */
-#define DAC_AMPLITUDETRIANGLE_3 ((uint32_t)0x00000100) /*!< max triangle amplitude: 3 */
-#define DAC_AMPLITUDETRIANGLE_7 ((uint32_t)0x00000200) /*!< max triangle amplitude: 7 */
-#define DAC_AMPLITUDETRIANGLE_15 ((uint32_t)0x00000300) /*!< max triangle amplitude: 15 */
-#define DAC_AMPLITUDETRIANGLE_31 ((uint32_t)0x00000400) /*!< max triangle amplitude: 31 */
-#define DAC_AMPLITUDETRIANGLE_63 ((uint32_t)0x00000500) /*!< max triangle amplitude: 63 */
-#define DAC_AMPLITUDETRIANGLE_127 ((uint32_t)0x00000600) /*!< max triangle amplitude: 127 */
-#define DAC_AMPLITUDETRIANGLE_255 ((uint32_t)0x00000700) /*!< max triangle amplitude: 255 */
-#define DAC_AMPLITUDETRIANGLE_511 ((uint32_t)0x00000800) /*!< max triangle amplitude: 511 */
-#define DAC_AMPLITUDETRIANGLE_1023 ((uint32_t)0x00000900) /*!< max triangle amplitude: 1023 */
-#define DAC_AMPLITUDETRIANGLE_2047 ((uint32_t)0x00000A00) /*!< max triangle amplitude: 2047 */
-#define DAC_AMPLITUDETRIANGLE_4095 ((uint32_t)0x00000B00) /*!< max triangle amplitude: 4095 */
-
-/**
- * @}
- */
-/** @defgroup DAC_OutputBuffer
- * @{
- */
-#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
-#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)0x00000002)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignment
- * @{
- */
-#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @{
- */
-#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
-#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-#define DAC_INT_DMAUDR ((uint32_t)0x00002000)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup DAC_Exported_Functions
- * @{
- */
-void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct);
-void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct);
-void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue);
-void DAC_IntConfig(uint32_t DAC_Channel, TypeState NewValue);
-void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue);
-void DAC_DualSoftwareTrigger_Enable(TypeState NewValue);
-void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_DAC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h
deleted file mode 100644
index 82eeba851c..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/**
- ******************************************************************************
- * @brief DMA header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_DMA_H
-#define __GD32F10X_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/** @defgroup DMA_Exported_Types
- * @{
- */
-
-/**
- * @brief DMA Initial Parameters
- */
-
-typedef struct {
- uint32_t DMA_PeripheralBaseAddr; /*!< The base address of the peripheral. */
-
- uint32_t DMA_MemoryBaseAddr; /*!< The base address of the memory. */
-
- uint32_t DMA_DIR; /*!< The direction of data transmission.
- detailed in @ref DMA_data_transfer_direction */
-
- uint32_t DMA_BufferSize; /*!< The buffer size of data transmission. */
-
- uint32_t DMA_PeripheralInc; /*!< The incremented_mode of the Peripheral address register.
- detailed in @ref DMA_peripheral_Address_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< The incremented_mode of the memory address register.
- detailed in @ref DMA_memory_Address_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< The data transmission width of Peripheral.
- detailed in @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< The data transmission width of Memory.
- detailed in @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< The mode of circular transmission.
- detailed in @ref DMA_circular_normal_mode */
-
- uint32_t DMA_Priority; /*!< The software priority for the DMAy Channelx.
- detailed in @ref DMA_priority_level */
- uint32_t DMA_MTOM; /*!< The mode of memory-to-memory transfer.
- detailed in @ref DMA_memory_to_memory */
-} DMA_InitPara;
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-
-#define DMA_DIR_PERIPHERALDST DMA_CTLR_DIR
-#define DMA_DIR_PERIPHERALSRC ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_Address_Increasing_mode
- * @{
- */
-
-#define DMA_PERIPHERALINC_ENABLE DMA_CTLR_PNAGA
-#define DMA_PERIPHERALINC_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_Address_Increasing_mode
- * @{
- */
-
-#define DMA_MEMORYINC_ENABLE DMA_CTLR_MNAGA
-#define DMA_MEMORYINC_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-
-#define DMA_PERIPHERALDATASIZE_BYTE ((uint32_t)0x00000000)
-#define DMA_PERIPHERALDATASIZE_HALFWORD DMA_CTLR_PSIZE_0
-#define DMA_PERIPHERALDATASIZE_WORD DMA_CTLR_PSIZE_1
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-
-#define DMA_MEMORYDATASIZE_BYTE ((uint32_t)0x00000000)
-#define DMA_MEMORYDATASIZE_HALFWORD DMA_CTLR_MSIZE_0
-#define DMA_MEMORYDATASIZE_WORD DMA_CTLR_MSIZE_1
-/**
- * @}
- */
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-
-#define DMA_MODE_CIRCULAR DMA_CTLR_CIRC
-#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup DMA_priority_level
- * @{
- */
-
-#define DMA_PRIORITY_VERYHIGH DMA_CTLR_PRIO
-#define DMA_PRIORITY_HIGH DMA_CTLR_PRIO_1
-#define DMA_PRIORITY_MEDIUM DMA_CTLR_PRIO_0
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_to_memory
- * @{
- */
-
-#define DMA_MEMTOMEM_ENABLE DMA_CTLR_MEMTOMEM
-#define DMA_MEMTOMEM_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupts_definition
- * @{
- */
-
-#define DMA_INT_TC DMA_CTLR_TCIE
-#define DMA_INT_HT DMA_CTLR_HTIE
-#define DMA_INT_ERR DMA_CTLR_ERRIE
-
-#define DMA1_INT_GL1 DMA_IFR_GIF1
-#define DMA1_INT_TC1 DMA_IFR_TCIF1
-#define DMA1_INT_HT1 DMA_IFR_HTIF1
-#define DMA1_INT_ERR1 DMA_IFR_ERRIF1
-#define DMA1_INT_GL2 DMA_IFR_GIF2
-#define DMA1_INT_TC2 DMA_IFR_TCIF2
-#define DMA1_INT_HT2 DMA_IFR_HTIF2
-#define DMA1_INT_ERR2 DMA_IFR_ERRIF2
-#define DMA1_INT_GL3 DMA_IFR_GIF3
-#define DMA1_INT_TC3 DMA_IFR_TCIF3
-#define DMA1_INT_HT3 DMA_IFR_HTIF3
-#define DMA1_INT_ERR3 DMA_IFR_ERRIF3
-#define DMA1_INT_GL4 DMA_IFR_GIF4
-#define DMA1_INT_TC4 DMA_IFR_TCIF4
-#define DMA1_INT_HT4 DMA_IFR_HTIF4
-#define DMA1_INT_ERR4 DMA_IFR_ERRIF4
-#define DMA1_INT_GL5 DMA_IFR_GIF5
-#define DMA1_INT_TC5 DMA_IFR_TCIF5
-#define DMA1_INT_HT5 DMA_IFR_HTIF5
-#define DMA1_INT_ERR5 DMA_IFR_ERRIF5
-#define DMA1_INT_GL6 DMA_IFR_GIF6
-#define DMA1_INT_TC6 DMA_IFR_TCIF6
-#define DMA1_INT_HT6 DMA_IFR_HTIF6
-#define DMA1_INT_ERR6 DMA_IFR_ERRIF6
-#define DMA1_INT_GL7 DMA_IFR_GIF7
-#define DMA1_INT_TC7 DMA_IFR_TCIF7
-#define DMA1_INT_HT7 DMA_IFR_HTIF7
-#define DMA1_INT_ERR7 DMA_IFR_ERRIF7
-
-#define DMA2_INT_GL1 ((uint32_t)0x10000001)
-#define DMA2_INT_TC1 ((uint32_t)0x10000002)
-#define DMA2_INT_HT1 ((uint32_t)0x10000004)
-#define DMA2_INT_TE1 ((uint32_t)0x10000008)
-#define DMA2_INT_GL2 ((uint32_t)0x10000010)
-#define DMA2_INT_TC2 ((uint32_t)0x10000020)
-#define DMA2_INT_HT2 ((uint32_t)0x10000040)
-#define DMA2_INT_TE2 ((uint32_t)0x10000080)
-#define DMA2_INT_GL3 ((uint32_t)0x10000100)
-#define DMA2_INT_TC3 ((uint32_t)0x10000200)
-#define DMA2_INT_HT3 ((uint32_t)0x10000400)
-#define DMA2_INT_TE3 ((uint32_t)0x10000800)
-#define DMA2_INT_GL4 ((uint32_t)0x10001000)
-#define DMA2_INT_TC4 ((uint32_t)0x10002000)
-#define DMA2_INT_HT4 ((uint32_t)0x10004000)
-#define DMA2_INT_TE4 ((uint32_t)0x10008000)
-#define DMA2_INT_GL5 ((uint32_t)0x10010000)
-#define DMA2_INT_TC5 ((uint32_t)0x10020000)
-#define DMA2_INT_HT5 ((uint32_t)0x10040000)
-#define DMA2_INT_TE5 ((uint32_t)0x10080000)
-
-
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-#define DMA1_FLAG_GL1 DMA_IFR_GIF1
-#define DMA1_FLAG_TC1 DMA_IFR_TCIF1
-#define DMA1_FLAG_HT1 DMA_IFR_HTIF1
-#define DMA1_FLAG_ERR1 DMA_IFR_ERRIF1
-#define DMA1_FLAG_GL2 DMA_IFR_GIF2
-#define DMA1_FLAG_TC2 DMA_IFR_TCIF2
-#define DMA1_FLAG_HT2 DMA_IFR_HTIF2
-#define DMA1_FLAG_ERR2 DMA_IFR_ERRIF2
-#define DMA1_FLAG_GL3 DMA_IFR_GIF3
-#define DMA1_FLAG_TC3 DMA_IFR_TCIF3
-#define DMA1_FLAG_HT3 DMA_IFR_HTIF3
-#define DMA1_FLAG_ERR3 DMA_IFR_ERRIF3
-#define DMA1_FLAG_GL4 DMA_IFR_GIF4
-#define DMA1_FLAG_TC4 DMA_IFR_TCIF4
-#define DMA1_FLAG_HT4 DMA_IFR_HTIF4
-#define DMA1_FLAG_ERR4 DMA_IFR_ERRIF4
-#define DMA1_FLAG_GL5 DMA_IFR_GIF5
-#define DMA1_FLAG_TC5 DMA_IFR_TCIF5
-#define DMA1_FLAG_HT5 DMA_IFR_HTIF5
-#define DMA1_FLAG_ERR5 DMA_IFR_ERRIF5
-#define DMA1_FLAG_GL6 DMA_IFR_GIF6
-#define DMA1_FLAG_TC6 DMA_IFR_TCIF6
-#define DMA1_FLAG_HT6 DMA_IFR_HTIF6
-#define DMA1_FLAG_ERR6 DMA_IFR_ERRIF6
-#define DMA1_FLAG_GL7 DMA_IFR_GIF7
-#define DMA1_FLAG_TC7 DMA_IFR_TCIF7
-#define DMA1_FLAG_HT7 DMA_IFR_HTIF7
-#define DMA1_FLAG_ERR7 DMA_IFR_ERRIF7
-
-#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
-#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
-#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
-#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
-#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
-#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
-#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
-#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
-#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
-#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
-#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
-#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
-#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
-#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
-#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
-#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
-#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
-#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
-#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
-#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-/** @defgroup DMA_Exported_Functions
- * @{
- */
-
-/* Function used to reset the DMA configuration */
-void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
-
-/* The functions of Initialization and Configuration */
-void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitPara *DMA_InitParaStruct);
-void DMA_ParaInit(DMA_InitPara *DMA_InitParaStruct);
-void DMA_Enable(DMA_Channel_TypeDef *DMAy_Channelx, TypeState NewValue);
-
-/* The functions of Data Counter */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
-
-/* The functions of Interrupts and flags management */
-void DMA_INTConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_INT, TypeState NewValue);
-TypeState DMA_GetBitState(uint32_t DMA_FLAG);
-void DMA_ClearBitState(uint32_t DMA_FLAG);
-TypeState DMA_GetIntBitState(uint32_t DMA_INT);
-void DMA_ClearIntBitState(uint32_t DMA_INT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10x_DMA_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h
deleted file mode 100644
index 6500a8a9ea..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h
+++ /dev/null
@@ -1,1407 +0,0 @@
-/**
- ******************************************************************************
- * @brief ETH header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_ETH_H
-#define __GD32F10X_ETH_H
-#define IF_USE_EXTERNPHY_LIB 0
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-#if (1 == IF_USE_EXTERNPHY_LIB)
-#include "phy.h"
-#endif
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup ETH
- * @{
- */
-
-/** @defgroup ETH_Exported_Types
- * @{
- */
-
-/**
- * @brief ETH MAC Initial Parameters
- */
-typedef struct {
- /**
- * @brief / * MAC
- */
- uint32_t ETH_MAC_AutoNegotiation; /*!< Enable or disable external PHY's AutoNegotiation function
- detailed in @ref ETH_AutoNegotiation */
-
- uint32_t ETH_MAC_Watchdog; /*!< Enable or disable the Watchdog timer
- detailed in @ref ETH_watchdog */
-
- uint32_t ETH_MAC_Jabber; /*!< Enable or disable Jabber timer
- detailed in @ref ETH_Jabber */
-
- uint32_t ETH_MAC_InterFrameGap; /*!< Set the gap of two frames when transmission
- detailed in @ref ETH_Inter_Frame_Gap */
-
- uint32_t ETH_MAC_CarrierSense; /*!< Enable or disable the Carrier Sense
- detailed in @ref ETH_Carrier_Sense */
-
- uint32_t ETH_MAC_Speed; /*!< Set the Ethernet speed, detailed in @ref ETH_Speed */
-
-
- uint32_t ETH_MAC_ReceiveOwn; /*!< Enable or disable the ReceiveOwn mode
- detailed in @ref ETH_Receive_Own */
-
- uint32_t ETH_MAC_LoopbackMode; /*!< Enable or disable the MAC Loopback mode
- detailed in @ref ETH_Loop_Back_Mode */
-
- uint32_t ETH_MAC_Mode; /*!< Set the MAC duplex mode, detailed in @ref ETH_Duplex_Mode */
-
- uint32_t ETH_MAC_ChecksumOffload; /*!< Enable or disable the IPv4(TCP/UDP/ICMP headers) checksum checking when reception
- detailed in @ref ETH_Checksum_Offload */
-
- uint32_t ETH_MAC_RetryTransmission; /*!< Enable or disable the MAC attempt retries transmission in Half-Duplex mode when a colision occurs
- detailed in @ref ETH_Retry_Transmission */
-
- uint32_t ETH_MAC_AutomaticPadCRCDrop; /*!< Enable or disable the Automatic Pad/CRC Drop
- detailed in @ref ETH_Automatic_Pad_CRC_Drop */
-
- uint32_t ETH_MAC_BackOffLimit; /*!< Set the BackOff limit value, detailed in @ref ETH_Back_Off_Limit */
-
- uint32_t ETH_MAC_DeferralCheck; /*!< Enable or disable the deferral check function only in Half-Duplex mode
- detailed in @ref ETH_Deferral_Check */
-
- uint32_t ETH_MAC_FilterDisable; /*!< Enable or disable the MAC filter, detailed in @ref ETH_Filter_Disable */
-
- uint32_t ETH_MAC_SourceAddrFilter; /*!< Set the SA Filter mode, detailed in @ref ETH_Source_Addr_Filter */
-
- uint32_t ETH_MAC_PassControlFrames; /*!< Set the mode of the control frames (including unicast and multicast PAUSE frames)
- detailed in @ref ETH_Pass_Control_Frames */
-
- uint32_t ETH_MAC_BroadcastFramesReception; /*!< Enable or disable the reception of Broadcast Frames
- detailed in @ref ETH_Broadcast_Frames_Reception */
-
- uint32_t ETH_MAC_DestinationAddrFilter; /*!< Set the DA filter mode, detailed in @ref ETH_Destination_Addr_Filter */
-
- uint32_t ETH_MAC_PromiscuousMode; /*!< Enable or disable the Promiscuous Mode
- detailed in @ref ETH_Promiscuous_Mode */
-
- uint32_t ETH_MAC_MulticastFramesFilter; /*!< Set the Multicast Frames filter mode
- detailed in @ref ETH_Multicast_Frames_Filter */
-
- uint32_t ETH_MAC_UnicastFramesFilter; /*!< Set the Unicast Frames filter mode
- detailed in @ref ETH_Unicast_Frames_Filter */
-
- uint32_t ETH_MAC_HashListHigh; /*!< Hash list higher 32 bits */
-
- uint32_t ETH_MAC_HashListLow; /*!< Hash list lower 32 bits */
-
- uint32_t ETH_MAC_PauseTime; /*!< Set the Pause Time field value in the transmit control frame */
-
- uint32_t ETH_MAC_ZeroQuantaPause; /*!< Enable or disable the automatic generation of Zero-Quanta Pause Control frames
- detailed in @ref ETH_Zero_Quanta_Pause */
-
- uint32_t ETH_MAC_PauseLowThreshold; /*!< Set the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame
- detailed in @ref ETH_Pause_Low_Threshold */
-
- uint32_t ETH_MAC_FlowControlDeactiveThreshold;/*!< Set the threshold of the deactive flow control
- detailed in @ref ETH_RFD_Threshold */
-
- uint32_t ETH_MAC_FlowControlActiveThreshold; /*!< Set the threshold of the active flow control
- detailed in @ref ETH_RFA_Threshold */
-
- uint32_t ETH_MAC_UnicastPauseFrameDetect; /*!< Enable or disable the unicast Pause frames detection
- detailed in @ref ETH_Unicast_Pause_Frame_Detect */
-
- uint32_t ETH_MAC_ReceiveFlowControl; /*!< Enable or disable the MAC to received Pause frame
- detailed in @ref ETH_Receive_Flow_Control */
-
- uint32_t ETH_MAC_TransmitFlowControl; /*!< Enable or disable the MAC to transmit Pause frames in Full-Duplex mode
- or back-pressure operation in Half-Duplex mode
- detailed in @ref ETH_Transmit_Flow_Control */
-
- uint32_t ETH_MAC_VLANTagComparison; /*!< Set VLAN tag comparison and filtering mode
- detailed in @ref ETH_VLAN_Tag_Comparison */
-
- uint32_t ETH_MAC_VLANTagIdentifier; /*!< Set VLAN tag identifier for receive frames */
-
- /**
- * @brief / * DMA
- */
-
- uint32_t ETH_DMA_DropTCPIPChecksumErrorFrame; /*!< Enable or disable the TCP/IP Checksum Error Frames drop
- detailed in @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
-
- uint32_t ETH_DMA_ReceiveStoreForward; /*!< Set the Rx FIFO operation mode
- detailed in @ref ETH_Receive_Store_Forward */
-
- uint32_t ETH_DMA_FlushReceivedFrame; /*!< Enable or disable the flushing Receive FIFO
- detailed in @ref ETH_Flush_Received_Frame */
-
- uint32_t ETH_DMA_TransmitStoreForward; /*!< Enable or disable Tx FIFO operation mode
- detailed in @ref ETH_Transmit_Store_Forward */
-
- uint32_t ETH_DMA_TransmitThresholdControl; /*!< Enable or disable the Transmit Threshold Control and set the level
- detailed in @ref ETH_Transmit_Threshold_Control */
-
- uint32_t ETH_DMA_ForwardErrorFrames; /*!< Enable or disable receive the erroneous frames to the DMA
- detailed in @ref ETH_Forward_Error_Frames */
-
- uint32_t ETH_DMA_ForwardUndersizedGoodFrames; /*!< Enable or disable receive the Undersized frames with no Error
- and length less than 64 bytes including pad-bytes and CRC to the DMA
- detailed in @ref ETH_Forward_Undersized_Good_Frames */
-
- uint32_t ETH_DMA_ReceiveThresholdControl; /*!< Enable or disable the Receive Threshold Control and set the level
- detailed in @ref ETH_Receive_Threshold_Control */
-
- uint32_t ETH_DMA_SecondFrameOperate; /*!< Enable or disable the Operate on second frame mode
- detailed in @ref ETH_Second_Frame_Operate */
-
- uint32_t ETH_DMA_AddressAligned; /*!< Enable or disable the Address Aligned
- detailed in @ref ETH_Address_Aligned */
-
- uint32_t ETH_DMA_FixedBurst; /*!< Enable or disable the AHB Master interface fixed burst transfers
- detailed in @ref ETH_Fixed_Burst */
-
- uint32_t ETH_DMA_RxDMABurstLength; /*!< Set the maximum number of beats to be transferred in one Rx DMA transaction
- detailed in @ref ETH_Rx_DMA_Burst_Length */
-
- uint32_t ETH_DMA_TxDMABurstLength; /*!< Set the maximum number of beats to be transferred in one Tx DMA transaction
- detailed in @ref ETH_Tx_DMA_Burst_Length */
-
- uint32_t ETH_DMA_DescriptorSkipLength; /*!< Set the number of word to skip between two descriptors only in Ring mode */
-
- uint32_t ETH_DMA_Arbitration; /*!< Set the DMA Tx/Rx priority ratio
- detailed in @ref ETH_DMA_Arbitration */
-} ETH_InitPara;
-
-/**
- * @brief ETH DMA Desciptors structure def
- */
-typedef struct {
- uint32_t Status; /*!< Status */
- uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
- uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
- uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
-} ETH_DMADESCTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Constants
- * @{
- */
-
-/** @defgroup ETH_delay_Def
- * @{
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */
-#else
-#define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Buffer_Def
- * @{
- */
-#define ETH_MAX_FRAME_SIZE 1520 /*!< FRAME_HEADER + FRAME_EXTRA + MAX_FRAME_PAYLOAD + FRAME_CRC */
-#define ETH_HEADER 14 /*!< 6 byte DA, 6 byte SA, 2 byte length/type */
-#define ETH_CRC 4 /*!< 4 byte CRC */
-#define ETH_EXTRA 2 /*!< Extra bytes in some cases */
-#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */
-#define MIN_ETH_DATALENGTH 46 /*!< Minimum Eth payload byte */
-#define MAX_ETH_DATALENGTH 1500 /*!< Maximum Eth payload byte */
-#define JUMBO_FRAME_DATALENGTH 9000 /*!< Jumbo frame payload byte */
-
-/**
- DMA Tx Desciptor
- -----------------------------------------------------------------------------------------------
- TDES0 | BUSY(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
- -----------------------------------------------------------------------------------------------
- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
- -----------------------------------------------------------------------------------------------
- TDES2 | Buffer1 Address [31:0] |
- -----------------------------------------------------------------------------------------------
- TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
- -----------------------------------------------------------------------------------------------
-*/
-
-/**
- * @brief DMA Tx descriptor TDES0 register Bit def
- */
-#define ETH_DMATXDESC_BUSY ((uint32_t)0x80000000) /*!< DMA or CPU control descriptor*/
-#define ETH_DMATXDESC_INTC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LSG ((uint32_t)0x20000000) /*!< contains the last segment of the frame */
-#define ETH_DMATXDESC_FSG ((uint32_t)0x10000000) /*!< contains the first segment of the frame */
-#define ETH_DMATXDESC_DCRC ((uint32_t)0x08000000) /*!< Disable CRC */
-#define ETH_DMATXDESC_DPAD ((uint32_t)0x04000000) /*!< Disable Pad */
-#define ETH_DMATXDESC_TTSEN ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CM ((uint32_t)0x00C00000) /*!< Checksum Mode: 4 cases */
-#define ETH_DMATXDESC_CM_DISABLE ((uint32_t)0x00000000) /*!< Checksum Insertion disabled */
-#define ETH_DMATXDESC_CM_IPV4HEADER ((uint32_t)0x00400000) /*!< Only IP header checksum calculation and insertion are enabled */
-#define ETH_DMATXDESC_CM_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated but pseudo-header */
-#define ETH_DMATXDESC_CM_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TERM ((uint32_t)0x00200000) /*!< Transmit End of Ring Mode*/
-#define ETH_DMATXDESC_TCHM ((uint32_t)0x00100000) /*!< Transmit des Chained Mode*/
-#define ETH_DMATXDESC_TTMSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IPHE ((uint32_t)0x00010000) /*!< IP Header Error: IP4 or IP6*/
-#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary */
-#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FRMF ((uint32_t)0x00002000) /*!< clean FIFO */
-#define ETH_DMATXDESC_IPPE ((uint32_t)0x00001000) /*!< IP Payload Error */
-#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier */
-#define ETH_DMATXDESC_NCA ((uint32_t)0x00000400) /*!< No Carrier */
-#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision */
-#define ETH_DMATXDESC_ECO ((uint32_t)0x00000100) /*!< abort transmission due to collision */
-#define ETH_DMATXDESC_VFRM ((uint32_t)0x00000080) /*!< VLAN Frame */
-#define ETH_DMATXDESC_COCNT ((uint32_t)0x00000078) /*!< Collision Count */
-#define ETH_DMATXDESC_EXD ((uint32_t)0x00000004) /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UFE ((uint32_t)0x00000002) /*!< late data arrival from the memory */
-#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
-
-/**
- * @brief DMA Tx descriptor TDES1 register Bit def
- */
-#define ETH_DMATXDESC_TB2S ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TB1S ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
-
-/**
- * @brief DMA Tx descriptor TDES2 register Bit def
- */
-#define ETH_DMATXDESC_TB1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
-
-/**
- * @brief DMA Tx descriptor TDES3 register Bit def
- */
-#define ETH_DMATXDESC_TB2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
-
-/**
- * @}
- */
-
-
-/** @defgroup DMA_Rx_descriptor
- * @{
- */
-
-/**
- DMA Rx Desciptor
- --------------------------------------------------------------------------------------------------------------------
- RDES0 | BUSY(31) | Status [30:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES2 | Buffer1 Address [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
-*/
-
-/**
- * @brief DMA Rx descriptor RDES0 register Bit def
- */
-#define ETH_DMARXDESC_BUSY ((uint32_t)0x80000000) /*!< DMA or CPU control descriptor */
-#define ETH_DMARXDESC_DAFF ((uint32_t)0x40000000) /*!< DA filter fail */
-#define ETH_DMARXDESC_FRML ((uint32_t)0x3FFF0000) /*!< Frame length */
-#define ETH_DMARXDESC_ERRS ((uint32_t)0x00008000) /*!< Error summary */
-#define ETH_DMARXDESC_DERR ((uint32_t)0x00004000) /*!< no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAFF ((uint32_t)0x00002000) /*!< SA filter fail */
-#define ETH_DMARXDESC_LERR ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OERR ((uint32_t)0x00000800) /*!< FIFO Overflow Error */
-#define ETH_DMARXDESC_VTAG ((uint32_t)0x00000400) /*!< VLAN Tag: a VLAN frame tag */
-#define ETH_DMARXDESC_FDES ((uint32_t)0x00000200) /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LDES ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPHCERR ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 or Ipv6 header checksum error */
-#define ETH_DMARXDESC_LCO ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FRMT ((uint32_t)0x00000020) /*!< Frame type */
-#define ETH_DMARXDESC_RWDT ((uint32_t)0x00000010) /*!< Receive WD Timeout */
-#define ETH_DMARXDESC_RERR ((uint32_t)0x00000008) /*!< the RX_ERR signal is asserted while RX_DV is asserted during frame reception */
-#define ETH_DMARXDESC_DBERR ((uint32_t)0x00000004) /*!< received frame has a non int multiple of bytes */
-#define ETH_DMARXDESC_CERR ((uint32_t)0x00000002) /*!< CRC error */
-#define ETH_DMARXDESC_PCERR ((uint32_t)0x00000001) /*!< Receive MAC address matched/ Receive Payload Checksum Error */
-
-/**
- * @brief DMA Rx descriptor RDES1 register Bit def
- */
-#define ETH_DMARXDESC_DINTC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RB2S ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RERM ((uint32_t)0x00008000) /*!< Receive End of Ring mode*/
-#define ETH_DMARXDESC_RCHM ((uint32_t)0x00004000) /*!< Receive des Chained mode */
-#define ETH_DMARXDESC_RB1S ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
-
-/**
- * @brief DMA Rx descriptor RDES2 register Bit def
- */
-#define ETH_DMARXDESC_RB1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
-
-/**
- * @brief DMA Rx descriptor RDES3 register Bit def
- */
-#define ETH_DMARXDESC_RB2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
-
-#ifndef _PHY_H_
-#define DP83848 0
-#define LAN8700 1
-#define PHY_TYPE DP83848
-
-/**
- * @}
- */
-
-/** @defgroup PHY_Read_write_Timeouts
- * @{
- */
-#define PHY_READ_TO ((uint32_t)0x0004FFFF)
-#define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
-
-/**
- * @}
- */
-
-/** @defgroup PHY_Reset_Delay
- * @{
- */
-#define PHY_RESETDELAY ((uint32_t)0x000FFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup PHY_Config_Delay
- * @{
- */
-#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup PHY_Register_address
- * @{
- */
-#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */
-#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */
-
-/**
- * @}
- */
-
-/** @defgroup PHY_basic_Control_register
- * @{
- */
-#define PHY_RESET ((u16)0x8000) /*!< PHY Reset */
-#define PHY_LOOPBACK ((u16)0x4000) /*!< Enable loop-back mode */
-#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Configure speed to 100 Mb/s and the full-duplex mode */
-#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Configure speed to 100 Mb/s and the half-duplex mode */
-#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Configure speed to 10 Mb/s and the full-duplex mode */
-#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Configure speed to 10 Mb/s and the half-duplex mode */
-#define PHY_AUTONEGOTIATION ((u16)0x1000) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((u16)0x0200) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((u16)0x0800) /*!< Enable the power down mode */
-#define PHY_ISOLATE ((u16)0x0400) /*!< Isolate PHY from MII */
-
-/**
- * @}
- */
-
-/** @defgroup PHY_basic_status_register
- * @{
- */
-#define PHY_AUTONEGO_COMPLETE ((u16)0x0020) /*!< Auto-Negotioation process completed */
-#define PHY_LINKED_STATUS ((u16)0x0004) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((u16)0x0002) /*!< Jabber condition detected */
-
-/**
- * @}
- */
-
-/** @defgroup PHY_status_register
- * @{
- */
-/* The PHY status register value change with PHY in different Manufacturer
- so the user can use external PHY lib to update this value if PHY types user selected not included in firmware */
-#if(PHY_TYPE == LAN8700)
-/**
- * @brief For LAN8700
- */
-#define PHY_SR 31 /*!< Tranceiver Status Register */
-/* The Speed and Duplex mask values change with PHY in different Manufacturer
- so the user can use external PHY lib to update this value if PHY types user selected not included in firmware */
-#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */
-#define PHY_DUPLEX_STATUS ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */
-
-#elif(PHY_TYPE == DP83848)
-/**
- * @brief For DP83848
- */
-#define PHY_SR 16 /*!< Tranceiver Status Register */
-/* The Speed and Duplex mask values change with PHY in different Manufacturer
- so the user can use external PHY lib to update this value if PHY types user selected not included in firmware */
-#define PHY_SPEED_STATUS ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */
-#define PHY_DUPLEX_STATUS ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */
-
-#define PHY_Reset PHY_RESETDELAY
-#define PHY_ResetDelay PHY_RESETDELAY
-#define PHY_Speed_Status PHY_SPEED_STATUS
-
-#endif
-
-#endif
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_AutoNegotiation
- * @{
- */
-#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
-#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_watchdog
- * @{
- */
-#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
-#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Jabber
- * @{
- */
-#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
-#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Inter_Frame_Gap
- * @{
- */
-#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000)
-#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000)
-#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000)
-#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000)
-#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000)
-#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000)
-#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000)
-#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Carrier_Sense
- * @{
- */
-#define ETH_CARRIERSENSE_ENABLE ((uint32_t)0x00000000)
-#define ETH_CARRIERSENSE_DISABLE ((uint32_t)0x00010000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Speed
- * @{
- */
-#define ETH_SPEEDMODE_10M ((uint32_t)0x00000000)
-#define ETH_SPEEDMODE_100M ((uint32_t)0x00004000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Own
- * @{
- */
-#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Loop_Back_Mode
- * @{
- */
-#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
-#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Duplex_Mode
- * @{
- */
-#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
-#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Checksum_Offload
- * @{
- */
-#define ETH_CHECKSUMOFFLOAD_ENABLE ((uint32_t)0x00000400)
-#define ETH_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Retry_Transmission
- * @{
- */
-#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
-#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Automatic_Pad_CRC_Drop
- * @{
- */
-#define ETH_AUTOMATICPADCRCDROP_ENABLE ((uint32_t)0x00000080)
-#define ETH_AUTOMATICPADCRCDROP_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Back_Off_Limit
- * @{
- */
-#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
-#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
-#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
-#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Deferral_Check
- * @{
- */
-#define ETH_DEFERRALCHECK_ENABLE ((uint32_t)0x00000010)
-#define ETH_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Filter_Disable
- * @{
- */
-#define ETH_FILTERDISABLE_ENABLE ((uint32_t)0x80000000)
-#define ETH_FILTERDISABLE_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Source_Addr_Filter
- * @{
- */
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
-#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Pass_Control_Frames
- * @{
- */
-#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040)
-#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080)
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Broadcast_Frames_Reception
- * @{
- */
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Destination_Addr_Filter
- * @{
- */
-#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
-#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Promiscuous_Mode
- * @{
- */
-#define ETH_PROMISCUOUSMODE_ENABLE ((uint32_t)0x00000001)
-#define ETH_PROMISCUOUSMODE_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Multicast_Frames_Filter
- * @{
- */
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
-#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Frames_Filter
- * @{
- */
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
-#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_Zero_Quanta_Pause
- * @{
- */
-#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
-#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
-/**
- * @}
- */
-
-/** @defgroup ETH_Pause_Low_Threshold
- * @{
- */
-#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000)
-#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010)
-#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020)
-#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_RFD_Threshold
- * @{
- */
-#define ETH_RFD_256BYTES ((uint32_t)0x00000000)
-#define ETH_RFD_512BYTES ((uint32_t)0x00000010)
-#define ETH_RFD_768BYTES ((uint32_t)0x00000020)
-#define ETH_RFD_1024BYTES ((uint32_t)0x00000030)
-#define ETH_RFD_1280BYTES ((uint32_t)0x00000040)
-#define ETH_RFD_1536BYTES ((uint32_t)0x00000050)
-#define ETH_RFD_1792BYTES ((uint32_t)0x00000060)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_RFA_Threshold
- * @{
- */
-#define ETH_RFA_256BYTES ((uint32_t)0x00000000)
-#define ETH_RFA_512BYTES ((uint32_t)0x00000001)
-#define ETH_RFA_768BYTES ((uint32_t)0x00000002)
-#define ETH_RFA_1024BYTES ((uint32_t)0x00000003)
-#define ETH_RFA_1280BYTES ((uint32_t)0x00000004)
-#define ETH_RFA_1536BYTES ((uint32_t)0x00000005)
-#define ETH_RFA_1792BYTES ((uint32_t)0x00000006)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Pause_Frame_Detect
- * @{
- */
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Flow_Control
- * @{
- */
-#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
-#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Flow_Control
- * @{
- */
-#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
-#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_VLAN_Tag_Comparison
- * @{
- */
-#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
-#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Flags
- * @{
- */
-#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MSCT ((uint32_t)0x00000040) /*!< MSC transmit flag */
-#define ETH_MAC_FLAG_MSCR ((uint32_t)0x00000020) /*!< MSC receive flag */
-#define ETH_MAC_FLAG_MSC ((uint32_t)0x00000010)
-#define ETH_MAC_FLAG_WUM ((uint32_t)0x00000008)
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Interrupts
- * @{
- */
-#define ETH_MAC_INT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_INT_MSCT ((uint32_t)0x00000040) /*!< MSC transmit interrupt */
-#define ETH_MAC_INT_MSCR ((uint32_t)0x00000020) /*!< MSC receive interrupt */
-#define ETH_MAC_INT_MSC ((uint32_t)0x00000010)
-#define ETH_MAC_INT_WUM ((uint32_t)0x00000008)
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses
- * @{
- */
-#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
-#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
-#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
- * @{
- */
-#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
- * @{
- */
-#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [7:0] */
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_DMA_Tx_descriptor_segment
- * @{
- */
-#define ETH_DMATXDESC_LASTSEGMENT ((uint32_t)0x40000000)
-#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
- * @{
- */
-#define ETH_DMATXDESC_CHECKSUMDISABLE ((uint32_t)0x00000000)
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000)
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000)
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Rx_descriptor_buffers_
- * @{
- */
-#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000)
-#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
- * @{
- */
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Store_Forward
- * @{
- */
-#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
-#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Flush_Received_Frame
- * @{
- */
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Store_Forward
- * @{
- */
-#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
-#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Threshold_Control
- * @{
- */
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000)
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Error_Frames
- * @{
- */
-#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
-#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Undersized_Good_Frames
- * @{
- */
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Threshold_Control
- * @{
- */
-#define ETH_RECEIVETHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000)
-#define ETH_RECEIVETHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008)
-#define ETH_RECEIVETHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010)
-#define ETH_RECEIVETHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018)
-/**
- * @}
- */
-
-/** @defgroup ETH_Second_Frame_Operate
- * @{
- */
-#define ETH_SECONDFRAMEOPERATE_ENABLE ((uint32_t)0x00000004)
-#define ETH_SECONDFRAMEOPERATE_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Address_Aligned
- * @{
- */
-#define ETH_ADDRESSALIGNED_ENABLE ((uint32_t)0x02000000)
-#define ETH_ADDRESSALIGNED_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Fixed_Burst
- * @{
- */
-#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
-#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Rx_DMA_Burst_Length
- * @{
- */
-#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000)
-#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000)
-#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000)
-#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000)
-#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000)
-#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000)
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000)
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000)
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000)
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000)
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000)
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000)
-/**
- * @}
- */
-
-/** @defgroup ETH_Tx_DMA_Burst_Length
- * @{
- */
-#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100)
-#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200)
-#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400)
-#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800)
-#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000)
-#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000)
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100)
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200)
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400)
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800)
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000)
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Arbitration
- * @{
- */
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
-#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Flags
- * @{
- */
-#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_WUM ((uint32_t)0x10000000) /*!< WUM interrupt (on DMA) */
-#define ETH_DMA_FLAG_MSC ((uint32_t)0x08000000) /*!< MSC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
-#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
-#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Transmit Underflow flag */
-#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Receive Overflow flag */
-#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Interrupts
- * @{
- */
-#define ETH_DMA_INT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_INT_WUM ((uint32_t)0x10000000) /*!< WUM interrupt (on DMA) */
-#define ETH_DMA_INT_MSC ((uint32_t)0x08000000) /*!< MSC interrupt (on DMA) */
-#define ETH_DMA_INT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
-#define ETH_DMA_INT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
-#define ETH_DMA_INT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
-#define ETH_DMA_INT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
-#define ETH_DMA_INT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
-#define ETH_DMA_INT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_INT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
-#define ETH_DMA_INT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_INT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
-#define ETH_DMA_INT_TU ((uint32_t)0x00000020) /*!< Transmit Underflow interrupt */
-#define ETH_DMA_INT_RO ((uint32_t)0x00000010) /*!< Receive Overflow interrupt */
-#define ETH_DMA_INT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_INT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_INT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
-#define ETH_DMA_INT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_transmit_process_state_
- * @{
- */
-#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000)
-#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000)
-#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000)
-#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000)
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000)
-#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000)
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_DMA_receive_process_state_
- * @{
- */
-#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000)
-#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000)
-#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000)
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000)
-#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000)
-#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_overflow_
- * @{
- */
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000)
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_WUM_Flags
- * @{
- */
-#define ETH_WUM_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */
-#define ETH_WUM_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
-#define ETH_WUM_FLAG_MPKR ((uint32_t)0x00000020) /*!< Magic Packet Received */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_MSC_Tx_Interrupts
- * @{
- */
-#define ETH_MSC_INT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MSC_INT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MSC_INT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_MSC_Rx_Interrupts
- * @{
- */
-#define ETH_MSC_INT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MSC_INT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MSC_INT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
-/**
- * @}
- */
-
-/** @defgroup ETH_MSC_Registers
- * @{
- */
-#define ETH_MSC_CTLR ((uint32_t)0x00000100)
-#define ETH_MSC_RISR ((uint32_t)0x00000104)
-#define ETH_MSC_TISR ((uint32_t)0x00000108)
-#define ETH_MSC_RIMR ((uint32_t)0x0000010C)
-#define ETH_MSC_TIMR ((uint32_t)0x00000110)
-#define ETH_MSC_SCCNT ((uint32_t)0x0000014C)
-#define ETH_MSC_MSCCNT ((uint32_t)0x00000150)
-#define ETH_MSC_TGFCNT ((uint32_t)0x00000168)
-#define ETH_MSC_RFCECNT ((uint32_t)0x00000194)
-#define ETH_MSC_RFAECNT ((uint32_t)0x00000198)
-#define ETH_MSC_RGUFCNT ((uint32_t)0x000001C4)
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_PTP_time_update_mode
- * @{
- */
-#define ETH_PTP_FINEMODE ((uint32_t)0x00000001)
-#define ETH_PTP_COARSEMODE ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_PTP_Flags
- * @{
- */
-#define ETH_PTP_FLAG_TMSARU ((uint32_t)0x00000020) /*!< Addend Register Update */
-#define ETH_PTP_FLAG_TMSITEN ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger Enable */
-#define ETH_PTP_FLAG_TMSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */
-#define ETH_PTP_FLAG_TMSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_PTP_time_sign
- * @{
- */
-#define ETH_PTP_POSITIVETIME ((uint32_t)0x00000000)
-#define ETH_PTP_NEGATIVETIME ((uint32_t)0x80000000)
-
-/**
- * @brief ETH PTP registers
- */
-#define ETH_PTP_TSCTLR ((uint32_t)0x00000700)
-#define ETH_PTP_SSINCR ((uint32_t)0x00000704)
-#define ETH_PTP_TMSHR ((uint32_t)0x00000708)
-#define ETH_PTP_TMSLR ((uint32_t)0x0000070C)
-#define ETH_PTP_TMSHUR ((uint32_t)0x00000710)
-#define ETH_PTP_TMSLUR ((uint32_t)0x00000714)
-#define ETH_PTP_TSACNT ((uint32_t)0x00000718)
-#define ETH_PTP_ETHR ((uint32_t)0x0000071C)
-#define ETH_PTP_ETLR ((uint32_t)0x00000720)
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_Exported_Functions
- * @{
- */
-void ETH_DeInit(void);
-void ETH_MDIOInit(void);
-uint32_t ETH_Init(ETH_InitPara *ETH_InitParaStruct, u16 PHYAddress);
-void ETH_ParaInit(ETH_InitPara *ETH_InitParaStruct);
-void ETH_SoftReset(void);
-TypeState ETH_GetSoftResetStatus(void);
-void ETH_Enable(TypeState NewValue);
-uint32_t ETH_HandleTxPkt(uint8_t *pbuf, uint16_t size);
-uint32_t ETH_HandleRxPkt(uint8_t *pbuf);
-uint32_t ETH_GetRxPktSize(void);
-void ETH_DropRxPkt(void);
-/**
- * @brief PHY
- */
-uint16_t ETH_GetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg);
-uint32_t ETH_SetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg, uint16_t PHYValue);
-uint32_t ETH_PHYLoopBack_Enable(uint16_t PHYAddr, TypeState NewValue);
-
-/**
- * @brief MAC
- */
-void ETH_MACTransmission_Enable(TypeState NewValue);
-void ETH_MACReception_Enable(TypeState NewValue);
-TypeState ETH_GetFlowControlBusyBitState(void);
-void ETH_PauseFrameInit(void) ;
-void ETH_BackPressureActivation_Enable(TypeState NewValue);
-TypeState ETH_GetMACBitState(uint32_t ETH_MAC_FLAG);
-TypeState ETH_GetMACIntBitState(uint32_t ETH_MAC_IT);
-void ETH_MACINTConfig(uint32_t ETH_MAC_IT, TypeState NewValue);
-void ETH_SetMACAddress(uint32_t addr, uint8_t *buf);
-void ETH_GetMACAddress(uint32_t addr, uint8_t *buf);
-void ETH_MACAddressPerfectFilter_Enable(uint32_t addr, TypeState NewValue);
-void ETH_MACAddressFilterConfig(uint32_t addr, uint32_t Filterfield);
-void ETH_MACAddressFilterMaskBytesConfig(uint32_t addr, uint32_t addrmask);
-
-/**
- * @brief DMA Tx/Rx descriptors
- */
-void ETH_DMATxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff, uint32_t TxBuffCnt);
-void ETH_DMATxDescRingModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff1, uint8_t *pTxBuff2, uint32_t TxBuffCnt);
-TypeState ETH_GetDMATxDescBitState(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
-uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
-void ETH_SetDMATxDescBusyBit(ETH_DMADESCTypeDef *DMATxDesc);
-void ETH_DMATxDescTransmitINTConfig(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue);
-void ETH_SetDMATxDescFrameSegment(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Segment);
-void ETH_SetDMATxDescChecksumInsertion(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
-void ETH_DMATxDescCRC_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue);
-void ETH_DMATxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue);
-void ETH_DMATxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue);
-void ETH_DMATxDescShortFramePadding_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue);
-void ETH_DMATxDescTimeStamp_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue);
-void ETH_SetDMATxDescBufferSize(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffer1Size, uint32_t Buffer2Size);
-void ETH_DMARxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff, uint32_t RxBuffCnt);
-void ETH_DMARxDescRingModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff1, uint8_t *pRxBuff2, uint32_t RxBuffCnt);
-TypeState ETH_GetDMARxDescBitState(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
-void ETH_SetDMARxDescBusyBit(ETH_DMADESCTypeDef *DMARxDesc);
-uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
-void ETH_DMARxDescReceiveINTConfig(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue);
-void ETH_DMARxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue);
-void ETH_DMARxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue);
-uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
-
-/**
- * @brief DMA
- */
-TypeState ETH_GetDMABitState(uint32_t ETH_DMA_FLAG);
-void ETH_DMAClearBitState(uint32_t ETH_DMA_FLAG);
-TypeState ETH_GetDMAIntBitState(uint32_t ETH_DMA_IT);
-void ETH_DMAClearIntBitState(uint32_t ETH_DMA_IT);
-uint32_t ETH_GetTransmitProcessState(void);
-uint32_t ETH_GetReceiveProcessState(void);
-void ETH_CleanTransmitFIFO(void);
-TypeState ETH_GetFlushTransmitFIFOStatus(void);
-void ETH_DMATransmission_Enable(TypeState NewValue);
-void ETH_DMAReception_Enable(TypeState NewValue);
-void ETH_DMAINTConfig(uint32_t ETH_DMA_IT, TypeState NewValue);
-TypeState ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
-uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
-uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
-uint32_t ETH_GetCurrentTxDescStartAddress(void);
-uint32_t ETH_GetCurrentRxDescStartAddress(void);
-uint32_t ETH_GetCurrentTxBufferAddress(void);
-uint32_t ETH_GetCurrentRxBufferAddress(void);
-void ETH_ResumeDMATransmission(void);
-void ETH_ResumeDMAReception(void);
-
-/**
- * @brief WUM
- */
-void ETH_ResetWakeUpFrameFilterRegister(void);
-void ETH_SetWakeUpFrameFilterRegister(uint32_t *pBuffer);
-void ETH_GlobalUnicastWakeUp_Enable(TypeState NewValue);
-TypeState ETH_GetWUMBitState(uint32_t ETH_WUM_FLAG);
-void ETH_WakeUpFrameDetection_Enable(TypeState NewValue);
-void ETH_MagicPacketDetection_Enable(TypeState NewValue);
-void ETH_PowerDown_Enable(TypeState NewValue);
-
-/**
- * @brief MSC
- */
-void ETH_MSCCounterFreeze_Enable(TypeState NewValue);
-void ETH_MSCResetOnRead_Enable(TypeState NewValue);
-void ETH_MSCCounterRollover_Enable(TypeState NewValue);
-void ETH_ResetMSCCounters(void);
-void ETH_MSCINTConfig(uint32_t ETH_MSC_IT, TypeState NewValue);
-TypeState ETH_GetMSCINTStatus(uint32_t ETH_MSC_IT);
-uint32_t ETH_GetMSCRegister(uint32_t ETH_MSC_Register);
-
-/**
- * @brief PTP
- */
-void ETH_PTPTimeStampAddendUpdate(void);
-void ETH_PTPTimeStampIntTrigger_Enable(TypeState NewValue);
-void ETH_PTPTimeStampUpdate_Enable(TypeState NewValue);
-void ETH_PTPTimeStampInit(void);
-void ETH_PTPUpdateModeConfig(uint32_t UpdateMode);
-void ETH_PTPTimeStamp_Enable(TypeState NewValue);
-TypeState ETH_GetPTPBitState(uint32_t ETH_PTP_FLAG);
-void ETH_SetPTPSubSecondIncrement(uint32_t SubSecond);
-void ETH_SetPTPUpdateTimeValue(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
-void ETH_SetPTPTimeStampAddend(uint32_t add);
-void ETH_SetPTPTargetTime(uint32_t HighReg_Value, uint32_t LowReg_Value);
-uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPRegister);
-void ETH_DMAPTPTxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,
- uint8_t *pTxBuff, uint32_t TxBuffCnt);
-void ETH_DMAPTPRxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,
- uint8_t *pRxBuff, uint32_t RxBuffCnt);
-uint32_t ETH_HandlePTPTxPkt(uint8_t *pbuf, uint16_t size, uint32_t *PTPTxTab);
-uint32_t ETH_HandlePTPRxPkt(uint8_t *pbuf, uint32_t *PTPRxTab);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_ETH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h
deleted file mode 100644
index 864efe9371..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/**
- ******************************************************************************
- * @brief EXMC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_EXMC_H
-#define __GD32F10X_EXMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup EXMC
- * @{
- */
-
-/** @defgroup EXMC_Exported_Types
- * @{
- */
-
-/**
- * @brief Initial Timing Parameters For NOR/SRAM Banks
- */
-typedef struct {
- uint32_t EXMC_AsynAccessMode; /*!< The asynchronous access mode, detailed in @ref EXMC_AsynAccess_Mode*/
- uint32_t EXMC_SynDataLatency; /*!< The number of CLK cycles to configure the data latency,
- which may assume a value between 0x0 and 0xF. */
- uint32_t EXMC_SynCLKDivision; /*!< The number of HCLK cycles to configure the clock divide ratio,
- which can be a value between 0x0 and 0xF. */
- uint32_t EXMC_BusLatency; /*!< The number of HCLK cycles to configure the bus latency,
- which can be a value between 0x0 and 0xF. */
- uint32_t EXMC_AsynDataSetupTime; /*!< The number of HCLK cycles to configure the data setup time
- while in the asynchronous access mode, which can be a value
- between 0x00 and 0xFF. */
- uint32_t EXMC_AsynAddressHoldTime; /*!< The number of HCLK cycles to configure the address hold time
- while in the asynchronous access mode, which can be a value
- between 0x0 and 0xF. */
- uint32_t EXMC_AsynAddressSetupTime; /*!< The number of HCLK cycles to configure the data setup time
- while in the asynchronous access mode, which can be a value
- between 0x0 and 0xF. */
-} EXMC_NORSRAMTimingInitPara;
-
-/**
- * @brief EXMC NOR/SRAM Init structure definition
- */
-typedef struct {
- uint32_t EXMC_NORSRAMBank; /*!< The specified region of NORSRAM Bank1,
- choose one from @ref EXMC_NORSRAMBank. */
- uint32_t EXMC_WriteMode; /*!< The write mode, details in @ref EXMC_WriteMode. */
- uint32_t EXMC_ExtendedMode; /*!< Enable or Disable the extended mode, details in
- @ref EXMC_ExtendedMode. */
- uint32_t EXMC_AsynWait; /*!< Enable or disable the asynchronous wait feature,detial
- in @ref EXMC_AsynWait. */
- uint32_t EXMC_NWAITSignal; /*!< Enable or Disable the NWAIT signal while in synchronous
- bust mode, details in @ref EXMC_NWAITSignal. */
- uint32_t EXMC_MemoryWrite; /*!< Enable or Disable the write operation, details in
- @ref EXMC_MemoryWrite. */
- uint32_t EXMC_NWAITConfig; /*!< NWAIT signal configuration, details in @ref EXMC_NWAITConfig */
- uint32_t EXMC_WrapBurstMode; /*!< Enable or Disable the wrap burst mode, details in
- @ref EXMC_WrapBurstMode. */
- uint32_t EXMC_NWAITPolarity; /*!< Specifies the polarity of NWAIT signal from memory,
- details in @ref EXMC_NWAITPolarity. */
- uint32_t EXMC_BurstMode; /*!< Enable or Disable the burst mode, details in
- @ref EXMC_BurstMode. */
- uint32_t EXMC_DatabusWidth; /*!< Specifies the databus width of external memory,
- details in @ref EXMC_DatabusWidth. */
- uint32_t EXMC_MemoryType; /*!< Specifies the type of external memory, details in
- @ref EXMC_MemoryType. */
- uint32_t EXMC_AddressDataMux; /*!< Specifies whether the data bus and address bus are multiplexed
- or not,details in @ref EXMC_AddressDataMux. */
-
- EXMC_NORSRAMTimingInitPara *EXMC_ReadWriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is
- used to define the timing parameters for read and write
- if the ExtendedMode is not used or define the timing
- parameters for read if the ExtendedMode is used. */
-
- EXMC_NORSRAMTimingInitPara *EXMC_WriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is
- only used to define the timing parameters for write when
- the ExtendedMode is used. */
-} EXMC_NORSRAMInitPara;
-
-/**
- * @brief Timing parameters For EXMC NAND and PCCARD Banks
- */
-
-typedef struct {
- uint32_t EXMC_DatabusHiZTime; /*!< The number of HCLK cycles to configure the dadtabus HiZ time
- for write operation, which can be a value between 0x00 and 0xFF. */
- uint32_t EXMC_HoldTime; /*!< The number of HCLK cycles to configure the address hold time
- (or the data hold time for write operation),which can be a value
- between 0x00 and 0xFF. */
- uint32_t EXMC_WaitTime; /*!< The number of HCLK cycles to configure the minimum wait time,
- which can be a value between 0x00 and 0xFF. */
- uint32_t EXMC_SetupTime; /*!< The number of HCLK cycles to configure the address setup time ,
- which can be a value between 0x00 and 0xFF. */
-} EXMC_NAND_PCCARDTimingInitPara;
-
-/**
- * @brief EXMC NAND Init structure definition
- */
-typedef struct {
- uint32_t EXMC_NANDBank; /*!< The specified Bank of NAND FLASH, choose one
- from @ref EXMC_NANDBank. */
- uint32_t EXMC_ECCSize; /*!< The page size for the ECC calculation,details
- in @ref EXMC_ECCSize. */
- uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure the
- latency of ALE low to RB low, which can be a
- value between 0x0 and 0xF. */
- uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure the
- latency of CLE low to RB low, which can be a
- value between 0x0 and 0xF. */
- uint32_t EXMC_ECCLogic; /*!< Enable or Disable the ECC calculation logic,
- details in @ref EXMC_ECCLogic. */
- uint32_t EXMC_DatabusWidth; /*!< the NAND flash databus width, details in
- @ref EXMC_DatabusWidth. */
- uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details
- in @ref EXMC_WaitFeature. */
- EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
- pointer, which is used to define the timing
- parameters for NAND flash Common Space. */
- EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
- pointer, which is used to define the timing
- parameters for NAND flash Attribute Space. */
-} EXMC_NANDInitPara;
-
-/**
- * @brief EXMC PCCARD Init structure definition
- */
-
-typedef struct {
- uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure
- the latency of ALE low to RB low, which can
- be a value between 0x0 and 0xF. */
- uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure
- the latency of CLE low to RB low, which can
- be a value between 0x0 and 0xF. */
- uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details
- in @ref EXMC_WaitFeature. */
- EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
- pointer, which is used to define the timing
- parameters for PC CARD Common Space. */
- EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
- pointer, which is used to define the timing
- parameters for PC CARD Attribute Space. */
- EXMC_NAND_PCCARDTimingInitPara *EXMC_IOSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara
- pointer, which is used to define the timing
- parameters for PC CARD I/O Space. */
-} EXMC_PCCARDInitPara;
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_Exported_Constants
- * @{
- */
-
-/** @defgroup EXMC_NORSRAMBank
- * @{
- */
-#define EXMC_BANK1_NORSRAM1 ((uint32_t)0x00000001)
-#define EXMC_BANK1_NORSRAM2 ((uint32_t)0x00000002)
-#define EXMC_BANK1_NORSRAM3 ((uint32_t)0x00000003)
-#define EXMC_BANK1_NORSRAM4 ((uint32_t)0x00000004)
-/**
- * @}
- */
-
-/** @defgroup EXMC_NANDBank
- * @{
- */
-#define EXMC_BANK2_NAND ((uint32_t)0x00000010)
-#define EXMC_BANK3_NAND ((uint32_t)0x00000100)
-/**
- * @}
- */
-
-/** @defgroup EXMC_PCCARD_Bank
- * @{
- */
-#define EXMC_BANK4_PCCARD ((uint32_t)0x00001000)
-
-/**
- * @}
- */
-
-/** @defgroup NORSRAM_Controller
- * @{
- */
-
-/** @defgroup EXMC_AddressDataMux
- * @{
- */
-#define EXMC_ADDRESS_DATA_MUX_DISABLE ((uint32_t)0x00000000)
-#define EXMC_ADDRESS_DATA_MUX_ENABLE ((uint32_t)0x00000002)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_MemoryType
- * @{
- */
-#define EXMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
-#define EXMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
-#define EXMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_DatabusWidth
- * @{
- */
-#define EXMC_DATABUS_WIDTH_8B ((uint32_t)0x00000000)
-#define EXMC_DATABUS_WIDTH_16B ((uint32_t)0x00000010)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_NORFlash_Access
- * @{
- */
-#define EXMC_NORFLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
-#define EXMC_NORFLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_BurstMode
- * @{
- */
-#define EXMC_BURST_MODE_DISABLE ((uint32_t)0x00000000)
-#define EXMC_BURST_MODE_ENABLE ((uint32_t)0x00000100)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_AsynWait
- * @{
- */
-#define EXMC_ASYN_WAIT_DISABLE ((uint32_t)0x00000000)
-#define EXMC_ASYN_WAIT_ENABLE ((uint32_t)0x00008000)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_NWAITPolarity
- * @{
- */
-#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000)
-#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_WrapBurstMode
- * @{
- */
-#define EXMC_WRAP_BURST_MODE_DISABLE ((uint32_t)0x00000000)
-#define EXMC_WRAP_BURST_MODE_ENABLE ((uint32_t)0x00000400)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_NWAITConfig
- * @{
- */
-#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000)
-#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_MemoryWrite
- * @{
- */
-#define EXMC_MEMORY_WRITE_DISABLE ((uint32_t)0x00000000)
-#define EXMC_MEMORY_WRITE_ENABLE ((uint32_t)0x00001000)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_NWAITSignal
- * @{
- */
-#define EXMC_NWAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define EXMC_NWAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_ExtendedMode
- * @{
- */
-#define EXMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define EXMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_WriteMode
- * @{
- */
-#define EXMC_ASYN_WRITE ((uint32_t)0x00000000)
-#define EXMC_SYN_WRITE ((uint32_t)0x00080000)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_AsynAccess_Mode
- * @{
- */
-#define EXMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define EXMC_ACCESS_MODE_B ((uint32_t)0x10000000)
-#define EXMC_ACCESS_MODE_C ((uint32_t)0x20000000)
-#define EXMC_ACCESS_MODE_D ((uint32_t)0x30000000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup EXMC_WaitFeature
- * @{
- */
-#define EXMC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define EXMC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_ECCLogic
- * @{
- */
-#define EXMC_ECC_LOGIC_DISABLE ((uint32_t)0x00000000)
-#define EXMC_ECC_LOGIC_ENABLE ((uint32_t)0x00000040)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_ECCSize
- * @{
- */
-#define EXMC_ECC_SIZE_256BYTES ((uint32_t)0x00000000)
-#define EXMC_ECC_SIZE_512BYTES ((uint32_t)0x00020000)
-#define EXMC_ECC_SIZE_1024BYTES ((uint32_t)0x00040000)
-#define EXMC_ECC_SIZE_2048BYTES ((uint32_t)0x00060000)
-#define EXMC_ECC_SIZE_4096BYTES ((uint32_t)0x00080000)
-#define EXMC_ECC_SIZE_8192BYTES ((uint32_t)0x000A0000)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_Interrupt_Source
- * @{
- */
-#define EXMC_INT_RISE ((uint32_t)0x00000008)
-#define EXMC_INT_LEVEL ((uint32_t)0x00000010)
-#define EXMC_INT_FALL ((uint32_t)0x00000020)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_FLAG
- * @{
- */
-#define EXMC_FLAG_RISE ((uint32_t)0x00000001)
-#define EXMC_FLAG_LEVEL ((uint32_t)0x00000002)
-#define EXMC_FLAG_FALL ((uint32_t)0x00000004)
-#define EXMC_FLAG_FIFOE ((uint32_t)0x00000040)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/** @defgroup EXMC_Exported_Functions
- * @{
- */
-void EXMC_NORSRAM_DeInit(uint32_t EXMC_NORSRAMBank);
-void EXMC_NAND_DeInit(uint32_t EXMC_NANDBank);
-void EXMC_PCCARD_DeInit(void);
-void EXMC_NORSRAM_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct);
-void EXMC_NAND_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct);
-void EXMC_PCCARD_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct);
-void EXMC_NORSRAMStruct_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct);
-void EXMC_NANDStruct_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct);
-void EXMC_PCCARDStruct_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct);
-void EXMC_NORSRAM_Enable(uint32_t EXMC_NORSRAMBank, TypeState NewValue);
-void EXMC_NAND_Enable(uint32_t EXMC_NANDBank, TypeState NewValue);
-void EXMC_PCCARD_Enable(TypeState NewValue);
-void EXMC_NANDECC_Enable(uint32_t EXMC_NANDBank, TypeState NewValue);
-uint32_t EXMC_GetECC(uint32_t EXMC_NANDBank);
-void EXMC_INTConfig(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT, TypeState NewValue);
-TypeState EXMC_GetBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG);
-void EXMC_ClearBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG);
-TypeState EXMC_GetIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT);
-void EXMC_ClearIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10x_EXMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h
deleted file mode 100644
index b36af10142..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
- ******************************************************************************
- * @brief EXTI header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_EXTI_H
-#define __GD32F10X_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-
-/** @defgroup EXTI_Exported_Types
- * @{
- */
-
-/**
- * @brief EXTI Mode enumeration
- */
-typedef enum {
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-} EXTI_ModePara;
-
-/**
- * @brief EXTI Trigger enumeration
- */
-typedef enum {
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-} EXTI_TriggerPara;
-
-/**
- * @brief EXTI Initial Parameters
- */
-typedef struct {
- uint32_t EXTI_LINE; /*!< The selection of EXTI lines. */
- EXTI_ModePara EXTI_Mode; /*!< The mode for the EXTI lines, detailed in @ref EXTIMode_Para. */
- EXTI_TriggerPara EXTI_Trigger; /*!< The trigger edge for the EXTI lines, detailed in EXTI_TriggerPara. */
- TypeState EXTI_LINEEnable; /*!< The new value of the selected EXTI lines. */
-} EXTI_InitPara;
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-
-/** @defgroup EXTI_lines
- * @{
- */
-#define EXTI_LINE0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
-#define EXTI_LINE1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
-#define EXTI_LINE2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
-#define EXTI_LINE3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
-#define EXTI_LINE4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
-#define EXTI_LINE5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
-#define EXTI_LINE6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
-#define EXTI_LINE7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
-#define EXTI_LINE8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
-#define EXTI_LINE9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
-#define EXTI_LINE10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
-#define EXTI_LINE11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
-#define EXTI_LINE12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
-#define EXTI_LINE13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
-#define EXTI_LINE14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
-#define EXTI_LINE15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
-
-#define EXTI_LINE16 ((uint32_t)0x00010000) /*!< External interrupt line 16
- Connected to the LVD */
-#define EXTI_LINE17 ((uint32_t)0x00020000) /*!< External interrupt line 17
- Connected to the RTC Alarm */
-#define EXTI_LINE18 ((uint32_t)0x00040000) /*!< External interrupt line 18
- Connected to the USB Wakeup */
-#define EXTI_LINE19 ((uint32_t)0x00080000) /*!< External interrupt line 19
- Connected to the Ethernet Wakeup */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Functions
- * @{
- */
-void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct);
-void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct);
-void EXTI_SWINT_Enable(uint32_t EXTI_LINE);
-TypeState EXTI_GetBitState(uint32_t EXTI_LINE);
-void EXTI_ClearBitState(uint32_t EXTI_LINE);
-TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE);
-void EXTI_ClearIntBitState(uint32_t EXTI_LINE);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_EXTI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h
deleted file mode 100644
index e57bf6b951..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/**
- ******************************************************************************
- * @brief FMC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_FMC_H
-#define __GD32F10X_FMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup FMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup FMC_Exported_Types
- * @{
- */
-
-/**
- * @brief FMC State
- */
-typedef enum {
- FMC_READY,
- FMC_BSY,
- FMC_WRPERR,
- FMC_PGERR,
- FMC_TIMEOUT_ERR
-} FMC_State;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FMC_Interrupts
- * @{
- */
-
-#define FMC_INT_EOP FMC_CMR_ENDIE /*!< End of programming interrupt source */
-#define FMC_INT_ERR FMC_CMR_ERIE /*!< Error interrupt source */
-#define FMC_INT_B2_EOP ((uint32_t)0x80000400) /*!< Bank2 End of programming interrupt source */
-#define FMC_INT_B2_ERR ((uint32_t)0x80001000) /*!< Bank2 Error interrupt source */
-/**
- * @}
- */
-
-/** @defgroup FMC_Option_Bytes_Write_Protection
- * @{
- */
-
-
-#define WRP_SECTOR0 ((uint32_t)0x00000001) /*!< Write protection of sector 0 */
-#define WRP_SECTOR1 ((uint32_t)0x00000002) /*!< Write protection of sector 1 */
-#define WRP_SECTOR2 ((uint32_t)0x00000004) /*!< Write protection of sector 2 */
-#define WRP_SECTOR3 ((uint32_t)0x00000008) /*!< Write protection of sector 3 */
-#define WRP_SECTOR4 ((uint32_t)0x00000010) /*!< Write protection of sector 4 */
-#define WRP_SECTOR5 ((uint32_t)0x00000020) /*!< Write protection of sector 5 */
-#define WRP_SECTOR6 ((uint32_t)0x00000040) /*!< Write protection of sector 6 */
-#define WRP_SECTOR7 ((uint32_t)0x00000080) /*!< Write protection of sector 7 */
-#define WRP_SECTOR8 ((uint32_t)0x00000100) /*!< Write protection of sector 8 */
-#define WRP_SECTOR9 ((uint32_t)0x00000200) /*!< Write protection of sector 9 */
-#define WRP_SECTOR10 ((uint32_t)0x00000400) /*!< Write protection of sector 10 */
-#define WRP_SECTOR11 ((uint32_t)0x00000800) /*!< Write protection of sector 11 */
-#define WRP_SECTOR12 ((uint32_t)0x00001000) /*!< Write protection of sector 12 */
-#define WRP_SECTOR13 ((uint32_t)0x00002000) /*!< Write protection of sector 13 */
-#define WRP_SECTOR14 ((uint32_t)0x00004000) /*!< Write protection of sector 14 */
-#define WRP_SECTOR15 ((uint32_t)0x00008000) /*!< Write protection of sector 15 */
-#define WRP_SECTOR16 ((uint32_t)0x00010000) /*!< Write protection of sector 16 */
-#define WRP_SECTOR17 ((uint32_t)0x00020000) /*!< Write protection of sector 17 */
-#define WRP_SECTOR18 ((uint32_t)0x00040000) /*!< Write protection of sector 18 */
-#define WRP_SECTOR19 ((uint32_t)0x00080000) /*!< Write protection of sector 19 */
-#define WRP_SECTOR20 ((uint32_t)0x00100000) /*!< Write protection of sector 20 */
-#define WRP_SECTOR21 ((uint32_t)0x00200000) /*!< Write protection of sector 21 */
-#define WRP_SECTOR22 ((uint32_t)0x00400000) /*!< Write protection of sector 22 */
-#define WRP_SECTOR23 ((uint32_t)0x00800000) /*!< Write protection of sector 23 */
-#define WRP_SECTOR24 ((uint32_t)0x01000000) /*!< Write protection of sector 24 */
-#define WRP_SECTOR25 ((uint32_t)0x02000000) /*!< Write protection of sector 25 */
-#define WRP_SECTOR26 ((uint32_t)0x04000000) /*!< Write protection of sector 26 */
-#define WRP_SECTOR27 ((uint32_t)0x08000000) /*!< Write protection of sector 27 */
-#define WRP_SECTOR28 ((uint32_t)0x10000000) /*!< Write protection of sector 28 */
-#define WRP_SECTOR29 ((uint32_t)0x20000000) /*!< Write protection of sector 29 */
-#define WRP_SECTOR30 ((uint32_t)0x40000000) /*!< Write protection of sector 30 */
-#define WRP_SECTOR31 ((uint32_t)0x80000000) /*!< Write protection of sector 31 */
-
-#define WRP_ALLSECTORS ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Option_Bytes_Read_Protection
- * @{
- */
-
-
-/**
- * @brief FMC_Read Protection Level
- */
-#define RDP_LEVEL_0 ((uint8_t)0xA5)
-#define RDP_LEVEL_1 ((uint8_t)0xBB)
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Option_Bytes_IWatchdog
- * @{
- */
-#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Option_Bytes_nRST_DEEPSLEEP
- * @{
- */
-#define OB_DEEPSLEEP_NORST ((uint8_t)0x02) /*!< No reset generated when entering in DEEPSLEEP */
-#define OB_DEEPSLEEP_RST ((uint8_t)0x00) /*!< Reset generated when entering in DEEPSLEEP */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Option_Bytes_nRST_STDBY
- * @{
- */
-#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Option_Bytes_BOOT
- * @{
- */
-#define OB_BOOT_B1 ((uint8_t)0x08) /*!< BOOT from Bank1 */
-#define OB_BOOT_B2 ((uint8_t)0x00) /*!< BOOT from Bank2 */
-#define OB_USER_BFB2 ((uint16_t)0x0008) /*!< Configure BOOT from Bank1 */
-/**
- * @}
- */
-
-
-
-/** @defgroup FMC_Flags
- * @{
- */
-
-#define FMC_FLAG_BSY FMC_CSR_BUSY /*!< FMC Busy flag */
-#define FMC_FLAG_PERR FMC_CSR_PGEF /*!< FMC Programming error flag */
-#define FMC_FLAG_WERR FMC_CSR_WPEF /*!< FMC Write protected error flag */
-#define FMC_FLAG_EOP FMC_CSR_ENDF /*!< FMC End of Programming flag */
-#define FMC_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FMC Option Byte error flag */
-#define FMC_FLAG_B2_BSY ((uint32_t)0x80000001) /*!< FMC Busy flag */
-#define FMC_FLAG_B2_PERR ((uint32_t)0x80000004) /*!< FMC Programming error flag */
-#define FMC_FLAG_B2_WERR ((uint32_t)0x80000010) /*!< FMC Write protected error flag */
-#define FMC_FLAG_B2_EOP ((uint32_t)0x80000020) /*!< FMC End of Programming flag */
-/**
- * @}
- */
-
-/** @defgroup FMC_Timeout_definition
- * @{
- */
-#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000)
-/**
- * @}
- */
-/* FMC BANK address */
-#define FMC_B1_END_ADDRESS ((uint32_t)0x807FFFF)
-#define FMC_BANK1_SIZE 0x0200
-#define FMC_SIZE (*(uint16_t *)0x1ffff7e0)
-/**
- * @}
- */
-
-/** @defgroup FMC_Exported_Functions
- * @{
- */
-
-/**
- * @brief FMC memory functions.
- */
-/* FMC Main Memory Programming functions *****************************************/
-void FMC_Unlock(void);
-void FMC_UnlockB1(void);
-void FMC_UnlockB2(void);
-void FMC_Lock(void);
-void FMC_LockB1(void);
-void FMC_LockB2(void);
-FMC_State FMC_ErasePage(uint32_t Page_Address);
-FMC_State FMC_MassErase(void);
-FMC_State FMC_MassB1Erase(void);
-FMC_State FMC_MassB2Erase(void);
-FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data);
-
-/* FMC Option Bytes Programming functions *****************************************/
-void FMC_OB_Unlock(void);
-void FMC_OB_Lock(void);
-void FMC_OB_Reset(void);
-FMC_State FMC_OB_Erase(void);
-FMC_State FMC_OB_EnableWRP(uint32_t OB_WRP);
-FMC_State FMC_ReadOutProtection(TypeState NewValue);
-FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP);
-FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY);
-FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT);
-FMC_State FMC_OB_WriteUser(uint8_t OB_USER);
-FMC_State FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data);
-uint8_t FMC_OB_GetUser(void);
-uint32_t FMC_OB_GetWRP(void);
-TypeState FMC_OB_GetRDP(void);
-
-/* FMC Interrupts and flags management functions **********************************/
-void FMC_INTConfig(uint32_t FMC_INT, TypeState NewValue);
-TypeState FMC_GetBitState(uint32_t FMC_FLAG);
-void FMC_ClearBitState(uint32_t FMC_FLAG);
-FMC_State FMC_GetState(void);
-FMC_State FMC_GetB1State(void);
-FMC_State FMC_GetB2State(void);
-FMC_State FMC_WaitReady(uint32_t uCount);
-FMC_State FMC_B1_WaitReady(uint32_t uCount);
-FMC_State FMC_B2_WaitReady(uint32_t uCount);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_FMC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h
deleted file mode 100644
index d32c81a7f9..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/**
- ******************************************************************************
- * @brief GPIO header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10x_GPIO_H
-#define __GD32F10x_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/** @defgroup GPIO_Exported_Types
- * @{
- */
-
-/**
- * @brief Output_Maximum_frequency_enumeration
- */
-typedef enum {
- GPIO_SPEED_10MHZ = 1,
- GPIO_SPEED_2MHZ,
- GPIO_SPEED_50MHZ
-} GPIO_SpeedPara;
-
-/**
- * @brief GPIO_Mode_enumeration
- */
-typedef enum {
- GPIO_MODE_AIN = 0x0,
- GPIO_MODE_IN_FLOATING = 0x04,
- GPIO_MODE_IPD = 0x28,
- GPIO_MODE_IPU = 0x48,
- GPIO_MODE_OUT_OD = 0x14,
- GPIO_MODE_OUT_PP = 0X10,
- GPIO_MODE_AF_OD = 0X1C,
- GPIO_MODE_AF_PP = 0X18
-} GPIO_ModePara;
-
-/**
- * @brief GPIO Initial Parameters
- */
-typedef struct {
- uint16_t GPIO_Pin; /*!< The GPIO pins to be configured. choose several from @ref GPIO_pins_define */
- GPIO_SpeedPara GPIO_Speed; /*!< The speed for This parameter can be a value of @ref GPIOSpeed_TypeDef */
- GPIO_ModePara GPIO_Mode; /*!< The operating mode for the selected pins. choose one from @ref GPIO_ModePara */
-} GPIO_InitPara;
-
-/**
- * @brief Bit_State_enumeration
- */
-typedef enum {
- Bit_RESET = 0,
- Bit_SET
-} BitState;
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001)
-#define GPIO_PIN_1 ((uint16_t)0x0002)
-#define GPIO_PIN_2 ((uint16_t)0x0004)
-#define GPIO_PIN_3 ((uint16_t)0x0008)
-#define GPIO_PIN_4 ((uint16_t)0x0010)
-#define GPIO_PIN_5 ((uint16_t)0x0020)
-#define GPIO_PIN_6 ((uint16_t)0x0040)
-#define GPIO_PIN_7 ((uint16_t)0x0080)
-#define GPIO_PIN_8 ((uint16_t)0x0100)
-#define GPIO_PIN_9 ((uint16_t)0x0200)
-#define GPIO_PIN_10 ((uint16_t)0x0400)
-#define GPIO_PIN_11 ((uint16_t)0x0800)
-#define GPIO_PIN_12 ((uint16_t)0x1000)
-#define GPIO_PIN_13 ((uint16_t)0x2000)
-#define GPIO_PIN_14 ((uint16_t)0x4000)
-#define GPIO_PIN_15 ((uint16_t)0x8000)
-#define GPIO_PIN_ALL ((uint16_t)0xFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Remap_define
- * @{
- */
-#define GPIO_REMAP_SPI1 ((uint32_t)0x00000001)
-#define GPIO_REMAP_I2C1 ((uint32_t)0x00000002)
-#define GPIO_REMAP_USART1 ((uint32_t)0x00000004)
-#define GPIO_REMAP_USART2 ((uint32_t)0x00000008)
-#define GPIO_PARTIAL_REMAP_USART3 ((uint32_t)0x00140010)
-#define GPIO_FULL_REMAP_USART3 ((uint32_t)0x00140030)
-#define GPIO_PARTIAL_REMAP_TIMER1 ((uint32_t)0x00160040)
-#define GPIO_FULL_REMAP_TIMER1 ((uint32_t)0x001600C0)
-#define GPIO_PARTIAL_REMAP1_TIMER2 ((uint32_t)0x00180100)
-#define GPIO_PARTIAL_REMAP2_TIMER2 ((uint32_t)0x00180200)
-#define GPIO_FULL_REMAP_TIMER2 ((uint32_t)0x00180300)
-#define GPIO_PARTIAL_REMAP_TIMER3 ((uint32_t)0x001A0800)
-#define GPIO_FULL_REMAP_TIMER3 ((uint32_t)0x001A0C00)
-#define GPIO_REMAP_TIMER4 ((uint32_t)0x00001000)
-#define GPIO_REMAP1_CAN1 ((uint32_t)0x001D4000)
-#define GPIO_REMAP2_CAN1 ((uint32_t)0x001D6000)
-#define GPIO_REMAP_PD01 ((uint32_t)0x00008000)
-#define GPIO_REMAP_TIMER5CH4_LSI ((uint32_t)0x00200001)
-#define GPIO_REMAP_ADC1_ETRGINJ ((uint32_t)0x00200002)
-#define GPIO_REMAP_ADC1_ETRGREG ((uint32_t)0x00200004)
-#define GPIO_REMAP_ADC2_ETRGINJ ((uint32_t)0x00200008)
-#define GPIO_REMAP_ADC2_ETRGREG ((uint32_t)0x00200010)
-#define GPIO_REMAP_ETH ((uint32_t)0x00200020)
-#define GPIO_REMAP_CAN2 ((uint32_t)0x00200040)
-#define GPIO_REMAP_SWJ_NOJTRST ((uint32_t)0x00300100)
-#define GPIO_REMAP_SWJ_JTAGDISABLE ((uint32_t)0x00300200)
-#define GPIO_REMAP_SWJ_DISABLE ((uint32_t)0x00300400)
-#define GPIO_REMAP_SPI3 ((uint32_t)0x00201100)
-#define GPIO_REMAP_TIMER2ITR1_PTP_SOF ((uint32_t)0x00202000)
-#define GPIO_REMAP_PTP_PPS ((uint32_t)0x00204000)
-#define GPIO_REMAP_TIMER15 ((uint32_t)0x80000001)
-#define GPIO_REMAP_TIMER16 ((uint32_t)0x80000002)
-#define GPIO_REMAP_TIMER17 ((uint32_t)0x80000004)
-#define GPIO_REMAP_CEC ((uint32_t)0x80000008)
-#define GPIO_REMAP_TIMER1_DMA ((uint32_t)0x80000010)
-#define GPIO_REMAP_TIMER9 ((uint32_t)0x80000020)
-#define GPIO_REMAP_TIMER10 ((uint32_t)0x80000040)
-#define GPIO_REMAP_TIMER11 ((uint32_t)0x80000080)
-#define GPIO_REMAP_TIMER13 ((uint32_t)0x80000100)
-#define GPIO_REMAP_TIMER14 ((uint32_t)0x80000200)
-#define GPIO_REMAP_EXMC_NADV ((uint32_t)0x80000400)
-#define GPIO_REMAP_TIMER67_DAC_DMA ((uint32_t)0x80000800)
-#define GPIO_REMAP_TIMER12 ((uint32_t)0x80001000)
-#define GPIO_REMAP_MISC ((uint32_t)0x80002000)
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Port_Sources
- * @{
- */
-#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00)
-#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01)
-#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02)
-#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03)
-#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04)
-#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05)
-#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06)
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PINSOURCE0 ((uint8_t)0x00)
-#define GPIO_PINSOURCE1 ((uint8_t)0x01)
-#define GPIO_PINSOURCE2 ((uint8_t)0x02)
-#define GPIO_PINSOURCE3 ((uint8_t)0x03)
-#define GPIO_PINSOURCE4 ((uint8_t)0x04)
-#define GPIO_PINSOURCE5 ((uint8_t)0x05)
-#define GPIO_PINSOURCE6 ((uint8_t)0x06)
-#define GPIO_PINSOURCE7 ((uint8_t)0x07)
-#define GPIO_PINSOURCE8 ((uint8_t)0x08)
-#define GPIO_PINSOURCE9 ((uint8_t)0x09)
-#define GPIO_PINSOURCE10 ((uint8_t)0x0A)
-#define GPIO_PINSOURCE11 ((uint8_t)0x0B)
-#define GPIO_PINSOURCE12 ((uint8_t)0x0C)
-#define GPIO_PINSOURCE13 ((uint8_t)0x0D)
-#define GPIO_PINSOURCE14 ((uint8_t)0x0E)
-#define GPIO_PINSOURCE15 ((uint8_t)0x0F)
-
-/**
- * @}
- */
-
-/** @defgroup Ethernet_Media_Interface
- * @{
- */
-#define GPIO_ETH_MEDIAINTERFACE_MII ((uint32_t)0x00000000)
-#define GPIO_ETH_MEDIAINTERFACE_RMII ((uint32_t)0x00800000)
-
-/**
- * @}
- */
-
-/* output mode definitions */
-#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
-#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
-#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
-#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
-#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
-
-/** @defgroup AFIO_Event_Output
- * @{
- */
-#define AFIO_ECR_EVOE_SET ((uint32_t)0x00000080)
-#define AFIO_ECR_EVOE_RESET ((uint32_t)0xffffff7f)
-
-/* gpio alternate function */
-#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
-#define GPIO_AF_0 AF(0) /*!< alternate function selected 0 */
-#define GPIO_AF_1 AF(1) /*!< alternate function selected 1 */
-#define GPIO_AF_2 AF(2) /*!< alternate function selected 2 */
-#define GPIO_AF_3 AF(3) /*!< alternate function selected 3 */
-#define GPIO_AF_4 AF(4) /*!< alternate function selected 4 */
-#define GPIO_AF_5 AF(5) /*!< alternate function selected 5 */
-#define GPIO_AF_6 AF(6) /*!< alternate function selected 6 */
-#define GPIO_AF_7 AF(7) /*!< alternate function selected 7 */
-#define GPIO_AF_8 AF(8) /*!< alternate function selected 8 */
-#define GPIO_AF_9 AF(9) /*!< alternate function selected 9 */
-#define GPIO_AF_10 AF(10) /*!< alternate function selected 10 */
-#define GPIO_AF_11 AF(11) /*!< alternate function selected 11 */
-#define GPIO_AF_12 AF(12) /*!< alternate function selected 12 */
-#define GPIO_AF_13 AF(13) /*!< alternate function selected 13 */
-#define GPIO_AF_14 AF(14) /*!< alternate function selected 14 */
-#define GPIO_AF_15 AF(15) /*!< alternate function selected 15 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions
- * @{
- */
-void GPIO_DeInit(GPIO_TypeDef *GPIOx);
-void GPIO_AFDeInit(void);
-void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitPara *GPIO_InitStruct);
-void GPIO_ParaInit(GPIO_InitPara *GPIO_InitStruct);
-uint8_t GPIO_ReadInputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
-uint8_t GPIO_ReadOutputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
-void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitState BitVal);
-void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
-void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
-void GPIO_EventOutputEnable(TypeState NewState);
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, TypeState NewState);
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h
deleted file mode 100644
index 8017f10a33..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/**
- ******************************************************************************
- * @brief I2C header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_I2C_H
-#define __GD32F10X_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/** @defgroup I2C_Exported_Types
- * @{
- */
-
-/**
- * @brief I2C Initial Parameters
- */
-typedef struct {
- uint16_t I2C_Protocol; /*!< The protocol type, detailed in @ref I2C_Protocol */
- uint16_t I2C_DutyCycle; /*!< The fast mode duty cycle, detailed in @ref I2C_Duty_Cycle */
- uint32_t I2C_BitRate; /*!< The I2C bit rate which must be lower than 400k bit/s */
- uint16_t I2C_AddressingMode; /*!< The I2C addressing mode, detailed in @ref I2C_Addressing_Mode */
- uint16_t I2C_DeviceAddress; /*!< The device address */
-} I2C_InitPara;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-/** @defgroup I2C_Protocol
- * @{
- */
-#define I2C_PROTOCOL_I2C ((uint16_t)0x0000)
-#define I2C_PROTOCOL_SMBUSDEVICE ((uint16_t)0x0002)
-#define I2C_PROTOCOL_SMBUSHOST ((uint16_t)0x000A)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Duty_Cycle
- * @{
- */
-#define I2C_DUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Addressing_Mode
- * @{
- */
-#define I2C_ADDRESSING_MODE_7BIT ((uint16_t)0x4000)
-#define I2C_ADDRESSING_MODE_10BIT ((uint16_t)0xC000)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Direction
- * @{
- */
-#define I2C_DIRECTION_TRANSMITTER ((uint8_t)0x00)
-#define I2C_DIRECTION_RECEIVER ((uint8_t)0x01)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Registers
- * @{
- */
-#define I2C_REGISTER_CTLR1 ((uint8_t)0x00)
-#define I2C_REGISTER_CTLR2 ((uint8_t)0x04)
-#define I2C_REGISTER_AR1 ((uint8_t)0x08)
-#define I2C_REGISTER_AR2 ((uint8_t)0x0C)
-#define I2C_REGISTER_DTR ((uint8_t)0x10)
-#define I2C_REGISTER_STR1 ((uint8_t)0x14)
-#define I2C_REGISTER_STR2 ((uint8_t)0x18)
-#define I2C_REGISTER_CLKR ((uint8_t)0x1C)
-#define I2C_REGISTER_RTR ((uint8_t)0x20)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_PEC_Position
- * @{
- */
-#define I2C_PECPOSITION_NEXT I2C_CTLR1_POAP
-#define I2C_PECPOSITION_CURRENT ((uint16_t)~I2C_CTLR1_POAP)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_NACK_Position
- * @{
- */
-#define I2C_NACKPOSITION_NEXT I2C_CTLR1_POAP
-#define I2C_NACKPOSITION_CURRENT ((uint16_t)~I2C_CTLR1_POAP)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_Control
- * @{
- */
-#define I2C_INT_EIE I2C_CTLR2_EIE
-#define I2C_INT_EE I2C_CTLR2_EE
-#define I2C_INT_BIE I2C_CTLR2_BIE
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_Source
- * @{
- */
-#define I2C_INT_SMBALTS ((uint32_t)0x01008000)
-#define I2C_INT_SMBTO ((uint32_t)0x01004000)
-#define I2C_INT_PECE ((uint32_t)0x01001000)
-#define I2C_INT_RXORE ((uint32_t)0x01000800)
-#define I2C_INT_AE ((uint32_t)0x01000400)
-#define I2C_INT_LOSTARB ((uint32_t)0x01000200)
-#define I2C_INT_BE ((uint32_t)0x01000100)
-#define I2C_INT_TBE ((uint32_t)0x06000080)
-#define I2C_INT_RBNE ((uint32_t)0x06000040)
-#define I2C_INT_STPSEND ((uint32_t)0x02000010)
-#define I2C_INT_ADD10SEND ((uint32_t)0x02000008)
-#define I2C_INT_BTC ((uint32_t)0x02000004)
-#define I2C_INT_ADDSEND ((uint32_t)0x02000002)
-#define I2C_INT_SBSEND ((uint32_t)0x02000001)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_FLAG
- * @{
- */
-
-/**
- * @brief STR2 register flags
- */
-#define I2C_FLAG_DUMODF ((uint32_t)0x00800000)
-#define I2C_FLAG_HSTSMB ((uint32_t)0x00400000)
-#define I2C_FLAG_DEFSMB ((uint32_t)0x00200000)
-#define I2C_FLAG_RXGC ((uint32_t)0x00100000)
-#define I2C_FLAG_TRS ((uint32_t)0x00040000)
-#define I2C_FLAG_I2CBSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MASTER ((uint32_t)0x00010000)
-
-/**
- * @brief STR1 register flags
- */
-#define I2C_FLAG_SMBALTS ((uint32_t)0x10008000)
-#define I2C_FLAG_SMBTO ((uint32_t)0x10004000)
-#define I2C_FLAG_PECE ((uint32_t)0x10001000)
-#define I2C_FLAG_RXORE ((uint32_t)0x10000800)
-#define I2C_FLAG_AE ((uint32_t)0x10000400)
-#define I2C_FLAG_LOSTARB ((uint32_t)0x10000200)
-#define I2C_FLAG_BE ((uint32_t)0x10000100)
-#define I2C_FLAG_TBE ((uint32_t)0x10000080)
-#define I2C_FLAG_RBNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STPSEND ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10SEND ((uint32_t)0x10000008)
-#define I2C_FLAG_BTC ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDSEND ((uint32_t)0x10000002)
-#define I2C_FLAG_SBSEND ((uint32_t)0x10000001)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_ProgrammingMode
- * @{
- */
-#define I2C_PROGRAMMINGMODE_MASTER_SBSEND ((uint32_t)0x00030001) /*!< I2CBSY, MASTER and SBSEND flag */
-
-#define I2C_PROGRAMMINGMODE_MASTER_TRANSMITTER_ADDSEND ((uint32_t)0x00070002) /*!< I2CBSY, MASTER, ADDSEND and TRS flags */
-#define I2C_PROGRAMMINGMODE_MASTER_RECEIVER_ADDSEND ((uint32_t)0x00030002) /*!< I2CBSY, MASTER and ADDSEND flags */
-
-#define I2C_PROGRAMMINGMODE_MASTER_ADD10SEND ((uint32_t)0x00030008) /*!< I2CBSY, MASTER and ADD10SEND flags */
-
-#define I2C_PROGRAMMINGMODE_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /*!< I2CBSY, MASTER and RBNE flags */
-#define I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /*!< TRS, I2CBSY, MASTER, TBE flags */
-#define I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /*!< TRS, I2CBSY, MASTER, TBE and BTC flags */
-
-#define I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_ADDSEND ((uint32_t)0x00020002) /*!< I2CBSY and ADDSEND flags */
-#define I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_ADDSEND ((uint32_t)0x00060002) /*!< TRS, I2CBSY and ADDSEND flags */
-
-#define I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_SECONDADDRESS_SELECTED ((uint32_t)0x00820000) /*!< DUMODF and I2CBSY flags */
-#define I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_SECONDADDRESS_SELECTED ((uint32_t)0x00860080) /*!< DUMODF, TRS, I2CBSY and TBE flags */
-
-#define I2C_PROGRAMMINGMODE_SLAVE_GENERALCALLADDRESS_SELECTED ((uint32_t)0x00120000) /*!< RXGC and I2CBSY flags */
-
-#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /*!< I2CBSY and RBNE flags */
-#define I2C_PROGRAMMINGMODE_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /*!< STPSEND flag */
-
-#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /*!< TRS, I2CBSY, TBE and BTC flags */
-#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /*!< TRS, I2CBSY and TBE flags */
-#define I2C_PROGRAMMINGMODE_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /*!< AE flag */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions
- * @{
- */
-void I2C_DeInit(I2C_TypeDef *I2Cx);
-void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitPara *I2C_InitParaStruct);
-void I2C_ParaInit(I2C_InitPara *I2C_InitParaStruct);
-void I2C_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_DMA_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_DMALastTransfer_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_StartOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_StopOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_Acknowledge_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_OwnAddress2(I2C_TypeDef *I2Cx, uint8_t Address);
-void I2C_DualAddress_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_GeneralCall_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, TypeState NewValue);
-void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
-void I2C_AddressingDevice_7bit(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
-uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
-void I2C_SoftwareReset_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_NACKPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertSend_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_PECTransmit_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_PECPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
-void I2C_PEC_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-uint8_t I2C_GetPECValue(I2C_TypeDef *I2Cx);
-void I2C_ARP_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_StretchClock_Enable(I2C_TypeDef *I2Cx, TypeState NewValue);
-void I2C_FastModeDutyCycle(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
-
-TypeState I2C_StateDetect(I2C_TypeDef *I2Cx, uint32_t I2C_State);
-uint32_t I2C_GetCurrentState(I2C_TypeDef *I2Cx);
-TypeState I2C_GetBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
-void I2C_ClearBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
-TypeState I2C_GetIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT);
-void I2C_ClearIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h
deleted file mode 100644
index 6d3e319fb7..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- ******************************************************************************
- * @brief IWDG header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_IWDG_H
-#define __GD32F10X_IWDG_H
-
-/* Exported macro ------------------------------------------------------------*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup IWDG
- * @{
- */
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-#define IWDG_WRITEACCESS_ENABLE ((uint16_t)0x5555)
-#define IWDG_WRITEACCESS_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-#define IWDG_PRESCALER_4 ((uint8_t)0x00)
-#define IWDG_PRESCALER_8 ((uint8_t)0x01)
-#define IWDG_PRESCALER_16 ((uint8_t)0x02)
-#define IWDG_PRESCALER_32 ((uint8_t)0x03)
-#define IWDG_PRESCALER_64 ((uint8_t)0x04)
-#define IWDG_PRESCALER_128 ((uint8_t)0x05)
-#define IWDG_PRESCALER_256 ((uint8_t)0x06)
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-#define IWDG_BIT_PUD IWDG_STR_PUD
-#define IWDG_BIT_RUD IWDG_STR_RUD
-#define IWDG_BIT_WUD IWDG_STR_WUD
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_functions
- * @{
- */
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_Write_Enable(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t PrescalerValue);
-void IWDG_SetReloadValue(uint16_t ReloadValue);
-void IWDG_ReloadCounter(void);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-TypeState IWDG_GetBitState(uint16_t IWDG_FLAG);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __IWDG_GD32F10X_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h
deleted file mode 100644
index f6f1f0902f..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- ******************************************************************************
- * @brief MCUDBG header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_MCUDBG_H
-#define __GD32F10X_MCUDBG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup MCUDBG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MCUDBG_Exported_Constants
- * @{
- */
-#define MCUDBG_SLEEP_HOLD ((uint32_t)0x00000001)
-#define MCUDBG_DEEPSLEEP_HOLD ((uint32_t)0x00000002)
-#define MCUDBG_STDBY_HOLD ((uint32_t)0x00000004)
-#define MCUDBG_IWDG_HOLD ((uint32_t)0x00000100)
-#define MCUDBG_WWDG_HOLD ((uint32_t)0x00000200)
-#define MCUDBG_TIMER1_HOLD ((uint32_t)0x00000400)
-#define MCUDBG_TIMER2_HOLD ((uint32_t)0x00000800)
-#define MCUDBG_TIMER3_HOLD ((uint32_t)0x00001000)
-#define MCUDBG_TIMER4_HOLD ((uint32_t)0x00002000)
-#define MCUDBG_CAN1_HOLD ((uint32_t)0x00004000)
-#define MCUDBG_I2C1_HOLD ((uint32_t)0x00008000)
-#define MCUDBG_I2C2_HOLD ((uint32_t)0x00010000)
-#define MCUDBG_TIMER5_HOLD ((uint32_t)0x00020000)
-#define MCUDBG_TIMER6_HOLD ((uint32_t)0x00040000)
-#define MCUDBG_TIMER7_HOLD ((uint32_t)0x00080000)
-#define MCUDBG_TIMER8_HOLD ((uint32_t)0x00100000)
-#define MCUDBG_CAN2_HOLD ((uint32_t)0x00200000)
-#define MCUDBG_TIMER12_HOLD ((uint32_t)0x02000000)
-#define MCUDBG_TIMER13_HOLD ((uint32_t)0x04000000)
-#define MCUDBG_TIMER14_HOLD ((uint32_t)0x08000000)
-#define MCUDBG_TIMER9_HOLD ((uint32_t)0x10000000)
-#define MCUDBG_TIMER10_HOLD ((uint32_t)0x20000000)
-#define MCUDBG_TIMER11_HOLD ((uint32_t)0x40000000)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/** @defgroup MCUDBG_Exported_Functions
- * @{
- */
-
-uint32_t MCUDBG_GetREVID(void);
-uint32_t MCUDBG_GetDEVID(void);
-void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_MCUDBG_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h
deleted file mode 100644
index 8ca8a6315f..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
- ******************************************************************************
- * @brief MISC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_MISC_H
-#define __GD32F10X_MISC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/** @defgroup MISC_Exported_Types
- * @{
- */
-
-/**
- * @brief MISC Initial Parameters
- */
-typedef struct {
- uint8_t NVIC_IRQ; /*!< The IRQ type,detailed in @ref IRQn_Type */
-
- uint8_t NVIC_IRQPreemptPriority; /*!< The pre-emption priority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */
-
- uint8_t NVIC_IRQSubPriority; /*!< The SubPriority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */
-
- TypeState NVIC_IRQEnable; /*!< Enable or disable the IRQ,this parameter can be ENABLE or DISABLE */
-
-} NVIC_InitPara;
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup MISC_System_Low_Power
- * @{
- */
-#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
-#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
-#define NVIC_LOWPOWER_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LOWPOWER_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LOWPOWER_SLEEPONEXIT ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Preemption_Priority_Group
- * @{
- */
-
-/* Preemption Priority Group -------------------------------------------------*/
-#define NVIC_PRIGROUP_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
-#define NVIC_PRIGROUP_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
-#define NVIC_PRIGROUP_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
-#define NVIC_PRIGROUP_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
-#define NVIC_PRIGROUP_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_SysTick_clock_source
- * @{
- */
-#define SYSTICK_CKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFB)
-#define SYSTICK_CKSOURCE_HCLK ((uint32_t)0x00000004)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Exported_Functions
- * @{
- */
-void NVIC_Init(NVIC_InitPara *NVIC_InitStruct);
-void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue);
-void SysTick_CKSource_Enable(uint32_t SysTick_CKSource);
-void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_MISC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h
deleted file mode 100644
index 36cd112d18..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- ******************************************************************************
- * @brief PWR header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_PWR_H
-#define __GD32F10X_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_Low_Voltage_Detector_Threshold
- * @{
- */
-#define PWR_LVDT_0 PWR_CTLR_LVDT_2V2
-#define PWR_LVDT_1 PWR_CTLR_LVDT_2V3
-#define PWR_LVDT_2 PWR_CTLR_LVDT_2V4
-#define PWR_LVDT_3 PWR_CTLR_LVDT_2V5
-#define PWR_LVDT_4 PWR_CTLR_LVDT_2V6
-#define PWR_LVDT_5 PWR_CTLR_LVDT_2V7
-#define PWR_LVDT_6 PWR_CTLR_LVDT_2V8
-#define PWR_LVDT_7 PWR_CTLR_LVDT_2V9
-
-/**
- * @}
- */
-
-/** @defgroup PWR_LDO_state_in_Deep-sleep_mode
- * @{
- */
-#define PWR_LDO_ON ((uint32_t)0x00000000)
-#define PWR_LDO_LOWPOWER PWR_CTLR_LDOLP
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Sleep_mode_entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Deep-sleep_mode_entry
- * @{
- */
-#define PWR_DEEPSLEEPENTRY_WFI ((uint8_t)0x01)
-#define PWR_DEEPSLEEPENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Standby_mode_entry
- * @{
- */
-#define PWR_STDBYENTRY_WFI ((uint8_t)0x01)
-#define PWR_STDBYENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-#define PWR_FLAG_WKUP PWR_STR_WUF
-#define PWR_FLAG_STB PWR_STR_SBF
-#define PWR_FLAG_LVDF PWR_STR_LVDF
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions
- * @{
- */
-void PWR_DeInit(void);
-void PWR_BackupAccess_Enable(TypeState NewValue);
-void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue);
-void PWR_WKUP_Pin_Enable(TypeState NewValue);
-void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY);
-void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY);
-void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY);
-TypeState PWR_GetBitState(uint32_t PWR_FLAG);
-void PWR_ClearBitState(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_PWR_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h
deleted file mode 100644
index 9772751542..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h
+++ /dev/null
@@ -1,690 +0,0 @@
-/**
- ******************************************************************************
- * @brief RCC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_RCC_H
-#define __GD32F10X_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/** @defgroup RCC_Exported_Types
- * @{
- */
-
-/**
- * @brief RCC Initial Parameters
- */
-
-typedef struct {
- uint32_t CK_SYS_Frequency; /*!< The frequency of the CK_SYS. */
- uint32_t AHB_Frequency; /*!< The frequency of the AHB. */
- uint32_t APB1_Frequency; /*!< The frequency of the APB1. */
- uint32_t APB2_Frequency; /*!< The frequency of the APB2. */
- uint32_t ADCCLK_Frequency; /*!< The frequency of the ADCCLK. */
-} RCC_ClocksPara;
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-
-#define RCC_HSE_OFF ((uint32_t)0x00000000)
-#define RCC_HSE_ON RCC_GCCR_HSEEN
-#define RCC_HSE_BYPASS RCC_GCCR_HSEEN | RCC_GCCR_HSEBPS
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_input_clock_source
- * @{
- */
-
-#define RCC_PLLSOURCE_HSI_DIV2 RCC_GCFGR_PLLSEL_HSI_DIV2
-
-#ifdef GD32F10X_CL
-#define RCC_PLLSOURCE_PREDIV1 RCC_GCFGR_PLLSEL_PREDIV1
-
-#else
-#define RCC_PLLSOURCE_HSE_DIV1 ((uint32_t)0x00010000)
-#define RCC_PLLSOURCE_HSE_DIV2 ((uint32_t)0x00030000)
-#endif /* GD32F10X_CL */
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Multiplication_factor
- * @{
- */
-
-
-#define RCC_PLLMUL_2 RCC_GCFGR_PLLMF2
-#define RCC_PLLMUL_3 RCC_GCFGR_PLLMF3
-#define RCC_PLLMUL_4 RCC_GCFGR_PLLMF4
-#define RCC_PLLMUL_5 RCC_GCFGR_PLLMF5
-#define RCC_PLLMUL_6 RCC_GCFGR_PLLMF6
-#define RCC_PLLMUL_7 RCC_GCFGR_PLLMF7
-#define RCC_PLLMUL_8 RCC_GCFGR_PLLMF8
-#define RCC_PLLMUL_9 RCC_GCFGR_PLLMF9
-#define RCC_PLLMUL_10 RCC_GCFGR_PLLMF10
-#define RCC_PLLMUL_11 RCC_GCFGR_PLLMF11
-#define RCC_PLLMUL_12 RCC_GCFGR_PLLMF12
-#define RCC_PLLMUL_13 RCC_GCFGR_PLLMF13
-#define RCC_PLLMUL_14 RCC_GCFGR_PLLMF14
-
-#define RCC_PLLMUL_16 RCC_GCFGR_PLLMF16
-#define RCC_PLLMUL_17 RCC_GCFGR_PLLMF17
-#define RCC_PLLMUL_18 RCC_GCFGR_PLLMF18
-#define RCC_PLLMUL_19 RCC_GCFGR_PLLMF19
-#define RCC_PLLMUL_20 RCC_GCFGR_PLLMF20
-#define RCC_PLLMUL_21 RCC_GCFGR_PLLMF21
-#define RCC_PLLMUL_22 RCC_GCFGR_PLLMF22
-#define RCC_PLLMUL_23 RCC_GCFGR_PLLMF23
-#define RCC_PLLMUL_24 RCC_GCFGR_PLLMF24
-#define RCC_PLLMUL_25 RCC_GCFGR_PLLMF25
-#define RCC_PLLMUL_26 RCC_GCFGR_PLLMF26
-#define RCC_PLLMUL_27 RCC_GCFGR_PLLMF27
-#define RCC_PLLMUL_28 RCC_GCFGR_PLLMF28
-#define RCC_PLLMUL_29 RCC_GCFGR_PLLMF29
-#define RCC_PLLMUL_30 RCC_GCFGR_PLLMF30
-#define RCC_PLLMUL_31 RCC_GCFGR_PLLMF31
-#define RCC_PLLMUL_32 RCC_GCFGR_PLLMF32
-
-#ifdef GD32F10X_CL
-#define RCC_PLLMUL_6_5 RCC_GCFGR_PLLMF6_5
-#else
-#define RCC_PLLMUL_15 RCC_GCFGR_PLLMF15
-
-#endif /* GD32F10X_CL */
-/**
- * @}
- */
-
-#ifdef GD32F10X_CL
-/** @defgroup RCC_PREDIV1_division_factor
- * @{
- */
-
-#define RCC_PREDIV1_DIV1 RCC_GCFGR2_PREDV1_DIV1
-#define RCC_PREDIV1_DIV2 RCC_GCFGR2_PREDV1_DIV2
-#define RCC_PREDIV1_DIV3 RCC_GCFGR2_PREDV1_DIV3
-#define RCC_PREDIV1_DIV4 RCC_GCFGR2_PREDV1_DIV4
-#define RCC_PREDIV1_DIV5 RCC_GCFGR2_PREDV1_DIV5
-#define RCC_PREDIV1_DIV6 RCC_GCFGR2_PREDV1_DIV6
-#define RCC_PREDIV1_DIV7 RCC_GCFGR2_PREDV1_DIV7
-#define RCC_PREDIV1_DIV8 RCC_GCFGR2_PREDV1_DIV8
-#define RCC_PREDIV1_DIV9 RCC_GCFGR2_PREDV1_DIV9
-#define RCC_PREDIV1_DIV10 RCC_GCFGR2_PREDV1_DIV10
-#define RCC_PREDIV1_DIV11 RCC_GCFGR2_PREDV1_DIV11
-#define RCC_PREDIV1_DIV12 RCC_GCFGR2_PREDV1_DIV12
-#define RCC_PREDIV1_DIV13 RCC_GCFGR2_PREDV1_DIV13
-#define RCC_PREDIV1_DIV14 RCC_GCFGR2_PREDV1_DIV14
-#define RCC_PREDIV1_DIV15 RCC_GCFGR2_PREDV1_DIV15
-#define RCC_PREDIV1_DIV16 RCC_GCFGR2_PREDV1_DIV16
-
-/**
- * @}
- */
-
-
-/** @defgroup RCC_PREDIV1_clock_source
- * @{
- */
-
-#define RCC_PREDIV1_SOURCE_HSE RCC_GCFGR2_PREDV1SEL_HSE
-#define RCC_PREDIV1_SOURCE_PLL2 RCC_GCFGR2_PREDV1SEL_PLL2
-
-/**
- * @}
- */
-
-
-/** @defgroup RCC_PREDIV2_division_factor
- * @{
- */
-#define RCC_PREDIV2_DIV1 RCC_GCFGR2_PREDV2_DIV1
-#define RCC_PREDIV2_DIV2 RCC_GCFGR2_PREDV2_DIV2
-#define RCC_PREDIV2_DIV3 RCC_GCFGR2_PREDV2_DIV3
-#define RCC_PREDIV2_DIV4 RCC_GCFGR2_PREDV2_DIV4
-#define RCC_PREDIV2_DIV5 RCC_GCFGR2_PREDV2_DIV5
-#define RCC_PREDIV2_DIV6 RCC_GCFGR2_PREDV2_DIV6
-#define RCC_PREDIV2_DIV7 RCC_GCFGR2_PREDV2_DIV7
-#define RCC_PREDIV2_DIV8 RCC_GCFGR2_PREDV2_DIV8
-#define RCC_PREDIV2_DIV9 RCC_GCFGR2_PREDV2_DIV9
-#define RCC_PREDIV2_DIV10 RCC_GCFGR2_PREDV2_DIV10
-#define RCC_PREDIV2_DIV11 RCC_GCFGR2_PREDV2_DIV11
-#define RCC_PREDIV2_DIV12 RCC_GCFGR2_PREDV2_DIV12
-#define RCC_PREDIV2_DIV13 RCC_GCFGR2_PREDV2_DIV13
-#define RCC_PREDIV2_DIV14 RCC_GCFGR2_PREDV2_DIV14
-#define RCC_PREDIV2_DIV15 RCC_GCFGR2_PREDV2_DIV15
-#define RCC_PREDIV2_DIV16 RCC_GCFGR2_PREDV2_DIV16
-
-/**
- * @}
- */
-
-
-/** @defgroup RCC_PLL2_multiplication_factor
- * @{
- */
-#define RCC_PLL2MUL_8 RCC_GCFGR2_PLL2MF8
-#define RCC_PLL2MUL_9 RCC_GCFGR2_PLL2MF9
-#define RCC_PLL2MUL_10 RCC_GCFGR2_PLL2MF10
-#define RCC_PLL2MUL_11 RCC_GCFGR2_PLL2MF11
-#define RCC_PLL2MUL_12 RCC_GCFGR2_PLL2MF12
-#define RCC_PLL2MUL_13 RCC_GCFGR2_PLL2MF13
-#define RCC_PLL2MUL_14 RCC_GCFGR2_PLL2MF14
-#define RCC_PLL2MUL_16 RCC_GCFGR2_PLL2MF16
-#define RCC_PLL2MUL_20 RCC_GCFGR2_PLL2MF20
-
-/**
- * @}
- */
-
-
-/** @defgroup RCC_PLL3_multiplication_factor
- * @{
- */
-#define RCC_PLL3MUL_8 RCC_GCFGR2_PLL3MF8
-#define RCC_PLL3MUL_9 RCC_GCFGR2_PLL3MF9
-#define RCC_PLL3MUL_10 RCC_GCFGR2_PLL3MF10
-#define RCC_PLL3MUL_11 RCC_GCFGR2_PLL3MF11
-#define RCC_PLL3MUL_12 RCC_GCFGR2_PLL3MF12
-#define RCC_PLL3MUL_13 RCC_GCFGR2_PLL3MF13
-#define RCC_PLL3MUL_14 RCC_GCFGR2_PLL3MF14
-#define RCC_PLL3MUL_16 RCC_GCFGR2_PLL3MF16
-#define RCC_PLL3MUL_20 RCC_GCFGR2_PLL3MF20
-
-/**
- * @}
- */
-#endif /* GD32F10X_CL */
-
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_GCFGR_SCS_HSI
-#define RCC_SYSCLKSOURCE_HSE RCC_GCFGR_SCS_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_GCFGR_SCS_PLL
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_GCFGR_AHBPS_DIV1
-#define RCC_SYSCLK_DIV2 RCC_GCFGR_AHBPS_DIV2
-#define RCC_SYSCLK_DIV4 RCC_GCFGR_AHBPS_DIV4
-#define RCC_SYSCLK_DIV8 RCC_GCFGR_AHBPS_DIV8
-#define RCC_SYSCLK_DIV16 RCC_GCFGR_AHBPS_DIV16
-#define RCC_SYSCLK_DIV64 RCC_GCFGR_AHBPS_DIV64
-#define RCC_SYSCLK_DIV128 RCC_GCFGR_AHBPS_DIV128
-#define RCC_SYSCLK_DIV256 RCC_GCFGR_AHBPS_DIV256
-#define RCC_SYSCLK_DIV512 RCC_GCFGR_AHBPS_DIV512
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB_Clock_Source
- * @{
- */
-#define RCC_APB1AHB_DIV1 RCC_GCFGR_APB1PS_DIV1
-#define RCC_APB1AHB_DIV2 RCC_GCFGR_APB1PS_DIV2
-#define RCC_APB1AHB_DIV4 RCC_GCFGR_APB1PS_DIV4
-#define RCC_APB1AHB_DIV8 RCC_GCFGR_APB1PS_DIV8
-#define RCC_APB1AHB_DIV16 RCC_GCFGR_APB1PS_DIV16
-
-#define RCC_APB2AHB_DIV1 RCC_GCFGR_APB2PS_DIV1
-#define RCC_APB2AHB_DIV2 RCC_GCFGR_APB2PS_DIV2
-#define RCC_APB2AHB_DIV4 RCC_GCFGR_APB2PS_DIV4
-#define RCC_APB2AHB_DIV8 RCC_GCFGR_APB2PS_DIV8
-#define RCC_APB2AHB_DIV16 RCC_GCFGR_APB2PS_DIV16
-/**
- * @}
- */
-
-/** @defgroup RCC_ADC_clock_source
- * @{
- */
-#define RCC_ADCCLK_APB2_DIV2 RCC_GCFGR_ADCPS_DIV2
-#define RCC_ADCCLK_APB2_DIV4 RCC_GCFGR_ADCPS_DIV4
-#define RCC_ADCCLK_APB2_DIV6 RCC_GCFGR_ADCPS_DIV6
-#define RCC_ADCCLK_APB2_DIV8 RCC_GCFGR_ADCPS_DIV8
-#define RCC_ADCCLK_APB2_DIV12 RCC_GCFGR_ADCPS_DIV12
-#define RCC_ADCCLK_APB2_DIV16 RCC_GCFGR_ADCPS_DIV16
-
-/**
- * @}
- */
-
-#ifdef GD32F10X_CL
-/** @defgroup RCC_USB_OTG_clock_source
- * @{
- */
-#define RCC_OTGCLK_PLL_DIV1 RCC_GCFGR_OTGFSPS_Div1
-#define RCC_OTGCLK_PLL_DIV1_5 RCC_GCFGR_OTGFSPS_Div1_5
-#define RCC_OTGCLK_PLL_DIV2 RCC_GCFGR_OTGFSPS_Div2
-#define RCC_OTGCLK_PLL_DIV2_5 RCC_GCFGR_OTGFSPS_Div2_5
-
-/**
- * @}
- */
-
-#else
-/** @defgroup RCC_USB_clock_source
- * @{
- */
-#define RCC_USBCLK_PLL_DIV1 RCC_GCFGR_USBPS_Div1
-#define RCC_USBCLK_PLL_DIV1_5 RCC_GCFGR_USBPS_Div1_5
-#define RCC_USBCLK_PLL_DIV2 RCC_GCFGR_USBPS_Div2
-#define RCC_USBCLK_PLL_DIV2_5 RCC_GCFGR_USBPS_Div2_5
-
-/**
- * @}
- */
-#endif /* GD32F10X_CL */
-
-
-
-/** @defgroup RCC_CK_OUT_Clock_Source
- * @{
- */
-#ifdef GD32F10X_CL
-#define RCC_CKOUTSRC_NOCLOCK RCC_GCFGR_CKOUTSEL_NoClock
-#define RCC_CKOUTSRC_SYSCLK RCC_GCFGR_CKOUTSEL_SYSCLK
-#define RCC_CKOUTSRC_HSI RCC_GCFGR_CKOUTSEL_HSI
-#define RCC_CKOUTSRC_HSE RCC_GCFGR_CKOUTSEL_HSE
-#define RCC_CKOUTSRC_PLLCLK_DIV2 RCC_GCFGR_CKOUTSEL_PLL_DIV2
-#define RCC_CKOUTSRC_PLL2CLK RCC_GCFGR_CKOUTSEL_PLL2
-#define RCC_CKOUTSRC_PLL3CLK RCC_GCFGR_CKOUTSEL_PLL3
-#define RCC_CKOUTSRC_PLL3CLK_DIV2 RCC_GCFGR_CKOUTSEL_PLL3_DIV2
-#define RCC_CKOUTSRC_EXT1 RCC_GCFGR_CKOUTSEL_EXT1
-
-#else
-#define RCC_CKOUTSRC_NOCLOCK RCC_GCFGR_CKOUTSEL_NoClock
-#define RCC_CKOUTSRC_SYSCLK RCC_GCFGR_CKOUTSEL_SYSCLK
-#define RCC_CKOUTSRC_HSI RCC_GCFGR_CKOUTSEL_HSI
-#define RCC_CKOUTSRC_HSE RCC_GCFGR_CKOUTSEL_HSE
-#define RCC_CKOUTSRC_PLLCLK_DIV2 RCC_GCFGR_CKOUTSEL_PLL_DIV2
-
-#endif /* GD32F10X_CL */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-#define RCC_INT_LSISTB ((uint8_t)0x01)
-#define RCC_INT_LSESTB ((uint8_t)0x02)
-#define RCC_INT_HSISTB ((uint8_t)0x04)
-#define RCC_INT_HSESTB ((uint8_t)0x08)
-#define RCC_INT_PLLSTB ((uint8_t)0x10)
-#define RCC_INT_CKM ((uint8_t)0x80)
-
-#ifdef GD32F10X_CL
-#define RCC_INT_PLL2STB ((uint8_t)0x20)
-#define RCC_INT_PLL3STB ((uint8_t)0x40)
-#endif /* GD32F10X_CL */
-
-/**
- * @}
- */
-
-#ifdef GD32F10X_CL
-/** @defgroup RCC_I2S2_clock_source
- * @{
- */
-#define RCC_I2S2CLK_SYSCLK RCC_GCFGR2_I2S2SEL_CK_SYS
-#define RCC_I2S2CLK_PLL3 RCC_GCFGR2_I2S2SEL_PLL3
-
-/**
- * @}
- */
-
-/** @defgroup RCC_I2S3_clock_source
- * @{
- */
-#define RCC_I2S3CLK_SYSCLK RCC_GCFGR2_I2S3SEL_CK_SYS
-#define RCC_I2S3CLK_PLL3 RCC_GCFGR2_I2S3SEL_PLL3
-
-/**
- * @}
- */
-#endif /* GD32F10X_CL */
-
-
-
-/** @defgroup RCC_LSE_configuration
- * @{
- */
-#define RCC_LSE_OFF ((uint32_t)0x00000000)
-#define RCC_LSE_EN RCC_BDCR_LSEEN
-#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEEN | RCC_BDCR_LSEBPS))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_clock_source
- * @{
- */
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE128
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_peripheral
- * @{
- */
-#define RCC_AHBPERIPH_DMA1 RCC_AHBCCR_DMA1EN
-#define RCC_AHBPERIPH_DMA2 RCC_AHBCCR_DMA2EN
-#define RCC_AHBPERIPH_SRAM RCC_AHBCCR_SRAMEN
-#define RCC_AHBPERIPH_FMC RCC_AHBCCR_FMCEN
-#define RCC_AHBPERIPH_CRC RCC_AHBCCR_CRCEN
-#define RCC_AHBPERIPH_EXMC RCC_AHBCCR_EXMCEN
-
-#ifdef GD32F10X_CL
-#define RCC_AHBPERIPH_OTG_FS RCC_AHBCCR_OTGFSEN
-#define RCC_AHBPERIPH_ETH_MAC RCC_AHBCCR_ETHMACEN
-#define RCC_AHBPERIPH_ETH_MAC_RX RCC_AHBCCR_ETHMACRXEN
-#define RCC_AHBPERIPH_ETH_MAC_TX RCC_AHBCCR_ETHMACTXEN
-
-#else
-#define RCC_AHBPERIPH_SDIO RCC_AHBCCR_SDIOEN
-#endif/* GD32F10X_CL */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripherals_RST
- * @{
- */
-#ifdef GD32F10X_CL
-#define RCC_AHBPERIPH_OTGFSRST RCC_AHBRCR_OTGFSRST
-#define RCC_AHBPERIPH_ETHMACRST RCC_AHBRCR_ETHMACRST
-
-#endif/* GD32F10X_CL */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_peripheral
- * @{
- */
-#define RCC_APB2PERIPH_AF RCC_APB2CCR_AFEN
-#define RCC_APB2PERIPH_GPIOA RCC_APB2CCR_PAEN
-#define RCC_APB2PERIPH_GPIOB RCC_APB2CCR_PBEN
-#define RCC_APB2PERIPH_GPIOC RCC_APB2CCR_PCEN
-#define RCC_APB2PERIPH_GPIOD RCC_APB2CCR_PDEN
-#define RCC_APB2PERIPH_GPIOE RCC_APB2CCR_PEEN
-#define RCC_APB2PERIPH_GPIOF RCC_APB2CCR_PFEN
-#define RCC_APB2PERIPH_GPIOG RCC_APB2CCR_PGEN
-#define RCC_APB2PERIPH_ADC0 RCC_APB2CCR_ADC0EN
-#define RCC_APB2PERIPH_ADC1 RCC_APB2CCR_ADC1EN
-#define RCC_APB2PERIPH_TIMER0 RCC_APB2CCR_TIMER0EN
-#define RCC_APB2PERIPH_SPI1 RCC_APB2CCR_SPI1EN
-#define RCC_APB2PERIPH_TIMER7 RCC_APB2CCR_TIMER7EN
-#define RCC_APB2PERIPH_USART1 RCC_APB2CCR_USART1EN
-#define RCC_APB2PERIPH_ADC2 RCC_APB2CCR_ADC2EN
-#define RCC_APB2PERIPH_TIMER8 RCC_APB2CCR_TIMER8EN
-#define RCC_APB2PERIPH_TIMER9 RCC_APB2CCR_TIMER9EN
-#define RCC_APB2PERIPH_TIMER10 RCC_APB2CCR_TIMER10EN
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals_RST
- * @{
- */
-#define RCC_APB2PERIPH_AFRST RCC_APB2RCR_AFRST
-#define RCC_APB2PERIPH_GPIOARST RCC_APB2RCR_PARST
-#define RCC_APB2PERIPH_GPIOBRST RCC_APB2RCR_PBRST
-#define RCC_APB2PERIPH_GPIOCRST RCC_APB2RCR_PCRST
-#define RCC_APB2PERIPH_GPIODRST RCC_APB2RCR_PDRST
-#define RCC_APB2PERIPH_GPIOERST RCC_APB2RCR_PERST
-#define RCC_APB2PERIPH_GPIOFRST RCC_APB2RCR_PFRST
-#define RCC_APB2PERIPH_GPIOGRST RCC_APB2RCR_PGRST
-#define RCC_APB2PERIPH_ADC0RST RCC_APB2RCR_ADC0RST
-#define RCC_APB2PERIPH_ADC1RST RCC_APB2RCR_ADC1RST
-#define RCC_APB2PERIPH_TIMER0RST RCC_APB2RCR_TIMER0RST
-#define RCC_APB2PERIPH_SPI1RST RCC_APB2RCR_SPI1RST
-#define RCC_APB2PERIPH_TIMER7RST RCC_APB2RCR_TIMER7RST
-#define RCC_APB2PERIPH_USART0RST RCC_APB2RCR_USART0RST
-#define RCC_APB2PERIPH_ADC2RST RCC_APB2RCR_ADC2RST
-#define RCC_APB2PERIPH_TIMER8RST RCC_APB2RCR_TIMER8RST
-#define RCC_APB2PERIPH_TIMER9RST RCC_APB2RCR_TIMER9RST
-#define RCC_APB2PERIPH_TIMER10RST RCC_APB2RCR_TIMER10RST
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_peripheral
- * @{
- */
-#define RCC_APB1PERIPH_TIMER1 RCC_APB1CCR_TIMER1EN
-#define RCC_APB1PERIPH_TIMER2 RCC_APB1CCR_TIMER2EN
-#define RCC_APB1PERIPH_TIMER3 RCC_APB1CCR_TIMER3EN
-#define RCC_APB1PERIPH_TIMER4 RCC_APB1CCR_TIMER4EN
-#define RCC_APB1PERIPH_TIMER5 RCC_APB1CCR_TIMER5EN
-#define RCC_APB1PERIPH_TIMER6 RCC_APB1CCR_TIMER6EN
-#define RCC_APB1PERIPH_TIMER11 RCC_APB1CCR_TIMER11EN
-#define RCC_APB1PERIPH_TIMER12 RCC_APB1CCR_TIMER12EN
-#define RCC_APB1PERIPH_TIMER13 RCC_APB1CCR_TIMER13EN
-#define RCC_APB1PERIPH_WWDG RCC_APB1CCR_WWDGEN
-#define RCC_APB1PERIPH_SPI2 RCC_APB1CCR_SPI2EN
-#define RCC_APB1PERIPH_SPI3 RCC_APB1CCR_SPI3EN
-#define RCC_APB1PERIPH_USART2 RCC_APB1CCR_USART2EN
-#define RCC_APB1PERIPH_USART3 RCC_APB1CCR_USART3EN
-#define RCC_APB1PERIPH_UART4 RCC_APB1CCR_UART4EN
-#define RCC_APB1PERIPH_UART5 RCC_APB1CCR_UART5EN
-#define RCC_APB1PERIPH_I2C1 RCC_APB1CCR_I2C1EN
-#define RCC_APB1PERIPH_I2C2 RCC_APB1CCR_I2C2EN
-#define RCC_APB1PERIPH_USB RCC_APB1CCR_USBEN
-#define RCC_APB1PERIPH_CAN1 RCC_APB1CCR_CAN1EN
-#define RCC_APB1PERIPH_CAN2 RCC_APB1CCR_CAN2EN
-#define RCC_APB1PERIPH_BKP RCC_APB1CCR_BKPEN
-#define RCC_APB1PERIPH_PWR RCC_APB1CCR_PWREN
-#define RCC_APB1PERIPH_DAC RCC_APB1CCR_DACEN
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals_RST
- * @{
- */
-#define RCC_APB1PERIPH_TIMER1RST RCC_APB1RCR_TIMER1RST
-#define RCC_APB1PERIPH_TIMER2RST RCC_APB1RCR_TIMER2RST
-#define RCC_APB1PERIPH_TIMER3RST RCC_APB1RCR_TIMER3RST
-#define RCC_APB1PERIPH_TIMER4RST RCC_APB1RCR_TIMER4RST
-#define RCC_APB1PERIPH_TIMER5RST RCC_APB1RCR_TIMER5RST
-#define RCC_APB1PERIPH_TIMER6RST RCC_APB1RCR_TIMER6RST
-#define RCC_APB1PERIPH_TIMER11RST RCC_APB1RCR_TIMER11RST
-#define RCC_APB1PERIPH_TIMER12RST RCC_APB1RCR_TIMER12RST
-#define RCC_APB1PERIPH_TIMER13RST RCC_APB1RCR_TIMER13RST
-#define RCC_APB1PERIPH_WWDGRST RCC_APB1RCR_WWDGRST
-#define RCC_APB1PERIPH_SPI2RST RCC_APB1RCR_SPI2RST
-#define RCC_APB1PERIPH_SPI3RST RCC_APB1RCR_SPI3RST
-#define RCC_APB1PERIPH_USART1RST RCC_APB1RCR_USART1RST
-#define RCC_APB1PERIPH_USART2RST RCC_APB1RCR_USART2RST
-#define RCC_APB1PERIPH_UART3RST RCC_APB1RCR_UART3RST
-#define RCC_APB1PERIPH_UART4RST RCC_APB1RCR_UART4RST
-#define RCC_APB1PERIPH_I2C1RST RCC_APB1RCR_I2C1RST
-#define RCC_APB1PERIPH_I2C2RST RCC_APB1RCR_I2C2RST
-#define RCC_APB1PERIPH_USBRST RCC_APB1RCR_USBRST
-#define RCC_APB1PERIPH_CAN1RST RCC_APB1RCR_CAN1RST
-#define RCC_APB1PERIPH_CAN2RST RCC_APB1RCR_CAN2RST
-#define RCC_APB1PERIPH_BKPRST RCC_APB1RCR_BKPRST
-#define RCC_APB1PERIPH_PWRRST RCC_APB1RCR_PWRRST
-#define RCC_APB1PERIPH_DACRST RCC_APB1RCR_DACRST
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-/* The flag to check is in GCCR register */
-#define RCC_FLAG_HSISTB ((uint8_t)0x21)
-#define RCC_FLAG_HSESTB ((uint8_t)0x31)
-#define RCC_FLAG_PLLSTB ((uint8_t)0x39)
-
-/* The flag to check is in BDCR register */
-#define RCC_FLAG_LSESTB ((uint8_t)0x41)
-
-/* The flag to check is in GCSR register */
-#define RCC_FLAG_LSISTB ((uint8_t)0x61)
-
-#define RCC_FLAG_EPRST ((uint8_t)0x7A)
-#define RCC_FLAG_POPDRST ((uint8_t)0x7B)
-#define RCC_FLAG_SWRRST ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
-#define RCC_FLAG_LPRRST ((uint8_t)0x7F)
-
-#ifdef GD32F10X_CL
-/* The flag to check is in GCCR register */
-#define RCC_FLAG_PLL2STB ((uint8_t)0x3B)
-#define RCC_FLAG_PLL3STB ((uint8_t)0x3D)
-
-#endif/* GD32F10X_CL */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions
- * @{
- */
-/* Reset the RCC clock configuration to the default reset state */
-
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CKM and CK_OUT configuration functions */
-
-void RCC_HSEConfig(uint32_t RCC_HSE);
-TypeState RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSI_Enable(TypeState NewValue);
-void RCC_PLLConfig(uint32_t RCC_PLLSelect, uint32_t RCC_PLLMF);
-void RCC_PLL_Enable(TypeState NewValue);
-void RCC_LSEConfig(uint32_t RCC_LSE);
-void RCC_LSI_Enable(TypeState NewValue);
-void RCC_HSEClockMonitor_Enable(TypeState NewValue);
-void RCC_CKOUTSRCConfig(uint32_t RCC_CKOUTSRC);
-
-#ifdef GD32F10X_CL
-void RCC_PREDV1Config(uint32_t RCC_PREDV1_Source, uint32_t RCC_PREDV1_Div);
-void RCC_PREDV2Config(uint32_t RCC_PREDV2_Div);
-void RCC_PLL2Config(uint32_t RCC_PLL2MF);
-void RCC_PLL2_Enable(TypeState NewValue);
-void RCC_PLL3Config(uint32_t RCC_PLL3MF);
-void RCC_PLL3_Enable(TypeState NewValue);
-#endif /* GD32F10X_CL */
-
-/* System, AHB, APB1 and APB2 busses clocks configuration functions */
-
-void RCC_CK_SYSConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetCK_SYSSource(void);
-void RCC_AHBConfig(uint32_t RCC_CK_SYSDiv);
-void RCC_APB1Config(uint32_t RCC_APB1);
-void RCC_APB2Config(uint32_t RCC_APB2);
-
-#ifndef GD32F10X_CL
-void RCC_USBCLKConfig(uint32_t RCC_USBCLK);
-#else
-void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLK);
-#endif /* GD32F10X_CL */
-
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK);
-
-#ifdef GD32F10X_CL
-void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLK);
-void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLK);
-#endif /* GD32F10X_CL */
-
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_GetClocksFreq(RCC_ClocksPara *RCC_Clocks);
-
-/* Peripheral clocks configuration functions */
-
-void RCC_AHBPeriphClock_Enable(uint32_t RCC_AHBPeriph, TypeState NewValue);
-void RCC_APB2PeriphClock_Enable(uint32_t RCC_APB2Periph, TypeState NewValue);
-void RCC_APB1PeriphClock_Enable(uint32_t RCC_APB1Periph, TypeState NewValue);
-void RCC_RTCCLK_Enable(TypeState NewValue);
-
-#ifdef GD32F10X_CL
-void RCC_AHBPeriphReset_Enable(uint32_t RCC_AHBPeriphRST, TypeState NewValue);
-#endif /* GD32F10X_CL */
-
-void RCC_APB2PeriphReset_Enable(uint32_t RCC_APB2PeriphRST, TypeState NewValue);
-void RCC_APB1PeriphReset_Enable(uint32_t RCC_APB1PeriphRST, TypeState NewValue);
-void RCC_BackupReset_Enable(TypeState NewValue);
-
-/* Interrupts and flags management functions */
-
-void RCC_INTConfig(uint8_t RCC_INT, TypeState NewValue);
-TypeState RCC_GetIntBitState(uint8_t RCC_INT);
-void RCC_ClearIntBitState(uint8_t RCC_INT);
-TypeState RCC_GetBitState(uint8_t RCC_FLAG);
-void RCC_ClearBitState(void);
-
-void RCC_KERNELVOLConfig(uint32_t RCC_KERNEL_VOL);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10x_RCC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h
deleted file mode 100644
index d63ce98930..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h
+++ /dev/null
@@ -1,1019 +0,0 @@
-/*!
- \file gd32f10x_rcu.h
- \brief definitions for the RCU
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2017-02-10, V1.0.1, firmware for GD32F30x
- 2021-01-02, firmware for GD32F10x
-*/
-
-#ifndef GD32F10X_RCU_H
-#define GD32F10X_RCU_H
-
-#include "gd32f10x.h"
-
-/* RCU definitions */
-#define RCU RCU_BASE
-
-/* registers definitions */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
- #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */
- #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
- #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
- #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
- #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */
- #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
- #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
- #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
- #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */
- #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */
- #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
- #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */
- #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */
- #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */
- #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */
-#elif defined(GD32F10X_CL)
- #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
- #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */
- #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
- #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
- #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
- #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */
- #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
- #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
- #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
- #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */
- #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */
- #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */
- #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
- #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */
- #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */
- #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */
- #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* bits definitions */
-/* RCU_CTL */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
- #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
- #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
- #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
- #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */
- #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
- #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
- #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
- #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
- #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
-#elif defined(GD32F10X_CL)
- #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
- #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
- #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
- #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
- #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */
- #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
- #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
- #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
- #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
- #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
- #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */
- #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */
- #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */
- #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* RCU_CFG0 */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
- #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
- #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
- #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
- #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
- #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */
- #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
- #define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */
- #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */
- #define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */
- #define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */
- #define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */
- #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */
- #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */
- #define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */
-#elif defined(GD32F10X_CL)
- #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
- #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
- #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
- #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
- #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
- #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */
- #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
- #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */
- #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */
- #define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */
- #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */
- #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */
- #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */
- #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */
- #define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* RCU_INT */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
- #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
- #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
- #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
- #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
- #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
- #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
- #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
- #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
- #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
- #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
- #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */
- #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */
- #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */
- #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */
- #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
- #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
-#elif defined(GD32F10X_CL)
- #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
- #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
- #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
- #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
- #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
- #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */
- #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */
- #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
- #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
- #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
- #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
- #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
- #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
- #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */
- #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */
- #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */
- #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */
- #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */
- #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */
- #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
- #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */
- #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */
- #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* RCU_APB2RST */
-#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */
-#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */
-#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */
-#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */
-#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */
-#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */
-#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */
-#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */
-#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */
-#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */
-#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */
-#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */
-#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */
-#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */
-#ifndef GD32F10X_CL
- #define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */
-#endif /* GD32F10X_CL */
-#ifndef GD32F10X_HD
- #define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */
- #define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */
- #define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */
-#endif /* GD32F10X_HD */
-
-/* RCU_APB1RST */
-#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */
-#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */
-#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */
-#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */
-#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */
-#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */
-#ifndef GD32F10X_HD
- #define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */
- #define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */
- #define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */
-#endif /* GD32F10X_HD */
-#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */
-#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */
-#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */
-#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */
-#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */
-#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */
-#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */
-#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */
-#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */
-#ifdef GD32F10X_CL
- #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */
-#endif /* GD32F10X_CL */
-#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */
-#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */
-#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */
-
-/* RCU_AHBEN */
-#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */
-#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */
-#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */
-#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */
-#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */
-#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */
-#elif defined(GD32F10X_CL)
- #define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */
- #define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */
- #define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */
- #define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* RCU_APB2EN */
-#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */
-#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */
-#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */
-#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */
-#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */
-#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */
-#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */
-#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */
-#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */
-#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */
-#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */
-#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */
-#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */
-#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */
-#ifndef GD32F10X_CL
- #define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */
-#endif /* GD32F10X_CL */
-#ifndef GD32F10X_HD
- #define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */
- #define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */
- #define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */
-#endif /* GD32F10X_HD */
-
-/* RCU_APB1EN */
-#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */
-#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */
-#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */
-#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */
-#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */
-#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */
-#ifndef GD32F10X_HD
- #define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */
- #define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */
- #define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */
-#endif /* GD32F10X_HD */
-#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */
-#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */
-#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */
-#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */
-#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */
-#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */
-#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */
-#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */
-#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */
-#ifdef GD32F10X_CL
- #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */
-#endif /* GD32F10X_CL */
-#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */
-#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */
-#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */
-
-/* RCU_BDCTL */
-#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */
-#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */
-#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */
-#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */
-#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */
-#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */
-#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */
-
-/* RCU_RSTSCK */
-#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */
-#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */
-#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */
-#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */
-#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */
-#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */
-#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */
-#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */
-#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */
-
-#ifdef GD32F10X_CL
- /* RCU_AHBRST */
- #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */
- #define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */
-#endif /* GD32F10X_CL */
-
-/* RCU_CFG1 */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */
- #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */
-#elif defined(GD32F10X_CL)
- #define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */
- #define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */
- #define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */
- #define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */
- #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */
- #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */
- #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */
- #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */
- #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */
- #define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* RCU_DSV */
-#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */
-
-/* RCU_ADDCTL */
-#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */
-#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */
-#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */
-#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */
-
-/* RCU_ADDINT */
-#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */
-#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */
-#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */
-
-/* RCU_ADDAPB1RST */
-#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */
-
-/* RCU_ADDAPB1EN */
-#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */
-
-
-/* constants definitions */
-/* define the peripheral clock enable bit position and its register index offset */
-#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
-#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
-#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
-
-/* register offset */
-/* peripherals enable */
-#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */
-#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */
-#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */
-#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */
-
-/* peripherals reset */
-#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */
-#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */
-#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */
-#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */
-#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */
-
-/* clock control */
-#define CTL_REG_OFFSET 0x00U /*!< control register offset */
-#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */
-#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */
-
-/* clock stabilization and stuck interrupt */
-#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */
-#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */
-
-/* configuration register */
-#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */
-#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */
-
-/* peripheral clock enable */
-typedef enum {
- /* AHB peripherals */
- RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
- RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
- RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */
- RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */
-#elif defined(GD32F10X_CL)
- RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */
- RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */
- RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */
- RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
- /* APB1 peripherals */
- RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */
- RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */
- RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */
- RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */
- RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */
- RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */
-#ifndef GD32F10X_HD
- RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */
- RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */
- RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */
-#endif /* GD32F10X_HD */
- RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */
- RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */
- RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */
- RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */
- RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */
- RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */
- RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */
- RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */
- RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */
-#endif /* GD32F10X_HD and GD32F10X_XD */
- RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */
-#ifdef GD32F10X_CL
- RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */
-#endif /* GD32F10X_CL */
- RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */
- RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */
- RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */
- RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */
- RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */
-
- /* APB2 peripherals */
- RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */
- RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */
- RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */
- RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */
- RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */
- RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */
- RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */
- RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */
- RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */
- RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */
- RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */
- RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */
- RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */
- RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */
-#ifndef GD32F10X_CL
- RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */
-#endif /* GD32F10X_CL */
-#ifndef GD32F10X_HD
- RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */
- RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */
- RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */
-#endif /* GD32F10X_HD */
-} rcu_periph_enum;
-
-/* peripheral clock enable when sleep mode*/
-typedef enum {
- /* AHB peripherals */
- RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
- RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
-} rcu_periph_sleep_enum;
-
-/* peripherals reset */
-typedef enum {
- /* AHB peripherals */
-#ifdef GD32F10X_CL
- RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
- RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */
-#endif /* GD32F10X_CL */
-
- /* APB1 peripherals */
- RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */
- RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */
- RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */
- RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */
- RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */
- RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */
-#ifndef GD32F10X_HD
- RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */
- RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */
- RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */
-#endif /* GD32F10X_HD */
- RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */
- RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */
- RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */
- RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */
- RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */
- RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */
- RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */
- RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */
- RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */
-#endif /* GD32F10X_HD and GD32F10X_XD */
- RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */
-#ifdef GD32F10X_CL
- RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */
-#endif /* GD32F10X_CL */
- RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */
- RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */
- RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */
- RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */
-
- /* APB2 peripherals */
- RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */
- RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */
- RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */
- RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */
- RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */
- RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */
- RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */
- RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */
- RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */
- RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */
- RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */
- RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */
- RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */
- RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */
-#ifndef GD32F10X_CL
- RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */
-#endif /* GD32F10X_CL */
-#ifndef GD32F10X_HD
- RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */
- RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */
- RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */
-#endif /* GD32F10X_HD */
-} rcu_periph_reset_enum;
-
-/* clock stabilization and peripheral reset flags */
-typedef enum {
- /* clock stabilization flags */
- RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
- RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
- RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */
-#ifdef GD32F10X_CL
- RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */
- RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */
-#endif /* GD32F10X_CL */
- RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */
- RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */
- RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */
- /* reset source flags */
- RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */
- RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */
- RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */
- RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */
- RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */
- RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */
-} rcu_flag_enum;
-
-/* clock stabilization and ckm interrupt flags */
-typedef enum {
- RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
- RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
- RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
- RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */
- RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */
-#ifdef GD32F10X_CL
- RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */
- RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */
-#endif /* GD32F10X_CL */
- RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */
- RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */
-} rcu_int_flag_enum;
-
-/* clock stabilization and stuck interrupt flags clear */
-typedef enum {
- RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
- RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
- RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
- RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */
- RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */
-#ifdef GD32F10X_CL
- RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */
- RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */
-#endif /* GD32F10X_CL */
- RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */
- RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */
-} rcu_int_flag_clear_enum;
-
-/* clock stabilization interrupt enable or disable */
-typedef enum {
- RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
- RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
- RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
- RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */
- RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */
-#ifdef GD32F10X_CL
- RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */
- RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
-#endif /* GD32F10X_CL */
- RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */
-} rcu_int_enum;
-
-/* oscillator types */
-typedef enum {
- RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */
- RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */
- RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */
- RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */
- RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */
- RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */
-#ifdef GD32F10X_CL
- RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */
- RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */
-#endif /* GD32F10X_CL */
-} rcu_osci_type_enum;
-
-/* rcu clock frequency */
-typedef enum {
- CK_SYS = 0, /*!< system clock */
- CK_AHB, /*!< AHB clock */
- CK_APB1, /*!< APB1 clock */
- CK_APB2, /*!< APB2 clock */
-} rcu_clock_freq_enum;
-
-/* RCU_CFG0 register bit define */
-/* system clock source select */
-#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
-#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */
-#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */
-#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */
-
-/* system clock source select status */
-#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
-#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */
-#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */
-#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */
-
-/* AHB prescaler selection */
-#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
-#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */
-#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */
-#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */
-#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */
-#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */
-#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */
-#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */
-#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */
-#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */
-
-/* APB1 prescaler selection */
-#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
-#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */
-#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */
-#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */
-#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */
-#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */
-
-/* APB2 prescaler selection */
-#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
-#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */
-#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */
-#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */
-#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */
-#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */
-
-/* ADC prescaler select */
-#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */
-#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */
-#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */
-#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */
-#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */
-#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */
-#define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */
-#define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */
-#define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */
-#define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */
-
-/* PLL clock source selection */
-#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */
-#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */
-
-/* PLL clock multiplication factor */
-#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */
-#define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */
-#define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */
-
-#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
-#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */
-#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */
-#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */
-#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */
-#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */
-#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */
-#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */
-#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */
-#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */
-#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */
-#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */
-#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */
-#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */
-#if(defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */
-#elif defined(GD32F10X_CL)
- #define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */
-#endif /* GD32F10X_HD and GD32F10X_XD */
-#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */
-#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */
-#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */
-#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */
-#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */
-#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */
-#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */
-#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */
-#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */
-#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */
-#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */
-#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */
-#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */
-#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */
-#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */
-#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */
-#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */
-#define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */
-#define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */
-#define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */
-#define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */
-#define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */
-#define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */
-#define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */
-#define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */
-#define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */
-#define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */
-#define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */
-#define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */
-#define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */
-#define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */
-#define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */
-#define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */
-#define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */
-#define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */
-#define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */
-#define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */
-#define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */
-#define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */
-#define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */
-#define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */
-#define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */
-#define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */
-#define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */
-#define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */
-#define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */
-#define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */
-#define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */
-
-#if(defined(GD32F10X_HD) || defined(GD32F10X_XD))
- #define USBPSC_2 RCU_CFG0_USBDPSC_2
-#elif defined(GD32F10X_CL)
- #define USBPSC_2 RCU_CFG0_USBFSPSC_2
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* USBD/USBFS prescaler select */
-#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
-#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */
-#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */
-#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */
-#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */
-#define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBD/USBFS prescaler select CK_PLL/3.5 */
-#define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBD/USBFS prescaler select CK_PLL/3 */
-#define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */
-
-/* CKOUT0 Clock source selection */
-#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
-#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */
-#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */
-#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */
-#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */
-#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */
-#ifdef GD32F10X_CL
- #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */
- #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */
- #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */
- #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */
-#endif /* GD32F10X_CL */
-
-/* LXTAL drive capability */
-#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
-#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */
-#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */
-#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */
-#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */
-
-/* RTC clock entry selection */
-#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
-#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */
-#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */
-#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */
-#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */
-
-/* PREDV0 division factor */
-#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
-#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */
-#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */
-#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */
-#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */
-#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */
-#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */
-#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */
-#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */
-#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */
-#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */
-#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */
-#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */
-#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */
-#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */
-#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */
-#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */
-
-/* PREDV1 division factor */
-#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
-#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */
-#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */
-#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */
-#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */
-#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */
-#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */
-#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */
-#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */
-#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */
-#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */
-#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */
-#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */
-#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */
-#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */
-#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */
-#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */
-
-/* PLL1 clock multiplication factor */
-#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
-#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */
-#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */
-#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */
-#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */
-#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */
-#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */
-#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */
-#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */
-#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */
-#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */
-
-/* PLL2 clock multiplication factor */
-#define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */
-
-#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12))
-#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */
-#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */
-#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */
-#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */
-#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */
-#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */
-#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */
-#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */
-#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */
-#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */
-#define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */
-#define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */
-#define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */
-#define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */
-#define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */
-#define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */
-#define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */
-#define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */
-#define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */
-#define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */
-#define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */
-#define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */
-#define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */
-#define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */
-#define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */
-
-#ifdef GD32F10X_CL
- /* PREDV0 input clock source selection */
- #define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */
- #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */
-
- /* I2S1 clock source selection */
- #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */
- #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */
-
- /* I2S2 clock source selection */
- #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */
- #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */
-#endif /* GD32F10X_CL */
-
-/* PLL input clock source selection */
-#define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */
-#define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */
-
-/* deep-sleep mode voltage */
-#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
-#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */
-#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */
-
-/* 48MHz clock selection */
-#define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */
-#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */
-
-/* function declarations */
-/* deinitialize the RCU */
-void rcu_deinit(void);
-/* enable the peripherals clock */
-void rcu_periph_clock_enable(rcu_periph_enum periph);
-/* disable the peripherals clock */
-void rcu_periph_clock_disable(rcu_periph_enum periph);
-/* enable the peripherals clock when sleep mode */
-void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
-/* disable the peripherals clock when sleep mode */
-void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
-/* reset the peripherals */
-void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
-/* disable reset the peripheral */
-void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
-/* reset the BKP domain */
-void rcu_bkp_reset_enable(void);
-/* disable the BKP domain reset */
-void rcu_bkp_reset_disable(void);
-
-/* configure the system clock source */
-void rcu_system_clock_source_config(uint32_t ck_sys);
-/* get the system clock source */
-uint32_t rcu_system_clock_source_get(void);
-/* configure the AHB prescaler selection */
-void rcu_ahb_clock_config(uint32_t ck_ahb);
-/* configure the APB1 prescaler selection */
-void rcu_apb1_clock_config(uint32_t ck_apb1);
-/* configure the APB2 prescaler selection */
-void rcu_apb2_clock_config(uint32_t ck_apb2);
-/* configure the CK_OUT0 clock source and divider */
-void rcu_ckout0_config(uint32_t ckout0_src);
-/* configure the PLL clock source selection and PLL multiply factor */
-void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
-/* configure the PLL clock source preselection */
-void rcu_pllpresel_config(uint32_t pll_presel);
-#if(defined(GD32F10X_HD) || defined(GD32F10X_XD))
- /* configure the PREDV0 division factor and clock source */
- void rcu_predv0_config(uint32_t predv0_div);
-#elif defined(GD32F10X_CL)
- /* configure the PREDV0 division factor and clock source */
- void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div);
- /* configure the PREDV1 division factor */
- void rcu_predv1_config(uint32_t predv1_div);
- /* configure the PLL1 clock */
- void rcu_pll1_config(uint32_t pll_mul);
- /* configure the PLL2 clock */
- void rcu_pll2_config(uint32_t pll_mul);
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/* configure the ADC division factor */
-void rcu_adc_clock_config(uint32_t adc_psc);
-/* configure the USBD/USBFS prescaler factor */
-void rcu_usb_clock_config(uint32_t usb_psc);
-/* configure the RTC clock source selection */
-void rcu_rtc_clock_config(uint32_t rtc_clock_source);
-#ifdef GD32F10X_CL
- /* configure the I2S1 clock source selection */
- void rcu_i2s1_clock_config(uint32_t i2s_clock_source);
- /* configure the I2S2 clock source selection */
- void rcu_i2s2_clock_config(uint32_t i2s_clock_source);
-#endif /* GD32F10X_CL */
-/* configure the CK48M clock selection */
-void rcu_ck48m_clock_config(uint32_t ck48m_clock_source);
-
-
-/* get the clock stabilization and periphral reset flags */
-FlagStatus rcu_flag_get(rcu_flag_enum flag);
-/* clear the reset flag */
-void rcu_all_reset_flag_clear(void);
-/* get the clock stabilization interrupt and ckm flags */
-FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
-/* clear the interrupt flags */
-void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
-/* enable the stabilization interrupt */
-void rcu_interrupt_enable(rcu_int_enum stab_int);
-/* disable the stabilization interrupt */
-void rcu_interrupt_disable(rcu_int_enum stab_int);
-
-/* configure the LXTAL drive capability */
-void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
-/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
-ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
-/* turn on the oscillator */
-void rcu_osci_on(rcu_osci_type_enum osci);
-/* turn off the oscillator */
-void rcu_osci_off(rcu_osci_type_enum osci);
-/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
-void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
-/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
-void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
-/* enable the HXTAL clock monitor */
-void rcu_hxtal_clock_monitor_enable(void);
-/* disable the HXTAL clock monitor */
-void rcu_hxtal_clock_monitor_disable(void);
-
-/* set the IRC8M adjust value */
-void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval);
-
-/* set the deep sleep mode voltage */
-void rcu_deepsleep_voltage_set(uint32_t dsvol);
-
-/* get the system clock, bus and peripheral clock frequency */
-uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
-
-#endif /* GD32F10X_RCU_H */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h
deleted file mode 100644
index 65d57f06c2..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/**
- ******************************************************************************
- * @brief RTC header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_RTC_H
-#define __GD32F10X_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/** @defgroup RTC_Exported_Defines
- * @{
- */
-
-/** @defgroup RTC_Interrupt_Def
- * @{
- */
-#define RTC_INT_OVF ((uint16_t)0x0004) /*!< Overflow interrupt */
-#define RTC_INT_AF ((uint16_t)0x0002) /*!< Alarm interrupt */
-#define RTC_INT_SF ((uint16_t)0x0001) /*!< Second interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Flags
- * @{
- */
-#define RTC_FLAG_LWOFF ((uint16_t)0x0020) /*!< Last write operation finished flag */
-#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
-#define RTC_FLAG_OVF ((uint16_t)0x0004) /*!< Overflow flag */
-#define RTC_FLAG_AF ((uint16_t)0x0002) /*!< Alarm flag */
-#define RTC_FLAG_SF ((uint16_t)0x0001) /*!< Second flag */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions
- * @{
- */
-void RTC_INT_Enable(uint16_t RTC_int, TypeState NewValue);
-void RTC_EnterConfigMode(void);
-void RTC_ExitConfigMode(void);
-uint32_t RTC_GetCounter(void);
-void RTC_SetCounter(uint32_t CounterValue);
-void RTC_SetPrescaler(uint32_t PrescalerValue);
-void RTC_SetAlarm(uint32_t AlarmTime);
-uint32_t RTC_GetDividerValue(void);
-void RTC_WaitLWOFF(void);
-void RTC_WaitRSF(void);
-TypeState RTC_GetBitState(uint16_t RTC_flag);
-void RTC_ClearBitState(uint16_t RTC_flag);
-TypeState RTC_GetIntBitState(uint16_t RTC_INT);
-void RTC_ClearIntBitState(uint16_t RTC_INT);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h
deleted file mode 100644
index 16c4d97b12..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/**
- ******************************************************************************
- * @brief SDIO header file of the firmware library
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_SDIO_H
-#define __GD32F10X_SDIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup SDIO
- * @{
- */
-
-/** @defgroup SDIO_Exported_Types
- * @{
- */
-
-typedef struct {
- uint32_t SDIO_ClockEdge; /*!< Configure the SDIO Clock edge on which the bit capture is made.
- This parameter can be a value of @ref SDIO_Clock_Edge*/
- uint32_t SDIO_ClockBypassState; /*!< Configure the SDIO Clock divider bypass mode
- This parameter can be a value of @ref SDIO_Clock_Bypass_State */
- uint32_t SDIO_ClockPWRSave; /*!< Configure the SDIO Clock output powersave mode when the bus is idle.
- This parameter can be a value of @ref SDIO_Clock_Power_Save */
- uint32_t SDIO_BusMode; /*!< Configure the SDIO bus mode.
- This parameter can be a value of @ref SDIO_Bus_Mode */
- uint32_t SDIO_HWFlowCtrlState; /*!< Configure the SDIO hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDIO_HW_Flow_Control_State */
- uint8_t SDIO_ClockDiv; /*!< Configure the clock frequency prescaler of the SDIO controller.
- This parameter can be a value between 0x00 and 0xFF. */
-} SDIO_InitPara;
-
-typedef struct {
- uint32_t SDIO_CMDParameter; /*!< Configure the SDIO command parameter which is sent to
- a card as part of a command message. */
- uint32_t SDIO_CMDIndex; /*!< Configure the SDIO command index. */
-
- uint32_t SDIO_ResponseType; /*!< Configure the SDIO response type.
- This parameter can be a value of @ref SDIO_Response_Type */
- uint32_t SDIO_WaitINTState; /*!< Configure whether SDIO wait-for-interrupt request is enabled or disabled.
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
- uint32_t SDIO_CSMState; /*!< Configure SDIO Command state machine (CSM) is enabled or disabled.
- This parameter can be a value of @ref SDIO_CSM_State */
-} SDIO_CmdInitPara;
-
-typedef struct {
- uint32_t SDIO_DataTimeOut; /*!< Configure the data timeout period in card bus clock periods. */
-
- uint32_t SDIO_DataLength; /*!< Configure the number of data bytes to be transferred. */
-
- uint32_t SDIO_DataBlockSize; /*!< Configure the data block size for block transfer.
- This parameter can be a value of @ref SDIO_Data_Block_Size */
- uint32_t SDIO_TransDirection; /*!< Configure the data transfer direction, read or write.
- This parameter can be a value of @ref SDIO_Transfer_Direction */
- uint32_t SDIO_TransMode; /*!< Configure whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDIO_Transfer_Mode */
- uint32_t SDIO_DSMState; /*!< Configure whether SDIO Data state machine (DSM) is enabled or disabled.
- This parameter can be a value of @ref SDIO_DSM_State */
-} SDIO_DataInitPara;
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Exported_Constants
- * @{
- */
-
-/** @defgroup SDIO_Clock_Edge
- * @{
- */
-#define SDIO_CLOCKEDGE_RISING ((uint32_t)0x00000000)
-#define SDIO_CLOCKEDGE_FALLING ((uint32_t)0x00002000)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_Bypass_State
- * @{
- */
-#define SDIO_CLOCKBYPASSSTATE_DISABLE ((uint32_t)0x00000000)
-#define SDIO_CLOCKBYPASSSTATE_ENABLE ((uint32_t)0x00000400)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Clock_PWR_Save
- * @{
- */
-#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000)
-#define SDIO_CLOCKPWRSAVE_ENABLE ((uint32_t)0x00000200)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Bus_Mode
- * @{
- */
-#define SDIO_BUSMODE_1B ((uint32_t)0x00000000)
-#define SDIO_BUSMODE_4B ((uint32_t)0x00000800)
-#define SDIO_BUSMODE_8B ((uint32_t)0x00001000)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_HW_Flow_Control_State
- * @{
- */
-
-#define SDIO_HWFLOWCTRLSTATE_DISABLE ((uint32_t)0x00000000)
-#define SDIO_HWFLOWCTRLSTATE_ENABLE ((uint32_t)0x00004000)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Power_State
- * @{
- */
-#define SDIO_PWRSTATE_OFF ((uint32_t)0x00000000)
-#define SDIO_PWRSTATE_ON ((uint32_t)0x00000003)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Interrupt_sources
- * @{
- */
-#define SDIO_INT_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_INT_DTCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_INT_CMDTMOUT ((uint32_t)0x00000004)
-#define SDIO_INT_DTTMOUT ((uint32_t)0x00000008)
-#define SDIO_INT_TXURE ((uint32_t)0x00000010)
-#define SDIO_INT_RXORE ((uint32_t)0x00000020)
-#define SDIO_INT_CMDREND ((uint32_t)0x00000040)
-#define SDIO_INT_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_INT_DTEND ((uint32_t)0x00000100)
-#define SDIO_INT_STBITE ((uint32_t)0x00000200)
-#define SDIO_INT_DTBLKEND ((uint32_t)0x00000400)
-#define SDIO_INT_CMDRUN ((uint32_t)0x00000800)
-#define SDIO_INT_TXRUN ((uint32_t)0x00001000)
-#define SDIO_INT_RXRUN ((uint32_t)0x00002000)
-#define SDIO_INT_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_INT_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_INT_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_INT_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_INT_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_INT_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_INT_TXDTVAL ((uint32_t)0x00100000)
-#define SDIO_INT_RXDTVAL ((uint32_t)0x00200000)
-#define SDIO_INT_SDIOINT ((uint32_t)0x00400000)
-#define SDIO_INT_ATAEND ((uint32_t)0x00800000)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Type
- * @{
- */
-#define SDIO_RESPONSETYPE_NO ((uint32_t)0x00000000)
-#define SDIO_RESPONSETYPE_SHORT ((uint32_t)0x00000040)
-#define SDIO_RESPONSETYPE_LONG ((uint32_t)0x000000C0)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Wait_Interrupt_State
- * @{
- */
-#define SDIO_WAITINTSTATE_NO ((uint32_t)0x00000000)
-#define SDIO_WAITINTSTATE_INT ((uint32_t)0x00000100)
-#define SDIO_WAITINTSTATE_PEND ((uint32_t)0x00000200)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_CSM_State
- * @{
- */
-#define SDIO_CSMSTATE_DISABLE ((uint32_t)0x00000000)
-#define SDIO_CSMSTATE_ENABLE ((uint32_t)0x00000400)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Response_Registers
- * @{
- */
-#define SDIO_RESP1 ((uint32_t)0x00000000)
-#define SDIO_RESP2 ((uint32_t)0x00000004)
-#define SDIO_RESP3 ((uint32_t)0x00000008)
-#define SDIO_RESP4 ((uint32_t)0x0000000C)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Data_Block_Size
- * @{
- */
-#define SDIO_DATABLOCKSIZE_1B ((uint32_t)0x00000000)
-#define SDIO_DATABLOCKSIZE_2B ((uint32_t)0x00000010)
-#define SDIO_DATABLOCKSIZE_4B ((uint32_t)0x00000020)
-#define SDIO_DATABLOCKSIZE_8B ((uint32_t)0x00000030)
-#define SDIO_DATABLOCKSIZE_16B ((uint32_t)0x00000040)
-#define SDIO_DATABLOCKSIZE_32B ((uint32_t)0x00000050)
-#define SDIO_DATABLOCKSIZE_64B ((uint32_t)0x00000060)
-#define SDIO_DATABLOCKSIZE_128B ((uint32_t)0x00000070)
-#define SDIO_DATABLOCKSIZE_256B ((uint32_t)0x00000080)
-#define SDIO_DATABLOCKSIZE_512B ((uint32_t)0x00000090)
-#define SDIO_DATABLOCKSIZE_1024B ((uint32_t)0x000000A0)
-#define SDIO_DATABLOCKSIZE_2048B ((uint32_t)0x000000B0)
-#define SDIO_DATABLOCKSIZE_4096B ((uint32_t)0x000000C0)
-#define SDIO_DATABLOCKSIZE_8192B ((uint32_t)0x000000D0)
-#define SDIO_DATABLOCKSIZE_16384B ((uint32_t)0x000000E0)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Direction
- * @{
- */
-#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000)
-#define SDIO_TRANSDIRECTION_TOSDIO ((uint32_t)0x00000002)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Transfer_Mode
- * @{
- */
-#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000)
-#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_DSM_State
- * @{
- */
-#define SDIO_DSMSTATE_DISABLE ((uint32_t)0x00000000)
-#define SDIO_DSMSTATE_ENABLE ((uint32_t)0x00000001)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Flag
- * @{
- */
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
-#define SDIO_FLAG_DTCRCFAIL ((uint32_t)0x00000002)
-#define SDIO_FLAG_CMDTMOUT ((uint32_t)0x00000004)
-#define SDIO_FLAG_DTTMOUT ((uint32_t)0x00000008)
-#define SDIO_FLAG_TXURE ((uint32_t)0x00000010)
-#define SDIO_FLAG_RXORE ((uint32_t)0x00000020)
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
-#define SDIO_FLAG_DTEND ((uint32_t)0x00000100)
-#define SDIO_FLAG_STBITE ((uint32_t)0x00000200)
-#define SDIO_FLAG_DTBLKEND ((uint32_t)0x00000400)
-#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800)
-#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000)
-#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000)
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
-#define SDIO_FLAG_TXDTVAL ((uint32_t)0x00100000)
-#define SDIO_FLAG_RXDTVAL ((uint32_t)0x00200000)
-#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000)
-#define SDIO_FLAG_ATAEND ((uint32_t)0x00800000)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Read_Wait_Mode
- * @{
- */
-#define SDIO_READWAITMODE_CLK ((uint32_t)0x00000001)
-#define SDIO_READWAITMODE_DAT2 ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup SDIO_Exported_Functions
- * @{
- */
-void SDIO_DeInit(void);
-void SDIO_Init(SDIO_InitPara *SDIO_InitParaStruct);
-void SDIO_ParaInit(SDIO_InitPara *SDIO_InitParaStruct);
-void SDIO_Clock_Enable(TypeState NewState);
-void SDIO_SetPWRState(uint32_t SDIO_PWRState);
-uint32_t SDIO_GetPWRState(void);
-void SDIO_INTConfig(uint32_t SDIO_INT, TypeState NewState);
-void SDIO_DMA_Enable(TypeState NewState);
-void SDIO_SendCMD(SDIO_CmdInitPara *SDIO_CmdInitParaStruct);
-void SDIO_CMDParaInit(SDIO_CmdInitPara *SDIO_CmdInitParaStruct);
-uint8_t SDIO_GetCMDResponse(void);
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
-void SDIO_DataConfig(SDIO_DataInitPara *SDIO_DataInitParaStruct);
-void SDIO_DataParaInit(SDIO_DataInitPara *SDIO_DataInitParaStruct);
-uint32_t SDIO_GetDataCount(void);
-uint32_t SDIO_ReadData(void);
-void SDIO_WriteData(uint32_t Data);
-uint32_t SDIO_GetFIFOCount(void);
-void SDIO_StartSDIOReadWait(TypeState NewState);
-void SDIO_StopSDIOReadWait(TypeState NewState);
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-void SDIO_SetSDIOOperation(TypeState NewState);
-void SDIO_SendSDIOSuspend_Enable(TypeState NewState);
-void SDIO_CMDCompletion_Enable(TypeState NewState);
-void SDIO_CEATAInt_Enable(TypeState NewState);
-void SDIO_SendCEATA_Enable(TypeState NewState);
-
-TypeState SDIO_GetBitState(uint32_t SDIO_FLAG);
-void SDIO_ClearBitState(uint32_t SDIO_FLAG);
-TypeState SDIO_GetIntBitState(uint32_t SDIO_INT);
-void SDIO_ClearIntBitState(uint32_t SDIO_INT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_SDIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_spi.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_spi.h
deleted file mode 100644
index cf0e88e26f..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_spi.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/**
- ******************************************************************************
- * @brief SPI header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_SPI_H
-#define __GD32F10X_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/** @defgroup SPI_Exported_Types
- * @{
- */
-
-/**
- * @brief SPI Initial Parameters
- */
-typedef struct {
- uint16_t SPI_TransType; /*!< The transfer type, choose one from @ref SPI_transfer_type. */
- uint16_t SPI_Mode; /*!< The operating mode, choose one from @ref SPI_mode. */
- uint16_t SPI_FrameFormat; /*!< The SPI data frame format, choose one from @ref SPI_data_frame_format. */
- uint16_t SPI_SCKPL; /*!< The clock polarity in idel state, choose one from @ref SPI_Clock_Polarity. */
- uint16_t SPI_SCKPH; /*!< The clock phase, choose one from @ref SPI_Clock_Phase. */
- uint16_t SPI_SWNSSEN; /*!< The NSS signal management, choose one from @ref SPI_Software_NSS_management. */
- uint16_t SPI_PSC; /*!< The Baud Rate prescaler value, choose one from @ref SPI_BaudRate_Prescaler. */
- uint16_t SPI_FirstBit; /*!< The data transfers start from MSB or LSB bit, choose one from @ref SPI_MSB_LSB_transmission. */
- uint16_t SPI_CRCPOL; /*!< The polynomial used for the CRC calculation. */
-} SPI_InitPara;
-
-/**
- * @brief I2S Initial Parameters
- */
-typedef struct {
- uint16_t I2S_Mode; /*!< The operating mode and transfer direction, choose one from @ref I2S_Mode. */
- uint16_t I2S_STD; /*!< The I2S standard, choose one from @ref I2S_Standard. */
- uint16_t I2S_FrameFormat; /*!< The I2S data length and channel length, choose one from @ref I2S_Data_Format. */
- uint16_t I2S_MCKOE; /*!< The I2S MCK output is enabled or disable, choose one from @ref I2S_MCLK_Output. */
- uint32_t I2S_AudioFreq; /*!< The audio sampling frequency, choose one from @ref I2S_Audio_Frequency. */
- uint16_t I2S_CKPL; /*!< The clock polarity in idel state, choose one from @ref I2S_Clock_Polarity. */
-} I2S_InitPara;
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-/** @defgroup SPI_transfer_type
- * @{
- */
-#define SPI_TRANSTYPE_FULLDUPLEX ((uint16_t)0x0000)
-#define SPI_TRANSTYPE_RXONLY SPI_CTLR1_RO
-#define SPI_TRANSTYPE_BDMRX SPI_CTLR1_BDM
-#define SPI_TRANSTYPE_BDMTX (SPI_CTLR1_BDM | SPI_CTLR1_BDOE)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-#define SPI_MODE_MASTER (SPI_CTLR1_MSTMODE|SPI_CTLR1_SWNSS)
-#define SPI_MODE_SLAVE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_data_frame_format
- * @{
- */
-#define SPI_FRAMEFORMAT_16BIT SPI_CTLR1_FF16
-#define SPI_FRAMEFORMAT_8BIT ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-#define SPI_SCKPL_LOW ((uint16_t)0x0000)
-#define SPI_SCKPL_HIGH SPI_CTLR1_SCKPL
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-#define SPI_SCKPH_1EDGE ((uint16_t)0x0000)
-#define SPI_SCKPH_2EDGE SPI_CTLR1_SCKPH
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Software_NSS_management
- * @{
- */
-#define SPI_SWNSS_SOFT SPI_CTLR1_SWNSSEN
-#define SPI_SWNSS_HARD ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-#define SPI_PSC_2 ((uint16_t)0x0000)
-#define SPI_PSC_4 ((uint16_t)0x0008)
-#define SPI_PSC_8 ((uint16_t)0x0010)
-#define SPI_PSC_16 ((uint16_t)0x0018)
-#define SPI_PSC_32 ((uint16_t)0x0020)
-#define SPI_PSC_64 ((uint16_t)0x0028)
-#define SPI_PSC_128 ((uint16_t)0x0030)
-#define SPI_PSC_256 ((uint16_t)0x0038)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB ((uint16_t)0x0000)
-#define SPI_FIRSTBIT_LSB SPI_CTLR1_LF
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Mode
- * @{
- */
-#define I2S_MODE_SLAVETX ((uint16_t)0x0000)
-#define I2S_MODE_SLAVERX ((uint16_t)0x0100)
-#define I2S_MODE_MASTERTX ((uint16_t)0x0200)
-#define I2S_MODE_MASTERRX ((uint16_t)0x0300)
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard
- * @{
- */
-#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
-#define I2S_STD_MSB ((uint16_t)0x0010)
-#define I2S_STD_LSB ((uint16_t)0x0020)
-#define I2S_STD_PCMSHORT ((uint16_t)0x0030)
-#define I2S_STD_PCMLONG ((uint16_t)0x00B0)
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format
- * @{
- */
-#define I2S_FRAMEFORMAT_DL16b_CL16b ((uint16_t)0x0000)
-#define I2S_FRAMEFORMAT_DL16b_CL32b ((uint16_t)0x0001)
-#define I2S_FRAMEFORMAT_DL24b_CL32b ((uint16_t)0x0003)
-#define I2S_FRAMEFORMAT_DL32b_CL32b ((uint16_t)0x0005)
-
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output
- * @{
- */
-#define I2S_MCK_ENABLE SPI_I2SCKP_MCKOE
-#define I2S_MCK_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency
- * @{
- */
-#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
-#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
-#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
-#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
-#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
-#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
-#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
-#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
-#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
-#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity
- * @{
- */
-#define I2S_CKPL_LOW ((uint16_t)0x0000)
-#define I2S_CKPL_HIGH SPI_I2SCTLR_CKPL
-
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-#define SPI_I2S_DMA_TX SPI_CTLR2_DMATE
-#define SPI_I2S_DMA_RX SPI_CTLR2_DMARE
-
-/**
- * @}
- */
-
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-#define SPI_SWNSS_SET ((uint16_t)0x0001)
-#define SPI_SWNSS_RESET ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-#define SPI_CRC_TX ((uint8_t)0x00)
-#define SPI_CRC_RX ((uint8_t)0x01)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-#define SPI_BDOE_RX (~SPI_CTLR1_BDOE)
-#define SPI_BDOE_TX SPI_CTLR1_BDOE
-
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-#define SPI_I2S_INT_TBE ((uint8_t)0x71)
-#define SPI_I2S_INT_RBNE ((uint8_t)0x60)
-#define SPI_I2S_INT_ERR ((uint8_t)0x50)
-#define SPI_I2S_INT_OVR ((uint8_t)0x56)
-#define SPI_INT_MODF ((uint8_t)0x55)
-#define SPI_INT_CRCERR ((uint8_t)0x54)
-#define I2S_INT_UDR ((uint8_t)0x53)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-#define SPI_FLAG_RBNE SPI_STR_RBNE
-#define SPI_FLAG_TBE SPI_STR_TBE
-#define SPI_FLAG_CRCERR SPI_STR_CRCE
-#define SPI_FLAG_MODF SPI_STR_CONFE
-#define SPI_FLAG_OVR SPI_STR_RXORE
-#define SPI_FLAG_BSY SPI_STR_TRANS
-
-#define I2S_FLAG_RBNE SPI_STR_RBNE
-#define I2S_FLAG_TBE SPI_STR_TBE
-#define I2S_FLAG_CHSIDE SPI_STR_I2SCH
-#define I2S_FLAG_UDR SPI_STR_TXURE
-#define I2S_FLAG_OVR SPI_STR_RXORE
-#define I2S_FLAG_BSY SPI_STR_TRANS
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup SPI_Exported_Functions
- * @{
- */
-void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
-void SPI_Init(SPI_TypeDef *SPIx, SPI_InitPara *SPI_InitParameter);
-void I2S_Init(SPI_TypeDef *SPIx, I2S_InitPara *I2S_InitParameter);
-void SPI_ParaInit(SPI_InitPara *SPI_InitParameter);
-void I2S_ParaInit(I2S_InitPara *I2S_InitParameter);
-void SPI_Enable(SPI_TypeDef *SPIx, TypeState NewValue);
-void I2S_Enable(SPI_TypeDef *SPIx, TypeState NewValue);
-void SPI_I2S_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT, TypeState NewValue);
-void SPI_I2S_DMA_Enable(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, TypeState NewValue);
-void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
-void SPI_SWNSSConfig(SPI_TypeDef *SPIx, uint16_t SPI_SWNSS);
-void SPI_NSSDRV(SPI_TypeDef *SPIx, TypeState NewValue);
-void SPI_FrameFormatConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
-void SPI_SendCRCNext(SPI_TypeDef *SPIx);
-void SPI_CRC_Enable(SPI_TypeDef *SPIx, TypeState NewValue);
-uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
-void SPI_BDOEConfig(SPI_TypeDef *SPIx, uint16_t SPI_BDOE);
-TypeState SPI_I2S_GetBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
-TypeState SPI_I2S_GetIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT);
-void SPI_I2S_ClearIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_timer.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_timer.h
deleted file mode 100644
index a720a1cd3e..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_timer.h
+++ /dev/null
@@ -1,758 +0,0 @@
-/**
- ******************************************************************************
- * @brief TIMER header file of the firmware library
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_TIMER_H
-#define __GD32F10X_TIMER_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup TIMER
- * @{
- */
-
-/** @defgroup TIMER_Exported_Types
- * @{
- */
-
-/**
- * @brief Timer base init structure
- */
-typedef struct {
- uint16_t TIMER_Prescaler; /*!< Clock prescaler value . */
- uint16_t TIMER_CounterMode; /*!< Counter mode ,
- a value of @ref TIMER_Counter_Mode. */
- uint32_t TIMER_Period; /*!< Value to be loaded into the active CARL at the next update event. */
- uint16_t TIMER_ClockDivision; /*!< Clock division ,
- a value of @ref TIMER_Clock_Division_CDIV. */
- uint8_t TIMER_RepetitionCounter; /*!< Repetition counter value , only valid in TIMER1/8. */
-} TIMER_BaseInitPara;
-
-/**
- * @brief Timer output compare init structure
- */
-typedef struct {
- uint16_t TIMER_OCMode; /*!< Out mode,
- a value of @ref TIMER_Output_Compare_and_PWM_modes */
-
- uint16_t TIMER_OutputState; /*!< Output Compare state ,
- a value of @ref TIMER_Output_Compare_State */
- uint16_t TIMER_OutputNState; /*!< Complementary Output Compare state ,
- a value of @ref TIMER_Output_Compare_N_State,
- valid only for TIMER1. */
- uint32_t TIMER_Pulse; /*!< Pulse value to be loaded into the CHCCx. */
- uint16_t TIMER_OCPolarity; /*!< Output polarity ,
- a value of @ref TIMER_Output_Compare_Polarity */
- uint16_t TIMER_OCNPolarity; /*!< Complementary output polarity ,
- a value of @ref TIMER_Output_Compare_N_Polarity */
- uint16_t TIMER_OCIdleState; /*!< TIM Output Compare pin state during Idle state ,
- a value of @ref TIMER_Output_Compare_Idle_State,
- valid only for TIMER1. */
- uint16_t TIMER_OCNIdleState; /*!< TIM Complementary Output Compare pin state during Idle state.
- a value of @ref TIMER_Output_Compare_N_Idle_State ,
- valid only for TIMER1. */
-} TIMER_OCInitPara;
-
-/**
- * @brief Timer input capture init structure
- */
-typedef struct {
- uint16_t TIMER_CH; /*!< TIMER channel ,
- a value of @ref TIMER_Channel */
- uint16_t TIMER_ICPolarity; /*!< Active edge of the input signal ,
- a value of @ref TIMER_Input_Capture_Polarity */
- uint16_t TIMER_ICSelection; /*!< Input Selection ,
- a value of @ref TIMER_Input_Capture_Selection */
- uint16_t TIMER_ICPrescaler; /*!< Input Capture Prescaler ,
- a value of @ref TIMER_Input_Capture_Prescaler */
- uint16_t TIMER_ICFilter; /*!< Input capture filter ,
- a number between 0x0 and 0xF */
-} TIMER_ICInitPara;
-
-/**
- * @brief Timer break and dead-time structure , valid only for TIMER1.
- */
-typedef struct {
- uint16_t TIMER_ROSState; /*!< Off-State selection used in Run mode ,
- a value of @ref TIMER_ROS_Off_State_Selection_for_Run_mode_State */
- uint16_t TIMER_IOSState; /*!< Off-State used in Idle state ,
- a value of @ref TIMER_IOS_Off_State_Selection_for_Idle_mode_State */
- uint16_t TIMER_LOCKLevel; /*!< LOCK level ,
- a value of @ref TIMER_Lock_level */
- uint16_t TIMER_DeadTime; /*!< delay time between the switching off and on of the outputs.
- a number between 0x00 and 0xFF */
- uint16_t TIMER_Break; /*!< Break input is enabled or disable,
- a value of @ref TIMER_Break_Input_State */
- uint16_t TIMER_BreakPolarity; /*!< Break Input pin polarity ,
- a value of @ref TIMER_Break_Input_Polarity */
- uint16_t TIMER_OutAuto; /*!< Automatic Output is enabled or disable.
- a value of @ref TIMER_OAE_Bit_State */
-} TIMER_BKDTInitPara;
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Exported_Constants
- * @{
- */
-
-/** @defgroup TIMER_Output_Compare_and_PWM_modes
- * @{
- */
-#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000)
-#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010)
-#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020)
-#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030)
-#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0060)
-#define TIMER_OC_MODE_PWM2 ((uint16_t)0x0070)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Single_Pulse_Mode
- * @{
- */
-#define TIMER_SP_MODE_SINGLE ((uint16_t)0x0008)
-#define TIMER_SP_MODE_REPETITIVE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Channel
- * @{
- */
-#define TIMER_CH_1 ((uint16_t)0x0000)
-#define TIMER_CH_2 ((uint16_t)0x0004)
-#define TIMER_CH_3 ((uint16_t)0x0008)
-#define TIMER_CH_4 ((uint16_t)0x000C)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Clock_Division_CDIV
- * @{
- */
-#define TIMER_CDIV_DIV1 ((uint16_t)0x0000)
-#define TIMER_CDIV_DIV2 ((uint16_t)0x0100)
-#define TIMER_CDIV_DIV4 ((uint16_t)0x0200)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Counter_Mode
- * @{
- */
-#define TIMER_COUNTER_UP ((uint16_t)0x0000)
-#define TIMER_COUNTER_DOWN ((uint16_t)0x0010)
-#define TIMER_COUNTER_CENTER_ALIGNED1 ((uint16_t)0x0020)
-#define TIMER_COUNTER_CENTER_ALIGNED2 ((uint16_t)0x0040)
-#define TIMER_COUNTER_CENTER_ALIGNED3 ((uint16_t)0x0060)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_Polarity
- * @{
- */
-#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000)
-#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_N_Polarity
- * @{
- */
-#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000)
-#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_State
- * @{
- */
-#define TIMER_OUTPUT_STATE_DISABLE ((uint16_t)0x0000)
-#define TIMER_OUTPUT_STATE_ENABLE ((uint16_t)0x0001)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_N_State
- * @{
- */
-#define TIMER_OUTPUTN_STATE_DISABLE ((uint16_t)0x0000)
-#define TIMER_OUTPUTN_STATE_ENABLE ((uint16_t)0x0004)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Capture_Compare_State
- * @{
- */
-#define TIMER_CCX_ENABLE ((uint16_t)0x0001)
-#define TIMER_CCX_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Capture_Compare_N_State
- * @{
- */
-#define TIMER_CCXN_ENABLE ((uint16_t)0x0004)
-#define TIMER_CCXN_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Break_Input_State
- * @{
- */
-#define TIMER_BREAK_ENABLE ((uint16_t)0x1000)
-#define TIMER_BREAK_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Break_Input_Polarity
- * @{
- */
-#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000)
-#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_OAE_Bit_State
- * @{
- */
-#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000)
-#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Lock_level
- * @{
- */
-#define TIMER_LOCK_LEVEL_OFF ((uint16_t)0x0000)
-#define TIMER_LOCK_LEVEL_1 ((uint16_t)0x0100)
-#define TIMER_LOCK_LEVEL_2 ((uint16_t)0x0200)
-#define TIMER_LOCK_LEVEL_3 ((uint16_t)0x0300)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_IOS_Off_State_Selection_for_Idle_mode_State
- * @{
- */
-#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400)
-#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_ROS_Off_State_Selection_for_Run_mode_State
- * @{
- */
-#define TIMER_ROS_STATE_ENABLE ((uint16_t)0x0800)
-#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_Idle_State
- * @{
- */
-#define TIMER_OC_IDLE_STATE_SET ((uint16_t)0x0100)
-#define TIMER_OC_IDLE_STATE_RESET ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_N_Idle_State
- * @{
- */
-#define TIMER_OCN_IDLE_STATE_SET ((uint16_t)0x0200)
-#define TIMER_OCN_IDLE_STATE_RESET ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Input_Capture_Polarity
- * @{
- */
-#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000)
-#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Input_Capture_Selection
- * @{
- */
-#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001)
-#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002)
-#define TIMER_IC_SELECTION_TRC ((uint16_t)0x0003)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Input_Capture_Prescaler
- * @{
- */
-#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000)
-#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004)
-#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008)
-#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000C)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_interrupt_sources
- * @{
- */
-#define TIMER_INT_UPDATE ((uint16_t)0x0001)
-#define TIMER_INT_CH1 ((uint16_t)0x0002)
-#define TIMER_INT_CH2 ((uint16_t)0x0004)
-#define TIMER_INT_CH3 ((uint16_t)0x0008)
-#define TIMER_INT_CH4 ((uint16_t)0x0010)
-#define TIMER_INT_CCUG ((uint16_t)0x0020)
-#define TIMER_INT_TRIGGER ((uint16_t)0x0040)
-#define TIMER_INT_BREAK ((uint16_t)0x0080)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_DMA_Base_address
- * @{
- */
-#define TIMER_DMA_BASE_ADDR_CTLR1 ((uint16_t)0x0000)
-#define TIMER_DMA_BASE_ADDR_CTLR2 ((uint16_t)0x0001)
-#define TIMER_DMA_BASE_ADDR_SMC ((uint16_t)0x0002)
-#define TIMER_DMA_BASE_ADDR_DIE ((uint16_t)0x0003)
-#define TIMER_DMA_BASE_ADDR_STR ((uint16_t)0x0004)
-#define TIMER_DMA_BASE_ADDR_EVG ((uint16_t)0x0005)
-#define TIMER_DMA_BASE_ADDR_CHCTLR1 ((uint16_t)0x0006)
-#define TIMER_DMA_BASE_ADDR_CHCTLR2 ((uint16_t)0x0007)
-#define TIMER_DMA_BASE_ADDR_CHE ((uint16_t)0x0008)
-#define TIMER_DMA_BASE_ADDR_CNT ((uint16_t)0x0009)
-#define TIMER_DMA_BASE_ADDR_PSC ((uint16_t)0x000A)
-#define TIMER_DMA_BASE_ADDR_CARL ((uint16_t)0x000B)
-#define TIMER_DMA_BASE_ADDR_CREP ((uint16_t)0x000C)
-#define TIMER_DMA_BASE_ADDR_CHCC1 ((uint16_t)0x000D)
-#define TIMER_DMA_BASE_ADDR_CHCC2 ((uint16_t)0x000E)
-#define TIMER_DMA_BASE_ADDR_CHCC3 ((uint16_t)0x000F)
-#define TIMER_DMA_BASE_ADDR_CHCC4 ((uint16_t)0x0010)
-#define TIMER_DMA_BASE_ADDR_BKDT ((uint16_t)0x0011)
-#define TIMER_DMA_BASE_ADDR_DCTLR ((uint16_t)0x0012)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_DMA_Burst_Transfer_Length
- * @{
- */
-#define TIMER_DMA_BURST_1TRANSFER ((uint16_t)0x0000)
-#define TIMER_DMA_BURST_2TRANSFERS ((uint16_t)0x0100)
-#define TIMER_DMA_BURST_3TRANSFERS ((uint16_t)0x0200)
-#define TIMER_DMA_BURST_4TRANSFERS ((uint16_t)0x0300)
-#define TIMER_DMA_BURST_5TRANSFERS ((uint16_t)0x0400)
-#define TIMER_DMA_BURST_6TRANSFERS ((uint16_t)0x0500)
-#define TIMER_DMA_BURST_7TRANSFERS ((uint16_t)0x0600)
-#define TIMER_DMA_BURST_8TRANSFERS ((uint16_t)0x0700)
-#define TIMER_DMA_BURST_9TRANSFERS ((uint16_t)0x0800)
-#define TIMER_DMA_BURST_10TRANSFERS ((uint16_t)0x0900)
-#define TIMER_DMA_BURST_11TRANSFERS ((uint16_t)0x0A00)
-#define TIMER_DMA_BURST_12TRANSFERS ((uint16_t)0x0B00)
-#define TIMER_DMA_BURST_13TRANSFERS ((uint16_t)0x0C00)
-#define TIMER_DMA_BURST_14TRANSFERS ((uint16_t)0x0D00)
-#define TIMER_DMA_BURST_15TRANSFERS ((uint16_t)0x0E00)
-#define TIMER_DMA_BURST_16TRANSFERS ((uint16_t)0x0F00)
-#define TIMER_DMA_BURST_17TRANSFERS ((uint16_t)0x1000)
-#define TIMER_DMA_BURST_18TRANSFERS ((uint16_t)0x1100)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_DMA_sources
- * @{
- */
-#define TIMER_DMA_UPDATE ((uint16_t)0x0100)
-#define TIMER_DMA_CH1 ((uint16_t)0x0200)
-#define TIMER_DMA_CH2 ((uint16_t)0x0400)
-#define TIMER_DMA_CH3 ((uint16_t)0x0800)
-#define TIMER_DMA_CH4 ((uint16_t)0x1000)
-#define TIMER_DMA_COM ((uint16_t)0x2000)
-#define TIMER_DMA_TRIGGER ((uint16_t)0x4000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_External_Trigger_Prescaler
- * @{
- */
-#define TIMER_EXT_TRI_PSC_OFF ((uint16_t)0x0000)
-#define TIMER_EXT_TRI_PSC_DIV2 ((uint16_t)0x1000)
-#define TIMER_EXT_TRI_PSC_DIV4 ((uint16_t)0x2000)
-#define TIMER_EXT_TRI_PSC_DIV8 ((uint16_t)0x3000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Internal_Trigger_Selection
- * @{
- */
-#define TIMER_TS_ITR0 ((uint16_t)0x0000)
-#define TIMER_TS_ITR1 ((uint16_t)0x0010)
-#define TIMER_TS_ITR2 ((uint16_t)0x0020)
-#define TIMER_TS_ITR3 ((uint16_t)0x0030)
-#define TIMER_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIMER_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIMER_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIMER_TS_ETRF ((uint16_t)0x0070)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_TIx_External_Clock_Source
- * @{
- */
-#define TIMER_TIX_EXCLK1_SRC_TI1 ((uint16_t)0x0050)
-#define TIMER_TIX_EXCLK1_SRC_TI2 ((uint16_t)0x0060)
-#define TIMER_TIX_EXCLK1_SRC_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_External_Trigger_Polarity
- * @{
- */
-#define TIMER_EXT_TRI_POLARITY_INVERTED ((uint16_t)0x8000)
-#define TIMER_EXT_TRI_POLARITY_NONINVERTED ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Prescaler_Reload_Mode
- * @{
- */
-#define TIMER_PSC_RELOAD_UPDATE ((uint16_t)0x0000)
-#define TIMER_PSC_RELOAD_NOW ((uint16_t)0x0001)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Forced_Output
- * @{
- */
-#define TIMER_FORCED_HIGH ((uint16_t)0x0050)
-#define TIMER_FORCED_LOW ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Encoder_Mode
- * @{
- */
-#define TIMER_ENCODER_MODE_TI1 ((uint16_t)0x0001)
-#define TIMER_ENCODER_MODE_TI2 ((uint16_t)0x0002)
-#define TIMER_ENCODER_MODE_TI12 ((uint16_t)0x0003)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Event_Source
- * @{
- */
-#define TIMER_EVENT_SRC_UPDATE ((uint16_t)0x0001)
-#define TIMER_EVENT_SRC_CH1 ((uint16_t)0x0002)
-#define TIMER_EVENT_SRC_CH2 ((uint16_t)0x0004)
-#define TIMER_EVENT_SRC_CH3 ((uint16_t)0x0008)
-#define TIMER_EVENT_SRC_CH4 ((uint16_t)0x0010)
-#define TIMER_EVENT_SRC_COM ((uint16_t)0x0020)
-#define TIMER_EVENT_SRC_TRIGGER ((uint16_t)0x0040)
-#define TIMER_EVENT_SRC_BREAK ((uint16_t)0x0080)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Update_Source
- * @{
- */
-#define TIMER_UPDATE_SRC_GLOBAL ((uint16_t)0x0000)
-#define TIMER_UPDATE_SRC_REGULAR ((uint16_t)0x0001)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_Preload_State
- * @{
- */
-#define TIMER_OC_PRELOAD_ENABLE ((uint16_t)0x0008)
-#define TIMER_OC_PRELOAD_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_Fast_State
- * @{
- */
-#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)
-#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Output_Compare_Clear_State
- * @{
- */
-#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080)
-#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Trigger_Output_Source
- * @{
- */
-#define TIMER_TRI_OUT_SRC_RESET ((uint16_t)0x0000)
-#define TIMER_TRI_OUT_SRC_ENABLE ((uint16_t)0x0010)
-#define TIMER_TRI_OUT_SRC_UPDATE ((uint16_t)0x0020)
-#define TIMER_TRI_OUT_SRC_OC1 ((uint16_t)0x0030)
-#define TIMER_TRI_OUT_SRC_OC1REF ((uint16_t)0x0040)
-#define TIMER_TRI_OUT_SRC_OC2REF ((uint16_t)0x0050)
-#define TIMER_TRI_OUT_SRC_OC3REF ((uint16_t)0x0060)
-#define TIMER_TRI_OUT_SRC_OC4REF ((uint16_t)0x0070)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Slave_Mode
- * @{
- */
-#define TIMER_SLAVE_MODE_RESET ((uint16_t)0x0004)
-#define TIMER_SLAVE_MODE_GATED ((uint16_t)0x0005)
-#define TIMER_SLAVE_MODE_TRIGGER ((uint16_t)0x0006)
-#define TIMER_SLAVE_MODE_EXTERNAL1 ((uint16_t)0x0007)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Master_Slave_Mode
- * @{
- */
-#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080)
-#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup TIMER_Flags
- * @{
- */
-#define TIMER_FLAG_UPDATE ((uint16_t)0x0001)
-#define TIMER_FLAG_CH1 ((uint16_t)0x0002)
-#define TIMER_FLAG_CH2 ((uint16_t)0x0004)
-#define TIMER_FLAG_CH3 ((uint16_t)0x0008)
-#define TIMER_FLAG_CH4 ((uint16_t)0x0010)
-#define TIMER_FLAG_COM ((uint16_t)0x0020)
-#define TIMER_FLAG_TRIGGER ((uint16_t)0x0040)
-#define TIMER_FLAG_BREAK ((uint16_t)0x0080)
-#define TIMER_FLAG_CH1OF ((uint16_t)0x0200)
-#define TIMER_FLAG_CH2OF ((uint16_t)0x0400)
-#define TIMER_FLAG_CH3OF ((uint16_t)0x0800)
-#define TIMER_FLAG_CH4OF ((uint16_t)0x1000)
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup TIMER_Exported_Functions
- * @{
- */
-/* TimeBase management ********************************************************/
-void TIMER_DeInit(TIMER_TypeDef *TIMERx);
-void TIMER_BaseInit(TIMER_TypeDef *TIMERx, TIMER_BaseInitPara *TIMER_Init);
-void TIMER_BaseStructInit(TIMER_BaseInitPara *TIMER_Init);
-void TIMER_PrescalerConfig(TIMER_TypeDef *TIMERx, uint16_t Prescaler, uint16_t TIMER_PSCReloadMode);
-void TIMER_CounterMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_CounterMode);
-void TIMER_SetCounter(TIMER_TypeDef *TIMERx, uint32_t Counter);
-void TIMER_SetAutoreload(TIMER_TypeDef *TIMERx, uint32_t AutoReloadValue);
-uint32_t TIMER_GetCounter(TIMER_TypeDef *TIMERx);
-uint16_t TIMER_GetPrescaler(TIMER_TypeDef *TIMERx);
-void TIMER_UpdateDisableConfig(TIMER_TypeDef *TIMERx, TypeState NewValue);
-void TIMER_UpdateRequestConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_UpdateSrc);
-void TIMER_CARLPreloadConfig(TIMER_TypeDef *TIMERx, TypeState NewValue);
-void TIMER_SinglePulseMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SPMode);
-void TIMER_SetClockDivision(TIMER_TypeDef *TIMERx, uint16_t TIMER_CDIV);
-void TIMER_Enable(TIMER_TypeDef *TIMERx, TypeState NewValue);
-
-/* Advanced timer features*******************/
-void TIMER_BKDTConfig(TIMER_TypeDef *TIMERx, TIMER_BKDTInitPara *TIMER_BKDTInit);
-void TIMER_BKDTStructInit(TIMER_BKDTInitPara *TIMER_BKDTInit);
-void TIMER_CtrlPWMOutputs(TIMER_TypeDef *TIMERx, TypeState NewValue);
-
-/* Output Compare management **************************************************/
-void TIMER_OC1_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit);
-void TIMER_OC2_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit);
-void TIMER_OC3_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit);
-void TIMER_OC4_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit);
-void TIMER_OCStructInit(TIMER_OCInitPara *TIMER_OCInit);
-void TIMER_OCxModeConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_OCMode);
-void TIMER_Compare1Config(TIMER_TypeDef *TIMERx, uint32_t CompValue1);
-void TIMER_Compare2Config(TIMER_TypeDef *TIMERx, uint32_t CompValue2);
-void TIMER_Compare3Config(TIMER_TypeDef *TIMERx, uint32_t CompValue3);
-void TIMER_Compare4Config(TIMER_TypeDef *TIMERx, uint32_t CompValue4);
-void TIMER_Forced_OC1(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced);
-void TIMER_Forced_OC2(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced);
-void TIMER_Forced_OC3(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced);
-void TIMER_Forced_OC4(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced);
-void TIMER_CC_PreloadControl(TIMER_TypeDef *TIMERx, TypeState NewValue);
-void TIMER_OC1_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload);
-void TIMER_OC2_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload);
-void TIMER_OC3_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload);
-void TIMER_OC4_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload);
-void TIMER_OC1_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast);
-void TIMER_OC2_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast);
-void TIMER_OC3_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast);
-void TIMER_OC4_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast);
-void TIMER_OC1_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear);
-void TIMER_OC2_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear);
-void TIMER_OC3_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear);
-void TIMER_OC4_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear);
-void TIMER_OC1_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity);
-void TIMER_OC1N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity);
-void TIMER_OC2_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity);
-void TIMER_OC2N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity);
-void TIMER_OC3_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity);
-void TIMER_OC3N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity);
-void TIMER_OC4_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity);
-void TIMER_SelectOCRefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCRef_Clear);
-void TIMER_CCxCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCx);
-void TIMER_CCxNCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCxN);
-void TIMER_SelectCOM(TIMER_TypeDef *TIMERx, TypeState NewValue);
-
-/* Input Capture management ***************************************************/
-void TIMER_ICInit(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit);
-void TIMER_ICStructInit(TIMER_ICInitPara *TIMER_ICInit);
-void TIMER_PWMCaptureConfig(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit);
-uint32_t TIMER_GetCapture1(TIMER_TypeDef *TIMERx);
-uint32_t TIMER_GetCapture2(TIMER_TypeDef *TIMERx);
-uint32_t TIMER_GetCapture3(TIMER_TypeDef *TIMERx);
-uint32_t TIMER_GetCapture4(TIMER_TypeDef *TIMERx);
-void TIMER_Set_IC1_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC);
-void TIMER_Set_IC2_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC);
-void TIMER_Set_IC3_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC);
-void TIMER_Set_IC4_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT, TypeState NewValue);
-void TIMER_GenerateEvent(TIMER_TypeDef *TIMERx, uint16_t TIMER_EventSrc);
-TypeState TIMER_GetBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG);
-void TIMER_ClearBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG);
-TypeState TIMER_GetIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT);
-void TIMER_ClearIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT);
-void TIMER_DMAConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMABase, uint16_t TIMER_DMABurstLength);
-void TIMER_DMACmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMASrc, TypeState NewValue);
-void TIMER_CC_DMA(TIMER_TypeDef *TIMERx, TypeState NewValue);
-
-/* Clocks management **********************************************************/
-void TIMER_InternalClockConfig(TIMER_TypeDef *TIMERx);
-void TIMER_ITRxExtClock(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc);
-void TIMER_TIxExtCLkConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_TIxExCLKSrc,
- uint16_t TIMER_ICPolarity, uint16_t ICFilter);
-void TIMER_ETRClockMode1Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity,
- uint16_t ExtTriFilter);
-void TIMER_ETRClockMode2Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler,
- uint16_t TIMER_ExTriPolarity, uint16_t ExtTriFilter);
-/* Synchronization management *************************************************/
-void TIMER_SelectInputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc);
-void TIMER_SelectOutputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_TriOutSrc);
-void TIMER_SelectSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SlaveMode);
-void TIMER_SelectMasterSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_MasterSlaveMode);
-void TIMER_ETRConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity,
- uint16_t ExtTriFilter);
-
-/* Specific interface management **********************************************/
-void TIMER_EncoderInterfaceConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_EncoderMode,
- uint16_t TIMER_IC1Polarity, uint16_t TIMER_IC2Polarity);
-void TIMER_SelectHallSensor(TIMER_TypeDef *TIMERx, TypeState NewValue);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_TIMER_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_usart.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_usart.h
deleted file mode 100644
index dec1f603a1..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_usart.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/**
- ******************************************************************************
- * @brief USART header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_USART_H
-#define __GD32F10X_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/** @defgroup USART_Exported_Types
- * @{
- */
-
-/**
- * @brief USART Initial Parameters
- */
-typedef struct {
- uint32_t USART_BRR; /*!< the USART communication baud rate configuration */
- uint16_t USART_WL; /*!< Set by USART_CTLR1_WL Word length 0: 8 Data bits,
- 1: 9 Data bits */
- uint16_t USART_STBits; /*!< Stop bits configuration */
-
- uint16_t USART_Parity; /*!< Set by USART_CTLR1_PCEN */
-
- uint16_t USART_RxorTx; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. */
-
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.This parameter can be a value of @ref USART_Hardware_Flow_Control */
-} USART_InitPara;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct {
- uint16_t USART_CKEN; /*!< USART clock enabled this parameter can be a value of @ref USART_CKEN */
-
- uint16_t USART_CPL; /*!< Clock polarity of Steady state this parameter can be a value of @ref USART_Clock_Polarity */
-
- uint16_t USART_CPH; /*!< Clock phase this parameter can be a value of @ref USART_Clock_Phase */
-
- uint16_t USART_LBCP; /*!< Last bit clock pulse this parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitPara;
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-/** @defgroup USART_WL
- * @{
- */
-#define USART_WL_8B ((uint16_t)0x0000)
-#define USART_WL_9B USART_CTLR1_WL
-
-/**
- * @}
- */
-
-/** @defgroup USART_STBits
- * @{
- */
-#define USART_STBITS_1 ((uint16_t)0x0000)
-#define USART_STBITS_0_5 ((uint16_t)0x1000)
-#define USART_STBITS_2 USART_CTLR2_STB_1
-#define USART_STBITS_1_5 (USART_CTLR2_STB_0 | USART_CTLR2_STB_1)
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-#define USART_PARITY_RESET ((uint16_t)0x0000)
-#define USART_PARITY_SETEVEN USART_CTLR1_PCEN
-#define USART_PARITY_SETODD (USART_CTLR1_PCEN | USART_CTLR1_PM)
-
-/**
- * @}
- */
-
-/** @defgroup USART_RxorTx
- * @{
- */
-#define USART_RXORTX_RX USART_CTLR1_REN
-#define USART_RXORTX_TX USART_CTLR1_TEN
-
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-#define USART_HARDWAREFLOWCONTROL_NONE ((uint16_t)0x0000)
-#define USART_HARDWAREFLOWCONTROL_RTS USART_CTLR3_RTSEN
-#define USART_HARDWAREFLOWCONTROL_CTS USART_CTLR3_CTSEN
-#define USART_HARDWAREFLOWCONTROL_RTS_CTS (USART_CTLR3_RTSEN | USART_CTLR3_CTSEN)
-
-/**
- * @}
- */
-
-/** @defgroup USART_CKEN
- * @{
- */
-#define USART_CKEN_RESET ((uint16_t)0x0000)
-#define USART_CKEN_SET USART_CTLR2_CKEN
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-#define USART_CPL_LOW ((uint16_t)0x0000)
-#define USART_CPL_HIGH USART_CTLR2_CPL
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-#define USART_CPH_1EDGE ((uint16_t)0x0000)
-#define USART_CPH_2EDGE USART_CTLR2_CPH
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-#define USART_LBCP_DISABLE ((uint16_t)0x0000)
-#define USART_LBCP_ENABLE USART_CTLR2_LBCP
-
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-#define USART_DMAREQ_TX USART_CTLR3_DENT
-#define USART_DMAREQ_RX USART_CTLR3_DENR
-/**
- * @}
- */
-/** @defgroup USART_Interrupt_definition
- * @brief USART Interrupt definition
- * USART_INT possible values
- * @{
- */
-#define USART_INT_PE ((uint16_t)0x0028)
-#define USART_INT_TBE ((uint16_t)0x0727)
-#define USART_INT_TC ((uint16_t)0x0626)
-#define USART_INT_RBNE ((uint16_t)0x0525)
-#define USART_INT_IDLEF ((uint16_t)0x0424)
-#define USART_INT_LBDF ((uint16_t)0x0846)
-#define USART_INT_CTSF ((uint16_t)0x096A)
-#define USART_INT_ERIE ((uint16_t)0x0060)
-#define USART_INT_ORE ((uint16_t)0x0360)
-#define USART_INT_NE ((uint16_t)0x0260)
-#define USART_INT_FE ((uint16_t)0x0160)
-
-/**
- * @}
- */
-
-
-
-/** @defgroup USART_MuteMode_WakeUp_methods
- * @{
- */
-#define USART_WAKEUP_IDLELINE ((uint16_t)0x0000)
-#define USART_WAKEUP_ADDRESSMARK USART_CTLR1_WM
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-#define USART_LINBREAKDETECTLENGTH_10B ((uint16_t)0x0000)
-#define USART_LINBREAKDETECTLENGTH_11B USART_CTLR2_LBDL
-
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-#define USART_IRDAMODE_LOWPOWER USART_CTLR3_IRLP
-#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
-
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-
-#define USART_FLAG_CTSF ((uint16_t)0x0200)
-#define USART_FLAG_LBDF ((uint16_t)0x0100)
-#define USART_FLAG_TBE ((uint16_t)0x0080)
-#define USART_FLAG_TC ((uint16_t)0x0040)
-#define USART_FLAG_RBNE ((uint16_t)0x0020)
-#define USART_FLAG_IDLEF ((uint16_t)0x0010)
-#define USART_FLAG_ORE ((uint16_t)0x0008)
-#define USART_FLAG_NE ((uint16_t)0x0004)
-#define USART_FLAG_FE ((uint16_t)0x0002)
-#define USART_FLAG_PE ((uint16_t)0x0001)
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions
- * @{
- */
-
-void USART_DeInit(USART_TypeDef *USARTx);
-void USART_Init(USART_TypeDef *USARTx, USART_InitPara *USART_InitParaStruct);
-void USART_ParaInit(USART_InitPara *USART_InitParaStruct);
-void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitPara *USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitPara *USART_ClockInitParaStruct);
-void USART_Enable(USART_TypeDef *USARTx, TypeState NewValue);
-void USART_HalfDuplex_Enable(USART_TypeDef *USARTx, TypeState NewValue);
-void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
-void USART_DataSend(USART_TypeDef *USARTx, uint16_t Data);
-uint16_t USART_DataReceive(USART_TypeDef *USARTx);
-void USART_Address(USART_TypeDef *USARTx, uint8_t USART_Address);
-void USART_MuteMode_Enable(USART_TypeDef *USARTx, TypeState NewState);
-void USART_MuteModeWakeUp_Set(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
-void USART_SetLINBDLength(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
-void USART_LIN_Enable(USART_TypeDef *USARTx, TypeState NewValue);
-void USART_GuardTime_Set(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
-void USART_SmartCard_Enable(USART_TypeDef *USARTx, TypeState NewValue);
-void USART_SmartCardNACK_Enable(USART_TypeDef *USARTx, TypeState NewValue);
-void USART_IrDA_Set(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
-void USART_IrDA_Enable(USART_TypeDef *USARTx, TypeState NewValue);
-void USART_DMA_Enable(USART_TypeDef *USARTx, uint16_t USART_DMAEnable, TypeState NewValue);
-void USART_INT_Set(USART_TypeDef *USARTx, uint16_t USART_INT, TypeState NewValue);
-TypeState USART_GetBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG);
-void USART_ClearBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG);
-TypeState USART_GetIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT);
-void USART_ClearIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT);
-void USART_SendBreak(USART_TypeDef *USARTx);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__GD32F10X_USART_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h
deleted file mode 100644
index 751defeb8e..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- ******************************************************************************
- * @brief WWDG header file of the firmware library.
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __GD32F10X_WWDG_H
-#define __GD32F10X_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup WWDG
- * @{
- */
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_PRESCALER
- * @{
- */
-#define WWDG_PRESCALER_1 ((uint32_t)0x00000000)
-#define WWDG_PRESCALER_2 ((uint32_t)0x00000080)
-#define WWDG_PRESCALER_4 ((uint32_t)0x00000100)
-#define WWDG_PRESCALER_8 ((uint32_t)0x00000180)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions ------------------------------------------------------- */
-/** @defgroup WWDG_Exported_Functions
- * @{
- */
-
-void WWDG_DeInit(void);
-void WWDG_SetPrescalerValue(uint32_t PrescalerValue);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableInt(void);
-void WWDG_SetCounterValue(uint8_t CounterValue);
-void WWDG_Enable(uint8_t CounterValue);
-TypeState WWDG_GetBitState(void);
-void WWDG_ClearBitState(void);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GD32F10X_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c
deleted file mode 100644
index 9d6205e1b2..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c
+++ /dev/null
@@ -1,977 +0,0 @@
-/**
- ******************************************************************************
- * @brief ADC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_adc.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/** @defgroup ADC_Private_Defines
- * @{
- */
-
-/* ADC CTLR1_DISNUM mask */
-#define CTLR1_DISNUM_RESET ((uint32_t)0xFFFF1FFF)
-
-/* ADC CTLR1_DISRC mask */
-#define CTLR1_DISRC_SET ((uint32_t)0x00000800)
-
-/* ADC CTLR1_ICA mask */
-#define CTLR1_ICA_SET ((uint32_t)0x00000400)
-
-/* ADC CTLR1_DISIC mask */
-#define CTLR1_DISIC_SET ((uint32_t)0x00001000)
-
-/* ADC CTLR1_AWCS mask */
-#define CTLR1_AWCS_RESET ((uint32_t)0xFFFFFFE0)
-
-/* ADC CTLR1_AWDMode mask */
-#define CTLR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)
-
-/* CTLR1 register mask */
-#define CTLR1_BITS_CLEAR ((uint32_t)0xFFF0FEFF)
-
-/* ADC CTLR2_ADCON mask */
-#define CTLR2_ADCON_SET ((uint32_t)0x00000001)
-
-/* ADC CTLR2_DMA mask */
-#define CTLR2_DMA_SET ((uint32_t)0x00000100)
-
-/* ADC CTLR2_RSTCLB mask */
-#define CTLR2_RSTCLB_SET ((uint32_t)0x00000008)
-
-/* ADC CTLR2_CLB mask */
-#define CTLR2_CLB_SET ((uint32_t)0x00000004)
-
-/* ADC CTLR2_SWRCST mask */
-#define CTLR2_SWRCST_SET ((uint32_t)0x00400000)
-
-/* ADC CTLR2_ETERC mask */
-#define CTLR2_ETERC_SET ((uint32_t)0x00100000)
-
-/* ADC CTLR2_ETERC_SWRCST mask */
-#define CTLR2_ETERC_SWRCST_SET ((uint32_t)0x00500000)
-
-/* ADC CTLR2_ETSIC mask */
-#define CTLR2_ETSIC_RESET ((uint32_t)0xFFFF8FFF)
-
-/* ADC CTLR2_ETEIC mask */
-#define CTLR2_ETEIC_SET ((uint32_t)0x00008000)
-
-/* ADC CTLR2_SWICST mask */
-#define CTLR2_SWICST_SET ((uint32_t)0x00200000)
-
-/* ADC CTLR2_ETEIC_SWICST mask */
-#define CTLR2_ETEIC_SWICST_SET ((uint32_t)0x00208000)
-
-/* ADC CTLR2_TSVREN mask */
-#define CTLR2_TSVREN_SET ((uint32_t)0x00800000)
-
-/* CTLR2 register mask */
-#define CTLR2_BITS_CLEAR ((uint32_t)0xFFF1F7FD)
-
-/* ADC RSQx mask */
-#define RSQ3_RSQ_SET ((uint32_t)0x0000001F)
-#define RSQ2_RSQ_SET ((uint32_t)0x0000001F)
-#define RSQ1_RSQ_SET ((uint32_t)0x0000001F)
-
-/* RSQ1 register mask */
-#define RSQ1_BITS_CLEAR ((uint32_t)0xFF0FFFFF)
-
-/* ADC ISQx mask */
-#define ISQ_ISQ_SET ((uint32_t)0x0000001F)
-
-/* ADC IL mask */
-#define ISQ_IL_SET ((uint32_t)0x00300000)
-
-/* ADC SPTx mask */
-#define SPT1_SPT_SET ((uint32_t)0x00000007)
-#define SPT2_SPT_SET ((uint32_t)0x00000007)
-
-/* ADC IDTRx registers offset */
-#define IDTR_OFFSET ((uint8_t)0x28)
-
-/* ADC0 RDTR register base address */
-#define RDTR_ADDRESS ((uint32_t)0x4001244C)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the ADC interface and init the sturct ADC_InitPara.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_InitParaStruct : the sturct ADC_InitPara pointer.
- * @retval None
- */
-void ADC_DeInit(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct)
-{
- if (ADCx == ADC0) {
- /* Enable ADC0 reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC0RST, ENABLE);
- /* Release ADC0 from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC0RST, DISABLE);
- } else if (ADCx == ADC1) {
- /* Enable ADC1 reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC1RST, ENABLE);
- /* Release ADC1 from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC1RST, DISABLE);
- }
- /* Initialize the ADC_Mode member,independent mode */
- ADC_InitParaStruct->ADC_Mode = ADC_MODE_INDEPENDENT;
- /* Initialize the ADC_Mode_Scan member,disable scan mode */
- ADC_InitParaStruct->ADC_Mode_Scan = DISABLE;
- /* Initialize the ADC_Mode_Continuous member,disable continuous mode */
- ADC_InitParaStruct->ADC_Mode_Continuous = DISABLE;
- /* Initialize the ADC_Trig_External member,choose T1 CC1 as external trigger */
- ADC_InitParaStruct->ADC_Trig_External = ADC_EXTERNAL_TRIGGER_MODE_T1_CC1;
- /* Initialize the ADC_Data_Align member,specifies the ADC data alignment right */
- ADC_InitParaStruct->ADC_Data_Align = ADC_DATAALIGN_RIGHT;
- /* Initialize the ADC_Channel_Number member,only 1 channel */
- ADC_InitParaStruct->ADC_Channel_Number = 1;
-}
-
-/**
- * @brief Initialize the ADCx interface parameters.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_InitParaStruct: the sturct ADC_InitPara pointer.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct)
-{
- uint32_t temp1 = 0;
- uint8_t temp2 = 0;
- /* ADCx CTLR1 Configuration */
- /* Get the ADCx CTLR1 previous value */
- temp1 = ADCx->CTLR1;
- /* Clear SM bits */
- temp1 &= CTLR1_BITS_CLEAR;
- /* Configure ADCx: Dual mode and scan conversion mode */
- /* Set DUALMOD bits according to ADC_Mode value */
- /* Configure SCAN bit according to ADC_Mode_Scan value */
- temp1 |= (uint32_t)(ADC_InitParaStruct->ADC_Mode | ((uint32_t)ADC_InitParaStruct->ADC_Mode_Scan << 8));
- /* Write new value to ADCx CTLR1 */
- ADCx->CTLR1 = temp1;
-
- /* ADCx CTLR2 Configuration */
- /* Get the ADCx CTLR2 previous value */
- temp1 = ADCx->CTLR2;
- /* Clear CTN, DAL and ETSRC bits */
- temp1 &= CTLR2_BITS_CLEAR;
- /* Configure ADCx: select external trigger mode and continuous conversion mode */
- /* Configure DAL bit according to ADC_Data_Align value */
- /* Configure ETSRC bits according to ADC_Trig_External value */
- /* Configure CTN bit according to ADC_Mode_Continuous value */
- temp1 |= (uint32_t)(ADC_InitParaStruct->ADC_Data_Align | ADC_InitParaStruct->ADC_Trig_External |
- ((uint32_t)ADC_InitParaStruct->ADC_Mode_Continuous << 1));
- /* Write new value to ADCx CTLR2 */
- ADCx->CTLR2 = temp1;
-
- /* ADCx RSQ1 Configuration */
- /* Get the ADCx RSQ1 previous value */
- temp1 = ADCx->RSQ1;
- /* Clear RL bits */
- temp1 &= RSQ1_BITS_CLEAR;
- /* Configure ADCx: regular channel sequence length */
- /* Configure RL bits according to ADC_Channel_Number value */
- temp2 |= (uint8_t)(ADC_InitParaStruct->ADC_Channel_Number - (uint8_t)1);
- temp1 |= (uint32_t)temp2 << 20;
- /* Write new value to ADCx RSQ1 */
- ADCx->RSQ1 = temp1;
-}
-
-/**
- * @brief Enable or disable the ADCx interface.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: New state of the ADCx interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ADCx interface */
- ADCx->CTLR2 |= CTLR2_ADCON_SET;
- } else {
- /* Disable the ADCx interface */
- ADCx->CTLR2 &= ~CTLR2_ADCON_SET;
- }
-}
-
-/**
- * @brief Enable or disable the ADCx DMA request.
- * @param ADCx: the ADC interface where x can be 1..3.
- * Note: ADC1 doesn't support DMA function.
- * @param NewValue: New state of ADCx DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMA_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable ADCx DMA request */
- ADCx->CTLR2 |= CTLR2_DMA_SET;
- } else {
- /* Disable ADCx DMA request */
- ADCx->CTLR2 &= ~CTLR2_DMA_SET;
- }
-}
-
-/**
- * @brief Enable or disable ADCx interrupts.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_INT: ADCx interrupt sources.
- * This parameter can be any combination of the following values:
- * @arg ADC_INT_EOC: Regular conversion over interrupt mask
- * @arg ADC_INT_AWE: Analog watchdog interrupt mask
- * @arg ADC_INT_EOIC: Inserted conversion over interrupt mask
- * @param NewValue: ADCx interrupts state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_INTConfig(ADC_TypeDef *ADCx, uint16_t ADC_INT, TypeState NewValue)
-{
- uint8_t temp_it = 0;
- /* ADCx INT old state */
- temp_it = (uint8_t)ADC_INT;
- if (NewValue != DISABLE) {
- /* Enable the ADCx interrupt */
- ADCx->CTLR1 |= temp_it;
- } else {
- /* Disable the ADCx interrupt */
- ADCx->CTLR1 &= (~(uint32_t)temp_it);
- }
-}
-
-/**
- * @brief ADCx calibration.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @retval None
- */
-void ADC_Calibration(ADC_TypeDef *ADCx)
-{
- /* Reset the selected ADCx calibration registers */
- ADCx->CTLR2 |= CTLR2_RSTCLB_SET;
- /* Check the RSTCLB bit state */
- while ((ADCx->CTLR2 & CTLR2_RSTCLB_SET));
- /* Enable ADCx calibration process */
- ADCx->CTLR2 |= CTLR2_CLB_SET;
- /* Check the CLB bit state */
- while ((ADCx->CTLR2 & CTLR2_CLB_SET) != (uint32_t)RESET);
-}
-
-/**
- * @brief Enable or disable ADCx software start conversion.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADCx software start conversion state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_SoftwareStartConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* ADCx software conversion start */
- ADCx->CTLR2 |= CTLR2_ETERC_SWRCST_SET;
- } else {
- /* ADCx software conversion stop */
- ADCx->CTLR2 &= ~CTLR2_ETERC_SWRCST_SET;
- }
-}
-
-/**
- * @brief Get the bit state of ADCx software start conversion.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @retval ADCx software start conversion state(SET or RESET).
- */
-TypeState ADC_GetSoftwareStartConvBitState(ADC_TypeDef *ADCx)
-{
- /* Check the SWRCST bit state*/
- if ((ADCx->CTLR2 & CTLR2_SWRCST_SET) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Configure the ADCx channel discontinuous mode.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param Number: the count value of discontinuous mode regular channel.
- * This number must be 1~8.
- * @retval None
- */
-void ADC_DiscModeChannelCount_Config(ADC_TypeDef *ADCx, uint8_t Number)
-{
- uint32_t temp1 = 0;
- uint32_t temp2 = 0;
- /* Get the old value of CTLR1 */
- temp1 = ADCx->CTLR1;
- /* Clear discontinuous mode channel count */
- temp1 &= CTLR1_DISNUM_RESET;
- /* Set the discontinuous mode channel count */
- temp2 = Number - 1;
- temp1 |= temp2 << 13;
- /* Write new value to CTLR1 */
- ADCx->CTLR1 = temp1;
-}
-
-/**
- * @brief Enable or disable the discontinuous mode.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADCx discontinuous mode state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable ADCx regular discontinuous mode */
- ADCx->CTLR1 |= CTLR1_DISRC_SET;
- } else {
- /* Disable ADCx regular discontinuous mode */
- ADCx->CTLR1 &= ~CTLR1_DISRC_SET;
- }
-}
-
-/**
- * @brief Configure array and sample time.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_Channel: the selected ADC channel.
- * This parameter can be as follows:
- * @arg ADC_CHANNEL_0: ADC Channel0
- * @arg ADC_CHANNEL_1: ADC Channel1
- * @arg ADC_CHANNEL_2: ADC Channel2
- * @arg ADC_CHANNEL_3: ADC Channel3
- * @arg ADC_CHANNEL_4: ADC Channel4
- * @arg ADC_CHANNEL_5: ADC Channel5
- * @arg ADC_CHANNEL_6: ADC Channel6
- * @arg ADC_CHANNEL_7: ADC Channel7
- * @arg ADC_CHANNEL_8: ADC Channel8
- * @arg ADC_CHANNEL_9: ADC Channel9
- * @arg ADC_CHANNEL_10: ADC Channel10
- * @arg ADC_CHANNEL_11: ADC Channel11
- * @arg ADC_CHANNEL_12: ADC Channel12
- * @arg ADC_CHANNEL_13: ADC Channel13
- * @arg ADC_CHANNEL_14: ADC Channel14
- * @arg ADC_CHANNEL_15: ADC Channel15
- * @arg ADC_CHANNEL_16: ADC Channel16
- * @arg ADC_CHANNEL_17: ADC Channel17
- * @param Array: The regular group sequencer rank. This parameter must be between 1 to 16.
- * @param ADC_SampleTime: The sample time value.
- * This parameter can be one of the following values:
- * @arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
- * @arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
- * @arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
- * @arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
- * @arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
- * @arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
- * @arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
- * @arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
- * @retval None
- */
-void ADC_RegularChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Array, uint8_t ADC_SampleTime)
-{
- uint32_t temp1 = 0, temp2 = 0;
-
- /* if ADC_Channel is between 10 to 17 */
- if (ADC_Channel > ADC_CHANNEL_9) {
- /* Get SPT1 value */
- temp1 = ADCx->SPT1;
- /* Calculate the mask to clear */
- temp2 = SPT1_SPT_SET << (3 * (ADC_Channel - 10));
- /* Clear sample time */
- temp1 &= ~temp2;
- /* Calculate the mask to set */
- temp2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
- /* Configure sample time */
- temp1 |= temp2;
- /* Write to SPT1 */
- ADCx->SPT1 = temp1;
- } else { /* ADC_Channel is between 0 to 9 */
- /* Get SPT2 value */
- temp1 = ADCx->SPT2;
- /* Calculate the mask to clear */
- temp2 = SPT2_SPT_SET << (3 * ADC_Channel);
- /* Clear sample time */
- temp1 &= ~temp2;
- /* Calculate the mask to set */
- temp2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set sample time */
- temp1 |= temp2;
- /* Write to SPT2 */
- ADCx->SPT2 = temp1;
- }
- /* For Array 1 to 6 */
- if (Array < 7) {
- /* Get RSQ3 value */
- temp1 = ADCx->RSQ3;
- /* Calculate the mask to clear */
- temp2 = RSQ3_RSQ_SET << (5 * (Array - 1));
- /* Clear RSQ3 bits */
- temp1 &= ~temp2;
- /* Calculate the mask to set */
- temp2 = (uint32_t)ADC_Channel << (5 * (Array - 1));
- /* Configure the RSQ3 bits */
- temp1 |= temp2;
- /* Write to RSQ3 */
- ADCx->RSQ3 = temp1;
- }
- /* For Array 7 to 12 */
- else if (Array < 13) {
- /* Get RSQ2 value */
- temp1 = ADCx->RSQ2;
- /* Calculate the mask to clear */
- temp2 = RSQ2_RSQ_SET << (5 * (Array - 7));
- /* Clear the old RSQ2 bits */
- temp1 &= ~temp2;
- /* Calculate the mask to set */
- temp2 = (uint32_t)ADC_Channel << (5 * (Array - 7));
- /* Set the RSQ2 bits */
- temp1 |= temp2;
- /* Write to RSQ2 */
- ADCx->RSQ2 = temp1;
- }
- /* For Array 13 to 16 */
- else {
- /* Get RSQ1 value */
- temp1 = ADCx->RSQ1;
- /* Calculate the mask to clear */
- temp2 = RSQ1_RSQ_SET << (5 * (Array - 13));
- /* Clear the old RSQ1 bits */
- temp1 &= ~temp2;
- /* Calculate the mask to set */
- temp2 = (uint32_t)ADC_Channel << (5 * (Array - 13));
- /* Set the RSQ1 bits */
- temp1 |= temp2;
- /* Write to RSQ1 */
- ADCx->RSQ1 = temp1;
- }
-}
-
-/**
- * @brief Enable or disable the ADCx external conversion.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADCx external trigger state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ExternalTrigConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable external trigger conversion */
- ADCx->CTLR2 |= CTLR2_ETERC_SET;
- } else {
- /* Disable external trigger conversion */
- ADCx->CTLR2 &= ~CTLR2_ETERC_SET;
- }
-}
-
-/**
- * @brief Return the ADCx regular channel conversion data.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @retval conversion data.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
-{
- /* Return ADCx conversion data */
- return (uint16_t) ADCx->RDTR;
-}
-
-/**
- * @brief Return the last ADC0 and ADC1 conversion result data in dual mode.
- * @retval The Data conversion value.
- */
-uint32_t ADC_GetDualModeConversionValue(void)
-{
- /* Return conversion value */
- return (*(__IO uint32_t *) RDTR_ADDRESS);
-}
-/**
- * @brief Enable or disable ADCx automatic inserted conversion.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADCx auto inserted conversion state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable ADCx automatic inserted conversion */
- ADCx->CTLR1 |= CTLR1_ICA_SET;
- } else {
- /* Disable ADCx automatic inserted conversion */
- ADCx->CTLR1 &= ~CTLR1_ICA_SET;
- }
-}
-
-/**
- * @brief Enable or disable the discontinuous mode for ADCx inserted group channel.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADCx discontinuous mode state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_InsertedDiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the inserted discontinuous mode of the selected ADC channel */
- ADCx->CTLR1 |= CTLR1_DISIC_SET;
- } else {
- /* Disable the inserted discontinuous mode of the selected ADC channel */
- ADCx->CTLR1 &= ~CTLR1_DISIC_SET;
- }
-}
-
-/**
- * @brief Configure the ADCx inserted channels external trigger conversion.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_ExternalTrigInsertConv: ADC inserted conversion trigger.
- * This parameter can be as follows:
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T1_TRGO: Timer1 TRIG event (used in ADC0, ADC1 and ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T1_CC4: Timer1 capture compare4 (used in ADC0, ADC1 and ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T2_TRGO: Timer2 TRIG event (used in ADC0 and ADC1)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T2_CC1: Timer2 capture compare1 (used in ADC0 and ADC1)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T3_CC4: Timer3 capture compare4 (used in ADC0 and ADC1)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T4_TRGO: Timer4 TRIG event (used in ADC0 and ADC1)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_EXT_IT15_T8_CC4: External interrupt line 15 or Timer8
- * capture compare4 (used in ADC0 and ADC1)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T4_CC3: Timer4 capture compare3 (used in ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC2: Timer8 capture compare2 (used in ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC4: Timer8 capture compare4 (used in ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T5_TRGO: Timer5 TRIG event (used in ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T5_CC4: Timer5 capture compare4 (used in ADC2)
- * @arg ADC_EXTERNAL_TRIG_INSERTCONV_NONE: Inserted conversion started by software (used in ADC0, ADC1 and ADC2)
- * @retval None
- */
-void ADC_ExternalTrigInsertedConv_Config(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInsertConv)
-{
- uint32_t temp = 0;
- /* Get CRLR2 value */
- temp = ADCx->CTLR2;
- /* Clear inserted external event */
- temp &= CTLR2_ETSIC_RESET;
- /* Configure inserted external event */
- temp |= ADC_ExternalTrigInsertConv;
- /* Write to CTLR2 */
- ADCx->CTLR2 = temp;
-}
-
-/**
- * @brief Enable or disable the ADCx inserted channels conversion through
- * external trigger
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADCx external trigger start of inserted conversion state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ExternalTrigInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable external event */
- ADCx->CTLR2 |= CTLR2_ETEIC_SET;
- } else {
- /* Disable external event */
- ADCx->CTLR2 &= ~CTLR2_ETEIC_SET;
- }
-}
-
-/**
- * @brief Enable or disable ADCx inserted channels conversion start.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param NewValue: ADC software start inserted conversion state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_SoftwareStartInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Start ADCx inserted conversion */
- ADCx->CTLR2 |= CTLR2_ETEIC_SWICST_SET;
- } else {
- /* Stop ADCx inserted conversion */
- ADCx->CTLR2 &= ~CTLR2_ETEIC_SWICST_SET;
- }
-}
-
-/**
- * @brief Get ADC Software start inserted conversion State.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @retval ADC software start inserted conversion state(SET or RESET).
- */
-TypeState ADC_GetSoftwareStartInsertedConvCmdBitState(ADC_TypeDef *ADCx)
-{
- /* Check SWICST bit */
- if ((ADCx->CTLR2 & CTLR2_SWICST_SET) != (uint32_t)RESET) {
- /* Set SWICST bit */
- return SET;
- } else {
- /* Reset SWICST bit */
- return RESET;
- }
-}
-
-/**
- * @brief Configure Array and sample time for the selected ADC inserted channel.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_Channel: the selected ADC channel.
- * This parameter can be as follows:
- * @arg ADC_CHANNEL_0: ADC Channel0
- * @arg ADC_CHANNEL_1: ADC Channel1
- * @arg ADC_CHANNEL_2: ADC Channel2
- * @arg ADC_CHANNEL_3: ADC Channel3
- * @arg ADC_CHANNEL_4: ADC Channel4
- * @arg ADC_CHANNEL_5: ADC Channel5
- * @arg ADC_CHANNEL_6: ADC Channel6
- * @arg ADC_CHANNEL_7: ADC Channel7
- * @arg ADC_CHANNEL_8: ADC Channel8
- * @arg ADC_CHANNEL_9: ADC Channel9
- * @arg ADC_CHANNEL_10: ADC Channel10
- * @arg ADC_CHANNEL_11: ADC Channel11
- * @arg ADC_CHANNEL_12: ADC Channel12
- * @arg ADC_CHANNEL_13: ADC Channel13
- * @arg ADC_CHANNEL_14: ADC Channel14
- * @arg ADC_CHANNEL_15: ADC Channel15
- * @arg ADC_CHANNEL_16: ADC Channel16
- * @arg ADC_CHANNEL_17: ADC Channel17
- * @param Array: The inserted group sequencer Array. This parameter must be between 1 and 4.
- * @param ADC_SampleTime: The sample time of the selected channel.
- * This parameter can be as follows:
- * @arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
- * @arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
- * @arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
- * @arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
- * @arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
- * @arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
- * @arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
- * @arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
- * @retval None
- */
-void ADC_InsertedChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Array, uint8_t ADC_SampleTime)
-{
- uint32_t temp1 = 0, temp2 = 0, temp3 = 0;
-
- /* if ADC_Channel is between 10 to 17 */
- if (ADC_Channel > ADC_CHANNEL_9) {
- /* Get SPT1 value */
- temp1 = ADCx->SPT1;
- /* Calculate the sample time mask */
- temp2 = SPT1_SPT_SET << (3 * (ADC_Channel - 10));
- /* Clear sample time */
- temp1 &= ~temp2;
- /* Calculate the sample time mask */
- temp2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
- /* Set sample time */
- temp1 |= temp2;
- /* Write to SPT1 */
- ADCx->SPT1 = temp1;
- } else { /* ADC_Channel is between 0 to 9 */
- /* Get SPT2 value */
- temp1 = ADCx->SPT2;
- /* Calculate the sample time mask */
- temp2 = SPT2_SPT_SET << (3 * ADC_Channel);
- /* Clear sample time */
- temp1 &= ~temp2;
- /* Calculate the sample time mask */
- temp2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
- /* Set sample time */
- temp1 |= temp2;
- /* Write to SPT2 */
- ADCx->SPT2 = temp1;
- }
- /* Array configuration */
- /* Get ISQ value */
- temp1 = ADCx->ISQ;
- /* Get IL value: Number = IL+1 */
- temp3 = (temp1 & ISQ_IL_SET) >> 20;
- /* Calculate the ISQ mask : ((Array-1)+(4-IL-1)) */
- temp2 = ISQ_ISQ_SET << (5 * (uint8_t)((Array + 3) - (temp3 + 1)));
- /* Clear ISQx bits */
- temp1 &= ~temp2;
- /* Calculate the ISQ mask: ((Array-1)+(4-IL-1)) */
- temp2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Array + 3) - (temp3 + 1)));
- /* Set ISQx bits */
- temp1 |= temp2;
- /* Write to ISQ */
- ADCx->ISQ = temp1;
-}
-
-/**
- * @brief Configure the sequencer length of inserted channels
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param Length: The sequencer length.
- * This parameter must be a number between 1 to 4.
- * @retval None
- */
-void ADC_InsertedSequencerLength_Config(ADC_TypeDef *ADCx, uint8_t Length)
-{
- uint32_t temp1 = 0;
- uint32_t temp2 = 0;
- /* Get ISQ value */
- temp1 = ADCx->ISQ;
- /* Clear IL bits */
- temp1 &= ~ISQ_IL_SET;
- /* Set IL bits */
- temp2 = Length - 1;
- temp1 |= temp2 << 20;
- /* Write to ISQ */
- ADCx->ISQ = temp1;
-}
-
-/**
- * @brief Set the offset of the inserted channels conversion value.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_InsertedChannel: one of the four inserted channels to set its offset.
- * This parameter can be one of the following values:
- * @arg ADC_INSERTEDCHANNEL_1: Inserted Channel1
- * @arg ADC_INSERTEDCHANNEL_2: Inserted Channel2
- * @arg ADC_INSERTEDCHANNEL_3: Inserted Channel3
- * @arg ADC_INSERTEDCHANNEL_4: Inserted Channel4
- * @param Offset: the offset value of the selected ADC inserted channel
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_SetInsertedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel, uint16_t Offset)
-{
- __IO uint32_t temp = 0;
- temp = (uint32_t)ADCx;
- temp += ADC_InsertedChannel;
-
- /* Set the offset of the selected inserted channel */
- *(__IO uint32_t *) temp = (uint32_t)Offset;
-}
-
-/**
- * @brief Get the ADC inserted channel conversion result
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_InsertedChannel: ADC inserted channel.
- * This parameter can be one of the following values:
- * @arg ADC_INSERTEDCHANNEL_1: Inserted Channel1
- * @arg ADC_INSERTEDCHANNEL_2: Inserted Channel2
- * @arg ADC_INSERTEDCHANNEL_3: Inserted Channel3
- * @arg ADC_INSERTEDCHANNEL_4: Inserted Channel4
- * @retval The conversion value.
- */
-uint16_t ADC_GetInsertedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel)
-{
- __IO uint32_t temp = 0;
- temp = (uint32_t)ADCx;
- temp += ADC_InsertedChannel + IDTR_OFFSET;
-
- /* Return the result of the selected inserted channel conversion */
- return (uint16_t)(*(__IO uint32_t *) temp);
-}
-
-/**
- * @brief Enable or disable the analog watchdog.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
- * This parameter can be one of the following values:
- * @arg ADC_ANALOGWATCHDOG_SINGLEREGENABLE: single regular channel
- * @arg ADC_ANALOGWATCHDOG_SINGLEINSERTENABLE: single inserted channel
- * @arg ADC_ANALOGWATCHDOG_SINGLEREGORINSERTENABLE: single regular or inserted channel
- * @arg ADC_ANALOGWATCHDOG_ALLREGENABLE: all regular channel
- * @arg ADC_ANALOGWATCHDOG_ALLINSERTENABLE: all inserted channel
- * @arg ADC_ANALOGWATCHDOG_ALLREGALLINSERTENABLE: all regular and inserted channels
- * @arg ADC_ANALOGWATCHDOG_NONE: No channel
- * @retval None
- */
-void ADC_AnalogWatchdog_Enable(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
-{
- uint32_t temp = 0;
- /* Get CTLR1 value */
- temp = ADCx->CTLR1;
- /* Clear AWDEN, AWDENJ and AWDSGL bits */
- temp &= CTLR1_AWDMODE_RESET;
- /* Set the analog watchdog mode */
- temp |= ADC_AnalogWatchdog;
- /* Write to CTLR1 */
- ADCx->CTLR1 = temp;
-}
-
-/**
- * @brief Configure the high and low thresholds of the analog watchdog.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholds_Config(ADC_TypeDef *ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Set the ADCx high threshold */
- ADCx->AWHT = HighThreshold;
- /* Set the ADCx low threshold */
- ADCx->AWLT = LowThreshold;
-}
-
-/**
- * @brief Configure the analog watchdog on single channel mode.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_Channel: ADC channel.
- * This parameter can be as follows:
- * @arg ADC_CHANNEL_0: ADC Channel0
- * @arg ADC_CHANNEL_1: ADC Channel1
- * @arg ADC_CHANNEL_2: ADC Channel2
- * @arg ADC_CHANNEL_3: ADC Channel3
- * @arg ADC_CHANNEL_4: ADC Channel4
- * @arg ADC_CHANNEL_5: ADC Channel5
- * @arg ADC_CHANNEL_6: ADC Channel6
- * @arg ADC_CHANNEL_7: ADC Channel7
- * @arg ADC_CHANNEL_8: ADC Channel8
- * @arg ADC_CHANNEL_9: ADC Channel9
- * @arg ADC_CHANNEL_10: ADC Channel10
- * @arg ADC_CHANNEL_11: ADC Channel11
- * @arg ADC_CHANNEL_12: ADC Channel12
- * @arg ADC_CHANNEL_13: ADC Channel13
- * @arg ADC_CHANNEL_14: ADC Channel14
- * @arg ADC_CHANNEL_15: ADC Channel15
- * @arg ADC_CHANNEL_16: ADC Channel16
- * @arg ADC_CHANNEL_17: ADC Channel17
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
-{
- uint32_t temp = 0;
- /* Get CTLR1 value */
- temp = ADCx->CTLR1;
- /* Clear AWCS */
- temp &= CTLR1_AWCS_RESET;
- /* Set the Analog watchdog channel */
- temp |= ADC_Channel;
- /* Write to CTLR1 */
- ADCx->CTLR1 = temp;
-}
-
-/**
- * @brief Enable or disable the temperature sensor and Vrefint channel.
- * @param NewValue: the state of the temperature sensor.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorVrefint_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the temperature sensor and Vrefint channel*/
- ADC0->CTLR2 |= CTLR2_TSVREN_SET;
- } else {
- /* Disable the temperature sensor and Vrefint channel*/
- ADC0->CTLR2 &= ~CTLR2_TSVREN_SET;
- }
-}
-
-/**
- * @brief Check the ADC flag.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_FLAG: the flag to check.
- * This parameter can be as follows:
- * @arg ADC_FLAG_AWE: The flag of the analog watchdog
- * @arg ADC_FLAG_EOC: The flag of the end of conversion
- * @arg ADC_FLAG_EOIC: The flag of the end of inserted group conversion
- * @arg ADC_FLAG_STIC: The flag of the start of inserted group conversion
- * @arg ADC_FLAG_STRC: The flag of the start of regular group conversion
- * @retval ADC_FLAG state(SET or RESET).
- */
-TypeState ADC_GetBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
-{
- /* Check the specified ADC flag state */
- if ((ADCx->STR & ADC_FLAG) != (uint8_t)RESET) {
- /* ADC_FLAG is set */
- return SET;
- } else {
- /* ADC_FLAG is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the ADCx's pending flags.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_FLAG: the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWE: The flag of the analog watchdog
- * @arg ADC_FLAG_EOC: The flag of the end of conversion
- * @arg ADC_FLAG_EOIC: The flag of the end of inserted group conversion
- * @arg ADC_FLAG_STIC: The flag of the start of inserted group conversion
- * @arg ADC_FLAG_STRC: The flag of the start of regular group conversion
- * @retval None
- */
-void ADC_ClearBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
-{
- /* Clear the selected ADC flags */
- ADCx->STR = ~(uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Check the specified ADC interrupt.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_INT: ADC interrupt source.
- * This parameter can be one of the following values:
- * @arg ADC_INT_EOC: The interrupt mask of the end of conversion
- * @arg ADC_INT_AWE: The interrupt mask of the analog watchdog
- * @arg ADC_INT_EOIC: The interrupt mask of the end of inserted conversion
- * @retval The new value of ADC_INT (SET or RESET).
- */
-TypeState ADC_GetIntState(ADC_TypeDef *ADCx, uint16_t ADC_INT)
-{
- uint32_t temp_it = 0, temp_enable = 0;
- /* Get the ADC interrupt mask index */
- temp_it = ADC_INT >> 8;
- /* Get the ADC_INT enable bit state */
- temp_enable = (ADCx->CTLR1 & (uint8_t)ADC_INT) ;
- /* Check the state of the specified ADC interrupt */
- if (((ADCx->STR & temp_it) != (uint32_t)RESET) && temp_enable) {
- /* ADC_INT is set */
- return SET;
- } else {
- /* ADC_INT is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the ADCx's interrupt pending bits.
- * @param ADCx: the ADC interface where x can be 1..3.
- * @param ADC_INT: the ADC interrupt pending bit.
- * This parameter can be any combination of the following values:
- * @arg ADC_INT_EOC: The interrupt mask of the end of conversion
- * @arg ADC_INT_AWE: The interrupt mask of the analog watchdog
- * @arg ADC_INT_EOIC: The interrupt mask of the end of inserted conversion
- * @retval None
- */
-void ADC_ClearIntBitState(ADC_TypeDef *ADCx, uint16_t ADC_INT)
-{
- uint8_t temp_it = 0;
- /* Get the ADC interrupt mask index */
- temp_it = (uint8_t)(ADC_INT >> 8);
- /* Clear ADCx interrupt pending bits */
- ADCx->STR = ~(uint32_t)temp_it;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_bkp.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_bkp.c
deleted file mode 100644
index 28f219825b..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_bkp.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/**
- ******************************************************************************
- * @brief BKP functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_bkp.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup BKP
- * @brief BKP driver modules
- * @{
- */
-
-/** @defgroup BKP_Private_Defines
- * @{
- */
-/* RTCOUTPUT bit is masked in BKP_RCCR register */
-#define RTCOUTPUT_MASK ((uint16_t)0xFC7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup BKP_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the BKP peripheral registers.
- * @param None
- * @retval None
- */
-void BKP_DeInit(void)
-{
- RCC_BackupReset_Enable(ENABLE);
- RCC_BackupReset_Enable(DISABLE);
-}
-
-/**
- * @brief Write user data to the BKP_DRx register.
- * @param BKP_DR: the Backup Data Register.
- * This parameter can be BKP_DRx where x can be (1..42)
- * @param Data: data to write
- * @retval None
- */
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
-{
- __IO uint32_t temp = 0;
-
- temp = (uint32_t)BKP_BASE;
- temp += BKP_DR;
-
- /* Store the write data */
- *(__IO uint16_t *) temp = Data;
-}
-
-/**
- * @brief Read data from the BKP_DRx register.
- * @param BKP_DR: The Backup Data Register.
- * This parameter can be BKP_DRx where x can be (1..42)
- * @retval The content of the BKP_DRx register.
- */
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
-{
- __IO uint32_t temp = 0;
-
- temp = (uint32_t)BKP_BASE;
- temp += BKP_DR;
-
- /* Return the BKP_DRx register value */
- return (*(__IO uint16_t *) temp);
-}
-
-/**
- * @brief Configure the RTC output on the Tamper pin.
- * @param BKP_RTCOUTPUT: the RTC output.
- * This parameter can be one of the following values:
- * @arg BKP_RTCOUTPUT_NULL: no RTC output on the TAMPER pin.
- * @arg BKP_RTCOUTPUT_CLKCAL: output the RTC clock with frequency
- * divided by 64 on the TAMPER pin.
- * @arg BKP_RTCOUTPUT_ALARM: output the RTC Alarm pulse signal on
- * the TAMPER pin.
- * @arg BKP_RTCOUTPUT_SECOND: output the RTC Second pulse signal on
- * the TAMPER pin.
- * @retval None
- */
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT)
-{
- uint16_t temp = 0;
-
- temp = BKP->RCCR;
-
- /* Clear RCCOE, ROE and ROS bits */
- temp &= RTCOUTPUT_MASK;
-
- /* Set RCCOE, ROE and ROS bits according to BKP_RTCOUTPUT value */
- temp |= BKP_RTCOUTPUT;
-
- /* Store the new value */
- BKP->RCCR = temp;
-}
-
-/**
- * @brief Set RTC Clock Calibration value.
- * @param CalibrationValue: the RTC Clock Calibration value.
- * This parameter must be a number between 0 and 0x7F.
- * @retval None
- */
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
-{
- uint16_t temp = 0;
-
- temp = BKP->RCCR;
-
- /* Clear RCCV[6:0] bits */
- temp &= ~BKP_RCCR_RCCV;
-
- /* Set CAL[6:0] bits according to CalibrationValue */
- temp |= CalibrationValue;
-
- /* Store the new value */
- BKP->RCCR = temp;
-}
-
-/**
- * @brief Configure the TAMPER pin active level.
- * @param BKP_TPAL: the TAMPER pin active level.
- * This parameter can be one of the following values:
- * @arg BKP_TPAL_HIGH: TAMPER pin active on high level
- * @arg BKP_TPAL_LOW: TAMPER pin active on low level
- * @param NewValue: New value of the TAMPER pin state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue)
-{
- uint16_t temp = 0;
-
- temp = BKP->TPCR;
-
- /* Clear TPE bit */
- temp &= ~((uint16_t)BKP_TPCR_TPE);
-
- /* Configure TPAL bit according to BKP_TPAL value */
- temp |= BKP_TPAL;
-
- /* Store the new value */
- BKP->TPCR = temp;
-
- /* Enable the TAMPER pin */
- if (NewValue != DISABLE) {
- /* The TAMPER pin is dedicated for the Backup Reset function */
- BKP->TPCR |= BKP_TPCR_TPE;
- } else {
- /* The TAMPER pin is free for GPIO functions */
- BKP->TPCR &= ~((uint16_t)BKP_TPCR_TPE);
- }
-}
-
-/**
- * @brief Enable or disable the Tamper Interrupt.
- * @param NewValue: New value of the Tamper Interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void BKP_TamperINT_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the tamper interrupt */
- BKP->TIER |= BKP_TIER_TIE;
- } else {
- /* Disable the tamper interrupt */
- BKP->TIER &= ~BKP_TIER_TIE;
- }
-}
-
-/**
- * @brief Get the bit flag of Tamper Event.
- * @param None
- * @retval The new value of Tamper Event flag (SET or RESET).
- */
-TypeState BKP_GetBitState(void)
-{
- /* Check and get the Tamper Event flag */
- if ((BKP->TIER & BKP_TIER_TEF) != (uint16_t)RESET) {
- /* Tamper Event occured */
- return SET;
- } else {
- /* No Tamper Event occured */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the bit flag of Tamper Event.
- * @param None
- * @retval None
- */
-void BKP_ClearBitState(void)
-{
- /* Set the TER bit to clear Tamper Event flag */
- BKP->TIER |= BKP_TIER_TER;
-}
-
-/**
- * @brief Get the interrupt bit flag of Tamper Interrupt.
- * @param None
- * @retval The new value of the Tamper Interrupt flag (SET or RESET).
- */
-TypeState BKP_GetIntBitState(void)
-{
- /* Check and get the Tamper Interrupt flag */
- if ((BKP->TIER & BKP_TIER_TIF) != (uint16_t)RESET) {
- /* Tamper Interrupt occured */
- return SET;
- } else {
- /* No Tamper Interrupt occured */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt bit flag of Tamper Interrupt.
- * @param None
- * @retval None
- */
-void BKP_ClearIntBitState(void)
-{
- /* Set the TIR bit to clear Tamper Interrupt flag */
- BKP->TIER |= BKP_TIER_TIR;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_can.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_can.c
deleted file mode 100644
index 604dca5caa..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_can.c
+++ /dev/null
@@ -1,1120 +0,0 @@
-/**
- ******************************************************************************
- * @brief CAN functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_can.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-
-/** @defgroup CAN_Private_Defines
- * @{
- */
-
-
-/* CAN Mailbox Transmit Request */
-#define CAN_TMIR_TE ((uint32_t)0x00000001)
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001)
-
-/* Time out for IWS bit */
-#define IWS_TIMEOUT ((uint32_t)0x0000FFFF)
-/* Time out for SWS bit */
-#define SWS_TIMEOUT ((uint32_t)0x0000FFFF)
-
-/* CAN TMIR_StdId masks */
-#define CAN_TMIR_StdId_Mask ((uint32_t)0x000007FF)
-
-/* CAN TMIR_ExtId masks */
-#define CAN_TMIR_ExtId_Mask ((uint32_t)0x1FFFFFFF)
-
-/* CAN TMIR_ExtId masks */
-#define CAN_FLAG_Mask ((uint32_t)0x000FFFFF)
-
-/* Flags in TSTR register */
-#define CAN_FLAGS_TSTR ((uint32_t)0x08000000)
-
-/* Flags in RFR1 register */
-#define CAN_FLAGS_RFR1 ((uint32_t)0x04000000)
-
-/* Flags in RFR0register */
-#define CAN_FLAGS_RFR0 ((uint32_t)0x02000000)
-
-/* Flags in STR register */
-#define CAN_FLAGS_STR ((uint32_t)0x01000000)
-
-/* Flags in ER register */
-#define CAN_FLAGS_ER ((uint32_t)0x00F00000)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-/* CAN Master Control Register bit */
-#define MCR_DBF ((uint32_t)0x00010000)
-
-
-#define CAN_MODE_MASK ((uint32_t)0x00000003)
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitialize the CAN peripheral registers.
- * @param CANx: where x:[1,2] to select the CAN peripheral.
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef *CANx)
-{
- if (CANx == CAN1) {
- /* Force CAN1 reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN1, ENABLE);
- /* Release CAN1 from reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN1, DISABLE);
- } else {
- /* Force CAN2 reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN2, ENABLE);
- /* Release CAN2 from reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN2, DISABLE);
- }
-}
-
-/**
- * @brief Initialize the CAN peripheral according to the CAN_InitParaStruct.
- * @param CANx:where x:[1,2]
- * @param CAN_InitParaStruct: contain the configuration information for the CAN peripheral.
- * @retval It will be returned the status of CAN_INITSTATE_FAILED or CAN_INITSTATE_SUCCESS.
- */
-uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitPara *CAN_InitParaStruct)
-{
- uint32_t wait_ack = 0x00000000;
-
- /* Out of sleep mode */
- CANx->CTLR &= (~(uint32_t)CAN_CTLR_SWM);
-
- /* Enable initial working */
- CANx->CTLR |= CAN_CTLR_IWM ;
-
- /* Wait the acknowledge */
- while (((CANx->STR & CAN_STR_IWS) != CAN_STR_IWS) && (wait_ack != IWS_TIMEOUT)) {
- wait_ack++;
- }
-
- /* Check whether initial working is success */
- if ((CANx->STR & CAN_STR_IWS) != CAN_STR_IWS) {
- return CAN_INITSTATE_FAILED;
- } else {
- /* Set the time triggered communication mode */
- if (CAN_InitParaStruct->CAN_TTC == ENABLE) {
- CANx->CTLR |= CAN_CTLR_TTC;
- } else {
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTC;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitParaStruct->CAN_ABOR == ENABLE) {
- CANx->CTLR |= CAN_CTLR_ABOR;
- } else {
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOR;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitParaStruct->CAN_AWK == ENABLE) {
- CANx->CTLR |= CAN_CTLR_AWK;
- } else {
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWK;
- }
-
- /* Set the automatic retransmission mode */
- if (CAN_InitParaStruct->CAN_ARD == ENABLE) {
- CANx->CTLR |= CAN_CTLR_ARD;
- } else {
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_ARD;
- }
-
- /* Set receive FIFO overwrite mode */
- if (CAN_InitParaStruct->CAN_RFOD == ENABLE) {
- CANx->CTLR |= CAN_CTLR_RFOD;
- } else {
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFOD;
- }
-
- /* Set the Transmit FIFO order */
- if (CAN_InitParaStruct->CAN_TFO == ENABLE) {
- CANx->CTLR |= CAN_CTLR_TFO;
- } else {
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_TFO;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitParaStruct->CAN_Mode << 30) | \
- ((uint32_t)CAN_InitParaStruct->CAN_SJW << 24) | \
- ((uint32_t)CAN_InitParaStruct->CAN_BS1 << 16) | \
- ((uint32_t)CAN_InitParaStruct->CAN_BS2 << 20) | \
- ((uint32_t)CAN_InitParaStruct->CAN_Prescaler - 1);
-
- /* leave initialisation */
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_IWM;
-
- /* Wait the acknowledge */
- wait_ack = 0;
-
- while (((CANx->STR & CAN_STR_IWS) == CAN_STR_IWS) && (wait_ack != IWS_TIMEOUT)) {
- wait_ack++;
- }
-
- /* Check whether qiut initial working mode */
- if ((CANx->STR & CAN_STR_IWS) == CAN_STR_IWS) {
- return CAN_INITSTATE_FAILED;
- } else {
- return CAN_INITSTATE_SUCCESS;
- }
- }
-
-}
-
-/**
- * @brief Initialize the CAN peripheral according to the CAN_FilterInitStruct.
- * @param CAN_FilterInitParaStruct:contain the information for the CAN peripheral.
- * @retval None.
- */
-void CAN_FilterInit(CAN_FilterInitPara *CAN_FilterInitParaStruct)
-{
- uint32_t filter_number = 0;
-
- filter_number = ((uint32_t)1) << CAN_FilterInitParaStruct->CAN_FilterNumber;
-
- /* Set filter lock disable */
- CAN1->FCTLR |= CAN_FCTLR_FLD;
-
- /* Disable Filter */
- CAN1->FWR &= ~(uint32_t)filter_number;
-
- /* Filter Scale */
- if (CAN_FilterInitParaStruct->CAN_FilterScale == CAN_FILTERSCALE_16BIT) {
- /* Set the filter 16-bit scale*/
- CAN1->FSR &= ~(uint32_t)filter_number;
-
- /* First 16-bit list and First 16-bit mask */
- /* Or First 16-bit list and Second 16-bit list */
- CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD0R =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD1R =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListHigh);
- }
-
- if (CAN_FilterInitParaStruct->CAN_FilterScale == CAN_FILTERSCALE_32BIT) {
- /* 32-bit scale for the filter */
- CAN1->FSR |= filter_number;
- /* 32-bit identifier or First 32-bit identifier */
- CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD0R =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD1R =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitParaStruct->CAN_FilterMode == CAN_FILTERMODE_MASK) {
- /*Filter with Mask mode*/
- CAN1->FMR &= ~(uint32_t)filter_number;
- } else { /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FILTERMODE_LIST */
- /*Filter with List mode*/
- CAN1->FMR |= (uint32_t)filter_number;
- }
-
- /* Filter associated with FIFO */
- if (CAN_FilterInitParaStruct->CAN_FilterFIFOAssociation == CAN_FILTER_FIFO0) {
- /* Filter associated with FIFO 0 */
- CAN1->FAFR &= ~(uint32_t)filter_number;
- }
-
- if (CAN_FilterInitParaStruct->CAN_FilterFIFOAssociation == CAN_FILTER_FIFO1) {
- /* Filter associated with FIFO 1 */
- CAN1->FAFR |= (uint32_t)filter_number;
- }
-
- /* Filter working */
- if (CAN_FilterInitParaStruct->CAN_FilterWork == ENABLE) {
- CAN1->FWR |= filter_number;
- }
-
- /* Exit the initialisation mode for the filter */
- CAN1->FCTLR &= ~CAN_FCTLR_FLD;
-}
-
-/**
- * @brief Configure each CAN_InitParaStruct member with default value.
- * @param CAN_InitParaStruct: pointer to a CAN_InitPara structure to initialize.
- * @retval None.
- */
-void CAN_StructInit(CAN_InitPara *CAN_InitParaStruct)
-{
- /* Set the time triggered communication mode */
- CAN_InitParaStruct->CAN_TTC = DISABLE;
-
- /* Set the automatic bus-off recovery */
- CAN_InitParaStruct->CAN_ABOR = DISABLE;
-
- /* Set the automatic wake up mode */
- CAN_InitParaStruct->CAN_AWK = DISABLE;
-
- /* Set the automatic retransmission disable */
- CAN_InitParaStruct->CAN_ARD = DISABLE;
-
- /* Set the receive FIFO overwrite mode */
- CAN_InitParaStruct->CAN_RFOD = DISABLE;
-
- /* Set the transmit FIFO order */
- CAN_InitParaStruct->CAN_TFO = DISABLE;
-
- /* Set the CAN_Mode member */
- CAN_InitParaStruct->CAN_Mode = CAN_MODE_NORMAL;
-
- /* Set the CAN_SJW member */
- CAN_InitParaStruct->CAN_SJW = CAN_SJW_1TQ;
-
- /* Set the CAN_BS1 member */
- CAN_InitParaStruct->CAN_BS1 = CAN_BS1_4TQ;
-
- /* Set the CAN_BS2 member */
- CAN_InitParaStruct->CAN_BS2 = CAN_BS2_3TQ;
-
- /* Set the CAN_Prescaler member */
- CAN_InitParaStruct->CAN_Prescaler = 1;
-}
-
-/**
- * @brief Set header bank of CAN2 filter.
- * @param CAN2_HeaderBankNumber: Select header bank of CAN2 filter.It can be 1 to 27.
- * @retval None.
- */
-void CAN_HeaderBank(uint8_t CAN_HeaderBankNumber)
-{
- /* Set filter lock disable */
- CAN1->FCTLR |= CAN_FCTLR_FLD;
-
- /* Select filter start number for slave CAN */
- CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ;
- CAN1->FCTLR |= (uint32_t)(CAN_HeaderBankNumber) << 8;
-
- /* Filter out the initialization mode */
- CAN1->FCTLR |= ~CAN_FCTLR_FLD;
-}
-
-/**
- * @brief Enable or disable the Debug Freeze for CAN.
- * @param CANx: where x :[1,2] for selecting the CAN peripheral.
- * @param NewValue: new state of the CAN peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void CAN_DebugFreeze(CAN_TypeDef *CANx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- CANx->CTLR |= CAN_CTLR_DFZ;
- } else {
- CANx->CTLR &= ~CAN_CTLR_DFZ;
- }
-}
-
-
-/**
- * @brief Enable or disabe the CAN Time Triggered communication mode.
- * @param CANx:where x :[1,2] for selecting the CAN peripheral.
- * @param NewValue : Mode new state , This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CAN_TimeTrigComMode_Enable(CAN_TypeDef *CANx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the TTC mode */
- CANx->CTLR |= CAN_CTLR_TTC;
-
- /* Set TSEbits */
- CANx->TxMailBox[0].TMPR |= ((uint32_t)CAN_TMPR0_TSE);
- CANx->TxMailBox[1].TMPR |= ((uint32_t)CAN_TMPR1_TSE);
- CANx->TxMailBox[2].TMPR |= ((uint32_t)CAN_TMPR2_TSE);
- } else {
- /* Disable the TTC mode */
- CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTC);
-
- /* Reset TSE bits */
- CANx->TxMailBox[0].TMPR &= ((uint32_t)~CAN_TMPR0_TSE);
- CANx->TxMailBox[1].TMPR &= ((uint32_t)~CAN_TMPR1_TSE);
- CANx->TxMailBox[2].TMPR &= ((uint32_t)~CAN_TMPR2_TSE);
- }
-}
-/**
- * @brief Initiate to transmit a message.
- * @param CANx: where x:[1,2]to to select the CAN peripheral.
- * @param TxMessage: contain CAN Id, CAN DLC and CAN data for the structure.
- * @retval The number of the mailbox that is used for transmission
- * or CAN_TxState_NoMailBox if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMessage *TxMessage)
-{
- uint8_t transmit_mailbox_number = 0;
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSTR & CAN_TSTR_TME0) == CAN_TSTR_TME0) {
- transmit_mailbox_number = 0;
- } else if ((CANx->TSTR & CAN_TSTR_TME1) == CAN_TSTR_TME1) {
- transmit_mailbox_number = 1;
- } else if ((CANx->TSTR & CAN_TSTR_TME2) == CAN_TSTR_TME2) {
- transmit_mailbox_number = 2;
- } else {
- transmit_mailbox_number = CAN_TXSTATE_NOMAILBOX;
- }
-
- if (transmit_mailbox_number != CAN_TXSTATE_NOMAILBOX) {
- /* Set up the Id */
- CANx->TxMailBox[transmit_mailbox_number].TMIR &= CAN_TMIR_TE;
- if (TxMessage->FF == CAN_FF_STANDARD) {
- CANx->TxMailBox[transmit_mailbox_number].TMIR |= ((TxMessage->StdId << 21) | \
- TxMessage->FT);
- } else {
- CANx->TxMailBox[transmit_mailbox_number].TMIR |= ((TxMessage->ExtId << 3) | \
- TxMessage->FF | \
- TxMessage->FT);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= ((uint8_t)CAN_TMPR0_DLC);
- CANx->TxMailBox[transmit_mailbox_number].TMPR &= ((uint32_t)~CAN_TMPR0_DLC);
- CANx->TxMailBox[transmit_mailbox_number].TMPR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->TxMailBox[transmit_mailbox_number].TMD0R = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->TxMailBox[transmit_mailbox_number].TMD1R = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->TxMailBox[transmit_mailbox_number].TMIR |= CAN_TMIR0_TE;
- }
- return transmit_mailbox_number;
-}
-
-/**
- * @brief Check the state of message transmission.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param TransmitMailbox: the number of the used transmission mailbox.
- * @retval Return CAN_TXSTATE_OK or CAN_TXSTATE_FAILED.
- */
-uint8_t CAN_TransmitState(CAN_TypeDef *CANx, uint8_t TransmitMailbox)
-{
- uint32_t state = 0;
-
- switch (TransmitMailbox) {
- case (CAN_TXMAILBOX_0):
- state = CANx->TSTR & (CAN_TSTR_MTF0 | CAN_TSTR_MTFNE0 | CAN_TSTR_TME0);
- break;
- case (CAN_TXMAILBOX_1):
- state = CANx->TSTR & (CAN_TSTR_MTF1 | CAN_TSTR_MTFNE1 | CAN_TSTR_TME1);
- break;
- case (CAN_TXMAILBOX_2):
- state = CANx->TSTR & (CAN_TSTR_MTF2 | CAN_TSTR_MTFNE2 | CAN_TSTR_TME2);
- break;
- default:
- state = CAN_TXSTATE_FAILED;
- break;
- }
- switch (state) {
- /* transmit pending */
- case (0x0):
- state = CAN_TXSTATE_PENDING;
- break;
- /* transmit failed */
- case (CAN_TSTR_MTF0 | CAN_TSTR_TME0):
- state = CAN_TXSTATE_FAILED;
- break;
- case (CAN_TSTR_MTF1 | CAN_TSTR_TME1):
- state = CAN_TXSTATE_FAILED;
- break;
- case (CAN_TSTR_MTF2 | CAN_TSTR_TME2):
- state = CAN_TXSTATE_FAILED;
- break;
- /* transmit succeeded */
- case (CAN_TSTR_MTF0 | CAN_TSTR_MTFNE0 | CAN_TSTR_TME0):
- state = CAN_TXSTATE_OK;
- break;
- case (CAN_TSTR_MTF1 | CAN_TSTR_MTFNE1 | CAN_TSTR_TME1):
- state = CAN_TXSTATE_OK;
- break;
- case (CAN_TSTR_MTF2 | CAN_TSTR_MTFNE2 | CAN_TSTR_TME2):
- state = CAN_TXSTATE_OK;
- break;
- default:
- state = CAN_TXSTATE_FAILED;
- break;
- }
- return (uint8_t) state;
-}
-
-/**
- * @brief Stop a transmit mission.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
- * @retval None.
- */
-void CAN_StopTransmit(CAN_TypeDef *CANx, uint8_t Mailbox)
-{
- /* Stop transmission */
- switch (Mailbox) {
- case (CAN_TXMAILBOX_0):
- CANx->TSTR |= CAN_TSTR_MST0;
- break;
- case (CAN_TXMAILBOX_1):
- CANx->TSTR |= CAN_TSTR_MST1;
- break;
- case (CAN_TXMAILBOX_2):
- CANx->TSTR |= CAN_TSTR_MST2;
- break;
- default:
- break;
- }
-}
-
-
-/**
- * @brief Receive a message.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: a structure receive message which contains
- * CAN Id, CAN DLC, CAN datas and FI number.
- * @retval None.
- */
-void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMessage *RxMessage)
-{
- /* Get the frame identifier */
- RxMessage->FF = (uint8_t)0x04 & CANx->FIFOMailBox[FIFONumber].RFMIR;
- if (RxMessage->FF == CAN_FF_STANDARD) {
- RxMessage->StdId = CAN_TMIR_StdId_Mask & (CANx->FIFOMailBox[FIFONumber].RFMIR >> 21);
- } else {
- RxMessage->ExtId = CAN_TMIR_ExtId_Mask & (CANx->FIFOMailBox[FIFONumber].RFMIR >> 3);
- }
-
- RxMessage->FT = (uint8_t)0x02 & CANx->FIFOMailBox[FIFONumber].RFMIR;
- /* Get the data length code */
- RxMessage->DLC = (uint8_t)0x0F & CANx->FIFOMailBox[FIFONumber].RFMPR;
- /* Get the filtering index */
- RxMessage->FI = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMPR >> 8);
- /* Get FIFO mailbox data */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->FIFOMailBox[FIFONumber].RFMD0R;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD0R >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD0R >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD0R >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->FIFOMailBox[FIFONumber].RFMD1R;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD1R >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD1R >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD1R >> 24);
- /* Release the FIFO */
- if (FIFONumber == CAN_FIFO0) {
- CANx->RFR0 |= CAN_RFR0_RFD0;
- }
-
- /* FIFONumber == CAN_FIFO1 */
- else {
- CANx->RFR1 |= CAN_RFR1_RFD1;
- }
-}
-
-/**
- * @brief Dequeue the FIFO.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param FIFONumber: FIFO to dequeue, it can be CAN_FIFO0 or CAN_FIFO1.
- * @retval None.
- */
-void CAN_FIFODequeue(CAN_TypeDef *CANx, uint8_t FIFONumber)
-{
-
- if (FIFONumber == CAN_FIFO0) {
- /* Release FIFO 0 */
- CANx->RFR0 |= CAN_RFR0_RFD0;
- } else { /* FIFONumber == CAN_FIFO1 */
- /* Release FIFO1 */
- CANx->RFR1 |= CAN_RFR1_RFD1;
- }
-}
-
-/**
- * @brief Return the length of receiving messages.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval message_length : which is the Length of pending message.
- */
-uint8_t CAN_MessageLength(CAN_TypeDef *CANx, uint8_t FIFONumber)
-{
- uint8_t message_length = 0;
- if (FIFONumber == CAN_FIFO0) {
- message_length = (uint8_t)(CANx->RFR0 & (uint32_t)0x03);
- } else if (FIFONumber == CAN_FIFO1) {
- message_length = (uint8_t)(CANx->RFR1 & (uint32_t)0x03);
- } else {
- message_length = 0;
- }
- return message_length;
-}
-
-
-/**
- * @brief Select the CAN Working mode.
- * @param CAN_WorkingMode : CAN Working Mode.It can be the following one.
- * @arg CAN_WORKINGMODE_INITIAL
- * @arg CAN_WORKINGMODE_NORMAL
- * @arg CAN_WORKINGMODE_SLEEP
- * @retval state of the requested mode which can be
- * @arg CAN_MODESTATE_FAILED
- * @arg CAN_MODESTATE_SUCCESS
- */
-uint8_t CAN_WorkingMode(CAN_TypeDef *CANx, uint8_t CAN_WorkingMode)
-{
- uint8_t state = CAN_MODESTATE_FAILED;
-
- /* Timeout for IWS or also for SWS bits*/
- uint32_t timeout = IWS_TIMEOUT;
-
- if (CAN_WorkingMode == CAN_WORKINGMODE_INITIAL) {
- /* Set initialisation */
- CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SWM)) | CAN_CTLR_IWM);
-
- /* Wait the acknowledge */
- while (((CANx->STR & CAN_MODE_MASK) != CAN_STR_IWS) && (timeout != 0)) {
- timeout--;
- }
- if ((CANx->STR & CAN_MODE_MASK) != CAN_STR_IWS) {
- state = CAN_MODESTATE_FAILED;
- } else {
- state = CAN_MODESTATE_SUCCESS;
- }
- } else if (CAN_WorkingMode == CAN_WORKINGMODE_NORMAL) {
- /* Enter Normal mode */
- CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SWM | CAN_CTLR_IWM));
-
- /* Wait the acknowledge */
- while (((CANx->STR & CAN_MODE_MASK) != 0) && (timeout != 0)) {
- timeout--;
- }
- if ((CANx->STR & CAN_MODE_MASK) != 0) {
- state = CAN_MODESTATE_FAILED;
- } else {
- state = CAN_MODESTATE_SUCCESS;
- }
- } else if (CAN_WorkingMode == CAN_WORKINGMODE_SLEEP) {
- /* Set Sleep mode */
- CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_IWM)) | CAN_CTLR_SWM);
-
- /* Wait the acknowledge */
- while (((CANx->STR & CAN_MODE_MASK) != CAN_STR_SWS) && (timeout != 0)) {
- timeout--;
- }
- if ((CANx->STR & CAN_MODE_MASK) != CAN_STR_SWS) {
- state = CAN_MODESTATE_FAILED;
- } else {
- state = CAN_MODESTATE_SUCCESS;
- }
- } else {
- state = CAN_MODESTATE_FAILED;
- }
-
- return (uint8_t) state;
-}
-
-/**
- * @brief Enter the Sleep mode.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @retval state: CAN_SLEEP_OK or CAN_SLEEP_FAILED.
- */
-uint8_t CAN_EnterSleep(CAN_TypeDef *CANx)
-{
- /* Set Sleep mode */
- CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_IWM)) | CAN_CTLR_SWM);
-
- if ((CANx->STR & (CAN_STR_SWS | CAN_STR_IWS)) == CAN_STR_SWS) {
- /* Sleep mode entered success*/
- return (uint8_t)CAN_SLEEP_OK;
- } else {
- /* Sleep mode entered failure */
- return (uint8_t)CAN_SLEEP_FAILED;
- }
-}
-
-/**
- * @brief Wake up CAN.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @retval status: CAN_WAKEUP_OK or CAN_WAKEUP_FAILED.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef *CANx)
-{
- uint32_t wait_sws = SWS_TIMEOUT;
-
- /*set wake up */
- CANx->CTLR &= ~(uint32_t)CAN_CTLR_SWM;
-
- /* Sleep mode state */
- while (((CANx->CTLR & CAN_CTLR_SWM) == CAN_CTLR_SWM) && (wait_sws != 0x00)) {
- wait_sws--;
- }
- if ((CANx->CTLR & CAN_CTLR_SWM) != CAN_CTLR_SWM) {
- /*Sleep mode exited */
- return (uint8_t)CAN_WAKEUP_OK;
- } else {
- /*Sleep mode exited failure */
- return (uint8_t)CAN_WAKEUP_FAILED;
- }
-}
-
-
-/**
- * @brief Return the CANx's last error type (LEC).
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @retval CAN_ErrorType: specify the Error type:
- * @arg CAN_ERRORTYPE_NOERR
- * @arg CAN_ERRORTYPE_STUFFERR
- * @arg CAN_ERRORTYPE_FORMERR
- * @arg CAN_ERRORTYPE_ACKERR
- * @arg CAN_ERRORTYPE_BITRECESSIVEERR
- * @arg CAN_ERRORTYPE_BITDOMINANTERR
- * @arg CAN_ERRORTYPE_CRCERR
- * @arg CAN_ERRORTYPE_SOFTWARESETERR
- */
-
-uint8_t CAN_GetErrorType(CAN_TypeDef *CANx)
-{
- uint8_t error_type = 0;
-
- /* Get the error type*/
- error_type = (((uint8_t)CANx->ER) & (uint8_t)CAN_ER_ET);
-
- /* Return the error type*/
- return error_type;
-}
-
-/**
- * @brief Get the Counter of CANx Receive Error(REC).
- * @note According to the error condition as defined by the CAN standard,
- * the counter of CANx Receive Error is increased by 1 or by 8.
- * When CAN received success everytime, the counter is decreased by 1
- * or reset to 120 if its value was over than 128.
- * When the counter value is over 127, the CAN controller enters the
- * error passive state.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @retval CAN Receive Error Counter.
- */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx)
-{
- uint8_t receive_counter = 0;
-
- /* Get the counter of CANx Receive Error*/
- receive_counter = (uint8_t)((CANx->ER & CAN_ER_REC) >> 24);
-
- /* Return the Receive Error Counter*/
- return receive_counter;
-}
-
-
-/**
- * @brief Get the Counter of CANx Transmit Error (TEC).
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @retval CAN Transmit Error Counter.
- */
-uint8_t CAN_GetTransmitErrorCounter(CAN_TypeDef *CANx)
-{
- uint8_t transmit_counter = 0;
-
- /* Get the Counter of CANx Transmit Error(TEC) */
- transmit_counter = (uint8_t)((CANx->ER & CAN_ER_TEC) >> 16);
-
- /* Return the Transmit Error Counter*/
- return transmit_counter;
-}
-
-
-/**
- * @brief Enable or disable the specified CANx interrupts.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param CAN_INT: specify the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg CAN_INT_TME
- * @arg CAN_INT_RFNE0
- * @arg CAN_INT_RFF0
- * @arg CAN_INT_RFO0
- * @arg CAN_INT_RFNE1
- * @arg CAN_INT_RFF1
- * @arg CAN_INT_RFO1
- * @arg CAN_INT_WE
- * @arg CAN_INT_PE
- * @arg CAN_INT_BOE
- * @arg CAN_INT_ET
- * @arg CAN_INT_ERR
- * @arg CAN_INT_WU
- * @arg CAN_INT_SLP
- * @param NewValue: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void CAN_INTConfig(CAN_TypeDef *CANx, uint32_t CAN_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable interrupt */
- CANx->IER |= CAN_INT;
- } else {
- /* Disable interrupt */
- CANx->IER &= ~CAN_INT;
- }
-}
-/**
- * @brief Check whether the specified CAN flag is set or not.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param CAN_FLAG: specify the flag to check.
- * This parameter can be one of the following flags:
- * @arg CAN_FLAG_WE: Warning error Flag
- * @arg CAN_FLAG_PE: Passive error Flag
- * @arg CAN_FLAG_BOE: Bus-off error Flag
- * @arg CAN_FLAG_MTF0: Mailbox 0 transmit finished Flag
- * @arg CAN_FLAG_MTF1: Mailbox 1 transmit finished Flag
- * @arg CAN_FLAG_MTF2: Mailbox 2 transmit finished Flag
- * @arg CAN_FLAG_RFL0: the length of the receive FIFO0 Flag
- * @arg CAN_FLAG_RFF0: Receive FIFO 0 full Flag
- * @arg CAN_FLAG_RFO0: Receive FIFO 0 overfull Flag
- * @arg CAN_FLAG_RFL1: the length of the receive FIFO1 Flag
- * @arg CAN_FLAG_RFF1: Receive FIFO 1 full Flag
- * @arg CAN_FLAG_RFO1: Receive FIFO 0 overfull Flag
- * @arg CAN_FLAG_WU: Wake up Flag
- * @arg CAN_FLAG_SLP: Sleep working state Flag
- * @arg CAN_FLAG_ET: Error type Flag
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-TypeState CAN_GetBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
-{
- if ((CAN_FLAG & CAN_FLAGS_ER) != (uint32_t)RESET) {
- /* Check the state of the specified CAN flag */
- if ((CANx->ER & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) {
- /* CAN_FLAG is set */
- return SET;
- } else {
- /* CAN_FLAG is reset */
- return RESET;
- }
- } else if ((CAN_FLAG & CAN_FLAGS_STR) != (uint32_t)RESET) {
- /* Check the state of the specified CAN flag */
- if ((CANx->STR & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) {
- /* CAN_FLAG is set */
- return SET;
- } else {
- /* CAN_FLAG is reset */
- return RESET;
- }
- } else if ((CAN_FLAG & CAN_FLAGS_TSTR) != (uint32_t)RESET) {
- /* Check the state of the specified CAN flag */
- if ((CANx->TSTR & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) {
- /* CAN_FLAG is set */
- return SET;
- } else {
- /* CAN_FLAG is reset */
- return RESET;
- }
- } else if ((CAN_FLAG & CAN_FLAGS_RFR0) != (uint32_t)RESET) {
- /* Check the state of the specified CAN flag */
- if ((CANx->RFR0 & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) {
- /* CAN_FLAG is set */
- return SET;
- } else {
- /* CAN_FLAG is reset */
- return RESET;
- }
- }
- /* If(CAN_FLAG & CAN_FLAGS_RFR1 != (uint32_t)RESET) */
- else {
- /* Check the state of the specified CAN flag */
- if ((uint32_t)(CANx->RFR1 & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) {
- /* CAN_FLAG is set */
- return SET;
- } else {
- /* CAN_FLAG is reset */
- return RESET;
- }
- }
-}
-
-/**
- * @brief Clear the CAN's flags.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param CAN_FLAG: specify the flag to clear.
- * This parameter can be one of the following flags:
- * @arg CAN_FLAG_MTF0: Mailbox 0 transmit finished Flag
- * @arg CAN_FLAG_MTF1: Mailbox 1 transmit finished Flag
- * @arg CAN_FLAG_MTF2: Mailbox 2 transmit finished Flag
- * @arg CAN_FLAG_RFF0: Receive FIFO 0 full Flag
- * @arg CAN_FLAG_RFO0: Receive FIFO 0 overfull Flag
- * @arg CAN_FLAG_RFF1: Receive FIFO 1 full Flag
- * @arg CAN_FLAG_RFO1: Receive FIFO 0 overfull Flag
- * @arg CAN_FLAG_WU: Wake up Flag
- * @arg CAN_FLAG_SLP: Sleep working state Flag
- * @arg CAN_FLAG_ET: Error type Flag
- * @retval None.
- */
-void CAN_ClearBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
-{
- uint32_t temp = 0;
-
- /* ER register */
- if (CAN_FLAG == CAN_FLAG_ET) {
- /* Clear the selected CAN flags */
- CANx->ER = (uint32_t)RESET;
- }
- /* STR or TSTR or RFR0 or RFR1 */
- else {
- temp = CAN_FLAG & CAN_FLAG_Mask;
-
- if ((CAN_FLAG & CAN_FLAGS_RFR0) != (uint32_t)RESET) {
- /* Receive Flags */
- CANx->RFR0 = (uint32_t)(temp);
- } else if ((CAN_FLAG & CAN_FLAGS_RFR1) != (uint32_t)RESET) {
- /* Receive Flags */
- CANx->RFR1 = (uint32_t)(temp);
- } else if ((CAN_FLAG & CAN_FLAGS_TSTR) != (uint32_t)RESET) {
- /* Transmit Flags */
- CANx->TSTR = (uint32_t)(temp);
- }
- /* If((CAN_FLAG & CAN_FLAGS_STR)!=(uint32_t)RESET) */
- else {
- CANx->STR = (uint32_t)(temp);
- }
- }
-}
-
-/**
- * @brief Check whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param CAN_INT: specify the CAN interrupt source to check.
- * This parameter can be:
- * @arg CAN_INT_TME
- * @arg CAN_INT_RFNE0
- * @arg CAN_INT_RFF0
- * @arg CAN_INT_RFO0
- * @arg CAN_INT_RFNE1
- * @arg CAN_INT_RFF1
- * @arg CAN_INT_RFO1
- * @arg CAN_INT_WE
- * @arg CAN_INT_PE
- * @arg CAN_INT_BOE
- * @arg CAN_INT_ET
- * @arg CAN_INT_ERR
- * @arg CAN_INT_WU
- * @arg CAN_INT_SLP
- * @retval The current state of CAN_INT (SET or RESET).
- */
-TypeState CAN_GetIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT)
-{
- TypeState intstate = RESET;
-
- /* Get the enable interrupt bit */
- if ((CANx->IER & CAN_INT) != RESET) {
- switch (CAN_INT) {
- case CAN_INT_TME:
- /* Check CAN_TSTR_MTFx bits */
- intstate = CheckINTState(CANx->TSTR, CAN_TSTR_MTF0 | CAN_TSTR_MTF1 | CAN_TSTR_MTF2);
- break;
- case CAN_INT_RFNE0:
- /* Check CAN_RFR0_RFL0 bit */
- intstate = CheckINTState(CANx->RFR0, CAN_RFR0_RFL0);
- break;
- case CAN_INT_RFF0:
- /* Check CAN_RFR0_RFF0 bit */
- intstate = CheckINTState(CANx->RFR0, CAN_RFR0_RFF0);
- break;
- case CAN_INT_RFO0:
- /* Check CAN_RFR0_RFO0 bit */
- intstate = CheckINTState(CANx->RFR0, CAN_RFR0_RFO0);
- break;
- case CAN_INT_RFNE1:
- /* Check CAN_RFR1_RFL1 bit */
- intstate = CheckINTState(CANx->RFR1, CAN_RFR1_RFL1);
- break;
- case CAN_INT_RFF1:
- /* Check CAN_RFR1_RFF1 bit */
- intstate = CheckINTState(CANx->RFR1, CAN_RFR1_RFF1);
- break;
- case CAN_INT_RFO1:
- /* Check CAN_RFR1_RFO1 bit */
- intstate = CheckINTState(CANx->RFR1, CAN_RFR1_RFO1);
- break;
- case CAN_INT_WU:
- /* Check CAN_STR_WIF bit */
- intstate = CheckINTState(CANx->STR, CAN_STR_WIF);
- break;
- case CAN_INT_SLP:
- /* Check CAN_STR_SEIF bit */
- intstate = CheckINTState(CANx->STR, CAN_STR_SEIF);
- break;
- case CAN_INT_WE:
- /* Check CAN_INT_WE bit */
- intstate = CheckINTState(CANx->ER, CAN_ER_WE);
- break;
- case CAN_INT_PE:
- /* Check CAN_INT_EP bit */
- intstate = CheckINTState(CANx->ER, CAN_ER_PE);
- break;
- case CAN_INT_BOE:
- /* Check CAN_ER_BOE bit */
- intstate = CheckINTState(CANx->ER, CAN_ER_BOE);
- break;
- case CAN_INT_ET:
- /* Check CAN_ER_ET bit */
- intstate = CheckINTState(CANx->ER, CAN_ER_ET);
- break;
- case CAN_INT_ERR:
- /* Check CAN_STR_EIF bit */
- intstate = CheckINTState(CANx->STR, CAN_STR_EIF);
- break;
- default :
- /* in case of error, return RESET */
- intstate = RESET;
- break;
- }
- } else {
- /* in case the Interrupt is not enabled, return RESET */
- intstate = RESET;
- }
-
- /* Return the CAN_INT status */
- return intstate;
-}
-
-/**
- * @brief Clear the CANx's interrupt pending bits.
- * @param CANx: where x:[1,2] to to select the CAN peripheral.
- * @param CAN_INT: specify the interrupt pending bit to clear.
- * This parameter can be:
- * @arg CAN_INT_TME
- * @arg CAN_INT_RFF0
- * @arg CAN_INT_RFO0
- * @arg CAN_INT_RFF1
- * @arg CAN_INT_RFO1
- * @arg CAN_INT_WE
- * @arg CAN_INT_PE
- * @arg CAN_INT_BOE
- * @arg CAN_INT_ET
- * @arg CAN_INT_ERR
- * @arg CAN_INT_WU
- * @arg CAN_INT_SLP
- * @retval None.
- */
-void CAN_ClearIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT)
-{
- switch (CAN_INT) {
- case CAN_INT_TME:
- /* Clear CAN_TSTR_MTFx (rc_w1)*/
- CANx->TSTR = CAN_TSTR_MTF0 | CAN_TSTR_MTF1 | CAN_TSTR_MTF2;
- break;
- case CAN_INT_RFF0:
- /* Clear CAN_RFR0_RFF0 (rc_w1)*/
- CANx->RFR0 = CAN_RFR0_RFF0;
- break;
- case CAN_INT_RFO0:
- /* Clear CAN_RFR0_RFO0 (rc_w1)*/
- CANx->RFR0 = CAN_RFR0_RFO0;
- break;
- case CAN_INT_RFF1:
- /* Clear CAN_RFR1_RFF1 (rc_w1)*/
- CANx->RFR1 = CAN_RFR1_RFF1;
- break;
- case CAN_INT_RFO1:
- /* Clear CAN_RFR1_RFO1 (rc_w1)*/
- CANx->RFR1 = CAN_RFR1_RFO1;
- break;
- case CAN_INT_WU:
- /* Clear CAN_STR_WIF (rc_w1)*/
- CANx->STR = CAN_STR_WIF;
- break;
- case CAN_INT_SLP:
- /* Clear CAN_STR_SEIF (rc_w1)*/
- CANx->STR = CAN_STR_SEIF;
- break;
- case CAN_INT_WE:
- /* Clear CAN_STR_EIF (rc_w1) */
- CANx->STR = CAN_STR_EIF;
- break;
- case CAN_INT_PE:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->STR = CAN_STR_EIF;
- break;
- case CAN_INT_BOE:
- /* Clear CAN_STR_EIF (rc_w1) */
- CANx->STR = CAN_STR_EIF;
- break;
- case CAN_INT_ET:
- /* Clear ET bits */
- CANx->ER = RESET;
- /* Clear CAN_STR_EIF (rc_w1) */
- CANx->STR = CAN_STR_EIF;
- break;
- case CAN_INT_ERR:
- /*Clear ET bits */
- CANx->ER = RESET;
- /* Clear CAN_STR_EIF (rc_w1) */
- CANx->STR = CAN_STR_EIF;
- break;
- default :
- break;
- }
-}
-
-/**
- * @brief Check whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: the register of CAN interrupt to check.
- * @param Int_Bit: the bit of interrupt source to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static TypeState CheckINTState(uint32_t CAN_Reg, uint32_t Int_Bit)
-{
- if ((CAN_Reg & Int_Bit) != (uint32_t)RESET) {
- /* CAN_INT is set */
- return SET;
- } else {
- /* CAN_IT is reset */
- return RESET;
- }
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c
deleted file mode 100644
index e081db43d0..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- ******************************************************************************
- * @brief CRC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_crc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset CRC DTR register to the value of 0xFFFFFFFF.
- * @param None
- * @retval None
- */
-void CRC_ResetDTR(void)
-{
- CRC->CTLR = CRC_CTLR_RESET;
-}
-
-/**
- * @brief Compute the 32-bit CRC value of a 32-bit data.
- * @param CRC_data: data to compute its CRC value
- * @retval 32-bit CRC value
- */
-uint32_t CRC_CalcSingleData(uint32_t CRC_data)
-{
- CRC->DTR = CRC_data;
-
- return (CRC->DTR);
-}
-
-/**
- * @brief Compute the 32-bit CRC value of a 32-bit data array.
- * @param pbuffer[]: pointer to the data array
- * @param buffer_length: length of the data array
- * @retval 32-bit CRC value
- */
-uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length)
-{
- uint32_t index = 0;
-
- for (index = 0; index < buffer_length; index++) {
- CRC->DTR = pbuffer[index];
- }
- return (CRC->DTR);
-}
-
-/**
- * @brief Read current CRC value.
- * @param None
- * @retval 32-bit CRC value
- */
-uint32_t CRC_ReadDTR(void)
-{
- return (CRC->DTR);
-}
-
-/**
- * @brief Write an 8-bit data in FDTR.
- * @param CRC_fdtr: 8-bit data to write
- * @retval None
- */
-void CRC_WriteFDTR(uint8_t CRC_fdtr)
-{
- CRC->FDTR = CRC_fdtr;
-}
-
-/**
- * @brief Read the 8-bit data stored in FDTR
- * @param None
- * @retval 8-bit data
- */
-uint8_t CRC_ReadFDTR(void)
-{
- return (CRC->FDTR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dac.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dac.c
deleted file mode 100644
index d50c031de6..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dac.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/**
- ******************************************************************************
- * @brief DAC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_dac.h"
-#include "gd32f10x_rcc.h"
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup DAC
- * @brief DAC driver modules
- * @{
- */
-
-/** @defgroup DAC_Private_Defines
- * @{
- */
-/* CTLR register bits mask */
-#define CTLR_BITS_CLEAR ((uint32_t)0x00000FFE)
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
-/* DHR registers offsets */
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)
-/* DOR register offset */
-#define DOR_OFFSET ((uint32_t)0x0000002C)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitialize the DAC peripheral registers.
- * @param DAC_InitParaStruct: DAC_InitPara structure that contains the
- * configuration information for the selected DAC channel.
- * @retval None
- */
-void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct)
-{
- /* Enable DAC reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, ENABLE);
- /* Release DAC from reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, DISABLE);
- /* Initialize the DAC_Trigger */
- DAC_InitParaStruct->DAC_Trigger = DAC_TRIGGER_NONE;
- /* Initialize the DAC_WaveGeneration */
- DAC_InitParaStruct->DAC_WaveType = DAC_WAVEGENE_NONE;
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude */
- DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle = DAC_LFSR_BIT0;
- /* Initialize the DAC_OutputBuffer */
- DAC_InitParaStruct->DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-}
-
-/**
- * @brief Initialize the DAC peripheral.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: select DAC Channel1
- * @arg DAC_Channel_2: select DAC Channel2
- * @param DAC_InitStruct: DAC_InitTypeDef structure .
- * @retval None
- */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct)
-{
- uint32_t temp1 = 0, temp2 = 0;
-
- /* DAC CTLR Configuration */
- /* Get the DAC CTLR value */
- temp1 = DAC->CTLR;
-
- /* Clear BOFF, TEN, TSEL, WAVE and MAMP bits */
- temp1 &= ~(CTLR_BITS_CLEAR << DAC_Channel);
-
- /* Configure for the DAC channel: buffer output, trigger, wave generation,
- mask/amplitude for wave generation */
- /* Set TSEL and TEN bits according to DAC_Trigger */
- /* Set WAVE bits according to DAC_WaveType */
- /* Set MAMP bits according to DAC_LFSRNoise_AmplitudeTriangle */
- /* Set BOFF bit according to DAC_OutputBuffer */
- temp2 = (DAC_InitParaStruct->DAC_Trigger | DAC_InitParaStruct->DAC_OutputBuffer |
- DAC_InitParaStruct->DAC_WaveType | DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle);
- /* Calculate CTLR register value */
- temp1 |= temp2 << DAC_Channel;
-
- /* Write to DAC CTLR */
- DAC->CTLR = temp1;
-}
-
-/**
- * @brief Enable or disable the DAC channel.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: select DAC Channel1.
- * @arg DAC_Channel_2: select DAC Channel2.
- * @param NewValue: New value of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the selected DAC channel */
- DAC->CTLR |= (DAC_CTLR_DEN1 << DAC_Channel) ;
- } else {
- /* Disable the selected DAC channel */
- DAC->CTLR &= ~(DAC_CTLR_DEN1 << DAC_Channel);
- }
-}
-
-/**
- * @brief Enable or disable the selected DAC channel software trigger.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: select DAC Channel1
- * @arg DAC_Channel_2: select DAC Channel2
- * @param NewValue: New value of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable software trigger for DAC channel1 */
- DAC->SWTR |= (uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4);
- } else {
- /* Disable software trigger for DAC channel1 */
- DAC->SWTR &= ~((uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enable or disable simultaneously the two DAC channels software
- * triggers.
- * @param NewValue: new value of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTrigger_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable software trigger */
- DAC->SWTR |= DUAL_SWTRIG_SET ;
- } else {
- /* Disable software trigger */
- DAC->SWTR &= ~DUAL_SWTRIG_SET;
- }
-}
-
-/**
- * @brief Enable or disable the selected DAC channel wave generation.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: select DAC Channel1
- * @arg DAC_Channel_2: select DAC Channel2
- * @param DAC_Wave: the wave type to enable or disable.
- * This parameter can be one of the following values:
- * @arg DAC_WAVE_NOISE: noise wave generation
- * @arg DAC_WAVE_TRIANGLE: triangle wave generation
- * @param NewValue: new value of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the selected DAC channel wave generation */
- DAC->CTLR |= DAC_Wave << DAC_Channel;
- } else {
- /* Disable the selected DAC channel wave generation */
- DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: the data alignment for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: select 8bit right data alignment
- * @arg DAC_ALIGN_12B_L: select 12bit left data alignment
- * @arg DAC_ALIGN_12B_R: select 12bit right data alignment
- * @param Data: Data to be loaded.
- * @retval None
- */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t temp = 0;
-
- temp = (uint32_t)DAC_BASE;
- temp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 */
- *(__IO uint32_t *) temp = Data;
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel2.
- * @param DAC_Align: the data alignment for DAC channel2.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: select 8bit right data alignment
- * @arg DAC_ALIGN_12B_L: select 12bit left data alignment
- * @arg DAC_ALIGN_12B_R: select 12bit right data alignment
- * @param Data: Data to be loaded.
- * @retval None
- */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t temp = 0;
-
- temp = (uint32_t)DAC_BASE;
- temp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 */
- *(__IO uint32_t *) temp = Data;
-}
-
-/**
- * @brief Set the specified data for dual channel
- * @param DAC_Align: the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: select 8bit right data alignment
- * @arg DAC_Align_12b_L: select 12bit left data alignment
- * @arg DAC_Align_12b_R: select 12bit right data alignment
- * @param Data2: Data for DAC Channel2.
- * @param Data1: Data for DAC Channel1.
- * @retval None
- */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, temp = 0;
-
- /* set dual DAC data holding register value */
- if (DAC_Align == DAC_ALIGN_8B_R) {
- data = ((uint32_t)Data2 << 8) | Data1;
- } else {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- temp = (uint32_t)DAC_BASE;
- temp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)temp = data;
-}
-
-/**
- * @brief Return the last data output value.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: select DAC Channel1
- * @arg DAC_Channel_2: select DAC Channel2
- * @retval The DAC channel1 data output value.
- */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
- __IO uint32_t temp = 0;
-
- temp = (uint32_t) DAC_BASE;
- temp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data */
- return (uint16_t)(*(__IO uint32_t *) temp);
-}
-
-/**
- * @brief Enable or disable DMA request.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: select DAC Channel1
- * @arg DAC_Channel_2: select DAC Channel2
- * @param NewValue: New value of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable DMA request */
- DAC->CTLR |= (DAC_CTLR_DDMAEN1 << DAC_Channel);
- } else {
- /* Disable DMA request */
- DAC->CTLR &= ~(DAC_CTLR_DDMAEN1 << DAC_Channel);
- }
-}
-
-/**
- * @brief Enable or disable the specified DAC interrupts.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param NewValue: Alternative state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_INTConfig(uint32_t DAC_Channel, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DAC DMAUDR interrupts */
- DAC->CTLR |= (DAC_INT_DMAUDR << DAC_Channel);
- } else {
- /* Disable the DAC DMAUDR interrupts */
- DAC->CTLR &= (~(uint32_t)(DAC_INT_DMAUDR << DAC_Channel));
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dma.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dma.c
deleted file mode 100644
index a519b30b9a..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dma.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/**
- ******************************************************************************
- * @brief DMA functions of the firmware library.
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_dma.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/** @defgroup DMA_Private_Defines
- * @{
- */
-
-/* DMA Reset registers mask */
-#define DMA_REGISTERS_RESET ((uint32_t)0x00000000)
-
-/* DMA Channel config registers Masks */
-#define CTLR_CLEAR_MASK ((uint32_t)0xFFFF800F)
-
-/* DMA Reset registers mask */
-#define DMA_INT_RESET ((uint32_t)0x00000000)
-
-/* DMA2 FLAG mask */
-#define DMA2_FLAG_Mask ((uint32_t)0x10000000)
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_Channel1_INT_Mask ((uint32_t)(DMA_IFR_GIF1 | DMA_IFR_TCIF1 | DMA_IFR_HTIF1 | DMA_IFR_ERRIF1))
-#define DMA1_Channel2_INT_Mask ((uint32_t)(DMA_IFR_GIF2 | DMA_IFR_TCIF2 | DMA_IFR_HTIF2 | DMA_IFR_ERRIF2))
-#define DMA1_Channel3_INT_Mask ((uint32_t)(DMA_IFR_GIF3 | DMA_IFR_TCIF3 | DMA_IFR_HTIF3 | DMA_IFR_ERRIF3))
-#define DMA1_Channel4_INT_Mask ((uint32_t)(DMA_IFR_GIF4 | DMA_IFR_TCIF4 | DMA_IFR_HTIF4 | DMA_IFR_ERRIF4))
-#define DMA1_Channel5_INT_Mask ((uint32_t)(DMA_IFR_GIF5 | DMA_IFR_TCIF5 | DMA_IFR_HTIF5 | DMA_IFR_ERRIF5))
-#define DMA1_Channel6_INT_Mask ((uint32_t)(DMA_IFR_GIF6 | DMA_IFR_TCIF6 | DMA_IFR_HTIF6 | DMA_IFR_ERRIF6))
-#define DMA1_Channel7_INT_Mask ((uint32_t)(DMA_IFR_GIF7 | DMA_IFR_TCIF7 | DMA_IFR_HTIF7 | DMA_IFR_ERRIF7))
-
-/* DMA2 Channelx interrupt pending bit masks */
-#define DMA2_Channel1_INT_Mask ((uint32_t)(DMA_IFR_GIF1 | DMA_IFR_TCIF1 | DMA_IFR_HTIF1 | DMA_IFR_ERRIF1))
-#define DMA2_Channel2_INT_Mask ((uint32_t)(DMA_IFR_GIF2 | DMA_IFR_TCIF2 | DMA_IFR_HTIF2 | DMA_IFR_ERRIF2))
-#define DMA2_Channel3_INT_Mask ((uint32_t)(DMA_IFR_GIF3 | DMA_IFR_TCIF3 | DMA_IFR_HTIF3 | DMA_IFR_ERRIF3))
-#define DMA2_Channel4_INT_Mask ((uint32_t)(DMA_IFR_GIF4 | DMA_IFR_TCIF4 | DMA_IFR_HTIF4 | DMA_IFR_ERRIF4))
-#define DMA2_Channel5_INT_Mask ((uint32_t)(DMA_IFR_GIF5 | DMA_IFR_TCIF5 | DMA_IFR_HTIF5 | DMA_IFR_ERRIF5))
-
-/**
- * @}
- */
-
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitialize the DMAy Channelx registers
- * @param DMAy_Channelx: where y:[1,2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel.
- * @retval None
- */
-void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
-{
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CTLR &= (uint16_t)(~DMA_CTLR_CHEN);
-
- /* Reset DMAy Channelx control register */
- DMAy_Channelx->CTLR = DMA_REGISTERS_RESET;
-
- /* Reset DMAy Channelx remaining bytes register */
- DMAy_Channelx->RCNT = DMA_REGISTERS_RESET;
-
- /* Reset DMAy Channelx peripheral address register */
- DMAy_Channelx->PBAR = DMA_REGISTERS_RESET;
-
- /* Reset DMAy Channelx memory address register */
- DMAy_Channelx->MBAR = DMA_REGISTERS_RESET;
-
- if (DMAy_Channelx == DMA1_CHANNEL1) {
- /* Reset interrupt pending bits for DMA1 Channel1 */
- DMA1->ICR |= DMA1_Channel1_INT_Mask;
- } else if (DMAy_Channelx == DMA1_CHANNEL2) {
- /* Reset interrupt pending bits for DMA1 Channel2 */
- DMA1->ICR |= DMA1_Channel2_INT_Mask;
- } else if (DMAy_Channelx == DMA1_CHANNEL3) {
- /* Reset interrupt pending bits for DMA1 Channel3 */
- DMA1->ICR |= DMA1_Channel3_INT_Mask;
- } else if (DMAy_Channelx == DMA1_CHANNEL4) {
- /* Reset interrupt pending bits for DMA1 Channel4 */
- DMA1->ICR |= DMA1_Channel4_INT_Mask;
- } else if (DMAy_Channelx == DMA1_CHANNEL5) {
- /* Reset interrupt pending bits for DMA1 Channel5 */
- DMA1->ICR |= DMA1_Channel5_INT_Mask;
- } else if (DMAy_Channelx == DMA1_CHANNEL6) {
- /* Reset interrupt pending bits for DMA1 Channel6 */
- DMA1->ICR |= DMA1_Channel6_INT_Mask;
- } else if (DMAy_Channelx == DMA1_CHANNEL7) {
- /* Reset interrupt pending bits for DMA1 Channel7 */
- DMA1->ICR |= DMA1_Channel7_INT_Mask;
- } else if (DMAy_Channelx == DMA2_CHANNEL1) {
- /* Reset interrupt pending bits for DMA2 Channel1 */
- DMA2->ICR |= DMA2_Channel1_INT_Mask;
- } else if (DMAy_Channelx == DMA2_CHANNEL2) {
- /* Reset interrupt pending bits for DMA2 Channel2 */
- DMA2->ICR |= DMA2_Channel2_INT_Mask;
- } else if (DMAy_Channelx == DMA2_CHANNEL3) {
- /* Reset interrupt pending bits for DMA2 Channel3 */
- DMA2->ICR |= DMA2_Channel3_INT_Mask;
- } else if (DMAy_Channelx == DMA2_CHANNEL4) {
- /* Reset interrupt pending bits for DMA2 Channel4 */
- DMA2->ICR |= DMA2_Channel4_INT_Mask;
- } else {
- if (DMAy_Channelx == DMA2_CHANNEL5) {
- /* Reset interrupt pending bits for DMA2 Channel5 */
- DMA2->ICR |= DMA2_Channel5_INT_Mask;
- }
- }
-}
-
-
-/**
- * @brief Initialize the DMAy Channelx according to the DMA_InitParaStruct.
- * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel.
- * @param DMA_InitParaStruct: contain the configuration information for the specified DMA Channel.
- * @retval None
- */
-void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitPara *DMA_InitParaStruct)
-{
- uint32_t temp = 0;
-
- /* Get the DMAy_Channelx CCR value */
- temp = DMAy_Channelx->CTLR;
-
- /* Clear MEMTOMEM, PRIO, MSIZE, PSIZE, MNAGA, PNAGA, CIRC and DIR bits */
- temp &= CTLR_CLEAR_MASK;
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
- /* Set MEMTOMEM, PRIO, MSIZE, PSIZE, MNAGA, PNAGA, CIRC and DIR bits according to DMA_InitParaStruct */
- temp |= DMA_InitParaStruct->DMA_DIR | DMA_InitParaStruct->DMA_Mode |
- DMA_InitParaStruct->DMA_PeripheralInc | DMA_InitParaStruct->DMA_MemoryInc |
- DMA_InitParaStruct->DMA_PeripheralDataSize | DMA_InitParaStruct->DMA_MemoryDataSize |
- DMA_InitParaStruct->DMA_Priority | DMA_InitParaStruct->DMA_MTOM;
-
- /* Write to DMAy Channelx CTLR */
- DMAy_Channelx->CTLR = temp;
-
- /* Write to DMAy Channelx RCNT */
- DMAy_Channelx->RCNT = DMA_InitParaStruct->DMA_BufferSize;
-
- /* Write to DMAy Channelx PBAR */
- DMAy_Channelx->PBAR = DMA_InitParaStruct->DMA_PeripheralBaseAddr;
-
- /* Write to DMAy Channelx MBAR */
- DMAy_Channelx->MBAR = DMA_InitParaStruct->DMA_MemoryBaseAddr;
-}
-
-/**
- * @brief Set each DMA_InitParaStruct member to its default value.
- * @param DMA_InitParaStruct: The structure pointer to DMA_InitParaStruct will be initialized.
- * @retval None
- */
-void DMA_ParaInit(DMA_InitPara *DMA_InitParaStruct)
-{
- /* Reset DMA init structure parameters values */
- DMA_InitParaStruct->DMA_PeripheralBaseAddr = DMA_INT_RESET;
-
- DMA_InitParaStruct->DMA_MemoryBaseAddr = DMA_INT_RESET;
-
- DMA_InitParaStruct->DMA_DIR = DMA_DIR_PERIPHERALSRC;
-
- DMA_InitParaStruct->DMA_BufferSize = DMA_INT_RESET;
-
- DMA_InitParaStruct->DMA_PeripheralInc = DMA_PERIPHERALINC_DISABLE;
-
- DMA_InitParaStruct->DMA_MemoryInc = DMA_MEMORYINC_DISABLE;
-
- DMA_InitParaStruct->DMA_PeripheralDataSize = DMA_PERIPHERALDATASIZE_BYTE;
-
- DMA_InitParaStruct->DMA_MemoryDataSize = DMA_MEMORYDATASIZE_BYTE;
-
- DMA_InitParaStruct->DMA_Mode = DMA_MODE_NORMAL;
-
- DMA_InitParaStruct->DMA_Priority = DMA_PRIORITY_LOW;
-
- DMA_InitParaStruct->DMA_MTOM = DMA_MEMTOMEM_DISABLE;
-}
-
-/**
- * @brief Enable or disable the DMAy Channelx.
- * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel.
- * @param NewValue: new state of the DMAy Channelx.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_Enable(DMA_Channel_TypeDef *DMAy_Channelx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMAy Channelx */
- DMAy_Channelx->CTLR |= DMA_CTLR_CHEN;
- } else {
- /* Disable the DMAy Channelx */
- DMAy_Channelx->CTLR &= (uint16_t)(~DMA_CTLR_CHEN);
- }
-}
-
-/**
- * @brief Enable or disable the DMAy Channelx interrupts.
- * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel.
- * @param DMA_INT: specify the DMA interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_INT_TC: Transfer complete interrupt mask
- * @arg DMA_INT_HT: Half transfer interrupt mask
- * @arg DMA_INT_ERR: Transfer error interrupt mask
- * @param NewValue: new state of the DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_INTConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMA interrupts */
- DMAy_Channelx->CTLR |= DMA_INT;
- } else {
- /* Disable the DMA interrupts */
- DMAy_Channelx->CTLR &= ~DMA_INT;
- }
-}
-
-/**
- * @brief Set the number of the remaining counter in the current DMAy Channelx transfer.
- * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel.
- * @param DataNumber: The number of the remaining counter in the current DMAy Channelx transfer.
- * @retval None.
- */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
-{
- /* Write to DMAy Channelx RCNT */
- DMAy_Channelx->RCNT = DataNumber;
-}
-
-/**
- * @brief Return the number of remaining counter in the current DMAy Channelx transfer.
- * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel.
- * @retval The number of remaining counter in the current DMAy Channelx transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
-{
- /* Return the number of remaining counter for DMAy Channelx */
- return ((uint16_t)(DMAy_Channelx->RCNT));
-}
-
-/**
- * @brief Check whether the DMAy Channelx flag is set or not.
- * @param DMAy_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- * @retval The new state of DMAy_FLAG (SET or RESET).
- */
-TypeState DMA_GetBitState(uint32_t DMAy_FLAG)
-{
- uint32_t temp = 0;
-
- /* Check the used DMAy */
- if ((DMAy_FLAG & DMA2_FLAG_Mask) != (uint32_t)RESET) {
- /* Get DMA2 ISR register value */
- temp = DMA2->IFR ;
- } else {
- /* Get DMA1 ISR register value */
- temp = DMA1->IFR ;
- }
-
- /* Check the status of the DMAy flag */
- if ((temp & DMAy_FLAG) != (uint32_t)RESET) {
- /* DMAy_FLAG is set */
- return SET;
- } else {
- /* DMAy_FLAG is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the DMAy Channelx's bit flags.
- * @param DMAy_FLAG: specifies the flag to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
- * @retval None
- */
-void DMA_ClearBitState(uint32_t DMAy_FLAG)
-{
- /* Check the used DMAy */
- if ((DMAy_FLAG & DMA2_FLAG_Mask) != (uint32_t)RESET) {
- /* Clear the selected DMAy flags */
- DMA2->ICR = DMAy_FLAG;
- } else {
- /* Clear the selected DMAy flags */
- DMA1->ICR = DMAy_FLAG;
- }
-}
-
-/**
- * @brief Check whether the DMAy Channelx interrupt has occurred or not.
- * @param DMAy_INT: specify the DMAy interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_INT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_INT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_INT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_INT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_INT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt.
- * @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt.
- * @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt.
- * @arg DMA1_INT_TE6: DMA1 Channel6 transfer error interrupt.
- * @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt.
- * @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt.
- * @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt.
- * @arg DMA1_INT_TE7: DMA1 Channel7 transfer error interrupt.
- * @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt.
- * @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt.
- * @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt.
- * @arg DMA2_INT_TE1: DMA2 Channel1 transfer error interrupt.
- * @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt.
- * @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt.
- * @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt.
- * @arg DMA2_INT_TE2: DMA2 Channel2 transfer error interrupt.
- * @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt.
- * @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt.
- * @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt.
- * @arg DMA2_INT_TE3: DMA2 Channel3 transfer error interrupt.
- * @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt.
- * @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt.
- * @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt.
- * @arg DMA2_INT_TE4: DMA2 Channel4 transfer error interrupt.
- * @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt.
- * @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt.
- * @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt.
- * @arg DMA2_INT_TE5: DMA2 Channel5 transfer error interrupt.
- * @retval The new state of DMAy_IT (SET or RESET).
- */
-TypeState DMA_GetIntBitState(uint32_t DMAy_INT)
-{
- uint32_t temp = 0;
-
- /* Calculate the used DMA */
- if ((DMAy_INT & DMA2_FLAG_Mask) != (uint32_t)RESET) {
- /* Get DMA2 IFR register value */
- temp = DMA2->IFR;
- } else {
- /* Get DMA1 IFR register value */
- temp = DMA1->IFR;
- }
-
- /* Check the status of the DMAy interrupt */
- if ((temp & DMAy_INT) != (uint32_t)RESET) {
- /* DMA_INT is set */
- return SET;
- } else {
- /* DMA_INT is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the DMAy Channelx's interrupt bits.
- * @param DMAy_INT: specify the DMAy interrupt pending bit to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_INT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_INT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_INT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_INT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_INT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt.
- * @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt.
- * @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt.
- * @arg DMA1_INT_TE6: DMA1 Channel6 transfer error interrupt.
- * @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt.
- * @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt.
- * @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt.
- * @arg DMA1_INT_TE7: DMA1 Channel7 transfer error interrupt.
- * @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt.
- * @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt.
- * @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt.
- * @arg DMA2_INT_TE1: DMA2 Channel1 transfer error interrupt.
- * @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt.
- * @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt.
- * @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt.
- * @arg DMA2_INT_TE2: DMA2 Channel2 transfer error interrupt.
- * @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt.
- * @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt.
- * @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt.
- * @arg DMA2_INT_TE3: DMA2 Channel3 transfer error interrupt.
- * @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt.
- * @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt.
- * @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt.
- * @arg DMA2_INT_TE4: DMA2 Channel4 transfer error interrupt.
- * @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt.
- * @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt.
- * @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt.
- * @arg DMA2_INT_TE5: DMA2 Channel5 transfer error interrupt.
- * @retval None
- */
-void DMA_ClearIntBitState(uint32_t DMAy_INT)
-{
-
- /* Check the used DMAy */
- if ((DMAy_INT & DMA2_FLAG_Mask) != (uint32_t)RESET) {
- /* Clear the DMA2 interrupt bits */
- DMA2->ICR = DMAy_INT;
- } else {
- /* Clear the DMA1 interrupt bits */
- DMA1->ICR = DMAy_INT;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_eth.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_eth.c
deleted file mode 100644
index fa83328d47..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_eth.c
+++ /dev/null
@@ -1,2587 +0,0 @@
-/**
- ******************************************************************************
- * @brief ETH header file of the firmware library.
- ******************************************************************************
- */
-#ifdef GD32F10X_CL
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_eth.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup ETH
- * @brief ETH driver modules
- * @{
- */
-
-/** @defgroup ETH_Private_Defines
- * @{
- */
-
-/* Global transmit and receive descriptors pointers */
-ETH_DMADESCTypeDef *DMACurrentTxDesc;
-ETH_DMADESCTypeDef *DMACurrentRxDesc;
-ETH_DMADESCTypeDef *DMACurrentPTPTxDesc;
-ETH_DMADESCTypeDef *DMACurrentPTPRxDesc;
-
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
-
-/* ETHERNET MAC_PHYAR register Mask */
-#define MAC_PHYAR_CLR_MASK ((uint32_t)0xFFFFFFE3)
-
-/* ETHERNET MAC_PHYAR register PHY address shift */
-#define MAC_PHYAR_PHYADDRSHIFT 11
-
-/* ETHERNET MAC_PHYAR register PHY register shift */
-#define MAC_PHYAR_PHYREGSHIFT 6
-
-/* ETHERNET MAC_CFR register Mask */
-#define MAC_CFR_CLEAR_MASK ((uint32_t)0xFF20810F)
-
-/* ETHERNET MAC_FCTLR register Mask */
-#define MAC_FCTLR_CLEAR_MASK ((uint32_t)0x0000FF41)
-
-/* ETHERNET DMA_CTLR register Mask */
-#define DMA_CTLR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8
-
-/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
-
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3
-
-/* ETHERNET DMA Tx descriptors size */
-#define ETH_DMATXDESC_SIZE 0x10
-
-/* ETHERNET DMA Rx descriptors size */
-#define ETH_DMARXDESC_SIZE 0x10
-
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
-
-/* ETHERNET errors */
-#define ERROR ((uint32_t)0)
-#define SUCCESS ((uint32_t)1)
-/**
- * @}
- */
-
-/** @defgroup ETH_Private_FunctionPrototypes
- * @{
- */
-
-#ifndef USE_Delay
- static void ETH_Delay(__IO uint32_t nCount);
-#endif /* USE_Delay*/
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the ETH registers.
- * @param None
- * @retval None
- */
-void ETH_DeInit(void)
-{
- RCC_AHBPeriphReset_Enable(RCC_AHBPERIPH_ETH_MAC, ENABLE);
- RCC_AHBPeriphReset_Enable(RCC_AHBPERIPH_ETH_MAC, DISABLE);
-}
-
-/**
- * @brief Initialize MDIO parameters.
- * @param None
- * @retval None
- */
-void ETH_MDIOInit(void)
-{
- uint32_t temp = 0;
- RCC_ClocksPara rcc_clocks;
- uint32_t hclk;
-
- /* ETHERNET MAC_PHYAR Configuration */
- /* Get the ETH_MAC_PHYAR value */
- temp = ETH_MAC->PHYAR;
- /* Clear Clock Range CLR[2:0] bits */
- temp &= MAC_PHYAR_CLR_MASK;
- /* Get hclk frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- hclk = rcc_clocks.AHB_Frequency;
- /* Set CLR bits depending on hclk value */
- if ((hclk >= 20000000) && (hclk < 35000000)) {
- /* Clock Range between 20-35 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV16;
- } else if ((hclk >= 35000000) && (hclk < 60000000)) {
- /* Clock Range between 35-60 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV26;
- } else if ((hclk >= 60000000) && (hclk < 90000000)) {
- /* Clock Range between 60-90 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV42;
- }
- /* ((hclk >= 90000000)&&(hclk <= 108000000)) */
- else {
- /* Clock Range between 90-108 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV64;
- }
- /* Write to ETHERNET MAC PHYAR */
- ETH_MAC->PHYAR = (uint32_t)temp;
-}
-
-/**
- * @brief Initial the ETH parameters.
- * @param ETH_InitParaStruct: The ETH_InitPara structure pointer.
- * @param PHYAddress: external PHY address
- * @retval The Initialize result(ERROR or SUCCESS)
- */
-uint32_t ETH_Init(ETH_InitPara *ETH_InitParaStruct, uint16_t PHYAddress)
-{
- uint32_t RegValue = 0, temp = 0;
- __IO uint32_t i = 0;
- RCC_ClocksPara rcc_clocks;
- uint32_t hclk;
- __IO uint32_t timeout = 0;
-
- /* MAC Config */
- /* ETH_MAC_PHYAR Configuration */
- /* Get the ETH_MAC_PHYAR value */
- temp = ETH_MAC->PHYAR;
- /* Clear Clock Range CLR[2:0] bits */
- temp &= MAC_PHYAR_CLR_MASK;
- /* Get hclk frequency value */
- RCC_GetClocksFreq(&rcc_clocks);
- hclk = rcc_clocks.AHB_Frequency;
- /* Set CLR bits depending on hclk value */
- if ((hclk >= 20000000) && (hclk < 35000000)) {
- /* Clock Range between 20-35 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV16;
- } else if ((hclk >= 35000000) && (hclk < 60000000)) {
- /* Clock Range between 35-60 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV26;
- } else if ((hclk >= 60000000) && (hclk < 90000000)) {
- /* Clock Range between 60-90 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV42;
- }
- /* ((hclk >= 90000000)&&(hclk <= 108000000)) */
- else {
- /* Clock Range between 90-108 MHz */
- temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV64;
- }
- ETH_MAC->PHYAR = (uint32_t)temp;
- /* PHY initialization and configuration */
- /* Set the PHY into reset mode */
- if (!(ETH_SetPHYRegisterValue(PHYAddress, PHY_BCR, PHY_RESET))) {
- /* Return ERROR due to write timeout */
- return ERROR;
- }
-
- /* PHY reset need some time */
- _eth_delay_(PHY_RESETDELAY);
-
- if (ETH_InitParaStruct->ETH_MAC_AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) {
- /* Wait for PHY_LINKED_STATUS bit be set */
- do {
- timeout++;
- } while (!(ETH_GetPHYRegisterValue(PHYAddress, PHY_BSR) & PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
- /* Return ERROR due to timeout */
- if (timeout == PHY_READ_TO) {
- return ERROR;
- }
- /* Reset Timeout counter */
- timeout = 0;
-
- /* Enable Auto-Negotiation */
- if (!(ETH_SetPHYRegisterValue(PHYAddress, PHY_BCR, PHY_AUTONEGOTIATION))) {
- /* Return ERROR due to write timeout */
- return ERROR;
- }
-
- /* Wait for the PHY_AUTONEGO_COMPLETE bit be set */
- do {
- timeout++;
- } while (!(ETH_GetPHYRegisterValue(PHYAddress, PHY_BSR) & PHY_AUTONEGO_COMPLETE) && (timeout < (uint32_t)PHY_READ_TO));
- /* Return ERROR due to timeout */
- if (timeout == PHY_READ_TO) {
- return ERROR;
- }
- /* Reset Timeout counter */
- timeout = 0;
-
- /* Read the result of the autonegotiation */
- RegValue = ETH_GetPHYRegisterValue(PHYAddress, PHY_SR);
-
- /* Configure the Duplex Mode of MAC following the autonegotiation result */
- if ((RegValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) {
- ETH_InitParaStruct->ETH_MAC_Mode = ETH_MODE_FULLDUPLEX;
-
- } else {
- ETH_InitParaStruct->ETH_MAC_Mode = ETH_MODE_HALFDUPLEX;
- }
- /* Configure the Communication speed of MAC following the autonegotiation result */
- if (RegValue & PHY_Speed_Status) {
- ETH_InitParaStruct->ETH_MAC_Speed = ETH_SPEEDMODE_10M;
- } else {
- ETH_InitParaStruct->ETH_MAC_Speed = ETH_SPEEDMODE_100M;
- }
- } else {
- if (!ETH_SetPHYRegisterValue(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitParaStruct->ETH_MAC_Mode >> 3) |
- (uint16_t)(ETH_InitParaStruct->ETH_MAC_Speed >> 1)))) {
- /* Return ERROR due to write timeout */
- return ERROR;
- }
- /* PHY configuration need some time */
- _eth_delay_(PHY_CONFIGDELAY);
- }
- /* ETH_MAC_CFR Configuration */
- /* Get the ETH_MAC_CFR value */
- temp = ETH_MAC->CFR;
- temp &= MAC_CFR_CLEAR_MASK;
- /* Set the WDD bit according to ETH_MAC_Watchdog value */
- /* Set the JBD: bit according to ETH_MAC_Jabber value */
- /* Set the IG bit according to ETH_MAC_InterFrameGap value */
- /* Set the CSD bit according to ETH_MAC_CarrierSense value */
- /* Set the SPD bit according to ETH_MAC_Speed value */
- /* Set the ROD bit according to ETH_MAC_ReceiveOwn value */
- /* Set the LBM bit according to ETH_MAC_LoopbackMode value */
- /* Set the DPM bit according to ETH_MAC_Mode value */
- /* Set the IP4CO bit according to ETH_MAC_ChecksumOffload value */
- /* Set the RTD bit according to ETH_MAC_RetryTransmission value */
- /* Set the APCD bit according to ETH_MAC_AutomaticPadCRCDrop value */
- /* Set the BOL bit according to ETH_MAC_BackOffLimit value */
- /* Set the DFC bit according to ETH_MAC_DeferralCheck value */
- temp |= (uint32_t)(ETH_InitParaStruct->ETH_MAC_Watchdog |
- ETH_InitParaStruct->ETH_MAC_Jabber |
- ETH_InitParaStruct->ETH_MAC_InterFrameGap |
- ETH_InitParaStruct->ETH_MAC_CarrierSense |
- ETH_InitParaStruct->ETH_MAC_Speed |
- ETH_InitParaStruct->ETH_MAC_ReceiveOwn |
- ETH_InitParaStruct->ETH_MAC_LoopbackMode |
- ETH_InitParaStruct->ETH_MAC_Mode |
- ETH_InitParaStruct->ETH_MAC_ChecksumOffload |
- ETH_InitParaStruct->ETH_MAC_RetryTransmission |
- ETH_InitParaStruct->ETH_MAC_AutomaticPadCRCDrop |
- ETH_InitParaStruct->ETH_MAC_BackOffLimit |
- ETH_InitParaStruct->ETH_MAC_DeferralCheck);
- /* Write to ETH_MAC_CFR */
- ETH_MAC->CFR = (uint32_t)temp;
-
- /* ETH_MAC_FRMFR Configuration */
- /* Set the FD bit according to ETH_MAC_FilterDisable value */
- /* Set the SAFLT and SAIFLT bits according to ETH_MAC_SourceAddrFilter value */
- /* Set the PCFRM bit according to ETH_MAC_PassControlFrames value */
- /* Set the DBF bit according to ETH_MAC_BroadcastFramesReception value */
- /* Set the DAIFLT bit according to ETH_MAC_DestinationAddrFilter value */
- /* Set the PM bit according to ETH_MAC_PromiscuousMode value */
- /* Set the PM, HMF and HPFLT bits according to ETH_MAC_MulticastFramesFilter value */
- /* Set the HUF and HPFLT bits according to ETH_MAC_UnicastFramesFilter value */
- /* Write to ETH_MAC_FRMFR */
- ETH_MAC->FRMFR = (uint32_t)(ETH_InitParaStruct->ETH_MAC_FilterDisable |
- ETH_InitParaStruct->ETH_MAC_SourceAddrFilter |
- ETH_InitParaStruct->ETH_MAC_PassControlFrames |
- ETH_InitParaStruct->ETH_MAC_BroadcastFramesReception |
- ETH_InitParaStruct->ETH_MAC_DestinationAddrFilter |
- ETH_InitParaStruct->ETH_MAC_PromiscuousMode |
- ETH_InitParaStruct->ETH_MAC_MulticastFramesFilter |
- ETH_InitParaStruct->ETH_MAC_UnicastFramesFilter);
- /* ETH_MAC_HLHR and MAC_HLLR Configuration */
- /* Write to ETHERNET MAC_HLHR */
- ETH_MAC->HLHR = (uint32_t)ETH_InitParaStruct->ETH_MAC_HashListHigh;
- /* Write to ETHERNET MAC_HLLR */
- ETH_MAC->HLLR = (uint32_t)ETH_InitParaStruct->ETH_MAC_HashListLow;
- /* ETH_MAC_FCTLR Configuration */
- /* Get the ETH_MAC_FCTLR value */
- temp = ETH_MAC->FCTLR;
- temp &= MAC_FCTLR_CLEAR_MASK;
-
- /* Set the PTM bit according to ETH_MAC_PauseTime value */
- /* Set the ZQPD bit according to ETH_MAC_ZeroQuantaPause value */
- /* Set the PLTS bit according to ETH_MAC_PauseLowThreshold value */
- /* Set the UPFDT bit according to ETH_MAC_UnicastPauseFrameDetect value */
- /* Set the RFCEN bit according to ETH_MAC_ReceiveFlowControl value */
- /* Set the TFCEN bit according to ETH_MAC_TransmitFlowControl value */
- temp |= (uint32_t)((ETH_InitParaStruct->ETH_MAC_PauseTime << 16) |
- ETH_InitParaStruct->ETH_MAC_ZeroQuantaPause |
- ETH_InitParaStruct->ETH_MAC_PauseLowThreshold |
- ETH_InitParaStruct->ETH_MAC_UnicastPauseFrameDetect |
- ETH_InitParaStruct->ETH_MAC_ReceiveFlowControl |
- ETH_InitParaStruct->ETH_MAC_TransmitFlowControl);
- /* Write to ETH_MAC_FCTLR */
- ETH_MAC->FCTLR = (uint32_t)temp;
- /* ETH_MAC_FCTHR Configuration */
- temp = ETH_MAC->FCTHR;
- temp |= (uint32_t)(ETH_InitParaStruct->ETH_MAC_FlowControlDeactiveThreshold |
- ETH_InitParaStruct->ETH_MAC_FlowControlActiveThreshold);
- ETH_MAC->FCTHR = (uint32_t)temp;
- /* ETH_MAC_VLTR Configuration */
- /* Set the VLTC bit according to ETH_MAC_VLANTagComparison value */
- /* Set the VLTI bit according to ETH_MAC_VLANTagIdentifier value */
- ETH_MAC->VLTR = (uint32_t)(ETH_InitParaStruct->ETH_MAC_VLANTagComparison |
- ETH_InitParaStruct->ETH_MAC_VLANTagIdentifier);
-
- /* DMA Config */
- /* ETH_DMA_CTLR Configuration */
- /* Get the ETHERNET DMA_CTLR value */
- temp = ETH_DMA->CTLR;
- temp &= DMA_CTLR_CLEAR_MASK;
-
- /* Set the DTCERFD bit according to ETH_DMA_DropTCPIPChecksumErrorFrame value */
- /* Set the RSFD bit according to ETH_DMA_ReceiveStoreForward value */
- /* Set the DAFRF bit according to ETH_DMA_FlushReceivedFrame value */
- /* Set the TSFD bit according to ETH_DMA_TransmitStoreForward value */
- /* Set the TTCH bit according to ETH_DMA_TransmitThresholdControl value */
- /* Set the FERF bit according to ETH_DMA_ForwardErrorFrames value */
- /* Set the FUF bit according to ETH_DMA_ForwardUndersizedGoodFrames value */
- /* Set the RTHC bit according to ETH_DMA_ReceiveThresholdControl value */
- /* Set the OSF bit according to ETH_DMA_SecondFrameOperate value */
- temp |= (uint32_t)(ETH_InitParaStruct->ETH_DMA_DropTCPIPChecksumErrorFrame |
- ETH_InitParaStruct->ETH_DMA_ReceiveStoreForward |
- ETH_InitParaStruct->ETH_DMA_FlushReceivedFrame |
- ETH_InitParaStruct->ETH_DMA_TransmitStoreForward |
- ETH_InitParaStruct->ETH_DMA_TransmitThresholdControl |
- ETH_InitParaStruct->ETH_DMA_ForwardErrorFrames |
- ETH_InitParaStruct->ETH_DMA_ForwardUndersizedGoodFrames |
- ETH_InitParaStruct->ETH_DMA_ReceiveThresholdControl |
- ETH_InitParaStruct->ETH_DMA_SecondFrameOperate);
- /* Write to ETH_DMA_CTLR */
- ETH_DMA->CTLR = (uint32_t)temp;
-
- /* ETH_DMA_BCR Configuration */
- /* Set the AA bit according to ETH_DMA_AddressAligned value */
- /* Set the FB bit according to ETH_DMA_FixedBurst value */
- /* Set the RXDP and 4*PBL bits according to ETH_DMA_RxDMABurstLength value */
- /* Set the FPBL and 4*PBL bits according to ETH_DMA_TxDMABurstLength value */
- /* Set the DPSL bit according to ETH_DesciptorSkipLength value */
- /* Set the RTPR and DAB bits according to ETH_DMA_Arbitration value */
- ETH_DMA->BCR = (uint32_t)(ETH_InitParaStruct->ETH_DMA_AddressAligned |
- ETH_InitParaStruct->ETH_DMA_FixedBurst |
- ETH_InitParaStruct->ETH_DMA_RxDMABurstLength | /* If 4xPBL is selected for Tx or Rx it is applied for the other */
- ETH_InitParaStruct->ETH_DMA_TxDMABurstLength |
- (ETH_InitParaStruct->ETH_DMA_DescriptorSkipLength << 2) |
- ETH_InitParaStruct->ETH_DMA_Arbitration |
- ETH_DMA_BCR_UIP); /* Enable use of separate PBL for Rx and Tx */
- /* Return Ethernet configuration success */
- return SUCCESS;
-}
-
-/**
- * @brief Initial the sturct ETH_InitPara.
- * @param ETH_InitParaStruct: pointer to a ETH_InitPara structure.
- * @retval None
- */
-void ETH_ParaInit(ETH_InitPara *ETH_InitParaStruct)
-{
- /* Reset ETH init structure parameters values */
- /* MAC */
- ETH_InitParaStruct->ETH_MAC_AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
- ETH_InitParaStruct->ETH_MAC_Watchdog = ETH_WATCHDOG_ENABLE;
- ETH_InitParaStruct->ETH_MAC_Jabber = ETH_JABBER_ENABLE;
- ETH_InitParaStruct->ETH_MAC_InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
- ETH_InitParaStruct->ETH_MAC_CarrierSense = ETH_CARRIERSENSE_ENABLE;
- ETH_InitParaStruct->ETH_MAC_Speed = ETH_SPEEDMODE_10M;
- ETH_InitParaStruct->ETH_MAC_ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
- ETH_InitParaStruct->ETH_MAC_LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
- ETH_InitParaStruct->ETH_MAC_Mode = ETH_MODE_HALFDUPLEX;
- ETH_InitParaStruct->ETH_MAC_ChecksumOffload = ETH_CHECKSUMOFFLOAD_DISABLE;
- ETH_InitParaStruct->ETH_MAC_RetryTransmission = ETH_RETRYTRANSMISSION_ENABLE;
- ETH_InitParaStruct->ETH_MAC_AutomaticPadCRCDrop = ETH_AUTOMATICPADCRCDROP_DISABLE;
- ETH_InitParaStruct->ETH_MAC_BackOffLimit = ETH_BACKOFFLIMIT_10;
- ETH_InitParaStruct->ETH_MAC_DeferralCheck = ETH_DEFERRALCHECK_DISABLE;
- ETH_InitParaStruct->ETH_MAC_FilterDisable = ETH_FILTERDISABLE_DISABLE;
- ETH_InitParaStruct->ETH_MAC_SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
- ETH_InitParaStruct->ETH_MAC_PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
- ETH_InitParaStruct->ETH_MAC_BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_DISABLE;
- ETH_InitParaStruct->ETH_MAC_DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
- ETH_InitParaStruct->ETH_MAC_PromiscuousMode = ETH_PROMISCUOUSMODE_DISABLE;
- ETH_InitParaStruct->ETH_MAC_MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
- ETH_InitParaStruct->ETH_MAC_UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
- ETH_InitParaStruct->ETH_MAC_HashListHigh = 0x0;
- ETH_InitParaStruct->ETH_MAC_HashListLow = 0x0;
- ETH_InitParaStruct->ETH_MAC_PauseTime = 0x0;
- ETH_InitParaStruct->ETH_MAC_ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
- ETH_InitParaStruct->ETH_MAC_PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
- ETH_InitParaStruct->ETH_MAC_FlowControlDeactiveThreshold = ETH_RFD_512BYTES;
- ETH_InitParaStruct->ETH_MAC_FlowControlActiveThreshold = ETH_RFA_1536BYTES;
- ETH_InitParaStruct->ETH_MAC_UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
- ETH_InitParaStruct->ETH_MAC_ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
- ETH_InitParaStruct->ETH_MAC_TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
- ETH_InitParaStruct->ETH_MAC_VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
- ETH_InitParaStruct->ETH_MAC_VLANTagIdentifier = 0x0;
- /* DMA */
- ETH_InitParaStruct->ETH_DMA_DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE;
- ETH_InitParaStruct->ETH_DMA_ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
- ETH_InitParaStruct->ETH_DMA_FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_DISABLE;
- ETH_InitParaStruct->ETH_DMA_TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
- ETH_InitParaStruct->ETH_DMA_TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
- ETH_InitParaStruct->ETH_DMA_ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
- ETH_InitParaStruct->ETH_DMA_ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
- ETH_InitParaStruct->ETH_DMA_ReceiveThresholdControl = ETH_RECEIVETHRESHOLDCONTROL_64BYTES;
- ETH_InitParaStruct->ETH_DMA_SecondFrameOperate = ETH_SECONDFRAMEOPERATE_DISABLE;
- ETH_InitParaStruct->ETH_DMA_AddressAligned = ETH_ADDRESSALIGNED_ENABLE;
- ETH_InitParaStruct->ETH_DMA_FixedBurst = ETH_FIXEDBURST_DISABLE;
- ETH_InitParaStruct->ETH_DMA_RxDMABurstLength = ETH_RXDMABURSTLENGTH_1BEAT;
- ETH_InitParaStruct->ETH_DMA_TxDMABurstLength = ETH_TXDMABURSTLENGTH_1BEAT;
- ETH_InitParaStruct->ETH_DMA_DescriptorSkipLength = 0x0;
- ETH_InitParaStruct->ETH_DMA_Arbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
-}
-
-/**
- * @brief Enable or disable the ETH's receive and transmit.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_Enable(TypeState NewValue)
-{
- /* Enable or Disable the ETH module */
- if (NewValue != DISABLE) {
- /* Enable MAC transmit */
- ETH_MACTransmission_Enable(ENABLE);
- /* Flush ETHERNET DMA Transmit FIFO */
- ETH_CleanTransmitFIFO();
- /* Enable MAC receive */
- ETH_MACReception_Enable(ENABLE);
-
- /* Enable DMA transmission */
- ETH_DMATransmission_Enable(ENABLE);
- /* Enable DMA reception */
- ETH_DMAReception_Enable(ENABLE);
- } else {
- /* Disable MAC transmit */
- ETH_MACTransmission_Enable(DISABLE);
- /* Flush ETHERNET DMA Transmit FIFO */
- ETH_CleanTransmitFIFO();
- /* Disable MAC receive */
- ETH_MACReception_Enable(DISABLE);
-
- /* Disable DMA transmission */
- ETH_DMATransmission_Enable(DISABLE);
- /* Disable DMA reception */
- ETH_DMAReception_Enable(DISABLE);
- }
-}
-
-/**
- * @brief Send data of application buffer as a transmit packet.
- * @param pbuf: Pointer to the application buffer.
- * @param size: the application buffer size.
- * @retval The transmission result(ERROR or SUCCESS)
- */
-uint32_t ETH_HandleTxPkt(uint8_t *pbuf, uint16_t size)
-{
- uint32_t offset = 0;
-
- /* Check the busy bit of Tx descriptor status */
- if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_BUSY) != (uint32_t)RESET) {
- /* Return ERROR: the descriptor is busy due to own by the DMA */
- return ERROR;
- }
-
- for (offset = 0; offset < size; offset++) {
- (*(__IO uint8_t *)((DMACurrentTxDesc->Buffer1Addr) + offset)) = (*(pbuf + offset));
- }
-
- /* Setting the Frame Length */
- DMACurrentTxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TB1S);
- /* Setting the segment of frame (ETH_DMATXDESC_LSG and ETH_DMATXDESC_FSG are SET that frame is transmitted in one descriptor) */
- DMACurrentTxDesc->Status |= ETH_DMATXDESC_LSG | ETH_DMATXDESC_FSG;
- /* Enable the DMA transmission */
- DMACurrentTxDesc->Status |= ETH_DMATXDESC_BUSY;
- /* Check Tx Buffer unavailable flag status */
- if ((ETH_DMA->STR & ETH_DMA_STR_TBU) != (uint32_t)RESET) {
- /* Clear TBU ETHERNET DMA flag */
- ETH_DMA->STR = ETH_DMA_STR_TBU;
- /* Resume DMA transmission by writing to the TPER register*/
- ETH_DMA->TPER = 0;
- }
-
- /* Update the ETHERNET DMA current Tx descriptor pointer to the next Tx decriptor in DMA Tx decriptor talbe*/
- /* Chained Mode */
- if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TCHM) != (uint32_t)RESET) {
- DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(DMACurrentTxDesc->Buffer2NextDescAddr);
- }
- /* Ring Mode */
- else {
- if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TERM) != (uint32_t)RESET) {
- DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->TDTAR);
- } else {
- DMACurrentTxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentTxDesc + ETH_DMATXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2));
- }
- }
- /* Return SUCCESS */
- return SUCCESS;
-}
-
-/**
- * @brief Receive a packet data to application buffer.
- * @param pbuf: Pointer on the application buffer.
- * @retval The Receive size(If framelength is equal to ERROR, the receiving unsuccessful)
- */
-uint32_t ETH_HandleRxPkt(uint8_t *pbuf)
-{
- uint32_t offset = 0, size = 0;
-
- /* Check the busy bit of Rx descriptor status */
- if ((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) != (uint32_t)RESET) {
- /* Return ERROR: the descriptor is busy due to own by the DMA */
- return ERROR;
- }
-
- if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) {
- /* Get the Frame Length exclusive CRC */
- size = ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FRML) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
- for (offset = 0; offset < size; offset++) {
- (*(pbuf + offset)) = (*(__IO uint8_t *)((DMACurrentRxDesc->Buffer1Addr) + offset));
- }
- } else {
- /* Return ERROR */
- size = ERROR;
- }
- /* Enable reception */
- DMACurrentRxDesc->Status = ETH_DMARXDESC_BUSY;
-
- /* Check Rx Buffer unavailable flag status */
- if ((ETH_DMA->STR & ETH_DMA_STR_RBU) != (uint32_t)RESET) {
- /* Clear RBU ETHERNET DMA flag */
- ETH_DMA->STR = ETH_DMA_STR_RBU;
- /* Resume DMA reception by writing to the RPER register*/
- ETH_DMA->RPER = 0;
- }
-
- /* Update the ETHERNET DMA current Rx descriptor pointer to the next Rx decriptor in DMA Rx decriptor talbe*/
- /* Chained Mode */
- if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RCHM) != (uint32_t)RESET) {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentRxDesc->Buffer2NextDescAddr);
- }
- /* Ring Mode */
- else {
- if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RERR) != (uint32_t)RESET) {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->RDTAR);
- } else {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentRxDesc + ETH_DMARXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2));
- }
- }
-
- /* Return Frame size or ERROR */
- return (size);
-}
-
-/**
- * @brief To obtain the received data length
- * @param None
- * @retval Received frame length.
- */
-uint32_t ETH_GetRxPktSize(void)
-{
- uint32_t size = 0;
-
- if ((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) != (uint32_t)RESET) {
- return 0;
- }
-
- if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) != (uint32_t)RESET) ||
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET) ||
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET)) {
- ETH_DropRxPkt();
-
- return 0;
- }
-
- if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) == (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) {
- /* Get the size of the received data including CRC */
- size = ETH_GetDMARxDescFrameLength(DMACurrentRxDesc);
- }
-
- /* Return Packet size */
- return size;
-}
-
-/**
- * @brief Discard a Received packet
- * @param None
- * @retval None
- */
-void ETH_DropRxPkt(void)
-{
- /* Enable reception */
- DMACurrentRxDesc->Status = ETH_DMARXDESC_BUSY;
- /* Chained Mode */
- if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RCHM) != (uint32_t)RESET) {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentRxDesc->Buffer2NextDescAddr);
- }
- /* Ring Mode */
- else {
- if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RERM) != (uint32_t)RESET) {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->RDTAR);
- } else {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentRxDesc + ETH_DMARXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2));
- }
- }
-}
-
-/* PHY */
-/**
- * @brief Get PHY of ETHERNET parameters.
- * @param PHYAddr: PHY device address, devices number max is 32.
- * @param PHYReg: PHY register address, register address max is 32.
- * Select one of the follwing values :
- * @arg PHY_BCR: Tranceiver Basic Control Register
- * @arg PHY_BSR: Tranceiver Basic Status Register
- * @arg PHY_SR : Tranceiver Status Register
- * @arg More PHY register could be read depending on the used PHY
- * @retval value read from the selected PHY register (if timeout return ERROR)
- */
-uint16_t ETH_GetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg)
-{
- uint32_t temp = 0;
- __IO uint32_t timeout = 0;
-
- /* Get the ETHERNET MAC_PHYAR value */
- temp = ETH_MAC->PHYAR;
- temp &= ~MAC_PHYAR_CLR_MASK;
- /* Configuration the PHY address register value */
- /* Set the PHY device address */
- temp |= (((uint32_t)PHYAddr << MAC_PHYAR_PHYADDRSHIFT) & ETH_MAC_PHYAR_PA);
- /* Set the PHY register address */
- temp |= (((uint32_t)PHYReg << MAC_PHYAR_PHYREGSHIFT) & ETH_MAC_PHYAR_PR);
- /* Set the read mode */
- temp &= ~ETH_MAC_PHYAR_PW;
- /* Set the PHY Busy bit */
- temp |= ETH_MAC_PHYAR_PB;
- ETH_MAC->PHYAR = temp;
- /* Check the PHY Busy flag status */
- do {
- timeout++;
- temp = ETH_MAC->PHYAR;
- } while ((temp & ETH_MAC_PHYAR_PB) && (timeout < (uint32_t)PHY_READ_TO));
- /* Return ERROR due to timeout */
- if (timeout == PHY_READ_TO) {
- return (uint16_t)ERROR;
- }
-
- /* Return PHY register selected value */
- return (uint16_t)(ETH_MAC->PHYDR);
-}
-
-/**
- * @brief Set PHY of ETHERNET parameters.
- * @param PHYAddr: PHY device address, devices number max is 32.
- * @param PHYReg: PHY register address, register address max is 32.
- * Select one of the follwing values :
- * @arg PHY_BCR : Tranceiver Control Register
- * @arg More PHY register could be written depending on the used PHY
- * @param PHYValue: write to register value
- * @retval The Write to the selected PHY register result(ERROR or SUCCESS)
- */
-uint32_t ETH_SetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg, uint16_t PHYValue)
-{
- uint32_t temp = 0;
- __IO uint32_t timeout = 0;
-
- /* Get the ETHERNET MAC_PHYAR value */
- temp = ETH_MAC->PHYAR;
- temp &= ~MAC_PHYAR_CLR_MASK;
- /* Configuration the PHY register address value */
- /* Set the PHY device address */
- temp |= (((uint32_t)PHYAddr << MAC_PHYAR_PHYADDRSHIFT) & ETH_MAC_PHYAR_PA);
- /* Set the PHY register address */
- temp |= (((uint32_t)PHYReg << MAC_PHYAR_PHYREGSHIFT) & ETH_MAC_PHYAR_PR);
- /* Set the write mode */
- temp |= ETH_MAC_PHYAR_PW;
- /* Set the PHY Busy bit */
- temp |= ETH_MAC_PHYAR_PB;
- /* Set the PHY selected register value */
- ETH_MAC->PHYDR = PHYValue;
- ETH_MAC->PHYAR = temp;
- /* Check the PHY Busy flag status */
- do {
- timeout++;
- temp = ETH_MAC->PHYAR;
- } while ((temp & ETH_MAC_PHYAR_PB) && (timeout < (uint32_t)PHY_WRITE_TO));
- /* Return ERROR due to timeout */
- if (timeout == PHY_WRITE_TO) {
- return ERROR;
- }
-
- return SUCCESS;
-}
-
-/**
- * @brief Enable or disable the PHY loopBack function by write PHY register.
- * @param PHYAddr: PHY device address, devices number max is 32.
- * @param NewValue: new value of the PHY loopBack mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval The Set PHYLoopBack mode result(ERROR or SUCCESS)
- */
-uint32_t ETH_PHYLoopBack_Enable(uint16_t PHYAddr, TypeState NewValue)
-{
- uint16_t temp = 0;
-
- /* Get the PHY BCR register value */
- temp = ETH_GetPHYRegisterValue(PHYAddr, PHY_BCR);
-
- if (NewValue != DISABLE) {
- /* Enable the PHY loopback mode */
- temp |= PHY_LOOPBACK;
- } else {
- /* Disable the PHY loopback mode (change to normal mode) */
- temp &= (uint16_t)(~(uint16_t)PHY_LOOPBACK);
- }
- /* Set the PHY BCR register with the new value */
- if (ETH_SetPHYRegisterValue(PHYAddr, PHY_BCR, temp) != (uint32_t)RESET) {
- return SUCCESS;
- } else {
- return ERROR;
- }
-}
-
-/* MAC */
-/**
- * @brief Enable or disable the MAC transmit function.
- * @param NewValue: new value of the MAC transmit function.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MACTransmission_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the MAC transmission */
- ETH_MAC->CFR |= ETH_MAC_CFR_TEN;
- } else {
- /* Disable the MAC transmission */
- ETH_MAC->CFR &= ~ETH_MAC_CFR_TEN;
- }
-}
-
-/**
- * @brief Enable or disable the MAC receive function.
- * @param NewValue: new value of the MAC reception.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MACReception_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the MAC reception */
- ETH_MAC->CFR |= ETH_MAC_CFR_REN;
- } else {
- /* Disable the MAC reception */
- ETH_MAC->CFR &= ~ETH_MAC_CFR_REN;
- }
-}
-
-/**
- * @brief Get the bit flag of the ETHERNET flow control busy status.
- * @param None
- * @retval current flow control busy bit status
- */
-TypeState ETH_GetFlowControlBusyBitState(void)
-{
- /* Check the flow control busy bit status */
- if ((ETH_MAC->FCTLR & ETH_MAC_FCTLR_FLCBBKPA) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Initiate a Pause Frame in Full-duplex mode only.
- * @param None
- * @retval None
- */
-void ETH_PauseFrameInit(void)
-{
- /* Initiate pause control frame in full duplex mode*/
- ETH_MAC->FCTLR |= ETH_MAC_FCTLR_FLCBBKPA;
-}
-
-/**
- * @brief Enable or disable the BackPressure requests in Half-duplex only.
- * @param NewValue: new value of the BackPressure operation requests.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_BackPressureActivation_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the BackPressure requests */
- ETH_MAC->FCTLR |= ETH_MAC_FCTLR_FLCBBKPA;
- } else {
- /* Disable the BackPressure requests */
- ETH_MAC->FCTLR &= ~ETH_MAC_FCTLR_FLCBBKPA;
- }
-}
-
-/**
- * @brief Get the status flag of ETH_MAC_ISR register.
- * @param ETH_MAC_FLAG: the status flag of ETH_MAC_ISR register.
- * Select one of the follwing values :
- * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
- * @arg ETH_MAC_FLAG_MSCT : MSC transmit flag
- * @arg ETH_MAC_FLAG_MSCR : MSC receive flag
- * @arg ETH_MAC_FLAG_MSC : MSC flag
- * @arg ETH_MAC_FLAG_WUM : WUM flag
- * @retval The current MAC bit selected status(SET or RESET).
- */
-TypeState ETH_GetMACBitState(uint32_t ETH_MAC_FLAG)
-{
- /* Check the ETH_MAC_FLAG status */
- if ((ETH_MAC->ISR & ETH_MAC_FLAG) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Get the interrupt flag of ETH_MAC_ISR register.
- * @param ETH_MAC_INT: the interrupt flag of ETH_MAC_ISR register.
- * Select one of the follwing values :
- * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_INT_MSCT : MSC transmit interrupt
- * @arg ETH_MAC_INT_MSCR : MSC receive interrupt
- * @arg ETH_MAC_INT_MSC : MSC interrupt
- * @arg ETH_MAC_INT_WUM : WUM interrupt
- * @retval The current MAC interrupt bit selected status(SET or RESET).
- */
-TypeState ETH_GetMACIntBitState(uint32_t ETH_MAC_INT)
-{
- /* Check the ETH_MAC_INT status */
- if ((ETH_MAC->ISR & ETH_MAC_INT) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_MAC_INT control bit.
- * @param ETH_MAC_INT: the interrupt bit flag.
- * Select one of the follwing values :
- * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_INT_WUM : WUM interrupt
- * @param NewValue: new value of the ETH_MAC_INT value.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MACINTConfig(uint32_t ETH_MAC_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the MAC interrupt */
- ETH_MAC->IMR &= (~(uint32_t)ETH_MAC_INT);
- } else {
- /* Disable the MAC interrupt */
- ETH_MAC->IMR |= ETH_MAC_INT;
- }
-}
-
-/**
- * @brief Set the MAC address to MAC address register selected.
- * @param addr: The MAC address register to selected.
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESS0 : MAC Address0
- * @arg ETH_MAC_ADDRESS1 : MAC Address1
- * @arg ETH_MAC_ADDRESS2 : MAC Address2
- * @arg ETH_MAC_ADDRESS3 : MAC Address3
- * @param buf: Pointer to application MAC address buffer(6 bytes).
- * @retval None
- */
-void ETH_SetMACAddress(uint32_t addr, uint8_t *buf)
-{
- uint32_t temp;
-
- temp = ((uint32_t)buf[5] << 8) | (uint32_t)buf[4];
- /* Set the selectecd MAC address high register */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) = temp;
- temp = ((uint32_t)buf[3] << 24) | ((uint32_t)buf[2] << 16) | ((uint32_t)buf[1] << 8) | buf[0];
-
- /* Set the selectecd MAC address low register */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + addr)) = temp;
-}
-
-/**
- * @brief Get the MAC address from MAC address register selected.
- * @param addr: The MAC addres to selected.
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESS0 : MAC Address0
- * @arg ETH_MAC_ADDRESS1 : MAC Address1
- * @arg ETH_MAC_ADDRESS2 : MAC Address2
- * @arg ETH_MAC_ADDRESS3 : MAC Address3
- * @param buf: Pointer to application MAC address buffer(6 bytes).
- * @retval None
- */
-void ETH_GetMACAddress(uint32_t addr, uint8_t *buf)
-{
- uint32_t temp;
-
- /* Get the selectecd MAC address high register */
- temp = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr));
-
- buf[5] = ((temp >> 8) & (uint8_t)0xFF);
- buf[4] = (temp & (uint8_t)0xFF);
- /* Get the selectecd MAC address low register */
- temp = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + addr));
- buf[3] = ((temp >> 24) & (uint8_t)0xFF);
- buf[2] = ((temp >> 16) & (uint8_t)0xFF);
- buf[1] = ((temp >> 8) & (uint8_t)0xFF);
- buf[0] = (temp & (uint8_t)0xFF);
-}
-
-/**
- * @brief Enable or disable the Address perfect filtering.
- * @param addr: the MAC address register selected for prfect filtering.
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESS1 : MAC Address1
- * @arg ETH_MAC_ADDRESS2 : MAC Address2
- * @arg ETH_MAC_ADDRESS3 : MAC Address3
- * @param NewValue: new value of the MAC address register selected for perfect filtering.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MACAddressPerfectFilter_Enable(uint32_t addr, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the perfect filtering to the MAC address register selected */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) |= ETH_MAC_A1HR_AFE;
- } else {
- /* Disable the perfect filtering to the MAC address register selected */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) &= (~(uint32_t)ETH_MAC_A1HR_AFE);
- }
-}
-
-/**
- * @brief Set the selected MAC address filter type mode.
- * @param addr: the MAC address to be used for filtering.
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESS1 : MAC Address1
- * @arg ETH_MAC_ADDRESS2 : MAC Address2
- * @arg ETH_MAC_ADDRESS3 : MAC Address3
- * @param Filterfield: the mode of receiving field for comparaison
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESSFILTER_SA : Compare with the SA fields of the received frame.
- * @arg ETH_MAC_ADDRESSFILTER_DA : Compare with the DA fields of the received frame.
- * @retval None
- */
-void ETH_MACAddressFilterConfig(uint32_t addr, uint32_t Filterfield)
-{
- if (Filterfield != ETH_MAC_ADDRESSFILTER_DA) {
- /* Compare with the SA fields of the received frame. */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) |= ETH_MAC_A1HR_SAF;
- } else {
- /* compare with the DA fields of the received frame. */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) &= (~(uint32_t)ETH_MAC_A1HR_SAF);
- }
-}
-
-/**
- * @brief Set the selected MAC address filter maskbyte.
- * @param addr: the MAC address to be used for filtering
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESS1 : MAC Address1
- * @arg ETH_MAC_ADDRESS2 : MAC Address2
- * @arg ETH_MAC_ADDRESS3 : MAC Address3
- * @param addrmask: the address bytes be selected for address filtering comparaison
- * Select one of the follwing values :
- * @arg ETH_MAC_ADDRESSMASK_BYTE6 : Mask MAC Address high register bits [15:8].
- * @arg ETH_MAC_ADDRESSMASK_BYTE5 : Mask MAC Address high register bits [7:0].
- * @arg ETH_MAC_ADDRESSMASK_BYTE4 : Mask MAC Address low register bits [31:24].
- * @arg ETH_MAC_ADDRESSMASK_BYTE3 : Mask MAC Address low register bits [23:16].
- * @arg ETH_MAC_ADDRESSMASK_BYTE2 : Mask MAC Address low register bits [15:8].
- * @arg ETH_MAC_ADDRESSMASK_BYTE1 : Mask MAC Address low register bits [7:0].
- * @retval None
- */
-void ETH_MACAddressFilterMaskBytesConfig(uint32_t addr, uint32_t addrmask)
-{
- /* Clear the MB bit of selected MAC address */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) &= (~(uint32_t)ETH_MAC_A1HR_MB);
- /* Set the mask bytes of selected Filetr */
- (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) |= addrmask;
-}
-
-/* DMA Tx/Rx Desciptors */
-
-/**
- * @brief Initialize the DMA Tx descriptors's parameters in chain mode.
- * @param DMATxDescTab: Pointer to the first Tx descriptor table
- * @param pTxBuff: Pointer to the first TxBuffer table
- * @param TxBuffCnt: the used Tx desc num in the table
- * @retval None
- */
-void ETH_DMATxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff, uint32_t TxBuffCnt)
-{
- uint32_t num = 0;
- ETH_DMADESCTypeDef *DMATxDesc;
-
- DMACurrentTxDesc = DMATxDescTab;
- /* Configuration each DMATxDesc descriptor */
- for (num = 0; num < TxBuffCnt; num++) {
- /* Get the pointer to the next descriptor of the Tx Desc table */
- DMATxDesc = DMATxDescTab + num;
- /* Set TCH bit with desc status */
- DMATxDesc->Status = ETH_DMATXDESC_TCHM;
-
- /* Set Buffer1 address pointer to application buffer */
- DMATxDesc->Buffer1Addr = (uint32_t)(&pTxBuff[num * ETH_MAX_FRAME_SIZE]);
-
- if (num < (TxBuffCnt - 1)) {
- /* Buffer2NextDescAddr equal to next descriptor address in the Tx Desc table */
- DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + num + 1);
- } else {
- /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Tx Desc table */
- DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
- }
- }
- ETH_DMA->TDTAR = (uint32_t) DMATxDescTab;
-}
-
-/**
- * @brief Initialize the DMA Tx descriptors's parameters in ring mode.
- * @param DMATxDescTab: Pointer to the first Tx descriptor table
- * @param pTxBuff1: Pointer to the first TxBuffer1 table
- * @param pTxBuff2: Pointer to the first TxBuffer2 table
- * @param TxBuffCnt: the used Tx desc num in the table
- * @retval None
- */
-void ETH_DMATxDescRingModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff1, uint8_t *pTxBuff2, uint32_t TxBuffCnt)
-{
- uint32_t num = 0;
- ETH_DMADESCTypeDef *DMATxDesc;
-
- DMACurrentTxDesc = DMATxDescTab;
- /* Configuration each DMATxDesc descriptor */
- for (num = 0; num < TxBuffCnt; num++) {
- /* Get the pointer to the next descriptor of the Tx Desc table */
- DMATxDesc = DMATxDescTab + num;
- /* Set Buffer1 address pointer to application buffer1 */
- DMATxDesc->Buffer1Addr = (uint32_t)(&pTxBuff1[num * ETH_MAX_FRAME_SIZE]);
-
- /* Set Buffer2 address pointer to application buffer2 */
- DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&pTxBuff2[num * ETH_MAX_FRAME_SIZE]);
-
- if (num == (TxBuffCnt - 1)) {
- /* Set ETH_DMATXDESC_TERM bit as transmitting End */
- DMATxDesc->Status = ETH_DMATXDESC_TERM;
- }
- }
- ETH_DMA->TDTAR = (uint32_t) DMATxDescTab;
-}
-
-/**
- * @brief Get the bit flag of ETHERNET DMA Tx Desc.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param ETH_DMATxDescFlag: the flag of Tx descriptor status.
- * Select one of the follwing values :
- * @arg ETH_DMATXDESC_BUSY : BUSY bit: descriptor is owned by DMA engine
- * @arg ETH_DMATXDESC_INTC : Interrupt on completetion
- * @arg ETH_DMATXDESC_LSG : Last Segment
- * @arg ETH_DMATXDESC_FSG : First Segment
- * @arg ETH_DMATXDESC_DCRC : Disable CRC
- * @arg ETH_DMATXDESC_DPAD : Disable Pad
- * @arg ETH_DMATXDESC_TTSEN : Transmit Time Stamp Enable
- * @arg ETH_DMATXDESC_TERM : Transmit End of Ring
- * @arg ETH_DMATXDESC_TCHM : Second Address Chained
- * @arg ETH_DMATXDESC_TTMSS : Tx Time Stamp Status
- * @arg ETH_DMATXDESC_IPHE : IP Header Error
- * @arg ETH_DMATXDESC_ES : Error summary
- * @arg ETH_DMATXDESC_JT : Jabber Timeout
- * @arg ETH_DMATXDESC_FRMF : Frame Flushed: DMA/MTL flushed the frame due to SW flush
- * @arg ETH_DMATXDESC_IPPE : IP Payload Error
- * @arg ETH_DMATXDESC_LCA : Loss of Carrier: carrier lost during tramsmission
- * @arg ETH_DMATXDESC_NCA : No Carrier: no carrier signal from the tranceiver
- * @arg ETH_DMATXDESC_LCO : Late Collision: transmission aborted due to collision
- * @arg ETH_DMATXDESC_ECO : Excessive Collision: transmission aborted after 16 collisions
- * @arg ETH_DMATXDESC_VFRM : VLAN Frame
- * @arg ETH_DMATXDESC_COCNT : Collision Count
- * @arg ETH_DMATXDESC_EXD : Excessive Deferral
- * @arg ETH_DMATXDESC_UFE : Underflow Error: late data arrival from the memory
- * @arg ETH_DMATXDESC_DB : Deferred Bit
- * @retval The current ETH_DMATxDescFlag selected bit status(SET or RESET).
- */
-TypeState ETH_GetDMATxDescBitState(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
-{
- if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) {
- /* ETH_DMATxDescFlag is set */
- return SET;
- } else {
- /* ETH_DMATxDescFlag is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Get the DMA Tx Desc collision count.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @retval The value of Transmit descriptor collision counter.
- */
-uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
-{
- return ((DMATxDesc->Status & ETH_DMATXDESC_COCNT) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
-}
-
-/**
- * @brief Set the DMA Tx Desc Busy bit for DMA or CPU.
- * @param DMATxDesc: Pointer on a Transmit descriptor
- * @retval None
- */
-void ETH_SetDMATxDescBusyBit(ETH_DMADESCTypeDef *DMATxDesc)
-{
- DMATxDesc->Status |= ETH_DMATXDESC_BUSY;
-}
-
-/**
- * @brief Enable or disable the ETH_DMATXDESC_INTC control bit.
- * @param DMATxDesc: Pointer to a Tx descriptor
- * @param NewValue: new value of the ETH_DMATXDESC_INTC control bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATxDescTransmitINTConfig(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMA Tx Desc after the frame has been transmitted Set Transmit interrupt */
- DMATxDesc->Status |= ETH_DMATXDESC_INTC;
- } else {
- /* Disable the DMA Tx Desc after the frame has been transmitted Set Transmit interrupt */
- DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_INTC);
- }
-}
-
-/**
- * @brief Enable or disable the DMATxDesc_FrameSegment control bit.
- * @param DMATxDesc: Pointer to a Tx descriptor
- * @param DMATxDesc_Segment: the actual Tx buffer contain first or last segment.
- * Select one of the follwing values :
- * @arg ETH_DMATXDESC_LASTSEGMENT : current Tx desc selected contain last segment
- * @arg ETH_DMATXDESC_FIRSTSEGMENT : current Tx desc selected contain first segment
- * @retval None
- */
-void ETH_SetDMATxDescFrameSegment(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Segment)
-{
- DMATxDesc->Status |= DMATxDesc_Segment;
-}
-
-/**
- * @brief Set the DMA Tx Desc Checksum Insertion mode.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param DMATxDesc_Checksum: the type of DMA Tx descriptor checksum insertion.
- * Select one of the follwing values :
- * @arg ETH_DMATXDESC_CHECKSUMDISABLE : Checksum bypass
- * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
- * @retval None
- */
-void ETH_SetDMATxDescChecksumInsertion(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
-{
- DMATxDesc->Status |= DMATxDesc_Checksum;
-}
-
-/**
- * @brief Enable or disable the DMA Tx descriptor CRC function.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param NewValue: new value of the DMA Tx descriptor CRC function.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATxDescCRC_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMATxDesc CRC */
- DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DCRC);
- } else {
- /* Disable the DMATxDesc CRC */
- DMATxDesc->Status |= ETH_DMATXDESC_DCRC;
- }
-}
-
-/**
- * @brief Enable or disable the DMA Tx descriptor end of ring.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param NewValue: new value of the DMA Tx descriptor end of ring.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMATxDesc end of ring */
- DMATxDesc->Status |= ETH_DMATXDESC_TERM;
- } else {
- /* Disable the DMATxDesc end of ring */
- DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TERM);
- }
-}
-
-/**
- * @brief Enable or disable the DMA Tx descriptor second address chained.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param NewValue: new value of the DMA Tx descriptor second address chained.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMATxDesc second address chained */
- DMATxDesc->Status |= ETH_DMATXDESC_TCHM;
- } else {
- /* Disable the DMATxDesc second address chained */
- DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TCHM);
- }
-}
-
-/**
- * @brief Enable or disable auto padding when transmit frame shorter than 64 bytes.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param NewValue: new value of the auto padding status.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATxDescShortFramePadding_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMATxDesc short frame padding */
- DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DPAD);
- } else {
- /* Disable the DMATxDesc short frame padding */
- DMATxDesc->Status |= ETH_DMATXDESC_DPAD;
- }
-}
-
-/**
- * @brief Enable or disable the DMA Tx descriptor time stamp function.
- * @param DMATxDesc: pointer to a DMA Tx descriptor
- * @param NewValue: new value of the DMA Tx descriptor time stamp.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATxDescTimeStamp_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMATxDesc time stamp */
- DMATxDesc->Status |= ETH_DMATXDESC_TTSEN;
- } else {
- /* Disable the DMATxDesc time stamp */
- DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TTSEN);
- }
-}
-
-/**
- * @brief Set the frame length by configures the DMA Tx Desc buffer1 and buffer2 sizes.
- * @param DMATxDesc: Pointer to a Tx descriptor
- * @param Buffer1Size: the Tx buffer1 size.
- * @param Buffer2Size: the Tx buffer2 size, set to 0 indicates it is not being used.
- * @retval None
- */
-void ETH_SetDMATxDescBufferSize(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffer1Size, uint32_t Buffer2Size)
-{
- DMATxDesc->ControlBufferSize |= (Buffer1Size | (Buffer2Size << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
-}
-
-/**
- * @brief Initialize the DMA Rx descriptors's parameters in chain mode.
- * @param DMARxDescTab: Pointer to the first Rx descriptor table
- * @param pRxBuff: Pointer to the first RxBuffer table
- * @param RxBuffCnt: the used Rx desc num in the table
- * @retval None
- */
-void ETH_DMARxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff, uint32_t RxBuffCnt)
-{
- uint32_t num = 0;
- ETH_DMADESCTypeDef *DMARxDesc;
-
- DMACurrentRxDesc = DMARxDescTab;
- /* Configuration each DMARxDesc descriptor */
- for (num = 0; num < RxBuffCnt; num++) {
- /* Get the pointer to the next descriptor of the Rx Desc table */
- DMARxDesc = DMARxDescTab + num;
- DMARxDesc->Status = ETH_DMARXDESC_BUSY;
-
- /* Set TCH bit and buffer1 size */
- DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCHM | (uint32_t)ETH_MAX_FRAME_SIZE;
- /* Set Buffer1 address pointer to application buffer */
- DMARxDesc->Buffer1Addr = (uint32_t)(&pRxBuff[num * ETH_MAX_FRAME_SIZE]);
-
- if (num < (RxBuffCnt - 1)) {
- /* Buffer2NextDescAddr equal to next descriptor address in the Rx Desc table */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + num + 1);
- } else {
- /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Rx Desc table */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
- }
- }
-
- ETH_DMA->RDTAR = (uint32_t) DMARxDescTab;
-}
-
-/**
- * @brief Initialize the DMA Rx descriptors's parameters in ring mode.
- * @param DMARxDescTab: Pointer to the first Rx descriptor table
- * @param pRxBuff1: Pointer to the first RxBuffer1 table
- * @param pRxBuff2: Pointer to the first RxBuffer2 table
- * @param RxBuffCnt: the used Rx descriptor num in the table
- * @retval None
- */
-void ETH_DMARxDescRingModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff1, uint8_t *pRxBuff2, uint32_t RxBuffCnt)
-{
- uint32_t num = 0;
- ETH_DMADESCTypeDef *DMARxDesc;
-
- DMACurrentRxDesc = DMARxDescTab;
- /* Configuration each DMARxDesc descriptor */
- for (num = 0; num < RxBuffCnt; num++) {
- /* Get the pointer to the next descriptor of the Rx Desc table */
- DMARxDesc = DMARxDescTab + num;
- DMARxDesc->Status = ETH_DMARXDESC_BUSY;
- DMARxDesc->ControlBufferSize = ETH_MAX_FRAME_SIZE;
- /* Set Buffer1 address pointer to application buffer1 */
- DMARxDesc->Buffer1Addr = (uint32_t)(&pRxBuff1[num * ETH_MAX_FRAME_SIZE]);
-
- /* Set Buffer2 address pointer to application buffer2 */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&pRxBuff2[num * ETH_MAX_FRAME_SIZE]);
-
- if (num == (RxBuffCnt - 1)) {
- /* Set ETH_DMARXDESC_RERR bit as Receive End */
- DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_RERR;
- }
- }
-
- ETH_DMA->RDTAR = (uint32_t) DMARxDescTab;
-}
-
-/**
- * @brief Get the bit flag of ETHERNET Rx descriptor.
- * @param DMARxDesc: pointer to a DMA Rx descriptor
- * @param ETH_DMARxDescFlag: the flag of Rx descriptor status.
- * Select one of the follwing values :
- * @arg ETH_DMARXDESC_BUSY : Descriptor is owned by DMA engine
- * @arg ETH_DMARXDESC_DAFF : DA Filter Fail for the rx frame
- * @arg ETH_DMARXDESC_ERRS : Error summary
- * @arg ETH_DMARXDESC_DERR : Desciptor error: no more descriptors for receive frame
- * @arg ETH_DMARXDESC_SAFF : SA Filter Fail for the received frame
- * @arg ETH_DMARXDESC_LERR : Frame size not matching with length field
- * @arg ETH_DMARXDESC_OERR : Overflow Error: Frame was damaged due to buffer overflow
- * @arg ETH_DMARXDESC_VTAG : VLAN Tag: received frame is a VLAN frame
- * @arg ETH_DMARXDESC_FDES : First descriptor of the frame
- * @arg ETH_DMARXDESC_LDES : Last descriptor of the frame
- * @arg ETH_DMARXDESC_IPHCERR : IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
- * @arg ETH_DMARXDESC_LCO : Late collision occurred during reception
- * @arg ETH_DMARXDESC_FRMT : Frame type - Ethernet, otherwise 802.3
- * @arg ETH_DMARXDESC_RWDT : Receive Watchdog Timeout: watchdog timer expired during reception
- * @arg ETH_DMARXDESC_RERR : Receive error: error reported by MII interface
- * @arg ETH_DMARXDESC_DERR : Dribble bit error: frame contains non int multiple of 8 bits
- * @arg ETH_DMARXDESC_CERR : CRC error
- * @arg ETH_DMARXDESC_PCERR : Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
- * @retval The current ETH_DMARxDescFlag selected bit status(SET or RESET).
- */
-TypeState ETH_GetDMARxDescBitState(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
-{
- if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) {
- /* ETH_DMARxDescFlag is set */
- return SET;
- } else {
- /* ETH_DMARxDescFlag is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Set the DMA Rx Desc busy bit for DMA or CPU
- * @param DMARxDesc: Pointer to a Rx descriptor
- * @retval None
- */
-void ETH_SetDMARxDescBusyBit(ETH_DMADESCTypeDef *DMARxDesc)
-{
- DMARxDesc->Status |= ETH_DMARXDESC_BUSY;
-}
-
-/**
- * @brief Get the DMA Rx Desc frame length.
- * @param DMARxDesc: pointer to a DMA Rx descriptor
- * @retval Received frame length of the Rx descriptor selected.
- */
-uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
-{
- return ((DMARxDesc->Status & ETH_DMARXDESC_FRML) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
-}
-
-/**
- * @brief Enable or disable the DMA Rx descriptor receive interrupt.
- * @param DMARxDesc: Pointer to a Rx descriptor
- * @param NewValue: new value of the DMA Rx descriptor interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMARxDescReceiveINTConfig(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMARxDesc receive interrupt */
- DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_DINTC);
- } else {
- /* Disable the DMARxDesc receive interrupt */
- DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_DINTC;
- }
-}
-
-/**
- * @brief Enable or disable the DMA Rx descriptor end of ring.
- * @param DMARxDesc: pointer to a DMA Rx descriptor
- * @param NewValue: new value of the DMA Rx descriptor end of ring.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMARxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMARxDesc end of ring */
- DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_RERR;
- } else {
- /* Disable the DMARxDesc end of ring */
- DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_RERR);
- }
-}
-
-/**
- * @brief Enable or disable the DMA Rx descriptor second address chained.
- * @param DMARxDesc: pointer to a DMA Rx descriptor
- * @param NewValue: new value of the DMA Rx descriptor second address chained.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMARxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMARxDesc second address chained */
- DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_RCHM;
- } else {
- /* Disable the DMARxDesc second address chained */
- DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_RCHM);
- }
-}
-
-/**
- * @brief Get the ETHERNET DMA Rx Desc buffer size.
- * @param DMARxDesc: pointer to a DMA Rx descriptor
- * @param DMARxDesc_BufferSelect: the DMA Rx descriptor buffer.
- * Select one of the follwing values :
- * @arg ETH_DMARXDESC_BUFFER1 : DMA Rx Desc Buffer1
- * @arg ETH_DMARXDESC_BUFFER2 : DMA Rx Desc Buffer2
- * @retval The Receive descriptor selected buffer size(buffer1 or buffer2).
- */
-uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_BufferSelect)
-{
- if (DMARxDesc_BufferSelect != ETH_DMARXDESC_BUFFER1) {
- return ((DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RB2S) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
- } else {
- return (DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RB1S);
- }
-}
-
-/* DMA */
-/**
- * @brief Resets all MAC subsystem.
- * @param None
- * @retval None
- */
-void ETH_SoftReset(void)
-{
- ETH_DMA->BCR |= ETH_DMA_BCR_SWR;
-}
-
-/**
- * @brief Get the bit flag of ETHERNET software reset.
- * @param None
- * @retval The current DMA Bus Mode register SWR bit status(SET or RESET).
- */
-TypeState ETH_GetSoftResetStatus(void)
-{
- if ((ETH_DMA->BCR & ETH_DMA_BCR_SWR) != (uint32_t)RESET) {
- /* The ETH_DMA_BCR_SWR bit is set */
- return SET;
- } else {
- /* The ETH_DMA_BCR_SWR bit is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Get the bit flag of specified ETHERNET DMA.
- * @param ETH_DMA_FLAG: the flag of ETHERNET DMA_STR register.
- * Select one of the follwing values :
- * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
- * @arg ETH_DMA_FLAG_WUM : WUM flag
- * @arg ETH_DMA_FLAG_MSC : MSC flag
- * @arg ETH_DMA_FLAG_DATATRANSFERERROR : Error bits 0-data buffer, 1-desc. access
- * @arg ETH_DMA_FLAG_READWRITEERROR : Error bits 0-write trnsf, 1-read transfr
- * @arg ETH_DMA_FLAG_ACCESSERROR : Error bits 0-Rx DMA, 1-Tx DMA
- * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
- * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
- * @arg ETH_DMA_FLAG_ER : Early receive flag
- * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
- * @arg ETH_DMA_FLAG_ET : Early transmit flag
- * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
- * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
- * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
- * @arg ETH_DMA_FLAG_R : Receive flag
- * @arg ETH_DMA_FLAG_TU : Underflow flag
- * @arg ETH_DMA_FLAG_RO : Overflow flag
- * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
- * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
- * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
- * @arg ETH_DMA_FLAG_T : Transmit flag
- * @retval The current ETH_DMA_FLAG selected bit status(SET or RESET).
- */
-TypeState ETH_GetDMABitState(uint32_t ETH_DMA_FLAG)
-{
- if ((ETH_DMA->STR & ETH_DMA_FLAG) != (uint32_t)RESET) {
- /* ETH_DMA_FLAG is set */
- return SET;
- } else {
- /* ETH_DMA_FLAG is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the ETHERNETs DMA bit flag.
- * @param ETH_DMA_FLAG: the flag of ETH_DMA_STR register to clear.
- * Select one of the follwing values :
- * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
- * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
- * @arg ETH_DMA_FLAG_ER : Early receive flag
- * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
- * @arg ETH_DMA_FLAG_ETI : Early transmit flag
- * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
- * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
- * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
- * @arg ETH_DMA_FLAG_R : Receive flag
- * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag
- * @arg ETH_DMA_FLAG_RO : Receive Overflow flag
- * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
- * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
- * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
- * @arg ETH_DMA_FLAG_T : Transmit flag
- * @retval None
- */
-void ETH_DMAClearBitState(uint32_t ETH_DMA_FLAG)
-{
- ETH_DMA->STR = (uint32_t) ETH_DMA_FLAG;
-}
-
-/**
- * @brief Get the bit flag of DMA interrupt.
- * @param ETH_DMA_INT: the interrupt source flag of ETHERNET DMA_STR register.
- * Select one of the follwing values :
- * @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt
- * @arg ETH_DMA_INT_WUM : WUM interrupt
- * @arg ETH_DMA_INT_MSC : MSC interrupt
- * @arg ETH_DMA_INT_NIS : Normal interrupt summary
- * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- * @arg ETH_DMA_INT_ER : Early receive interrupt
- * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- * @arg ETH_DMA_INT_ET : Early transmit interrupt
- * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- * @arg ETH_DMA_INT_R : Receive interrupt
- * @arg ETH_DMA_INT_TU : Underflow interrupt
- * @arg ETH_DMA_INT_RO : Overflow interrupt
- * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- * @arg ETH_DMA_INT_T : Transmit interrupt
- * @retval The current ETH_DMA_INT selected bit status(SET or RESET).
- */
-TypeState ETH_GetDMAIntBitState(uint32_t ETH_DMA_INT)
-{
- if ((ETH_DMA->STR & ETH_DMA_INT) != (uint32_t)RESET) {
- /* ETH_DMA_INT is set */
- return SET;
- } else {
- /* ETH_DMA_INT is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the ETHERNETs DMA IT bit flag.
- * @param ETH_DMA_INT: the interrupt source flag of ETH_DMA_STR register to clear.
- * Select one of the follwing values :
- * @arg ETH_DMA_INT_NIS : Normal interrupt summary
- * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- * @arg ETH_DMA_INT_ER : Early receive interrupt
- * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- * @arg ETH_DMA_INT_ETI : Early transmit interrupt
- * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- * @arg ETH_DMA_INT_R : Receive interrupt
- * @arg ETH_DMA_INT_TU : Transmit Underflow interrupt
- * @arg ETH_DMA_INT_RO : Receive Overflow interrupt
- * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- * @arg ETH_DMA_INT_T : Transmit interrupt
- * @retval None
- */
-void ETH_DMAClearIntBitState(uint32_t ETH_DMA_INT)
-{
- ETH_DMA->STR = (uint32_t) ETH_DMA_INT;
-}
-
-/**
- * @brief Get the DMA Transmit Process State.
- * @param None
- * @retval The current DMA Transmit Process State:
- * Select one of the follwing values :
- * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued
- * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor
- * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status
- * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory
- * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
- * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor
- */
-uint32_t ETH_GetTransmitProcessState(void)
-{
- return ((uint32_t)(ETH_DMA->STR & ETH_DMA_STR_TS));
-}
-
-/**
- * @brief Get the DMA Receive Process State.
- * @param None
- * @retval The current DMA Receive Process State:
- * Select one of the follwing values :
- * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued
- * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor
- * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet
- * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
- * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor
- * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory
- */
-uint32_t ETH_GetReceiveProcessState(void)
-{
- return ((uint32_t)(ETH_DMA->STR & ETH_DMA_STR_RS));
-}
-
-/**
- * @brief Flush the ETHERNET transmit FIFO.
- * @param None
- * @retval None
- */
-void ETH_CleanTransmitFIFO(void)
-{
- /* Set the FTF bit for Flushing Transmit FIFO */
- ETH_DMA->CTLR |= ETH_DMA_CTLR_FTF;
-}
-
-/**
- * @brief Get the bit flag of ETHERNET transmit FIFO.
- * @param None
- * @retval The current ETHERNET flush transmit FIFO bit status(SET or RESET).
- */
-TypeState ETH_GetFlushTransmitFIFOStatus(void)
-{
- if ((ETH_DMA->CTLR & ETH_DMA_CTLR_FTF) != (uint32_t)RESET) {
- /* Flush transmit FIFO bit is set */
- return SET;
- } else {
- /* Flush transmit FIFO bit is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Enable or disable the DMA transmission function.
- * @param NewValue: new value of the DMA transmission status.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMATransmission_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Set the STE bit for Enable the DMA transmission */
- ETH_DMA->CTLR |= ETH_DMA_CTLR_STE;
- } else {
- /* Reset the STE bit for Disable the DMA transmission */
- ETH_DMA->CTLR &= ~ETH_DMA_CTLR_STE;
- }
-}
-
-/**
- * @brief Enable or disable the DMA reception function.
- * @param NewValue: new value of the DMA reception status.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMAReception_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable DMA reception */
- ETH_DMA->CTLR |= ETH_DMA_CTLR_SRE;
- } else {
- /* Disable DMA reception */
- ETH_DMA->CTLR &= ~ETH_DMA_CTLR_SRE;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_DMA_INT control bit.
- * @param ETH_DMA_INT: the interrupt source flag of ETH_DMA_IER register.
- * Select one of the follwing values :
- * @arg ETH_DMA_INT_NIS : Normal interrupt summary
- * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- * @arg ETH_DMA_INT_ER : Early receive interrupt
- * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- * @arg ETH_DMA_INT_ET : Early transmit interrupt
- * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- * @arg ETH_DMA_INT_R : Receive interrupt
- * @arg ETH_DMA_INT_TU : Underflow interrupt
- * @arg ETH_DMA_INT_RO : Overflow interrupt
- * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- * @arg ETH_DMA_INT_T : Transmit interrupt
- * @param NewValue: new value of the DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_DMAINTConfig(uint32_t ETH_DMA_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_DMA_INT control bit */
- ETH_DMA->IER |= ETH_DMA_INT;
- } else {
- /* Disable the ETH_DMA_INT control bit */
- ETH_DMA->IER &= (~(uint32_t)ETH_DMA_INT);
- }
-}
-
-/**
- * @brief Get the bit flag of ETHERNET DMA overflow.
- * @param ETH_DMA_Overflow: the DMA overflow flag of ETHERNET DMA_MFBOCNT register.
- * Select one of the follwing values :
- * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflow Counter
- * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Missed Frame Counter
- * @retval The current ETHERNET DMA overflow Flag selected bit status(SET or RESET).
- */
-TypeState ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
-{
- if ((ETH_DMA->MFBOCNT & ETH_DMA_Overflow) != (uint32_t)RESET) {
- /* DMA overflow Flag is set */
- return SET;
- } else {
- /* DMA overflow Flag is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Get the DMA Rx value of overflow Missed Frame Counter.
- * @param None
- * @retval The ETH_DMA_MFBOCNT register MFA bit value.
- */
-uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
-{
- return ((uint32_t)((ETH_DMA->MFBOCNT & ETH_DMA_MFBOCNT_MSFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
-}
-
-/**
- * @brief Get the DMA value of Buffer unavailable Missed Frame Counter.
- * @param None
- * @retval The ETH_DMA_MFBOCNT register MFC bit value.
- */
-uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
-{
- return ((uint32_t)(ETH_DMA->MFBOCNT) & ETH_DMA_MFBOCNT_MSFC);
-}
-
-/**
- * @brief Get the DMA value of the current Tx desc start address.
- * @param None
- * @retval The ETH_DMA_CTDAR register value.
- */
-uint32_t ETH_GetCurrentTxDescStartAddress(void)
-{
- return ((uint32_t)(ETH_DMA->CTDAR));
-}
-
-/**
- * @brief Get the DMA value of the current Rx desc start address.
- * @param None
- * @retval The ETH_DMA_CRDAR register value.
- */
-uint32_t ETH_GetCurrentRxDescStartAddress(void)
-{
- return ((uint32_t)(ETH_DMA->CRDAR));
-}
-
-/**
- * @brief Get the DMA value of the current Tx buffer address.
- * @param None
- * @retval The ETH_DMA_CTBAR register value.
- */
-uint32_t ETH_GetCurrentTxBufferAddress(void)
-{
- return ((uint32_t)(ETH_DMA->CTBAR));
-}
-
-/**
- * @brief Get the DMA value of the current Rx buffer address.
- * @param None
- * @retval The ETH_DMA_CRBAR register value.
- */
-uint32_t ETH_GetCurrentRxBufferAddress(void)
-{
- return ((uint32_t)(ETH_DMA->CRBAR));
-}
-
-/**
- * @brief Poll the DMA Transmission enable by writing any value to the ETH_DMA_TPER register.
- * This will make the DMA to resume transmission.
- * @param None
- * @retval None.
- */
-void ETH_ResumeDMATransmission(void)
-{
- ETH_DMA->TPER = 0;
-}
-
-/**
- * @brief Poll the DMA Transmission enable by writing any value to the ETH_DMA_RPER register.
- * This will make the DMA to resume reception.
- * @param None
- * @retval None.
- */
-void ETH_ResumeDMAReception(void)
-{
- ETH_DMA->RPER = 0;
-}
-
-/* WUM */
-/**
- * @brief Reset Wakeup frame filter register pointer.
- * @param None
- * @retval None
- */
-void ETH_WakeUpFrameFilterRegisterReset(void)
-{
- /* Set WUFFRPR bit for Reseting the ETH_MAC_RWFFR register pointer to 0 */
- ETH_MAC->WUMR |= ETH_MAC_WUMR_WUFFRPR;
-}
-
-/**
- * @brief Set the remote wakeup frame registers.
- * @param pBuffer: Pointer to remote WakeUp Frame Filter Register buffer data (8 words).
- * @retval None
- */
-void ETH_SetWakeUpFrameFilterRegister(uint32_t *pBuffer)
-{
- uint32_t num = 0;
-
- /* Configuration ETH_MAC_RWFFR register */
- for (num = 0; num < ETH_WAKEUP_REGISTER_LENGTH; num++) {
- ETH_MAC->RWFFR = pBuffer[num];
- }
-}
-
-/**
- * @brief Enable or disable ETH_MAC_WUMR_GU control bit.
- * @param NewValue: new value of the MAC Global Unicast Wake-Up.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_GlobalUnicastWakeUp_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_MAC_WUMR_GU control bit */
- ETH_MAC->WUMR |= ETH_MAC_WUMR_GU;
- } else {
- /* Disable the ETH_MAC_WUMR_GU control bit */
- ETH_MAC->WUMR &= ~ETH_MAC_WUMR_GU;
- }
-}
-
-/**
- * @brief Get the bit flag of the WUM.
- * @param ETH_WUM_FLAG: the flag of ETH_MAC_WUMR register.
- * Select one of the follwing values :
- * @arg ETH_WUM_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
- * @arg ETH_WUM_FLAG_WUFR : Wake-Up Frame Received
- * @arg ETH_WUM_FLAG_MPKR : Magic Packet Received
- * @retval The current ETHERNET WUM Flag selected bit status(SET or RESET).
- */
-TypeState ETH_GetWUMBitState(uint32_t ETH_WUM_FLAG)
-{
- if ((ETH_MAC->WUMR & ETH_WUM_FLAG) != (uint32_t)RESET) {
- /* WUM Flag is set */
- return SET;
- } else {
- /* WUM Flag is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_MAC_WUMR_WFEN control bit.
- * @param NewValue: new value of the ETH_MAC_WUMR_WFEN bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_WakeUpFrameDetection_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Active the MAC Wake-Up Frame Detection */
- ETH_MAC->WUMR |= ETH_MAC_WUMR_WFEN;
- } else {
- /* Deactive the MAC Wake-Up Frame Detection */
- ETH_MAC->WUMR &= ~ETH_MAC_WUMR_WFEN;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_MAC_WUMR_MPEN control bit.
- * @param NewValue: new value of the ETH_MAC_WUMR_MPEN bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MagicPacketDetection_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_MAC_WUMR_MPEN control bit */
- ETH_MAC->WUMR |= ETH_MAC_WUMR_MPEN;
- } else {
- /* Disable the ETH_MAC_WUMR_MPEN control bit */
- ETH_MAC->WUMR &= ~ETH_MAC_WUMR_MPEN;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_MAC_WUMR_PWD control bit.
- * @param NewValue: new value of the ETH_MAC_WUMR_PWD bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_PowerDown_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_MAC_WUMR_PWD control bit */
- ETH_MAC->WUMR |= ETH_MAC_WUMR_PWD;
- } else {
- /* Disable the ETH_MAC_WUMR_PWD control bit */
- ETH_MAC->WUMR &= ~ETH_MAC_WUMR_PWD;
- }
-}
-
-/* MSC */
-/**
- * @brief Enable or disable the ETH_MSC_CTLR_MCFZ control bit.
- * @param NewValue: new value of the MSC Counter Freeze.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MSCCounterFreeze_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_MSC_CTLR_MCFZ control bit */
- ETH_MSC->CTLR |= ETH_MSC_CTLR_MCFZ;
- } else {
- /* Disable the ETH_MSC_CTLR_MCFZ control bit */
- ETH_MSC->CTLR &= ~ETH_MSC_CTLR_MCFZ;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_MSC_CTLR_RTOR control bit.
- * @param NewValue: new value of the MSC Reset On Read.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MSCResetOnRead_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_MSC_CTLR_RTOR control bit */
- ETH_MSC->CTLR |= ETH_MSC_CTLR_RTOR;
- } else {
- /* Disable the ETH_MSC_CTLR_RTOR control bit */
- ETH_MSC->CTLR &= ~ETH_MSC_CTLR_RTOR;
- }
-}
-
-/**
- * @brief Enable or disable the ETH_MSC_CTLR_CTSR control bit.
- * @param NewValue: new value of the ETH_MSC_CTLR_CTSR bit.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MSCCounterRollover_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_MSC_CTLR_CTSR control bit */
- ETH_MSC->CTLR &= ~ETH_MSC_CTLR_CTSR;
- } else {
- /* Disable the ETH_MSC_CTLR_CTSR control bit */
- ETH_MSC->CTLR |= ETH_MSC_CTLR_CTSR;
- }
-}
-
-/**
- * @brief Resets the MSC Counters.
- * @param None
- * @retval None
- */
-void ETH_MSCCountersReset(void)
-{
- ETH_MSC->CTLR |= ETH_MSC_CTLR_CTR;
-}
-
-/**
- * @brief Enable or disable the ETH_MSC_INT control bit.
- * @param ETH_MSC_INT: the MSC interrupt sources flag of MSC_RIMR and MSC_TIMR.
- * This parameter can be any combination of Tx interrupt or
- * any combination of Rx interrupt (but not both)of the following values:
- * @arg ETH_MSC_INT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MSC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MSC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @arg ETH_MSC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MSC_INT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MSC_INT_RFCE : When Rx crc error counter reaches half the maximum value
- * @param NewValue: new value of the MSC interrupt sources flag of MSC_RIMR and MSC_TIMR.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_MSCINTConfig(uint32_t ETH_MSC_INT, TypeState NewValue)
-{
- if ((ETH_MSC_INT & (uint32_t)0x10000000) != (uint32_t)RESET) {
- /* Get MSC interrupts souce bit position */
- ETH_MSC_INT &= 0xEFFFFFFF;
-
- /* MSC Rx interrupts souce bit selected */
- if (NewValue != DISABLE) {
- /* Enable the Rx ETH_MSC_INT control bit */
- ETH_MSC->RIMR &= (~(uint32_t)ETH_MSC_INT);
- } else {
- /* Disable the Rx ETH_MSC_INT control bit */
- ETH_MSC->RIMR |= ETH_MSC_INT;
- }
- } else {
- /* MSC Tx interrupts souce bit selected */
- if (NewValue != DISABLE) {
- /* Enable the Tx ETH_MSC_INT control bit */
- ETH_MSC->TIMR &= (~(uint32_t)ETH_MSC_INT);
- } else {
- /* Disable the Tx ETH_MSC_INT control bit */
- ETH_MSC->TIMR |= ETH_MSC_INT;
- }
- }
-}
-
-/**
- * @brief Get the bit flag of MSC INT.
- * @param ETH_MSC_INT: the MSC interrupt flag of ETH_MSC_RISR and ETH_MSC_TISR.
- * Select one of the follwing values :
- * @arg ETH_MSC_INT_TGF: When Tx good frame counter reaches half the maximum value
- * @arg ETH_MSC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MSC_INT_TGFSC: When Tx good single col counter reaches half the maximum value
- * @arg ETH_MSC_INT_RGUF: When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MSC_INT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MSC_INT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval The current ETHERNET MSC IT selected bit status(SET or RESET).
- */
-TypeState ETH_GetMSCINTStatus(uint32_t ETH_MSC_INT)
-{
- if ((ETH_MSC_INT & (uint32_t)0x10000000) != (uint32_t)RESET) {
- /* Check if the MSC interrupt flag of ETH_MSC_RISR selected is enabled and occured */
- if ((((ETH_MSC->RISR & ETH_MSC_INT) != (uint32_t)RESET)) && ((ETH_MSC->RIMR & ETH_MSC_INT) != (uint32_t)RESET)) {
- /* The MSC interrupt flag of ETH_MSC_RISR is set */
- return SET;
- } else {
- /* The MSC interrupt flag of ETH_MSC_RISR is reset */
- return RESET;
- }
- } else {
- /* Check if the MSC interrupt flag of ETH_MSC_TISR selected is enabled and occured */
- if ((((ETH_MSC->TISR & ETH_MSC_INT) != (uint32_t)RESET)) && ((ETH_MSC->RIMR & ETH_MSC_INT) != (uint32_t)RESET)) {
- /* The MSC interrupt flag of ETH_MSC_TISR is set */
- return SET;
- } else {
- /* The MSC interrupt flag of ETH_MSC_TISR is reset */
- return RESET;
- }
- }
-}
-
-/**
- * @brief Read value of the MSC module register.
- * @param ETH_MSC_Register: the MSC module register selected.
- * Select one of the follwing values :
- * @arg ETH_MSC_CTLR : MSC CR register
- * @arg ETH_MSC_RISR : MSC RIR register
- * @arg ETH_MSC_TISR : MSC TIR register
- * @arg ETH_MSC_RIMR : MSC RIMR register
- * @arg ETH_MSC_TIMR : MSC TIMR register
- * @arg ETH_MSC_SCCNT : MSC TGFSCCR register
- * @arg ETH_MSC_MSCCNT : MSC TGFMSCCR register
- * @arg ETH_MSC_TGFCNT : MSC TGFCR register
- * @arg ETH_MSC_RFCECNT : MSC RFCECR register
- * @arg ETH_MSC_RFAECNT : MSC RFAECR register
- * @arg ETH_MSC_RGUFCNT : MSC RGUFCRregister
- * @retval MSC module Register selected value.
- */
-uint32_t ETH_GetMSCRegister(uint32_t ETH_MSC_Register)
-{
- /* Return the value of MSC module Register selected */
- return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MSC_Register));
-}
-
-/* PTP */
-/**
- * @brief Updated the Time Stamp Addend register value to the PTP block(used only when the system time is configured
- * for Fine update mode).
- * @param None
- * @retval None
- */
-void ETH_PTPTimeStampAddendUpdate(void)
-{
- ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSARU;
-}
-
-/**
- * @brief Set ETH_PTP_TSCTLR_TMSITEN bit.
- * @param NewValue: new value of the MAC reception.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_PTPTimeStampIntTrigger_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable ETH_PTP_TSCTLR_TMSITEN bit */
- ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSITEN;
- } else {
- /* Disable ETH_PTP_TSCTLR_TMSITEN bit */
- ETH_PTP->TSCTLR &= ~ETH_PTP_TSCTLR_TMSITEN;
- }
-}
-
-/**
- * @brief Updated the Time Stamp Update register value to the PTP system time.
- * @param NewValue: new value of the MAC reception.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_PTPTimeStampUpdate_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable PTP time stamp update */
- ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSSTU;
- } else {
- /* Disable PTP time stamp update */
- ETH_PTP->TSCTLR &= ~ETH_PTP_TSCTLR_TMSSTU;
- }
-}
-
-/**
- * @brief Initialize the PTP Time Stamp mode
- * @param None
- * @retval None
- */
-void ETH_PTPTimeStampInit(void)
-{
- ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSSTI;
-}
-
-/**
- * @brief Set the PTP Time Stamp Update mode
- * @param UpdateMode: the PTP Update mode selected
- * Select one of the follwing values :
- * @arg ETH_PTP_FINEMODE : Fine Update method
- * @arg ETH_PTP_COARSEMODE : Coarse Update method
- * @retval None
- */
-void ETH_PTPUpdateModeConfig(uint32_t UpdateMode)
-{
- if (UpdateMode != ETH_PTP_COARSEMODE) {
- /* Enable the PTP Fine Update mode */
- ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSFCU;
- } else {
- /* Disable the PTP Coarse Update mode */
- ETH_PTP->TSCTLR &= (~(uint32_t)ETH_PTP_TSCTLR_TMSFCU);
- }
-}
-
-/**
- * @brief Enable or disable ETH_PTP_TSCTLR_TMSEN control bit.
- * @param NewValue: new value of the ETH_PTP_TSCTLR_TMSEN control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ETH_PTPTimeStamp_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the ETH_PTP_TSCTLR_TMSEN control bit */
- ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSEN;
- } else {
- /* Disable the ETH_PTP_TSCTLR_TMSEN control bit */
- ETH_PTP->TSCTLR &= (~(uint32_t)ETH_PTP_TSCTLR_TMSEN);
- }
-}
-
-/**
- * @brief Get the bit flag of ETHERNET PTP.
- * @param ETH_PTP_FLAG: the flag of PTP_TSCTLR register.
- * Select one of the follwing values :
- * @arg ETH_PTP_FLAG_TMSARU : Addend Register Update
- * @arg ETH_PTP_FLAG_TMSITEN : Time Stamp Interrupt Trigger Enable
- * @arg ETH_PTP_FLAG_TMSSTU : Time Stamp Update
- * @arg ETH_PTP_FLAG_TMSSTI : Time Stamp Initialize
- * @retval The current ETHERNET PTP Flag selected bit status(SET or RESET).
- */
-TypeState ETH_GetPTPBitState(uint32_t ETH_PTP_FLAG)
-{
- if ((ETH_PTP->TSCTLR & ETH_PTP_FLAG) != (uint32_t)RESET) {
- /* ETH_PTP_FLAG is set */
- return SET;
- } else {
- /* ETH_PTP_FLAG is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Set Each HCLK cycle the system time Sub-Second Increased value.
- * @param SubSecond: the PTP_SSINCR Register value.
- * @retval None
- */
-void ETH_SetPTPSubSecondIncrement(uint32_t SubSecond)
-{
- ETH_PTP->SSINCR = SubSecond;
-}
-
-/**
- * @brief Set the system time update sign and values.
- * @param Sign: the PTP Time update value sign(positive or negative).
- * Select one of the follwing values :
- * @arg ETH_PTP_POSITIVETIME : positive time value.
- * @arg ETH_PTP_NEGATIVETIME : negative time value.
- * @param Second: the PTP Time update value in second part.
- * @param SubSecond: the PTP Time update value in sub-second part.
- * This parameter is a 31 bit value, bit32 correspond to the sign.
- * @retval None
- */
-void ETH_SetPTPUpdateTimeValue(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
-{
- /* Set the PTP Time Update High Register with second value*/
- ETH_PTP->TMSHUR = SecondValue;
-
- /* Set the PTP Time Update Low Register with subsecond value and sign */
- ETH_PTP->TMSLUR = Sign | SubSecondValue;
-}
-
-/**
- * @brief Set the system time Addend value(used only when the system time is configured
- * for Fine update mode).
- * @param add: the PTP PTP_TSACNT Register value.
- * @retval None
- */
-void ETH_SetPTPTimeStampAddend(uint32_t add)
-{
- ETH_PTP->TSACNT = add;
-}
-
-/**
- * @brief Set the Target system Time values.
- * @param HighReg_Value: the PTP Expected Time High Register value.
- * @param LowReg_Value: the PTP Expected Time Low Register value.
- * @retval None
- */
-void ETH_SetPTPTargetTime(uint32_t HighReg_Value, uint32_t LowReg_Value)
-{
- /* Set the PTP Expected Time High Register */
- ETH_PTP->ETHR = HighReg_Value;
- /* Set the PTP Expected Time Low Register */
- ETH_PTP->ETLR = LowReg_Value;
-}
-
-/**
- * @brief Read the value of PTP module register .
- * @param ETH_PTPRegister: the PTP module register selected.
- * Select one of the follwing values :
- * @arg ETH_PTP_TSCTLR : Sub-Second Increment Register
- * @arg ETH_PTP_SSINCR : Sub-Second Increment Register
- * @arg ETH_PTP_TMSHR : Time Stamp High Register
- * @arg ETH_PTP_TMSLR : Time Stamp Low Register
- * @arg ETH_PTP_TMSHUR : Time Stamp High Update Register
- * @arg ETH_PTP_TMSLUR : Time Stamp Low Update Register
- * @arg ETH_PTP_TSACNT : Time Stamp Addend Register
- * @arg ETH_PTP_ETHR : Target Time High Register
- * @arg ETH_PTP_ETLR : Target Time Low Register
- * @retval ETHERNET PTP Register selected value.
- */
-uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPRegister)
-{
- return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPRegister));
-}
-
-/**
- * @brief Initialize the DMA Tx descriptors's parameters in chain mode with PTP.
- * @param DMATxDescTab: Pointer to the first Tx descriptor table
- * @param DMAPTPTxDescTab: Pointer to the first PTP Tx descriptor table
- * @param pTxBuff: Pointer to the first TxBuffer table
- * @param TxBuffCnt: the used Tx descriptor sum in the table
- * @retval None
- */
-void ETH_DMAPTPTxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,
- uint8_t *pTxBuff, uint32_t TxBuffCnt)
-{
- uint32_t num = 0;
- ETH_DMADESCTypeDef *DMATxDesc;
-
- DMACurrentTxDesc = DMATxDescTab;
- DMACurrentPTPTxDesc = DMAPTPTxDescTab;
- /* Configuration each DMATxDesc descriptor */
- for (num = 0; num < TxBuffCnt; num++) {
- /* Get the pointer to the next descriptor of the Tx Desc table */
- DMATxDesc = DMATxDescTab + num;
- /* Set TCH bit and enable PTP with desc status */
- DMATxDesc->Status = ETH_DMATXDESC_TCHM | ETH_DMATXDESC_TTSEN;
-
- /* Set Buffer1 address pointer to application buffer */
- DMATxDesc->Buffer1Addr = (uint32_t)(&pTxBuff[num * ETH_MAX_FRAME_SIZE]);
-
- if (num < (TxBuffCnt - 1)) {
- /* Buffer2NextDescAddr equal to next descriptor address in the Tx Desc table */
- DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + num + 1);
- } else {
- /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Tx Desc table */
- DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
- }
- /* Set DMAPTPTxDescTab equal to DMATxDescTab */
- (&DMAPTPTxDescTab[num])->Buffer1Addr = DMATxDesc->Buffer1Addr;
- (&DMAPTPTxDescTab[num])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
- }
- /* When it is the last PTPdescriptor, DMAPTPTxDesc status equal to the first descriptor address in the PTPTx Desc list address */
- (&DMAPTPTxDescTab[num - 1])->Status = (uint32_t) DMAPTPTxDescTab;
-
- ETH_DMA->TDTAR = (uint32_t) DMATxDescTab;
-}
-
-/**
- * @brief Initialize the DMA Rx descriptors's parameters in chain mode with PTP.
- * @param DMARxDescTab: Pointer to the first Rx descriptor table
- * @param DMAPTPRxDescTab: Pointer to the first PTP Rx descriptor table
- * @param pRxBuff: Pointer to the first RxBuffer table
- * @param RxBuffCnt: the used Rx descriptor sum in the table
- * @retval None
- */
-void ETH_DMAPTPRxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,
- uint8_t *pRxBuff, uint32_t RxBuffCnt)
-{
- uint32_t num = 0;
- ETH_DMADESCTypeDef *DMARxDesc;
-
- DMACurrentRxDesc = DMARxDescTab;
- DMACurrentPTPRxDesc = DMAPTPRxDescTab;
- /* Configuration each DMARxDesc descriptor */
- for (num = 0; num < RxBuffCnt; num++) {
- /* Get the pointer to the next descriptor of the Rx Desc table */
- DMARxDesc = DMARxDescTab + num;
- DMARxDesc->Status = ETH_DMARXDESC_BUSY;
-
- /* Set TCH bit and buffer1 size */
- DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCHM | (uint32_t)ETH_MAX_FRAME_SIZE;
- /* Set Buffer1 address pointer to application buffer */
- DMARxDesc->Buffer1Addr = (uint32_t)(&pRxBuff[num * ETH_MAX_FRAME_SIZE]);
-
- if (num < (RxBuffCnt - 1)) {
- /* Buffer2NextDescAddr equal to next descriptor address in the Rx Desc table */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + num + 1);
- } else {
- /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Rx Desc table */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
- }
- /* Set DMAPTPRxDescTab equal to DMARxDescTab */
- (&DMAPTPRxDescTab[num])->Buffer1Addr = DMARxDesc->Buffer1Addr;
- (&DMAPTPRxDescTab[num])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
- }
- /* When it is the last PTPdescriptor, DMAPTPRxDesc status equal to the first descriptor address in the PTPRx Desc table address */
- (&DMAPTPRxDescTab[num - 1])->Status = (uint32_t) DMAPTPRxDescTab;
-
- /* Update Receive Desciptor Table Address Register */
- ETH_DMA->RDTAR = (uint32_t) DMARxDescTab;
-}
-
-/**
- * @brief Send data with Time Stamp values of application buffer as a transmit packet.
- * @param pbuf: pointer to the applicationbuffer.
- * @param size: the application buffer size.
- * @param PTPTxTab: Pointer to the first PTP Tx table to store Time stamp values.
- * @retval The transmission with PTP result(ERROR or SUCCESS)
- */
-uint32_t ETH_HandlePTPTxPkt(uint8_t *pbuf, uint16_t size, uint32_t *PTPTxTab)
-{
- uint32_t offset = 0, timeout = 0;
-
- if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_BUSY) != (uint32_t)RESET) {
- /* Return ERROR: the descriptor is busy due to own by the DMA */
- return ERROR;
- }
- for (offset = 0; offset < size; offset++) {
- (*(__IO uint8_t *)((DMACurrentPTPTxDesc->Buffer1Addr) + offset)) = (*(pbuf + offset));
- }
- /* Setting the Frame Length */
- DMACurrentTxDesc->ControlBufferSize = (size & (uint32_t)0x1FFF);
- /* Setting the segment of frame (ETH_DMATXDESC_LSG and ETH_DMATXDESC_FSG are SET that frame is transmitted in one descriptor) */
- DMACurrentTxDesc->Status |= ETH_DMATXDESC_LSG | ETH_DMATXDESC_FSG;
- /* Enable the DMA transmission */
- DMACurrentTxDesc->Status |= ETH_DMATXDESC_BUSY;
- /* Check Tx Buffer unavailable flag status */
- if ((ETH_DMA->STR & ETH_DMA_STR_TBU) != (uint32_t)RESET) {
- /* Clear TBU ETHERNET DMA flag */
- ETH_DMA->STR = ETH_DMA_STR_TBU;
- /* Resume DMA transmission by writing to the TPER register*/
- ETH_DMA->TPER = 0;
- }
- /* Wait for ETH_DMATXDESC_TTMSS flag to be set unless timeout */
- do {
- timeout++;
- } while (!(DMACurrentTxDesc->Status & ETH_DMATXDESC_TTMSS) && (timeout < 0xFFFF));
- /* Return ERROR due to timeout */
- if (timeout == PHY_READ_TO) {
- return ERROR;
- }
- /* Clear the DMACurrentTxDesc status register TTSS flag */
- DMACurrentTxDesc->Status &= ~ETH_DMATXDESC_TTMSS;
- *PTPTxTab++ = DMACurrentTxDesc->Buffer1Addr;
- *PTPTxTab = DMACurrentTxDesc->Buffer2NextDescAddr;
- /* Update the ETHERNET DMA current Tx descriptor pointer to the next Tx decriptor in DMA Tx decriptor talbe*/
- /* Chained Mode */
- if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TCHM) != (uint32_t)RESET) {
- DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPTxDesc->Buffer2NextDescAddr);
- if (DMACurrentPTPTxDesc->Status != 0) {
- DMACurrentPTPTxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPTxDesc->Status);
- } else {
- DMACurrentPTPTxDesc++;
- }
- }
- /* Ring Mode */
- else {
- if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TERM) != (uint32_t)RESET) {
- DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->TDTAR);
- DMACurrentPTPTxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->TDTAR);
- } else {
- DMACurrentTxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentTxDesc + ETH_DMATXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2));
- DMACurrentPTPTxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentPTPTxDesc + ETH_DMATXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2));
- }
- }
- return SUCCESS;
-}
-
-/**
- * @brief Receive a packet data with Time Stamp values to application buffer.
- * @param pbuf: Pointer on the application buffer.
- * @param PTPRxTab: Pointer to the first PTP Rx table to store Time stamp values.
- * @retval The Receive frame length with PTP(If size is equal to ERROR, the receiving unsuccessful)
- */
-uint32_t ETH_HandlePTPRxPkt(uint8_t *pbuf, uint32_t *PTPRxTab)
-{
- uint32_t offset = 0, size = 0;
-
- if ((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) != (uint32_t)RESET) {
- /* Return ERROR: the descriptor is busy due to own by the DMA */
- return ERROR;
- }
- if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) &&
- ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) {
- /* Get the Frame Length exclusive CRC */
- size = ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FRML) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
- for (offset = 0; offset < size; offset++) {
- (*(pbuf + offset)) = (*(__IO uint8_t *)((DMACurrentPTPRxDesc->Buffer1Addr) + offset));
- }
- } else {
- /* Return ERROR */
- size = ERROR;
- }
- /* Check Rx Buffer unavailable flag status */
- if ((ETH_DMA->STR & ETH_DMA_STR_RBU) != (uint32_t)RESET) {
- /* Clear RBU ETHERNET DMA flag */
- ETH_DMA->STR = ETH_DMA_STR_RBU;
- /* Resume DMA reception by writing to the RPER register*/
- ETH_DMA->RPER = 0;
- }
- *PTPRxTab++ = DMACurrentRxDesc->Buffer1Addr;
- *PTPRxTab = DMACurrentRxDesc->Buffer2NextDescAddr;
- /* Enable reception */
- DMACurrentRxDesc->Status |= ETH_DMARXDESC_BUSY;
- /* Update the ETHERNET DMA current Rx descriptor pointer to the next Rx decriptor in DMA Rx decriptor talbe*/
- /* Chained Mode */
- if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RCHM) != (uint32_t)RESET) {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPRxDesc->Buffer2NextDescAddr);
- if (DMACurrentPTPRxDesc->Status != 0) {
- DMACurrentPTPRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPRxDesc->Status);
- } else {
- DMACurrentPTPRxDesc++;
- }
- }
- /* Ring Mode */
- else {
- if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RERR) != (uint32_t)RESET) {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->RDTAR);
- } else {
- DMACurrentRxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentRxDesc + ETH_DMARXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2));
- }
- }
- /* Return Frame size or ERROR */
- return (size);
-}
-
-#ifndef USE_Delay
-/**
- * @brief Insert a delay time.
- * @param nCount: specifies the delay time length.
- * @retval None
- */
-static void ETH_Delay(__IO uint32_t nCount)
-{
- __IO uint32_t time = 0;
-
- for (time = nCount; time != 0; time--) {
- }
-}
-#endif /* USE_Delay */
-#endif /* GD32F10X_CL */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exmc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exmc.c
deleted file mode 100644
index b0a93ff71a..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exmc.c
+++ /dev/null
@@ -1,758 +0,0 @@
-/**
- ******************************************************************************
- * @brief EXMC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_exmc.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup EXMC
- * @brief EXMC driver modules
- * @{
- */
-
-/** @defgroup EXMC_Private_Defines
- * @{
- */
-
-/* EXMC Bank1 SCTLRx_BAKEN and SCTLRx_NORAEN Mask */
-#define SCTLR_BAKEN_SET ((uint32_t)0x00000001)
-#define SCTLR_BAKEN_RESET ((uint32_t)0x000FFFFE)
-
-/* EXMC Bank1 SCTLRx_NOREN Mask */
-#define SCTLR_NOREN_SET ((uint32_t)0x00000040)
-
-
-/* EXMC Bank2/3/4 CTLRx_BAKEN Mask */
-#define CTLR_BAKEN_SET ((uint32_t)0x00000004)
-#define CTLR_BAKEN_RESET ((uint32_t)0x000FFFFB)
-
-/* EXMC Bank2/3/4 CTLRx_ECCEN Mask */
-#define CTLR_ECCEN_SET ((uint32_t)0x00000040)
-#define CTLR_ECCEN_RESET ((uint32_t)0x000FFFBF)
-
-/* EXMC Bank2/3/4 CTLRx_MTYPE Mask */
-#define CTLR_EMTYP_NAND ((uint32_t)0x00000008)
-
-/* EXMC Bank1 Register Reset mask*/
-#define BANK1_SCTLR1_RESET ((uint32_t)0x000030DB)
-#define BANK1_SCTLR_RESET ((uint32_t)0x000030D2)
-#define BANK1_STR_RESET ((uint32_t)0x0FFFFFFF)
-#define BANK1_SWTR_RESET ((uint32_t)0x0FFFFFFF)
-
-/* EXMC Bank2/3 Register Reset mask*/
-#define BANK2_3_CTLR_RESET ((uint32_t)0x00000018)
-#define BANK2_3_SIR_RESET ((uint32_t)0x00000040)
-#define BANK2_3_COMTR_RESET ((uint32_t)0xFCFCFCFC)
-#define BANK2_3_ATTR_RESET ((uint32_t)0xFCFCFCFC)
-
-/* EXMC Bank4 Register Reset mask*/
-#define BANK4_CTLR_RESET ((uint32_t)0x00000018)
-#define BANK4_SIR_RESET ((uint32_t)0x00000000)
-#define BANK4_COMTR_RESET ((uint32_t)0xFCFCFCFC)
-#define BANK4_ATTR_RESET ((uint32_t)0xFCFCFCFC)
-#define BANK4_IOTR_RESET ((uint32_t)0xFCFCFCFC)
-
-/* EXMC register bit offset */
-#define STR_AHT_OFFSET ((uint32_t)0x00000004)
-#define STR_DST_OFFSET ((uint32_t)0x00000008)
-#define STR_BUSLAT_OFFSET ((uint32_t)0x00000010)
-#define STR_CDIV_OFFSET ((uint32_t)0x00000014)
-#define STR_DLAT_OFFSET ((uint32_t)0x00000018)
-
-#define SWTR_AHT_OFFSET ((uint32_t)0x00000004)
-#define SWTR_DST_OFFSET ((uint32_t)0x00000008)
-#define SWTR_CDIV_OFFSET ((uint32_t)0x00000014)
-#define SWTR_DLAT_OFFSET ((uint32_t)0x00000018)
-
-#define CTLR_CTR_OFFSET ((uint32_t)0x00000009)
-#define CTLR_ATR_OFFSET ((uint32_t)0x0000000D)
-
-#define COMTR_COMWT_OFFSET ((uint32_t)0x00000008)
-#define COMTR_COMHT_OFFSET ((uint32_t)0x00000010)
-#define COMTR_COMHIZT_OFFSET ((uint32_t)0x00000018)
-
-#define ATTR_ATTWT_OFFSET ((uint32_t)0x00000008)
-#define ATTR_ATTHT_OFFSET ((uint32_t)0x00000010)
-#define ATTR_ATTHIZT_OFFSET ((uint32_t)0x00000018)
-
-#define IOTR_IOTWT_OFFSET ((uint32_t)0x00000008)
-#define IOTR_IOHT_OFFSET ((uint32_t)0x00000010)
-#define IOTR_IOHIZT_OFFSET ((uint32_t)0x00000018)
-
-#define SIR_INTEN_OFFSET ((uint32_t)0x00000003)
-
-/**
- * @}
- */
-
-/** @defgroup EXMC_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the Bank1 NOR/SRAM registers.
- * @param EXMC_NORSRAMBank: specifies the Region of Bank1.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK1_NORSRAM1: the Region1 of Bank1
- * @arg EXMC_BANK1_NORSRAM2: the Region2 of Bank1
- * @arg EXMC_BANK1_NORSRAM3: the Region3 of Bank1
- * @arg EXMC_BANK1_NORSRAM4: the Region4 of Bank1
- * @retval None
- */
-void EXMC_NORSRAM_DeInit(uint32_t EXMC_NORSRAMBank)
-{
- switch (EXMC_NORSRAMBank) {
- case EXMC_BANK1_NORSRAM1: {
- /* the Region1 of Bank1 */
- EXMC_BANK1->SCTLR1 = BANK1_SCTLR1_RESET;
- EXMC_BANK1->STR1 = BANK1_STR_RESET;
- EXMC_BANK1_WT->SWTR1 = BANK1_SWTR_RESET;
- break;
- }
- case EXMC_BANK1_NORSRAM2: {
- /* the Region2 of Bank1 */
- EXMC_BANK1->SCTLR2 = BANK1_SCTLR_RESET;
- EXMC_BANK1->STR2 = BANK1_STR_RESET;
- EXMC_BANK1_WT->SWTR2 = BANK1_SWTR_RESET;
- break;
- }
- case EXMC_BANK1_NORSRAM3: {
- /* the Region3 of Bank1 */
- EXMC_BANK1->SCTLR3 = BANK1_SCTLR_RESET;
- EXMC_BANK1->STR3 = BANK1_STR_RESET;
- EXMC_BANK1_WT->SWTR3 = BANK1_SWTR_RESET;
- break;
- }
- case EXMC_BANK1_NORSRAM4: {
- /* the Region4 of Bank1 */
- EXMC_BANK1->SCTLR4 = BANK1_SCTLR_RESET;
- EXMC_BANK1->STR4 = BANK1_STR_RESET;
- EXMC_BANK1_WT->SWTR4 = BANK1_SWTR_RESET;
- break;
- }
- default:
- break;
- }
-}
-
-/**
- * @brief Reset the Bank2 or Bank3 NAND registers.
- * @param EXMC_NANDBank: specifies the Bank2 or Bank3 to be used.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: Bank2
- * @arg EXMC_BANK3_NAND: Bank3
- * @retval None
- */
-void EXMC_NAND_DeInit(uint32_t EXMC_NANDBank)
-{
- if (EXMC_NANDBank == EXMC_BANK2_NAND) {
- /* Reset the Bank2 NAND registers */
- EXMC_BANK2->CTLR2 = BANK2_3_CTLR_RESET;
- EXMC_BANK2->SIR2 = BANK2_3_SIR_RESET;
- EXMC_BANK2->COMTR2 = BANK2_3_COMTR_RESET;
- EXMC_BANK2->ATTR2 = BANK2_3_ATTR_RESET;
- }
- /* EXMC_Bank3_NAND */
- else {
- /* Reset the Bank3 NAND registers */
- EXMC_BANK3->CTLR3 = BANK2_3_CTLR_RESET;
- EXMC_BANK3->SIR3 = BANK2_3_SIR_RESET;
- EXMC_BANK3->COMTR3 = BANK2_3_COMTR_RESET;
- EXMC_BANK3->ATTR3 = BANK2_3_ATTR_RESET;
- }
-}
-
-/**
- * @brief Reset the Bank4 PCCARD registers.
- * @param None
- * @retval None
- */
-void EXMC_PCCARD_DeInit(void)
-{
- /* Reset EXMC Bank4 PCCARD registers */
- EXMC_BANK4->CTLR4 = BANK4_CTLR_RESET;
- EXMC_BANK4->SIR4 = BANK4_SIR_RESET;
- EXMC_BANK4->COMTR4 = BANK4_COMTR_RESET;
- EXMC_BANK4->ATTR4 = BANK4_ATTR_RESET;
- EXMC_BANK4->IOTR4 = BANK4_IOTR_RESET;
-}
-
-/**
- * @brief Initializes the EXMC Bank1 NOR/SRAM parameters.
- * @param EXMC_NORSRAMInitParaStruct : the struct EXMC_NORSRAMInitPara pointer
- * @retval None
- */
-void EXMC_NORSRAM_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct)
-{
- uint32_t temp_SCTLR = 0x00000000, temp_STR = 0x00000000, temp_SWTR = 0x00000000;
-
- temp_SCTLR = (uint32_t)EXMC_NORSRAMInitParaStruct->EXMC_AddressDataMux |
- EXMC_NORSRAMInitParaStruct->EXMC_MemoryType |
- EXMC_NORSRAMInitParaStruct->EXMC_DatabusWidth |
- EXMC_NORSRAMInitParaStruct->EXMC_BurstMode |
- EXMC_NORSRAMInitParaStruct->EXMC_NWAITPolarity |
- EXMC_NORSRAMInitParaStruct->EXMC_WrapBurstMode |
- EXMC_NORSRAMInitParaStruct->EXMC_NWAITConfig |
- EXMC_NORSRAMInitParaStruct->EXMC_MemoryWrite |
- EXMC_NORSRAMInitParaStruct->EXMC_NWAITSignal |
- EXMC_NORSRAMInitParaStruct->EXMC_ExtendedMode |
- EXMC_NORSRAMInitParaStruct->EXMC_AsynWait |
- EXMC_NORSRAMInitParaStruct->EXMC_WriteMode;
-
- temp_STR = (uint32_t)EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressSetupTime |
- (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressHoldTime << STR_AHT_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynDataSetupTime << STR_DST_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_BusLatency << STR_BUSLAT_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynCLKDivision << STR_CDIV_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynDataLatency << STR_DLAT_OFFSET) |
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAccessMode;
-
- if (EXMC_NORSRAMInitParaStruct->EXMC_MemoryType == EXMC_MEMORY_TYPE_NOR) {
- temp_SCTLR |= (uint32_t)SCTLR_NOREN_SET;
- }
-
- if (EXMC_NORSRAMInitParaStruct->EXMC_ExtendedMode == EXMC_EXTENDED_MODE_ENABLE) {
- temp_SWTR = (uint32_t)EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressSetupTime |
- (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressHoldTime << SWTR_AHT_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynDataSetupTime << SWTR_DST_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynCLKDivision << SWTR_CDIV_OFFSET) |
- (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynDataLatency << SWTR_DLAT_OFFSET) |
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAccessMode;
- } else {
- temp_SWTR = BANK1_SWTR_RESET;
- }
-
- switch (EXMC_NORSRAMInitParaStruct->EXMC_NORSRAMBank) {
- case EXMC_BANK1_NORSRAM1: {
- /* Bank1 NOR/SRAM Region1 registers configuration */
- EXMC_BANK1->SCTLR1 = temp_SCTLR;
- EXMC_BANK1->STR1 = temp_STR;
- EXMC_BANK1_WT->SWTR1 = temp_SWTR;
- break;
- }
- case EXMC_BANK1_NORSRAM2: {
- /* Bank1 NOR/SRAM Region2 registers configuration */
- EXMC_BANK1->SCTLR2 = temp_SCTLR;
- EXMC_BANK1->STR2 = temp_STR;
- EXMC_BANK1_WT->SWTR2 = temp_SWTR;
- break;
- }
- case EXMC_BANK1_NORSRAM3: {
- /* Bank1 NOR/SRAM Region3 registers configuration */
- EXMC_BANK1->SCTLR3 = temp_SCTLR;
- EXMC_BANK1->STR3 = temp_STR;
- EXMC_BANK1_WT->SWTR3 = temp_SWTR;
- break;
- }
- case EXMC_BANK1_NORSRAM4: {
- /* Bank1 NOR/SRAM Region4 registers configuration */
- EXMC_BANK1->SCTLR4 = temp_SCTLR;
- EXMC_BANK1->STR4 = temp_STR;
- EXMC_BANK1_WT->SWTR4 = temp_SWTR;
- break;
- }
- default:
- break;
- }
-}
-
-/**
- * @brief Initialize the EXMC Bank2 or Bank3 NAND parameters.
- * @param EXMC_NANDInitParaStruct : the struct EXMC_NANDInitPara pointer
- * @retval None
- */
-
-void EXMC_NAND_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct)
-{
- uint32_t temp_CTLR = 0x00000000, temp_COMTR = 0x00000000, temp_ATTR = 0x00000000;
-
- temp_CTLR = (uint32_t)EXMC_NANDInitParaStruct->EXMC_WaitFeature |
- CTLR_EMTYP_NAND |
- EXMC_NANDInitParaStruct->EXMC_DatabusWidth |
- EXMC_NANDInitParaStruct->EXMC_ECCLogic |
- EXMC_NANDInitParaStruct->EXMC_ECCSize |
- (EXMC_NANDInitParaStruct->EXMC_CTRLatency << CTLR_CTR_OFFSET) |
- (EXMC_NANDInitParaStruct->EXMC_ATRLatency << CTLR_ATR_OFFSET);
-
- temp_COMTR = (uint32_t)EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime |
- (EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime << COMTR_COMWT_OFFSET) |
- (EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime << COMTR_COMHT_OFFSET) |
- (EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime << COMTR_COMHIZT_OFFSET);
-
- temp_ATTR = (uint32_t)EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime |
- (EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime << ATTR_ATTWT_OFFSET) |
- (EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime << ATTR_ATTHT_OFFSET) |
- (EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime << ATTR_ATTHIZT_OFFSET);
-
- if (EXMC_NANDInitParaStruct->EXMC_NANDBank == EXMC_BANK2_NAND) {
- /* Configure the EXMC_Bank2 NAND registers using the value of parameters */
- EXMC_BANK2->CTLR2 = temp_CTLR;
- EXMC_BANK2->COMTR2 = temp_COMTR;
- EXMC_BANK2->ATTR2 = temp_ATTR;
- } else {
- /* EXMC_Bank3_NAND registers configuration */
- EXMC_BANK3->CTLR3 = temp_CTLR;
- EXMC_BANK3->COMTR3 = temp_COMTR;
- EXMC_BANK3->ATTR3 = temp_ATTR;
- }
-}
-
-/**
- * @brief Initialize the EXMC Bank4 PCCARD parameters.
- * @param EXMC_PCCARDInitParaStruct : the struct EXMC_PCCARDInitPara pointer.
- * @retval None
- */
-void EXMC_PCCARD_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct)
-{
- /* Configure the EXMC_Bank4_PCCARD CTLR4 register using the value of parameters */
- EXMC_BANK4->CTLR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_WaitFeature |
- EXMC_DATABUS_WIDTH_16B |
- (EXMC_PCCARDInitParaStruct->EXMC_CTRLatency << CTLR_CTR_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_ATRLatency << CTLR_ATR_OFFSET);
-
- /* Configure the EXMC_Bank4_PCCARD COMTR4 register using the value of parameters */
- EXMC_BANK4->COMTR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime |
- (EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime << COMTR_COMWT_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime << COMTR_COMHT_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime << COMTR_COMHIZT_OFFSET);
-
- /* Configure the EXMC_Bank4_PCCARD ATTR4 register using the value of parameters */
- EXMC_BANK4->ATTR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime |
- (EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime << ATTR_ATTWT_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime << ATTR_ATTHT_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime << ATTR_ATTHIZT_OFFSET);
-
- /* Configure the EXMC_Bank4_PCCARD IOTR4 register using the value of parameters */
- EXMC_BANK4->IOTR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_SetupTime |
- (EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_WaitTime << IOTR_IOTWT_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_HoldTime << IOTR_IOHT_OFFSET) |
- (EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_DatabusHiZTime << IOTR_IOHIZT_OFFSET);
-}
-
-/**
- * @brief Initialize the struct EXMC_NORSRAMInitPara
- * @param EXMC_NORSRAMInitParaStruct: the struct EXMC_NORSRAMInitPara pointer
- * @retval None
- */
-void EXMC_NORSRAMStruct_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct)
-{
- EXMC_NORSRAMInitParaStruct->EXMC_NORSRAMBank = EXMC_BANK1_NORSRAM1;
- EXMC_NORSRAMInitParaStruct->EXMC_AddressDataMux = EXMC_ADDRESS_DATA_MUX_ENABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_MemoryType = EXMC_MEMORY_TYPE_SRAM;
- EXMC_NORSRAMInitParaStruct->EXMC_DatabusWidth = EXMC_DATABUS_WIDTH_8B;
- EXMC_NORSRAMInitParaStruct->EXMC_BurstMode = EXMC_BURST_MODE_DISABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_NWAITPolarity = EXMC_NWAIT_POLARITY_LOW;
- EXMC_NORSRAMInitParaStruct->EXMC_WrapBurstMode = EXMC_WRAP_BURST_MODE_DISABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_NWAITConfig = EXMC_NWAIT_CONFIG_BEFORE;
- EXMC_NORSRAMInitParaStruct->EXMC_MemoryWrite = EXMC_MEMORY_WRITE_ENABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_NWAITSignal = EXMC_NWAIT_SIGNAL_ENABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_ExtendedMode = EXMC_EXTENDED_MODE_DISABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_AsynWait = EXMC_ASYN_WAIT_DISABLE;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteMode = EXMC_ASYN_WRITE;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressSetupTime = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressHoldTime = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynDataSetupTime = 0xFF;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_BusLatency = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynCLKDivision = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynDataLatency = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAccessMode = EXMC_ACCESS_MODE_A;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressSetupTime = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressHoldTime = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynDataSetupTime = 0xFF;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_BusLatency = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynCLKDivision = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynDataLatency = 0xF;
- EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAccessMode = EXMC_ACCESS_MODE_A;
-}
-
-/**
- * @brief Initialize the struct EXMC_NANDInitPara
- * @param EXMC_NANDInitParaStruct: the struct EXMC_NANDInitPara pointer.
- * @retval None
- */
-void EXMC_NANDStruct_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct)
-{
- EXMC_NANDInitParaStruct->EXMC_NANDBank = EXMC_BANK2_NAND;
- EXMC_NANDInitParaStruct->EXMC_WaitFeature = EXMC_WAIT_FEATURE_DISABLE;
- EXMC_NANDInitParaStruct->EXMC_DatabusWidth = EXMC_DATABUS_WIDTH_8B;
- EXMC_NANDInitParaStruct->EXMC_ECCLogic = EXMC_ECC_LOGIC_DISABLE;
- EXMC_NANDInitParaStruct->EXMC_ECCSize = EXMC_ECC_SIZE_256BYTES;
- EXMC_NANDInitParaStruct->EXMC_CTRLatency = 0x0;
- EXMC_NANDInitParaStruct->EXMC_ATRLatency = 0x0;
- EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime = 0xFC;
- EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC;
-}
-
-/**
- * @brief Initialize the struct EXMC_PCCARDInitParaStruct
- * @param EXMC_PCCARDInitPara: the struct EXMC_PCCARDInitParaStruct pointer.
- * @retval None
- */
-void EXMC_PCCARDStruct_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct)
-{
- EXMC_PCCARDInitParaStruct->EXMC_WaitFeature = EXMC_WAIT_FEATURE_DISABLE;
- EXMC_PCCARDInitParaStruct->EXMC_CTRLatency = 0x0;
- EXMC_PCCARDInitParaStruct->EXMC_ATRLatency = 0x0;
- EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_SetupTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_WaitTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_HoldTime = 0xFC;
- EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC;
-}
-
-/**
- * @brief Enable or disable the specified Region of Bank1.
- * @param EXMC_NORSRAMBank: specifies the Region of Bank1.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK1_NORSRAM1: the Region1 of Bank1
- * @arg EXMC_BANK1_NORSRAM2: the Region2 of Bank1
- * @arg EXMC_BANK1_NORSRAM3: the Region3 of Bank1
- * @arg EXMC_BANK1_NORSRAM4: the Region4 of Bank1
- * @param NewValue: new value of the specified Region of Bank1.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void EXMC_NORSRAM_Enable(uint32_t EXMC_NORSRAMBank, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- switch (EXMC_NORSRAMBank) {
- case EXMC_BANK1_NORSRAM1:
- EXMC_BANK1->SCTLR1 |= SCTLR_BAKEN_SET;
- break;
- case EXMC_BANK1_NORSRAM2:
- EXMC_BANK1->SCTLR2 |= SCTLR_BAKEN_SET;
- break;
- case EXMC_BANK1_NORSRAM3:
- EXMC_BANK1->SCTLR3 |= SCTLR_BAKEN_SET;
- break;
- case EXMC_BANK1_NORSRAM4:
- EXMC_BANK1->SCTLR4 |= SCTLR_BAKEN_SET;
- break;
- default:
- break;
- }
- } else {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- switch (EXMC_NORSRAMBank) {
- case EXMC_BANK1_NORSRAM1:
- EXMC_BANK1->SCTLR1 &= SCTLR_BAKEN_RESET;
- break;
- case EXMC_BANK1_NORSRAM2:
- EXMC_BANK1->SCTLR2 &= SCTLR_BAKEN_RESET;
- break;
- case EXMC_BANK1_NORSRAM3:
- EXMC_BANK1->SCTLR3 &= SCTLR_BAKEN_RESET;
- break;
- case EXMC_BANK1_NORSRAM4:
- EXMC_BANK1->SCTLR4 &= SCTLR_BAKEN_RESET;
- break;
- default:
- break;
- }
- }
-}
-
-/**
- * @brief Enable or disable the specified NAND Bank2 or Bank3.
- * @param EXMC_NANDBank: specifies the NAND Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @param NewValue: new value of the specified Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void EXMC_NAND_Enable(uint32_t EXMC_NANDBank, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if (EXMC_NANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->CTLR2 |= CTLR_BAKEN_SET;
- } else {
- EXMC_BANK3->CTLR3 |= CTLR_BAKEN_SET;
- }
- } else {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if (EXMC_NANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->CTLR2 &= CTLR_BAKEN_RESET;
- } else {
- EXMC_BANK3->CTLR3 &= CTLR_BAKEN_RESET;
- }
- }
-}
-
-/**
- * @brief Enable or disable the Bank4 of PCCARD.
- * @param NewValue: new value of the PCCARD Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void EXMC_PCCARD_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the PCCARD Bank */
- EXMC_BANK4->CTLR4 |= CTLR_BAKEN_SET;
- } else {
- /* Disable the PCCARD Bank */
- EXMC_BANK4->CTLR4 &= CTLR_BAKEN_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the EXMC_CTLR1_ECCEN control bit.
- * @param EXMC_NANDBank: specifies the NAND Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @param NewValue: new value of the EXMC Bank2 or Bank3 ECC calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void EXMC_NANDECC_Enable(uint32_t EXMC_NANDBank, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if (EXMC_NANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->CTLR2 |= CTLR_ECCEN_SET;
- } else {
- EXMC_BANK3->CTLR3 |= CTLR_ECCEN_SET;
- }
- } else {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if (EXMC_NANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->CTLR2 &= CTLR_ECCEN_RESET;
- } else {
- EXMC_BANK3->CTLR3 &= CTLR_ECCEN_RESET;
- }
- }
-}
-
-/**
- * @brief Get the EXMC_ECCR value.
- * @param EXMC_NANDBank: specifies the NAND Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @retval The Error Correction Code (ECC) value.
- */
-uint32_t EXMC_GetECC(uint32_t EXMC_NANDBank)
-{
- if (EXMC_NANDBank == EXMC_BANK2_NAND) {
- return (EXMC_BANK2->ECCR2);
- } else {
- return (EXMC_BANK3->ECCR3);
- }
-}
-
-/**
- * @brief Enable or disable the specified EXMC Bank2/3/4 interrupts.
- * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4
- * @param EXMC_INT: the EXMC interrupt sources.
- * This parameter can be any combination of the following values:
- * @arg EXMC_INT_RISE: Rising edge detection interrupt
- * @arg EXMC_INT_LEVEL: Level edge detection interrupt
- * @arg EXMC_INT_FALL: Falling edge detection interrupt
- * @param NewValue: new value of the specified EXMC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void EXMC_INTConfig(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the specified EXMC_Bank2 interrupts */
- if (EXMC_PCNANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->SIR2 |= EXMC_INT;
- }
- /* Enable the specified EXMC_Bank3 interrupts */
- else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) {
- EXMC_BANK3->SIR3 |= EXMC_INT;
- }
- /* Enable the specified EXMC_Bank4 interrupts */
- else {
- EXMC_BANK4->SIR4 |= EXMC_INT;
- }
- } else {
- /* Disable the specified EXMC_Bank2 interrupts */
- if (EXMC_PCNANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->SIR2 &= ~((uint32_t)EXMC_INT);
- }
- /* Disable the specified EXMC_Bank3 interrupts */
- else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) {
- EXMC_BANK3->SIR3 &= ~((uint32_t)EXMC_INT);
- }
- /* Disable the specified EXMC_Bank4 interrupts */
- else {
- EXMC_BANK4->SIR4 &= ~((uint32_t)EXMC_INT);
- }
- }
-}
-
-/**
- * @brief Get the bit flag of EXMC_SIRx register.
- * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4
- * @param EXMC_FLAG: the flag of EXMC_SIRx register.
- * This parameter can be one of the following values:
- * @arg EXMC_FLAG_RISE: Rising egde detection Flag
- * @arg EXMC_FLAG_LEVEL: Level detection Flag
- * @arg EXMC_FLAG_FALL: Falling egde detection Flag
- * @arg EXMC_FLAG_FIFOE: FIFO empty Flag
- * @retval The new value of EXMC_FLAG (SET or RESET).
- */
-TypeState EXMC_GetBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG)
-{
- uint32_t temp_SIR = 0x00000000;
- /* the NAND Bank2 */
- if (EXMC_PCNANDBank == EXMC_BANK2_NAND) {
- temp_SIR = EXMC_BANK2->SIR2;
- }
- /* the NAND Bank3 */
- else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) {
- temp_SIR = EXMC_BANK3->SIR3;
- }
- /* the PCCARD Bank4 */
- else {
- temp_SIR = EXMC_BANK4->SIR4;
- }
-
- if ((temp_SIR & EXMC_FLAG) != (uint16_t)RESET) {
- /* EXMC_FLAG is set */
- return SET;
- } else {
- /* EXMC_FLAG is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the bit flag of EXMC_SIRx register.
- * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4
- * @param EXMC_FLAG: the flag of EXMC_SIRx register.
- * This parameter can be any combination of the following values:
- * @arg EXMC_FLAG_RISE: Rising egde detection Flag
- * @arg EXMC_FLAG_LEVEL: Level detection Flag
- * @arg EXMC_FLAG_FALL: Falling egde detection Flag
- * @retval None
- */
-void EXMC_ClearBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG)
-{
- if (EXMC_PCNANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->SIR2 &= ~EXMC_FLAG;
- } else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) {
- EXMC_BANK3->SIR3 &= ~EXMC_FLAG;
- }
- /* EXMC_Bank4_PCCARD*/
- else {
- EXMC_BANK4->SIR4 &= ~EXMC_FLAG;
- }
-}
-
-/**
- * @brief Get the interrupt bit flag.
- * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4
- * @param EXMC_INT: the interrupt bit flag.
- * This parameter can be one of the following values:
- * @arg EXMC_INT_RISE: Rising edge detection interrupt
- * @arg EXMC_INT_LEVEL: Level edge detection interrupt
- * @arg EXMC_INT_FALL: Falling edge detection interrupt
- * @retval The new value of EXMC_INT (SET or RESET).
- */
-TypeState EXMC_GetIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT)
-{
- uint32_t temp_SIR = 0x00000000, temp_INTState = 0x00000000, temp_INTEnable = 0x00000000;
-
- if (EXMC_PCNANDBank == EXMC_BANK2_NAND) {
- temp_SIR = EXMC_BANK2->SIR2;
- } else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) {
- temp_SIR = EXMC_BANK3->SIR3;
- }
- /* EXMC_Bank4_PCCARD*/
- else {
- temp_SIR = EXMC_BANK4->SIR4;
- }
-
- temp_INTState = temp_SIR & EXMC_INT;
-
- temp_INTEnable = temp_SIR & (EXMC_INT >> SIR_INTEN_OFFSET);
-
- if ((temp_INTState != (uint32_t)RESET) && (temp_INTEnable != (uint32_t)RESET)) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt bit flag.
- * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank.
- * This parameter can be one of the following values:
- * @arg EXMC_BANK2_NAND: the NAND Bank2
- * @arg EXMC_BANK3_NAND: the NAND Bank3
- * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4
- * @param EXMC_INT: the interrupt bit flag.
- * This parameter can be any combination of the following values:
- * @arg EXMC_FLAG_RISE: Rising edge detection interrupt
- * @arg EXMC_FLAG_LEVEL: Level edge detection interrupt
- * @arg EXMC_FLAG_FALL: Falling edge detection interrupt
- * @retval None
- */
-void EXMC_ClearIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT)
-{
- if (EXMC_PCNANDBank == EXMC_BANK2_NAND) {
- EXMC_BANK2->SIR2 &= ~(EXMC_INT >> SIR_INTEN_OFFSET);
- } else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) {
- EXMC_BANK3->SIR3 &= ~(EXMC_INT >> SIR_INTEN_OFFSET);
- }
- /* EXMC_Bank4_PCCARD*/
- else {
- EXMC_BANK4->SIR4 &= ~(EXMC_INT >> SIR_INTEN_OFFSET);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c
deleted file mode 100644
index d541e371f1..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/**
- ******************************************************************************
- * @brief EXTI functions of the firmware library.
- ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_exti.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-/** @defgroup EXTI_Private_Defines
- * @{
- */
-/* No interrupt line is selected */
-#define EXTI_LINE_NULL ((uint32_t)0x00000000)
-
-/* ----------------- EXTI Reset Configuration Registers ------------------ */
-/* The reset value of EXTI_IER */
-#define EXTI_IER_RST ((uint32_t)0x00000000)
-
-/* The reset value of EXTI_EER */
-#define EXTI_EER_RST ((uint32_t)0x00000000)
-
-/* The reset value of EXTI_RTE */
-#define EXTI_RTE_RST ((uint32_t)0x00000000)
-
-/* The reset value of EXTI_FTE */
-#define EXTI_FTE_RST ((uint32_t)0x00000000)
-
-/* The reset value of EXTI_PD */
-#define EXTI_PD_RST ((uint32_t)0x000FFFFF)
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the EXTI peripheral registers and the struct EXTI_InitPara.
- * @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer.
- * @retval None
- */
-void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct)
-{
- /* Reset the EXTI peripheral registers */
- EXTI->IER = EXTI_IER_RST;
- EXTI->EER = EXTI_EER_RST;
- EXTI->RTE = EXTI_RTE_RST;
- EXTI->FTE = EXTI_FTE_RST;
- EXTI->PD = EXTI_PD_RST;
-
- /* Reset the struct EXTI_InitPara */
- EXTI_InitParaStruct->EXTI_LINE = EXTI_LINE_NULL;
- EXTI_InitParaStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitParaStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitParaStruct->EXTI_LINEEnable = DISABLE;
-}
-
-/**
- * @brief Initialize the EXTI peripheral registers.
- * @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer.
- * @retval None
- */
-void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct)
-{
- uint32_t temp = 0;
-
- temp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitParaStruct->EXTI_LINEEnable != DISABLE) {
- /* Clear Interrupt and Event from EXTI Lines */
- EXTI->IER &= ~EXTI_InitParaStruct->EXTI_LINE;
- EXTI->EER &= ~EXTI_InitParaStruct->EXTI_LINE;
-
- temp += EXTI_InitParaStruct->EXTI_Mode;
-
- *(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE;
-
- /* Clear the Rising and Falling edge trigger enable registers */
- EXTI->RTE &= ~EXTI_InitParaStruct->EXTI_LINE;
- EXTI->FTE &= ~EXTI_InitParaStruct->EXTI_LINE;
-
- /* Select the trigger type for the selected EXTI Lines */
- if (EXTI_InitParaStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
- /* Rising and Falling edge trigger are both selected */
- EXTI->RTE |= EXTI_InitParaStruct->EXTI_LINE;
- EXTI->FTE |= EXTI_InitParaStruct->EXTI_LINE;
- } else {
- temp = (uint32_t)EXTI_BASE;
- temp += EXTI_InitParaStruct->EXTI_Trigger;
-
- *(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE;
- }
- } else {
- temp += EXTI_InitParaStruct->EXTI_Mode;
-
- /* Disable the selected EXTI lines */
- *(__IO uint32_t *) temp &= ~EXTI_InitParaStruct->EXTI_LINE;
- }
-}
-
-/**
- * @brief Activate the software interrupt or event request of the selected EXTI Lines.
- * @param EXTI_LINE: the selected EXTI lines.
- * This parameter can be any combination of EXTI_LINEx where x can be (0..19).
- * @retval None
- */
-void EXTI_SWINT_Enable(uint32_t EXTI_LINE)
-{
- /* Enable the software interrupt or event request of the selected EXTI Lines */
- EXTI->SIE |= EXTI_LINE;
-}
-
-/**
- * @brief Get the bit flag of the selected EXTI lines.
- * @param EXTI_LINE: the selected EXTI lines.
- * This parameter can be any combination of EXTI_LINEx where x can be (0..19).
- * @retval The new value of EXTI_LINE (SET or RESET).
- */
-TypeState EXTI_GetBitState(uint32_t EXTI_LINE)
-{
- /* Check and get the selected EXTI lines flag */
- if ((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) {
- /* EXTI_LINE bit is SET */
- return SET;
- } else {
- /* EXTI_LINE bit is RESET */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the bit flag of the selected EXTI lines.
- * @param EXTI_LINE: the selected EXTI lines.
- * This parameter can be any combination of EXTI_LINEx where x can be (0..19).
- * @retval None
- */
-void EXTI_ClearBitState(uint32_t EXTI_LINE)
-{
- /* Clear the bit flag of the selected EXTI lines */
- EXTI->PD = EXTI_LINE;
-}
-
-/**
- * @brief Get the interrupt bit flag of the selected EXTI lines..
- * @param EXTI_LINE: the selected EXTI lines.
- * This parameter can be any combination of EXTI_LINEx where x can be (0..19).
- * @retval The new value of EXTI_LINE (SET or RESET).
- */
-TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE)
-{
- /* Check and get the interrupt source is set or not */
- if (((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) && ((EXTI->IER & EXTI_LINE) != (uint32_t)RESET)) {
- /* The interrupt bit of EXTI_LINE is SET */
- return SET;
- } else {
- /* The interrupt bit of EXTI_LINE is RESET */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt bit flag of the selected EXTI lines.
- * @param EXTI_LINE: the selected EXTI lines.
- * This parameter can be any combination of EXTI_LINEx where x can be (0..19).
- * @retval None
- */
-void EXTI_ClearIntBitState(uint32_t EXTI_LINE)
-{
- /* Clear the interrupt bit flag of the selected EXTI lines */
- EXTI->PD = EXTI_LINE;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_fmc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_fmc.c
deleted file mode 100644
index 68d5a283a4..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_fmc.c
+++ /dev/null
@@ -1,1166 +0,0 @@
-/**
- ******************************************************************************
- * @brief FMC functions of the firmware library.
- ******************************************************************************/
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_fmc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup FMC
- * @brief FMC driver modules
- * @{
- */
-
-/** @defgroup FMC_Private_Functions
- * @{
- */
-
-/** @defgroup FMC_Group1 FMC Memory Programming functions
- * @brief FMC Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FMC Memory Programming functions #####
- ===============================================================================
-
- [..] The FMC Memory Programming functions, includes the following functions:
- (+) void FMC_Unlock(void);
- (+) void FMC_UnlockBank1(void);
- (+) void FMC_UnlockBank2(void);
- (+) void FMC_Lock(void);
- (+) void FMC_LockBank1(void)
- (+) void FMC_LockBank2(void)
- (+) FMC_State FMC_ErasePage(uint32_t Page_Address);
- (+) FMC_State FMC_MassErase(void);
- (+) FMC_State FMC_MassBank1Erase(void)
- (+) FMC_State FMC_MassBank2Erase(void)
- (+) FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data);
- [..] Any operation of erase or program should follow these steps:
-
- (#) Call the FMC_Unlock() function to unlock the FMC operation
- (#) Call erase or program data
- (#) Call the FMC_Lock() to lock the FMC operation
-
-@endverbatim
- * @{
- */
-/**
- * @brief Unlock the main FMC operation.
- * @param None
- * @retval None
- */
-void FMC_Unlock(void)
-{
- if ((FMC->CMR & FMC_CMR_LK) != RESET) {
- /* Write the FMC key */
- FMC->UKEYR = FMC_KEY1;
- FMC->UKEYR = FMC_KEY2;
- }
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- /* Authorize the FPEC of Bank2 Access */
- if ((FMC->CMR2 & FMC_CMR_LK) != RESET) {
- FMC->UKEYR2 = FMC_KEY1;
- FMC->UKEYR2 = FMC_KEY2;
- }
- }
-}
-
-/**
- * @brief Unlocks the FMC Bank1 Program Erase Controller.
- * @note This function can be used for all GD32F10x devices.
- * - For GD32F10X_XD and GD32F10X_CL devices this function unlocks Bank1.
- * - For all other devices it unlocks Bank1 and it is
- * equivalent to FLASH_Unlock function.
- * @param None
- * @retval None
- */
-void FMC_UnlockB1(void)
-{
- /* Authorize the FPEC of Bank1 Access */
- if ((FMC->CMR & FMC_CMR_LK) != RESET) {
- FMC->UKEYR = FMC_KEY1;
- FMC->UKEYR = FMC_KEY2;
- }
-}
-
-/**
- * @brief Unlocks the FMC Bank2 Program Erase Controller.
- * @note This function can be used for GD32F10X_XD and GD32F10X_CL density devices.
- * @param None
- * @retval None
- */
-#if defined GD32F10X_XD || defined GD32F10X_CL
-void FMC_UnlockB2(void)
-{
- /* Authorize the FPEC of Bank2 Access */
- if ((FMC->CMR2 & FMC_CMR_LK) != RESET) {
- FMC->UKEYR2 = FMC_KEY1;
- FMC->UKEYR2 = FMC_KEY2;
- }
-}
-#endif /* GD32F10X_XD and GD32F10X_CL */
-
-/**
- * @brief Lock the main FMC operation.
- * @param None
- * @retval None
- */
-void FMC_Lock(void)
-{
- /* Set the LOCK bit*/
- FMC->CMR |= FMC_CMR_LK;
-
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
- FMC->CMR2 |= FMC_CMR_LK;
- }
-}
-
-/**
- * @brief Locks the FMC Bank1 Program Erase Controller.
- * @note this function can be used for all GD32F10X devices.
- * - For GD32F10X_XD and GD32F10X_CL devices this function Locks Bank1.
- * - For all other devices it Locks Bank1 and it is equivalent
- * to FMC_Lock function.
- * @param None
- * @retval None
- */
-void FMC_LockB1(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CMR of Bank1 */
- FMC->CMR |= FMC_CMR_LK;
-}
-
-/**
- * @brief Locks the FMC Bank2 Program Erase Controller.
- * @note This function can be used for GD32F10X_XD and GD32F10X_CL density devices.
- * @param None
- * @retval None
- */
-#if defined GD32F10X_XD || defined GD32F10X_CL
-void FMC_LockB2(void)
-{
- /* Set the Lock Bit to lock the FPEC and the CMR of Bank2 */
- FMC->CMR2 |= FMC_CMR_LK;
-}
-#endif
-
-/**
- * @brief Erase a page.
- * @param Page_Address: The page address to be erased.
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_ErasePage(uint32_t Page_Address)
-{
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
- if (Page_Address < FMC_B1_END_ADDRESS) {
- /* Wait for last operation to be completed */
- FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- FMC->CMR |= FMC_CMR_PE;
- FMC->AR = Page_Address;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the PE bit */
- FMC->CMR &= ~FMC_CMR_PE;
- }
- } else {
- /* Wait for last operation to be completed */
- FMC_State temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- FMC->CMR2 |= FMC_CMR_PE;
- FMC->AR2 = Page_Address;
- if (FMC->OPTR & FMC_OPTR_PLEVEL1) {
- FMC->AR = Page_Address;
- }
- FMC->CMR2 |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the PE bit */
- FMC->CMR2 &= ~FMC_CMR_PE;
- }
- }
- /* Return the FMC state */
- return temp_state;
- }
-
- else {
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Start page erase */
- FMC->CMR |= FMC_CMR_PE;
- FMC->AR = Page_Address;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the PE bit */
- FMC->CMR &= ~FMC_CMR_PE;
- }
- /* Return the FMC state */
- return temp_state;
- }
-}
-
-/**
- * @brief Erase all main FMC.
- * @param None
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_MassErase(void)
-{
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- /* Wait for last operation to be completed */
- FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
- if (temp_state == FMC_READY) {
- /* Start chip erase */
- FMC->CMR |= FMC_CMR_ME;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the MER bit */
- FMC->CMR &= ~FMC_CMR_ME;
- }
- temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
- if (temp_state == FMC_READY) {
- /* Start chip erase */
- FMC->CMR2 |= FMC_CMR_ME;
- FMC->CMR2 |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the MER bit */
- FMC->CMR2 &= ~FMC_CMR_ME;
- }
- /* Return the FMC state */
- return temp_state;
- } else {
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Start chip erase */
- FMC->CMR |= FMC_CMR_ME;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the MER bit */
- FMC->CMR &= ~FMC_CMR_ME;
- }
- /* Return the FMC state */
- return temp_state;
- }
-}
-
-/**
- * @brief Erases all Bank1 FMC pages.
- * @note This function can be used for all GD32F10x devices.
- * - For GD32F10X_XD and GD32F10X_CL devices this function erases all Bank1 pages.
- * - For all other devices it erases all Bank1 pages and it is equivalent
- * to FLASH_EraseAllPages function.
- * @param None
- * @retval FLASH Status: FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_MassB1Erase(void)
-{
- FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Start chip erase */
- FMC->CMR |= FMC_CMR_ME;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the MER bit */
- FMC->CMR &= ~FMC_CMR_ME;
- }
- /* Return the Erase Status */
- return temp_state;
-}
-
-/**
- * @brief Erases all Bank2 FMC pages.
- * @note This function can be used for GD32F10X_XD and GD32F10X_CL density devices.
- * @param None
- * @retval FMC Status: FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-
-FMC_State FMC_MassB2Erase(void)
-{
- FMC_State temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Start chip erase */
- FMC->CMR2 |= FMC_CMR_ME;
- FMC->CMR2 |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the MER bit */
- FMC->CMR2 &= ~FMC_CMR_ME;
- }
- /* Return the Erase Status */
- return temp_state;
-}
-
-
-/**
- * @brief Program a word at the corresponding address.
- * @param Address: The address to be programmed.
- * @param Data: The data to be programmed.
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data)
-{
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
- if (Address < FMC_B1_END_ADDRESS) {
- FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Set the PG bit to start program */
- FMC->CMR |= FMC_CMR_PG;
-
- *(__IO uint32_t *)Address = Data;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the PG bit */
- FMC->CMR &= ~FMC_CMR_PG;
- }
- } else {
- FMC_State temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Set the PG bit to start program */
- FMC->CMR2 |= FMC_CMR_PG;
-
- *(__IO uint32_t *)Address = Data;
-
- /* Wait for the FMC ready */
- temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the PG bit */
- FMC->CMR2 &= ~FMC_CMR_PG;
- }
- }
-
- /* Return the FMC state */
- return temp_state;
- } else {
-
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Set the PG bit to start program */
- FMC->CMR |= FMC_CMR_PG;
-
- *(__IO uint32_t *)Address = Data;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Reset the PG bit */
- FMC->CMR &= ~FMC_CMR_PG;
- }
-
- /* Return the FMC state */
- return temp_state;
-
- }
-
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Group2 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
-
- [..] The FMC_Option Bytes Programming_functions, includes the following functions:
- (+) void FMC_OB_Unlock(void);
- (+) void FMC_OB_Lock(void);
- (+) void FMC_OB_Reset(void);
- (+) FMC_State FMC_OB_Erase(void);
- (+) FMC_State FMC_OB_WRPConfig(uint32_t OB_WRP);
- (+) FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP);
- (+) FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY);
- (+) FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT);
- (+) FMC_State FMC_OB_WriteUser(uint8_t OB_USER);
- (+) FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data);
- (+) uint8_t FMC_OB_GetUser(void);
- (+) uint32_t FMC_OB_GetWRP(void);
- (+) FlagStatus FMC_OB_GetRDP(void);
- [..] Any operation of erase or program should follow these steps:
-
- (#) Call the FMC_OB_Unlock() function to enable the Option Bytes registers access
-
- (#) Call one or several functions to program the desired option bytes
- (++) FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
- (++) FMC_State FMC_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- => to Enable/Disable the desired sector write protection
- (++) FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY)
- => to configure the user option Bytes: IWDG, DEEPSLEEP and the Standby.
- (++) FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT1)
- => to set or reset BOOT1
- (++) FMC_State FMC_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
- => to enable or disable the VDDA Analog Monitoring
- (++) You can write all User Options bytes at once using a single function
- by calling FMC_State FMC_OB_WriteUser(uint8_t OB_USER)
- (++) FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data) to program the
- two half word in the option bytes
-
- (#) Once all needed option bytes to be programmed are correctly written, call the
- FMC_OB_Launch(void) function to launch the Option Bytes programming process.
-
- (#) Call the FMC_OB_Lock() to disable the Option Bytes registers access (recommended
- to protect the option Bytes against possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the option byte operation
- * @param None
- * @retval None
- */
-void FMC_OB_Unlock(void)
-{
- if ((FMC->CMR & FMC_CMR_OBWE) == RESET) {
- /* Write the FMC key */
- FMC->OBKEYR = FMC_KEY1;
- FMC->OBKEYR = FMC_KEY2;
- }
-}
-
-/**
- * @brief Lock the option byte operation.
- * @param None
- * @retval None
- */
-void FMC_OB_Lock(void)
-{
- /* Reset the OBWE bit */
- FMC->CMR &= ~FMC_CMR_OBWE;
-}
-
-/**
- * @brief Generate a system reset to reload the option byte.
- * @param None
- * @retval None
- */
-void FMC_OB_Reset(void)
-{
- /* Set the OPTR bit */
- FMC->CMR |= FMC_CMR_OPTR;
-}
-
-/**
- * @brief Erase the FMC option byte.
- * @param None
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_OB_Erase(void)
-{
- uint16_t temp_rdp = RDP_LEVEL_0;
-
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- /* Check the ReadOut Protection Option Byte */
- if (FMC_OB_GetRDP() != RESET) {
- temp_rdp = 0x00;
- }
-
- if (temp_state == FMC_READY) {
- /* Start erase the option byte */
- FMC->CMR |= FMC_CMR_OBER;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Reset the OPER bit */
- FMC->CMR &= ~FMC_CMR_OBER;
-
- /* Set the OBPG bit */
- FMC->CMR |= FMC_CMR_OBPG;
-
- /* Set default RDP level */
- OB->RDP = (uint16_t)temp_rdp;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- } else {
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Program Write protect Byte
- * @param OB_WRP: specify the address of the pages to be write protected.
- * The legal parameter can be:
- * @arg WRP_SECTOR0 ... WRP_SECTOR31
- * @arg WRP_ALLSECTORS
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_OB_EnableWRP(uint32_t OB_WRP)
-{
- uint16_t temp_WRP0, temp_WRP1, temp_WRP2, temp_WRP3;
-
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- OB_WRP = (uint32_t)(~OB_WRP);
- temp_WRP0 = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
- temp_WRP1 = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);
- temp_WRP2 = (uint16_t)((OB_WRP & OB_WRP1_WRP1) >> 16);
- temp_WRP3 = (uint16_t)((OB_WRP & OB_WRP1_nWRP1) >> 24);
-
- if (temp_state == FMC_READY) {
- FMC->OBKEYR = FMC_KEY1;
- FMC->OBKEYR = FMC_KEY2;
- /* Set the OBPG bit*/
- FMC->CMR |= FMC_CMR_OBPG;
-
- if (temp_WRP0 != 0xFF) {
- OB->WRP0 = temp_WRP0;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- }
- if ((temp_state == FMC_READY) && (temp_WRP1 != 0xFF)) {
- OB->WRP1 = temp_WRP1;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- }
- if ((temp_state == FMC_READY) && (temp_WRP2 != 0xFF)) {
- OB->WRP2 = temp_WRP2;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- }
- if ((temp_state == FMC_READY) && (temp_WRP3 != 0xFF)) {
- OB->WRP3 = temp_WRP3;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- }
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Enable or disable the read out protection,this function erases all option bytes.
- * @param NewValue: ENABLE or DISABLE.
- * @retval FMC state: FMC_READY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_ReadOutProtection(TypeState NewValue)
-{
- FMC_State temp_state = FMC_READY;
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- if (temp_state == FMC_READY) {
- /* Unlock option bytes */
- FMC->OBKEYR = FMC_KEY1;
- FMC->OBKEYR = FMC_KEY2;
- while ((FMC->CMR & FMC_CMR_OBWE) != FMC_CMR_OBWE)
- {}
- FMC->CMR |= FMC_CMR_OBER;
- FMC->CMR |= FMC_CMR_START;
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- if (temp_state == FMC_READY) {
- /* Disable the OBER Bit */
- FMC->CMR &= ~FMC_CMR_OBER ;
- /* Enable the OBPG Bit */
- FMC->CMR |= FMC_CMR_OBPG;
- if (NewValue != DISABLE) {
- OB->RDP = 0x00;
- } else {
- OB->RDP = RDP_LEVEL_0;
- }
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Enable the OBPG Bit */
- FMC->CMR &= ~FMC_CMR_OBPG ;
- }
- } else {
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Disable the OBER Bit */
- FMC->CMR &= ~FMC_CMR_OBER ;
- }
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Config the Read Out Protection bit.
- * @param FMC_ReadProtection_Level: The Read Out Protection level.
- * This parameter can be:
- * @arg RDP_LEVEL_0: No protection
- * @arg RDP_LEVEL_1: Read Outprotection of the memory
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP)
-{
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- FMC->CMR |= FMC_CMR_OBER;
- FMC->CMR |= FMC_CMR_START;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Reset the OBER bit */
- FMC->CMR &= ~FMC_CMR_OBER;
-
- /* Start the Option Bytes Programming */
- FMC->CMR |= FMC_CMR_OBPG;
-
- OB->RDP = OB_RDP;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- } else {
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBER Bit */
- FMC->CMR &= ~FMC_CMR_OBER;
- }
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Program the FMC User Option Byte: IWDG_SW / RST_DEEPSLEEP / RST_STDBY.
- * @param OB_IWDG: Config the WDG mode
- * @arg OB_IWDG_SW: Software WDG selected
- * @arg OB_IWDG_HW: Hardware WDG selected
- * @param OB_DEEPSLEEP: Config Reset event when entering DEEPSLEEP mode.
- * @arg OB_DEEPSLEEP_NORST: No reset generated when entering in DEEPSLEEP
- * @arg OB_DEEPSLEEP_RST: Reset generated when entering in DEEPSLEEP
- * @param OB_STDBY: Config Reset event when entering Standby mode.
- * @arg OB_STDBY_NORST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY)
-{
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Set the OBPG bit*/
- FMC->CMR |= FMC_CMR_OBPG;
-
- OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_DEEPSLEEP) | (uint16_t)(OB_STDBY | 0xF8));
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Program the BOOT option bit.
- * @param OB_BOOT: The legal parameter can be one of the following value:
- * @arg OB_BOOT_B1:Start up from Bank1
- * @arg OB_BOOT_B2:Start up from Bank2
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT)
-{
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
- FMC->OBKEYR = FMC_KEY1;
- FMC->OBKEYR = FMC_KEY2;
-
- if (temp_state == FMC_READY) {
- /* Set the OBPG bit*/
- FMC->CMR |= FMC_CMR_OBPG;
-
- if (OB_BOOT == OB_BOOT_B1) {
- OB->USER |= OB_USER_BFB2;
- } else {
- OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
- }
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Program the FMC User Option Byte.
- * @param OB_USER: Select all user option byte
- * The legal parameter is one of the following values:
- * @arg OB_IWDG_SW
- * @arg OB_IWDG_HW
- * @arg OB_DEEPSLEEP_NORST
- * @arg OB_DEEPSLEEP_RST
- * @arg OB_STDBY_NORST
- * @arg OB_STDBY_RST
- * @arg OB_BOOT_B1
- * @arg OB_BOOT_B2
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_OB_WriteUser(uint8_t OB_USER)
-{
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* Set the OBPG bit */
- FMC->CMR |= FMC_CMR_OBPG;
-
- OB->USER = OB_USER | 0xf0;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OBPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Program Option Byte Data.
- * @param Address: The Option Byte address to be programmed.
- * The legal parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data: The Byte to be programmed.
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
- FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state == FMC_READY) {
- /* SET the OPTPG bit */
- FMC->CMR |= FMC_CMR_OBPG;
- *(__IO uint16_t *)Address = Data;
-
- /* Wait for the FMC ready */
- temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT);
-
- if (temp_state != FMC_TIMEOUT_ERR) {
- /* Reset the OPTPG bit */
- FMC->CMR &= ~FMC_CMR_OBPG;
- }
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Get the FMC User Option Byte.
- * @param None
- * @retval The FMC User Option Byte.
- */
-uint8_t FMC_OB_GetUser(void)
-{
- return (uint8_t)(FMC->OPTR >> 8);
-}
-
-/**
- * @brief Get the FMC Write Protection Option Byte.
- * @param None
- * @retval The FMC Write Protection Option Byte
- */
-uint32_t FMC_OB_GetWRP(void)
-{
- return (uint32_t)(FMC->WPR);
-}
-
-/**
- * @brief Check whether the FMC Read out Protection Status is SET or RESET.
- * @param None
- * @retval FMC ReadOut Protection state
- */
-TypeState FMC_OB_GetRDP(void)
-{
- TypeState RDPState = RESET;
-
- if ((uint8_t)(FMC->OPTR & (FMC_OPTR_PLEVEL1)) != RESET) {
- RDPState = SET;
- } else {
- RDPState = RESET;
- }
- return RDPState;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable or disable the corresponding FMC interrupt source.
- * @param FMC_INT: The FMC interrupt source to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FMC_INT_EOP: FMC end of programming Interrupt
- * @arg FMC_INT_ERR: FMC Error Interrupt
- * @arg FMC_INT_B2_EOP: FMC end of programming Interrupt
- * @arg FMC_INT_B2_ERR: FMC Error Interrupt
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_INTConfig(uint32_t FMC_INT, TypeState NewValue)
-{
-
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- if ((FMC_INT & 0x80000000) != 0x0) {
- if (NewValue != DISABLE) {
- /* Enable the interrupt sources */
- FMC->CMR2 |= (FMC_INT & 0x7fffffff);
- } else {
- /* Disable the interrupt sources */
- FMC->CMR2 &= ~(uint32_t)(FMC_INT & 0x7fffffff);
- }
- } else {
- if (NewValue != DISABLE) {
- /* Enable the interrupt sources */
- FMC->CMR |= FMC_INT;
- } else {
- /* Disable the interrupt sources */
- FMC->CMR &= ~(uint32_t)FMC_INT;
- }
- }
- } else {
- if (NewValue != DISABLE) {
- /* Enable the interrupt sources */
- FMC->CMR |= FMC_INT;
- } else {
- /* Disable the interrupt sources */
- FMC->CMR &= ~(uint32_t)FMC_INT;
- }
- }
-}
-
-/**
- * @brief Checks whether the FMC flag is SET or RESET.
- * @param FMC_FLAG: the corresponding FMC flag.
- * the legal parameter can be:
- * @arg FMC_FLAG_BSY: FMC BUSY flag
- * @arg FMC_FLAG_PERR: FMC Programming error flag flag
- * @arg FMC_FLAG_WERR: FMC Write protection error flag
- * @arg FMC_FLAG_EOP: FMC End of Programming flag
- * @arg FMC_FLAG_OPTER: FMC option byte error flag
- * @retval The state of the FMC flag.
- */
-TypeState FMC_GetBitState(uint32_t FMC_FLAG)
-{
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- /* Check the parameters */
- if (FMC_FLAG == FMC_FLAG_OPTERR) {
- if ((FMC->OPTR & FMC_FLAG_OPTERR) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
- } else {
- if ((FMC_FLAG & 0x80000000) != 0x0) {
- if ((FMC->CSR2 & FMC_FLAG) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
- } else {
- if ((FMC->CSR & FMC_FLAG) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
- }
- }
- } else {
- if (FMC_FLAG == FMC_FLAG_OPTERR) {
- if ((FMC->OPTR & FMC_FLAG_OPTERR) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
- } else {
- if ((FMC->CSR & FMC_FLAG) != (uint32_t)RESET) {
- return SET;
- }
- /* Return the state of corresponding FMC flag */
- else {
- return RESET;
- }
- }
- }
-}
-
-/**
- * @brief Clear the FMC pending flag.
- * @param FMC_FLAG: clear the corresponding FMC flag.
- * @arg FMC_FLAG_PERR: Programming error flag flag
- * @arg FMC_FLAG_WERR: Write protection error flag
- * @arg FMC_FLAG_EOP: End of Programming flag
- * @retval None
- */
-void FMC_ClearBitState(uint32_t FMC_FLAG)
-{
- if (FMC_SIZE > FMC_BANK1_SIZE) {
- if ((FMC_FLAG & 0x80000000) != 0x0) {
- /* Clear the flags */
- FMC->CSR2 = FMC_FLAG;
- } else {
- /* Clear the flags */
- FMC->CSR = FMC_FLAG;
- }
- } else {
- FMC->CSR = FMC_FLAG;
- }
-}
-
-/**
- * @brief Return the FMC state.
- * @param None
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, or FMC_PGERR
- */
-FMC_State FMC_GetState(void)
-{
- FMC_State temp_state = FMC_READY;
-
- if ((FMC->CSR & FMC_CSR_BUSY) == FMC_CSR_BUSY) {
- temp_state = FMC_BSY;
- } else {
- if ((FMC->CSR & (uint32_t)FMC_CSR_WPEF) != (uint32_t)0x00) {
- temp_state = FMC_WRPERR;
- } else {
- if ((FMC->CSR & (uint32_t)(FMC_CSR_PGEF)) != (uint32_t)0x00) {
- temp_state = FMC_PGERR;
- } else {
- temp_state = FMC_READY;
- }
- }
- }
-
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Return the FMC bak1 state.
- * @param None
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, or FMC_PGERR
- */
-FMC_State FMC_GetB1State(void)
-{
- FMC_State temp_state = FMC_READY;
-
- if ((FMC->CSR & FMC_CSR_BUSY) == FMC_CSR_BUSY) {
- temp_state = FMC_BSY;
- } else {
- if ((FMC->CSR & (uint32_t)FMC_CSR_WPEF) != (uint32_t)0x00) {
- temp_state = FMC_WRPERR;
- } else {
- if ((FMC->CSR & (uint32_t)(FMC_CSR_PGEF)) != (uint32_t)0x00) {
- temp_state = FMC_PGERR;
- } else {
- temp_state = FMC_READY;
- }
- }
- }
- return temp_state;
-}
-
-/**
- * @brief Return the FMC bak2 state.
- * @param None
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, or FMC_PGERR
- */
-
-FMC_State FMC_GetB2State(void)
-{
-
- FMC_State temp_state = FMC_READY;
-
- if ((FMC->CSR2 & FMC_CSR2_BUSY & 0x7fffffff) == (FMC_CSR2_BUSY & 0x7fffffff)) {
- temp_state = FMC_BSY;
- } else {
- if ((FMC->CSR2 & FMC_CSR2_WPEF & 0x7fffffff) != (uint32_t)0x00) {
- temp_state = FMC_WRPERR;
- } else {
- if ((FMC->CSR2 & FMC_CSR2_PGEF & 0x7fffffff) != (uint32_t)0x00) {
- temp_state = FMC_PGERR;
- } else {
- temp_state = FMC_READY;
- }
- }
- }
-
- /* Return the FMC state */
- return temp_state;
-}
-
-
-/**
- * @brief Check whether FMC is ready or not.
- * @param Timeout: Count of loop
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_WaitReady(uint32_t uCount)
-{
- FMC_State temp_state = FMC_BSY;
-
- /* Wait for FMC ready */
- do {
- /* Get FMC state */
- temp_state = FMC_GetState();
- uCount--;
- } while ((temp_state == FMC_BSY) && (uCount != 0x00));
-
- if (temp_state == FMC_BSY) {
- temp_state = FMC_TIMEOUT_ERR;
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Check whether FMC Bank1 is ready or not.
- * @param Timeout: Count of loop
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-FMC_State FMC_B1_WaitReady(uint32_t uCount)
-{
- FMC_State temp_state = FMC_BSY;
-
- /* Wait for FMC ready */
- do {
- /* Get FMC state */
- temp_state = FMC_GetB1State();
- uCount--;
- } while ((temp_state == FMC_BSY) && (uCount != 0x00));
-
- if (temp_state == FMC_BSY) {
- temp_state = FMC_TIMEOUT_ERR;
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @brief Check whether FMC Bank2 is ready or not.
- * @param Timeout: Count of loop
- * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR.
- */
-
-FMC_State FMC_B2_WaitReady(uint32_t uCount)
-{
- FMC_State temp_state = FMC_BSY;
-
- /* Wait for FMC ready */
- do {
- /* Get FMC state */
- temp_state = FMC_GetB2State();
- uCount--;
- } while ((temp_state == (FMC_BSY && 0x7FFFFFFF)) && (uCount != 0x00));
-
- if (temp_state == FMC_BSY) {
- temp_state = FMC_TIMEOUT_ERR;
- }
- /* Return the FMC state */
- return temp_state;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-* @}
-*/
-
-/**
- * @}
- */
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_gpio.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_gpio.c
deleted file mode 100644
index 99a16e4d43..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_gpio.c
+++ /dev/null
@@ -1,511 +0,0 @@
-/**
- ******************************************************************************
- * @brief GPIO functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_gpio.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/** @defgroup GPIO_Private_Defines
- * @{
- */
-#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
-#define LSB_MASK ((uint16_t)0xFFFF)
-#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
-#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
-#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
-#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
-#define AFIO_PCFR1_MII_RMII ((uint32_t)0x00800000)
-#define AFIO_ESSR1_BITS_FIELDS ((uint8_t)0x04)
-#define AFIO_ESSR2_BITS_FIELDS ((uint8_t)0x08)
-#define AFIO_ESSR3_BITS_FIELDS ((uint8_t)0x0c)
-#define AFIO_ESSR_PIN_FIELDS ((uint8_t)0x04)
-#define AFIO_ESSR_4BIT_FIELDS ((uint8_t)0x0f)
-#define CTLR1_8BIT_FIELDS ((uint32_t)0x00ff)
-#define CTLR2_8BIT_FIELDS ((uint32_t)0x00ff)
-#define AFIO_PCFR2_FIELDS ((uint32_t)0x80000000)
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the GPIOx peripheral.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
- if (GPIOx == GPIOA) {
- /* Enable GPIOA reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOA, ENABLE);
- /* Release GPIOA from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOA, DISABLE);
- } else if (GPIOx == GPIOB) {
- /* Enable GPIOB reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOB, ENABLE);
- /* Release GPIOB from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOB, DISABLE);
- } else if (GPIOx == GPIOC) {
- /* Enable GPIOC reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOC, ENABLE);
- /* Release GPIOC from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOC, DISABLE);
- } else if (GPIOx == GPIOD) {
- /* Enable GPIOD reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOD, ENABLE);
- /* Release GPIOD from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOD, DISABLE);
- } else if (GPIOx == GPIOE) {
- /* Enable GPIOE reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOE, ENABLE);
- /* Release GPIOE from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOE, DISABLE);
- } else if (GPIOx == GPIOF) {
- /* Enable GPIOF reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOF, ENABLE);
- /* Release GPIOF from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOF, DISABLE);
- } else if (GPIOx == GPIOG) {
- /* Enable GPIOG reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOG, ENABLE);
- /* Release GPIOG from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOG, DISABLE);
- }
-}
-
-/**
- * @brief Deinitialize the Alternate Functions (remap, event control
- * and EXTI configuration) registers to their default reset values.
- * @param None
- * @retval None
- */
-void GPIO_AFDeInit(void)
-{
- /* Enable AFIO reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_AF, ENABLE);
- /* Release AFIO from reset state */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_AF, DISABLE);
-}
-
-/**
- * @brief Initialize the GPIOx peripheral.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param GPIO_InitStruct: The structuer contains configuration information.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitPara *GPIO_InitStruct)
-{
- uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
- uint32_t tempreg = 0x00, pinmask = 0x00;
-
- /* GPIO Mode Configuration */
- currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
- if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) {
- /* Output mode */
- currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
- }
- /* GPIO CTLR1 Configuration */
- /* Configure the eight low port pins */
- if (((uint32_t)GPIO_InitStruct->GPIO_Pin & CTLR1_8BIT_FIELDS) != 0x00) {
- tempreg = GPIOx->CTLR1;
- for (pinpos = 0x00; pinpos < 0x08; pinpos++) {
- pos = ((uint32_t)0x01) << pinpos;
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
- if (currentpin == pos) {
- pos = pinpos << 2;
- /* Clear the corresponding low control register bits */
- pinmask = ((uint32_t)0x0F) << pos;
- tempreg &= ~pinmask;
- /* Write the mode configuration in the corresponding bits */
- tempreg |= (currentmode << pos);
- /* Reset the corresponding ODR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPD) {
- GPIOx->BCR = (((uint32_t)0x01) << pinpos);
- } else {
- /* Set the corresponding ODR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPU) {
- GPIOx->BOR = (((uint32_t)0x01) << pinpos);
- }
- }
- }
- }
- GPIOx->CTLR1 = tempreg;
- }
- /* GPIO CTLR2 Configuration */
- /* Configure the eight high port pins */
- if (GPIO_InitStruct->GPIO_Pin > CTLR2_8BIT_FIELDS) {
- tempreg = GPIOx->CTLR2;
- for (pinpos = 0x00; pinpos < 0x08; pinpos++) {
- pos = (((uint32_t)0x01) << (pinpos + 0x08));
- /* Get the port pins position */
- currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
- if (currentpin == pos) {
- pos = pinpos << 2;
- /* Clear the corresponding high control register bits */
- pinmask = ((uint32_t)0x0F) << pos;
- tempreg &= ~pinmask;
- /* Write the mode configuration in the corresponding bits */
- tempreg |= (currentmode << pos);
- /* Reset the corresponding DOR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPD) {
- GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
- }
- /* Set the corresponding DOR bit */
- if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPU) {
- GPIOx->BOR = (((uint32_t)0x01) << (pinpos + 0x08));
- }
- }
- }
- GPIOx->CTLR2 = tempreg;
- }
-}
-
-/**
- * @brief Initial GPIO_InitParameter members.
- * @param GPIO_InitParameter : pointer to a GPIO_InitPara structure.
- * @retval None
- */
-void GPIO_ParaInit(GPIO_InitPara *GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_PIN_ALL;
- GPIO_InitStruct->GPIO_Speed = GPIO_SPEED_2MHZ;
- GPIO_InitStruct->GPIO_Mode = GPIO_MODE_IN_FLOATING;
-}
-
-/**
- * @brief Read the select input port.
- * @param GPIOx: Select the GPIO peripheral.
- * @param GPIO_Pin: Select the port.
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- if ((GPIOx->DIR & GPIO_Pin) != (uint32_t)Bit_RESET) {
- bitstatus = (uint8_t)Bit_SET;
- } else {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Read the specified GPIO input data port.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @retval GPIO input data port value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
-{
- return ((uint16_t)GPIOx->DIR);
-}
-
-/**
- * @brief Read the specified output data port bit.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral.
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- if ((GPIOx->DOR & GPIO_Pin) != (uint32_t)Bit_RESET) {
- bitstatus = (uint8_t)Bit_SET;
- } else {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Read the specified GPIO output data port.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
-{
- return ((uint16_t)GPIOx->DOR);
-}
-
-/**
- * @brief Set the selected data port bits.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- GPIOx->BOR = GPIO_Pin;
-}
-
-/**
- * @brief Clear the selected data port bits.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- GPIOx->BCR = GPIO_Pin;
-}
-
-/**
- * @brief Set or clear the selected data port bit.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral.
- * @param BitVal: specifies the state of the port.Select one of the follwing values :
- * @arg Bit_RESET: clear the port pin
- * @arg Bit_SET: set the port pin
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitState BitVal)
-{
- if (BitVal != Bit_RESET) {
- GPIOx->BOR = GPIO_Pin;
- } else {
- GPIOx->BCR = GPIO_Pin;
- }
-}
-
-/**
- * @brief Write data to the specified GPIO data port.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param PortVal: specifies the value to be written to the port data output register.
- * @retval None
- */
-void GPIO_WritePort(GPIO_TypeDef *GPIOx, uint16_t PortVal)
-{
- GPIOx->DOR = PortVal;
-}
-
-/**
- * @brief Lock GPIO Pins configuration.
- * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
- * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral.
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- uint32_t temp = 0x00010000;
-
- temp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LOCKR = temp;
- /* Reset LCKK bit */
- GPIOx->LOCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LOCKR = temp;
- /* Read LCKK bit*/
- temp = GPIOx->LOCKR;
- /* Read LCKK bit*/
- temp = GPIOx->LOCKR;
-}
-
-/**
- * @brief Select the GPIO pin used as Event output.
- * @param GPIO_PortSource: This parameter can be GPIO_PORT_SOURCE_GPIOx where x can be (A..G).
- * @param GPIO_PinSource: This parameter can be GPIO_PINSOURCEx where x can be (0..15).
- * @retval None
- */
-void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
-{
- uint32_t temp = 0x00;
-
- temp = AFIO->AFIO_EVR;
- /* Clear the PORT[6:4] and PIN[3:0] bits */
- temp &= ECR_PORTPINCONFIG_MASK;
- temp |= (uint32_t)GPIO_PortSource << 0x04;
- temp |= GPIO_PinSource;
- AFIO->AFIO_EVR = temp;
-}
-
-/**
- * @brief Enable or disable the Event Output.
- * @param AFIO_Event: AFIO_Event Enable or Disable bit.
- * @param NewState: new state of the Event output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void GPIO_EventOutput_Enable(uint32_t AFIO_Event, TypeState NewState)
-{
- /* Enable or disable the Event Output */
- if (NewState != DISABLE) {
- AFIO->AFIO_EVR |= AFIO_ECR_EVOE_SET;
- } else {
- AFIO->AFIO_EVR &= AFIO_ECR_EVOE_RESET;
- }
-}
-
-/**
- * @brief Change the mapping of the specified pin.
- * @param GPIO_Remap: selects the pin to remap.
- * This parameter can be one of the following values:
- * @arg GPIO_REMAP_SPI1
- * @arg GPIO_REMAP_I2C1
- * @arg GPIO_REMAP_USART1
- * @arg GPIO_REMAP_USART2
- * @arg GPIO_PARTIAL_REMAP_USART3
- * @arg GPIO_FULL_REMAP_USART3
- * @arg GPIO_PARTIAL_REMAP_TIMER1
- * @arg GPIO_FULL_REMAP_TIMER1
- * @arg GPIO_PARTIAL_REMAP1_TIMER2
- * @arg GPIO_PARTIAL_REMAP2_TIMER2
- * @arg GPIO_FULL_REMAP_TIMER2
- * @arg GPIO_PARTIAL_REMAP_TIMER3
- * @arg GPIO_FULL_REMAP_TIMER3
- * @arg GPIO_REMAP_TIMER4
- * @arg GPIO_REMAP1_CAN1
- * @arg GPIO_REMAP2_CAN1
- * @arg GPIO_REMAP_PD01
- * @arg GPIO_REMAP_TIMER5CH4_LSI
- * @arg GPIO_REMAP_ADC1_ETRGINJ
- * @arg GPIO_REMAP_ADC1_ETRGREG
- * @arg GPIO_REMAP_ADC2_ETRGINJ
- * @arg GPIO_REMAP_ADC2_ETRGREG
- * @arg GPIO_REMAP_ETH
- * @arg GPIO_REMAP_CAN2
- * @arg GPIO_REMAP_SWJ_NOJTRST
- * @arg GPIO_REMAP_SWJ_JTAGDISABLE
- * @arg GPIO_REMAP_SWJ_DISABLE
- * @arg GPIO_REMAP_SPI3
- * @arg GPIO_REMAP_TIMER2ITR1_PTP_SOF
- * @arg GPIO_REMAP_PTP_PPS
- * @arg GPIO_REMAP_TIMER15
- * @arg GPIO_REMAP_TIMER16
- * @arg GPIO_REMAP_TIMER17
- * @arg GPIO_REMAP_CEC
- * @arg GPIO_REMAP_TIMER1_DMA
- * @arg GPIO_REMAP_TIMER9
- * @arg GPIO_REMAP_TIMER10
- * @arg GPIO_REMAP_TIMER11
- * @arg GPIO_REMAP_TIMER13
- * @arg GPIO_REMAP_TIMER14
- * @arg GPIO_REMAP_EXMC_NADV
- * @arg GPIO_REMAP_TIMER67_DAC_DMA
- * @arg GPIO_REMAP_TIMER12
- * @arg GPIO_REMAP_MISC
- * @param NewState: new state of the port pin remapping.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void GPIO_PinRemapConfig(uint32_t GPIO_Remap, TypeState NewState)
-{
- uint32_t temp = 0x00, temp1 = 0x00, tempreg = 0x00, tempmask = 0x00;
-
- if ((GPIO_Remap & 0x80000000) == 0x80000000) {
- tempreg = AFIO->AFIO_PCFR2;
- } else {
- tempreg = AFIO->AFIO_PCFR1;
- }
-
- tempmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
- temp = GPIO_Remap & LSB_MASK;
-
- if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) {
- tempreg &= DBGAFR_SWJCFG_MASK;
- AFIO->AFIO_PCFR1 &= DBGAFR_SWJCFG_MASK;
- } else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) {
- temp1 = ((uint32_t)0x03) << tempmask;
- tempreg &= ~temp1;
- tempreg |= ~DBGAFR_SWJCFG_MASK;
- } else {
- tempreg &= ~(temp << ((GPIO_Remap >> 0x15) * 0x10));
- tempreg |= ~DBGAFR_SWJCFG_MASK;
- }
- if (NewState != DISABLE) {
- tempreg |= (temp << ((GPIO_Remap >> 0x15) * 0x10));
- }
- if ((GPIO_Remap & AFIO_PCFR2_FIELDS) == AFIO_PCFR2_FIELDS) {
- AFIO->AFIO_PCFR2 = tempreg;
- } else {
- AFIO->AFIO_PCFR1 = tempreg;
- }
-}
-
-/**
- * @brief Select the GPIO pin used as EXTI Line.
- * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
- * This parameter can be GPIO_PORT_SOURCE_GPIOx where x can be (A..G).
- * @param GPIO_PinSource: specifies the EXTI line to be configured.
- * This parameter can be GPIO_PINSOURCEx where x can be (0..15).
- * @retval None
- */
-void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
-{
- uint32_t temp = 0x00;
-
- temp = ((uint32_t)0x0f) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03));
- /* Select EXTI0->EXTI3 bit */
- if (GPIO_PinSource < AFIO_ESSR1_BITS_FIELDS) {
- AFIO->AFIO_ESSR1 &= ~temp;
- AFIO->AFIO_ESSR1 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03)));
- }
- /* Select EXTI4->EXTI7 bit */
- else if (GPIO_PinSource < AFIO_ESSR2_BITS_FIELDS) {
- AFIO->AFIO_ESSR2 &= ~temp;
- AFIO->AFIO_ESSR2 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03)));
- }
- /* Select EXTI8->EXTI11 bit */
- else if (GPIO_PinSource < AFIO_ESSR3_BITS_FIELDS) {
- AFIO->AFIO_ESSR3 &= ~temp;
- AFIO->AFIO_ESSR3 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03)));
- }
- /* Select EXTI12->EXTI15 bit */
- else {
- AFIO->AFIO_ESSR4 &= ~temp;
- AFIO->AFIO_ESSR4 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03)));
- }
-}
-
-/**
- * @brief Select the Ethernet media interface.
- * @note This function applies only to GD32 Connectivity line devices.
- * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
- * This parameter can be one of the following values:
- * @arg GPIO_ETH_MEDIA_INTERFACE_MII: MII mode
- * @arg GPIO_ETH_MEDIA_INTERFACE_RMII: RMII mode
- * @retval None
- */
-void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
-{
- uint32_t temp = 0;
- temp = AFIO->AFIO_PCFR1;
- /* Clear MII_RMII_SEL bit */
- temp &= ~((uint32_t)AFIO_PCFR1_MII_RMII);
- /* Configure MII_RMII bit according to GPIO_ETH_MediaInterface value */
- temp |= GPIO_ETH_MediaInterface;
- /* Store the new value */
- AFIO->AFIO_PCFR1 = temp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_i2c.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_i2c.c
deleted file mode 100644
index efc83ed26f..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_i2c.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/**
- ******************************************************************************
- * @brief I2C functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_i2c.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/** @defgroup I2C_Private_Defines
- * @{
- */
-
-/* I2C CTLR1_I2CEN mask */
-#define CTLR1_I2CEN_SET I2C_CTLR1_I2CEN
-#define CTLR1_I2CEN_RESET ((uint16_t)~I2C_CTLR1_I2CEN)
-
-/* I2C CTLR1_GENSTA mask */
-#define CTLR1_GENSTA_SET I2C_CTLR1_GENSTA
-#define CTLR1_GENSTA_RESET ((uint16_t)~I2C_CTLR1_GENSTA)
-
-/* I2C CTLR1_GENSTP mask */
-#define CTLR1_GENSTP_SET I2C_CTLR1_GENSTP
-#define CTLR1_GENSTP_RESET ((uint16_t)~I2C_CTLR1_GENSTP)
-
-/* I2C CTLR1_ACKEN mask */
-#define CTLR1_ACKEN_SET I2C_CTLR1_ACKEN
-#define CTLR1_ACKEN_RESET ((uint16_t)~I2C_CTLR1_ACKEN)
-
-/* I2C CTLR1_GCEN mask */
-#define CTLR1_GCEN_SET I2C_CTLR1_GCEN
-#define CTLR1_GCEN_RESET ((uint16_t)~I2C_CTLR1_GCEN)
-
-/* I2C CTLR1_SRESET mask */
-#define CTLR1_SRESET_SET I2C_CTLR1_SRESET
-#define CTLR1_SRESET_RESET ((uint16_t)~I2C_CTLR1_SRESET)
-
-/* I2C CTLR1_SALT mask */
-#define CTLR1_SALT_SET I2C_CTLR1_SALT
-#define CTLR1_SALT_RESET ((uint16_t)~I2C_CTLR1_SALT)
-
-/* I2C CTLR1_PECTRANS mask */
-#define CTLR1_PECTRANS_SET I2C_CTLR1_PECTRANS
-#define CTLR1_PECTRANS_RESET ((uint16_t)~I2C_CTLR1_PECTRANS)
-
-/* I2C CTLR1_PECEN mask */
-#define CTLR1_PECEN_SET I2C_CTLR1_PECEN
-#define CTLR1_PECEN_RESET ((uint16_t)~I2C_CTLR1_PECEN)
-
-/* I2C CTLR1_ARPEN mask */
-#define CTLR1_ARPEN_SET I2C_CTLR1_ARPEN
-#define CTLR1_ARPEN_RESET ((uint16_t)~I2C_CTLR1_ARPEN)
-
-/* I2C CTLR1_DISSTRC mask */
-#define CTLR1_DISSTRC_SET I2C_CTLR1_DISSTRC
-#define CTLR1_DISSTRC_RESET ((uint16_t)~I2C_CTLR1_DISSTRC)
-
-/* I2C registers Masks */
-#define CTLR1_CLEAR_MASK ((uint16_t)0xFBF5)
-
-/* I2C CTLR2_DMAON mask */
-#define CTLR2_DMAON_SET I2C_CTLR2_DMAON
-#define CTLR2_DMAON_RESET ((uint16_t)~I2C_CTLR2_DMAON)
-
-/* I2C CTLR2_DMALST mask */
-#define CTLR2_DMALST_SET I2C_CTLR2_DMALST
-#define CTLR2_DMALST_RESET ((uint16_t)~I2C_CTLR2_DMALST)
-
-/* I2C CTLR2_I2CCLK mask */
-#define CTLR2_I2CCLK_RESET ((uint16_t)0xFFC0)
-
-/* I2C I2CCLK_Freq_MAX */
-#define I2CCLK_FREQ_MAX I2C_CTLR2_I2CCLK
-
-/* I2C AR1_ADDRESS0 mask */
-#define AR1_ADDRESS0_SET I2C_AR1_ADDRESS0
-#define AR1_ADDRESS0_RESET ((uint16_t)~I2C_AR1_ADDRESS0)
-
-/* I2C AR2_DUADEN mask */
-#define AR2_DUADEN_SET ((uint16_t)0x0001)
-#define AR2_DUADEN_RESET ((uint16_t)0xFFFE)
-
-/* I2C AR2_ADDRESS2 mask */
-#define AR2_ADDRESS2_RESET ((uint16_t)0xFF01)
-
-/* I2C CLKR_FAST mask */
-#define CLKR_FAST_SET ((uint16_t)0x8000)
-
-/* I2C CLKR_CLKC mask */
-#define CLKR_CLKC_SET ((uint16_t)0x0FFF)
-
-/* I2C STR_FLAG mask */
-#define STR_FLAG_MASK ((uint32_t)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define INTEN_MASK ((uint32_t)0x07000000)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the I2Cx interface.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @retval None.
- */
-void I2C_DeInit(I2C_TypeDef *I2Cx)
-{
- if (I2Cx == I2C1) {
- /* Enable I2C1 reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C1RST, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C1RST, DISABLE);
- } else {
- /* Enable I2C2 reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C2RST, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C2RST, DISABLE);
- }
-}
-
-/**
- * @brief Initialize the I2Cx interface parameters.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_InitParaStruct: the sturct I2C_InitPara pointer.
- * @retval None.
- */
-void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitPara *I2C_InitParaStruct)
-{
- uint16_t temp = 0, freqrange = 0;
- uint16_t result = 0x04;
- uint32_t pclk1 = 8000000;
- RCC_ClocksPara rcc_clocks;
-
- /* Disable I2C */
- I2Cx->CTLR1 &= CTLR1_I2CEN_RESET;
-
- /* CTLR2 */
- temp = I2Cx->CTLR2;
-
- /* I2CCLK[5:0] */
- temp &= CTLR2_I2CCLK_RESET;
- RCC_GetClocksFreq(&rcc_clocks);
- pclk1 = rcc_clocks.APB1_Frequency;
- freqrange = (uint16_t)(pclk1 / 1000000);
- if (freqrange > I2CCLK_FREQ_MAX) {
- freqrange = I2CCLK_FREQ_MAX;
- }
- temp |= freqrange;
- I2Cx->CTLR2 = temp;
-
- /* RTR and CLKR */
- temp = 0;
-
- if (I2C_InitParaStruct->I2C_BitRate <= 100000) {
- /* Standard mode */
- result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate << 1));
- if (result < 0x04) {
- /* The CLKR.CLKC higher than 0x04 in standard mode*/
- result = 0x04;
- }
- temp |= result;
- I2Cx->CLKR = temp;
-
- /* RTR */
- if (freqrange >= I2CCLK_FREQ_MAX) {
- I2Cx->RTR = I2CCLK_FREQ_MAX;
- } else {
- I2Cx->RTR = freqrange + 1;
- }
- } else {
- /* Fast mode */
- if (I2C_InitParaStruct->I2C_DutyCycle == I2C_DUTYCYCLE_2) {
- /* I2C_DutyCycle == 2 */
- result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate * 3));
- } else {
- /* I2C_DutyCycle == 16/9 */
- result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate * 25));
- result |= I2C_DUTYCYCLE_16_9;
- }
-
- if ((result & CLKR_CLKC_SET) == 0) {
- /* The CLKR.CLKC higher than 0x01 in fast mode*/
- result |= (uint16_t)0x0001;
- }
- temp |= (uint16_t)(result | CLKR_FAST_SET);
-
- /* RTR */
- I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
- }
- I2Cx->CLKR = temp;
-
- /* CTLR1 */
- I2Cx->CTLR1 |= CTLR1_I2CEN_SET;
-
- temp = I2Cx->CTLR1;
- temp &= CTLR1_CLEAR_MASK;
- temp |= (uint16_t)((uint32_t)I2C_InitParaStruct->I2C_Protocol | CTLR1_ACKEN_SET);
- I2Cx->CTLR1 = temp;
-
- /* AR1 */
- I2Cx->AR1 = (I2C_InitParaStruct->I2C_AddressingMode | I2C_InitParaStruct->I2C_DeviceAddress);
-}
-
-/**
- * @brief Initial the sturct I2C_InitPara.
- * @param I2C_InitParaStruct: the sturct I2C_InitPara pointer.
- * @retval None.
- */
-void I2C_ParaInit(I2C_InitPara *I2C_InitParaStruct)
-{
- I2C_InitParaStruct->I2C_Protocol = I2C_PROTOCOL_I2C;
- I2C_InitParaStruct->I2C_DutyCycle = I2C_DUTYCYCLE_2;
- I2C_InitParaStruct->I2C_BitRate = 10000;
- I2C_InitParaStruct->I2C_AddressingMode = I2C_ADDRESSING_MODE_7BIT;
- I2C_InitParaStruct->I2C_DeviceAddress = 0x08;
-}
-
-/**
- * @brief Enable or disable the I2Cx interface.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2Cx interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the I2Cx interface */
- I2Cx->CTLR1 |= CTLR1_I2CEN_SET;
- } else {
- /* Disable the I2Cx interface */
- I2Cx->CTLR1 &= CTLR1_I2CEN_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2Cx DMA requests.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_DMA_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the I2Cx DMA requests */
- I2Cx->CTLR2 |= CTLR2_DMAON_SET;
- } else {
- /* Disable the I2Cx DMA requests */
- I2Cx->CTLR2 &= CTLR2_DMAON_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the DMA last.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C DMA last transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_DMALastTransfer_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Next DMA transfer is the last transfer */
- I2Cx->CTLR2 |= CTLR2_DMALST_SET;
- } else {
- /* Next DMA transfer is not the last transfer */
- I2Cx->CTLR2 &= CTLR2_DMALST_RESET;
- }
-}
-
-/**
- * @brief Enable or disable I2C_CTLR1_GENSTA control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_StartOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_GENSTA control bit */
- I2Cx->CTLR1 |= CTLR1_GENSTA_SET;
- } else {
- /* Disable I2C_CTLR1_GENSTA control bit */
- I2Cx->CTLR1 &= CTLR1_GENSTA_RESET;
- }
-}
-
-/**
- * @brief Enable or disable I2C_CTLR1_GENSTP control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_StopOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_GENSTP control bit */
- I2Cx->CTLR1 |= CTLR1_GENSTP_SET;
- } else {
- /* Disable I2C_CTLR1_GENSTP control bit */
- I2Cx->CTLR1 &= CTLR1_GENSTP_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_ACKEN control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C Acknowledgement.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_Acknowledge_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_ACKEN control bit */
- I2Cx->CTLR1 |= CTLR1_ACKEN_SET;
- } else {
- /* Disable I2C_CTLR1_ACKEN control bit */
- I2Cx->CTLR1 &= CTLR1_ACKEN_RESET;
- }
-}
-
-/**
- * @brief Set the I2Cx own address2.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param Address: specifies the 7bit I2C own address2.
- * @retval None.
- */
-void I2C_OwnAddress2(I2C_TypeDef *I2Cx, uint8_t Address)
-{
- uint16_t temp = 0;
-
- temp = I2Cx->AR2;
- temp &= AR2_ADDRESS2_RESET;
- temp |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
- /* I2C_AR2_ADDRESS2 */
- I2Cx->AR2 = temp;
-}
-
-/**
- * @brief Enable or disable the I2C_AR2_DUADEN control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C dual addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_DualAddress_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the I2C_AR2_DUADEN control bit */
- I2Cx->AR2 |= AR2_DUADEN_SET;
- } else {
- /* Disable the I2C_AR2_DUADEN control bit */
- I2Cx->AR2 &= AR2_DUADEN_RESET;
- }
-}
-
-/**
- * @brief Enable or disable I2C_CTLR1_GCEN control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C General call.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_GeneralCall_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_GCEN control bit */
- I2Cx->CTLR1 |= CTLR1_GCEN_SET;
- } else {
- /* Disable I2C_CTLR1_GCEN control bit */
- I2Cx->CTLR1 &= CTLR1_GCEN_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the specified I2C interrupt.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_INT: the I2C interrupt sources.
- * This parameter can be any combination of the following values:
- * @arg I2C_INT_EIE: Error interrupt
- * @arg I2C_INT_EE: Event interrupt
- * @arg I2C_INT_BIE: Buffer interrupt
- * @param NewValue: new value of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the I2C interrupt */
- I2Cx->CTLR2 |= I2C_INT;
- } else {
- /* Disable the I2C interrupt */
- I2Cx->CTLR2 &= (uint16_t)~I2C_INT;
- }
-}
-
-/**
- * @brief Send one byte to bus.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param Data: Byte to be transmitted.
- * @retval None.
- */
-void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
-{
- /* Write Data to DTR */
- I2Cx->DTR = Data;
-}
-
-/**
- * @brief Receive one byte from the bus.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @retval The received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
-{
- /* Read the DTR register */
- return (uint8_t)I2Cx->DTR;
-}
-
-/**
- * @brief Addressing a device on the I2C bus.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param Address: the slave device's address.
- * @param I2C_Direction: Transmitter or a Receiver.
- * This parameter can be one of the following values:
- * @arg I2C_DIRECTION_TRANSMITTER: Transmitter mode
- * @arg I2C_DIRECTION_RECEIVER: Receiver mode
- * @retval None.
- */
-void I2C_AddressingDevice_7bit(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
-{
- if (I2C_Direction != I2C_DIRECTION_TRANSMITTER) {
- /* Receiver mode */
- Address |= AR1_ADDRESS0_SET;
- } else {
- /* Transmitter mode */
- Address &= AR1_ADDRESS0_RESET;
- }
- I2Cx->DTR = Address;
-}
-
-/**
- * @brief Read the I2Cx register.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_Register: the I2Cx register.
- * This parameter can be one of the following values:
- * @arg I2C_REGISTER_CTLR1: CTLR1 register.
- * @arg I2C_REGISTER_CTLR2: CTLR2 register.
- * @arg I2C_REGISTER_AR1: AR1 register.
- * @arg I2C_REGISTER_AR2: AR2 register.
- * @arg I2C_REGISTER_DTR: DTR register.
- * @arg I2C_REGISTER_STR1: STR1 register.
- * @arg I2C_REGISTER_STR2: STR2 register.
- * @arg I2C_REGISTER_CLKR: CLKR register.
- * @arg I2C_REGISTER_RTR: RTR register.
- * @retval The value of the read register.
- */
-uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t temp = 0;
-
- temp = (uint32_t) I2Cx;
- temp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint16_t *) temp);
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_SRESET control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_SoftwareReset_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_SRESET control bit */
- I2Cx->CTLR1 |= CTLR1_SRESET_SET;
- } else {
- /* Disable I2C_CTLR1_SRESET control bit */
- I2Cx->CTLR1 &= CTLR1_SRESET_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_POAP control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_NACKPosition: the position of NACK.
- * This parameter can be one of the following values:
- * @arg I2C_NACKPOSITION_NEXT: the next byte is the last received byte
- * @arg I2C_NACKPOSITION_CURRENT: the current byte is the last received byte
- * @retval None.
- */
-void I2C_NACKPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
-{
- if (I2C_NACKPosition == I2C_NACKPOSITION_NEXT) {
- /* Next byte will be the last received byte */
- I2Cx->CTLR1 |= I2C_NACKPOSITION_NEXT;
- } else {
- /* Current byte is the last received byte */
- I2Cx->CTLR1 &= I2C_NACKPOSITION_CURRENT;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_SALT control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C software reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SMBusAlertSend_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_SALT control bit */
- I2Cx->CTLR1 |= CTLR1_SALT_SET;
- } else {
- /* Disable I2C_CTLR1_SALT control bit */
- I2Cx->CTLR1 &= CTLR1_SALT_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_PECTRANS control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2C PEC transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_PECTransmit_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_PECTRANS control bit */
- I2Cx->CTLR1 |= CTLR1_PECTRANS_SET;
- } else {
- /* Disable I2C_CTLR1_PECTRANS control bit */
- I2Cx->CTLR1 &= CTLR1_PECTRANS_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_POAP control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_PECPosition: the position of PEC.
- * This parameter can be one of the following values:
- * @arg I2C_PECPOSITION_NEXT: the next byte is PEC
- * @arg I2C_PECPOSITION_CURRENT: the current byte is PEC
- * @retval None.
- */
-void I2C_PECPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
-{
- if (I2C_PECPosition == I2C_PECPOSITION_NEXT) {
- /* The next byte is PEC */
- I2Cx->CTLR1 |= I2C_PECPOSITION_NEXT;
- } else {
- /* The current byte is PEC */
- I2Cx->CTLR1 &= I2C_PECPOSITION_CURRENT;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_PECEN control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2Cx PEC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_PEC_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_PECEN control bit */
- I2Cx->CTLR1 |= CTLR1_PECEN_SET;
- } else {
- /* Disable I2C_CTLR1_PECEN control bit */
- I2Cx->CTLR1 &= CTLR1_PECEN_RESET;
- }
-}
-
-/**
- * @brief The Packet Error Checking value.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @retval The PEC value.
- */
-uint8_t I2C_GetPECValue(I2C_TypeDef *I2Cx)
-{
- /* I2C_STR2_ECV */
- return ((I2Cx->STR2) >> 8);
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_ARPEN control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2Cx ARP.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_ARP_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I2C_CTLR1_ARPEN control bit */
- I2Cx->CTLR1 |= CTLR1_ARPEN_SET;
- } else {
- /* Disable I2C_CTLR1_ARPEN control bit */
- I2Cx->CTLR1 &= CTLR1_ARPEN_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CTLR1_DISSTRC control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param NewValue: new value of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None.
- */
-void I2C_StretchClock_Enable(I2C_TypeDef *I2Cx, TypeState NewValue)
-{
- if (NewValue == DISABLE) {
- /* Enable I2C_CTLR1_DISSTRC control bit */
- I2Cx->CTLR1 |= CTLR1_DISSTRC_SET;
- } else {
- /* Enable I2C_CTLR1_DISSTRC control bit */
- I2Cx->CTLR1 &= CTLR1_DISSTRC_RESET;
- }
-}
-
-/**
- * @brief Enable or disable the I2C_CLKR_DTCY control bit.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_DutyCycle: the duty cycle in fast mode.
- * This parameter can be one of the following values:
- * @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
- * @arg I2C_DUTYCYCLE_16_9: I2C fast mode Tlow/Thigh = 16/9
- * @retval None.
- */
-void I2C_FastModeDutyCycle(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
-{
- if (I2C_DutyCycle != I2C_DUTYCYCLE_16_9) {
- /* DutyCycle=2:1 */
- I2Cx->CLKR &= I2C_DUTYCYCLE_2;
- } else {
- /* DutyCycle=16:9 */
- I2Cx->CLKR |= I2C_DUTYCYCLE_16_9;
- }
-}
-
-/**
- * @brief Detect I2Cx State Machine.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_State: I2Cx State Machine.
- * This parameter can be one of the following values:
- * @arg I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_ADDSEND
- * @arg I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_ADDSEND
- * @arg I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_SECONDADDRESS_SELECTED
- * @arg I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_SECONDADDRESS_SELECTED
- * @arg I2C_PROGRAMMINGMODE_SLAVE_GENERALCALLADDRESS_SELECTED
- * @arg I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED
- * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUMODF)
- * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED | I2C_FLAG_RXGC)
- * @arg I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED
- * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUMODF)
- * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_RXGC)
- * @arg I2C_PROGRAMMINGMODE_SLAVE_ACK_FAILURE
- * @arg I2C_PROGRAMMINGMODE_SLAVE_STOP_DETECTED
- * @arg I2C_PROGRAMMINGMODE_MASTER_SBSEND
- * @arg I2C_PROGRAMMINGMODE_MASTER_TRANSMITTER_ADDSEND
- * @arg I2C_PROGRAMMINGMODE_MASTER_RECEIVER_ADDSEND
- * @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_RECEIVED
- * @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTING
- * @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTED
- * @arg I2C_PROGRAMMINGMODE_MASTER_ADD10SEND
- * @retval The detected result(SUCCESS or ERROR).
- */
-TypeState I2C_StateDetect(I2C_TypeDef *I2Cx, uint32_t I2C_State)
-{
- uint32_t currentstate = 0;
- uint32_t flag1 = 0, flag2 = 0;
- TypeState state = ERROR;
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->STR1;
- flag2 = I2Cx->STR2;
- flag2 = flag2 << 16;
-
- /* Get the state value from I2C status register */
- currentstate = (flag1 | flag2) & STR_FLAG_MASK;
-
- if ((currentstate & I2C_State) == I2C_State) {
- /* I2C_State is detected */
- state = SUCCESS;
- } else {
- /* I2C_State is not detected */
- state = ERROR;
- }
- return state;
-}
-
-/**
- * @brief Get the I2Cx Current State.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @retval The current state.
- */
-uint32_t I2C_GetCurrentState(I2C_TypeDef *I2Cx)
-{
- uint32_t currentstate = 0;
- uint32_t flag1 = 0, flag2 = 0;
-
- /* Read the I2Cx status register */
- flag1 = I2Cx->STR1;
- flag2 = I2Cx->STR2;
- flag2 = flag2 << 16;
-
- /* Get the last event value from I2C status register */
- currentstate = (flag1 | flag2) & STR_FLAG_MASK;
-
- return currentstate;
-}
-
-/**
- * @brief Get the bit flag of STRx registers.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_FLAG: the flag of STRx registers.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_DUMODF: Dual flag (Slave mode)
- * @arg I2C_FLAG_HSTSMB: SMBus host header (Slave mode)
- * @arg I2C_FLAG_DEFSMB: SMBus default header (Slave mode)
- * @arg I2C_FLAG_RXGC: General call header flag (Slave mode)
- * @arg I2C_FLAG_TRS: Transmitter or Receiver flag
- * @arg I2C_FLAG_I2CBSY: Bus busy flag
- * @arg I2C_FLAG_MASTER: Master or Slave flag
- * @arg I2C_FLAG_SMBALTS: SMBus Alert flag
- * @arg I2C_FLAG_SMBTO: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECE: PEC error in reception flag
- * @arg I2C_FLAG_RXORE: Overrun or Underrun flag (Slave mode)
- * @arg I2C_FLAG_AE: Acknowledge failure flag
- * @arg I2C_FLAG_LOSTARB: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BE: Bus error flag
- * @arg I2C_FLAG_TBE: Data register empty flag (Transmitter)
- * @arg I2C_FLAG_RBNE: Data register not empty (Receiver) flag
- * @arg I2C_FLAG_STPSEND: Stop detection flag (Slave mode)
- * @arg I2C_FLAG_ADD10SEND: 10-bit header sent flag (Master mode)
- * @arg I2C_FLAG_BTC: Byte transfer finished flag
- * @arg I2C_FLAG_ADDSEND: Address sent flag (Master mode) or Address matched flag (Slave mode)
- * @arg I2C_FLAG_SBSEND: Start bit flag (Master mode)
- * @retval The new value of I2C_FLAG (SET or RESET).
- */
-TypeState I2C_GetBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
-{
- __IO uint32_t i2creg = 0, i2cxbase = 0;
-
- /* Get the I2Cx peripheral base address */
- i2cxbase = (uint32_t)I2Cx;
-
- /* Read flag register index */
- i2creg = I2C_FLAG >> 28;
-
- /* Get bit[23:0] of the flag */
- I2C_FLAG &= STR_FLAG_MASK;
-
- if (i2creg != 0) {
- /* Flag in I2Cx STR1 register */
- i2cxbase += 0x14;
- } else {
- /* Flag in I2Cx STR2 Register */
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
- /* Get the I2Cx STR2 register address */
- i2cxbase += 0x18;
- }
-
- if (((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) {
- /* I2C_FLAG is set */
- return SET;
- } else {
- /* I2C_FLAG is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the bit flag of STRx registers.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_FLAG: the flag of STRx registers.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALTS: SMBus Alert flag
- * @arg I2C_FLAG_SMBTO: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECE: PEC error in reception flag
- * @arg I2C_FLAG_RXORE: Overrun or Underrun flag (Slave mode)
- * @arg I2C_FLAG_AE: Acknowledge failure flag
- * @arg I2C_FLAG_LOSTARB: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BE: Bus error flag
- * @retval None.
- */
-void I2C_ClearBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t flagpos = 0;
-
- /* Get the I2C flag position */
- flagpos = I2C_FLAG & STR_FLAG_MASK;
- /* Clear the selected I2C flag */
- I2Cx->STR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @brief Get the interrupt bit flag.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_INT: the interrupt bit flag.
- * This parameter can be one of the following values:
- * @arg I2C_INT_SMBALTS: SMBus Alert flag
- * @arg I2C_INT_SMBTO: Timeout or Tlow error flag
- * @arg I2C_INT_PECE: PEC error in reception flag
- * @arg I2C_INT_RXORE: Overrun or Underrun flag (Slave mode)
- * @arg I2C_INT_AE: Acknowledge failure flag
- * @arg I2C_INT_LOSTARB: Arbitration lost flag (Master mode)
- * @arg I2C_INT_BE: Bus error flag
- * @arg I2C_INT_TBE: Data register empty flag (Transmitter)
- * @arg I2C_INT_RBNE: Data register not empty (Receiver) flag
- * @arg I2C_INT_STPSEND: Stop detection flag (Slave mode)
- * @arg I2C_INT_ADD10SEND: 10-bit header sent flag (Master mode)
- * @arg I2C_INT_BTC: Byte transfer finished flag
- * @arg I2C_INT_ADDSEND: Address sent flag (Master mode) or Address matched flag (Slave mode)
- * @arg I2C_INT_SBSEND: Start bit flag (Master mode)
- * @retval The new value of I2C_INT (SET or RESET).
- */
-TypeState I2C_GetIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT)
-{
- uint32_t enablestatus = 0;
-
- /* Check if the interrupt source is enabled or not */
- enablestatus = (uint32_t)(((I2C_INT & INTEN_MASK) >> 16) & (I2Cx->CTLR2)) ;
-
- /* Get bit[23:0] of the flag */
- I2C_INT &= STR_FLAG_MASK;
-
- if (((I2Cx->STR1 & I2C_INT) != (uint32_t)RESET) && enablestatus) {
- /* I2C_INT is set */
- return SET;
- } else {
- /* I2C_INT is reset */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt bit flag.
- * @param I2Cx: the I2C interface where x can be 1 or 2.
- * @param I2C_INT: the interrupt bit flag.
- * This parameter can be any combination of the following values:
- * @arg I2C_INT_SMBALTS: SMBus Alert interrupt
- * @arg I2C_INT_SMBTO: Timeout or Tlow error interrupt
- * @arg I2C_INT_PECE: PEC error in reception interrupt
- * @arg I2C_INT_RXORE: Overrun or Underrun interrupt (Slave mode)
- * @arg I2C_INT_AE: Acknowledge failure interrupt
- * @arg I2C_INT_LOSTARB: Arbitration lost interrupt (Master mode)
- * @arg I2C_INT_BE: Bus error interrupt
- * @retval None.
- */
-void I2C_ClearIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT)
-{
- uint32_t flagpos = 0;
-
- /* Get the I2C flag position */
- flagpos = I2C_INT & STR_FLAG_MASK;
- /* Clear the selected I2C flag */
- I2Cx->STR1 = (uint16_t)~flagpos;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c
deleted file mode 100644
index 1032f064e5..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
- ******************************************************************************
- * @brief IWDG functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_iwdg.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/** @defgroup IWDG_Private_Variables
- * @{
- */
-
-/* CTLR register bit mask */
-#define CTLR_KEY_RELOAD ((uint16_t)0xAAAA)
-#define CTLR_KEY_ENABLE ((uint16_t)0xCCCC)
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/**
- * @brief Enable or disable the IWDG_PSR, IWDG_RLDR and IWDG_WND write protection.
- * @param IWDG_WriteAccess: value to enable or disable the write access to registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WRITEACCESS_ENABLE: Enable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers
- * @arg IWDG_WRITEACCESS_DISABLE: Disable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers
- * @retval None
- */
-void IWDG_Write_Enable(uint16_t IWDG_WriteAccess)
-{
- IWDG->CTLR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Set IWDG prescaler value.
- * @param PrescalerValue: IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_PRESCALER_4: IWDG prescaler set to 4
- * @arg IWDG_PRESCALER_8: IWDG prescaler set to 8
- * @arg IWDG_PRESCALER_16: IWDG prescaler set to 16
- * @arg IWDG_PRESCALER_32: IWDG prescaler set to 32
- * @arg IWDG_PRESCALER_64: IWDG prescaler set to 64
- * @arg IWDG_PRESCALER_128: IWDG prescaler set to 128
- * @arg IWDG_PRESCALER_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t PrescalerValue)
-{
- IWDG->PSR = PrescalerValue;
-}
-
-/**
- * @brief Set independent watchdog counter reload value.
- * @param ReloadValue: IWDG Reload value.
- * This parameter must be between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReloadValue(uint16_t ReloadValue)
-{
- IWDG->RLDR = ReloadValue;
-}
-
-/**
- * @brief Reload the counter.
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->CTLR = CTLR_KEY_RELOAD;
-}
-
-/**
- * @brief Start the independent watchdog counter.
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->CTLR = CTLR_KEY_ENABLE;
-}
-
-/**
- * @brief Check registers' bit state.
- * @param IWDG_FLAG: the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_BIT_PUD: A write operation to IWDG_PSR register on going
- * @arg IWDG_BIT_RUD: A write operation to IWDG_RLDR register on going
- * @arg IWDG_BIT_WUD: A write operation to IWDG_WND register on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-TypeState IWDG_GetBitState(uint16_t IWDG_FLAG)
-{
- if ((IWDG->STR & IWDG_FLAG) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c
deleted file mode 100644
index 03b0618344..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- ******************************************************************************
- * @brief MCUDBG functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_mcudbg.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup MCUDBG
- * @brief MCUDBG driver modules
- * @{
- */
-
-
-/** @defgroup MCUDBG_Private_Defines
- * @{
- */
-
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-/**
- * @}
- */
-
-
-/** @defgroup MCUDBG_Private_Functions
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t MCUDBG_GetREVID(void)
-{
- return (MCUDBG->IDR >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t MCUDBG_GetDEVID(void)
-{
- return (MCUDBG->IDR & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Configure the specified peripheral and low power mode behavior
- * when the MCU under Debug mode.
- * @param MCUDBG_Periph: specifies the peripheral and low power mode.
- * This parameter can be any combination of the following values:
- * @arg MCUDBG_SLEEP_HOLD: Keep debugger connection during SLEEP mode
- * @arg MCUDBG_DEEPSLEEP_HOLD: Keep debugger connection during DEEPSLEEP mode
- * @arg MCUDBG_STDBY_HOLD: Keep debugger connection during STANDBY mode
- * @arg MCUDBG_IWDG_HOLD: Debug IWDG hold when Core is halted
- * @arg MCUDBG_WWDG_HOLD: Debug WWDG hold when Core is halted
- * @arg MCUDBG_TIMER1_HOLD: TIMER1 counter hold when Core is halted
- * @arg MCUDBG_TIMER2_HOLD: TIMER2 counter hold when Core is halted
- * @arg MCUDBG_TIMER3_HOLD: TIMER3 counter hold when Core is halted
- * @arg MCUDBG_TIMER4_HOLD: TIMER4 counter hold when Core is halted
- * @arg MCUDBG_CAN1_HOLD: Debug CAN1 hold when Core is halted
- * @arg MCUDBG_I2C1_HOLD: I2C1 SMBUS timeout mode hold when Core is halted
- * @arg MCUDBG_I2C2_HOLD: I2C2 SMBUS timeout mode hold when Core is halted
- * @arg MCUDBG_TIMER5_HOLD: TIMER5 counter hold when Core is halted
- * @arg MCUDBG_TIMER6_HOLD: TIMER6 counter hold when Core is halted
- * @arg MCUDBG_TIMER7_HOLD: TIMER7 counter hold when Core is halted
- * @arg MCUDBG_TIMER8_HOLD: TIMER8 counter hold when Core is halted
- * @arg MCUDBG_CAN2_HOLD: Debug CAN2 hold when Core is halted
- * @arg MCUDBG_TIMER12_HOLD: TIMER12 counter hold when Core is halted
- * @arg MCUDBG_TIMER13_HOLD: TIMER13 counter hold when Core is halted
- * @arg MCUDBG_TIMER14_HOLD: TIMER14 counter hold when Core is halted
- * @arg MCUDBG_TIMER9_HOLD: TIMER9 counter hold when Core is halted
- * @arg MCUDBG_TIMER10_HOLD: TIMER10 counter hold when Core is halted
- * @arg MCUDBG_TIMER11_HOLD: TIMER11 counter hold when Core is halted
- * @param NewState: new state of the specified peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- MCUDBG->CTLR |= MCUDBG_Periph;
- } else {
- MCUDBG->CTLR &= ~MCUDBG_Periph;
- }
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c
deleted file mode 100644
index cee195ebc5..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/**
- ******************************************************************************
- * @brief MISC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_misc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/** @defgroup MISC_Private_Defines
- * @{
- */
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-
-/**
- * @brief By the PRIGROUP[10:8] bits of the AIRCR register, Setting the priority grouping:
- * pre-emption priority and subpriority.
- * @param NVIC_PriGroup: NVIC_PRIGROUP_0, NVIC_PRIGROUP_1,...NVIC_PRIGROUP_4.
- * @retval None
- */
-void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup)
-{
- /* Set the priority grouping value */
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PRIGroup;
-}
-
-/**
- * @brief The NVIC peripheral Initialization.
- * @param NVIC_InitStruct: a NVIC_InitPara structure pointer.
- * @retval None
- */
-void NVIC_Init(NVIC_InitPara *NVIC_InitStruct)
-{
- uint32_t temppriority = 0x00, temppreempt = 0x00, tempsub = 0x00;
-
- if (NVIC_InitStruct->NVIC_IRQEnable != DISABLE) {
- if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_0) {
- temppreempt = 0;
- tempsub = 0x4;
- } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_1) {
- temppreempt = 1;
- tempsub = 0x3;
- } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_2) {
- temppreempt = 2;
- tempsub = 0x2;
- } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_3) {
- temppreempt = 3;
- tempsub = 0x1;
- } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_4) {
- temppreempt = 4;
- tempsub = 0x0;
- }
-
- temppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQPreemptPriority << (0x4 - temppreempt);
- temppriority |= NVIC_InitStruct->NVIC_IRQSubPriority & (0x0F >> (0x4 - tempsub));
- temppriority = temppriority << 0x04;
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQ] = temppriority;
-
- /* Enable the Selected IRQ Channels */
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F);
- } else {
- /* Disable the Selected IRQ Channels */
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Specify the vector table in RAM or FLASH memory and its Offset.
- * @param NVIC_VectTab: NVIC_VECTTAB_RAM,NVIC_VECTTAB_FLASH
- * @param Offset: Vector Table start address.
- * @retval None
- */
-void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset)
-{
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-/**
- * @brief Specify the state of the system to enter low power mode.
- * @param LowPowerMode: NVIC_LOWPOWER_SEVONPEND,NVIC_LOWPOWER_SLEEPDEEP,NVIC_LOWPOWER_SLEEPONEXIT.
- * @param NewValue: new value of Low Power state. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SCB->SCR |= LowPowerMode;
- } else {
- SCB->SCR &= (~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Specify the SysTick clock source.
- * @param SysTick_CKSource: SYSTICK_CKSOURCE_HCLK_DIV8,SYSTICK_CKSOURCE_HCLK.
- * @retval None
- */
-void SysTick_CKSource_Enable(uint32_t SysTick_CKSource)
-{
- if (SysTick_CKSource == SYSTICK_CKSOURCE_HCLK) {
- SysTick->CTRL |= SYSTICK_CKSOURCE_HCLK;
- } else {
- SysTick->CTRL &= SYSTICK_CKSOURCE_HCLK_DIV8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c
deleted file mode 100644
index cd44b98dfe..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/**
- ******************************************************************************
- * @brief PWR functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_pwr.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/** @defgroup PWR_Private_Defines
- * @{
- */
-/* Left shift SBF or WUF(PWR_STR) to SBFR or WUFR(PWR_CTLR) */
-#define BIT_SHIFT 2
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the PWR peripheral registers.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_PWRRST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_PWRRST, DISABLE);
-}
-
-/**
- * @brief Enable or disable write access to the registers in Backup domain.
- * @note After reset, any write access to the registers in Backup domain is disabled.
- * This bit has to be set to enable write access to these registers.
- * @param NewValue: New value of write access state to the registers in Backup domain.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccess_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the Backup Domain Access */
- PWR->CTLR |= PWR_CTLR_BKPWE;
- } else {
- /* Disable the Backup Domain Access */
- PWR->CTLR &= ~((uint32_t)PWR_CTLR_BKPWE);
- }
-}
-
-/**
- * @brief Enable or disable the LVD(Low Voltage Detector), and configure the voltage
- * threshold detected by the LVD.
- * @note The LVDE bit controls whether LVD is enabled or not, while the LVDT[2:0]
- * bits select the LVDT from 2.2V to 2.9V.
- * @note The LVD is stopped in Standby mode.
- * @param PWR_LVDT: the LVD threshold.
- * This parameter can be one of the following values:
- * @arg PWR_LVDT_0
- * @arg PWR_LVDT_1
- * @arg PWR_LVDT_2
- * @arg PWR_LVDT_3
- * @arg PWR_LVDT_4
- * @arg PWR_LVDT_5
- * @arg PWR_LVDT_6
- * @arg PWR_LVDT_7
- * @param NewValue: New value of the LVD state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue)
-{
- uint32_t temp = 0;
-
- temp = PWR->CTLR;
-
- /* Clear LVDT[7:5] bits */
- temp &= ~((uint32_t)PWR_CTLR_LVDT);
-
- /* Set LVDT[7:5] bits according to PWR_LVDT value */
- temp |= PWR_LVDT;
-
- /* Store the new value */
- PWR->CTLR = temp;
-
- /* Enable or disable the LVD */
- if (NewValue != DISABLE) {
- /* Enable the LVD */
- PWR->CTLR |= PWR_CTLR_LVDE;
- } else {
- /* Disable the LVD */
- PWR->CTLR &= ~((uint32_t)PWR_CTLR_LVDE);
- }
-}
-
-/**
- * @brief Enable or disable the WakeUp Pin(PA0 pin) function.
- * @note If WUPE is set before entering the power saving mode,
- * a rising edge on the WKUP Pin wakes up the system from the power
- * saving mode. As the WKUP pin is active high, it will setup
- * an input pull down mode when this bit is high.
- * @param NewValue: New value of the WKUP Pin state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WKUP_Pin_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the WKUP pin */
- PWR->STR |= PWR_STR_WUPE;
- } else {
- /* Disable the WKUP pin */
- PWR->STR &= ~PWR_STR_WUPE;
- }
-}
-
-/**
- *@verbatim
-
- [..] The GD32F10x series of devices provide three types of power saving modes.
-
- *** Sleep mode ***
- ==================
- [..] The Sleep mode is based on the SLEEPING mode of the Cortex-M3. In Sleep
- mode, only clock of Cortex-M3 is off.
- (+) Entry:
- (++) To enter the Sleep mode, it is only necessary to clear SLEEPDEEP bit
- in the Cortex-M3 System Control Register, and execute a WFI or WFE
- instruction.
- (++) The Sleep mode is entered using the PWR_SLEEPMode_Entry() function.
- (+) Wakeup:
- (++) Any interrupt for WFI or Any event for WFE.
- (+) Wakeup Latency:
- (++) None
-
- *** Deep-sleep mode ***
- =================
- [..] The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex-M3. In
- Deep-sleep mode, all clocks in the 1.2V domain are off, and all of HSI,
- HSE and PLL are disabled. The LDO can operate normally or in low
- power mode depending on the LDOLP bit in the PWR_CTLR register.
- (+) Entry:
- (++) Before entering the Deep-sleep mode, it is necessary to set the
- SLEEPDEEP bit in the Cortex-M3 System Control Register, and clear
- the SDBM bit in the PWR_CTLR register.
- (++) The Deep-sleep mode is entered using the PWR_DEEPSLEEPMode_Entry()
- function.
- (+) Wakeup:
- (++) Any interrupt or event from EXTI Lines.
- (+) Wakeup Latency:
- (++) HSI wakeup time; LDO wakeup time if LDO is in low power mode.
-
- *** Standby mode ***
- ====================
- [..] The Standby mode is based on the SLEEPDEEP mode of the Cortex-M3. In Standby
- mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
- HSI, HSE and PLL are disabled. Besides, the contents of SRAM and
- registers(except Backup Registers) are lost in Standby mode.
- (+) Entry:
- (++) Before entering the Standby mode, it is necessary to set the
- SLEEPDEEP bit in the Cortex-M3 System Control Register, and set
- the SDBM bit in the PWR_CTLR register, and clear WUF bit in the
- PWR_STR register. .
- (++) The Standby mode is entered using the PWR_STDBYMode_Entry() function.
- (+) Wakeup:
- (++) NRST pin, WKUP pin rising edge, RTC alarm, IWDG reset.
- (+) Wakeup Latency:
- (++) Power on sequence
- *@endverbatim
- */
-/**
- * @brief Enter Sleep mode.
- * @note By default, this function selects the Sleep-now entry mechanism (SLEEPONEXIT = 0).
- * @param PWR_SLEEPENTRY: WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction
- * @arg PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction
- * @retval None
- */
-void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY)
-{
- /* Clear SLEEPDEEP bit of Cortex-M3 System Control Register */
- SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
- /* Select WFI or WFE to enter Sleep mode */
- if (PWR_SLEEPENTRY == PWR_SLEEPENTRY_WFI) {
- __WFI();
- } else {
- __WFE();
- }
-}
-
-/**
- * @brief Enter Deep-sleep mode.
- * @note When exiting Deep-sleep mode, the HSI is selected as the system clock.
- * @note An additional wakeup delay will be incurred if the LDO operates in
- * low power mode.
- * @param PWR_LDO: the LDO state in Deep-sleep mode.
- * This parameter can be one of the following values:
- * @arg PWR_LDO_ON: Deep-sleep mode with LDO ON
- * @arg PWR_LDO_LOWPOWER: Deep-sleep mode with LDO in low power mode
- * @param PWR_DEEPSLEEPENTRY: WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_DEEPSLEEPENTRY_WFI: enter Deep-sleep mode with WFI instruction
- * @arg PWR_DEEPSLEEPENTRY_WFE: enter Deep-sleep mode with WFE instruction
- * @retval None
- */
-void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY)
-{
- uint32_t temp = 0;
-
- /* Select the LDO state in Deep-sleep mode */
- temp = PWR->CTLR;
-
- /* Clear SDBM and LDOLP bits, and select Deep-sleep mode */
- temp &= ~((uint32_t)(PWR_CTLR_SDBM | PWR_CTLR_LDOLP));
-
- /* Set LDOLP bit according to PWR_LDO value, and select the LDO's state */
- temp |= PWR_LDO;
-
- /* Store the new value */
- PWR->CTLR = temp;
-
- /* Set SLEEPDEEP bit of Cortex-M3 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select WFI or WFE to enter Deep-sleep mode */
- if (PWR_DEEPSLEEPENTRY == PWR_DEEPSLEEPENTRY_WFI) {
- __WFI();
- } else {
- __SEV();
- __WFE();
- __WFE();
- }
- /* Reset SLEEPDEEP bit of Cortex-M3 System Control Register */
- SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/**
- * @brief Enter Standby mode.
- * @note The Standby mode achieves the lowest power consumption, but spends
- * longest time to wake up.
- * @note When exiting from the Standby mode, a power-on reset occurs and the
- * Cortex-M3 will execute instructions code from the 0x0000_0000 address.
- * @param PWR_STDBYENTRY: WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STDBYENTRY_WFI: enter Standby mode with WFI instruction
- * @arg PWR_STDBYENTRY_WFE: enter Standby mode with WFE instruction
- * @retval None
- */
-void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY)
-{
- /* Set SLEEPDEEP bit of Cortex-M3 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Set SDBM bit, and select Standby mode */
- PWR->CTLR |= PWR_CTLR_SDBM;
-
- /* Reset Wakeup flag */
- PWR->CTLR |= PWR_CTLR_WUFR;
-
- /* Select WFI or WFE to enter Standby mode */
- if (PWR_STDBYENTRY == PWR_STDBYENTRY_WFI) {
- __WFI();
- } else {
- __WFE();
- }
-}
-
-/**
- * @brief Get the bit flag of some PWR_STR registers.
- * @param PWR_FLAG: the flag of PWR_STR registers.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WKUP: WakeUp flag. This flag indicates that a wakeup
- * event was received from the WKUP pin or from the RTC alarm,
- * IWDG reset or NRST pin.
- * @arg PWR_FLAG_STB: StandBy flag. This flag indicates that the
- * system has been in Standby mode.
- * @arg PWR_FLAG_LVDF: LVD State flag. This flag is valid only if LVD
- * is enabled by the PWR_LVD_Config()function.
- * @retval The new value of PWR_FLAG (SET or RESET).
- */
-TypeState PWR_GetBitState(uint32_t PWR_FLAG)
-{
- /* Check and get the selected PWR flag */
- if ((PWR->STR & PWR_FLAG) != (uint32_t)RESET) {
- /* PWR_FLAG bit is SET */
- return SET;
- } else {
- /* PWR_FLAG bit is RESET */
- return RESET;
- }
-}
-
-/**
- * @brief Clear the bit flag of some PWR_STR registers.
- * @param PWR_FLAG: the flag of PWR_STR registers.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WKUP: Wake_Up flag
- * @arg PWR_FLAG_STB: StandBy flag
- * @retval None
- */
-void PWR_ClearBitState(uint32_t PWR_FLAG)
-{
- /* Clear the selected PWR flag */
- PWR->CTLR |= PWR_FLAG << BIT_SHIFT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c
deleted file mode 100644
index f14e848695..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c
+++ /dev/null
@@ -1,1323 +0,0 @@
-/**
- ******************************************************************************
- * @brief RCC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/** @defgroup RCC_Private_Defines
- * @{
- */
-
-
-/* RCC GCCR_HSIEN mask */
-#define GCCR_HSIEN_SET ((uint32_t)0x00000001)
-
-/* RCC GCFGR_Reset mask */
-#define GCFGR_RESET_CL ((uint32_t)0xE0FF0000)
-#define GCFGR_RESET ((uint32_t)0xE8FF0000)
-
-/* RCC GCCR_HSEEN_CKMEN_PLLEN masks */
-#define GCCR_HSEEN_CKMEN_PLLEN_RESET ((uint32_t)0xFEF6FFFF)
-
-/* RCC GCCR_HSEBPS mask */
-#define GCCR_HSEBPS_RESET ((uint32_t)0xFFFBFFFF)
-
-/* RCC GCFGR_PLLSEL_PLLPREDV_PLLMF masks */
-#define GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET ((uint32_t)0xF700FFFF)
-#define GCFGR_PLLSEL_PLLPREDV_PLLMF_OTGFSPS_RESET_CL ((uint32_t)0xDF00FFFF)
-
-/* RCC GCCR_PLL2EN_PLL3EN masks */
-#define GCCR_PLL2EN_PLL3EN_RESET ((uint32_t)0xEBFFFFFF)
-
-/* RCC GCFGR2 reset */
-#define GCFGR2_RESET ((uint32_t)0x00000000)
-
-/* RCC GCIR_INT ans FLAG masks */
-#define GCIR_INT_FLAG_RESET ((uint32_t)0x009F0000)
-#define GCIR_INT_FLAG_RESET_CL ((uint32_t)0x00FF0000)
-
-#define GCCR_HSEEN_HSEBPS_RESET ((uint32_t)0xFFFAFFFF)
-
-/* RCC GCCR_HSIADJ masks */
-#define GCCR_HSIADJ_OFFSET ((uint32_t)0x00000003)
-
-
-#define RCC_GCFGR_PLLMF_3_0 ((uint32_t)0x003C0000) /*!< PLLMF[3:0] Bits */
-
-/* RCC HSI clock divided by 2 masks */
-#define HSI_CLOCK_DIVIDED_2 ((uint32_t)0x00000001)
-
-/* RCC HSE clock divided by 2 masks */
-#define HSE_CLOCK_DIVIDED_2 ((uint32_t)0x00000001)
-
-
-static __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-static __I uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-
-/* GCIR register byte 1 (Bits[15:8]) base address */
-#define GCIR_BYTE1_ADDRESS ((uint32_t)0x40021009)
-
-/* GCIR register byte 2 (Bits[23:16]) base address */
-#define GCIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)
-
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration.
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set RCC GCCR_HSIEN mask */
- RCC->GCCR |= GCCR_HSIEN_SET;
-
- /* Reset SCS[1:0], AHBPS[3:0], APB1PS[2:0],APB2PS[2:0], ADCPS[2:0],CKOTUSEL[2:0] bits */
-#ifdef GD32F10X_CL
- RCC->GCFGR &= GCFGR_RESET_CL;
-#else
- RCC->GCFGR &= GCFGR_RESET;
-#endif /* GD32F10X_CL */
-
- /* Reset HSEEN, CKMEN and PLLEN bits */
- RCC->GCCR &= GCCR_HSEEN_CKMEN_PLLEN_RESET;
-
- /* Reset HSEBPS bit */
- RCC->GCCR &= GCCR_HSEBPS_RESET;
-
- /* Reset PLLSEL, PLLPREDV and PLLMF[4:0] USBPS/OTGFSPS bits */
-#ifdef GD32F10X_CL
- RCC->GCFGR &= GCFGR_PLLSEL_PLLPREDV_PLLMF_OTGFSPS_RESET_CL;
-#else
- RCC->GCFGR &= GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET;
-#endif /* GD32F10X_CL */
-
-#ifdef GD32F10X_CL
- /* Reset PLL2EN and PLL3EN bits */
- RCC->GCCR &= GCCR_PLL2EN_PLL3EN_RESET;
-
- /* Reset GCFGR2 register */
- RCC->GCFGR2 = GCFGR2_RESET ;
-
- /* Disable all interrupts and clear flag bits */
- RCC->GCIR = GCIR_INT_FLAG_RESET_CL;
-#else
- /* Disable all interrupts and clear flag bits */
- RCC->GCIR = GCIR_INT_FLAG_RESET;
-#endif /* GD32F10X_CL */
-}
-
-/**
- * @brief Configure the External High Speed oscillator (HSE).
- * @param RCC_HSE: specify the new state of HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn off the HSE
- * @arg RCC_HSE_ON: turn on the HSE
- * @arg RCC_HSE_BYPASS: HSE bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint32_t RCC_HSE)
-{
- /* Reset HSEEN and HSEBPS bits */
- RCC->GCCR &= GCCR_HSEEN_HSEBPS_RESET;
- /* Set the new state of HSE */
- RCC->GCCR |= RCC_HSE;
-
-}
-
-/**
- * @brief Wait for HSE start-up.
- * @param None
- * @retval The HSE start-up result(SUCCESS or ERROR)
- */
-TypeState RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t HSE_StartOk_Counter = 0;
- TypeState HSEState = RESET;
-
- /* Wait until HSE is ready and if timeout to exit */
- while ((HSE_StartOk_Counter != HSE_STARTUP_TIMEOUT) && (HSEState == RESET)) {
- HSEState = RCC_GetBitState(RCC_FLAG_HSESTB);
- HSE_StartOk_Counter++;
- }
-
- if (RCC_GetBitState(RCC_FLAG_HSESTB) != RESET) {
- return SUCCESS;
- } else {
- return ERROR;
- }
-}
-
-/**
- * @brief Adjust the Internal High Speed oscillator (HSI) calibration value.
- * @param HSICalibrationValue: the HSI calibration value.
- * This parameter must be between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t temp_adjust = 0;
-
- temp_adjust = RCC->GCCR;
-
- /* Clear HSIADJ[4:0] bits */
- temp_adjust &= ~RCC_GCCR_HSIADJ;
-
- /* Set HSIADJ[4:0] bits according to HSICalibrationValue value */
- temp_adjust |= (uint32_t)HSICalibrationValue << GCCR_HSIADJ_OFFSET ;
-
- /* Store the calibration value */
- RCC->GCCR = temp_adjust;
-}
-
-/**
- * @brief Enable or disable the Internal High Speed oscillator (HSI).
- * @param NewValue: new value of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSI_Enable(TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- RCC->GCCR |= RCC_GCCR_HSIEN;
- } else {
- RCC->GCCR &= ~RCC_GCCR_HSIEN;
- }
-}
-
-/**
- * @brief Configure the PLL clock source and multiplication factor.
- * @param RCC_PLLSelect: specify the PLL clock source.
- * For @b GD32_Connectivity_line_devices, this parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_HSI_DIV2: HSI divided by 2 selected as PLL clock source
- * @arg RCC_PLLSOURCE_PREDIV1: PREDIV1 clock selected as PLL clock source
- * For @b other GD32_devices, this parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_HSI_DIV2: HSI divided by 2 selected as PLL clock source
- * @arg RCC_PLLSOURCE_HSE_DIV1: HSE selected as PLL clock source
- * @arg RCC_PLLSOURCE_HSE_DIV2: HSE divided by 2 selected as PLL clock source
- * @param RCC_PLLMF: specify the PLL multiplication factor.
- * For @b GD32_Connectivity_line_devices, this parameter can be RCC_PLLMUL_x where x:{[2,32], 6_5}
- * For @b other_GD32_devices, this parameter can be RCC_PLLMUL_x where x:[2,32]
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSelect, uint32_t RCC_PLLMF)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR;
- /* Clear PLLSEL [16] and PLLMF[4:0] bits */
- temp &= ~(RCC_GCFGR_PLLMF | RCC_GCFGR_PLLSEL);
- /* Set the PLLSEL and PLLMF */
- temp |= RCC_PLLSelect | RCC_PLLMF;
-
- RCC->GCFGR = temp;
-}
-
-/**
- * @brief Enable or disable the PLL.
- * @param NewValue: new value of the PLL.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLL_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->GCCR |= RCC_GCCR_PLLEN;
- } else {
- RCC->GCCR &= ~RCC_GCCR_PLLEN;
- }
-}
-
-
-#ifdef GD32F10X_CL
-/**
- * @brief Configure the PREDV1 division factor.
- * @param RCC_PREDV1_Source: specifies the PREDV1 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PREDIV1_SOURCE_HSE: HSE selected as PREDIV1 clock
- * @arg RCC_PREDIV1_SOURCE_PLL2: PLL2 selected as PREDIV1 clock
- * @param RCC_PREDV1_DIV: specify the PREDV1 division factor.
- * This parameter can be RCC_PREDIV1_DIVx where x:[1,16]
- * @retval None
- */
-void RCC_PREDV1Config(uint32_t RCC_PREDV1_Source, uint32_t RCC_PREDV1_Div)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR2;
- /* Clear PREDV1[3:0] and PREDV1SEL bits */
- temp &= ~(RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL);
- /* Set the PREDV1 division factor and PREDV1SEL */
- temp |= (RCC_PREDV1_Div | RCC_PREDV1_Source);
-
- RCC->GCFGR2 = temp;
-}
-
-/**
- * @brief Configure the PREDV2 division factor.
- * @param RCC_PREDV2_Div: specify the PREDV2 clock division factor.
- * This parameter can be RCC_PREDIV2_DIVx where x:[1,16]
- * @retval None
- */
-void RCC_PREDV2Config(uint32_t RCC_PREDV2_Div)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR2;
- /* Clear PREDV2[3:0] bits */
- temp &= ~RCC_GCFGR2_PREDV2;
- /* Set the PREDV2 division factor */
- temp |= RCC_PREDV2_Div;
-
- RCC->GCFGR2 = temp;
-}
-
-/**
- * @brief Configure the PLL2 multiplication factor.
- * @param RCC_PLL2MF: specify the PLL2 multiplication factor.
- * This parameter can be RCC_PLL2MUL_x where x:{[8,14], 16, 20}
- * @retval None
- */
-void RCC_PLL2Config(uint32_t RCC_PLL2MF)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR2;
- /* Clear PLL2MF[3:0] bits */
- temp &= ~RCC_GCFGR2_PLL2MF;
- /* Set the PLL2 configuration bits */
- temp |= RCC_PLL2MF;
-
- RCC->GCFGR2 = temp;
-}
-
-
-/**
- * @brief Enable or disable the PLL2.
- * @param NewValue: new value of the PLL2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLL2_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->GCCR |= RCC_GCCR_PLL2EN;
- } else {
- RCC->GCCR &= ~RCC_GCCR_PLL2EN;
- }
-}
-
-
-/**
- * @brief Configure the PLL3 multiplication factor.
- * @param RCC_PLL3MF: specify the PLL3 multiplication factor.
- * This parameter can be RCC_PLL3MUL_x where x:{[8,14], 16, 20}
- * @retval None
- */
-void RCC_PLL3Config(uint32_t RCC_PLL3MF)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR2;
- /* Clear PLL2MF[3:0] bits */
- temp &= ~RCC_GCFGR2_PLL3MF;
- /* Set the PLL3 configuration bits */
- temp |= RCC_PLL3MF;
-
- RCC->GCFGR2 = temp;
-}
-
-
-/**
- * @brief Enable or disable the PLL3.
- * @param NewValue: new value of the PLL3.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLL3_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->GCCR |= RCC_GCCR_PLL3EN;
- } else {
- RCC->GCCR &= ~RCC_GCCR_PLL3EN;
- }
-}
-#endif /* GD32F10X_CL */
-
-/**
- * @brief Configure the system clock (CK_SYS)
- * @param RCC_SYSCLKSource: specify the system clock source
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSOURCE_HSI: selecte HSI as CK_SYS source
- * @arg RCC_SYSCLKSOURCE_HSE: selecte HSE as CK_SYS source
- * @arg RCC_SYSCLKSOURCE_PLLCLK: selecte PLL as CK_SYS source
- * @retval None
- */
-void RCC_CK_SYSConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR;
-
- /* Clear SCS[1:0] bits */
- temp &= ~RCC_GCFGR_SCS;
-
- /* Set SCS[1:0] bits according to RCC_SYSCLKSource value */
- temp |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->GCFGR = temp;
-}
-
-/**
- * @brief Get the system clock source.
- * @param None
- * @retval Get the system clock source. The returned value can be one
- * of the following values:
- * @arg 0x00: HSI used as CK_SYS source
- * @arg 0x04: HSE used as CK_SYS source
- * @arg 0x08: PLL used as CK_SYS source
- */
-uint8_t RCC_GetCK_SYSSource(void)
-{
- return ((uint8_t)(RCC->GCFGR & RCC_GCFGR_SCSS));
-}
-/**
- * @brief Configure the AHB clock.
- * @param RCC_CK_SYSDiv: specify the AHB clock divider. This clock is derived from
- * the system clock (CK_SYS).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_DIV1: AHB clock = CK_SYS
- * @arg RCC_SYSCLK_DIV2: AHB clock = CK_SYS/2
- * @arg RCC_SYSCLK_DIV4: AHB clock = CK_SYS/4
- * @arg RCC_SYSCLK_DIV8: AHB clock = CK_SYS/8
- * @arg RCC_SYSCLK_DIV16: AHB clock = CK_SYS/16
- * @arg RCC_SYSCLK_DIV64: AHB clock = CK_SYS/64
- * @arg RCC_SYSCLK_DIV128: AHB clock = CK_SYS/128
- * @arg RCC_SYSCLK_DIV256: AHB clock = CK_SYS/256
- * @arg RCC_SYSCLK_DIV512: AHB clock = CK_SYS/512
- * @retval None
- */
-void RCC_AHBConfig(uint32_t RCC_CK_SYSDiv)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR;
-
- /* Clear AHBPS[3:0] bits */
- temp &= ~RCC_GCFGR_AHBPS;
-
- /* Set AHBPS[3:0] bits according to RCC_CK_SYSDiv value */
- temp |= RCC_CK_SYSDiv;
-
- /* Store the new value */
- RCC->GCFGR = temp;
-}
-
-/**
- * @brief Configure the APB1 clock.
- * @param RCC_APB1: specify the APB1 clock divider. This clock is derived from
- * the AHB clock.
- * This parameter can be one of the following values:
- * @arg RCC_APB1AHB_DIV1: APB1 clock = AHB
- * @arg RCC_APB1AHB_DIV2: APB1 clock = AHB/2
- * @arg RCC_APB1AHB_DIV4: APB1 clock = AHB/4
- * @arg RCC_APB1AHB_DIV8: APB1 clock = AHB/8
- * @arg RCC_APB1AHB_DIV16: APB1 clock = AHB/16
- * @retval None
- */
-void RCC_APB1Config(uint32_t RCC_APB1)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR;
-
- /* Clear APB1PS[2:0] bits */
- temp &= ~RCC_GCFGR_APB1PS;
-
- /* Set APB1PS[2:0] bits according to RCC_APB1 value */
- temp |= RCC_APB1;
-
- /* Store the new value */
- RCC->GCFGR = temp;
-}
-
-/**
- * @brief Configure the APB2 clock.
- * @param RCC_APB2: specify the APB2 clock divider. This clock is derived from
- * the AHB clock.
- * This parameter can be one of the following values:
- * @arg RCC_APB2AHB_DIV1: APB2 clock = AHB
- * @arg RCC_APB2AHB_DIV2: APB2 clock = AHB/2
- * @arg RCC_APB2AHB_DIV4: APB2 clock = AHB/4
- * @arg RCC_APB2AHB_DIV8: APB2 clock = AHB/8
- * @arg RCC_APB2AHB_DIV16: APB2 clock = AHB/16
- * @retval None
- */
-void RCC_APB2Config(uint32_t RCC_APB2)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR;
-
- /* Clear APB2PS[2:0] bits */
- temp &= ~RCC_GCFGR_APB2PS;
-
- /* Set APB2PS[2:0] bits according to RCC_APB2 value */
- temp |= RCC_APB2;
-
- /* Store the new value */
- RCC->GCFGR = temp;
-}
-
-#ifdef GD32F10X_CL
-/**
- * @brief Configure the USB_OTG clock (USB_OTG CLK).
- * @param RCC_OTGFSCLK: specify the USB_OTG clock source. This clock is derived
- * from the PLL.
- * This parameter can be one of the following values:
- * @arg RCC_OTGCLK_PLL_DIV1_5: USB_OTG clock = PLL/1.5
- * @arg RCC_OTGCLK_PLL_DIV1: USB_OTG clock = PLL
- * @arg RCC_OTGCLK_PLL_DIV2: USB_OTG clock = PLL/2
- * @arg RCC_OTGCLK_PLL_DIV2_5: USB-OTG clock = PLL/2.5
- * @retval None
- */
-void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLK)
-{
-
- /* Clear OTGFSPS bit */
- RCC->GCFGR &= ~RCC_GCFGR_OTGFSPS;
- /* Set OTGFSPS bits according to RCC_OTGFSCLK value */
- RCC->GCFGR |= RCC_OTGFSCLK;
-
-}
-
-#else
-/**
- * @brief Configure the USB clock (USBCLK).
- * @param RCC_USBCLK: specify the USB clock source. This clock is derived
- * from the PLL.
- * This parameter can be one of the following values:
- * @arg RCC_USBCLK_PLL_DIV1_5: USB clock = PLL/1.5
- * @arg RCC_USBCLK_PLL_DIV1: USB clock = PLL
- * @arg RCC_USBCLK_PLL_DIV2: USB clock = PLL/2
- * @arg RCC_USBCLK_PLL_DIV2_5: USB clock = PLL/2.5
- * @retval None
- */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
-{
-
- /* Clear USBPS bit */
- RCC->GCFGR &= ~RCC_GCFGR_USBPS;
- /* Set USBPS bits according to RCC_USBCLK value */
- RCC->GCFGR |= RCC_USBCLK;
-
-}
-#endif /* GD32F10X_CL */
-
-/**
- * @brief Configure the ADC clock (ADCCLK).
- * @param RCC_ADCCLK: specify the ADC clock source. This clock is derived from APB2 clock.
- * This parameter can be one of the following values:
- * @arg RCC_ADCCLK_APB2_DIV2: ADC clock = APB2/2
- * @arg RCC_ADCCLK_APB2_DIV4: ADC clock = APB2/4
- * @arg RCC_ADCCLK_APB2_DIV6: ADC clock = APB2/6
- * @arg RCC_ADCCLK_APB2_DIV8: ADC clock = APB2/8
- * @arg RCC_ADCCLK_APB2_DIV12: ADC clock = APB2/12
- * @arg RCC_ADCCLK_APB2_DIV16: ADC clock = APB2/16
- * @retval None
- */
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
-{
-
- /* Clear ADCPS bit */
- RCC->GCFGR &= ~RCC_GCFGR_ADCPS;
- /* Set ADCPS bits according to RCC_APB2 value */
- RCC->GCFGR |= RCC_ADCCLK;
-}
-
-#ifdef GD32F10X_CL
-/**
- * @brief Configure the I2S2 clock source(I2S2CLK).
- * @param RCC_I2S2CLK: specify the I2S2 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S2CLK_SYSCLK: system clock selected as I2S2 clock entry
- * @arg RCC_I2S2CLK_PLL3: PLL3 clock selected as I2S2 clock entry
- * @note If the RCC_I2S2CLK_PLL3 selected, the I2S2 clock is (PLL3 x 2).
- * @retval None
- */
-void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLK)
-{
- /* Clear I2S2SEL bit */
- RCC->GCFGR2 &= ~RCC_GCFGR2_I2S2SEL;
- /* Set I2S2CLK bits according to RCC_I2S2CLK value */
- RCC->GCFGR2 |= RCC_I2S2CLK;
-
-}
-
-/**
- * @brief Configure the I2S3 clock source(I2S3CLK).
- * @param RCC_I2S3CLK: specify the I2S3 clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2S3CLK_SYSCLK: system clock selected as I2S3 clock entry
- * @arg RCC_I2S3CLK_PLL3: PLL3 clock selected as I2S3 clock entry
- * @note If the RCC_I2S3CLK_PLL3 selected, the I2S3 clock is (PLL3 x 2).
- * @retval None
- */
-void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLK)
-{
- /* Clear I2S3SEL bit */
- RCC->GCFGR2 &= ~RCC_GCFGR2_I2S3SEL;
- /* Set I2S3CLK bits according to RCC_I2S3CLK value */
- RCC->GCFGR2 |= RCC_I2S3CLK;
-}
-#endif /* GD32F10X_CL */
-
-/**
- * @brief Configure the External Low Speed oscillator (LSE).
- * @param RCC_LSE: specify the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn off the LSE
- * @arg RCC_LSE_EN: turn on the LSE
- * @arg RCC_LSE_BYPASS: LSE bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint32_t RCC_LSE)
-{
-
- /* Reset LSEEN and LSEBPS bits before configuring the LSE */
- RCC->BDCR &= ~(RCC_BDCR_LSEEN);
- RCC->BDCR &= ~(RCC_BDCR_LSEBPS);
-
- /* Configure LSE */
- RCC->BDCR |= RCC_LSE;
-}
-
-
-/**
- * @brief Enable or disable the Internal Low Speed oscillator (LSI).
- * @param NewValue: new value of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_LSI_Enable(TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- RCC->GCSR |= RCC_GCSR_LSIEN;
- } else {
- RCC->GCSR &= ~RCC_GCSR_LSIEN;
- }
-}
-
-/**
- * @brief Configure the RTC clock (RTCCLK).
- * @param RCC_RTCCLKSource: specify the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_LSE: selecte LSE as RTC clock
- * @arg RCC_RTCCLKSOURCE_LSI: selecte LSI as RTC clock
- * @arg RCC_RTCCLKSOURCE_HSE_DIV128: selecte HSE divided by 128 as RTC clock
- * @note if using HSE as RTC source, the maximum clock frequency for RTC is 2 MHz.
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- /* Clear RTCSEL bit */
- RCC->BDCR &= ~RCC_BDCR_RTCSEL;
- /* Select the RTC clock source */
- RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
- * @brief Enable or disable the RTC clock.
- * @param NewValue: new state of the RTC clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLK_Enable(TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- RCC->BDCR |= RCC_BDCR_RTCEN;
- } else {
- RCC->BDCR &= ~RCC_BDCR_RTCEN;
- }
-}
-
-/**
- * @brief Get the frequencies of the CK_SYS, AHB, APB1, APB2, ADC clocks.
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksPara *RCC_Clocks)
-{
- uint32_t temp = 0, pllmf = 0, pllmf4 = 0, pllselect = 0, presc = 0;
-
-#ifdef GD32F10X_CL
- uint32_t prediv1select = 0, prediv1factor = 0, prediv2factor = 0, pll2mf = 0;
-#endif /* GD32F10X_CL */
-
-
- /* Get CK_SYS source */
- temp = RCC->GCFGR & RCC_GCFGR_SCSS;
-
- switch (temp) {
- case 0x00: /* HSI used as CK_SYS */
- RCC_Clocks->CK_SYS_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as CK_SYS */
- RCC_Clocks->CK_SYS_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as CK_SYS */
-#ifdef GD32F10X_CL
- /* Get PLL clock source and multiplication factor */
- /* Get PLLMF[3:0] */
- pllmf = RCC->GCFGR & RCC_GCFGR_PLLMF_3_0;
- /* Get PLLMF[4] */
- pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4;
-
- pllmf4 = ((pllmf4 >> 29) * 16);
-
- pllmf = (pllmf >> 18) + pllmf4;
- if (pllmf == 0x0D) {
- /* PLL multiplication factor = PLL input clock * 6.5*/
- /* Beacause of the float number 6.5, pllmf * 2 to remove the float number */
- pllmf = 13 * 2 / 2;
-
- } else if (pllmf >= 0x0F) {
- pllmf += 1;
- /* Here is consistent with the above that pllmf * 2 to remove the float number*/
- pllmf = pllmf * 2;
- } else {
- pllmf += 2;
- /* Here is consistent with the above that pllmf * 2 to remove the float number*/
- pllmf = pllmf * 2;
- }
-
- pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL;
- if (pllselect == 0x00) {
- /* HSI clock divided by 2 selected as PLL clock source */
- /* Here is consistent with the above that pllmf / 2 */
- RCC_Clocks->CK_SYS_Frequency = (HSI_VALUE >> HSI_CLOCK_DIVIDED_2) * pllmf / 2;
- } else {
- /* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1select = RCC->GCFGR2 & RCC_GCFGR2_PREDV1SEL;
- prediv1factor = (RCC->GCFGR2 & RCC_GCFGR2_PREDV1) + 1;
-
- if (prediv1select == 0) {
- /* HSE clock selected as PREDIV1 clock entry */
- /* Here is consistent with the above that pllmf / 2 */
- RCC_Clocks->CK_SYS_Frequency = (HSE_VALUE / prediv1factor) * pllmf / 2;
- } else {
- /* PLL2 clock selected as PREDIV1 clock entry */
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->GCFGR2 & RCC_GCFGR2_PREDV2) >> 4) + 1;
- pll2mf = ((RCC->GCFGR2 & RCC_GCFGR2_PLL2MF) >> 8);
- if (pll2mf != 15) {
- pll2mf += 2;
- } else {
- pll2mf += 5;
- }
- /* Here is consistent with the above that pllmf / 2 */
- RCC_Clocks->CK_SYS_Frequency = (((HSE_VALUE / prediv2factor) * pll2mf) / prediv1factor) * pllmf / 2;
- }
- }
-#else
- /* Get PLL clock source and multiplication factor */
- /* Get PLLMF[3:0] */
- pllmf = RCC->GCFGR & RCC_GCFGR_PLLMF_3_0;
- /* Get PLLMF[4] */
- pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4;
-
- pllmf4 = ((pllmf4 >> 27) * 16);
- pllmf = (pllmf >> 18) + pllmf4;
- if (pllmf >= 0x0F)
- pllmf += 1;
- else
- pllmf += 2;
-
- pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL;
- if (pllselect == 0x00) {
- /* HSI clock divided by 2 selected as PLL clock source */
- RCC_Clocks->CK_SYS_Frequency = (HSI_VALUE >> HSI_CLOCK_DIVIDED_2) * pllmf;
- } else {
- if ((RCC->GCFGR & RCC_GCFGR_PLLPREDV) != (uint32_t)RESET) {
- /* HSE clock divided by 2 */
- RCC_Clocks->CK_SYS_Frequency = (HSE_VALUE >> HSE_CLOCK_DIVIDED_2) * pllmf;
- } else {
- RCC_Clocks->CK_SYS_Frequency = HSE_VALUE * pllmf;
- }
- }
-#endif/* GD32F10X_CL */
- break;
- default: /* HSI used as system clock */
- RCC_Clocks->CK_SYS_Frequency = HSI_VALUE;
- break;
- }
-
- /* Get AHB prescaler */
- temp = RCC->GCFGR & RCC_GCFGR_AHBPS;
- temp = temp >> 4;
- presc = AHBPrescTable[temp];
- /* Get AHB clock frequency */
- RCC_Clocks->AHB_Frequency = RCC_Clocks->CK_SYS_Frequency >> presc;
-
- /* Get APB1 prescaler */
- temp = RCC->GCFGR & RCC_GCFGR_APB1PS;
- temp = temp >> 8;
- presc = APBPrescTable[temp];
- /* Get APB1 clock frequency */
- RCC_Clocks->APB1_Frequency = RCC_Clocks->AHB_Frequency >> presc;
-
- /* Get APB2 prescaler */
- temp = RCC->GCFGR & RCC_GCFGR_APB2PS;
- temp = temp >> 11;
- presc = APBPrescTable[temp];
- /* Get APB2 clock frequency */
- RCC_Clocks->APB2_Frequency = RCC_Clocks->AHB_Frequency >> presc;
-
- /* Get ADCCLK clock frequency */
- temp = ((RCC->GCFGR & RCC_GCFGR_ADCPS_2) >> 26);
- temp += ((RCC->GCFGR & (RCC_GCFGR_ADCPS_0 | RCC_GCFGR_ADCPS_1)) >> 14);
- switch (temp) {
- case 0x00: /* ADC Clock is derived from APB2/2 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 2);
- break;
- case 0x01: /* ADC Clock is derived from APB2/4 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 4);
- break;
- case 0x02: /* ADC Clock is derived from APB2/6 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 6);
- break;
- case 0x03: /* ADC Clock is derived from APB2/8 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 8);
- break;
- case 0x04: /* ADC Clock is derived from APB2/2 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 2);
- break;
- case 0x05: /* ADC Clock is derived from APB2/12 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 12);
- break;
- case 0x06: /* ADC Clock is derived from APB2/8 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 8);
- break;
- case 0x07: /* ADC Clock is derived from APB2/16 */
- RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 16);
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Enable or disable the AHB peripheral clock.
- * @param RCC_AHBPeriph: specify the AHB peripheral clock.
- * For @b GD32_Connectivity_line_devices,
- * this parameter can be any combination of the following values:
- * @arg RCC_AHBPERIPH_DMA1
- * @arg RCC_AHBPERIPH_DMA2
- * @arg RCC_AHBPERIPH_SRAM
- * @arg RCC_AHBPERIPH_FMC
- * @arg RCC_AHBPERIPH_CRC
- * @arg RCC_AHBPERIPH_EXMC
- * @arg RCC_AHBPERIPH_OTG_FS
- * @arg RCC_AHBPERIPH_ETH_MAC
- * @arg RCC_AHBPERIPH_ETH_MAC_RX
- * @arg RCC_AHBPERIPH_ETH_MAC_TX
- *
- * For @b other_GD32_devices, this parameter can be any combination of the
- * following values:
- * @arg RCC_AHBPERIPH_DMA1
- * @arg RCC_AHBPERIPH_DMA2
- * @arg RCC_AHBPERIPH_SRAM
- * @arg RCC_AHBPERIPH_FMC
- * @arg RCC_AHBPERIPH_CRC
- * @arg RCC_AHBPERIPH_EXMC
- * @arg RCC_AHBPERIPH_SDIO
- * @param NewValue: new state of the peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClock_Enable(uint32_t RCC_AHBPeriph, TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- RCC->AHBCCR |= RCC_AHBPeriph;
- } else {
- RCC->AHBCCR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enable or disable the APB2 peripheral clock.
- * @param RCC_APB2Periph: specify the APB2 peripheral clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2PERIPH_AF
- * @arg RCC_APB2PERIPH_GPIOA
- * @arg RCC_APB2PERIPH_GPIOB
- * @arg RCC_APB2PERIPH_GPIOC
- * @arg RCC_APB2PERIPH_GPIOD
- * @arg RCC_APB2PERIPH_GPIOE
- * @arg RCC_APB2PERIPH_GPIOF
- * @arg RCC_APB2PERIPH_GPIOG
- * @arg RCC_APB2PERIPH_ADC1
- * @arg RCC_APB2PERIPH_ADC2
- * @arg RCC_APB2PERIPH_TIMER1
- * @arg RCC_APB2PERIPH_SPI1
- * @arg RCC_APB2PERIPH_TIMER8
- * @arg RCC_APB2PERIPH_USART1
- * @arg RCC_APB2PERIPH_ADC3
- * @arg RCC_APB2PERIPH_TIMER9
- * @arg RCC_APB2PERIPH_TIMER10
- * @arg RCC_APB2PERIPH_TIMER11
- * @param NewValue: new state of the peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClock_Enable(uint32_t RCC_APB2Periph, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->APB2CCR |= RCC_APB2Periph;
- } else {
- RCC->APB2CCR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enable or disable the APB1 peripheral clock.
- * @param RCC_APB1Periph: specify the APB1 peripheral clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1PERIPH_TIMER2
- * @arg RCC_APB1PERIPH_TIMER3
- * @arg RCC_APB1PERIPH_TIMER4
- * @arg RCC_APB1PERIPH_TIMER5
- * @arg RCC_APB1PERIPH_TIMER6
- * @arg RCC_APB1PERIPH_TIMER7
- * @arg RCC_APB1PERIPH_TIMER12
- * @arg RCC_APB1PERIPH_TIMER13
- * @arg RCC_APB1PERIPH_TIMER14
- * @arg RCC_APB1PERIPH_WWDG
- * @arg RCC_APB1PERIPH_SPI2
- * @arg RCC_APB1PERIPH_SPI3,
- * @arg RCC_APB1PERIPH_USART2
- * @arg RCC_APB1PERIPH_USART3
- * @arg RCC_APB1PERIPH_UART4
- * @arg RCC_APB1PERIPH_UART5
- * @arg RCC_APB1PERIPH_I2C1
- * @arg RCC_APB1PERIPH_I2C2
- * @arg RCC_APB1PERIPH_USB
- * @arg RCC_APB1PERIPH_CAN1
- * @arg RCC_APB1PERIPH_CAN2
- * @arg RCC_APB1PERIPH_BKP
- * @arg RCC_APB1PERIPH_PWR
- * @arg RCC_APB1PERIPH_DAC
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClock_Enable(uint32_t RCC_APB1Periph, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->APB1CCR |= RCC_APB1Periph;
- } else {
- RCC->APB1CCR &= ~RCC_APB1Periph;
- }
-}
-
-#ifdef GD32F10X_CL
-/**
- * @brief Force or release AHB peripheral reset.
- * @param RCC_AHBPeriphRST: specify the AHB peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_OTGFSRST
- * @arg RCC_AHBPeriph_ETHMACRST
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphReset_Enable(uint32_t RCC_AHBPeriphRST, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->AHBRCR |= RCC_AHBPeriphRST;
- } else {
- RCC->AHBRCR &= ~RCC_AHBPeriphRST;
- }
-}
-#endif /* GD32F10X_CL */
-
-/**
- * @brief Force or release APB2 peripheral reset.
- * @param RCC_APB2PeriphRST: specify the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2PERIPH_AFRST
- * @arg RCC_APB2PERIPH_GPIOARST
- * @arg RCC_APB2PERIPH_GPIOBRST
- * @arg RCC_APB2PERIPH_GPIOCRST
- * @arg RCC_APB2PERIPH_GPIODRST
- * @arg RCC_APB2PERIPH_GPIOERST
- * @arg RCC_APB2PERIPH_GPIOFRST
- * @arg RCC_APB2PERIPH_GPIOGRST
- * @arg RCC_APB2PERIPH_ADC1RST
- * @arg RCC_APB2PERIPH_ADC2RST
- * @arg RCC_APB2PERIPH_TIMER1RST
- * @arg RCC_APB2PERIPH_SPI1RST
- * @arg RCC_APB2PERIPH_TIMER8RST
- * @arg RCC_APB2PERIPH_USART1RST
- * @arg RCC_APB2PERIPH_ADC3RST
- * @arg RCC_APB2PERIPH_TIMER9RST
- * @arg RCC_APB2PERIPH_TIMER10RST
- * @arg RCC_APB2PERIPH_TIMER11RST
- * @param NewValue: new state of the peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphReset_Enable(uint32_t RCC_APB2PeriphRST, TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- RCC->APB2RCR |= RCC_APB2PeriphRST;
- } else {
- RCC->APB2RCR &= ~RCC_APB2PeriphRST;
- }
-}
-
-
-/**
- * @brief Force or release APB1 peripheral reset.
- * @param RCC_APB1PeriphRST: specify the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1PERIPH_TIMER2RST
- * @arg RCC_APB1PERIPH_TIMER3RST
- * @arg RCC_APB1PERIPH_TIMER4RST
- * @arg RCC_APB1PERIPH_TIMER5RST
- * @arg RCC_APB1PERIPH_TIMER6RST
- * @arg RCC_APB1PERIPH_TIMER7RST
- * @arg RCC_APB1PERIPH_TIMER12RST
- * @arg RCC_APB1PERIPH_TIMER13RST
- * @arg RCC_APB1PERIPH_TIMER14RST
- * @arg RCC_APB1PERIPH_WWDGRST
- * @arg RCC_APB1PERIPH_SPI2RST
- * @arg RCC_APB1PERIPH_SPI3RST
- * @arg RCC_APB1PERIPH_USART2RST
- * @arg RCC_APB1PERIPH_USART3RST
- * @arg RCC_APB1PERIPH_UART4RST
- * @arg RCC_APB1PERIPH_UART5RST
- * @arg RCC_APB1PERIPH_I2C1RST
- * @arg RCC_APB1PERIPH_I2C2RST
- * @arg RCC_APB1PERIPH_USBRST
- * @arg RCC_APB1PERIPH_CAN1RST
- * @arg RCC_APB1PERIPH_CAN2RST
- * @arg RCC_APB1PERIPH_BKPRST
- * @arg RCC_APB1PERIPH_PWRRST
- * @arg RCC_APB1PERIPH_DACRST
- * @param NewValue: new state of the peripheral clock (ENABLE or DISABLE).
- * @retval None
- */
-void RCC_APB1PeriphReset_Enable(uint32_t RCC_APB1PeriphRST, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->APB1RCR |= RCC_APB1PeriphRST;
- } else {
- RCC->APB1RCR &= ~RCC_APB1PeriphRST;
- }
-}
-
-/**
- * @brief Force or release the Backup domain reset.
- * @param NewValue: new state of the Backup domain reset (ENABLE or DISABLE).
- * @retval None
- */
-void RCC_BackupReset_Enable(TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- RCC->BDCR |= RCC_BDCR_BKPRST;
- } else {
- RCC->BDCR &= ~RCC_BDCR_BKPRST;
- }
-}
-
-/**
- * @brief Enable or disable the Clock Security System.
- * @param NewValue: new value of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSEClockMonitor_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- RCC->GCCR |= RCC_GCCR_CKMEN;
- } else {
- RCC->GCCR &= ~RCC_GCCR_CKMEN;
- }
-}
-
-/**
- * @brief Select the clock source to output on CKOUTSRC and the corresponding prescaler.
- * @param RCC_CKOUTSRC: specify the clock source to output.
- * For @b GD32_Connectivity_line_devices, this parameter can be one of the
- * following values:
- * @arg RCC_CKOUTSRC_NOCLOCK: No clock selected
- * @arg RCC_CKOUTSRC_SYSCLK: System clock selected
- * @arg RCC_CKOUTSRC_HSI: HSI oscillator clock selected
- * @arg RCC_CKOUTSRC_HSE: HSE oscillator clock selected
- * @arg RCC_CKOUTSRC_PLL2CLK: PLL2 clock selected
- * @arg RCC_CKOUTSRC_PLLCLK_DIV2: PLL clock divided by 2 selected
- * @arg RCC_CKOUTSRC_PLL3CLK: PLL3 clock selected
- * @arg RCC_CKOUTSRC_PLL3CLK_DIV2: PLL3 clock divided by 2 selected
- * @arg RCC_CKOUTSRC_EXT1: External 3-25 MHz oscillator clock selected
- * For @b other_GD32_devices, this parameter can be one of the following values:
- * @arg RCC_CKOUTSRC_NOCLOCK: No clock selected
- * @arg RCC_CKOUTSRC_SYSCLK: System clock selected
- * @arg RCC_CKOUTSRC_HSI: HSI oscillator clock selected
- * @arg RCC_CKOUTSRC_HSE: HSE oscillator clock selected
- * @arg RCC_CKOUTSRC_PLLCLK_DIV2: PLL clock divided by 2 selected
- * @retval None
- */
-
-void RCC_CKOUTSRCConfig(uint32_t RCC_CKOUTSRC)
-{
- uint32_t temp = 0;
-
- temp = RCC->GCFGR;
- /* Clear CKOUTSRC[2:0] bits */
- temp &= ~(RCC_GCFGR_CKOUTSEL);
- /* Set the RCC_CKOUTSRC */
- temp |= RCC_CKOUTSRC;
- /* Store the new value */
- RCC->GCFGR = temp;
-}
-
-
-/**
- * @brief Enable or disable RCC interrupts.
- * @param RCC_INT: specify the RCC interrupt sources.
- * For @b GD32_Connectivity_line_devices, this parameter can be any combination
- * of the following values
- * @arg RCC_INT_LSISTB: LSI ready interrupt
- * @arg RCC_INT_LSESTB LSE ready interrupt
- * @arg RCC_INT_HSISTB: HSI ready interrupt
- * @arg RCC_INT_HSESTB: HSE ready interrupt
- * @arg RCC_INT_PLLSTB: PLL ready interrupt
- * @arg RCC_INT_PLL2STB: PLL2 ready interrupt
- * @arg RCC_INT_PLL3STB: PLL3 ready interrupt
- *
- * For @b other_GD32_devices, this parameter can be any combination of the
- * following values
- * @arg RCC_INT_LSISTB: LSI ready interrupt
- * @arg RCC_INT_LSESTB: LSE ready interrupt
- * @arg RCC_INT_HSISTB: HSI ready interrupt
- * @arg RCC_INT_HSESTB: HSE ready interrupt
- * @arg RCC_INT_PLLSTB: PLL ready interrupt
- * @param NewValue: new state of the RCC interrupts (ENABLE or DISABLE).
- * @retval None
- */
-void RCC_INTConfig(uint8_t RCC_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Perform Byte access to RCC_GCIR[14:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) GCIR_BYTE1_ADDRESS |= RCC_INT;
- } else {
- /* Perform Byte access to RCC_GCIR bits to disable the selected interrupts */
- *(__IO uint8_t *) GCIR_BYTE1_ADDRESS &= (uint8_t)~RCC_INT;
- }
-}
-
-
-/**
- * @brief Check whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specify the flag to check.
- * For @b GD32_Connectivity_line_devices, this parameter can be one of the
- * following values:
- * @arg RCC_FLAG_HSISTB: HSI clock ready
- * @arg RCC_FLAG_HSESTB: HSE clock ready
- * @arg RCC_FLAG_PLLSTB: PLL clock ready
- * @arg RCC_FLAG_PLL2STB: PLL2 clock ready
- * @arg RCC_FLAG_PLL3STB: PLL3 clock ready
- * @arg RCC_FLAG_LSESTB: LSE clock ready
- * @arg RCC_FLAG_LSISTB: LSI clock ready
- * @arg RCC_FLAG_EPRST: Pin reset
- * @arg RCC_FLAG_POPDRST: POR/PDR reset
- * @arg RCC_FLAG_SWRRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPRRST: Low Power reset
- * For @b other_GD32_devices, this parameter can be one of the following values:
- * @arg RCC_FLAG_HSISTB: HSI oscillator clock ready
- * @arg RCC_FLAG_HSESTB: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLSTB: PLL clock ready
- * @arg RCC_FLAG_LSESTB: LSE oscillator clock ready
- * @arg RCC_FLAG_LSISTB: LSI oscillator clock ready
- * @arg RCC_FLAG_EPRST: Pin reset
- * @arg RCC_FLAG_POPDRST: POR/PDR reset
- * @arg RCC_FLAG_SWRRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPRRST: Low Power reset
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-TypeState RCC_GetBitState(uint8_t RCC_FLAG)
-{
- uint32_t temp = 0;
- uint32_t statusreg = 0;
-
- /* Get the RCC register index */
- temp = RCC_FLAG >> 5;
-
- /* The flag to check is in GCCR register */
- if (temp == 1) {
- statusreg = RCC->GCCR;
- }
-
- /* The flag to check is in BDCR register */
- else if (temp == 2) {
- statusreg = RCC->BDCR;
- }
-
- /* The flag to check is in GCSR register */
- else {
- statusreg = RCC->GCSR;
- }
-
- /* Get the flag position */
- temp = RCC_FLAG & FLAG_MASK;
- if ((statusreg & ((uint32_t)(1 << temp))) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-
-}
-
-/**
- * @brief Clear the RCC all reset flags.
- * @param None
- * @retval None
- */
-void RCC_ClearBitState(void)
-{
- /* Set RSTFC bit to clear all reset flags */
- RCC->GCSR |= RCC_GCSR_RSTFC;
-}
-
-
-/**
- * @brief Check whether the RCC interrupt has occurred or not.
- * @param RCC_INT: specify the RCC interrupt source to check.
- * For @b GD32_Connectivity_line_devices, this parameter can be one of the
- * following values:
- * @arg RCC_INT_LSISTB: the flag of LSI ready interrupt
- * @arg RCC_INT_LSESTB: the flag of LSE ready interrupt
- * @arg RCC_INT_HSISTB: the flag of HSI ready interrupt
- * @arg RCC_INT_HSESTB: the flag of HSE ready interrupt
- * @arg RCC_INT_PLLSTB: the flag of PLL ready interrupt
- * @arg RCC_INT_PLL2STB: the flag of PLL2 ready interrupt
- * @arg RCC_INT_PLL3STB: the flag of PLL3 ready interrupt
- * @arg RCC_INT_CKM: the flag of Clock Security System interrupt
- * For @b other_GD32_devices, this parameter can be one of the following values:
- * @arg RCC_INT_LSISTB: the flag of LSI ready interrupt
- * @arg RCC_INT_LSESTB: the flag of LSE ready interrupt
- * @arg RCC_INT_HSISTB: the flag of HSI ready interrupt
- * @arg RCC_INT_HSESTB: the flag of HSE ready interrupt
- * @arg RCC_INT_PLLSTB: the flag of PLL ready interrupt
- * @arg RCC_INT_CKM: the flag of Clock Security System interrupt
- * @retval The new state of RCC_INT (SET or RESET).
- */
-TypeState RCC_GetIntBitState(uint8_t RCC_INT)
-{
- /* Check the status of the RCC interrupt */
- if ((RCC->GCIR & RCC_INT) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-/**
- * @brief Clear the RCC interrupt bits.
- * @param RCC_INT: specify the interrupt bit to clear.
- * For @b GD32_Connectivity_line_devices, this parameter can be any combination
- * of the following values:
- * @arg RCC_INT_LSISTB: LSI ready interrupt
- * @arg RCC_INT_LSESTB LSE ready interrupt
- * @arg RCC_INT_HSISTB: HSI ready interrupt
- * @arg RCC_INT_HSESTB: HSE ready interrupt
- * @arg RCC_INT_PLLSTB: PLL ready interrupt
- * @arg RCC_INT_PLL2STB: PLL2 ready interrupt
- * @arg RCC_INT_PLL3STB: PLL3 ready interrupt
- * @arg RCC_INT_CKM: Clock Security System interrupt
- * For @b other_GD32_devices, this parameter can be any combination of the
- * following values
- * @arg RCC_INT_LSISTB: LSI ready interrupt
- * @arg RCC_INT_LSESTB: LSE ready interrupt
- * @arg RCC_INT_HSISTB: HSI ready interrupt
- * @arg RCC_INT_HSESTB: HSE ready interrupt
- * @arg RCC_INT_PLLSTB: PLL ready interrupt
- * @arg RCC_INT_CKM: Clock Security System interrupt
- * @retval None
- */
-
-void RCC_ClearIntBitState(uint8_t RCC_INT)
-{
-
-
- /* Perform RCC_GCIR[23:16] bits to clear the selected interrupt bits */
- *(__IO uint8_t *) GCIR_BYTE2_ADDRESS = RCC_INT;
-}
-
-/**
- * @brief Configure the kernel voltage in Deep-sleep mode.
- * @note Only unlock the power,this configuration is effective.
- * @param RCC_KERNEL_VOL: specify the kernel voltage.
- * This parameter can be one of the following values:
- * @arg RCC_KERNEL_VOL1_2: The kernel voltage in Deep-sleep mode is 1.2V
- * @arg RCC_KERNEL_VOL1_1: The kernel voltage in Deep-sleep mode is 1.1V
- * @arg RCC_KERNEL_VOL1_0: The kernel voltage in Deep-sleep mode is 1.0V
- * @arg RCC_KERNEL_VOL0_9: The kernel voltage in Deep-sleep mode is 0.9V
- * @retval None
- */
-void RCC_KERNELVOLConfig(uint32_t RCC_KERNEL_VOL)
-{
- /* Clear DEEPSLEEP_VC bit */
- RCC->RCC_DEEPSLEEP_VC &= ~RCC_DEEPSLEEP_VC_CLEAR;
- /* Set DEEPSLEEP_VC bits according to RCC_KERNEL_VOL value */
- RCC->RCC_DEEPSLEEP_VC |= RCC_KERNEL_VOL;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c
deleted file mode 100644
index 1757e170ef..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c
+++ /dev/null
@@ -1,1277 +0,0 @@
-/*!
- \file gd32f10x_rcu.c
- \brief RCU driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2017-02-10, V1.0.1, firmware for GD32F30x
- 2021-01-02, firmware for GD32F10x
-*/
-
-#include "gd32f10x_rcu.h"
-
-/* define clock source */
-#define SEL_IRC8M ((uint16_t)0U)
-#define SEL_HXTAL ((uint16_t)1U)
-#define SEL_PLL ((uint16_t)2U)
-
-/* define startup timeout count */
-#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
-#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)
-
-/*!
- \brief deinitialize the RCU
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_deinit(void)
-{
- /* enable IRC8M */
- RCU_CTL |= RCU_CTL_IRC8MEN;
- rcu_osci_stab_wait(RCU_IRC8M);
-
- /* reset CFG0 register */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
- RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF |
- RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBDPSC_2);
-#elif defined(GD32F10X_CL)
- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
- RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
- RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBFSPSC_2);
-#endif /* GD32F10X_HD and GD32F10X_XD */
- /* reset CTL register */
- RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
- RCU_CTL &= ~RCU_CTL_HXTALBPS;
-#ifdef GD32F10X_CL
- RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
-#endif /* GD32F10X_CL */
-
- /* reset INT and CFG1 register */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- RCU_INT = 0x009f0000U;
- RCU_CFG1 &= ~(RCU_CFG1_ADCPSC_3 | RCU_CFG1_PLLPRESEL);
-#elif defined(GD32F10X_CL)
- RCU_INT = 0x00ff0000U;
- RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
- RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL | RCU_CFG1_ADCPSC_3 |
- RCU_CFG1_PLLPRESEL | RCU_CFG1_PLL2MF_4);
-#endif /* GD32F10X_HD and GD32F10X_XD */
-}
-
-/*!
- \brief enable the peripherals clock
- \param[in] periph: RCU peripherals, refer to rcu_periph_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
- \arg RCU_AF : alternate function clock
- \arg RCU_CRC: CRC clock
- \arg RCU_DMAx (x=0,1): DMA clock
- \arg RCU_ENET: ENET clock(CL series available)
- \arg RCU_ENETTX: ENETTX clock(CL series available)
- \arg RCU_ENETRX: ENETRX clock(CL series available)
- \arg RCU_USBD: USBD clock(HD,XD series available)
- \arg RCU_USBFS: USBFS clock(CL series available)
- \arg RCU_EXMC: EXMC clock
- \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock
- \arg RCU_WWDGT: WWDGT clock
- \arg RCU_SPIx (x=0,1,2): SPI clock
- \arg RCU_USARTx (x=0,1,2): USART clock
- \arg RCU_UARTx (x=3,4): UART clock
- \arg RCU_I2Cx (x=0,1): I2C clock
- \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
- \arg RCU_PMU: PMU clock
- \arg RCU_DAC: DAC clock
- \arg RCU_RTC: RTC clock
- \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
- \arg RCU_SDIO: SDIO clock(not available for CL series)
- \arg RCU_CTC: CTC clock
- \arg RCU_BKPI: BKP interface clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_enable(rcu_periph_enum periph)
-{
- RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief disable the peripherals clock
- \param[in] periph: RCU peripherals, refer to rcu_periph_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
- \arg RCU_AF: alternate function clock
- \arg RCU_CRC: CRC clock
- \arg RCU_DMAx (x=0,1): DMA clock
- \arg RCU_ENET: ENET clock(CL series available)
- \arg RCU_ENETTX: ENETTX clock(CL series available)
- \arg RCU_ENETRX: ENETRX clock(CL series available)
- \arg RCU_USBD: USBD clock(HD,XD series available)
- \arg RCU_USBFS: USBFS clock(CL series available)
- \arg RCU_EXMC: EXMC clock
- \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock
- \arg RCU_WWDGT: WWDGT clock
- \arg RCU_SPIx (x=0,1,2): SPI clock
- \arg RCU_USARTx (x=0,1,2): USART clock
- \arg RCU_UARTx (x=3,4): UART clock
- \arg RCU_I2Cx (x=0,1): I2C clock
- \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
- \arg RCU_PMU: PMU clock
- \arg RCU_DAC: DAC clock
- \arg RCU_RTC: RTC clock
- \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
- \arg RCU_SDIO: SDIO clock(not available for CL series)
- \arg RCU_CTC: CTC clock
- \arg RCU_BKPI: BKP interface clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_disable(rcu_periph_enum periph)
-{
- RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief enable the peripherals clock when sleep mode
- \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_FMC_SLP: FMC clock
- \arg RCU_SRAM_SLP: SRAM clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
-{
- RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief disable the peripherals clock when sleep mode
- \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_FMC_SLP: FMC clock
- \arg RCU_SRAM_SLP: SRAM clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
-{
- RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief reset the peripherals
- \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
- \arg RCU_AFRST : reset alternate function clock
- \arg RCU_ENETRST: reset ENET(CL series available)
- \arg RCU_USBDRST: reset USBD(HD,XD series available)
- \arg RCU_USBFSRST: reset USBFS(CL series available)
- \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER
- \arg RCU_WWDGTRST: reset WWDGT
- \arg RCU_SPIxRST (x=0,1,2): reset SPI
- \arg RCU_USARTxRST (x=0,1,2): reset USART
- \arg RCU_UARTxRST (x=3,4): reset UART
- \arg RCU_I2CxRST (x=0,1): reset I2C
- \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
- \arg RCU_PMURST: reset PMU
- \arg RCU_DACRST: reset DAC
- \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC
- \arg RCU_CTCRST: reset CTC
- \arg RCU_BKPIRST: reset BKPI
- \param[out] none
- \retval none
-*/
-void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
-{
- RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
-}
-
-/*!
- \brief disable reset the peripheral
- \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
- \arg RCU_AFRST : reset alternate function clock
- \arg RCU_ENETRST: reset ENET(CL series available)
- \arg RCU_USBDRST: reset USBD(HD,XD series available)
- \arg RCU_USBFSRST: reset USBFS(CL series available)
- \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER
- \arg RCU_WWDGTRST: reset WWDGT
- \arg RCU_SPIxRST (x=0,1,2): reset SPI
- \arg RCU_USARTxRST (x=0,1,2): reset USART
- \arg RCU_UARTxRST (x=3,4): reset UART
- \arg RCU_I2CxRST (x=0,1): reset I2C
- \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
- \arg RCU_PMURST: reset PMU
- \arg RCU_DACRST: reset DAC
- \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC
- \arg RCU_CTCRST: reset CTC
- \arg RCU_BKPIRST: reset BKPI
- \param[out] none
- \retval none
-*/
-void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
-{
- RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
-}
-
-/*!
- \brief reset the BKP domain
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_bkp_reset_enable(void)
-{
- RCU_BDCTL |= RCU_BDCTL_BKPRST;
-}
-
-/*!
- \brief disable the BKP domain reset
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_bkp_reset_disable(void)
-{
- RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
-}
-
-/*!
- \brief configure the system clock source
- \param[in] ck_sys: system clock source select
- only one parameter can be selected which is shown as below:
- \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
- \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
- \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
- \param[out] none
- \retval none
-*/
-void rcu_system_clock_source_config(uint32_t ck_sys)
-{
- uint32_t reg;
-
- reg = RCU_CFG0;
- /* reset the SCS bits and set according to ck_sys */
- reg &= ~RCU_CFG0_SCS;
- RCU_CFG0 = (reg | ck_sys);
-}
-
-/*!
- \brief get the system clock source
- \param[in] none
- \param[out] none
- \retval which clock is selected as CK_SYS source
- \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source
- \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
- \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source
-*/
-uint32_t rcu_system_clock_source_get(void)
-{
- return (RCU_CFG0 & RCU_CFG0_SCSS);
-}
-
-/*!
- \brief configure the AHB clock prescaler selection
- \param[in] ck_ahb: AHB clock prescaler selection
- only one parameter can be selected which is shown as below:
- \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
- \param[out] none
- \retval none
-*/
-void rcu_ahb_clock_config(uint32_t ck_ahb)
-{
- uint32_t reg;
-
- reg = RCU_CFG0;
-
- /* reset the AHBPSC bits and set according to ck_ahb */
- reg &= ~RCU_CFG0_AHBPSC;
- RCU_CFG0 = (reg | ck_ahb);
-}
-
-/*!
- \brief configure the APB1 clock prescaler selection
- \param[in] ck_apb1: APB1 clock prescaler selection
- only one parameter can be selected which is shown as below:
- \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
- \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
- \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
- \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
- \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
- \param[out] none
- \retval none
-*/
-void rcu_apb1_clock_config(uint32_t ck_apb1)
-{
- uint32_t reg;
-
- reg = RCU_CFG0;
-
- /* reset the APB1PSC and set according to ck_apb1 */
- reg &= ~RCU_CFG0_APB1PSC;
- RCU_CFG0 = (reg | ck_apb1);
-}
-
-/*!
- \brief configure the APB2 clock prescaler selection
- \param[in] ck_apb2: APB2 clock prescaler selection
- only one parameter can be selected which is shown as below:
- \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
- \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
- \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
- \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
- \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
- \param[out] none
- \retval none
-*/
-void rcu_apb2_clock_config(uint32_t ck_apb2)
-{
- uint32_t reg;
-
- reg = RCU_CFG0;
-
- /* reset the APB2PSC and set according to ck_apb2 */
- reg &= ~RCU_CFG0_APB2PSC;
- RCU_CFG0 = (reg | ck_apb2);
-}
-
-/*!
- \brief configure the CK_OUT0 clock source
- \param[in] ckout0_src: CK_OUT0 clock source selection
- only one parameter can be selected which is shown as below:
- \arg RCU_CKOUT0SRC_NONE: no clock selected
- \arg RCU_CKOUT0SRC_CKSYS: system clock selected
- \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected
- \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected
- \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
- \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected
- \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected
- \arg RCU_CKOUT0SRC_EXT1: EXT1 selected
- \arg RCU_CKOUT0SRC_CKPLL2: PLL selected
- \param[out] none
- \retval none
-*/
-void rcu_ckout0_config(uint32_t ckout0_src)
-{
- uint32_t reg;
-
- reg = RCU_CFG0;
-
- /* reset the CKOUT0SRC, set according to ckout0_src */
- reg &= ~RCU_CFG0_CKOUT0SEL;
- RCU_CFG0 = (reg | ckout0_src);
-}
-
-/*!
- \brief configure the main PLL clock
- \param[in] pll_src: PLL clock source selection
- \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL
- \arg RCU_PLLSRC_HXTAL_IRC48M: HXTAL or IRC48M selected as source clock of PLL
- \param[in] pll_mul: PLL clock multiplication factor
- \arg RCU_PLL_MULx (XD series x = 2..63, CL series x = 2..14, 16..63, 6.5)
- \param[out] none
- \retval none
-*/
-void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
-{
- uint32_t reg = 0U;
-
- reg = RCU_CFG0;
-
- /* PLL clock source and multiplication factor configuration */
- reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
- reg |= (pll_src | pll_mul);
-
- RCU_CFG0 = reg;
-}
-
-/*!
- \brief configure the PLL clock source preselection
- \param[in] pll_presel: PLL clock source preselection
- \arg RCU_PLLPRESRC_HXTAL: HXTAL selected as PLL source clock
- \arg RCU_PLLPRESRC_IRC48M: CK_PLL selected as PREDV0 input source clock
- \param[out] none
- \retval none
-*/
-void rcu_pllpresel_config(uint32_t pll_presel)
-{
- uint32_t reg = 0U;
-
- reg = RCU_CFG1;
-
- /* PLL clock source preselection */
- reg &= ~RCU_CFG1_PLLPRESEL;
- reg |= pll_presel;
-
- RCU_CFG1 = reg;
-}
-
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
-/*!
- \brief configure the PREDV0 division factor
- \param[in] predv0_div: PREDV0 division factor
- \arg RCU_PREDV0_DIVx, x = 1,2
- \param[out] none
- \retval none
-*/
-void rcu_predv0_config(uint32_t predv0_div)
-{
- uint32_t reg = 0U;
-
- reg = RCU_CFG0;
- /* reset PREDV0 bit */
- reg &= ~RCU_CFG0_PREDV0;
- if (RCU_PREDV0_DIV2 == predv0_div) {
- /* set the PREDV0 bit */
- reg |= RCU_CFG0_PREDV0;
- }
-
- RCU_CFG0 = reg;
-}
-#elif defined(GD32F10X_CL)
-/*!
- \brief configure the PREDV0 division factor and clock source
- \param[in] predv0_source: PREDV0 input clock source selection
- \arg RCU_PREDV0SRC_HXTAL_IRC48M: HXTAL or IRC48M selected as PREDV0 input source clock
- \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock
- \param[in] predv0_div: PREDV0 division factor
- \arg RCU_PREDV0_DIVx, x = 1..16
- \param[out] none
- \retval none
-*/
-void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div)
-{
- uint32_t reg = 0U;
-
- reg = RCU_CFG1;
- /* reset PREDV0SEL and PREDV0 bits */
- reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0);
- /* set the PREDV0SEL and PREDV0 division factor */
- reg |= (predv0_source | predv0_div);
-
- RCU_CFG1 = reg;
-}
-
-/*!
- \brief configure the PREDV1 division factor
- \param[in] predv1_div: PREDV1 division factor
- \arg RCU_PREDV1_DIVx, x = 1..16
- \param[out] none
- \retval none
-*/
-void rcu_predv1_config(uint32_t predv1_div)
-{
- uint32_t reg = 0U;
-
- reg = RCU_CFG1;
- /* reset the PREDV1 bits */
- reg &= ~RCU_CFG1_PREDV1;
- /* set the PREDV1 division factor */
- reg |= predv1_div;
-
- RCU_CFG1 = reg;
-}
-
-/*!
- \brief configure the PLL1 clock
- \param[in] pll_mul: PLL clock multiplication factor
- \arg RCU_PLL1_MULx (x = 8..16, 20)
- \param[out] none
- \retval none
-*/
-void rcu_pll1_config(uint32_t pll_mul)
-{
- RCU_CFG1 &= ~RCU_CFG1_PLL1MF;
- RCU_CFG1 |= pll_mul;
-}
-
-/*!
- \brief configure the PLL2 clock
- \param[in] pll_mul: PLL clock multiplication factor
- \arg RCU_PLL2_MULx (x = 8..16, 18..32, 40)
- \param[out] none
- \retval none
-*/
-void rcu_pll2_config(uint32_t pll_mul)
-{
- RCU_CFG1 &= ~RCU_CFG1_PLL2MF;
- RCU_CFG1 |= pll_mul;
-}
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
-/*!
- \brief configure the ADC prescaler factor
- \param[in] adc_psc: ADC prescaler factor
- \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2
- \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4
- \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6
- \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8
- \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12
- \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16
- \arg RCU_CKADC_CKAHB_DIV5: ADC prescaler select CK_AHB/5
- \arg RCU_CKADC_CKAHB_DIV6: ADC prescaler select CK_AHB/6
- \arg RCU_CKADC_CKAHB_DIV10: ADC prescaler select CK_AHB/10
- \arg RCU_CKADC_CKAHB_DIV20: ADC prescaler select CK_AHB/20
- \param[out] none
- \retval none
-*/
-void rcu_adc_clock_config(uint32_t adc_psc)
-{
- uint32_t reg0, reg1;
-
- /* reset the ADCPSC bits */
- reg0 = RCU_CFG0;
- reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
- reg1 = RCU_CFG1;
- reg1 &= ~RCU_CFG1_ADCPSC_3;
-
- /* set the ADC prescaler factor */
- switch (adc_psc) {
- case RCU_CKADC_CKAPB2_DIV2:
- case RCU_CKADC_CKAPB2_DIV4:
- case RCU_CKADC_CKAPB2_DIV6:
- case RCU_CKADC_CKAPB2_DIV8:
- reg0 |= (adc_psc << 14);
- break;
-
- case RCU_CKADC_CKAPB2_DIV12:
- case RCU_CKADC_CKAPB2_DIV16:
- adc_psc &= ~BIT(2);
- reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2);
- break;
-
- case RCU_CKADC_CKAHB_DIV5:
- case RCU_CKADC_CKAHB_DIV6:
- case RCU_CKADC_CKAHB_DIV10:
- case RCU_CKADC_CKAHB_DIV20:
- adc_psc &= ~BITS(2, 3);
- reg0 |= (adc_psc << 14);
- reg1 |= RCU_CFG1_ADCPSC_3;
- break;
-
- default:
- break;
- }
-
- /* set the register */
- RCU_CFG0 = reg0;
- RCU_CFG1 = reg1;
-}
-
-/*!
- \brief configure the USBD/USBFS prescaler factor
- \param[in] adc_div: USB prescaler factor
- \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5
- \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1
- \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5
- \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2
- \arg RCU_CKUSB_CKPLL_DIV3: USBD/USBFS prescaler select CK_PLL/3
- \arg RCU_CKUSB_CKPLL_DIV3_5: USBD/USBFS prescaler select CK_PLL/3.5
- \arg RCU_CKUSB_CKPLL_DIV4: USBD/USBFS prescaler select CK_PLL/4
- \param[out] none
- \retval none
-*/
-void rcu_usb_clock_config(uint32_t usb_psc)
-{
- uint32_t reg;
-
- reg = RCU_CFG0;
-
- /* configure the USBD/USBFS prescaler factor */
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- reg &= ~RCU_CFG0_USBDPSC;
-#elif defined(GD32F10X_CL)
- reg &= ~RCU_CFG0_USBFSPSC;
-#endif /* GD32F10X_HD and GD32F10X_XD */
-
- RCU_CFG0 = (reg | usb_psc);
-}
-
-/*!
- \brief configure the RTC clock source selection
- \param[in] rtc_clock_source: RTC clock source selection
- only one parameter can be selected which is shown as below:
- \arg RCU_RTCSRC_NONE: no clock selected
- \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
- \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
- \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock
- \param[out] none
- \retval none
-*/
-void rcu_rtc_clock_config(uint32_t rtc_clock_source)
-{
- uint32_t reg;
-
- reg = RCU_BDCTL;
- /* reset the RTCSRC bits and set according to rtc_clock_source */
- reg &= ~RCU_BDCTL_RTCSRC;
- RCU_BDCTL = (reg | rtc_clock_source);
-}
-
-#ifdef GD32F10X_CL
-/*!
- \brief configure the I2S1 clock source selection
- \param[in] i2s_clock_source: I2S1 clock source selection
- only one parameter can be selected which is shown as below:
- \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock
- \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock
- \param[out] none
- \retval none
-*/
-void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
-{
- uint32_t reg;
-
- reg = RCU_CFG1;
- /* reset the I2S1SEL bit and set according to i2s_clock_source */
- reg &= ~RCU_CFG1_I2S1SEL;
- RCU_CFG1 = (reg | i2s_clock_source);
-}
-
-/*!
- \brief configure the I2S2 clock source selection
- \param[in] i2s_clock_source: I2S2 clock source selection
- only one parameter can be selected which is shown as below:
- \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock
- \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock
- \param[out] none
- \retval none
-*/
-void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
-{
- uint32_t reg;
-
- reg = RCU_CFG1;
- /* reset the I2S2SEL bit and set according to i2s_clock_source */
- reg &= ~RCU_CFG1_I2S2SEL;
- RCU_CFG1 = (reg | i2s_clock_source);
-}
-#endif /* GD32F10X_CL */
-
-/*!
- \brief configure the CK48M clock source selection
- \param[in] ck48m_clock_source: CK48M clock source selection
- only one parameter can be selected which is shown as below:
- \arg RCU_CK48MSRC_CKPLL: CK_PLL selected as CK48M source clock
- \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock
- \param[out] none
- \retval none
-*/
-void rcu_ck48m_clock_config(uint32_t ck48m_clock_source)
-{
- uint32_t reg;
-
- reg = RCU_ADDCTL;
- /* reset the CK48MSEL bit and set according to ck48m_clock_source */
- reg &= ~RCU_ADDCTL_CK48MSEL;
- RCU_ADDCTL = (reg | ck48m_clock_source);
-}
-
-/*!
- \brief get the clock stabilization and periphral reset flags
- \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
- \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
- \arg RCU_FLAG_PLLSTB: PLL stabilization flag
- \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only)
- \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only)
- \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
- \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
- \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag
- \arg RCU_FLAG_EPRST: external PIN reset flag
- \arg RCU_FLAG_PORRST: power reset flag
- \arg RCU_FLAG_SWRST: software reset flag
- \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag
- \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag
- \arg RCU_FLAG_LPRST: low-power reset flag
- \param[out] none
- \retval none
-*/
-FlagStatus rcu_flag_get(rcu_flag_enum flag)
-{
- /* get the rcu flag */
- if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/*!
- \brief clear all the reset flag
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_all_reset_flag_clear(void)
-{
- RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
-}
-
-/*!
- \brief get the clock stabilization interrupt and ckm flags
- \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
- \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
- \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
- \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
- \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
- \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only)
- \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only)
- \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
- \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
-{
- /* get the rcu interrupt flag */
- if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/*!
- \brief clear the interrupt flags
- \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
- \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
- \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
- \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
- \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
- \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only)
- \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only)
- \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
- \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear
- \param[out] none
- \retval none
-*/
-void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
-{
- RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
-}
-
-/*!
- \brief enable the stabilization interrupt
- \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
- Only one parameter can be selected which is shown as below:
- \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
- \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
- \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
- \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
- \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
- \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
- \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
- \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
- \param[out] none
- \retval none
-*/
-void rcu_interrupt_enable(rcu_int_enum stab_int)
-{
- RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
-}
-
-/*!
- \brief disable the stabilization interrupt
- \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
- \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
- \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
- \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
- \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
- \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
- \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
- \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
- \param[out] none
- \retval none
-*/
-void rcu_interrupt_disable(rcu_int_enum stab_int)
-{
- RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
-}
-
-/*!
- \brief configure the LXTAL drive capability
- \param[in] lxtal_dricap: drive capability of LXTAL
- only one parameter can be selected which is shown as below:
- \arg RCU_LXTAL_LOWDRI: lower driving capability
- \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability
- \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability
- \arg RCU_LXTAL_HIGHDRI: higher driving capability
- \param[out] none
- \retval none
-*/
-void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
-{
- uint32_t reg;
-
- reg = RCU_BDCTL;
-
- /* reset the LXTALDRI bits and set according to lxtal_dricap */
- reg &= ~RCU_BDCTL_LXTALDRI;
- RCU_BDCTL = (reg | lxtal_dricap);
-}
-
-/*!
- \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
- \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
- \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
- \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M)
- \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
- \arg RCU_PLL_CK: phase locked loop(PLL)
- \arg RCU_PLL1_CK: phase locked loop 1(CL series only)
- \arg RCU_PLL2_CK: phase locked loop 2(CL series only)
- \param[out] none
- \retval ErrStatus: SUCCESS or ERROR
-*/
-ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
-{
- uint32_t stb_cnt = 0U;
- ErrStatus reval = ERROR;
- FlagStatus osci_stat = RESET;
-
- switch (osci) {
- /* wait HXTAL stable */
- case RCU_HXTAL:
- while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) {
- reval = SUCCESS;
- }
- break;
-
- /* wait LXTAL stable */
- case RCU_LXTAL:
- while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) {
- reval = SUCCESS;
- }
- break;
-
- /* wait IRC8M stable */
- case RCU_IRC8M:
- while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) {
- reval = SUCCESS;
- }
- break;
-
- /* wait IRC48M stable */
- case RCU_IRC48M:
- while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) {
- reval = SUCCESS;
- }
- break;
-
- /* wait IRC40K stable */
- case RCU_IRC40K:
- while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) {
- reval = SUCCESS;
- }
- break;
-
- /* wait PLL stable */
- case RCU_PLL_CK:
- while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) {
- reval = SUCCESS;
- }
- break;
-
-#ifdef GD32F10X_CL
- /* wait PLL1 stable */
- case RCU_PLL1_CK:
- while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) {
- reval = SUCCESS;
- }
- break;
- /* wait PLL2 stable */
- case RCU_PLL2_CK:
- while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
- osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) {
- reval = SUCCESS;
- }
- break;
-#endif /* GD32F10X_CL */
-
- default:
- break;
- }
-
- /* return value */
- return reval;
-}
-
-/*!
- \brief turn on the oscillator
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
- \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
- \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
- \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M)
- \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
- \arg RCU_PLL_CK: phase locked loop(PLL)
- \arg RCU_PLL1_CK: phase locked loop 1(CL series only)
- \arg RCU_PLL2_CK: phase locked loop 2(CL series only)
- \param[out] none
- \retval none
-*/
-void rcu_osci_on(rcu_osci_type_enum osci)
-{
- RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
-}
-
-/*!
- \brief turn off the oscillator
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
- \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
- \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
- \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M)
- \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
- \arg RCU_PLL_CK: phase locked loop(PLL)
- \arg RCU_PLL1_CK: phase locked loop 1(CL series only)
- \arg RCU_PLL2_CK: phase locked loop 2(CL series only)
- \param[out] none
- \retval none
-*/
-void rcu_osci_off(rcu_osci_type_enum osci)
-{
- RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
-}
-
-/*!
- \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
- \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
- \param[out] none
- \retval none
-*/
-void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
-{
- uint32_t reg;
-
- switch (osci) {
- /* enable HXTAL to bypass mode */
- case RCU_HXTAL:
- reg = RCU_CTL;
- RCU_CTL &= ~RCU_CTL_HXTALEN;
- RCU_CTL = (reg | RCU_CTL_HXTALBPS);
- break;
- /* enable LXTAL to bypass mode */
- case RCU_LXTAL:
- reg = RCU_BDCTL;
- RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
- RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
- break;
- case RCU_IRC8M:
- case RCU_IRC48M:
- case RCU_IRC40K:
- case RCU_PLL_CK:
-#ifdef GD32F10X_CL
- case RCU_PLL1_CK:
- case RCU_PLL2_CK:
-#endif /* GD32F10X_CL */
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
- \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
- \param[out] none
- \retval none
-*/
-void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
-{
- uint32_t reg;
-
- switch (osci) {
- /* disable HXTAL to bypass mode */
- case RCU_HXTAL:
- reg = RCU_CTL;
- RCU_CTL &= ~RCU_CTL_HXTALEN;
- RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
- break;
- /* disable LXTAL to bypass mode */
- case RCU_LXTAL:
- reg = RCU_BDCTL;
- RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
- RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
- break;
- case RCU_IRC8M:
- case RCU_IRC48M:
- case RCU_IRC40K:
- case RCU_PLL_CK:
-#ifdef GD32F10X_CL
- case RCU_PLL1_CK:
- case RCU_PLL2_CK:
-#endif /* GD32F10X_CL */
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief enable the HXTAL clock monitor
- \param[in] none
- \param[out] none
- \retval none
-*/
-
-void rcu_hxtal_clock_monitor_enable(void)
-{
- RCU_CTL |= RCU_CTL_CKMEN;
-}
-
-/*!
- \brief disable the HXTAL clock monitor
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_hxtal_clock_monitor_disable(void)
-{
- RCU_CTL &= ~RCU_CTL_CKMEN;
-}
-
-/*!
- \brief set the IRC8M adjust value
- \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
- \param[out] none
- \retval none
-*/
-void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
-{
- uint32_t reg;
-
- reg = RCU_CTL;
- /* reset the IRC8MADJ bits and set according to irc8m_adjval */
- reg &= ~RCU_CTL_IRC8MADJ;
- RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3));
-}
-
-/*!
- \brief deep-sleep mode voltage select
- \param[in] dsvol: deep sleep mode voltage
- only one parameter can be selected which is shown as below:
- \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
- \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
- \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V
- \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V
- \param[out] none
- \retval none
-*/
-void rcu_deepsleep_voltage_set(uint32_t dsvol)
-{
- dsvol &= RCU_DSV_DSLPVS;
- RCU_DSV = dsvol;
-}
-
-/*!
- \brief get the system clock, bus and peripheral clock frequency
- \param[in] clock: the clock frequency which to get
- only one parameter can be selected which is shown as below:
- \arg CK_SYS: system clock frequency
- \arg CK_AHB: AHB clock frequency
- \arg CK_APB1: APB1 clock frequency
- \arg CK_APB2: APB2 clock frequency
- \param[out] none
- \retval clock frequency of system, AHB, APB1, APB2
-*/
-uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
-{
- uint32_t sws, ck_freq = 0U;
- uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
- uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src, idx, clk_exp;
-#ifdef GD32F10X_CL
- uint32_t predv0, predv1, pll1mf;
-#endif /* GD32F10X_CL */
-
- /* exponent of AHB, APB1 and APB2 clock divider */
- uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
- uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
- uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
- sws = GET_BITS(RCU_CFG0, 2, 3);
- switch (sws) {
- /* IRC8M is selected as CK_SYS */
- case SEL_IRC8M:
- cksys_freq = IRC8M_VALUE;
- break;
- /* HXTAL is selected as CK_SYS */
- case SEL_HXTAL:
- cksys_freq = HXTAL_VALUE;
- break;
- /* PLL is selected as CK_SYS */
- case SEL_PLL:
- /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */
- pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
-
- if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) {
- /* PLL clock source is HXTAL or IRC48M */
- pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL);
-
- if (RCU_PLLPRESRC_HXTAL == pllpresel) {
- /* PLL clock source is HXTAL */
- ck_src = HXTAL_VALUE;
- } else {
- /* PLL clock source is IRC48 */
- ck_src = IRC48M_VALUE;
- }
-
-#if (defined(GD32F10X_HD) || defined(GD32F10X_XD))
- predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
- /* PREDV0 input source clock divided by 2 */
- if (RCU_CFG0_PREDV0 == predv0sel) {
- ck_src = HXTAL_VALUE / 2U;
- }
-#elif defined(GD32F10X_CL)
- predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
- /* source clock use PLL1 */
- if (RCU_PREDV0SRC_CKPLL1 == predv0sel) {
- predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
- pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
- if (17U == pll1mf) {
- pll1mf = 20U;
- }
- ck_src = (ck_src / predv1) * pll1mf;
- }
- predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
- ck_src /= predv0;
-#endif /* GD32F10X_HD and GD32F10X_XD */
- } else {
- /* PLL clock source is IRC8M/2 */
- ck_src = IRC8M_VALUE / 2U;
- }
-
- /* PLL multiplication factor */
- pllmf = GET_BITS(RCU_CFG0, 18, 21);
- if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) {
- pllmf |= 0x10U;
- }
- if ((RCU_CFG0 & RCU_CFG0_PLLMF_5)) {
- pllmf |= 0x20U;
- }
- if (pllmf < 15U) {
- pllmf += 2U;
- } else if ((pllmf >= 15U) && (pllmf <= 62U)) {
- pllmf += 1U;
- } else {
- pllmf = 63U;
- }
- cksys_freq = ck_src * pllmf;
-#ifdef GD32F10X_CL
- if (15U == pllmf) {
- cksys_freq = ck_src * 6U + ck_src / 2U;
- }
-#endif /* GD32F10X_CL */
-
- break;
- /* IRC8M is selected as CK_SYS */
- default:
- cksys_freq = IRC8M_VALUE;
- break;
- }
-
- /* calculate AHB clock frequency */
- idx = GET_BITS(RCU_CFG0, 4, 7);
- clk_exp = ahb_exp[idx];
- ahb_freq = cksys_freq >> clk_exp;
-
- /* calculate APB1 clock frequency */
- idx = GET_BITS(RCU_CFG0, 8, 10);
- clk_exp = apb1_exp[idx];
- apb1_freq = ahb_freq >> clk_exp;
-
- /* calculate APB2 clock frequency */
- idx = GET_BITS(RCU_CFG0, 11, 13);
- clk_exp = apb2_exp[idx];
- apb2_freq = ahb_freq >> clk_exp;
-
- /* return the clocks frequency */
- switch (clock) {
- case CK_SYS:
- ck_freq = cksys_freq;
- break;
- case CK_AHB:
- ck_freq = ahb_freq;
- break;
- case CK_APB1:
- ck_freq = apb1_freq;
- break;
- case CK_APB2:
- ck_freq = apb2_freq;
- break;
- default:
- break;
- }
- return ck_freq;
-}
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c
deleted file mode 100644
index 5080fc07f7..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/**
- ******************************************************************************
- * @brief RTC functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_rtc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/** @defgroup RTC_Private_Defines
- * @{
- */
-
-/* RTC LSB Mask */
-#define RTC_LSB_MASK ((uint32_t)0x0000FFFF)
-
-/* RTC Prescaler MSB Mask */
-#define PRL1_MSB_MASK ((uint32_t)0x000F0000)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/**
- * @brief Enable or disable the specified RTC interrupts.
- * @param RTC_INT: specify the RTC interrupt sources
- * This parameter can be any combination of the following value:
- * @arg RTC_INT_OVI: Overflow event interrupt
- * @arg RTC_INT_AI: Alarm event interrupt
- * @arg RTC_INT_SI: Tamper event interrupt
- * @param NewValue: RTC interrupt state to configure
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_INT_Enable(uint16_t RTC_INT, TypeState NewValue)
-{
- if (NewValue == ENABLE) {
- /* Enable the interrupts in RTC_CTLR register */
- RTC->CTLR1 |= RTC_INT;
- } else {
- /* Disable the interrupts in RTC_CTLR register */
- RTC->CTLR1 &= ~((uint16_t)RTC_INT);
- }
-}
-
-/**
- * @brief Enter the RTC configuration mode.
- * @param None
- * @retval None
- */
-void RTC_EnterConfigMode(void)
-{
- /* Enter in the Configuration Mode by set the CMF flag */
- RTC->CTLR2 |= RTC_CTLR2_CMF;
-}
-
-/**
- * @brief Exit from the RTC configuration mode.
- * @param None
- * @retval None
- */
-void RTC_ExitConfigMode(void)
-{
- /* Exit from the Configuration Mode by reset the CMF flag */
- RTC->CTLR2 &= ~((uint16_t)RTC_CTLR2_CMF);
-}
-
-/**
- * @brief Get the RTC counter value.
- * @param None
- * @retval The value of RTC counter.
- */
-uint32_t RTC_GetCounter(void)
-{
- uint16_t temp = 0;
- temp = RTC->CNT2;
- return (((uint32_t)RTC->CNT1 << 16) | temp) ;
-}
-
-/**
- * @brief Set the RTC counter value.
- * @param CounterValue: New value of the RTC counter.
- * @retval None
- */
-void RTC_SetCounter(uint32_t CounterValue)
-{
- RTC_EnterConfigMode();
- /* Set the RTC counter MSB word */
- RTC->CNT1 = CounterValue >> 16;
- /* Set the RTC counter LSB word */
- RTC->CNT2 = (CounterValue & RTC_LSB_MASK);
- RTC_ExitConfigMode();
-}
-
-/**
- * @brief Set the RTC prescaler value.
- * @param PrescalerValue: New value of the RTC prescaler.
- * @retval None
- */
-void RTC_SetPrescaler(uint32_t PrescalerValue)
-{
- RTC_EnterConfigMode();
- /* Set the RTC prescaler MSB word */
- RTC->PLR1 = (PrescalerValue & PRL1_MSB_MASK) >> 16;
- /* Set the RTC prescaler LSB word */
- RTC->PLR2 = (PrescalerValue & RTC_LSB_MASK);
- RTC_ExitConfigMode();
-}
-
-/**
- * @brief Set the RTC alarm value.
- * @param AlarmValue: New value of the RTC alarm.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t AlarmValue)
-{
- RTC_EnterConfigMode();
- /* Set the alarm MSB word */
- RTC->ALRMR1 = AlarmValue >> 16;
- /* Set the alarm LSB word */
- RTC->ALRMR2 = (AlarmValue & RTC_LSB_MASK);
- RTC_ExitConfigMode();
-}
-
-/**
- * @brief Get the RTC divider value.
- * @param None
- * @retval The value of RTC Divider.
- */
-uint32_t RTC_GetDivider(void)
-{
- uint32_t temp = 0x00;
- temp = ((uint32_t)RTC->PREDIV1 & (uint32_t)0x000F) << 16;
- temp |= RTC->PREDIV2;
- return temp;
-}
-
-/**
- * @brief Wait until last write operation on RTC registers has finished.
- * @note This function must be called before any write to RTC registers.
- * @param None
- * @retval None
- */
-void RTC_WaitLWOFF(void)
-{
- /* Loop until RTOFF flag is set */
- while ((RTC->CTLR2 & RTC_FLAG_LWOFF) == (uint16_t)RESET) {
- }
-}
-
-/**
- * @brief Wait until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
- * are synchronized with RTC APB clock.
- * @note This function must be called before any read operation after an APB reset
- * or an APB clock stop.
- * @param None
- * @retval None
- */
-void RTC_WaitRSF(void)
-{
- /* Clear RSF flag */
- RTC->CTLR2 &= ~((uint16_t)RTC_FLAG_RSF);
- /* Loop until RSF flag is set */
- while ((RTC->CTLR2 & RTC_FLAG_RSF) == (uint16_t)RESET) {
- }
-}
-
-/**
- * @brief Check whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifie the flag to check.
- * This parameter can be one the following values:
- * @arg RTC_FLAG_LWOFF: RTC Operation Off flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_OVF: Overflow flag
- * @arg RTC_FLAG_AF: Alarm flag
- * @arg RTC_FLAG_SF: Second flag
- * @retval The new bitstate of RTC_FLAG (SET or RESET).
- */
-TypeState RTC_GetBitState(uint16_t RTC_FLAG)
-{
- if ((RTC->CTLR2 & RTC_FLAG) != (uint16_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the RTC's pending flags.
- * @param RTC_FLAG: specifie the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
- * an APB reset or an APB Clock stop.
- * @arg RTC_FLAG_OVF: Overflow flag
- * @arg RTC_FLAG_AF: Alarm flag
- * @arg RTC_FLAG_SF: Second flag
- * @retval None
- */
-void RTC_ClearBitState(uint16_t RTC_flag)
-{
- /* Clear the corresponding RTC flag */
- RTC->CTLR2 &= ~((uint16_t)RTC_flag);
-}
-
-/**
- * @brief Check whether the specified RTC interrupt has occurred or not.
- * @param RTC_INT: specifie the RTC interrupts sources to check.
- * This parameter can be one of the following values:
- * @arg RTC_INT_OVI: Overflow event interrupt
- * @arg RTC_INT_AI: Alarm event interrupt
- * @arg RTC_INT_SI: Tamper event interrupt
- * @retval The new state of the RTC_IT (SET or RESET).
- */
-TypeState RTC_GetIntBitState(uint16_t RTC_INT)
-{
-
- if (((RTC->CTLR1 & RTC_INT) != (uint16_t)RESET) && ((RTC->CTLR2 & RTC_INT) != (uint16_t)RESET)) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the RTC's interrupt bit.
- * @param RTC_INT: specifie the interrupt bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_INT_OVI: Overflow event interrupt
- * @arg RTC_INT_AI: Alarm event interrupt
- * @arg RTC_INT_SI: Tamper event interrupt
- * @retval None
- */
-void RTC_ClearIntBitState(uint16_t RTC_INT)
-{
- /* Clear the RTC's interrupt bitstate */
- RTC->CTLR2 &= ~((uint16_t)RTC_INT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c
deleted file mode 100644
index 110fe8f410..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/**
- ******************************************************************************
- * @brief SDIO functions of the firmware library.
- ******************************************************************************
- */
-#ifdef GD32F10X_HD
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_sdio.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup SDIO
- * @brief SDIO driver modules
- * @{
- */
-
-/** @defgroup SDIO_Private_Defines
- * @{
- */
-
-/* SDIO registers bit mask */
-/* CLKCTLR register mask */
-#define CLKCTLR_CLEAR_MASK ((uint32_t)0xFFFF8100)
-/* POWER_PWRSTATE mask */
-#define POWER_PWRSTATE_MASK ((uint32_t)0xFFFFFFFC)
-/* DTCTLR register mask */
-#define DTCTLR_CLEAR_MASK ((uint32_t)0xFFFFFF08)
-/* CMD register mask */
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitialize the SDIO .
- * @param None
- * @retval None
- */
-void SDIO_DeInit(void)
-{
- SDIO->POWER = 0x00000000;
- SDIO->CLKCTLR = 0x00000000;
- SDIO->PARA = 0x00000000;
- SDIO->CMD = 0x00000000;
- SDIO->DTTR = 0x00000000;
- SDIO->DTLEN = 0x00000000;
- SDIO->DTCTLR = 0x00000000;
- SDIO->ICR = 0x00C007FF;
- SDIO->IER = 0x00000000;
-}
-
-/**
- * @brief Initialize the SDIO .
- * @param SDIO_InitParaStruct : pointer to a SDIO_InitPara structure .
- * @retval None
- */
-void SDIO_Init(SDIO_InitPara *SDIO_InitParaStruct)
-{
- uint32_t temp = 0;
-
- /* SDIO CLKCTLR Configuration */
- /* Get the SDIO CLKCTLR value */
- temp = SDIO->CLKCTLR;
-
- /* Clear CLKCTLR register */
- temp &= CLKCTLR_CLEAR_MASK;
-
- /* Configure the SDIO_ClockDiv value */
- /* Configure the SDIO_ClockPWRSave value */
- /* Configure the SDIO_ClockBypassState value */
- /* Configure the SDIO_BusMode value */
- /* Configure the SDIO_ClockEdge value */
- /* Configure the SDIO_HWFlowCtrlState value */
- temp |= (SDIO_InitParaStruct->SDIO_ClockDiv | SDIO_InitParaStruct->SDIO_ClockPWRSave |
- SDIO_InitParaStruct->SDIO_ClockBypassState | SDIO_InitParaStruct->SDIO_BusMode |
- SDIO_InitParaStruct->SDIO_ClockEdge | SDIO_InitParaStruct->SDIO_HWFlowCtrlState);
-
- /* Update the SDIO CLKCTLR */
- SDIO->CLKCTLR = temp;
-}
-
-/**
- * @brief Fill each SDIO_InitParaStruct Struct member with a default value.
- * @param SDIO_InitParaStruct: pointer to an SDIO_InitPara structure.
- * @retval None
- */
-void SDIO_ParaInit(SDIO_InitPara *SDIO_InitParaStruct)
-{
- /* Fill the default value */
- SDIO_InitParaStruct->SDIO_ClockDiv = 0x00;
- SDIO_InitParaStruct->SDIO_ClockEdge = SDIO_CLOCKEDGE_RISING;
- SDIO_InitParaStruct->SDIO_ClockBypassState = SDIO_CLOCKBYPASSSTATE_DISABLE;
- SDIO_InitParaStruct->SDIO_ClockPWRSave = SDIO_CLOCKPWRSAVE_DISABLE;
- SDIO_InitParaStruct->SDIO_BusMode = SDIO_BUSMODE_1B;
- SDIO_InitParaStruct->SDIO_HWFlowCtrlState = SDIO_HWFLOWCTRLSTATE_DISABLE;
-}
-
-/**
- * @brief ENABLE or DISABLE the SDIO Clock.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_Clock_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SDIO->CLKCTLR |= SDIO_CLKCTLR_CKEN;
- } else {
- SDIO->CLKCTLR &= (uint16_t)~(SDIO_CLKCTLR_CKEN);
- }
-}
-
-/**
- * @brief Configure the power state of SDIO.
- * @param SDIO_PwrState: new Power state for SDIO.
- * This value will be :
- * @arg SDIO_PWRSTATE_ON
- * @arg SDIO_PWRSTATE_OFF
- * @retval None
- */
-void SDIO_SetPWRState(uint32_t SDIO_PwrState)
-{
- /* Update the SDIO POWER */
- SDIO->POWER |= SDIO_PwrState;
-}
-
-/**
- * @brief Get the power state of SDIO.
- * @param None
- * @retval Power state for SDIO.
- * This value will be :
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPWRState(void)
-{
- return (SDIO->POWER & (~POWER_PWRSTATE_MASK));
-}
-
-/**
- * @brief Configure interrupts enables.
- * @param SDIO_INT: The interrupts sources to configure.
- * This value will be :
- * @arg SDIO_INT_CCRCFAIL: Command response CRC failed interrupt
- * @arg SDIO_INT_DTCRCFAIL: Data CRC failed interrupt
- * @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt
- * @arg SDIO_INT_DTTMOUT: Data timeout interrupt
- * @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt
- * @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt
- * @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt
- * @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide bus mode interrupt
- * @arg SDIO_INT_DTBLKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_INT_CMDRUN: Command transfer in progress interrupt
- * @arg SDIO_INT_TXRUN: Data transmit in progress interrupt
- * @arg SDIO_INT_RXRUN: Data receive in progress interrupt
- * @arg SDIO_INT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_INT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_INT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_INT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_INT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_INT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_INT_TXDTVAL: Data valid in transmit FIFO interrupt
- * @arg SDIO_INT_RXDTVAL: Data valid in receive FIFO interrupt
- * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
- * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_INTConfig(uint32_t SDIO_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the interrupt */
- SDIO->IER |= SDIO_INT;
- } else {
- /* Disable the interrupt */
- SDIO->IER &= ~SDIO_INT;
- }
-}
-
-/**
- * @brief Enable or disable the DMA request for SDIO.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_DMA_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable DMA request */
- SDIO->DTCTLR |= SDIO_DTCTLR_DMAEN;
- } else {
- /* Disenable DMA request */
- SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_DMAEN);
- }
-}
-
-/**
- * @brief Initialize the SDIO Command.
- * @param SDIO_CmdInitParaStruct : pointer to a SDIO_CmdInitPara structure.
- * @retval None
- */
-void SDIO_SendCMD(SDIO_CmdInitPara *SDIO_CmdInitParaStruct)
-{
- uint32_t temp = 0;
-
- /* SDIO PARA Configuration */
- /* Configure the SDIO_CMDParameter value */
- SDIO->PARA = SDIO_CmdInitParaStruct->SDIO_CMDParameter;
-
- /* SDIO CMD Configuration */
- /* Get the SDIO CMD value */
- temp = SDIO->CMD;
- /* Clear CMD register */
- temp &= CMD_CLEAR_MASK;
- /* Configure the SDIO_CMDIndex value */
- /* Configure the SDIO_ResponseType value */
- /* Configure the SDIO_WaitINTState value */
- /* Configure the SDIO_CSMState value */
- temp |= (uint32_t)SDIO_CmdInitParaStruct->SDIO_CMDIndex | SDIO_CmdInitParaStruct->SDIO_ResponseType
- | SDIO_CmdInitParaStruct->SDIO_WaitINTState | SDIO_CmdInitParaStruct->SDIO_CSMState;
-
- /* Update the SDIO CMD */
- SDIO->CMD = temp;
-}
-
-/**
- * @brief Fill SDIO_CmdInitStruct member with a default value.
- * @param SDIO_CmdInitParaStruct: pointer to an SDIO_CmdInitPara structure.
- * @retval None
- */
-void SDIO_CMDParaInit(SDIO_CmdInitPara *SDIO_CmdInitParaStruct)
-{
- /* Fill the default value */
- SDIO_CmdInitParaStruct->SDIO_CMDParameter = 0x00;
- SDIO_CmdInitParaStruct->SDIO_CMDIndex = 0x00;
- SDIO_CmdInitParaStruct->SDIO_ResponseType = SDIO_RESPONSETYPE_NO ;
- SDIO_CmdInitParaStruct->SDIO_WaitINTState = SDIO_WAITINTSTATE_NO;
- SDIO_CmdInitParaStruct->SDIO_CSMState = SDIO_CSMSTATE_DISABLE;
-}
-
-/**
- * @brief Return last response command index.
- * @param None
- * @retval Return last response command index.
- */
-uint8_t SDIO_GetCMDResponse(void)
-{
- return (uint8_t)(SDIO->RESPCMD);
-}
-
-/**
- * @brief Return the response for the last received command.
- * @param SDIO_RESP: The SDIO response registers.
- * This value will be :
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value.
- */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
- __IO uint32_t temp = 0;
-
- temp = SDIO_RESP_ADDR + SDIO_RESP;
-
- return (*(__IO uint32_t *) temp);
-}
-
-/**
- * @brief Initialize the SDIO SDIO_DataInitParaStruct members.
- * @param SDIO_DataInitParaStruct : pointer to a SDIO_DataInitPara structure.
- * @retval None
- */
-void SDIO_DataConfig(SDIO_DataInitPara *SDIO_DataInitParaStruct)
-{
- uint32_t temp = 0;
-
- /* SDIO DTTR Configuration */
- /* Set the SDIO SDIO_DataTimeOut value */
- SDIO->DTTR = SDIO_DataInitParaStruct->SDIO_DataTimeOut;
-
- /* SDIO DTLEN Configuration */
- /* Set the SDIO SDIO_DataLength value */
- SDIO->DTLEN = SDIO_DataInitParaStruct->SDIO_DataLength;
-
- /* SDIO DTCTLR Configuration */
- /* Get the SDIO DTCTLR value */
- temp = SDIO->DTCTLR;
- /* Clear DTCTLR register */
- temp &= DTCTLR_CLEAR_MASK;
- /* Configure the SDIO_DataBlockSize value */
- /* Configure the SDIO_TransDirection value */
- /* Configure the SDIO_TransMode value */
- /* Configure the SDIO_DSMState value */
- temp |= (uint32_t)SDIO_DataInitParaStruct->SDIO_DataBlockSize | SDIO_DataInitParaStruct->SDIO_TransDirection
- | SDIO_DataInitParaStruct->SDIO_TransMode | SDIO_DataInitParaStruct->SDIO_DSMState;
-
- /* Update the SDIO DTCTLR */
- SDIO->DTCTLR = temp;
-}
-
-/**
- * @brief Fill each SDIO_DataInitParaStruct member with a default value.
- * @param SDIO_DataInitParaStruct: pointer to an SDIO_DataInitPara structure.
- * @retval None
- */
-void SDIO_DataParaInit(SDIO_DataInitPara *SDIO_DataInitParaStruct)
-{
- /* Fill the default value */
- SDIO_DataInitParaStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
- SDIO_DataInitParaStruct->SDIO_DataLength = 0x00;
- SDIO_DataInitParaStruct->SDIO_DataBlockSize = SDIO_DATABLOCKSIZE_1B;
- SDIO_DataInitParaStruct->SDIO_TransDirection = SDIO_TRANSDIRECTION_TOCARD;
- SDIO_DataInitParaStruct->SDIO_TransMode = SDIO_TRANSMODE_BLOCK;
- SDIO_DataInitParaStruct->SDIO_DSMState = SDIO_DSMSTATE_DISABLE;
-}
-
-/**
- * @brief Return the number of remaining data bytes to be transferred to card.
- * @param None
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCount(void)
-{
- return SDIO->DTCNT;
-}
-
-/**
- * @brief Read one word from receive FIFO.
- * @param None
- * @retval Data received
- */
-uint32_t SDIO_ReadData(void)
-{
- return SDIO->FIFO;
-}
-
-/**
- * @brief Write one word to transmit FIFO.
- * @param Data: 32-bit data write to the card.
- * @retval None
- */
-void SDIO_WriteData(uint32_t Data)
-{
- SDIO->FIFO = Data;
-}
-
-/**
- * @brief Return the number of words remaining to be written or read from FIFO.
- * @param None
- * @retval Remaining number of words.
- */
-uint32_t SDIO_GetFIFOCount(void)
-{
- return SDIO->FIFOCNT;
-}
-
-/**
- * @brief Start SD I/O Read Wait operation.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StartSDIOReadWait(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Start Read Wait operation */
- SDIO->DTCTLR |= SDIO_DTCTLR_RWSTART;
- } else {
- SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWSTART);
- }
-}
-
-/**
- * @brief Stop the SD I/O Read Wait operation.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_StopSDIOReadWait(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SDIO->DTCTLR |= SDIO_DTCTLR_RWSTOP;
- } else {
- /* Stop Read Wait operation */
- SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWSTOP);
- }
-}
-
-/**
- * @brief Configure the SD I/O read wait mode.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
- * This value will be :
- * @arg SDIO_READWAITMODE_CLK: Read Wait operation realize by stopping SDIOCLK
- * @arg SDIO_READWAITMODE_DAT2: Read Wait operation use SDIO_DAT2
- * @retval None
- */
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
- if (SDIO_ReadWaitMode == SDIO_READWAITMODE_CLK) {
- /* Read Wait operation stop SDIOCLK */
- SDIO->DTCTLR |= SDIO_DTCTLR_RWMODE;
- } else {
- /* Read Wait operation use SDIO_DAT2 */
- SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWMODE);
- }
-}
-
-/**
- * @brief SD I/O Mode Operation configuration.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SetSDIOOperation(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable I/O Mode Operation */
- SDIO->DTCTLR |= SDIO_DTCTLR_SDIOEN;
- } else {
- /* Disenable I/O Mode Operation */
- SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_SDIOEN);
- }
-}
-
-/**
- * @brief Enable or disable the SD I/O suspend operation.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendSDIOSuspend_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable suspend operation */
- SDIO->CMD |= SDIO_CMD_SDIOSUSPEND;
- } else {
- /* Disenable suspend operation */
- SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_SDIOSUSPEND);
- }
-}
-
-/**
- * @brief Enable or disable the CE-ATA command completion signal.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CMDCompletion_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable CE-ATA command completion signal */
- SDIO->CMD |= SDIO_CMD_ENCMDC;
- } else {
- /* Disenable CE-ATA command completion signal */
- SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_ENCMDC);
- }
-}
-
-/**
- * @brief Enable or disable the CE-ATA interrupt.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_CEATAInt_Enable(TypeState NewValue)
-{
- if (NewValue != ENABLE) {
- /* Enable CE-ATA interrupt */
- SDIO->CMD |= SDIO_CMD_NIEN;
- } else {
- /* Disenable CE-ATA interrupt */
- SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_NIEN);
- }
-}
-
-/**
- * @brief Send CE-ATA command (CMD61).
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SDIO_SendCEATA_Enable(TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SDIO->CMD |= SDIO_CMD_ATACMD;
- } else {
- SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_ATACMD);
- }
-}
-
-/**
- * @brief Check whether the flag is set or not.
- * @param SDIO_FLAG: the flag to check.
- * This value will be :
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC failed)
- * @arg SDIO_FLAG_DTCRCFAIL: Data block sent/received (CRC failed)
- * @arg SDIO_FLAG_CMDTMOUT: Command response timeout
- * @arg SDIO_FLAG_DTTMOUT: Data timeout
- * @arg SDIO_FLAG_TXURE: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXORE: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DTEND: Data end (data counter, SDIDTCNT, is zero)
- * @arg SDIO_FLAG_STBITE: Start bit not detected on all data signals in wide
- * bus mode.
- * @arg SDIO_FLAG_DTBLKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDRUN: Command transfer in progress
- * @arg SDIO_FLAG_TXRUN: Data transmit in progress
- * @arg SDIO_FLAG_RXRUN: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDTVAL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDTVAL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received
- * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-TypeState SDIO_GetBitState(uint32_t SDIO_FLAG)
-{
- if ((SDIO->STR & SDIO_FLAG) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the pending flags.
- * @param SDIO_FLAG: the flag to clear.
- * This value will be :
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DTCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CMDTMOUT: Command response timeout
- * @arg SDIO_FLAG_DTTMOUT: Data timeout
- * @arg SDIO_FLAG_TXURE: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXORE: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DTEND: Data end (data counter, SDIO_DTCNT, is zero)
- * @arg SDIO_FLAG_STBITE: Start bit not detected on all data signals in wide bus mode
- * @arg SDIO_FLAG_DTBLKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received
- * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearBitState(uint32_t SDIO_FLAG)
-{
- SDIO->ICR = SDIO_FLAG;
-}
-
-/**
- * @brief Check whether the interrupt is pending or not.
- * @param SDIO_INT: the SDIO interrupt source to check.
- * This value will be :
- * @arg SDIO_INT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_INT_DTCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt
- * @arg SDIO_INT_DTTMOUT: Data timeout interrupt
- * @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt
- * @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt
- * @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt
- * @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide bus mode interrupt
- * @arg SDIO_INT_DTBLKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_INT_CMDRUN: Command transfer in progress interrupt
- * @arg SDIO_INT_TXRUN: Data transmit in progress interrupt
- * @arg SDIO_INT_RXRUN: Data receive in progress interrupt
- * @arg SDIO_INT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_INT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_INT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_INT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_INT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_INT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_INT_TXDTVAL: Data available in transmit FIFO interrupt
- * @arg SDIO_INT_RXDTVAL: Data available in receive FIFO interrupt
- * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
- * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt
- * @retval The new state of SDIO_INT (SET or RESET).
- */
-TypeState SDIO_GetIntBitState(uint32_t SDIO_INT)
-{
- if ((SDIO->STR & SDIO_INT) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt pending bits.
- * @param SDIO_INT: the interrupt pending bit to clear.
- * This value will be :
- * @arg SDIO_INT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_INT_DTCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt
- * @arg SDIO_INT_DTTMOUT: Data timeout interrupt
- * @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt
- * @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt
- * @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt
- * @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide
- * bus mode interrupt
- * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt
- * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61
- * @retval None
- */
-void SDIO_ClearIntBitState(uint32_t SDIO_INT)
-{
- SDIO->ICR = SDIO_INT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c
deleted file mode 100644
index b55a6dc911..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/**
- ******************************************************************************
- * @brief SPI functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_spi.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/** @defgroup SPI_Private_Defines
- * @{
- */
-
-/* SPI registers Masks */
-#define CTLR1_CLEAR_MASK ((uint16_t)0x3040)
-#define I2SCTLR_CLEAR_MASK ((uint16_t)0xF040)
-
-/* I2S clock source selection Masks */
-#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
-#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
-#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
-#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
-/**
- * @}
- */
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the SPIx and the I2Sx peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
-{
- if (SPIx == SPI1) {
- /* Reset SPI1 */
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_SPI1RST, ENABLE);
-
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_SPI1RST, DISABLE);
- } else if (SPIx == SPI2) {
- /* Reset SPI2 and I2S2 peripheral */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI2RST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI2RST, DISABLE);
- } else if (SPIx == SPI3) {
- /* Reset SPI3 and I2S3 peripheral */
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI3RST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI3RST, DISABLE);
- }
-}
-
-/**
- * @brief Initialize the SPIx peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_InitParameter: The structuer contains configuration information.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef *SPIx, SPI_InitPara *SPI_InitParameter)
-{
- uint16_t temp_ctrl1 = 0;
-
- /* Configure SPIx CTRL1 according to the SPI_InitParameter */
- temp_ctrl1 = SPIx->CTLR1;
- temp_ctrl1 &= CTLR1_CLEAR_MASK;
- temp_ctrl1 |= (uint16_t)((uint32_t)SPI_InitParameter->SPI_TransType | SPI_InitParameter->SPI_Mode |
- SPI_InitParameter->SPI_FrameFormat | SPI_InitParameter->SPI_SCKPL |
- SPI_InitParameter->SPI_SCKPH | SPI_InitParameter->SPI_SWNSSEN |
- SPI_InitParameter->SPI_PSC | SPI_InitParameter->SPI_FirstBit);
- SPIx->CTLR1 = temp_ctrl1;
-
- /* Configure SPIx CRC Polynomial */
- SPIx->CPR = SPI_InitParameter->SPI_CRCPOL;
-
- /* Configure the I2SSEL bit in I2SCTLR register as SPI mode */
- SPIx->I2SCTLR &= ~SPI_I2SCTLR_I2SSEL;
-
-}
-
-/**
- * @brief Initialize the I2Sx peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 2 or 3.
- * @param I2S_InitParameter: The structuer contains configuration information.
- * @retval None
- */
-void I2S_Init(SPI_TypeDef *SPIx, I2S_InitPara *I2S_InitParameter)
-{
- uint16_t temp_i2sctrl = 0, div = 2, of = 0;
- uint32_t temp = 0;
- RCC_ClocksPara RCC_Clocks;
- uint32_t sourceclock = 0;
-
- /* SPIx I2SCTLR & I2SCKP Configuration */
- /* Deinit I2SCTLR I2SCKP register */
- SPIx->I2SCTLR &= I2SCTLR_CLEAR_MASK;
- SPIx->I2SCKP = 0x0002;
-
- /* Default config of the prescaler*/
- if (I2S_InitParameter->I2S_AudioFreq == I2S_AUDIOFREQ_DEFAULT) {
- of = (uint16_t)0;
- div = (uint16_t)2;
- } else {
- /* Get the I2S clock source */
- if (((uint32_t)SPIx) == SPI2_BASE) {
- temp = I2S2_CLOCK_SRC;
- } else {
- temp = I2S3_CLOCK_SRC;
- }
-
- /* I2S clock source configuration depend on different device */
-#ifdef GD32F10X_CL
- if ((RCC->GCFGR2 & temp) != 0) {
- /* Get RCC PLL3 multiplier */
- temp = (uint32_t)((RCC->GCFGR2 & I2S_MUL_MASK) >> 12);
-
- if ((temp > 5) && (temp < 15)) {
- /* Multiplier is between 8 and 14 (value 15 is forbidden) */
- temp += 2;
- } else {
- if (temp == 15) {
- /* Multiplier is 20 */
- temp = 20;
- }
- }
- /* Get the PREDV2 value */
- sourceclock = (uint32_t)(((RCC->GCFGR2 & I2S_DIV_MASK) >> 4) + 1);
-
- /* Calculate sourceclock based on PLL3 and PREDV2 */
- sourceclock = (uint32_t)((HSE_VALUE / sourceclock) * temp * 2);
- } else {
- /* Get system clock */
- RCC_GetClocksFreq(&RCC_Clocks);
- sourceclock = RCC_Clocks.CK_SYS_Frequency;
- }
-#else
- /* Get system clock */
- RCC_GetClocksFreq(&RCC_Clocks);
- sourceclock = RCC_Clocks.CK_SYS_Frequency;
-#endif /* GD32F10X_CL */
-
- /* Calculate the prescaler depending on the MCLK output state and the data format with a flaoting point. */
- if (I2S_InitParameter->I2S_MCKOE == I2S_MCK_ENABLE) {
- temp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitParameter->I2S_AudioFreq)) + 5);
- } else {
- if (I2S_InitParameter->I2S_FrameFormat == I2S_FRAMEFORMAT_DL16b_CL16b) {
- temp = (uint16_t)(((((sourceclock / 32) * 10) / I2S_InitParameter->I2S_AudioFreq)) + 5);
- } else {
- temp = (uint16_t)(((((sourceclock / 64) * 10) / I2S_InitParameter->I2S_AudioFreq)) + 5);
- }
- }
-
- /* Remove the flaoting point */
- temp = temp / 10;
- of = (uint16_t)(temp & (uint16_t)0x0001);
- div = (uint16_t)((temp - of) / 2);
- of = (uint16_t)(of << 8);
- }
-
- /* Inappropriate prescaler, Set the default values */
- if ((div < 1) || (div > 0xFF)) {
- div = 2;
- of = 0;
- }
-
- /* Configure SPIx I2SCKP */
- SPIx->I2SCKP = (uint16_t)(div | (uint16_t)(of | (uint16_t)I2S_InitParameter->I2S_MCKOE));
-
- /* Configure SPIx I2SCTLR according to the I2S_InitParameter */
- temp_i2sctrl = SPIx->I2SCTLR;
- temp_i2sctrl |= (uint16_t)(SPI_I2SCTLR_I2SSEL | (uint16_t)(I2S_InitParameter->I2S_Mode | \
- (uint16_t)(I2S_InitParameter->I2S_STD | (uint16_t)(I2S_InitParameter->I2S_FrameFormat | \
- (uint16_t)I2S_InitParameter->I2S_CKPL))));
- SPIx->I2SCTLR = temp_i2sctrl;
-
-}
-
-/**
- * @brief Initial SPI_InitParameter members.
- * @param SPI_InitParameter : pointer to a SPI_InitPara structure.
- * @retval None
- */
-void SPI_ParaInit(SPI_InitPara *SPI_InitParameter)
-{
- /* Reset SPI init structure parameters values */
- SPI_InitParameter->SPI_TransType = SPI_TRANSTYPE_FULLDUPLEX;
- SPI_InitParameter->SPI_Mode = SPI_MODE_SLAVE;
- SPI_InitParameter->SPI_FrameFormat = SPI_FRAMEFORMAT_8BIT;
- SPI_InitParameter->SPI_SCKPL = SPI_SCKPL_LOW;
- SPI_InitParameter->SPI_SCKPH = SPI_SCKPH_1EDGE;
- SPI_InitParameter->SPI_SWNSSEN = SPI_SWNSS_HARD;
- SPI_InitParameter->SPI_PSC = SPI_PSC_2;
- SPI_InitParameter->SPI_FirstBit = SPI_FIRSTBIT_MSB;
- SPI_InitParameter->SPI_CRCPOL = 7;
-}
-
-/**
- * @brief Initial I2S_InitParameter members.
- * @param I2S_InitParameter : pointer to a I2S_InitPara structure.
- * @retval None
- */
-void I2S_ParaInit(I2S_InitPara *I2S_InitParameter)
-{
- /* Reset I2S init structure parameters values */
- I2S_InitParameter->I2S_Mode = I2S_MODE_SLAVETX;
- I2S_InitParameter->I2S_STD = I2S_STD_PHILLIPS;
- I2S_InitParameter->I2S_FrameFormat = I2S_FRAMEFORMAT_DL16b_CL16b;
- I2S_InitParameter->I2S_MCKOE = I2S_MCK_DISABLE;
- I2S_InitParameter->I2S_AudioFreq = I2S_AUDIOFREQ_DEFAULT;
- I2S_InitParameter->I2S_CKPL = I2S_CKPL_LOW;
-}
-
-/**
- * @brief Enable or disable the SPI peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Enable(SPI_TypeDef *SPIx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SPIx->CTLR1 |= SPI_CTLR1_SPIEN;
- } else {
- SPIx->CTLR1 &= ~SPI_CTLR1_SPIEN;
- }
-}
-
-/**
- * @brief Enable or disable the I2S peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 2 or 3.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Enable(SPI_TypeDef *SPIx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SPIx->I2SCTLR |= SPI_I2SCTLR_I2SEN;
- } else {
- SPIx->I2SCTLR &= ~SPI_I2SCTLR_I2SEN;
- }
-}
-
-/**
- * @brief Enable or disable the SPI or I2S interrupts.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_I2S_INT: specifies the SPI or I2S interrupt source. Select one of the follwing values :
- * @arg SPI_I2S_INT_TBE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_INT_RBNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_INT_ERR: Error interrupt mask
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT, TypeState NewValue)
-{
- uint16_t intmask = 0 ;
-
- /* Get the interrupt enable bit in CTRL2 */
- intmask = (uint16_t)1 << (uint16_t)(SPI_I2S_INT >> 4);
-
- /* Enable or disable the selected interrupt */
- if (NewValue != DISABLE) {
- SPIx->CTLR2 |= intmask;
- } else {
- SPIx->CTLR2 &= (uint16_t)~intmask;
- }
-}
-
-/**
- * @brief Enable or disable the SPIx or I2Sx DMA transfer request.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_I2S_DMAReq: Select the SPI or I2S DMA transfer request. Select one of the follwing values :
- * @arg SPI_I2S_DMA_TX: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMA_RX: Rx buffer DMA transfer request
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMA_Enable(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SPIx->CTLR2 |= SPI_I2S_DMAReq;
- } else {
- SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @brief Send a Data by the SPIx or I2Sx peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param Data : Data to be Send.
- * @retval None
- */
-void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
-{
- SPIx->DTR = Data;
-}
-
-/**
- * @brief Return the received data by the SPIx or I2Sx peripheral.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
-{
- return SPIx->DTR;
-}
-
-/**
- * @brief NSS pin internal software management.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_SWNSS: specifies the SPI NSS internal state. Select one of the follwing values :
- * @arg SPI_SWNSS_SET: Set NSS pin internally
- * @arg SPI_SWNSS_RESET: Reset NSS pin internally
- * @retval None
- */
-void SPI_SWNSSConfig(SPI_TypeDef *SPIx, uint16_t SPI_SWNSS)
-{
- if (SPI_SWNSS != SPI_SWNSS_RESET) {
- /* Set NSS pin */
- SPIx->CTLR1 |= SPI_CTLR1_SWNSS;
- } else {
- /* Reset NSS pin */
- SPIx->CTLR1 &= ~SPI_CTLR1_SWNSS;
- }
-}
-
-/**
- * @brief Enable or disable the NSS output.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_NSSDRV(SPI_TypeDef *SPIx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- SPIx->CTLR2 |= SPI_CTLR2_NSSDRV;
- } else {
- SPIx->CTLR2 &= ~SPI_CTLR2_NSSDRV;
- }
-}
-
-/**
- * @brief Configure the data frame format.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_FrameFormat: Select the data frame format. Select one of the follwing values :
- * @arg SPI_FRAMEFORMAT_16BIT: Set data frame format to 16bit
- * @arg SPI_FRAMEFORMAT_8BIT: Set data frame format to 8bit
- * @retval None
- */
-void SPI_FrameFormatConfig(SPI_TypeDef *SPIx, uint16_t SPI_FrameFormat)
-{
- /* Clear FF16 bit */
- SPIx->CTLR1 &= (uint16_t)~SPI_FRAMEFORMAT_16BIT;
- /* Set new FF16 bit value */
- SPIx->CTLR1 |= SPI_FrameFormat;
-}
-
-/**
- * @brief Send the SPIx CRC value.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @retval None
- */
-void SPI_SendCRCNext(SPI_TypeDef *SPIx)
-{
- /* Enable the CRC transmission */
- SPIx->CTLR1 |= SPI_CTLR1_CRCNT;
-}
-
-/**
- * @brief Enable or disable the CRC calculation.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CRC_Enable(SPI_TypeDef *SPIx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the CRC calculation */
- SPIx->CTLR1 |= SPI_CTLR1_CRCEN;
- } else {
- /* Disable the CRC calculation */
- SPIx->CTLR1 &= ~SPI_CTLR1_CRCEN;
- }
-}
-
-/**
- * @brief Get the transmit or the receive CRC register value.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_CRC: Select the transmit or the receive CRC register. Select one of the follwing values :
- * @arg SPI_CRC_TX: Selects Tx CRC register
- * @arg SPI_CRC_RX: Selects Rx CRC register
- * @retval The selected CRC register value.
- */
-uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
-{
- if (SPI_CRC != SPI_CRC_RX) {
- /* Transmit CRC value */
- return SPIx->TCR;
- } else {
- /* Receive CRC value */
- return SPIx->RCR;
- }
-}
-
-/**
- * @brief Get the CRC Polynomial value.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @retval The CRC Polynomial value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
- return SPIx->CPR;
-}
-
-/**
- * @brief Select the transfer direction in bidirectional mode.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_BDOE: The transfer direction in bi-directional mode. Select one of the follwing values :
- * @arg SPI_BDOE_TX: Selects Tx transmission direction
- * @arg SPI_BDOE_RX: Selects Rx receive direction
- * @retval None
- */
-void SPI_BDOEConfig(SPI_TypeDef *SPIx, uint16_t SPI_BDOE)
-{
- if (SPI_BDOE == SPI_BDOE_TX) {
- /* Transmit only mode*/
- SPIx->CTLR1 |= SPI_BDOE_TX;
- } else {
- /* Receive only mode */
- SPIx->CTLR1 &= SPI_BDOE_RX;
- }
-}
-
-/**
- * @brief Check whether the flag is set or not.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_I2S_FLAG: Select the flag. Select one of the follwing values :
- * @arg SPI_FLAG_TBE: Transmit buffer empty flag.
- * @arg SPI_FLAG_RBNE: Receive buffer not empty flag.
- * @arg SPI_FLAG_BSY: Busy flag.
- * @arg SPI_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg I2S_FLAG_TBE: Transmit buffer empty flag.
- * @arg I2S_FLAG_RBNE: Receive buffer not empty flag.
- * @arg I2S_FLAG_BSY: Busy flag.
- * @arg I2S_FLAG_OVR: Overrun flag.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG.
- */
-TypeState SPI_I2S_GetBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the status of the selected flag */
- if ((SPIx->STR & SPI_I2S_FLAG) != (uint16_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the flag, only used for clear CRCERR flag.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_I2S_FLAG: Select the flag. This parametric only can be SPI_FLAG_CRCERR.
- * @note
- * The other flags are cleared by software sequences:
- * - OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DTR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_STR register (SPI_I2S_GetBitState()).
- * - UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_STR register (SPI_I2S_GetBitState()).
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_STR register (SPI_I2S_GetBitState()) followed by a
- * write operation to SPI_CTLR1 register (SPI_Enable() to enable the SPI).
- * @retval None
- */
-void SPI_I2S_ClearBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
-{
- SPIx->STR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Check whether interrupt has occurred.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_I2S_INT: Select the SPI/I2S interrupt. Select one of the follwing values :
- * @arg SPI_I2S_INT_TBE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_INT_RBNE: Receive buffer not empty interrupt.
- * @arg SPI_I2S_INT_OVR: Overrun interrupt.
- * @arg SPI_INT_MODF: Mode Fault interrupt.
- * @arg SPI_INT_CRCERR: CRC Error interrupt.
- * @arg I2S_INT_UDR: Underrun Error interrupt.
- * @retval The new state of SPI_I2S_INT.
- */
-TypeState SPI_I2S_GetIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT)
-{
- uint16_t intposition = 0, intmask = 0;
- /* Get the interrupt pending bit and enable bit */
- intposition = 0x01 << (SPI_I2S_INT & 0x0F);
- intmask = 0x01 << (SPI_I2S_INT >> 4);
-
- /* Check the status of the interrupt */
- if (((SPIx->STR & intposition) != (uint16_t)RESET) && (SPIx->CTLR2 & intmask)) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the SPIx or I2S interrupt pending bit, only uesd for clear CRCERR interrupt.
- * @param SPIx: the SPI/I2S peripheral where x can be 1..3.
- * @param SPI_I2S_INT: Select the SPI or I2S interrupt. This parametric only can be SPI_INT_CRCERR.
- * @note
- * The other flags are cleared by software sequences:
- * - OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DTR register (SPI_I2S_ReceiveData()) followed by a read
- * operation to SPI_STR register (SPI_I2S_GetBitState()).
- * - UDR (UnderRun error) flag is cleared by a read operation to
- * SPI_STR register (SPI_I2S_GetBitState()).
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_STR register (SPI_I2S_GetBitState()) followed by a
- * write operation to SPI_CTLR1 register (SPI_Enable() to enable the SPI).
- * @retval None
- */
-void SPI_I2S_ClearIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT)
-{
- uint16_t itpos = 0;
-
- /* Clear the select interrupt pending bit. */
- itpos = 0x01 << (SPI_I2S_INT & 0x0F);
- SPIx->STR = (uint16_t)~itpos;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c
deleted file mode 100644
index d5fd7fdf74..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c
+++ /dev/null
@@ -1,2360 +0,0 @@
-/**
- ******************************************************************************
- * @brief TIMER functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_timer.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup TIMER
- * @brief TIMER driver modules
- * @{
- */
-
-/** @defgroup TIMER_Private_Defines
- * @{
- */
-/* TIMER registers bit mask */
-#define SMC_ETR_MASK ((uint16_t)0x00FF)
-#define CHCTLR_OFFSET ((uint16_t)0x0018)
-#define CHE_CHE_SET ((uint16_t)0x0001)
-#define CHE_CHNE_SET ((uint16_t)0x0004)
-/**
- * @}
- */
-
-/* Private function prototypes */
-static void TI1_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter);
-static void TI2_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter);
-static void TI3_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter);
-static void TI4_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter);
-
-/** @defgroup TIMER_Private_Functions
- * @{
- */
-
-/**
- * @brief Deinitialize the TIMER .
- * @param TIMERx: x ={ 0-13 } .
- * @retval None
- */
-void TIMER_DeInit(TIMER_TypeDef *TIMERx)
-{
- if (TIMERx == TIMER0) {
- RCC->APB2RCR |= RCC_APB2PERIPH_TIMER0RST;
- RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER0;
- } else if (TIMERx == TIMER1) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER1RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER1;
- } else if (TIMERx == TIMER2) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER2RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER2;
- } else if (TIMERx == TIMER3) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER3RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER3;
- } else if (TIMERx == TIMER4) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER4RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER4;
- } else if (TIMERx == TIMER5) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER5RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER5;
- } else if (TIMERx == TIMER6) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER6RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER6;
- } else if (TIMERx == TIMER7) {
- RCC->APB2RCR |= RCC_APB2PERIPH_TIMER7RST;
- RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER7;
- } else if (TIMERx == TIMER8) {
- RCC->APB2RCR |= RCC_APB2PERIPH_TIMER8RST;
- RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER8;
- } else if (TIMERx == TIMER9) {
- RCC->APB2RCR |= RCC_APB2PERIPH_TIMER9RST;
- RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER9;
- } else if (TIMERx == TIMER10) {
- RCC->APB2RCR |= RCC_APB2PERIPH_TIMER10RST;
- RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER10;
- } else if (TIMERx == TIMER11) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER11RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER11;
- } else if (TIMERx == TIMER12) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER12RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER12;
- } else if (TIMERx == TIMER13) {
- RCC->APB1RCR |= RCC_APB1PERIPH_TIMER13RST;
- RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER13;
- }
-}
-
-/**
- * @brief Initialize the specified Timer
- * @param TIMERx: x ={ 0 -13 } .
- * @param TIMER_Init: pointer to a TIMER_BaseInitPara structure.
- * @retval None
- */
-void TIMER_BaseInit(TIMER_TypeDef *TIMERx, TIMER_BaseInitPara *TIMER_Init)
-{
- uint16_t tmpctlr1 = 0;
-
- tmpctlr1 = TIMERx->CTLR1;
-
- if ((TIMERx == TIMER0) || (TIMERx == TIMER7) || (TIMERx == TIMER1) || (TIMERx == TIMER2) ||
- (TIMERx == TIMER3) || (TIMERx == TIMER4) || (TIMERx == TIMER8) || (TIMERx == TIMER9)
- || (TIMERx == TIMER10) || (TIMERx == TIMER11) || (TIMERx == TIMER12) || (TIMERx == TIMER13)) {
- /* Configure the Counter Mode */
- tmpctlr1 &= (uint16_t)(~((uint16_t)(TIMER_CTLR1_DIR | TIMER_CTLR1_CAM)));
- tmpctlr1 |= (uint32_t)TIMER_Init->TIMER_CounterMode;
- }
-
- if ((TIMERx != TIMER5) && (TIMERx != TIMER6)) {
- /* Configure the clock division */
- tmpctlr1 &= (uint16_t)(~((uint16_t)TIMER_CTLR1_CDIV));
- tmpctlr1 |= (uint32_t)TIMER_Init->TIMER_ClockDivision;
- }
-
- TIMERx->CTLR1 = tmpctlr1;
-
- /* Configure the Autoreload value */
- TIMERx->CARL = TIMER_Init->TIMER_Period ;
-
- /* Configure the Prescaler value */
- TIMERx->PSC = TIMER_Init->TIMER_Prescaler;
-
- if ((TIMERx == TIMER0) ||
- (TIMERx == TIMER7)) {
- /* Configure the Repetition Counter value */
- TIMERx->CREP = TIMER_Init->TIMER_RepetitionCounter;
- }
-
- /* Generate an update event */
- TIMERx->EVG = TIMER_PSC_RELOAD_NOW;
-}
-
-/**
- * @brief Fill each TIMER_BaseInitPara Struct member with a default value.
- * @param TIMER_Init: pointer to a TIMER_BaseInitPara structure.
- * @retval None
- */
-void TIMER_BaseStructInit(TIMER_BaseInitPara *TIMER_Init)
-{
- /* Fill the default value */
- TIMER_Init->TIMER_Period = 0xFFFFFFFF;
- TIMER_Init->TIMER_Prescaler = 0x0000;
- TIMER_Init->TIMER_ClockDivision = TIMER_CDIV_DIV1;
- TIMER_Init->TIMER_CounterMode = TIMER_COUNTER_UP;
- TIMER_Init->TIMER_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configure the TIMER Prescaler.
- * @param TIMERx: x ={ 0-13 }
- * @param Prescaler: Prescaler value
- * @param TIMER_PSCReloadMode: Prescaler Reload mode
- * This value will be :
- * @arg TIMER_PSC_RELOAD_UPDATE : The Prescaler is loaded at the next update event.
- * @arg TIMER_PSC_RELOAD_NOW : The Prescaler is loaded right now.
- * @retval None
- */
-void TIMER_PrescalerConfig(TIMER_TypeDef *TIMERx, uint16_t Prescaler, uint16_t TIMER_PSCReloadMode)
-{
- /* Set PSC */
- TIMERx->PSC = Prescaler;
-
- /* Choose reload mode */
- TIMERx->EVG = TIMER_PSCReloadMode;
-}
-
-/**
- * @brief Configure the TIMER Counter Mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_CounterMode: the Counter Mode
- * This value will be :
- * @arg TIMER_COUNTER_UP : Up Counting Mode
- * @arg TIMER_COUNTER_DOWN : Down Counting Mode
- * @arg TIMER_COUNTER_CENTER_ALIGNED1: Center Aligned Counting Mode1
- * @arg TIMER_COUNTER_CENTER_ALIGNED2: Center Aligned Counting Mode2
- * @arg TIMER_COUNTER_CENTER_ALIGNED3: Center Aligned Counting Mode3
- * @retval None
- */
-void TIMER_CounterMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_CounterMode)
-{
- uint16_t tmpctlr1 = 0;
-
- tmpctlr1 = TIMERx->CTLR1;
-
- /* Reset the CAM and DIR Bits */
- tmpctlr1 &= (uint16_t)(~((uint16_t)(TIMER_CTLR1_DIR | TIMER_CTLR1_CAM)));
-
- /* Configures the Counter Mode */
- tmpctlr1 |= TIMER_CounterMode;
-
- /* Update the TIMER CTLR1 */
- TIMERx->CTLR1 = tmpctlr1;
-}
-
-/**
- * @brief Configure the TIMER Counter Register value
- * @param TIMERx: x ={ 0-13 } .
- * @param Counter: the Counter register new value.
- * @retval None
- */
-void TIMER_SetCounter(TIMER_TypeDef *TIMERx, uint32_t Counter)
-{
- TIMERx->CNT = Counter;
-}
-
-/**
- * @brief Configure the Autoreload value
- * @param TIMERx: x ={ 0-13 } .
- * @param AutoReloadValue:
- * @retval None
- */
-void TIMER_SetAutoreload(TIMER_TypeDef *TIMERx, uint32_t AutoReloadValue)
-{
- TIMERx->CARL = AutoReloadValue;
-}
-
-/**
- * @brief Get the Counter value.
- * @param TIMERx: x ={ 0-13 } .
- * @retval Counter Register value.
- */
-uint32_t TIMER_GetCounter(TIMER_TypeDef *TIMERx)
-{
- return TIMERx->CNT;
-}
-
-/**
- * @brief Get the Prescaler value.
- * @param TIMERx: x ={ 0-13 } .
- * @retval Prescaler Register value
- */
-uint16_t TIMER_GetPrescaler(TIMER_TypeDef *TIMERx)
-{
- return TIMERx->PSC;
-}
-
-/**
- * @brief Configure the TIMERx Update event.
- * @param TIMERx: x ={ 0-13 } .
- * @param NewValue: new value of the TIMERx UPDIS bit
- * This value will be :
- * @arg ENABLE : Update Enbale
- * @arg DISABLE : Update Disable
- * @retval None
- */
-void TIMER_UpdateDisableConfig(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- TIMERx->CTLR1 |= TIMER_CTLR1_UPDIS;
- } else {
- TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_UPDIS);
- }
-}
-
-/**
- * @brief Configure the TIMER Update Request source.
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_UpdateSrc: Configures the Update source.
- * This value will be :
- * @arg TIMER_UPDATE_SRC_GLOBAL : Update generate by setting of UPG bit or the counter
- * overflow/underflow , or the slave mode controller trigger.
- * @arg TIMER_UPDATE_SRC_REGULAR : Update generate only by counter overflow/underflow.
- * @retval None
- */
-void TIMER_UpdateRequestConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_UpdateSrc)
-{
- if (TIMER_UpdateSrc != TIMER_UPDATE_SRC_GLOBAL) {
- TIMERx->CTLR1 |= TIMER_CTLR1_UPS;
- } else {
- TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_UPS);
- }
-}
-
-/**
- * @brief Configure the CARL Preload function
- * @param TIMERx: x ={ 0-13 } .
- * @param NewValue: the state of the Preload function on CARL.
- * This value will be :
- * @arg ENABLE
- * @arg DISABLE
- * @retval None
- */
-void TIMER_CARLPreloadConfig(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Set the CARL Preload Bit */
- TIMERx->CTLR1 |= TIMER_CTLR1_ARSE;
- } else {
- /* Reset the CARL Preload Bit */
- TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_ARSE);
- }
-}
-
-/**
- * @brief Select the TIMER Single Pulse Mode.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_SPMode: specifies the SPM Mode to be used.
- * This value will be :
- * @arg TIMER_SP_MODE_SINGLE
- * @arg TIMER_SP_MODE_REPETITIVE
- * @retval None
- */
-void TIMER_SinglePulseMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SPMode)
-{
- /* Reset the SPM Bit */
- TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_SPM);
-
- /* Set the SPM Bit */
- TIMERx->CTLR1 |= TIMER_SPMode;
-}
-
-/**
- * @brief Configure the TIMERx Clock Division value.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_CDIV: the clock division value.
- * This value will be :
- * @arg TIMER_CDIV_DIV1: TDTS = Tck_tim
- * @arg TIMER_CDIV_DIV2: TDTS = 2*Tck_tim
- * @arg TIMER_CDIV_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIMER_SetClockDivision(TIMER_TypeDef *TIMERx, uint16_t TIMER_CDIV)
-{
- /* Reset the CDIV value*/
- TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_CDIV);
-
- /* Set the CDIV value */
- TIMERx->CTLR1 |= TIMER_CDIV;
-}
-
-/**
- * @brief ENABLE or DISABLE the TIMER.
- * @param TIMERx: x ={ 0-13 } .
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void TIMER_Enable(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the TIMER */
- TIMERx->CTLR1 |= TIMER_CTLR1_CNTE;
- } else {
- /* Disable the TIMER */
- TIMERx->CTLR1 &= (uint16_t)(~((uint16_t)TIMER_CTLR1_CNTE));
- }
-}
-
-/**
- * @brief Configure the: Break feature, dead time, Lock level, ROS/IOS State and the OAE
- * @param TIMERx: x ={ 1 , 8 } .
- * @param TIMER_BKDTInit: pointer to a TIMER_BKDTInitPara structure that
- * contains the BKDT Register configuration information for the TIMER.
- * @retval None
- */
-void TIMER_BKDTConfig(TIMER_TypeDef *TIMERx, TIMER_BKDTInitPara *TIMER_BKDTInit)
-{
- TIMERx->BKDT = (uint32_t)TIMER_BKDTInit->TIMER_ROSState |
- TIMER_BKDTInit->TIMER_IOSState |
- TIMER_BKDTInit->TIMER_LOCKLevel |
- TIMER_BKDTInit->TIMER_DeadTime |
- TIMER_BKDTInit->TIMER_Break |
- TIMER_BKDTInit->TIMER_BreakPolarity |
- TIMER_BKDTInit->TIMER_OutAuto;
-}
-
-/**
- * @brief Fill TIMER_BKDTInit structure member with default value.
- * @param TIMER_BKDTInit : pointer to a TIMER_BKDTInitPara structure which will be initialized.
- * @retval None
- */
-void TIMER_BKDTStructInit(TIMER_BKDTInitPara *TIMER_BKDTInit)
-{
- TIMER_BKDTInit->TIMER_ROSState = TIMER_ROS_STATE_DISABLE;
- TIMER_BKDTInit->TIMER_IOSState = TIMER_IOS_STATE_DISABLE;
- TIMER_BKDTInit->TIMER_LOCKLevel = TIMER_LOCK_LEVEL_OFF;
- TIMER_BKDTInit->TIMER_DeadTime = 0x00;
- TIMER_BKDTInit->TIMER_Break = TIMER_BREAK_DISABLE;
- TIMER_BKDTInit->TIMER_BreakPolarity = TIMER_BREAK_POLARITY_LOW;
- TIMER_BKDTInit->TIMER_OutAuto = TIMER_OUTAUTO_DISABLE;
-}
-
-/**
- * @brief Enable or disable the TIMER ALL Outputs.
- * @param TIMERx: x ={ 1 , 8 } .
- * @param NewValue: ENABLE or DISABLE .
- * @retval None
- */
-void TIMER_CtrlPWMOutputs(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the TIMER ALL Output */
- TIMERx->BKDT |= TIMER_BKDT_POE;
- } else {
- /* Disable the TIMER ALL Output */
- TIMERx->BKDT &= (uint16_t)(~((uint16_t)TIMER_BKDT_POE));
- }
-}
-
-/**
- * @brief Initialize the TIMERx Channel1 with TIMER_OCInitPara .
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure .
- * @retval None
- */
-void TIMER_OC1_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
-{
- uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0;
-
- /* Disable the Channel 1: Reset the CH1E Bit */
- TIMERx->CHE &= (uint16_t)(~(uint16_t)TIMER_CHE_CH1E);
-
- /* Get the TIMERx CHE register value */
- tmpche = TIMERx->CHE;
-
- /* Get the TIMERx CTLR2 register value */
- tmpctlr2 = TIMERx->CTLR2;
-
- /* Get the TIMERx CHCTLR1 register value */
- tmpchctlrx = TIMERx->CHCTLR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH1OM));
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH1M));
-
- /* Select the Output Compare Mode */
- tmpchctlrx |= TIMER_OCInit->TIMER_OCMode;
-
- /* Reset the Output Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1P));
-
- /* Set the Output Compare Polarity */
- tmpche |= TIMER_OCInit->TIMER_OCPolarity;
-
- /* Set the Output State */
- tmpche |= TIMER_OCInit->TIMER_OutputState;
-
- if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
- /* Reset the Output complementary Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1NP));
-
- /* Set the Output complementary Polarity */
- tmpche |= TIMER_OCInit->TIMER_OCNPolarity;
-
- /* Reset the Output complementary State */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1NE));
-
- /* Set the Output complementary State */
- tmpche |= TIMER_OCInit->TIMER_OutputNState;
-
- /* Reset the Ouput Compare and Output Compare complementary IDLE State */
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO1));
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO1N));
-
- /* Set the Output Idle state */
- tmpctlr2 |= TIMER_OCInit->TIMER_OCIdleState;
-
- /* Set the Output complementary Idle state */
- tmpctlr2 |= TIMER_OCInit->TIMER_OCNIdleState;
- }
-
- /* Write to TIMERx CTLR2 */
- TIMERx->CTLR2 = tmpctlr2;
-
- /* Write to TIMERx CHCTLR1 */
- TIMERx->CHCTLR1 = tmpchctlrx;
-
- /* Set the Capture / Compare Register value */
- TIMERx->CHCC1 = TIMER_OCInit->TIMER_Pulse;
-
- /* Write to TIMERx CHE */
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Initialize the TIMERx Channel2 with TIMER_OCInitPara .
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure .
- * @retval None
- */
-void TIMER_OC2_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
-{
- uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0;
-
- /* Disable the Channel 2: Reset the CH2E Bit */
- TIMERx->CHE &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2E));
-
- /* Get the TIMERx CHE register value */
- tmpche = TIMERx->CHE;
-
- /* Get the TIMERx CTLR2 register value */
- tmpctlr2 = TIMERx->CTLR2;
-
- /* Get the TIMERx CHCTLR1 register value */
- tmpchctlrx = TIMERx->CHCTLR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH2OM));
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH2M));
-
- /* Select the Output Compare Mode */
- tmpchctlrx |= (uint16_t)(TIMER_OCInit->TIMER_OCMode << 8);
-
- /* Reset the Output Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2P));
-
- /* Set the Output Compare Polarity */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCPolarity << 4);
-
- /* Set the Output State */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 4);
-
- if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
- /* Reset the Output complementary Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2NP));
-
- /* Set the Output complementary Polarity */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCNPolarity << 4);
-
- /* Reset the Output complementary State */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2NE));
-
- /* Set the Output complementary State */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputNState << 4);
-
- /* Reset the Ouput Compare and Output Compare complementary IDLE State */
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO2));
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO2N));
-
- /* Set the Output Idle state */
- tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCIdleState << 2);
-
- /* Set the Output complementary Idle state */
- tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCNIdleState << 2);
- }
-
- /* Write to TIMERx CTLR2 */
- TIMERx->CTLR2 = tmpctlr2;
-
- /* Write to TIMERx CHCTLR1 */
- TIMERx->CHCTLR1 = tmpchctlrx;
-
- /* Set the Capture / Compare Register value */
- TIMERx->CHCC2 = TIMER_OCInit->TIMER_Pulse;
-
- /* Write to TIMERx CHE */
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Initialize the TIMERx Channel3 with TIMER_OCInitPara .
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8} .
- * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure .
- * @retval None
- */
-void TIMER_OC3_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
-{
- uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0;
-
- /* Disable the Channel 3: Reset the CH3E Bit */
- TIMERx->CHE &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3E));
-
- /* Get the TIMERx CHE register value */
- tmpche = TIMERx->CHE;
-
- /* Get the TIMERx CTLR2 register value */
- tmpctlr2 = TIMERx->CTLR2;
-
- /* Get the TIMERx CHCTLR2 register value */
- tmpchctlrx = TIMERx->CHCTLR2;
-
- /* Reset the Output Compare Mode Bits */
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH3OM));
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH3M));
-
- /* Select the Output Compare Mode */
- tmpchctlrx |= TIMER_OCInit->TIMER_OCMode;
-
- /* Reset the Output Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3P));
-
- /* Set the Output Compare Polarity */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCPolarity << 8);
-
- /* Set the Output State */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 8);
-
- if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
- /* Reset the Output complementary Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3NP));
-
- /* Set the Output complementary Polarity */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCNPolarity << 8);
-
- /* Reset the Output complementary State */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3NE));
-
- /* Set the Output complementary State */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputNState << 8);
-
- /* Reset the Ouput Compare and Output Compare complementary IDLE State */
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO3));
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO3N));
-
- /* Set the Output Idle state */
- tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCIdleState << 4);
-
- /* Set the Output complementary Idle state */
- tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCNIdleState << 4);
- }
- /* Write to TIMERx CTLR2 */
- TIMERx->CTLR2 = tmpctlr2;
-
- /* Write to TIMERx CHCTLR2 */
- TIMERx->CHCTLR2 = tmpchctlrx;
-
- /* Set the Capture / Compare Register value */
- TIMERx->CHCC3 = TIMER_OCInit->TIMER_Pulse;
-
- /* Write to TIMERx CHE */
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Initialize the TIMERx Channel4 with TIMER_OCInitPara .
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8} .
- * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure .
- * @retval None
- */
-void TIMER_OC4_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit)
-{
- uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0;
-
- /* Disable the Channel 4: Reset the CH4E Bit */
- TIMERx->CHE &= (uint16_t)(~((uint16_t)TIMER_CHE_CH4E));
-
- /* Get the TIMERx CHE register value */
- tmpche = TIMERx->CHE;
-
- /* Get the TIMERx CTLR2 register value */
- tmpctlr2 = TIMERx->CTLR2;
-
- /* Get the TIMERx CHCTLR2 register value */
- tmpchctlrx = TIMERx->CHCTLR2;
-
- /* Reset the Output Compare Mode Bits */
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH4OM));
- tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH4M));
-
- /* Select the Output Compare Mode */
- tmpchctlrx |= (uint16_t)(TIMER_OCInit->TIMER_OCMode << 8);
-
- /* Reset the Output Polarity */
- tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH4P));
-
- /* Set the Output Compare Polarity */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCPolarity << 12);
-
- /* Set the Output State */
- tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 12);
-
- if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) {
- /* Reset the Ouput Compare IDLE State */
- tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO4));
-
- /* Set the Output Idle state */
- tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCIdleState << 6);
- }
-
- /* Write to TIMERx CTLR2 */
- TIMERx->CTLR2 = tmpctlr2;
-
- /* Write to TIMERx CHCTLR2 */
- TIMERx->CHCTLR2 = tmpchctlrx;
-
- /* Set the Capture Compare Register value */
- TIMERx->CHCC4 = TIMER_OCInit->TIMER_Pulse;
-
- /* Write to TIMERx CHE */
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Fill TIMER_OCInitPara member with default value.
- * @param TIMER_OCInit: pointer to a TIMER_OCInitPara structure.
- * @retval None
- */
-void TIMER_OCStructInit(TIMER_OCInitPara *TIMER_OCInit)
-{
- TIMER_OCInit->TIMER_OCMode = TIMER_OC_MODE_TIMING;
- TIMER_OCInit->TIMER_OutputState = TIMER_OUTPUT_STATE_DISABLE;
- TIMER_OCInit->TIMER_OutputNState = TIMER_OUTPUTN_STATE_DISABLE;
- TIMER_OCInit->TIMER_Pulse = 0x0000000;
- TIMER_OCInit->TIMER_OCPolarity = TIMER_OC_POLARITY_HIGH;
- TIMER_OCInit->TIMER_OCNPolarity = TIMER_OC_POLARITY_HIGH;
- TIMER_OCInit->TIMER_OCIdleState = TIMER_OC_IDLE_STATE_RESET;
- TIMER_OCInit->TIMER_OCNIdleState = TIMER_OCN_IDLE_STATE_RESET;
-}
-
-/**
- * @brief Configure the TIMER Output Compare Mode.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_Ch:
- * This value will be :
- * @arg TIMER_CH_1
- * @arg TIMER_CH_2
- * @arg TIMER_CH_3
- * @arg TIMER_CH_4
- * @param TIMER_OCMode: the TIMER Output Compare Mode.
- * This value will be :
- * @arg TIMER_OC_MODE_TIMING
- * @arg TIMER_OC_MODE_ACTIVE
- * @arg TIMER_OC_MODE_TOGGLE
- * @arg TIMER_OC_MODE_PWM1
- * @arg TIMER_OC_MODE_PWM2
- * @arg TIMER_FORCED_HIGH
- * @arg TIMER_FORCED_LOW
- * @retval None
- */
-void TIMER_OCxModeConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- tmp = (uint32_t) TIMERx;
- tmp += CHCTLR_OFFSET;
-
- tmp1 = CHE_CHE_SET << (uint16_t)TIMER_Ch;
-
- /* Disable the Channel: Reset the CHxE Bit */
- TIMERx->CHE &= (uint16_t) ~tmp1;
-
- if ((TIMER_Ch == TIMER_CH_1) || (TIMER_Ch == TIMER_CH_3)) {
- tmp += (TIMER_Ch >> 1);
-
- /* Reset the CHxOM bits in the CHCTLRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIMER_CHCTLR1_CH1OM);
-
- /* Configure the CHxOM bits in the CHCTLRx register */
- *(__IO uint32_t *) tmp |= TIMER_OCMode;
- } else {
- tmp += (uint16_t)(TIMER_Ch - (uint16_t)4) >> (uint16_t)1;
-
- /* Reset the CHxOM bits in the CHCTLRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIMER_CHCTLR1_CH2OM);
-
- /* Configure the CHxOM bits in the CHCTLRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIMER_OCMode << 8);
- }
-}
-
-/**
- * @brief Configure the TIMERx Capture or Compare Register value
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param CompValue1: the Capture / Compare1 register new value
- * @retval None
- */
-void TIMER_Compare1Config(TIMER_TypeDef *TIMERx, uint32_t CompValue1)
-{
- TIMERx->CHCC1 = CompValue1 ;
-}
-
-/**
- * @brief Configure the TIMERx Capture or Compare Register value
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param CompValue2: the Capture / Compare1 register new value
- * @retval None
- */
-void TIMER_Compare2Config(TIMER_TypeDef *TIMERx, uint32_t CompValue2)
-{
- TIMERx->CHCC2 = CompValue2;
-}
-
-/**
- * @brief Configure the TIMERx Capture or Compare Register value
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param CompValue3: the Capture / Compare1 register new value
- * @retval None
- */
-void TIMER_Compare3Config(TIMER_TypeDef *TIMERx, uint32_t CompValue3)
-{
- TIMERx->CHCC3 = CompValue3;
-}
-
-/**
- * @brief Configure the TIMERx Capture or Compare Register value
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param CompValue4: the Capture / Compare1 register new value
- * @retval None
- */
-void TIMER_Compare4Config(TIMER_TypeDef *TIMERx, uint32_t CompValue4)
-{
- TIMERx->CHCC4 = CompValue4;
-}
-
-/**
- * @brief Force the TIMERx output level to high or low
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_Forced: forced the output level.
- * This value will be :
- * @arg TIMER_FORCED_HIGH: Force output high level
- * @arg TIMER_FORCED_LOW : Force output low level
- * @retval None
- */
-void TIMER_Forced_OC1(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH1OM Bits */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OM);
-
- /* Configure The Forced output Mode */
- tmpchctlr1 |= TIMER_Forced ;
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief Force the TIMERx output level to high or low
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_Forced: forced the output level.
- * This value will be :
- * @arg TIMER_FORCED_HIGH: Force output high level
- * @arg TIMER_FORCED_LOW : Force output low level
- * @retval None
- */
-void TIMER_Forced_OC2(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH2OM Bits */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OM);
-
- /* Configure The Forced output Mode */
- tmpchctlr1 |= (uint16_t)(TIMER_Forced << 8);
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief Force the TIMERx output level to high or low
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_Forced: forced the output level.
- * This value will be :
- * @arg TIMER_FORCED_HIGH: Force output high level
- * @arg TIMER_FORCED_LOW : Force output low level
- * @retval None
- */
-void TIMER_Forced_OC3(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH3OM Bits */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OM);
-
- /* Configure The Forced output Mode */
- tmpchctlr2 |= TIMER_Forced ;
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief Force the TIMERx output level to high or low
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_Forced: forced the output level.
- * This value will be :
- * @arg TIMER_FORCED_HIGH: Force output high level
- * @arg TIMER_FORCED_LOW : Force output low level
- * @retval None
- */
-void TIMER_Forced_OC4(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH4OM Bits */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OM);
-
- /* Configure The Forced output Mode */
- tmpchctlr2 |= (uint16_t)(TIMER_Forced << 8);
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief Configure the TIMER Capture or Compare Preload Control bit
- * @param TIMERx: x ={ 1 , 8 } .
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void TIMER_CC_PreloadControl(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Set the CCSE Bit */
- TIMERx->CTLR2 |= TIMER_CTLR2_CCSE;
- } else {
- /* Reset the CCSE Bit */
- TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_CCSE);
- }
-}
-
-/**
- * @brief Configure the TIMER channel 1 Capture or Compare Preload register
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_OCPreload : state of the TIMERx Preload register
- * This value will be :
- * @arg TIMER_OC_PRELOAD_ENABLE
- * @arg TIMER_OC_PRELOAD_DISABLE
- * @retval None
- */
-void TIMER_OC1_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH1OSE Bit */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OSE);
-
- /* Enable or Disable the Output Compare Preload */
- tmpchctlr1 |= TIMER_OCPreload;
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief Configure the TIMER channel 2 Capture or Compare Preload register
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_OCPreload : state of the TIMERx Preload register
- * This value will be :
- * @arg TIMER_OC_PRELOAD_ENABLE
- * @arg TIMER_OC_PRELOAD_DISABLE
- * @retval None
- */
-void TIMER_OC2_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH2OSE Bit */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OSE);
-
- /* Enable or Disable the Output Compare Preload */
- tmpchctlr1 |= (uint16_t)(TIMER_OCPreload << 8);
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief Configure the TIMER channel 3 Capture or Compare Preload register
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCPreload : state of the TIMERx Preload register
- * This value will be :
- * @arg TIMER_OC_PRELOAD_ENABLE
- * @arg TIMER_OC_PRELOAD_DISABLE
- * @retval None
- */
-void TIMER_OC3_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH3OSE Bit */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OSE);
-
- /* Enable or Disable the Output Compare Preload */
- tmpchctlr2 |= TIMER_OCPreload;
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief Configure the TIMER channel 4 Capture or Compare Preload register
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCPreload : state of the TIMERx Preload register
- * This value will be :
- * @arg TIMER_OC_PRELOAD_ENABLE
- * @arg TIMER_OC_PRELOAD_DISABLE
- * @retval None
- */
-void TIMER_OC4_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH4OSE Bit */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OSE);
-
- /* Enable or Disable the Output Compare Preload */
- tmpchctlr2 |= (uint16_t)(TIMER_OCPreload << 8);
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief Configure the TIMER channel 1 Compare output Fast mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit.
- * This value will be :
- * @arg TIMER_OC_FAST_ENABLE : output fast enable
- * @arg TIMER_OC_FAST_DISABLE: output fast disable
- * @retval None
- */
-void TIMER_OC1_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH1OFE Bit */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OFE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpchctlr1 |= TIMER_OCFast;
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief Configure the TIMER channel 2 Compare output Fast mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit.
- * This value will be :
- * @arg TIMER_OC_FAST_ENABLE : output fast enable
- * @arg TIMER_OC_FAST_DISABLE: output fast disable
- * @retval None
- */
-void TIMER_OC2_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH2OFE Bit */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OFE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpchctlr1 |= (uint16_t)(TIMER_OCFast << 8);
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief Configure the TIMER channel 3 Compare output Fast mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit.
- * This value will be :
- * @arg TIMER_OC_FAST_ENABLE : output fast enable
- * @arg TIMER_OC_FAST_DISABLE: output fast disable
- * @retval None
- */
-void TIMER_OC3_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH3OFE Bit */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OFE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpchctlr2 |= TIMER_OCFast;
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief Configure the TIMER channel 4 Compare output Fast mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit.
- * This value will be :
- * @arg TIMER_OC_FAST_ENABLE : output fast enable
- * @arg TIMER_OC_FAST_DISABLE: output fast disable
- * @retval None
- */
-void TIMER_OC4_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH4OFE Bit */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OFE);
-
- /* Enable or Disable the Output Compare Fast Bit */
- tmpchctlr2 |= (uint16_t)(TIMER_OCFast << 8);
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief If Clear the OCREF signal on an external event
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_OCClear: new state of the Output Compare Clear Enable Bit.
- * This value will be :
- * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable
- * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable
- * @retval None
- */
-void TIMER_OC1_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the CH1OCE Bit */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OCE);
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpchctlr1 |= TIMER_OCClear;
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief If Clear the OCREF signal on an external event
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_OCClear: new state the Output Compare Clear Enable Bit.
- * This value will be :
- * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable
- * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable
- * @retval None
- */
-void TIMER_OC2_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear)
-{
- uint16_t tmpchctlr1 = 0;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- /* Reset the OC2CE Bit */
- tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OCE);
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpchctlr1 |= (uint16_t)(TIMER_OCClear << 8);
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-}
-
-/**
- * @brief If Clear the OCREF signal on an external event
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCClear: new state the Output Compare Clear Enable Bit.
- * This value will be :
- * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable
- * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable
- * @retval None
- */
-void TIMER_OC3_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the CH3OCE Bit */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OCE);
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpchctlr2 |= TIMER_OCClear;
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief If Clear the OCREF signal on an external event
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCClear: new state the Output Compare Clear Enable Bit.
- * This value will be :
- * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable
- * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable
- * @retval None
- */
-void TIMER_OC4_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear)
-{
- uint16_t tmpchctlr2 = 0;
-
- tmpchctlr2 = TIMERx->CHCTLR2;
-
- /* Reset the OC4CE Bit */
- tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OCE);
-
- /* Enable or Disable the Output Compare Clear Bit */
- tmpchctlr2 |= (uint16_t)(TIMER_OCClear << 8);
-
- TIMERx->CHCTLR2 = tmpchctlr2;
-}
-
-/**
- * @brief Configure the TIMERx channel 1 polarity.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_OCPolarity :
- * This value will be :
- * @arg TIMER_OC_POLARITY_HIGH: active high
- * @arg TIMER_OC_POLARITY_LOW : active low
- * @retval None
- */
-void TIMER_OC1_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configures the CH1P Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH1P);
- tmpche |= TIMER_OCPolarity;
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TIMERx Channel 1 complementary polarity.
- * @param TIMERx: x ={ 1 , 8 } .
- * @param TIMER_OCNPolarity:
- * This value will be :
- * @arg TIMER_OCN_POLARITY_HIGH: active high
- * @arg TIMER_OCN_POLARITY_LOW: active low
- * @retval None
- */
-void TIMER_OC1N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configures the CH1NP Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH1NP);
- tmpche |= TIMER_OCNPolarity;
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TIMERx channel 2 polarity.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_OCPolarity :
- * This value will be :
- * @arg TIMER_OC_POLARITY_HIGH: active high
- * @arg TIMER_OC_POLARITY_LOW : active low
- * @retval None
- */
-void TIMER_OC2_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configure the CH2P Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH2P);
- tmpche |= (uint16_t)(TIMER_OCPolarity << 4);
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TIMERx Channel 2 complementary polarity.
- * @param TIMERx: x ={ 1 , 8 } .
- * @param TIMER_OCNPolarity:
- * This value will be :
- * @arg TIMER_OCN_POLARITY_HIGH: active high
- * @arg TIMER_OCN_POLARITY_LOW: active low
- * @retval None
- */
-void TIMER_OC2N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configure the CH2NP Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH2NP);
- tmpche |= (uint16_t)(TIMER_OCNPolarity << 4);
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TIMERx channel 3 polarity.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCPolarity :
- * This value will be :
- * @arg TIMER_OC_POLARITY_HIGH: active high
- * @arg TIMER_OC_POLARITY_LOW : active low
- * @retval None
- */
-void TIMER_OC3_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configure the CH3P Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH3P);
- tmpche |= (uint16_t)(TIMER_OCPolarity << 8);
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TIMERx Channel 3 complementary polarity.
- * @param TIMERx: x ={ 1 , 8 } .
- * @param TIMER_OCNPolarity:
- * This value will be :
- * @arg TIMER_OCN_POLARITY_HIGH: active high
- * @arg TIMER_OCN_POLARITY_LOW : active low
- * @retval None
- */
-void TIMER_OC3N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configure the CH3NP Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH3NP);
- tmpche |= (uint16_t)(TIMER_OCNPolarity << 8);
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TIMERx channel 4 polarity.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_OCPolarity :
- * This value will be :
- * @arg TIMER_OC_POLARITY_HIGH: active high
- * @arg TIMER_OC_POLARITY_LOW : active low
- * @retval None
- */
-void TIMER_OC4_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity)
-{
- uint16_t tmpche = 0;
-
- tmpche = TIMERx->CHE;
-
- /* Configure the CH4P Bit */
- tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH4P);
- tmpche |= (uint16_t)(TIMER_OCPolarity << 12);
-
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Turn-on or off the Channel x Capture or Compare .
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_Ch:
- * This value will be :
- * @arg TIMER_CH_1:
- * @arg TIMER_CH_2:
- * @arg TIMER_CH_3:
- * @arg TIMER_CH_4:
- * @param TIMER_CCx: the TIMER Channel CCxE bit new value.
- * This value will be:
- * @arg TIMER_CCX_ENABLE
- * @arg TIMER_CCX_DISABLE
- * @retval None
- */
-void TIMER_CCxCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCx)
-{
- uint16_t tmp = 0;
-
- tmp = CHE_CHE_SET << TIMER_Ch;
-
- /* Reset the CCx Bit */
- TIMERx->CHE &= (uint16_t)~ tmp;
-
- /* Configure the CCx Bit */
- TIMERx->CHE |= (uint16_t)(TIMER_CCx << TIMER_Ch);
-}
-
-/**
- * @brief Turn-on or off the Channel x complementary Capture or Compare
- * @param TIMERx: x ={ 1 , 8 } .
- * @param TIMER_Ch:
- * This value will be :
- * @arg TIMER_CH_1:
- * @arg TIMER_CH_2:
- * @arg TIMER_CH_3:
- * @param TIMER_CCxN: the Channel CCxN bit new value.
- * This value will be:
- * @arg TIMER_CCXN_ENABLE
- * @arg TIMER_CCXN_DISABLE
- * @retval None
- */
-void TIMER_CCxNCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCxN)
-{
- uint16_t tmp = 0;
-
- tmp = CHE_CHNE_SET << TIMER_Ch;
-
- /* Reset the CCxN Bit */
- TIMERx->CHE &= (uint16_t) ~tmp;
-
- /* Configure the CCxN Bit */
- TIMERx->CHE |= (uint16_t)(TIMER_CCxN << TIMER_Ch);
-}
-
-/**
- * @brief Select control shadow register update control.
- * @param TIMERx: x ={ 1, 8 } .
- * @param NewState: ENABLE or DISABLE.
- * @retval None
- */
-void TIMER_SelectCOM(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
-
- if (NewValue != DISABLE) {
- /* Set the CCUC Bit */
- TIMERx->CTLR2 |= TIMER_CTLR2_CCUC;
- } else {
- /* Reset the CCUC Bit */
- TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_CCUC);
- }
-}
-
-/**
- * @brief Initialize the Input Capture parameters of the timer
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_ICInit: pointer to a TIMER_ICInitPara structure
- * @retval None
- */
-void TIMER_ICInit(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit)
-{
-
- if (TIMER_ICInit->TIMER_CH == TIMER_CH_1) {
- TI1_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity,
- TIMER_ICInit->TIMER_ICSelection,
- TIMER_ICInit->TIMER_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIMER_Set_IC1_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
- } else if (TIMER_ICInit->TIMER_CH == TIMER_CH_2) {
- TI2_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity,
- TIMER_ICInit->TIMER_ICSelection,
- TIMER_ICInit->TIMER_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIMER_Set_IC2_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
- } else if (TIMER_ICInit->TIMER_CH == TIMER_CH_3) {
- TI3_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity,
- TIMER_ICInit->TIMER_ICSelection,
- TIMER_ICInit->TIMER_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIMER_Set_IC3_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
- } else {
- TI4_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity,
- TIMER_ICInit->TIMER_ICSelection,
- TIMER_ICInit->TIMER_ICFilter);
-
- /* Set the Input Capture Prescaler value */
- TIMER_Set_IC4_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
- }
-}
-
-/**
- * @brief Fill TIMER_ICInitPara member with default value.
- * @param TIMER_ICInit : pointer to a TIMER_ICInitPara structure
- * @retval None
- */
-void TIMER_ICStructInit(TIMER_ICInitPara *TIMER_ICInit)
-{
- TIMER_ICInit->TIMER_CH = TIMER_CH_1;
- TIMER_ICInit->TIMER_ICPolarity = TIMER_IC_POLARITY_RISING;
- TIMER_ICInit->TIMER_ICSelection = TIMER_IC_SELECTION_DIRECTTI;
- TIMER_ICInit->TIMER_ICPrescaler = TIMER_IC_PSC_DIV1;
- TIMER_ICInit->TIMER_ICFilter = 0x00;
-}
-
-/**
- * @brief Configure the TIMER PWM input Capture mode parameters
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_ICInit: pointer to a TIMER_ICInitPara structure
- * @retval None
- */
-void TIMER_PWMCaptureConfig(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit)
-{
- uint16_t icoppositepolarity = TIMER_IC_POLARITY_RISING;
- uint16_t icoppositeselection = TIMER_IC_SELECTION_DIRECTTI;
-
- /* Select the Opposite Input Polarity */
- if (TIMER_ICInit->TIMER_ICPolarity == TIMER_IC_POLARITY_RISING) {
- icoppositepolarity = TIMER_IC_POLARITY_FALLING;
- } else {
- icoppositepolarity = TIMER_IC_POLARITY_RISING;
- }
-
- /* Select the Opposite Input */
- if (TIMER_ICInit->TIMER_ICSelection == TIMER_IC_SELECTION_DIRECTTI) {
- icoppositeselection = TIMER_IC_SELECTION_INDIRECTTI;
- } else {
- icoppositeselection = TIMER_IC_SELECTION_DIRECTTI;
- }
-
- if (TIMER_ICInit->TIMER_CH == TIMER_CH_1) {
- TI1_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity,
- TIMER_ICInit->TIMER_ICSelection,
- TIMER_ICInit->TIMER_ICFilter);
-
- TIMER_Set_IC1_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
-
- TI2_Config(TIMERx, icoppositepolarity, icoppositeselection, TIMER_ICInit->TIMER_ICFilter);
-
- TIMER_Set_IC2_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
- } else {
- TI2_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity,
- TIMER_ICInit->TIMER_ICSelection,
- TIMER_ICInit->TIMER_ICFilter);
-
- TIMER_Set_IC2_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
-
- TI1_Config(TIMERx, icoppositepolarity, icoppositeselection, TIMER_ICInit->TIMER_ICFilter);
-
- TIMER_Set_IC1_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler);
- }
-}
-
-/**
- * @brief Read the TIMERx Input Capture value.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @retval None
- */
-uint32_t TIMER_GetCapture1(TIMER_TypeDef *TIMERx)
-{
- return TIMERx->CHCC1;
-}
-
-/**
- * @brief Read the TIMERx Input Capture value.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @retval None
- */
-uint32_t TIMER_GetCapture2(TIMER_TypeDef *TIMERx)
-{
- return TIMERx->CHCC2;
-}
-
-/**
- * @brief Read the TIMERx Input Capture value.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @retval None
- */
-uint32_t TIMER_GetCapture3(TIMER_TypeDef *TIMERx)
-{
- return TIMERx->CHCC3;
-}
-
-/**
- * @brief Read the TIMERx Input Capture value.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @retval None
- */
-uint32_t TIMER_GetCapture4(TIMER_TypeDef *TIMERx)
-{
- return TIMERx->CHCC4;
-}
-
-/**
- * @brief Configure the TIMERx Input Capture prescaler.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_ICPSC: the Input Capture1 prescaler value.
- * This value will be :
- * @arg TIMER_IC_PSC_DIV1: no prescaler
- * @arg TIMER_IC_PSC_DIV2: divided by 2
- * @arg TIMER_IC_PSC_DIV4: divided by 4
- * @arg TIMER_IC_PSC_DIV8: divided by 8
- * @retval None
- */
-void TIMER_Set_IC1_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC)
-{
- TIMERx->CHCTLR1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1ICP);
-
- TIMERx->CHCTLR1 |= TIMER_ICPSC;
-}
-
-/**
- * @brief Configure the TIMERx Input Capture prescaler.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_ICPSC: the Input Capture1 prescaler value.
- * This value will be :
- * @arg TIMER_IC_PSC_DIV1: no prescaler
- * @arg TIMER_IC_PSC_DIV2: divided by 2
- * @arg TIMER_IC_PSC_DIV4: divided by 4
- * @arg TIMER_IC_PSC_DIV8: divided by 8
- * @retval None
- */
-void TIMER_Set_IC2_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC)
-{
- TIMERx->CHCTLR1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2ICP);
-
- TIMERx->CHCTLR1 |= (uint16_t)(TIMER_ICPSC << 8);
-}
-
-/**
- * @brief Configure the TIMERx Input Capture prescaler.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ICPSC: the Input Capture1 prescaler value.
- * This value will be :
- * @arg TIMER_IC_PSC_DIV1: no prescaler
- * @arg TIMER_IC_PSC_DIV2: divided by 2
- * @arg TIMER_IC_PSC_DIV4: divided by 4
- * @arg TIMER_IC_PSC_DIV8: divided by 8
- * @retval None
- */
-void TIMER_Set_IC3_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC)
-{
- TIMERx->CHCTLR2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3ICP);
-
- TIMERx->CHCTLR2 |= TIMER_ICPSC;
-}
-
-/**
- * @brief Configure the TIMERx Input Capture prescaler.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ICPSC: the Input Capture1 prescaler value.
- * This value will be :
- * @arg TIMER_IC_PSC_DIV1: no prescaler
- * @arg TIMER_IC_PSC_DIV2: divided by 2
- * @arg TIMER_IC_PSC_DIV4: divided by 4
- * @arg TIMER_IC_PSC_DIV8: divided by 8
- * @retval None
- */
-void TIMER_Set_IC4_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC)
-{
- TIMERx->CHCTLR2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4ICP);
-
- TIMERx->CHCTLR2 |= (uint16_t)(TIMER_ICPSC << 8);
-}
-
-/**
- * @brief Configure interrupts Enables
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_INT: the interrupts sources to Configure.
- * This value will be :
- * @arg TIMER_INT_UPDATE : update Interrupt
- * @arg TIMER_INT_CH1 : Channel 1 Capture or Compare Interrupt
- * @arg TIMER_INT_CH2 : Channel 2 Capture or Compare Interrupt
- * @arg TIMER_INT_CH3 : Channel 3 Capture or Compare Interrupt
- * @arg TIMER_INT_CH4 : Channel 4 Capture or Compare Interrupt
- * @arg TIMER_INT_CCUG : Commutation Interrupt
- * @arg TIMER_INT_TRIGGER : Trigger Interrupt
- * @arg TIMER_INT_BREAK : Break Interrupt
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- TIMERx->DIE |= TIMER_INT;
- } else {
- TIMERx->DIE &= (uint16_t)~TIMER_INT;
- }
-}
-
-/**
- * @brief Generate the software event
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_EventSrc:
- * This value will be :
- * @arg TIMER_EVENT_SRC_UPDATE : update Event
- * @arg TIMER_EVENT_SRC_CH1 : Channel 1 Capture or Compare Event
- * @arg TIMER_EVENT_SRC_CH2 : Channel 2 Capture or Compare Event
- * @arg TIMER_EVENT_SRC_CH3 : Channel 3 Capture or Compare Event
- * @arg TIMER_EVENT_SRC_CH4 : Channel 4 Capture or Compare Event
- * @arg TIMER_EVENT_SRC_COM : COM event
- * @arg TIMER_EVENT_SRC_TRIGGER : Trigger Event
- * @arg TIMER_EVENT_SRC_BREAK : Break event
- * @retval None
- */
-void TIMER_GenerateEvent(TIMER_TypeDef *TIMERx, uint16_t TIMER_EventSrc)
-{
- TIMERx->EVG = TIMER_EventSrc;
-}
-
-/**
- * @brief Get current flag status
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_FLAG:
- * This value will be :
- * @arg TIMER_FLAG_UPDATE : update Flag
- * @arg TIMER_FLAG_CH1 : Channel 1 Capture or Compare Flag
- * @arg TIMER_FLAG_CH2 : Channel 2 Capture or Compare Flag
- * @arg TIMER_FLAG_CH3 : Channel 3 Capture or Compare Flag
- * @arg TIMER_FLAG_CH4 : Channel 4 Capture or Compare Flag
- * @arg TIMER_FLAG_COM : Commutation Flag
- * @arg TIMER_FLAG_TRIGGER : Trigger Flag
- * @arg TIMER_FLAG_BREAK : Break Flag
- * @arg TIMER_FLAG_CH1OF : Channel 1 Capture or Compare overcapture Flag
- * @arg TIMER_FLAG_CH2OF : Channel 2 Capture or Compare overcapture Flag
- * @arg TIMER_FLAG_CH3OF : Channel 3 Capture or Compare overcapture Flag
- * @arg TIMER_FLAG_CH4OF : Channel 4 Capture or Compare overcapture Flag
- * @retval The state of TIMER_FLAG ( SET or RESET ).
- */
-TypeState TIMER_GetBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG)
-{
- if ((TIMERx->STR & TIMER_FLAG) != (uint16_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the flags
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_FLAG: the flag bit to clear.
- * This value will be :
- * @arg TIMER_FLAG_UPDATE : update Flag
- * @arg TIMER_FLAG_CH1 : Channel 1 Capture or Compare Flag
- * @arg TIMER_FLAG_CH2 : Channel 2 Capture or Compare Flag
- * @arg TIMER_FLAG_CH3 : Channel 3 Capture or Compare Flag
- * @arg TIMER_FLAG_CH4 : Channel 4 Capture or Compare Flag
- * @arg TIMER_FLAG_COM : Commutation Flag
- * @arg TIMER_FLAG_TRIGGER : Trigger Flag
- * @arg TIMER_FLAG_BREAK : Break Flag
- * @arg TIMER_FLAG_CH1OF : Channel 1 Capture or Compare overcapture Flag
- * @arg TIMER_FLAG_CH2OF : Channel 2 Capture or Compare overcapture Flag
- * @arg TIMER_FLAG_CH3OF : Channel 3 Capture or Compare overcapture Flag
- * @arg TIMER_FLAG_CH4OF : Channel 4 Capture or Compare overcapture Flag
- * @retval None
- */
-void TIMER_ClearBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG)
-{
- TIMERx->STR = (uint16_t)~TIMER_FLAG;
-}
-
-/**
- * @brief Get interrupt state
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_INT:
- * This value will be :
- * @arg TIMER_INT_UPDATE: update Interrupt
- * @arg TIMER_INT_CH1 : Channel 1 Capture or Compare Interrupt
- * @arg TIMER_INT_CH2 : Channel 2 Capture or Compare Interrupt
- * @arg TIMER_INT_CH3 : Channel 3 Capture or Compare Interrupt
- * @arg TIMER_INT_CH4 : Channel 4 Capture or Compare Interrupt
- * @arg TIMER_INT_CCUG : Commutation Interrupt
- * @arg TIMER_INT_TRIGGER : Trigger Interrupt
- * @arg TIMER_INT_BREAK : Break Interrupt
- * @retval The new state of the TIMER_INT(SET or RESET).
- */
-TypeState TIMER_GetIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT)
-{
- uint16_t TypeState = 0x0, itenable = 0x0;
-
- TypeState = TIMERx->STR & TIMER_INT;
- itenable = TIMERx->DIE & TIMER_INT;
-
- if ((TypeState != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt pending bits
- * @param TIMERx: x ={ 0-13 } .
- * @param TIMER_INT:
- * This value will be :
- * @arg TIMER_INT_UPDATE: update Interrupt
- * @arg TIMER_INT_CH1 : Channel 1 Capture or Compare Interrupt
- * @arg TIMER_INT_CH2 : Channel 2 Capture or Compare Interrupt
- * @arg TIMER_INT_CH3 : Channel 3 Capture or Compare Interrupt
- * @arg TIMER_INT_CH4 : Channel 4 Capture or Compare Interrupt
- * @arg TIMER_INT_CCUG : Commutation Interrupt
- * @arg TIMER_INT_TRIGGER : Trigger Interrupt
- * @arg TIMER_INT_BREAK : Break Interrupt
- * @retval None
- */
-void TIMER_ClearIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT)
-{
- TIMERx->STR = (uint16_t)~TIMER_INT;
-}
-
-/**
- * @brief Configure the DMA .
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_DMABase: DMA Base address.
- * This value will be :
- * @arg TIMER_DMA_BASE_ADDR_CTLR1
- * @arg TIMER_DMA_BASE_ADDR_CTLR2
- * @arg TIMER_DMA_BASE_ADDR_SMC
- * @arg TIMER_DMA_BASE_ADDR_DIE
- * @arg TIMER_DMA_BASE_ADDR_STR
- * @arg TIMER_DMA_BASE_ADDR_EVG
- * @arg TIMER_DMA_BASE_ADDR_CHCTLR1
- * @arg TIMER_DMA_BASE_ADDR_CHCTLR2
- * @arg TIMER_DMA_BASE_ADDR_CHE
- * @arg TIMER_DMA_BASE_ADDR_CNT
- * @arg TIMER_DMA_BASE_ADDR_PSC
- * @arg TIMER_DMA_BASE_ADDR_CARL
- * @arg TIMER_DMA_BASE_ADDR_CREP
- * @arg TIMER_DMA_BASE_ADDR_CHCC1
- * @arg TIMER_DMA_BASE_ADDR_CHCC2
- * @arg TIMER_DMA_BASE_ADDR_CHCC3
- * @arg TIMER_DMA_BASE_ADDR_CHCC4
- * @arg TIMER_DMA_BASE_ADDR_BKDT
- * @arg TIMER_DMA_BASE_ADDR_DCTLR
- * @arg TIMER_DMA_BASE_ADDR_DTRSF
- * @param TIMER_DMABurstLength: DMA Burst length.
- * This value will be :
- * [ TIMER_DMA_BURST_1TRANSFER , TIMER_DMA_BURST_18TRANSFERS ]
- * @retval None
- */
-void TIMER_DMAConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMABase, uint16_t TIMER_DMABurstLength)
-{
- TIMERx->DCTLR = TIMER_DMABase | TIMER_DMABurstLength;
-}
-
-/**
- * @brief Configure the TIMERx's DMA Requests
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 } .
- * @param TIMER_DMASrc: the DMA Request sources.
- * This value will be :
- * @arg TIMER_DMA_UPDATE : update start DMA
- * @arg TIMER_DMA_CH1 : Channel 1 Capture or Compare start DMA
- * @arg TIMER_DMA_CH2 : Channel 2 Capture or Compare start DMA
- * @arg TIMER_DMA_CH3 : Channel 3 Capture or Compare start DMA
- * @arg TIMER_DMA_CH4 : Channel 4 Capture or Compare start DMA
- * @arg TIMER_DMA_COM : Commutation DMA
- * @arg TIMER_DMA_TRIGGER : Trigger DMA
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void TIMER_DMACmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMASrc, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- /* Enable the DMA */
- TIMERx->DIE |= TIMER_DMASrc;
- } else {
- /* Disable the DMA */
- TIMERx->DIE &= (uint16_t)~TIMER_DMASrc;
- }
-}
-
-/**
- * @brief Select the Capture or Compare DMA source
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param NewValue: ENABLE or DISABLE
- * @retval None
- */
-void TIMER_CC_DMA(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- TIMERx->CTLR2 |= TIMER_CTLR2_DMAS;
- } else {
- TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_DMAS);
- }
-}
-
-/**
- * @brief Configure the internal Clock
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 }
- * @retval None
- */
-void TIMER_InternalClockConfig(TIMER_TypeDef *TIMERx)
-{
- TIMERx->SMC &= (uint16_t)(~((uint16_t)TIMER_SMC_SMC));
-}
-
-/**
- * @brief Configure the Internal Trigger as External Input Clock
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_InputTriSrc:
- * This value will be :
- * @arg TIMER_TS_ITR0 : Internal Trigger 0
- * @arg TIMER_TS_ITR1 : Internal Trigger 1
- * @arg TIMER_TS_ITR2 : Internal Trigger 2
- * @arg TIMER_TS_ITR3 : Internal Trigger 3
- * @retval None
- */
-void TIMER_ITRxExtClock(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc)
-{
- /* Select the Internal Trigger */
- TIMER_SelectInputTrigger(TIMERx, TIMER_InputTriSrc);
-
- /* Select the External clock mode1 */
- TIMERx->SMC |= TIMER_SLAVE_MODE_EXTERNAL1;
-}
-
-/**
- * @brief Configure the External Trigger as External Input Clock
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_TIxExCLKSrc: Trigger source.
- * This value will be :
- * @arg TIMER_TIX_EXCLK1_SRC_TI1ED : TI1 Edge Detector
- * @arg TIMER_TIX_EXCLK1_SRC_TI1 : Filtered Timer Input 1
- * @arg TIMER_TIX_EXCLK1_SRC_TI2 : Filtered Timer Input 2
- * @param TIMER_ICPolarity:
- * This value will be :
- * @arg TIMER_IC_POLARITY_RISING
- * @arg TIMER_IC_POLARITY_FALLING
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIMER_TIxExtCLkConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_TIxExCLKSrc,
- uint16_t TIMER_ICPolarity, uint16_t ICFilter)
-{
- /* Select the Input Clock Source */
- if (TIMER_TIxExCLKSrc == TIMER_TIX_EXCLK1_SRC_TI2) {
- TI2_Config(TIMERx, TIMER_ICPolarity, TIMER_IC_SELECTION_DIRECTTI, ICFilter);
- } else {
- TI1_Config(TIMERx, TIMER_ICPolarity, TIMER_IC_SELECTION_DIRECTTI, ICFilter);
- }
-
- /* Select the Trigger source */
- TIMER_SelectInputTrigger(TIMERx, TIMER_TIxExCLKSrc);
-
- /* Enter the External clock mode1 */
- TIMERx->SMC |= TIMER_SLAVE_MODE_EXTERNAL1;
-}
-
-/**
- * @brief Configure the External clock Mode1
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ExtTriPrescaler: The external Trigger Prescaler.
- * This value will be :
- * @arg TIMER_EXT_TRI_PSC_OFF: no divided.
- * @arg TIMER_EXT_TRI_PSC_DIV2: divided by 2.
- * @arg TIMER_EXT_TRI_PSC_DIV4: divided by 4.
- * @arg TIMER_EXT_TRI_PSC_DIV8: divided by 8.
- * @param TIMER_ExtTriPolarity: Trigger Polarity.
- * This value will be :
- * @arg TIMER_EXT_TRI_POLARITY_INVERTED : active low or falling edge active.
- * @arg TIMER_EXT_TRI_POLARITY_NONINVERTED: active high or rising edge active.
- * @param ExtTriFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIMER_ETRClockMode1Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity,
- uint16_t ExtTriFilter)
-{
- uint16_t tmpsmc = 0;
-
- /* Configure the external Trigger Clock source */
- TIMER_ETRConfig(TIMERx, TIMER_ExTriPrescaler, TIMER_ExTriPolarity, ExtTriFilter);
-
- /* Get the TIMERx SMC register value */
- tmpsmc = TIMERx->SMC;
-
- tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_SMC));
-
- /* Select the External clock mode1 */
- tmpsmc |= TIMER_SLAVE_MODE_EXTERNAL1;
-
- /* Select the Trigger selection : ETRF */
- tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_TRGS));
- tmpsmc |= TIMER_TS_ETRF;
-
- TIMERx->SMC = tmpsmc;
-}
-
-/**
- * @brief Configure the External clock Mode2
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ExtTriPrescaler: The external Trigger Prescaler.
- * This value will be :
- * @arg TIMER_EXT_TRI_PSC_OFF: no divided.
- * @arg TIMER_EXT_TRI_PSC_DIV2: divided by 2.
- * @arg TIMER_EXT_TRI_PSC_DIV4: divided by 4.
- * @arg TIMER_EXT_TRI_PSC_DIV8: divided by 8.
- * @param TIMER_ExtTriPolarity: Trigger Polarity.
- * This value will be :
- * @arg TIMER_EXT_TRI_POLARITY_INVERTED : active low or falling edge active.
- * @arg TIMER_EXT_TRI_POLARITY_NONINVERTED: active high or rising edge active.
- * @param ExtTriFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIMER_ETRClockMode2Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler,
- uint16_t TIMER_ExTriPolarity, uint16_t ExtTriFilter)
-{
- /* Configure the ETR Clock source */
- TIMER_ETRConfig(TIMERx, TIMER_ExTriPrescaler, TIMER_ExTriPolarity, ExtTriFilter);
-
- /* Select the External clock mode2 */
- TIMERx->SMC |= TIMER_SMC_ECM2E;
-}
-
-/**
- * @brief Select the Input Trigger source
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_InputTriSrc: The Input Trigger source.
- * This value will be :
- * @arg TIMER_TS_ITR0 : Internal Trigger 0
- * @arg TIMER_TS_ITR1 : Internal Trigger 1
- * @arg TIMER_TS_ITR2 : Internal Trigger 2
- * @arg TIMER_TS_ITR3 : Internal Trigger 3
- * @arg TIMER_TS_TI1F_ED : TI1 Edge Detector
- * @arg TIMER_TS_TI1FP1 : Filtered Timer Input 1
- * @arg TIMER_TS_TI2FP2 : Filtered Timer Input 2
- * @arg TIMER_TS_ETRF : External Trigger input
- * @retval None
- */
-void TIMER_SelectInputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc)
-{
- uint16_t tmpsmc = 0;
-
- tmpsmc = TIMERx->SMC;
-
- /* Reset the TS Bits */
- tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_TRGS));
-
- /* Set the Input Trigger source */
- tmpsmc |= TIMER_InputTriSrc ;
-
- TIMERx->SMC = tmpsmc;
-}
-
-/**
- * @brief Configure the TIMERx Trigger Output Mode.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 ,10 , 11 , 13 , 14} .
- * @param TIMER_TriOutSrc:
- * This value will be :
- * @arg TIMER_TRI_OUT_SRC_RESET : The UPG bit in the TIMERx_EVG register as TriO.
- * @arg TIMER_TRI_OUT_SRC_ENABLE : The CEN bit in TIMERx_CTLR1 as TriO.
- * @arg TIMER_TRI_OUT_SRC_UPDATE : Update event as TriO.
- * @arg TIMER_TRI_OUT_SRC_OC1 : capture or compare match ( CC1IF bit set ) as TriO.
- * @arg TIMER_TRI_OUT_SRC_OC1REF : OC1REF as TriO.
- * @arg TIMER_TRI_OUT_SRC_OC2REF : OC2REF as TriO.
- * @arg TIMER_TRI_OUT_SRC_OC3REF : OC3REF as TriO.
- * @arg TIMER_TRI_OUT_SRC_OC4REF : OC4REF as TriO.
- * @retval None
- */
-void TIMER_SelectOutputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_TriOutSrc)
-{
- /* Reset the MMC Bits */
- TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_MMC);
-
- /* Configures the TriO source */
- TIMERx->CTLR2 |= TIMER_TriOutSrc;
-}
-
-/**
- * @brief Configure the TIMERx Slave Mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_SlaveMode:
- * This value will be :
- * @arg TIMER_SLAVE_MODE_RESET : The trigger signal reset the timer
- * @arg TIMER_SLAVE_MODE_GATED : The trigger signal enable the counter when high.
- * @arg TIMER_SLAVE_MODE_TRIGGER : The trigger signal starts the counter.
- * @arg TIMER_SLAVE_MODE_EXTERNAL1 : The trigger signal as a counter clock.
- * @retval None
- */
-void TIMER_SelectSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SlaveMode)
-{
- /* Reset the SMC Bits */
- TIMERx->SMC &= (uint16_t)~((uint16_t)TIMER_SMC_SMC);
-
- /* Configure the Slave Mode */
- TIMERx->SMC |= TIMER_SlaveMode;
-}
-
-/**
- * @brief Configure the TIMERx Master or Slave Mode
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 10 , 11 , 13 , 14} .
- * @param TIMER_MasterSlaveMode:
- * This value will be :
- * @arg TIMER_MASTER_SLAVE_MODE_ENABLE : synchronize master and slave by TriO
- * @arg TIMER_MASTER_SLAVE_MODE_DISABLE : Don't synchronize
- * @retval None
- */
-void TIMER_SelectMasterSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_MasterSlaveMode)
-{
- /* Reset the MSM Bit */
- TIMERx->SMC &= (uint16_t)~((uint16_t)TIMER_SMC_MSM);
-
- /* Configure the MSM Bit */
- TIMERx->SMC |= TIMER_MasterSlaveMode;
-}
-
-/**
- * @brief Configure the External Trigger (ETR)
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ExTriPrescaler: external Trigger Prescaler.
- * This value will be :
- * @arg TIMER_EXT_TRI_PSC_OFF : no divided.
- * @arg TIMER_EXT_TRI_PSC_DIV2: divided by 2.
- * @arg TIMER_EXT_TRI_PSC_DIV4: divided by 4.
- * @arg TIMER_EXT_TRI_PSC_DIV8: divided by 8.
- * @param TIMER_ExtTriPolarity: Trigger Polarity.
- * This value will be :
- * @arg TIMER_EXT_TRI_POLARITY_INVERTED : active low or falling edge active.
- * @arg TIMER_EXT_TRI_POLARITY_NONINVERTED: active high or rising edge active.
- * @param ExtTRGFilter: The External Trigger signal Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIMER_ETRConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity,
- uint16_t ExtTriFilter)
-{
- uint16_t tmpsmc = 0;
-
- tmpsmc = TIMERx->SMC;
-
- /*Reset the ETR Bits */
- tmpsmc &= SMC_ETR_MASK;
-
- /* Configure the Prescaler, the Filter value and the Polarity */
- tmpsmc |= (uint16_t)(TIMER_ExTriPrescaler | (uint16_t)(TIMER_ExTriPolarity | (uint16_t)(ExtTriFilter << (uint16_t)8)));
-
- TIMERx->SMC = tmpsmc;
-}
-
-/**
- * @brief Configure the Encoder Interface.
- * @param TIMERx: x ={ 1 , 8 , 9 , 12 } .
- * @param TIMER_EncoderMode:
- * This value will be :
- * @arg TIMER_ENCODER_MODE_TI1 : Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIMER_ENCODER_MODE_TI2 : Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIMER_ENCODER_MODE_TI12 : Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIMER_IC1Polarity: input capture 1 Polarity
- * This value will be :
- * @arg TIMER_IC_POLARITY_FALLING : capture Falling edge.
- * @arg TIMER_IC_POLARITY_RISING : capture Rising edge.
- * @param TIMER_IC2Polarity: input capture 2 Polarity
- * This value will be :
- * @arg TIMER_IC_POLARITY_FALLING : capture Falling edge.
- * @arg TIMER_IC_POLARITY_RISING : capture Rising edge.
- * @retval None
- */
-void TIMER_EncoderInterfaceConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_EncoderMode,
- uint16_t TIMER_IC1Polarity, uint16_t TIMER_IC2Polarity)
-{
- uint16_t tmpsmc = 0;
- uint16_t tmpchctlr1 = 0;
- uint16_t tmpche = 0;
-
- tmpsmc = TIMERx->SMC;
-
- tmpchctlr1 = TIMERx->CHCTLR1;
-
- tmpche = TIMERx->CHE;
-
- /* select the encoder Mode */
- tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_SMC));
- tmpsmc |= TIMER_EncoderMode;
-
- tmpchctlr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1M)) & (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH2M)));
- tmpchctlr1 |= TIMER_CHCTLR1_CH1M_0 | TIMER_CHCTLR1_CH2M_0;
-
- /* select the TI1 and the TI2 Polarities*/
- tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH1P | TIMER_CHE_CH1NP)) & (uint16_t)~((uint16_t)(TIMER_CHE_CH2P | TIMER_CHE_CH2NP));
- tmpche |= (uint16_t)(TIMER_IC1Polarity | (uint16_t)(TIMER_IC2Polarity << (uint16_t)4));
-
- TIMERx->SMC = tmpsmc;
-
- TIMERx->CHCTLR1 = tmpchctlr1;
-
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the Hall sensor interface
- * @param TIMERx: x ={ 1 , 8 } .
- * @param NewValue: ENABLE or DISABLE.
- * @retval None
- */
-void TIMER_SelectHallSensor(TIMER_TypeDef *TIMERx, TypeState NewValue)
-{
- if (NewValue != DISABLE) {
- TIMERx->CTLR2 |= TIMER_CTLR2_TI1S;
- } else {
- TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_TI1S);
- }
-}
-
-/* Private functions */
-/**
- * @brief Configure the TI1 as Capture Input.
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} .
- * @param TIMER_ICPolarity: Input Capture Polarity.
- * This value will be :
- * @arg TIMER_IC_POLARITY_RISING : Capture rising edge
- * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge
- * @param TIMER_ICSelection: Input Capture source.
- * This value will be :
- * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC1.
- * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC2.
- * @arg TIMER_IC_SELECTION_TRC : connected to TRC.
- * @param TIMER_ICFilter: Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter)
-{
- uint16_t tmpchctlr1 = 0, tmpche = 0;
-
- /* Disable the Channel 1 */
- TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH1E);
- tmpchctlr1 = TIMERx->CHCTLR1;
- tmpche = TIMERx->CHE;
-
- /* Select the Input and Configure the filter */
- tmpchctlr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1M)) & ((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1ICF)));
- tmpchctlr1 |= (uint16_t)(TIMER_ICSelection | (uint16_t)(TIMER_ICFilter << (uint16_t)4));
-
- /* Configure the Polarity and channel enable Bit */
- tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH1P | TIMER_CHE_CH1NP));
- tmpche |= (uint16_t)(TIMER_ICPolarity | (uint16_t)TIMER_CHE_CH1E);
-
- TIMERx->CHCTLR1 = tmpchctlr1;
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TI2 as Capture Input.
- * @note None
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } .
- * @param TIMER_ICPolarity: Input Capture Polarity.
- * This value will be :
- * @arg TIMER_IC_POLARITY_RISING : Capture rising edge
- * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge
- * @param TIMER_ICSelection: Input Capture source.
- * This value will be :
- * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC2.
- * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC1.
- * @arg TIMER_IC_SELECTION_TRC : connected to TRC.
- * @param TIMER_ICFilter: Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter)
-{
- uint16_t tmpchctlr1 = 0, tmpche = 0, tmp = 0;
-
- /* Disable the Channel 2 */
- TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH2E);
- tmpchctlr1 = TIMERx->CHCTLR1;
- tmpche = TIMERx->CHE;
- tmp = (uint16_t)(TIMER_ICPolarity << 4);
-
- /* Select the Input and Configure the filter */
- tmpchctlr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2M)) & ((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2ICF)));
- tmpchctlr1 |= (uint16_t)(TIMER_ICFilter << 12);
- tmpchctlr1 |= (uint16_t)(TIMER_ICSelection << 8);
-
- /* Configure the Polarity and channel enable Bit */
- tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH2P | TIMER_CHE_CH2NP));
- tmpche |= (uint16_t)(tmp | (uint16_t)TIMER_CHE_CH2E);
-
- TIMERx->CHCTLR1 = tmpchctlr1 ;
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TI3 as Capture Input
- * @note None
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ICPolarity: Input Capture Polarity.
- * This value will be :
- * @arg TIMER_IC_POLARITY_RISING : Capture rising edge
- * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge
- * @param TIMER_ICSelection: Input Capture source.
- * This value will be :
- * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC3.
- * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC4.
- * @arg TIMER_IC_SELECTION_TRC : connected to TRC.
- * @param TIMER_ICFilter: Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter)
-{
- uint16_t tmpchctlr2 = 0, tmpche = 0, tmp = 0;
-
- /* Disable the Channel 3 */
- TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH3E);
- tmpchctlr2 = TIMERx->CHCTLR2;
- tmpche = TIMERx->CHE;
- tmp = (uint16_t)(TIMER_ICPolarity << 8);
-
- /* Select the Input and Configure the filter */
- tmpchctlr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3M)) & ((uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3ICF)));
- tmpchctlr2 |= (uint16_t)(TIMER_ICSelection | (uint16_t)(TIMER_ICFilter << (uint16_t)4));
-
- /* Configure the Polarity and channel enable Bit */
- tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH3P | TIMER_CHE_CH3NP));
- tmpche |= (uint16_t)(tmp | (uint16_t)TIMER_CHE_CH3E);
-
- TIMERx->CHCTLR2 = tmpchctlr2;
- TIMERx->CHE = tmpche;
-}
-
-/**
- * @brief Configure the TI4 as Capture Input
- * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } .
- * @param TIMER_ICPolarity: Input Capture Polarity.
- * This value will be :
- * @arg TIMER_IC_POLARITY_RISING : Capture rising edge
- * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge
- * @param TIMER_ICSelection: Input Capture source.
- * This value will be :
- * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC4.
- * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC3.
- * @arg TIMER_IC_SELECTION_TRC : connected to TRC.
- * @param TIMER_ICFilter: Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection,
- uint16_t TIMER_ICFilter)
-{
- uint16_t tmpchctlr2 = 0, tmpche = 0, tmp = 0;
-
- /* Disable the Channel 4 */
- TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH4E);
- tmpchctlr2 = TIMERx->CHCTLR2;
- tmpche = TIMERx->CHE;
- tmp = (uint16_t)(TIMER_ICPolarity << 12);
-
- /* Select the Input and Configure the filter */
- tmpchctlr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIMER_CHCTLR2_CH4M) & ((uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4ICF)));
- tmpchctlr2 |= (uint16_t)(TIMER_ICSelection << 8);
- tmpchctlr2 |= (uint16_t)(TIMER_ICFilter << 12);
-
- /* Configure the Polarity and channel enable Bit */
- tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH4P | TIMER_CHE_CH4NP));
- tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH4P));
- tmpche |= (uint16_t)(tmp | (uint16_t)TIMER_CHE_CH4E);
-
- TIMERx->CHCTLR2 = tmpchctlr2;
- TIMERx->CHE = tmpche;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c
deleted file mode 100644
index fa9304dd7b..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/**
- ******************************************************************************
- * @brief USART functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_usart.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/** @defgroup USART_Private_Defines
- * @{
- */
-/* USART Interrupts mask */
-#define INT_MASK ((uint16_t)(0x001F))
-
-/* USART CTLR1 initializes bit mask */
-#define CTLR1_CLEAR_MASK ((uint16_t)(0x160C))
-
-/* USART CTLR2 CLOCK initializes bit mask */
-#define CTLR2_CLOCK_CLEAR_MASK ((uint16_t)(0x0F00))
-
-/* USART CTLR3 initializes bit mask */
-#define CTLR3_CLEAR_MASK ((uint16_t)(0x0300))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the USART peripheral.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: new value of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef *USARTx)
-{
- if (USARTx == USART0) {
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_USART0RST, ENABLE);
- RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_USART0RST, DISABLE);
- } else if (USARTx == USART1) {
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART1RST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART1RST, DISABLE);
- } else if (USARTx == USART2) {
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART2RST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART2RST, DISABLE);
- } else if (USARTx == UART3) {
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART3RST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART3RST, DISABLE);
- } else {
- if (USARTx == UART4) {
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART4RST, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART4RST, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initialize the USART peripheral interface parameters.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_InitParaStruct: the struct USART_InitPara pointer.
- * @retval None
- */
-void USART_Init(USART_TypeDef *USARTx, USART_InitPara *USART_InitParaStruct)
-{
- uint32_t divider = 0, apbclock = 0, temp = 0;
- RCC_ClocksPara RCC_ClocksState;
-
- USARTx->CTLR1 &= ~((uint32_t)USART_CTLR1_UEN);
- /* Initialize CTLR2 */
- temp = USARTx->CTLR2;
- /* Reset stop bits then set it use USART_STBits */
- temp &= ~((uint32_t)USART_CTLR2_STB);
- temp |= (uint32_t)USART_InitParaStruct->USART_STBits;
-
- USARTx->CTLR2 = temp;
-
- /*Initialize CTLR1*/
- temp = USARTx->CTLR1;
- /* Reset WL, PCEN, PM, TEN and REN bits */
- temp &= ~((uint32_t)CTLR1_CLEAR_MASK);
-
- /* According to USART_WL,USART_Parity,USART_RxorTx to configure the CTLR1 */
- temp |= (uint32_t)USART_InitParaStruct->USART_WL | USART_InitParaStruct->USART_Parity |
- USART_InitParaStruct->USART_RxorTx;
- USARTx->CTLR1 = temp;
-
- /*Initialize CTLR3*/
- temp = USARTx->CTLR3;
- /* Reset CTSEN and RTSEN bits */
- temp &= ~((uint32_t)CTLR3_CLEAR_MASK);
-
- /* According to USART_HardwareFlowControl to configure the CTLR3 */
- temp |= USART_InitParaStruct->USART_HardwareFlowControl;
- USARTx->CTLR3 = temp;
-
- /*Initialize USART BRR*/
- RCC_GetClocksFreq(&RCC_ClocksState);
-
- if (USARTx == USART0) {
- apbclock = RCC_ClocksState.APB2_Frequency;
- } else {
- apbclock = RCC_ClocksState.APB1_Frequency;
- }
-
- /* Get integer of baud-rate divide and raction of baud-rate divider */
- divider = (uint32_t)((apbclock) / ((USART_InitParaStruct->USART_BRR)));
- temp = (uint32_t)((apbclock) % ((USART_InitParaStruct->USART_BRR)));
-
- /* Round the divider : if fractional part i greater than 0.5 increment divider */
- if (temp >= (USART_InitParaStruct->USART_BRR) / 2) {
- divider++;
- }
-
- USARTx->BRR = (uint16_t)divider;
-}
-
-/**
- * @brief Initial the struct USART_InitPara
- * @param USART_InitParaStruct: the struct USART_InitPara pointer
- * @retval None
- */
-void USART_ParaInit(USART_InitPara *USART_InitParaStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitParaStruct->USART_BRR = 9600;
- USART_InitParaStruct->USART_WL = USART_WL_8B;
- USART_InitParaStruct->USART_STBits = USART_STBITS_1;
- USART_InitParaStruct->USART_Parity = USART_PARITY_RESET;
- USART_InitParaStruct->USART_RxorTx = USART_RXORTX_RX | USART_RXORTX_TX;
- USART_InitParaStruct->USART_HardwareFlowControl = USART_HARDWAREFLOWCONTROL_NONE;
-}
-
-/**
- * @brief Initialize the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitPara *USART_ClockInitStruct)
-{
- uint32_t temp = 0;
-
- temp = USARTx->CTLR2;
- /* Clear CKEN, CPL, CPH, LBCP and SSM bits */
- temp &= ~(CTLR2_CLOCK_CLEAR_MASK);
-
- /* Reset hen set it usethe USART Clock, CPL, CPH, LBCP */
- temp |= (uint32_t)(USART_ClockInitStruct->USART_CKEN | USART_ClockInitStruct->USART_CPL |
- USART_ClockInitStruct->USART_CPH | USART_ClockInitStruct->USART_LBCP);
- /* Write to USART CTLR2 */
- USARTx->CTLR2 = (uint16_t)temp;
-}
-
-/**
- * @brief Initial the struct USART_ClockInitPara.
- * @param USART_ClockInitParaStruct: the struct USART_ClockInitPara pointer
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitPara *USART_ClockInitParaStruct)
-{
- /*Reset USART_ClockInitStruct members default value */
- USART_ClockInitParaStruct->USART_CKEN = USART_CKEN_RESET;
- USART_ClockInitParaStruct->USART_CPL = USART_CPL_LOW;
- USART_ClockInitParaStruct->USART_CPH = USART_CPH_1EDGE;
- USART_ClockInitParaStruct->USART_LBCP = USART_LBCP_DISABLE;
-}
-
-/**
- * @brief Enable or disable the specified USART peripheral.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: new value of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* Enable or disable the specified USART peripheral by setting the UEN bit in the CTLR1 register */
- if (NewValue != DISABLE) {
- USARTx->CTLR1 |= USART_CTLR1_UEN;
- } else {
- USARTx->CTLR1 &= ~((uint16_t)USART_CTLR1_UEN);
- }
-}
-
-/**
- * @brief Set the system clock prescaler.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note This function has to be called before calling USART_Enable() function.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
-{
- /* Clear and set the USART prescaler */
- USARTx->GTPR &= ~((uint16_t)USART_GTPR_PSC);
-
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @brief Send data by the USART peripheral.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param Data: the data will be sent.
- * @retval None
- */
-void USART_DataSend(USART_TypeDef *USARTx, uint16_t Data)
-{
- USARTx->DR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Receive data by the USART peripheral.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @retval The received data.
- */
-uint16_t USART_DataReceive(USART_TypeDef *USARTx)
-{
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
-}
-
-
-/**
- * @brief Set the address of the USART terminal.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_Address(USART_TypeDef *USARTx, uint8_t USART_Address)
-{
- /* Clear the USART address and Set the USART terminal*/
- USARTx->CTLR2 &= ~USART_CTLR2_ADD;
-
- USARTx->CTLR2 |= USART_Address;
-}
-
-/**
- * @brief Enable or disable the USART's mute mode.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_MuteMode_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* By setting the MEN bit in the CTLR1 register enable or disable the USART's mute mode*/
- if (NewValue != DISABLE) {
- USARTx->CTLR1 |= USART_CTLR1_RWU;
- } else {
- USARTx->CTLR1 &= ~USART_CTLR1_RWU;
- }
-}
-
-/**
- * @brief Set the USART WakeUp method from mute mode.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_WakeUp
- * This parameter can be one of the following values
- * @arg USART_WAKEUP_IDLELINE
- * @arg USART_WAKEUP_ADDRESSMARK
- * @retval None
- */
-void USART_MuteModeWakeUp_Set(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
-{
- USARTx->CTLR1 &= ~((uint16_t)USART_CTLR1_WM);
- USARTx->CTLR1 |= USART_WakeUp;
-}
-
-
-/**
- * @brief Set the USART LIN Break detection length.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_LINBreakDetectLength
- * This parameter can be one of the following values
- * @arg USART_LINBREAKDETECTLENGTH_10B
- * @arg USART_LINBREAKDETECTLENGTH_11B
- * @retval None
- */
-void USART_SetLINBDLength(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
-{
- USARTx->CTLR2 &= ~((uint16_t)USART_CTLR2_LBDL);
- USARTx->CTLR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enable or disable the USART's LIN mode.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: the USART LIN mode value.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LIN_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* By setting the LINEN bit in the CTLR2 register enable or disable the USART's LIN mode */
- if (NewValue != DISABLE) {
- USARTx->CTLR2 |= USART_CTLR2_LMEN;
- } else {
- USARTx->CTLR2 &= ~((uint16_t)USART_CTLR2_LMEN);
- }
-}
-
-/**
- * @brief Enable or disable the Half-duplex mode.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: the USART Half-duplex mode value.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplex_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* By setting the HDEN bit in the CTLR3 register enable or disable the Half-duplex mode */
- if (NewValue != DISABLE) {
- USARTx->CTLR3 |= USART_CTLR3_HDEN;
- } else {
- USARTx->CTLR3 &= ~USART_CTLR3_HDEN;
- }
-}
-
-/**
- * @brief Set the the USART guard time.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @param USART_GuardTime: the USART guard time.
- * @retval None
- */
-void USART_GuardTime_Set(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
-{
- /* Set the USART guard time */
- USARTx->GTPR &= ~((uint16_t)USART_GTPR_GT);
-
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enable or disable the USART's Smart Card mode.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @param NewValue: the Smart Card mode value.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCard_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* By setting the SCEN bit in the CTLR3 register enable or disable the USART's Smart Card mode */
- if (NewValue != DISABLE) {
- USARTx->CTLR3 |= USART_CTLR3_SCEN;
- } else {
- USARTx->CTLR3 &= ~((uint16_t)USART_CTLR3_SCEN);
- }
-}
-
-/**
- * @brief Enable or disable NACK transmission.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: the NACK transmission state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACK_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* By setting the NACK bit in the CTLR3 register Enable or disable NACK transmission */
- if (NewValue != DISABLE) {
- USARTx->CTLR3 |= USART_CTLR3_NACK;
- } else {
- USARTx->CTLR3 &= ~((uint32_t)USART_CTLR3_NACK);
- }
-}
-
-/**
- * @brief DMA enable for transmission or reception.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_DMAEnable: the DMA request.
- * This parameter can be one of the following values
- * @arg USART_DMAREQ_RX
- * @arg USART_DMAREQ_TX
- * @param NewValue: the DMA Request sources state.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMA_Enable(USART_TypeDef *USARTx, uint16_t USART_DMAEnable, TypeState NewValue)
-{
- /* Enable or disable the DMA transfer for transmission or reception by setting the DENT and/or
- DENR bits in the USART CTLR3 register */
- if (NewValue != DISABLE) {
- USARTx->CTLR3 |= USART_DMAEnable;
- } else {
- USARTx->CTLR3 &= ~USART_DMAEnable;
- }
-
-}
-
-/**
- * @brief Set the USARTX IrDA low-power.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_IrDAMode
- * This parameter can be one of the following values
- * @arg USART_IRDAMODE_LOWPOWER
- * @arg USART_IRDAMODE_NORMAL.
- * @retval None
- */
-void USART_IrDA_Set(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
-{
- USARTx->CTLR3 &= ~((uint16_t)USART_CTLR3_IRLP);
- USARTx->CTLR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enable or disable the USART's IrDA interface.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param NewValue: the IrDA mode value.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDA_Enable(USART_TypeDef *USARTx, TypeState NewValue)
-{
- /* By setting the IREN bit in the CTLR3 register enable or disable the USART's IrDA interface */
- if (NewValue != DISABLE) {
- USARTx->CTLR3 |= USART_CTLR3_IREN;
- } else {
- USARTx->CTLR3 &= ~((uint16_t)USART_CTLR3_IREN);
- }
-}
-
-/**
- * @brief Detect the bit flag of STR register.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_FLAG: the flag of STR register.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTSF: CTS Change flag.(not available for UART4 and UART5)
- * @arg USART_FLAG_LBDF: LIN Break detection flag
- * @arg USART_FLAG_TBE: Transmit data register empty flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RBNE: Receive data register not empty flag.
- * @arg USART_FLAG_IDLEF:Idle Line detection flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Error flag.
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-TypeState USART_GetBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG)
-{
- if ((USARTx->STR & USART_FLAG) != (uint16_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Enable or disable USART interrupt.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_INT: the USART interrupt
- * This parameter can be one of the following values:
- * @arg USART_INT_PE
- * @arg USART_INT_TBE
- * @arg USART_INT_TC
- * @arg USART_INT_RBNE
- * @arg USART_INT_IDLEF
- * @arg USART_INT_LBDF
- * @arg USART_INT_CTSF (not available for UART4 and UART5)
- * @arg USART_INT_ERIE
- * @param NewValue: the USART interrupt State.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_INT_Set(USART_TypeDef *USARTx, uint16_t USART_INT, TypeState NewValue)
-{
- uint32_t intpos = 0, usartreg = 0;
- uint32_t usartxbase = 0;
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index and the interrupt position */
- usartreg = ((uint8_t)(USART_INT) >> 0x05);
- intpos = USART_INT & INT_MASK;
-
- /* Get the interrupt from which register: CTLR1,CTLR2 OR CTLR3 */
- if (usartreg == 0x01) {
- usartxbase += 0x0C;
- } else if (usartreg == 0x02) {
- usartxbase += 0x10;
- } else {
- usartxbase += 0x14;
- }
- if (NewValue != DISABLE) {
- *(__IO uint32_t *)usartxbase |= (((uint32_t)0x01) << intpos);
- } else {
- *(__IO uint32_t *)usartxbase &= ~(((uint32_t)0x01) << intpos);
- }
-}
-
-/**
- * @brief Clear the bit flag.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_FLAG: the bit flag usart .
- * This parameter can be one of the following values:
- * @arg USART_FLAG_CTSF: CTS Change flag.(not available for UART4 and UART5)
- * @arg USART_FLAG_LBDF: LIN Break detection flag
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RBNE: Receive data register not empty flag.
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLEF (Idle line detected) flag bits are cleared by
- * software sequence: a read operation to USART_STR register
- * (USART_GetBitState()) followed by a read operation to USART_DR register
- * (USART_DataReceive()).
- * - RBNE flag bit can be also cleared by a read to the USART_DR register
- * (USART_DataReceive()).
- * - TC flag bit can be also cleared by software sequence: a read
- * operation to USART_STR register (USART_GetBitState()) followed by a write
- * operation to USART_DR register (USART_DataSend()).
- * - TBE flag bit is cleared only by a write to the USART_DR register
- * (USART_DataSend()).
- * @retval None
- */
-void USART_ClearBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG)
-{
- USARTx->STR = (uint16_t)~ USART_FLAG;
-}
-
-/**
- * @brief Detect the interrupt bit flag.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_INT: the USART interrupt bit flag.
- * This parameter can be one of the following values:
- * @arg USART_INT_PE
- * @arg USART_INT_TBE
- * @arg USART_INT_TC
- * @arg USART_INT_RBNE
- * @arg USART_INT_IDLEF
- * @arg USART_INT_LBDF
- * @arg USART_INT_CTSF: CTS flag interrupt (not available for UART4 and UART5)
- * @arg USART_INT_ORE
- * @arg USART_INT_NE
- * @arg USART_INT_FE
- * @retval The new state of USART_INT (SET or RESET).
- */
-TypeState USART_GetIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT)
-{
- uint16_t bitpos = 0, itmask = 0, usartreg = 0;
-
- /* Get the USART register index and the interrupt position */
- usartreg = (((uint8_t)USART_INT) >> 0x05);
-
- itmask = (USART_INT) & (INT_MASK);
-
- itmask = (uint16_t)0x01 << itmask;
-
- if (usartreg == 0x01) {
- itmask &= USARTx->CTLR1;
- } else {
- if (usartreg == 0x02) {
- itmask &= USARTx->CTLR2;
- } else {
- itmask &= USARTx->CTLR3;
- }
- }
-
- bitpos = USART_INT >> 0x08;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->STR;
- if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear the interrupt bit flag.
- * @param USARTx: the USART peripheral.
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @param USART_INT: the interrupt bit flag.
- * This parameter can be one of the following values: * @arg USART_INT_TC
- * @arg USART_INT_LBDF
- * @arg USART_INT_CTSF: CTS Flag interrupt (not available for UART4 and UART5)
- * @arg USART_INT_RBNE
- * @arg USART_INT_TC
- * @note
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLEF (Idle line detected flag) interrupt bits are cleared by
- * software sequence: a read operation to USART_STR register
- * (USART_GetINTState()) followed by a read operation to USART_DR register
- * (USART_DataReceive()).
- * - RBNE interrupt bit can be also cleared by a read to the USART_DR register
- * (USART_DataReceive()).
- * - TC interrupt bit can be also cleared by software sequence: a read
- * operation to USART_STR register (USART_GetINTState()) followed by a write
- * operation to USART_DR register (USART_DataSend()).
- * - TBE interrupt bit is cleared only by a write to the USART_DR register
- * (USART_DataSend()).
- * @retval None
- */
-void USART_ClearIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT)
-{
- uint16_t bitpos = 0, itmask = 0;
-
- bitpos = USART_INT >> 0x08;
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
- USARTx->STR = (uint16_t)~itmask;
-}
-
-/**
- * @brief Send break command.
- * @param USARTx: the USART peripheral
- * This parameter can be one of the following values
- * @arg USART1
- * @arg USART2
- * @arg USART3
- * @arg UART4
- * @arg UART5
- * @retval None
- */
-void USART_SendBreak(USART_TypeDef *USARTx)
-{
-
- /* Send break command */
- USARTx->CTLR1 |= USART_CTLR1_SBKCMD;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c
deleted file mode 100644
index 504aad2868..0000000000
--- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
- ******************************************************************************
- * @brief WWDG functions of the firmware library.
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "gd32f10x_wwdg.h"
-#include "gd32f10x_rcc.h"
-
-/** @addtogroup GD32F10x_Firmware
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/** @defgroup WWDG_Private_Variables
- * @{
- */
-
-/* CFR register bit mask */
-#define CFR_PS_MASK ((uint32_t)0xFFFFFE7F)
-#define CFR_WIN_MASK ((uint32_t)0xFFFFFF80)
-#define BIT_MASK ((uint8_t)0x7F)
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/**
- * @brief Reset the WWDG configuration.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_WWDG, ENABLE);
- RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_WWDG, DISABLE);
-}
-
-/**
- * @brief Set WWDG prescaler value.
- * @param PrescalerValue: WWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg WWDG_PRESCALER_1: the time base of watchdog counter = (PCLK1/4096)/1
- * @arg WWDG_PRESCALER_2: the time base of watchdog counter = (PCLK1/4096)/2
- * @arg WWDG_PRESCALER_4: the time base of watchdog counter = (PCLK1/4096)/4
- * @arg WWDG_PRESCALER_8: the time base of watchdog counter = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescalerValue(uint32_t PrescalerValue)
-{
- uint32_t temp = 0;
-
- /* Clear PS[1:0] bits */
- temp = WWDG->CFR & CFR_PS_MASK;
-
- /* Set PS[1:0] bits */
- temp |= PrescalerValue;
- WWDG->CFR = temp;
-}
-
-/**
- * @brief Set watchdog window value.
- * @param WindowValue: the window value to be compared to the downcounter.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t temp = 0;
-
- /* Clear WIN[6:0] bits */
- temp = WWDG->CFR & CFR_WIN_MASK;
-
- /* Set WIN[6:0] bits */
- temp |= WindowValue & (uint32_t) BIT_MASK;
- WWDG->CFR = temp;
-}
-
-/**
- * @brief Enable the WWDG Early wakeup interrupt(EWI).
- * @note An interrupt occurs when the counter reaches 0x40 if the bit is set.
- * It's cleared by a hardware reset. A write of 0 has no effect.
- * @param None
- * @retval None
- */
-void WWDG_EnableInt(void)
-{
- WWDG->CFR |= WWDG_CFR_EWI;
-}
-
-/**
- * @brief Set the value of the watchdog counter.
- * @param CounterValue: the watchdog counter value.
- * @retval None
- */
-void WWDG_SetCounterValue(uint8_t CounterValue)
-{
- /* Write to CNT[6:0] bits */
- WWDG->CTLR = CounterValue & BIT_MASK;
-}
-
-/**
- * @brief Start the window watchdog counter.
- * @param CounterValue: The value of the watchdog counter.
- * @retval None
- */
-void WWDG_Enable(uint8_t CounterValue)
-{
- WWDG->CTLR = WWDG_CTLR_WDGEN | CounterValue;
-}
-
-/**
- * @brief Check the Early Wakeup interrupt bit state.
- * @param None
- * @retval The new state of the Early Wakeup interrupt (SET or RESET).
- */
-TypeState WWDG_GetBitState(void)
-{
- if ((WWDG->STR) != (uint32_t)RESET) {
- return SET;
- } else {
- return RESET;
- }
-}
-
-/**
- * @brief Clear Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearBitState(void)
-{
- WWDG->STR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
diff --git a/bsp/gd32103c-eval/Libraries/SConscript b/bsp/gd32103c-eval/Libraries/SConscript
deleted file mode 100644
index a4967104cb..0000000000
--- a/bsp/gd32103c-eval/Libraries/SConscript
+++ /dev/null
@@ -1,26 +0,0 @@
-import rtconfig
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-
-src = Glob('GD32F1xx_standard_peripheral/Source/*.c')
-src += [cwd + '/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c']
-
-#add for startup script
-if rtconfig.CROSS_TOOL == 'gcc':
- src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s']
- src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s']
-
-path = [
- cwd + '/CMSIS/GD/GD32F1xx/Include',
- cwd + '/CMSIS',
- cwd + '/GD32F1xx_standard_peripheral/Include',]
-
-CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F1XX']
-
-group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')
diff --git a/bsp/gd32103c-eval/README.md b/bsp/gd32103c-eval/README.md
deleted file mode 100644
index d55bccd908..0000000000
--- a/bsp/gd32103c-eval/README.md
+++ /dev/null
@@ -1,74 +0,0 @@
-# GD32103C-EVAL
-
-## 简介
-
-GD32103C-EVAL是-兆易创新推出的一款GD32F103VCT6系列的评估板，板载资源主要如下：
-
-| 硬件 | 描述 |
-| --------- | ------------- |
-| 芯片型号 | GD32F103VCT6 |
-| CPU | ARM Cortex M3 |
-| 主频 | 108M |
-| 片内SRAM | 48K |
-| 片内FLASH | 256K |
-| 片外FLASH | 1Gb |
-
-## 编译说明
-
-GD32103C-EVAL板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息：
-
-| IDE/编译器 | 已测试版本 |
-| ---------- | ---------------------------- |
-| GCC |gcc version 6.2.1 20161205 (release) |
-
-## 烧写及执行
-
-供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。
-
-下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。
-
-串口连接：使用串口线连接到COM1(UART0)，或者使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)。
-
-### 运行结果
-
-如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
-
-```bash
- \ | /
-- RT - Thread Operating System
- / | \ 4.0.3 build Jan 4 2021
- 2006 - 2021 Copyright by rt-thread team
-msh />
-```
-## 驱动支持情况及计划
-
-| 驱动 | 支持情况 | 备注 |
-| --------- | -------- | :------------------------: |
-| UART | 支持 | UART0~4 |
-| GPIO | 支持 | GPIOA~G |
-| ADC | 支持 | ADC0~1 |
-| HWTIMER | 支持 | TIMER0~7 |
-| RTC | 支持 | RTC |
-| WDT | 支持 | Free watchdog timer |
-| IIC | 未支持 | I2C0~1 |
-| SPI | 未支持 | SPI0~2 |
-| ETH | 未支持 | |
-| LCD | 未支持 | |
-| SDRAM | 未支持 | |
-| SPI FLASH | 未支持 | |
-
-### IO在板级支持包中的映射情况
-
-| IO号 | 板级包中的定义 |
-| ---- | -------------- |
-| PC0 | LED1 |
-| PC2 | LED2 |
-| PE0 | LED3 |
-| PE1 | LED4 |
-| PA0 | KEY1 |
-| PC13 | KEY2 |
-| PB14 | KEY3 |
-
-## 联系人信息
-
-维护人：[iysheng](https://github.com/iysheng)
diff --git a/bsp/gd32103c-eval/SConstruct b/bsp/gd32103c-eval/SConstruct
deleted file mode 100644
index 6b5d561848..0000000000
--- a/bsp/gd32103c-eval/SConstruct
+++ /dev/null
@@ -1,40 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
- RTT_ROOT = os.getenv('RTT_ROOT')
-else:
- RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-try:
- from building import *
-except:
- print('Cannot found RT-Thread root directory, please check RTT_ROOT')
- print(RTT_ROOT)
- exit(-1)
-
-TARGET = 'rtthread-gd32f4xx.' + rtconfig.TARGET_EXT
-
-DefaultEnvironment(tools=[])
-env = Environment(tools = ['mingw'],
- AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
- CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
- AR = rtconfig.AR, ARFLAGS = '-rc',
- LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-if rtconfig.PLATFORM == 'iar':
- env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
- env.Replace(ARFLAGS = [''])
- env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
-
-# make a building
-DoBuilding(TARGET, objs)
diff --git a/bsp/gd32103c-eval/applications/main.c b/bsp/gd32103c-eval/applications/main.c
deleted file mode 100644
index e9256f1d4d..0000000000
--- a/bsp/gd32103c-eval/applications/main.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-01-04 iysheng first version
- */
-
-#include
-#include
-#include
-#include
-#include
-#include "board.h"
-
-#define LED1 GET_PIN(C, 0)
-
-int main(void)
-{
- rt_pin_mode(LED1, PIN_MODE_OUTPUT);
-
- while (1)
- {
- rt_pin_write(LED1, PIN_HIGH);
- rt_thread_mdelay(500);
- rt_pin_write(LED1, PIN_LOW);
- rt_thread_mdelay(500);
- }
-
- return 0;
-}
diff --git a/bsp/gd32103c-eval/drivers/SConscript b/bsp/gd32103c-eval/drivers/SConscript
deleted file mode 100644
index 30a1a338d0..0000000000
--- a/bsp/gd32103c-eval/drivers/SConscript
+++ /dev/null
@@ -1,35 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = os.path.join(str(Dir('#')), 'drivers')
-
-# add the general drivers.
-src = Split("""
-board.c
-""")
-
-CPPPATH = [cwd]
-
-# add uart drivers.
-if GetDepend('RT_USING_SERIAL'):
- src += ['drv_usart.c']
-
-if GetDepend('RT_USING_PIN'):
- src += ['drv_gpio.c']
-
-if GetDepend('RT_USING_ADC'):
- src += ['drv_adc.c']
-
-if GetDepend('RT_USING_HWTIMER'):
- src += ['drv_hwtimer.c']
-
-if GetDepend('RT_USING_RTC'):
- src += ['drv_rtc.c']
-
-if GetDepend('RT_USING_WDT'):
- src += ['drv_iwdt.c']
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/gd32103c-eval/drivers/board.h b/bsp/gd32103c-eval/drivers/board.h
deleted file mode 100644
index 6e48eba213..0000000000
--- a/bsp/gd32103c-eval/drivers/board.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-01-04 iysheng first version
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include
-
-#include "drv_gpio.h"
-
-#define GD32_SRAM_SIZE 48
-#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
-
-extern int __bss_end;
-#define HEAP_BEGIN (&__bss_end)
-
-#define HEAP_END GD32_SRAM_END
-
-#endif
diff --git a/bsp/gd32103c-eval/drivers/drv_comm.h b/bsp/gd32103c-eval/drivers/drv_comm.h
deleted file mode 100644
index 5aef53cce2..0000000000
--- a/bsp/gd32103c-eval/drivers/drv_comm.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-01-28 iysheng first version
- */
-
-#ifndef __DRV_COMM_H__
-#define __DRV_COMM_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DRV_HWTIMER_H__ */
-
diff --git a/bsp/gd32103c-eval/drivers/drv_gpio.c b/bsp/gd32103c-eval/drivers/drv_gpio.c
deleted file mode 100644
index beee11b65d..0000000000
--- a/bsp/gd32103c-eval/drivers/drv_gpio.c
+++ /dev/null
@@ -1,512 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-12-27 iysheng first version
- * 2021-01-01 iysheng support exti interrupt
- */
-
-#include
-#include "drv_gpio.h"
-
-#ifdef RT_USING_PIN
-
-#if defined(GPIOG)
-#define __GD32_PORT_MAX 7u
-#elif defined(GPIOF)
-#define __GD32_PORT_MAX 6u
-#elif defined(GPIOE)
-#define __GD32_PORT_MAX 5u
-#elif defined(GPIOD)
-#define __GD32_PORT_MAX 4u
-#elif defined(GPIOC)
-#define __GD32_PORT_MAX 3u
-#elif defined(GPIOB)
-#define __GD32_PORT_MAX 2u
-#elif defined(GPIOA)
-#define __GD32_PORT_MAX 1u
-#else
-#define __GD32_PORT_MAX 0u
-#error Unsupported GD32 GPIO peripheral.
-#endif
-
-#define PIN_GDPORT_MAX __GD32_PORT_MAX
-
-static const struct pin_irq_map pin_irq_map[] =
-{
-#if defined(SOC_SERIES_GD32F1)
- {GPIO_PIN_0, EXTI0_IRQn},
- {GPIO_PIN_1, EXTI1_IRQn},
- {GPIO_PIN_2, EXTI2_IRQn},
- {GPIO_PIN_3, EXTI3_IRQn},
- {GPIO_PIN_4, EXTI4_IRQn},
- {GPIO_PIN_5, EXTI9_5_IRQn},
- {GPIO_PIN_6, EXTI9_5_IRQn},
- {GPIO_PIN_7, EXTI9_5_IRQn},
- {GPIO_PIN_8, EXTI9_5_IRQn},
- {GPIO_PIN_9, EXTI9_5_IRQn},
- {GPIO_PIN_10, EXTI15_10_IRQn},
- {GPIO_PIN_11, EXTI15_10_IRQn},
- {GPIO_PIN_12, EXTI15_10_IRQn},
- {GPIO_PIN_13, EXTI15_10_IRQn},
- {GPIO_PIN_14, EXTI15_10_IRQn},
- {GPIO_PIN_15, EXTI15_10_IRQn},
-#else
-#error "Unsupported soc series"
-#endif
-};
-
-static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
-{
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
- {-1, 0, RT_NULL, RT_NULL},
-};
-static uint32_t pin_irq_enable_mask = 0;
-
-#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
-
-static rt_base_t gd32_pin_get(const char *name)
-{
- rt_base_t pin = 0;
- int hw_port_num, hw_pin_num = 0;
- int i, name_len;
-
- name_len = rt_strlen(name);
-
- if ((name_len < 4) || (name_len >= 6))
- {
- return -RT_EINVAL;
- }
- if ((name[0] != 'P') || (name[2] != '.'))
- {
- return -RT_EINVAL;
- }
-
- if ((name[1] >= 'A') && (name[1] <= 'Z'))
- {
- hw_port_num = (int)(name[1] - 'A');
- }
- else
- {
- return -RT_EINVAL;
- }
-
- for (i = 3; i < name_len; i++)
- {
- hw_pin_num *= 10;
- hw_pin_num += name[i] - '0';
- }
-
- pin = PIN_NUM(hw_port_num, hw_pin_num);
-
- return pin;
-}
-
-static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
-{
- GPIO_TypeDef *gpio_port;
- uint16_t gpio_pin;
-
- if (PIN_PORT(pin) < PIN_GDPORT_MAX)
- {
- gpio_port = PIN_GDPORT(pin);
- gpio_pin = PIN_GDPIN(pin);
-
- GPIO_WriteBit(gpio_port, gpio_pin, (BitState)value);
- }
-}
-
-static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
-{
- GPIO_TypeDef *gpio_port;
- uint16_t gpio_pin;
- int value = PIN_LOW;
-
- if (PIN_PORT(pin) < PIN_GDPORT_MAX)
- {
- gpio_port = PIN_GDPORT(pin);
- gpio_pin = PIN_GDPIN(pin);
- value = GPIO_ReadInputBit(gpio_port, gpio_pin);
- }
-
- return value;
-}
-
-static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
-{
- GPIO_InitPara GPIO_InitStruct = {0};
-
- if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
- {
- return;
- }
-
- /* Configure GPIO_InitStructure */
- GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
- GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_2MHZ;
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IN_FLOATING;
-
- switch (mode)
- {
- case PIN_MODE_OUTPUT:
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUT_PP;
- break;
- case PIN_MODE_INPUT:
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IN_FLOATING;
- break;
- case PIN_MODE_INPUT_PULLUP:
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPD;
- break;
- case PIN_MODE_INPUT_PULLDOWN:
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPU;
- break;
- case PIN_MODE_OUTPUT_OD:
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUT_OD;
- break;
- default:
- break;
- }
-
- GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct);
-}
-
-rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
-{
- int i;
- for (i = 0; i < 32; i++)
- {
- if ((0x01 << i) == bit)
- {
- return i;
- }
- }
- return -1;
-}
-
-rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
-{
- rt_int32_t mapindex = bit2bitno(pinbit);
- if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
- {
- return RT_NULL;
- }
- return &pin_irq_map[mapindex];
-};
-
-static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
- rt_uint32_t mode, void (*hdr)(void *args), void *args)
-{
- rt_base_t level;
- rt_int32_t irqindex = -1;
-
- if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
- {
- return -RT_ENOSYS;
- }
-
- irqindex = bit2bitno(PIN_GDPIN(pin));
- if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
- {
- return RT_ENOSYS;
- }
-
- level = rt_hw_interrupt_disable();
- if (pin_irq_hdr_tab[irqindex].pin == pin &&
- pin_irq_hdr_tab[irqindex].hdr == hdr &&
- pin_irq_hdr_tab[irqindex].mode == mode &&
- pin_irq_hdr_tab[irqindex].args == args)
- {
- rt_hw_interrupt_enable(level);
- return RT_EOK;
- }
- if (pin_irq_hdr_tab[irqindex].pin != -1)
- {
- rt_hw_interrupt_enable(level);
- return RT_EBUSY;
- }
- pin_irq_hdr_tab[irqindex].pin = pin;
- pin_irq_hdr_tab[irqindex].hdr = hdr;
- pin_irq_hdr_tab[irqindex].mode = mode;
- pin_irq_hdr_tab[irqindex].args = args;
- rt_hw_interrupt_enable(level);
-
- return RT_EOK;
-}
-
-static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
-{
- rt_base_t level;
- rt_int32_t irqindex = -1;
-
- if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
- {
- return -RT_ENOSYS;
- }
-
- irqindex = bit2bitno(PIN_GDPIN(pin));
- if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
- {
- return RT_ENOSYS;
- }
-
- level = rt_hw_interrupt_disable();
- if (pin_irq_hdr_tab[irqindex].pin == -1)
- {
- rt_hw_interrupt_enable(level);
- return RT_EOK;
- }
- pin_irq_hdr_tab[irqindex].pin = -1;
- pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
- pin_irq_hdr_tab[irqindex].mode = 0;
- pin_irq_hdr_tab[irqindex].args = RT_NULL;
- rt_hw_interrupt_enable(level);
-
- return RT_EOK;
-}
-
-static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
- rt_uint32_t enabled)
-{
- const struct pin_irq_map *irqmap;
- rt_base_t level;
- rt_int32_t irqindex = -1;
- GPIO_InitPara GPIO_InitStruct = {0};
- EXTI_InitPara EXTI_InitParaStruct = {0};
-
- if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
- {
- return -RT_ENOSYS;
- }
-
- GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
- EXTI_InitParaStruct.EXTI_LINE = PIN_GDPIN(pin);
- EXTI_InitParaStruct.EXTI_Mode = EXTI_Mode_Interrupt;
- if (enabled == PIN_IRQ_ENABLE)
- {
- irqindex = bit2bitno(PIN_GDPIN(pin));
- if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
- {
- return RT_ENOSYS;
- }
-
- level = rt_hw_interrupt_disable();
-
- if (pin_irq_hdr_tab[irqindex].pin == -1)
- {
- rt_hw_interrupt_enable(level);
- return RT_ENOSYS;
- }
-
- irqmap = &pin_irq_map[irqindex];
-
- /* Configure GPIO_InitStructure */
- GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_10MHZ;
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IN_FLOATING;
-
- EXTI_InitParaStruct.EXTI_LINEEnable = ENABLE;
- GPIO_EXTILineConfig(PIN_PORT(pin), PIN_NO(pin));
- switch (pin_irq_hdr_tab[irqindex].mode)
- {
- case PIN_IRQ_MODE_RISING:
- EXTI_InitParaStruct.EXTI_Trigger = EXTI_Trigger_Rising;
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPD;
- EXTI_Init(&EXTI_InitParaStruct);
- break;
- case PIN_IRQ_MODE_FALLING:
- GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPU;
- EXTI_InitParaStruct.EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_Init(&EXTI_InitParaStruct);
- break;
- case PIN_IRQ_MODE_RISING_FALLING:
- EXTI_InitParaStruct.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
- EXTI_Init(&EXTI_InitParaStruct);
- break;
- default:
- break;
- }
- GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct);
-
- NVIC_SetPriority(irqmap->irqno, 0);
- NVIC_EnableIRQ(irqmap->irqno);
- pin_irq_enable_mask |= irqmap->pinbit;
-
- rt_hw_interrupt_enable(level);
- }
- else if (enabled == PIN_IRQ_DISABLE)
- {
- irqmap = get_pin_irq_map(PIN_GDPIN(pin));
- if (irqmap == RT_NULL)
- {
- return RT_ENOSYS;
- }
-
- level = rt_hw_interrupt_disable();
-
- EXTI_InitParaStruct.EXTI_LINEEnable = DISABLE;
- EXTI_Init(&EXTI_InitParaStruct);
-
- pin_irq_enable_mask &= ~irqmap->pinbit;
- if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
- {
- if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
- {
- NVIC_DisableIRQ(irqmap->irqno);
- }
- }
- else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
- {
- if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
- {
- NVIC_DisableIRQ(irqmap->irqno);
- }
- }
- else
- {
- NVIC_DisableIRQ(irqmap->irqno);
- }
- rt_hw_interrupt_enable(level);
- }
- else
- {
- return -RT_ENOSYS;
- }
-
- return RT_EOK;
-}
-const static struct rt_pin_ops _gd32_pin_ops =
-{
- gd32_pin_mode,
- gd32_pin_write,
- gd32_pin_read,
- gd32_pin_attach_irq,
- gd32_pin_dettach_irq,
- gd32_pin_irq_enable,
- gd32_pin_get,
-};
-
-rt_inline void pin_irq_hdr(int irqno)
-{
- if (pin_irq_hdr_tab[irqno].hdr)
- {
- pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
- }
-}
-
-/**
- * @brief This function handles EXTI interrupt request.
- * @param gpio_pin: Specifies the pins connected EXTI line
- * @retval none
- */
-void gd32_pin_exti_irqhandler(uint16_t gpio_pin)
-{
- if (SET == EXTI_GetIntBitState(gpio_pin))
- {
- EXTI_ClearIntBitState(gpio_pin);
- pin_irq_hdr(bit2bitno(gpio_pin));
- }
-}
-
-void EXTI0_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_0);
- rt_interrupt_leave();
-}
-
-void EXTI1_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_1);
- rt_interrupt_leave();
-}
-
-void EXTI2_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_2);
- rt_interrupt_leave();
-}
-
-void EXTI3_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_3);
- rt_interrupt_leave();
-}
-
-void EXTI4_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_4);
- rt_interrupt_leave();
-}
-
-void EXTI5_9_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_5);
- gd32_pin_exti_irqhandler(GPIO_PIN_6);
- gd32_pin_exti_irqhandler(GPIO_PIN_7);
- gd32_pin_exti_irqhandler(GPIO_PIN_8);
- gd32_pin_exti_irqhandler(GPIO_PIN_9);
- rt_interrupt_leave();
-}
-
-void EXTI10_15_IRQHandler(void)
-{
- rt_interrupt_enter();
- gd32_pin_exti_irqhandler(GPIO_PIN_10);
- gd32_pin_exti_irqhandler(GPIO_PIN_11);
- gd32_pin_exti_irqhandler(GPIO_PIN_12);
- gd32_pin_exti_irqhandler(GPIO_PIN_13);
- gd32_pin_exti_irqhandler(GPIO_PIN_14);
- gd32_pin_exti_irqhandler(GPIO_PIN_15);
- rt_interrupt_leave();
-}
-
-int rt_hw_pin_init(void)
-{
-#if defined(GPIOG)
- rcu_periph_clock_enable(RCU_GPIOG);
-#endif
-#if defined(GPIOF)
- rcu_periph_clock_enable(RCU_GPIOF);
-#endif
-#if defined(GPIOE)
- rcu_periph_clock_enable(RCU_GPIOE);
-#endif
-#if defined(GPIOD)
- rcu_periph_clock_enable(RCU_GPIOD);
-#endif
-#if defined(GPIOC)
- rcu_periph_clock_enable(RCU_GPIOC);
-#endif
-#if defined(GPIOB)
- rcu_periph_clock_enable(RCU_GPIOB);
-#endif
-#if defined(GPIOA)
- rcu_periph_clock_enable(RCU_GPIOA);
-#endif
- rcu_periph_clock_enable(RCU_AF);
- return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
-}
-INIT_BOARD_EXPORT(rt_hw_pin_init);
-#endif /* RT_USING_PIN */
-
diff --git a/bsp/gd32103c-eval/drivers/drv_gpio.h b/bsp/gd32103c-eval/drivers/drv_gpio.h
deleted file mode 100644
index 34d30d63d4..0000000000
--- a/bsp/gd32103c-eval/drivers/drv_gpio.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2020-12-27 iysheng first release
- */
-
-#ifndef __DRV_GPIO_H__
-#define __DRV_GPIO_H__
-
-#include
-#include
-#include
-#include
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define __GD32_PORT(port) GPIO##port##_BASE
-
-#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
-
-#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
-#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
-#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
-
-#define PIN_GDPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
-#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
-
-struct pin_irq_map
-{
- rt_uint16_t pinbit;
- IRQn_Type irqno;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DRV_GPIO_H__ */
-
diff --git a/bsp/gd32103c-eval/drivers/drv_hwtimer.h b/bsp/gd32103c-eval/drivers/drv_hwtimer.h
deleted file mode 100644
index 1b1a7e7da9..0000000000
--- a/bsp/gd32103c-eval/drivers/drv_hwtimer.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-01-15 iysheng first release
- */
-
-#ifndef __DRV_HWTIMER_H__
-#define __DRV_HWTIMER_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-
-typedef struct {
- TIMER_TypeDef *reg_base;
- IRQn_Type irqn;
- rcu_periph_enum rcu;
-} gd32_hwtimer_data;
-
-typedef struct {
- char dev_name[RT_NAME_MAX];
- const gd32_hwtimer_data hw_data;
- rt_hwtimer_t hwtimer_dev;
- const struct rt_hwtimer_info hwtimer_info;
-} gd32_hwtimer_device;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DRV_HWTIMER_H__ */
-
diff --git a/bsp/gd32103c-eval/drivers/drv_usart.c b/bsp/gd32103c-eval/drivers/drv_usart.c
deleted file mode 100644
index c89ce02e0c..0000000000
--- a/bsp/gd32103c-eval/drivers/drv_usart.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-01-04 iysheng first version
- */
-
-#include
-#include
-#include
-
-#ifdef RT_USING_SERIAL
-
-#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
- !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
- !defined(BSP_USING_UART4)
- #error "Please define at least one UARTx"
-
-#endif
-
-#include
-
-static void uart_isr(struct rt_serial_device *serial);
-
-#if defined(BSP_USING_UART0)
-struct rt_serial_device serial0;
-
-void USART0_IRQHandler(void)
-{
- /* enter interrupt */
- rt_interrupt_enter();
-
- uart_isr(&serial0);
-
- /* leave interrupt */
- rt_interrupt_leave();
-}
-
-#endif /* BSP_USING_UART0 */
-
-#if defined(BSP_USING_UART1)
-struct rt_serial_device serial1;
-
-void USART1_IRQHandler(void)
-{
- /* enter interrupt */
- rt_interrupt_enter();
-
- uart_isr(&serial1);
-
- /* leave interrupt */
- rt_interrupt_leave();
-}
-
-#endif /* BSP_USING_UART1 */
-
-#if defined(BSP_USING_UART2)
-struct rt_serial_device serial2;
-
-void USART2_IRQHandler(void)
-{
- /* enter interrupt */
- rt_interrupt_enter();
-
- uart_isr(&serial2);
-
- /* leave interrupt */
- rt_interrupt_leave();
-}
-
-#endif /* BSP_USING_UART2 */
-
-#if defined(BSP_USING_UART3)
-struct rt_serial_device serial3;
-
-void UART3_IRQHandler(void)
-{
- /* enter interrupt */
- rt_interrupt_enter();
-
- uart_isr(&serial3);
-
- /* leave interrupt */
- rt_interrupt_leave();
-}
-
-#endif /* BSP_USING_UART3 */
-
-#if defined(BSP_USING_UART4)
-struct rt_serial_device serial4;
-
-void UART4_IRQHandler(void)
-{
- /* enter interrupt */
- rt_interrupt_enter();
-
- uart_isr(&serial4);
-
- /* leave interrupt */
- rt_interrupt_leave();
-}
-#endif /* BSP_USING_UART4 */
-
-static const struct gd32_uart uarts[] = {
-#ifdef BSP_USING_UART0
- {
- USART0, /* uart peripheral index */
- USART0_IRQn, /* uart iqrn */
- RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */
- GPIOA, GPIOA, /* tx port, tx alternate, tx pin */
- GPIO_PIN_9, GPIO_PIN_10, /* rx port, rx alternate, rx pin */
- &serial0,
- "uart0",
- },
-#endif
-
-#ifdef BSP_USING_UART1
- {
- USART1, /* uart peripheral index */
- USART1_IRQn, /* uart iqrn */
- RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */
- GPIOA, GPIOA, /* tx port, tx alternate, tx pin */
- GPIO_PIN_2, GPIO_PIN_3, /* rx port, rx alternate, rx pin */
- &serial1,
- "uart1",
- },
-#endif
-
-#ifdef BSP_USING_UART2
- {
- USART2, /* uart peripheral index */
- USART2_IRQn, /* uart iqrn */
- RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */
- GPIOB, GPIOB, /* tx port, tx alternate, tx pin */
- GPIO_PIN_10, GPIO_PIN_11, /* rx port, rx alternate, rx pin */
- &serial2,
- "uart2",
- },
-#endif
-
-#ifdef BSP_USING_UART3
- {
- UART3, /* uart peripheral index */
- UART3_IRQn, /* uart iqrn */
- RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */
- GPIOC, GPIOC, /* tx port, tx alternate, tx pin */
- GPIO_PIN_10, GPIO_PIN_11, /* rx port, rx alternate, rx pin */
- &serial3,
- "uart3",
- },
-#endif
-
-#ifdef BSP_USING_UART4
- {
- UART4, /* uart peripheral index */
- UART4_IRQn, /* uart iqrn */
- RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */
- GPIOC, GPIOD, /* tx port, tx alternate, tx pin */
- GPIO_PIN_12, GPIO_PIN_2, /* rx port, rx alternate, rx pin */
- &serial4,
- "uart4",
- },
-#endif
-};
-
-/**
-* @brief UART MSP Initialization
-* This function configures the hardware resources used in this example:
-* - Peripheral's clock enable
-* - Peripheral's GPIO Configuration
-* - NVIC configuration for UART interrupt request enable
-* @param huart: UART handle pointer
-* @retval None
-*/
-void gd32_uart_gpio_init(struct gd32_uart *uart)
-{
- GPIO_TypeDef *GPIOx;
- GPIO_InitPara GPIO_InitStructure = {0};
- /* enable USART clock */
- rcu_periph_clock_enable(uart->tx_gpio_clk);
- rcu_periph_clock_enable(uart->rx_gpio_clk);
- rcu_periph_clock_enable(uart->per_clk);
-
- GPIOx = (GPIO_TypeDef *)uart->tx_port;
- GPIO_InitStructure.GPIO_Pin = uart->tx_pin;
- GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_SPEED_10MHZ;
- GPIO_Init(GPIOx, &GPIO_InitStructure);
- /* TODO 初始化 RX */
- GPIOx = (GPIO_TypeDef *)uart->rx_port;
- GPIO_InitStructure.GPIO_Pin = uart->rx_pin;
- GPIO_InitStructure.GPIO_Mode = GPIO_MODE_IN_FLOATING;
- GPIO_InitStructure.GPIO_Speed = GPIO_SPEED_10MHZ;
- GPIO_Init(GPIOx, &GPIO_InitStructure);
-
- NVIC_SetPriority(uart->irqn, 0);
- NVIC_EnableIRQ(uart->irqn);
-}
-
-static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
- struct gd32_uart *uart;
- USART_TypeDef *USARTx;
- USART_InitPara USART_InitParaStruct = {0};
-
- RT_ASSERT(serial != RT_NULL);
- RT_ASSERT(cfg != RT_NULL);
-
- uart = (struct gd32_uart *)serial->parent.user_data;
- gd32_uart_gpio_init(uart);
-
- USARTx = (USART_TypeDef *)uart->uart_periph;
- USART_InitParaStruct.USART_BRR = cfg->baud_rate;
-
- switch (cfg->data_bits) {
- case DATA_BITS_9:
- USART_InitParaStruct.USART_WL = USART_WL_9B;
- break;
-
- default:
- USART_InitParaStruct.USART_WL = USART_WL_8B;
- break;
- }
-
- switch (cfg->stop_bits) {
- case STOP_BITS_2:
- USART_InitParaStruct.USART_STBits = USART_STBITS_2;
- break;
- default:
- USART_InitParaStruct.USART_STBits = USART_STBITS_1;
- break;
- }
-
- switch (cfg->parity) {
- case PARITY_ODD:
- USART_InitParaStruct.USART_Parity = USART_PARITY_SETODD;
- break;
- case PARITY_EVEN:
- USART_InitParaStruct.USART_Parity = USART_PARITY_SETEVEN;
- break;
- default:
- USART_InitParaStruct.USART_Parity = USART_PARITY_RESET;
- break;
- }
-
- USART_InitParaStruct.USART_HardwareFlowControl = USART_HARDWAREFLOWCONTROL_NONE;
- USART_InitParaStruct.USART_RxorTx = USART_RXORTX_RX | USART_RXORTX_TX;
- USART_Init(USARTx, &USART_InitParaStruct);
- USART_Enable(USARTx, ENABLE);
-
- return RT_EOK;
-}
-
-static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
- struct gd32_uart *uart;
- USART_TypeDef *USARTx;
-
- RT_ASSERT(serial != RT_NULL);
- uart = (struct gd32_uart *)serial->parent.user_data;
- USARTx = (USART_TypeDef *)uart->uart_periph;
-
- switch (cmd) {
- case RT_DEVICE_CTRL_CLR_INT:
- /* disable rx irq */
- NVIC_DisableIRQ(uart->irqn);
- /* disable interrupt */
- USART_INT_Set(USARTx, USART_INT_RBNE, DISABLE);
- break;
- case RT_DEVICE_CTRL_SET_INT:
- /* enable rx irq */
- NVIC_EnableIRQ(uart->irqn);
- /* enable interrupt */
- USART_INT_Set(USARTx, USART_INT_RBNE, ENABLE);
- break;
- }
-
- return RT_EOK;
-}
-
-static int gd32_putc(struct rt_serial_device *serial, char ch)
-{
- struct gd32_uart *uart;
-
- RT_ASSERT(serial != RT_NULL);
- uart = (struct gd32_uart *)serial->parent.user_data;
-
-
- USART_DataSend((USART_TypeDef *)uart->uart_periph, ch);
- while ((USART_GetBitState(uart->uart_periph, USART_FLAG_TC) == RESET));
-
- return 1;
-}
-
-static int gd32_getc(struct rt_serial_device *serial)
-{
- int ch;
- struct gd32_uart *uart;
-
- RT_ASSERT(serial != RT_NULL);
- uart = (struct gd32_uart *)serial->parent.user_data;
-
- ch = -1;
- if (USART_GetBitState(uart->uart_periph, USART_FLAG_RBNE) != RESET)
- ch = USART_DataReceive(uart->uart_periph);
- return ch;
-}
-
-/**
- * Uart common interrupt process. This need add to uart ISR.
- *
- * @param serial serial device
- */
-static void uart_isr(struct rt_serial_device *serial)
-{
- struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data;
-
- RT_ASSERT(uart != RT_NULL);
-
- if ((USART_GetIntBitState((USART_TypeDef *)uart->uart_periph, USART_INT_RBNE) != RESET) &&
- (USART_GetBitState((USART_TypeDef *)uart->uart_periph, USART_FLAG_RBNE) != RESET)) {
- rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
- /* Clear RXNE interrupt flag */
- USART_ClearBitState(uart->uart_periph, USART_FLAG_RBNE);
- }
-}
-
-static const struct rt_uart_ops gd32_uart_ops = {
- gd32_configure,
- gd32_control,
- gd32_putc,
- gd32_getc,
-};
-
-int gd32_hw_usart_init(void)
-{
- struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
- int i;
-
-
- for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) {
- uarts[i].serial->ops = &gd32_uart_ops;
- uarts[i].serial->config = config;
-
- /* register UART device */
- rt_hw_serial_register(uarts[i].serial,
- uarts[i].device_name,
- RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
- (void *)&uarts[i]);
- }
-
- return 0;
-}
-INIT_BOARD_EXPORT(gd32_hw_usart_init);
-#endif
diff --git a/bsp/gd32103c-eval/drivers/drv_usart.h b/bsp/gd32103c-eval/drivers/drv_usart.h
deleted file mode 100644
index ad3455db60..0000000000
--- a/bsp/gd32103c-eval/drivers/drv_usart.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-01-04 iysheng first version
- */
-
-#ifndef __USART_H__
-#define __USART_H__
-
-#include
-#include
-
-/* GD32 uart driver */
-struct gd32_uart {
- USART_TypeDef * uart_periph;
- IRQn_Type irqn;
- rcu_periph_enum per_clk;
- rcu_periph_enum tx_gpio_clk;
- rcu_periph_enum rx_gpio_clk;
- GPIO_TypeDef * tx_port;
- GPIO_TypeDef * rx_port;
- uint16_t tx_pin;
- uint16_t rx_pin;
-
- struct rt_serial_device *serial;
- char *device_name;
-};
-
-#endif
diff --git a/bsp/gd32450z-eval/.config b/bsp/gd32450z-eval/.config
index 5102985dc4..1869a867eb 100644
--- a/bsp/gd32450z-eval/.config
+++ b/bsp/gd32450z-eval/.config
@@ -263,8 +263,7 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@@ -495,6 +494,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -505,7 +505,6 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -556,6 +555,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -667,6 +667,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -754,6 +755,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
CONFIG_SOC_GD32450Z=y
CONFIG_BSP_USING_SDRAM=y
CONFIG_BSP_USING_UART0=y
diff --git a/bsp/gd32450z-eval/project.uvprojx b/bsp/gd32450z-eval/project.uvprojx
index 1fb3e8e5f0..592fc6bd8d 100644
--- a/bsp/gd32450z-eval/project.uvprojx
+++ b/bsp/gd32450z-eval/project.uvprojx
@@ -333,7 +333,7 @@
USE_STDPERIPH_DRIVER, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
- applications;.;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\nogcc;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\finsh;.;..\..\include;Libraries\CMSIS\GD\GD32F4xx\Include;Libraries\CMSIS;Libraries\GD32F4xx_standard_peripheral\Include;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\libc\posix\io;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\ipc;..\..\components\net\netdev\include;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket\sys_socket;..\..\examples\utest\testcases\kernel
+ applications;.;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\extension;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\finsh;.;..\..\include;Libraries\CMSIS\GD\GD32F4xx\Include;Libraries\CMSIS;Libraries\GD32F4xx_standard_peripheral\Include;..\..\components\net\lwip-2.0.3\src;..\..\components\net\lwip-2.0.3\src\include;..\..\components\net\lwip-2.0.3\src\include\ipv4;..\..\components\net\lwip-2.0.3\src\arch\include;..\..\components\net\lwip-2.0.3\src\include\netif;..\..\components\libc\posix\io;..\..\components\libc\posix\io\poll;..\..\components\libc\posix\ipc;..\..\components\net\netdev\include;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\socket\sys_socket;..\..\examples\utest\testcases\kernel
@@ -386,13 +386,6 @@
Compiler
-
-
- libc_syms.c
- 1
- ..\..\components\libc\compilers\armlibc\libc_syms.c
-
-
syscalls.c
@@ -407,6 +400,13 @@
..\..\components\libc\compilers\armlibc\syscall_mem.c
+
+
+ libc_syms.c
+ 1
+ ..\..\components\libc\compilers\armlibc\libc_syms.c
+
+
stdlib.c
@@ -478,9 +478,9 @@
- dataqueue.c
+ completion.c
1
- ..\..\components\drivers\src\dataqueue.c
+ ..\..\components\drivers\src\completion.c
@@ -492,9 +492,16 @@
- workqueue.c
+ ringbuffer.c
1
- ..\..\components\drivers\src\workqueue.c
+ ..\..\components\drivers\src\ringbuffer.c
+
+
+
+
+ dataqueue.c
+ 1
+ ..\..\components\drivers\src\dataqueue.c
@@ -504,13 +511,6 @@
..\..\components\drivers\src\ringblk_buf.c
-
-
- completion.c
- 1
- ..\..\components\drivers\src\completion.c
-
-
waitqueue.c
@@ -520,9 +520,9 @@
- ringbuffer.c
+ workqueue.c
1
- ..\..\components\drivers\src\ringbuffer.c
+ ..\..\components\drivers\src\workqueue.c
@@ -601,6 +601,13 @@
..\..\components\dfs\filesystems\devfs\devfs.c
+
+
+ ffunicode.c
+ 1
+ ..\..\components\dfs\filesystems\elmfat\ffunicode.c
+
+
dfs_elm.c
@@ -615,13 +622,6 @@
..\..\components\dfs\filesystems\elmfat\ff.c
-
-
- ffunicode.c
- 1
- ..\..\components\dfs\filesystems\elmfat\ffunicode.c
-
-
Finsh
@@ -656,6 +656,13 @@
Kernel
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
ipc.c
@@ -663,6 +670,55 @@
..\..\src\ipc.c
+
+
+ components.c
+ 1
+ ..\..\src\components.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\src\timer.c
+
+
+
+
+ mem.c
+ 1
+ ..\..\src\mem.c
+
+
+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
+
+
+
+
+ object.c
+ 1
+ ..\..\src\object.c
+
+
+
+
+ mempool.c
+ 1
+ ..\..\src\mempool.c
+
+
thread.c
@@ -677,20 +733,6 @@
..\..\src\kservice.c
-
-
- clock.c
- 1
- ..\..\src\clock.c
-
-
-
-
- object.c
- 1
- ..\..\src\object.c
-
-
device.c
@@ -700,51 +742,9 @@
- timer.c
+ clock.c
1
- ..\..\src\timer.c
-
-
-
-
- scheduler.c
- 1
- ..\..\src\scheduler.c
-
-
-
-
- mempool.c
- 1
- ..\..\src\mempool.c
-
-
-
-
- mem.c
- 1
- ..\..\src\mem.c
-
-
-
-
- components.c
- 1
- ..\..\src\components.c
-
-
-
-
- idle.c
- 1
- ..\..\src\idle.c
-
-
-
-
- irq.c
- 1
- ..\..\src\irq.c
+ ..\..\src\clock.c
@@ -752,37 +752,37 @@
Libraries
- gd32f4xx_dma.c
+ gd32f4xx_adc.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c
- gd32f4xx_spi.c
+ gd32f4xx_wwdgt.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c
- gd32f4xx_exti.c
+ gd32f4xx_usart.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c
- gd32f4xx_rcu.c
+ gd32f4xx_dac.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c
- gd32f4xx_enet.c
+ gd32f4xx_i2c.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c
@@ -801,23 +801,23 @@
- gd32f4xx_i2c.c
+ gd32f4xx_timer.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c
- gd32f4xx_gpio.c
+ gd32f4xx_sdio.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c
- gd32f4xx_dac.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c
+ startup_gd32f4xx.s
+ 2
+ Libraries\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s
@@ -836,86 +836,23 @@
- gd32f4xx_sdio.c
+ gd32f4xx_gpio.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c
- gd32f4xx_dci.c
+ gd32f4xx_exti.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c
- gd32f4xx_iref.c
+ gd32f4xx_rcu.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c
-
-
-
-
- system_gd32f4xx.c
- 1
- Libraries\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c
-
-
-
-
- gd32f4xx_usart.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c
-
-
-
-
- gd32f4xx_dbg.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c
-
-
-
-
- gd32f4xx_syscfg.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c
-
-
-
-
- startup_gd32f4xx.s
- 2
- Libraries\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s
-
-
-
-
- gd32f4xx_fmc.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c
-
-
-
-
- gd32f4xx_pmu.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c
-
-
-
-
- gd32f4xx_wwdgt.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c
-
-
-
-
- gd32f4xx_ctc.c
- 1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c
@@ -927,16 +864,16 @@
- gd32f4xx_ipa.c
+ gd32f4xx_spi.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c
- gd32f4xx_adc.c
+ gd32f4xx_ctc.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c
@@ -948,9 +885,44 @@
- gd32f4xx_timer.c
+ gd32f4xx_enet.c
1
- Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c
+
+
+
+
+ system_gd32f4xx.c
+ 1
+ Libraries\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c
+
+
+
+
+ gd32f4xx_fmc.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c
+
+
+
+
+ gd32f4xx_iref.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c
+
+
+
+
+ gd32f4xx_dbg.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c
+
+
+
+
+ gd32f4xx_pmu.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c
@@ -960,6 +932,34 @@
Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c
+
+
+ gd32f4xx_ipa.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c
+
+
+
+
+ gd32f4xx_syscfg.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c
+
+
+
+
+ gd32f4xx_dci.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c
+
+
+
+
+ gd32f4xx_dma.c
+ 1
+ Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c
+
+
gd32f4xx_fwdgt.c
@@ -970,263 +970,263 @@
lwIP
-
-
- ping.c
- 1
- ..\..\components\net\lwip-2.0.2\src\apps\ping\ping.c
-
-
netdb.c
1
- ..\..\components\net\lwip-2.0.2\src\api\netdb.c
+ ..\..\components\net\lwip-2.0.3\src\api\netdb.c
ip.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ip.c
+ ..\..\components\net\lwip-2.0.3\src\core\ip.c
autoip.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\autoip.c
ethernet.c
1
- ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c
+ ..\..\components\net\lwip-2.0.3\src\netif\ethernet.c
netif.c
1
- ..\..\components\net\lwip-2.0.2\src\core\netif.c
+ ..\..\components\net\lwip-2.0.3\src\core\netif.c
sys.c
1
- ..\..\components\net\lwip-2.0.2\src\core\sys.c
+ ..\..\components\net\lwip-2.0.3\src\core\sys.c
sockets.c
1
- ..\..\components\net\lwip-2.0.2\src\api\sockets.c
+ ..\..\components\net\lwip-2.0.3\src\api\sockets.c
netifapi.c
1
- ..\..\components\net\lwip-2.0.2\src\api\netifapi.c
+ ..\..\components\net\lwip-2.0.3\src\api\netifapi.c
tcpip.c
1
- ..\..\components\net\lwip-2.0.2\src\api\tcpip.c
+ ..\..\components\net\lwip-2.0.3\src\api\tcpip.c
ip4_addr.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\ip4_addr.c
dhcp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\dhcp.c
init.c
1
- ..\..\components\net\lwip-2.0.2\src\core\init.c
+ ..\..\components\net\lwip-2.0.3\src\core\init.c
ethernetif.c
1
- ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c
+ ..\..\components\net\lwip-2.0.3\src\netif\ethernetif.c
etharp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\etharp.c
memp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\memp.c
+ ..\..\components\net\lwip-2.0.3\src\core\memp.c
ip4.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\ip4.c
netbuf.c
1
- ..\..\components\net\lwip-2.0.2\src\api\netbuf.c
+ ..\..\components\net\lwip-2.0.3\src\api\netbuf.c
raw.c
1
- ..\..\components\net\lwip-2.0.2\src\core\raw.c
+ ..\..\components\net\lwip-2.0.3\src\core\raw.c
ip4_frag.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\ip4_frag.c
tcp_out.c
1
- ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c
+ ..\..\components\net\lwip-2.0.3\src\core\tcp_out.c
lowpan6.c
1
- ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c
+ ..\..\components\net\lwip-2.0.3\src\netif\lowpan6.c
icmp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\icmp.c
api_lib.c
1
- ..\..\components\net\lwip-2.0.2\src\api\api_lib.c
+ ..\..\components\net\lwip-2.0.3\src\api\api_lib.c
inet_chksum.c
1
- ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c
+ ..\..\components\net\lwip-2.0.3\src\core\inet_chksum.c
stats.c
1
- ..\..\components\net\lwip-2.0.2\src\core\stats.c
+ ..\..\components\net\lwip-2.0.3\src\core\stats.c
err.c
1
- ..\..\components\net\lwip-2.0.2\src\api\err.c
+ ..\..\components\net\lwip-2.0.3\src\api\err.c
tcp_in.c
1
- ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c
+ ..\..\components\net\lwip-2.0.3\src\core\tcp_in.c
dns.c
1
- ..\..\components\net\lwip-2.0.2\src\core\dns.c
+ ..\..\components\net\lwip-2.0.3\src\core\dns.c
sys_arch.c
1
- ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c
+ ..\..\components\net\lwip-2.0.3\src\arch\sys_arch.c
timeouts.c
1
- ..\..\components\net\lwip-2.0.2\src\core\timeouts.c
+ ..\..\components\net\lwip-2.0.3\src\core\timeouts.c
igmp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c
+ ..\..\components\net\lwip-2.0.3\src\core\ipv4\igmp.c
udp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\udp.c
+ ..\..\components\net\lwip-2.0.3\src\core\udp.c
pbuf.c
1
- ..\..\components\net\lwip-2.0.2\src\core\pbuf.c
+ ..\..\components\net\lwip-2.0.3\src\core\pbuf.c
def.c
1
- ..\..\components\net\lwip-2.0.2\src\core\def.c
+ ..\..\components\net\lwip-2.0.3\src\core\def.c
api_msg.c
1
- ..\..\components\net\lwip-2.0.2\src\api\api_msg.c
+ ..\..\components\net\lwip-2.0.3\src\api\api_msg.c
+
+
+
+
+ ping.c
+ 1
+ ..\..\components\net\lwip-2.0.3\src\apps\ping\ping.c
tcp.c
1
- ..\..\components\net\lwip-2.0.2\src\core\tcp.c
+ ..\..\components\net\lwip-2.0.3\src\core\tcp.c
@@ -1249,6 +1249,13 @@
SAL
+
+
+ netdev.c
+ 1
+ ..\..\components\net\netdev\src\netdev.c
+
+
netdev_ipaddr.c
@@ -1258,9 +1265,9 @@
- netdev.c
+ sal_socket.c
1
- ..\..\components\net\netdev\src\netdev.c
+ ..\..\components\net\sal_socket\src\sal_socket.c
@@ -1284,13 +1291,6 @@
..\..\components\net\sal_socket\dfs_net\dfs_net.c
-
-
- sal_socket.c
- 1
- ..\..\components\net\sal_socket\src\sal_socket.c
-
-
af_inet_lwip.c
diff --git a/bsp/gd32450z-eval/rtconfig.h b/bsp/gd32450z-eval/rtconfig.h
index 24e31e0e72..f77bbc63ca 100644
--- a/bsp/gd32450z-eval/rtconfig.h
+++ b/bsp/gd32450z-eval/rtconfig.h
@@ -152,7 +152,7 @@
/* light weight TCP/IP stack */
#define RT_USING_LWIP
-#define RT_USING_LWIP202
+#define RT_USING_LWIP203
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
diff --git a/bsp/imx6sx/cortex-a9/.config b/bsp/imx6sx/cortex-a9/.config
index 6cf3583151..4b42f0268a 100644
--- a/bsp/imx6sx/cortex-a9/.config
+++ b/bsp/imx6sx/cortex-a9/.config
@@ -235,8 +235,7 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@@ -467,6 +466,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -477,7 +477,6 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -528,6 +527,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -639,6 +639,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -726,5 +727,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
CONFIG_SOC_MCIMX6X4=y
CONFIG_RT_USING_UART1=y
diff --git a/bsp/imx6sx/cortex-a9/rtconfig.h b/bsp/imx6sx/cortex-a9/rtconfig.h
index 4990f78084..ee4491554a 100644
--- a/bsp/imx6sx/cortex-a9/rtconfig.h
+++ b/bsp/imx6sx/cortex-a9/rtconfig.h
@@ -134,7 +134,7 @@
/* light weight TCP/IP stack */
#define RT_USING_LWIP
-#define RT_USING_LWIP202
+#define RT_USING_LWIP203
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction.h
new file mode 100644
index 0000000000..1efab708fe
--- /dev/null
+++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction.h
@@ -0,0 +1,812 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_H_
+#define _FSL_OS_ABSTRACTION_H_
+
+#include "fsl_common.h"
+#include "fsl_os_abstraction_config.h"
+#include "generic_list.h"
+
+/*!
+ * @addtogroup osa_adapter
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Type for the Task Priority*/
+typedef uint16_t osa_task_priority_t;
+/*! @brief Type for a task handler */
+typedef void *osa_task_handle_t;
+/*! @brief Type for the parameter to be passed to the task at its creation */
+typedef void *osa_task_param_t;
+/*! @brief Type for task pointer. Task prototype declaration */
+typedef void (*osa_task_ptr_t)(osa_task_param_t task_param);
+/*! @brief Type for the semaphore handler */
+typedef void *osa_semaphore_handle_t;
+/*! @brief Type for the mutex handler */
+typedef void *osa_mutex_handle_t;
+/*! @brief Type for the event handler */
+typedef void *osa_event_handle_t;
+/*! @brief Type for an event flags group, bit 32 is reserved. */
+typedef uint32_t osa_event_flags_t;
+/*! @brief Message definition. */
+typedef void *osa_msg_handle_t;
+/*! @brief Type for the message queue handler */
+typedef void *osa_msgq_handle_t;
+/*! @brief Type for the Timer handler */
+typedef void *osa_timer_handle_t;
+/*! @brief Type for the Timer callback function pointer. */
+typedef void (*osa_timer_fct_ptr_t)(void const *argument);
+/*! @brief Thread Definition structure contains startup information of a thread.*/
+typedef struct osa_task_def_tag
+{
+ osa_task_ptr_t pthread; /*!< start address of thread function*/
+ uint32_t tpriority; /*!< initial thread priority*/
+ uint32_t instances; /*!< maximum number of instances of that thread function*/
+ uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/
+ uint32_t *tstack; /*!< stack pointer*/
+ void *tlink; /*!< link pointer*/
+ uint8_t *tname; /*!< name pointer*/
+ uint8_t useFloat; /*!< is use float*/
+} osa_task_def_t;
+/*! @brief Thread Link Definition structure .*/
+typedef struct osa_thread_link_tag
+{
+ uint8_t link[12]; /*!< link*/
+ osa_task_handle_t osThreadId; /*!< thread id*/
+ osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/
+ uint32_t *osThreadStackHandle; /*!< pointer of thread stack handle*/
+} osa_thread_link_t, *osa_thread_link_handle_t;
+
+/*! @brief Definition structure contains timer parameters.*/
+typedef struct osa_time_def_tag
+{
+ osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */
+ void *argument; /* < argument of a timer function */
+} osa_time_def_t;
+
+/*! @brief Type for the timer definition*/
+typedef enum _osa_timer
+{
+ KOSA_TimerOnce = 0, /*!< one-shot timer*/
+ KOSA_TimerPeriodic = 1 /*!< repeating timer*/
+} osa_timer_t;
+
+/*! @brief Defines the return status of OSA's functions */
+typedef enum _osa_status
+{
+ KOSA_StatusSuccess = kStatus_Success, /*!< Success */
+ KOSA_StatusError = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */
+ KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */
+ KOSA_StatusIdle = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready
+ and timeout still not occur */
+} osa_status_t;
+
+#ifdef USE_RTOS
+#undef USE_RTOS
+#endif
+
+#define USE_RTOS (1)
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#define OSA_TASK_HANDLE_SIZE (12U)
+#else
+#define OSA_TASK_HANDLE_SIZE (16U)
+#endif
+#define OSA_EVENT_HANDLE_SIZE (8U)
+#define OSA_SEM_HANDLE_SIZE (4U)
+#define OSA_MUTEX_HANDLE_SIZE (4U)
+#define OSA_MSGQ_HANDLE_SIZE (4U)
+#define OSA_MSG_HANDLE_SIZE (0U)
+
+/*! @brief Priority setting for OSA. */
+#ifndef OSA_PRIORITY_IDLE
+#define OSA_PRIORITY_IDLE (6)
+#endif
+
+#ifndef OSA_PRIORITY_LOW
+#define OSA_PRIORITY_LOW (5)
+#endif
+
+#ifndef OSA_PRIORITY_BELOW_NORMAL
+#define OSA_PRIORITY_BELOW_NORMAL (4)
+#endif
+
+#ifndef OSA_PRIORITY_NORMAL
+#define OSA_PRIORITY_NORMAL (3)
+#endif
+
+#ifndef OSA_PRIORITY_ABOVE_NORMAL
+#define OSA_PRIORITY_ABOVE_NORMAL (2)
+#endif
+
+#ifndef OSA_PRIORITY_HIGH
+#define OSA_PRIORITY_HIGH (1)
+#endif
+
+#ifndef OSA_PRIORITY_REAL_TIME
+#define OSA_PRIORITY_REAL_TIME (0)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MAX
+#define OSA_TASK_PRIORITY_MAX (0)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MIN
+#define OSA_TASK_PRIORITY_MIN (15)
+#endif
+
+#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t))
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define osaWaitForever_c ((uint32_t)(-1))
+#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF))
+#define osThreadStackArray(name) osThread_##name##_stack
+#define osThreadStackDef(name, stacksize, instances) \
+ uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)];
+
+/* ==== Thread Management ==== */
+
+/* Create a Thread Definition with function, priority, and stack requirements.
+ * \param name name of the thread function.
+ * \param priority initial priority of the thread function.
+ * \param instances number of possible thread instances.
+ * \param stackSz stack size (in bytes) requirements for the thread function.
+ * \param useFloat
+ */
+#if defined(FSL_RTOS_MQX)
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osa_thread_link_t osThreadLink_##name[instances] = {0}; \
+ osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+ (uint8_t *)#name, (useFloat)}
+#elif defined(FSL_RTOS_UCOSII)
+#if gTaskMultipleInstancesManagement_c
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osa_thread_link_t osThreadLink_##name[instances] = {0}; \
+ osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+ (uint8_t *)#name, (useFloat)}
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+ (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)}
+#endif
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \
+ osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \
+ NULL, NULL, (uint8_t *)#name, (useFloat)}
+#endif
+/* Access a Thread defintion.
+ * \param name name of the thread definition object.
+ */
+#define OSA_TASK(name) &os_thread_def_##name
+
+#define OSA_TASK_PROTO(name) externosa_task_def_t os_thread_def_##name
+/* ==== Timer Management ====
+ * Define a Timer object.
+ * \param name name of the timer object.
+ * \param function name of the timer call back function.
+ */
+
+#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL}
+
+/* Access a Timer definition.
+ * \param name name of the timer object.
+ */
+#define OSA_TIMER(name) &os_timer_def_##name
+
+/* ==== Buffer Definition ==== */
+
+/*!
+ * @brief Defines the semaphore handle
+ *
+ * This macro is used to define a 4 byte aligned semaphore handle.
+ * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle.
+ *
+ * The macro should be global and could be optional. You could also define semaphore handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * @endcode
+ *
+ * @param name The name string of the semaphore handle.
+ */
+#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \
+ uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the mutex handle
+ *
+ * This macro is used to define a 4 byte aligned mutex handle.
+ * Then use "(osa_mutex_handle_t)name" to get the mutex handle.
+ *
+ * The macro should be global and could be optional. You could also define mutex handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * @endcode
+ *
+ * @param name The name string of the mutex handle.
+ */
+#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the event handle
+ *
+ * This macro is used to define a 4 byte aligned event handle.
+ * Then use "(osa_event_handle_t)name" to get the event handle.
+ *
+ * The macro should be global and could be optional. You could also define event handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * @endcode
+ *
+ * @param name The name string of the event handle.
+ */
+#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the message queue handle
+ *
+ * This macro is used to define a 4 byte aligned message queue handle.
+ * Then use "(osa_msgq_handle_t)name" to get the message queue handle.
+ *
+ * The macro should be global and could be optional. You could also define message queue handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct));
+ * @endcode
+ *
+ * @param name The name string of the message queue handle.
+ * @param numberOfMsgs Number of messages.
+ * @param msgSize Message size.
+ *
+ */
+
+/*< Macro For FREE_RTOS*/
+#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
+ uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the TASK handle
+ *
+ * This macro is used to define a 4 byte aligned TASK handle.
+ * Then use "(osa_task_handle_t)name" to get the TASK handle.
+ *
+ * The macro should be global and could be optional. You could also define TASK handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * @endcode
+ *
+ * @param name The name string of the TASK handle.
+ */
+#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+#include "fsl_os_abstraction_rtthread.h"
+
+extern const uint8_t gUseRtos_c;
+
+/*
+ * alloc the temporary memory to store the status
+ */
+#define OSA_SR_ALLOC() uint32_t osaCurrentSr;
+/*
+ * Enter critical mode
+ */
+#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr)
+/*
+ * Exit critical mode and retore the previous mode
+ */
+#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param length Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory can't be allocated.
+ */
+void *OSA_MemoryAllocate(uint32_t length);
+
+/*!
+ * @brief Frees the memory previously reserved.
+ *
+ * The function is used to free the memory block previously reserved.
+ *
+ * @param p Pointer to the start of the memory block previously reserved.
+ *
+ */
+void OSA_MemoryFree(void *p);
+
+/*!
+ * @brief Enter critical with nesting mode.
+ *
+ * @param sr Store current status and return to caller.
+ */
+void OSA_EnterCritical(uint32_t *sr);
+
+/*!
+ * @brief Exit critical with nesting mode.
+ *
+ * @param sr Previous status to restore.
+ */
+void OSA_ExitCritical(uint32_t sr);
+
+/*!
+ * @name Task management
+ * @{
+ */
+
+/*!
+ * @brief Creates a task.
+ *
+ * This function is used to create task based on the resources defined
+ * by the macro OSA_TASK_DEFINE.
+ *
+ * Example below shows how to use this API to create the task handle.
+ * @code
+ * OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);
+ * OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL);
+ * @endcode
+ *
+ * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * or
+ * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param thread_def pointer to theosa_task_def_t structure which defines the task.
+ * @param task_param Pointer to be passed to the task when it is created.
+ * @retval KOSA_StatusSuccess The task is successfully created.
+ * @retval KOSA_StatusError The task can not be created.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Gets the handler of active task.
+ *
+ * @return Handler to current active task.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Puts the active task to the end of scheduler's queue.
+ *
+ * When a task calls this function, it gives up the CPU and puts itself to the
+ * end of a task ready list.
+ *
+ * @retval KOSA_StatusSuccess The function is called successfully.
+ * @retval KOSA_StatusError Error occurs with this function.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskYield(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Gets the priority of a task.
+ *
+ * @param taskHandle The handler of the task whose priority is received.
+ *
+ * @return Task's priority.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Sets the priority of a task.
+ *
+ * @param taskHandle The handler of the task whose priority is set.
+ * @param taskPriority The priority to set.
+ *
+ * @retval KOSA_StatusSuccess Task's priority is set successfully.
+ * @retval KOSA_StatusError Task's priority can not be set.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Destroys a previously created task.
+ *
+ * @param taskHandle The handler of the task to destroy.
+ *
+ * @retval KOSA_StatusSuccess The task was successfully destroyed.
+ * @retval KOSA_StatusError Task destruction failed or invalid parameter.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the value to the parameter
+ * initValue.
+ *
+ * Example below shows how to use this API to create the semaphore handle.
+ * @code
+ * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff);
+ * @endcode
+ *
+ * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * or
+ * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param initValue Initial value the semaphore will be set to.
+ *
+ * @retval KOSA_StatusSuccess the new semaphore if the semaphore is created successfully.
+ * @retval KOSA_StatusError if the semaphore can not be created.
+ */
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue);
+
+/*!
+ * @brief Destroys a previously created semaphore.
+ *
+ * @param semaphoreHandle The semaphore handle.
+ * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer,
+ * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully destroyed.
+ * @retval KOSA_StatusError The semaphore can not be destroyed.
+ */
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Pending a semaphore with timeout.
+ *
+ * This function checks the semaphore's counting value. If it is positive,
+ * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used
+ * to wait.
+ *
+ * @param semaphoreHandle The semaphore handle.
+ * @param millisec The maximum number of milliseconds to wait if semaphore is not
+ * positive. Pass osaWaitForever_c to wait indefinitely, pass 0
+ * will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is received.
+ * @retval KOSA_StatusTimeout The semaphore is not received within the specified 'timeout'.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec);
+
+/*!
+ * @brief Signals for someone waiting on the semaphore to wake up.
+ *
+ * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
+ * the semaphore's counting value.
+ *
+ * @param semaphoreHandle The semaphore handle to signal.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully signaled.
+ * @retval KOSA_StatusError The object can not be signaled or invalid parameter.
+ *
+ */
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Create an unlocked mutex.
+ *
+ * This function creates a non-recursive mutex and sets it to unlocked status.
+ *
+ * Example below shows how to use this API to create the mutex handle.
+ * @code
+ * OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * OSA_MutexCreate((osa_mutex_handle_t)mutexHandle);
+ * @endcode
+ *
+ * @param mutexHandle Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * or
+ * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @retval KOSA_StatusSuccess the new mutex if the mutex is created successfully.
+ * @retval KOSA_StatusError if the mutex can not be created.
+ */
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex's status. If it is unlocked, locks it and returns the
+ * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock.
+ *
+ * @param mutexHandle The mutex handle.
+ * @param millisec The maximum number of milliseconds to wait for the mutex.
+ * If the mutex is locked, Pass the value osaWaitForever_c will
+ * wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ * immediately.
+ *
+ * @retval KOSA_StatusSuccess The mutex is locked successfully.
+ * @retval KOSA_StatusTimeout Timeout occurred.
+ * @retval KOSA_StatusError Incorrect parameter was passed.
+ *
+ * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
+ */
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec);
+
+/*!
+ * @brief Unlocks a previously locked mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully unlocked.
+ * @retval KOSA_StatusError The mutex can not be unlocked or invalid parameter.
+ */
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Destroys a previously created mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully destroyed.
+ * @retval KOSA_StatusError The mutex can not be destroyed.
+ *
+ */
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Initializes an event object with all flags cleared.
+ *
+ * This function creates an event object and set its clear mode. If autoClear
+ * is 1, when a task gets the event flags, these flags will be
+ * cleared automatically. Otherwise these flags must
+ * be cleared manually.
+ *
+ * Example below shows how to use this API to create the event handle.
+ * @code
+ * OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * OSA_EventCreate((osa_event_handle_t)eventHandle, 0);
+ * @endcode
+ *
+ * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * or
+ * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param autoClear 1 The event is auto-clear.
+ * 0 The event manual-clear
+ * @retval KOSA_StatusSuccess the new event if the event is created successfully.
+ * @retval KOSA_StatusError if the event can not be created.
+ */
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear);
+
+/*!
+ * @brief Sets one or more event flags.
+ *
+ * Sets specified flags of an event object.
+ *
+ * @param eventHandle The event handle.
+ * @param flagsToSet Flags to be set.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully set.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet);
+
+/*!
+ * @brief Clears one or more flags.
+ *
+ * Clears specified flags of an event object.
+ *
+ * @param eventHandle The event handle.
+ * @param flagsToClear Flags to be clear.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully cleared.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear);
+
+/*!
+ * @brief Get event's flags.
+ *
+ * Get specified flags of an event object.
+ *
+ * @param eventHandle The event handle.
+ * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer,
+ * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used.
+ * @param flagsMask The flags user want to get are specified by this parameter.
+ * @param pFlagsOfEvent The event flags are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The event flags were successfully got.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle,
+ osa_event_flags_t flagsMask,
+ osa_event_flags_t *pFlagsOfEvent);
+
+/*!
+ * @brief Waits for specified event flags to be set.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * Applications can wait for any/all bits to be set. Also this function could
+ * obtain the flags who wakeup the waiting task.
+ *
+ * @param eventHandle The event handle.
+ * @param flagsToWait Flags that to wait.
+ * @param waitAll Wait all flags or any flag to be set.
+ * @param millisec The maximum number of milliseconds to wait for the event.
+ * If the wait condition is not met, pass osaWaitForever_c will
+ * wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ * immediately.
+ * @param pSetFlags Flags that wakeup the waiting task are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The wait condition met and function returns successfully.
+ * @retval KOSA_StatusTimeout Has not met wait condition within timeout.
+ * @retval KOSA_StatusError An incorrect parameter was passed.
+ *
+ * @note Please pay attention to the flags bit width, FreeRTOS uses the most
+ * significant 8 bis as control bits, so do not wait these bits while using
+ * FreeRTOS.
+ *
+ */
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+ osa_event_flags_t flagsToWait,
+ uint8_t waitAll,
+ uint32_t millisec,
+ osa_event_flags_t *pSetFlags);
+
+/*!
+ * @brief Destroys a previously created event object.
+ *
+ * @param eventHandle The event handle.
+ *
+ * @retval KOSA_StatusSuccess The event is successfully destroyed.
+ * @retval KOSA_StatusError Event destruction failed.
+ */
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle);
+
+/*!
+ * @brief Initializes a message queue.
+ *
+ * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
+ *
+ * Example below shows how to use this API to create the massage queue handle.
+ * @code
+ * OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ * OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg));
+ * @endcode
+ *
+ * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel
+ * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ * or
+ * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param msgNo :number of messages the message queue should accommodate.
+ * @param msgSize :size of a single message structure.
+ *
+ * @retval KOSA_StatusSuccess Message queue successfully Create.
+ * @retval KOSA_StatusError Message queue create failure.
+ */
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize);
+
+/*!
+ * @brief Puts a message at the end of the queue.
+ *
+ * This function puts a message to the end of the message queue. If the queue
+ * is full, this function returns the KOSA_StatusError;
+ *
+ * @param msgqHandle Message Queue handler.
+ * @param pMessage Pointer to the message to be put into the queue.
+ *
+ * @retval KOSA_StatusSuccess Message successfully put into the queue.
+ * @retval KOSA_StatusError The queue was full or an invalid parameter was passed.
+ */
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage);
+
+/*!
+ * @brief Reads and remove a message at the head of the queue.
+ *
+ * This function gets a message from the head of the message queue. If the
+ * queue is empty, timeout is used to wait.
+ *
+ * @param msgqHandle Message Queue handler.
+ * @param pMessage Pointer to a memory to save the message.
+ * @param millisec The number of milliseconds to wait for a message. If the
+ * queue is empty, pass osaWaitForever_c will wait indefinitely,
+ * pass 0 will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess Message successfully obtained from the queue.
+ * @retval KOSA_StatusTimeout The queue remains empty after timeout.
+ * @retval KOSA_StatusError Invalid parameter.
+ */
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec);
+
+/*!
+ * @brief Destroys a previously created queue.
+ *
+ * @param msgqHandle Message Queue handler.
+ *
+ * @retval KOSA_StatusSuccess The queue was successfully destroyed.
+ * @retval KOSA_StatusError Message queue destruction failed.
+ */
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle);
+
+/*!
+ * @brief Enable all interrupts.
+ */
+void OSA_InterruptEnable(void);
+
+/*!
+ * @brief Disable all interrupts.
+ */
+void OSA_InterruptDisable(void);
+
+/*!
+ * @brief Enable all interrupts using PRIMASK.
+ */
+void OSA_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable all interrupts using PRIMASK.
+ */
+void OSA_DisableIRQGlobal(void);
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param millisec The time in milliseconds to wait.
+ */
+void OSA_TimeDelay(uint32_t millisec);
+
+/*!
+ * @brief This function gets current time in milliseconds.
+ *
+ * @retval current time in milliseconds
+ */
+uint32_t OSA_TimeGetMsec(void);
+
+/*!
+ * @brief Installs the interrupt handler.
+ *
+ * @param IRQNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ */
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
+
+/*! @}*/
+#ifdef __cplusplus
+}
+#endif
+/*! @}*/
+#endif
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_config.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_config.h
new file mode 100644
index 0000000000..11eec49e7d
--- /dev/null
+++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_config.h
@@ -0,0 +1,36 @@
+/*!
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
+#define _FSL_OS_ABSTRACTION_CONFIG_H_
+
+#ifndef gMainThreadStackSize_c
+#define gMainThreadStackSize_c 1024
+#endif
+
+#ifndef gMainThreadPriority_c
+#define gMainThreadPriority_c 1
+#endif
+
+#ifndef gTaskMultipleInstancesManagement_c
+#define gTaskMultipleInstancesManagement_c 0
+#endif
+
+/*! @brief Definition to determine whether enable OSA's TASK module. */
+#ifndef OSA_USED
+#ifndef FSL_OSA_TASK_ENABLE
+#define FSL_OSA_TASK_ENABLE 0U
+#endif
+#else
+#if defined(FSL_OSA_TASK_ENABLE)
+#undef FSL_OSA_TASK_ENABLE
+#endif
+#define FSL_OSA_TASK_ENABLE 1U
+#endif /* OSA_USED */
+
+#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_rtthread.c b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_rtthread.c
new file mode 100644
index 0000000000..4601d5f7bd
--- /dev/null
+++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_rtthread.c
@@ -0,0 +1,917 @@
+/*! *********************************************************************************
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * This is the source file for the OS Abstraction layer for freertos.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_common.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_os_abstraction_rtthread.h"
+#include
+#include "generic_list.h"
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private macros
+*************************************************************************************
+********************************************************************************** */
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__ICCARM__)
+#define __WEAK_FUNC __weak
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define __WEAK_FUNC __attribute__((weak))
+#endif
+
+#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U)
+
+#ifdef DEBUG_ASSERT
+#define OS_ASSERT(condition) \
+ if (!(condition)) \
+ while (1) \
+ ;
+#else
+#define OS_ASSERT(condition) (void)(condition);
+#endif
+
+/*! @brief Converts milliseconds to ticks*/
+#define MSEC_TO_TICK(msec) \
+ (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL)
+#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ))
+/************************************************************************************
+*************************************************************************************
+* Private type definitions
+*************************************************************************************
+************************************************************************************/
+typedef struct osa_freertos_task
+{
+ list_element_t link;
+ rt_thread_t taskHandle;
+} osa_freertos_task_t;
+
+typedef struct _osa_event_struct
+{
+ rt_event_t handle; /* The event handle */
+ uint8_t autoClear; /*!< Auto clear or manual clear */
+} osa_event_struct_t;
+
+/*! @brief State structure for bm osa manager. */
+typedef struct _osa_state
+{
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+ list_label_t taskList;
+ OSA_TASK_HANDLE_DEFINE(mainTaskHandle);
+#endif
+ uint32_t basePriority;
+ int32_t basePriorityNesting;
+ uint32_t interruptDisableCount;
+} osa_state_t;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private prototypes
+*************************************************************************************
+********************************************************************************** */
+__WEAK_FUNC void main_task(void const *argument);
+__WEAK_FUNC void main_task(void const *argument)
+{
+}
+
+void startup_task(void *argument);
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public memory declarations
+*************************************************************************************
+********************************************************************************** */
+const uint8_t gUseRtos_c = USE_RTOS; // USE_RTOS = 0 for BareMetal and 1 for OS
+
+static osa_state_t s_osaState = {0};
+/*! *********************************************************************************
+*************************************************************************************
+* Private memory declarations
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryAllocate
+ * Description : Reserves the requested amount of memory in bytes.
+ *
+ *END**************************************************************************/
+void *OSA_MemoryAllocate(uint32_t length)
+{
+ void *p = rt_malloc(length);
+
+ if (RT_NULL != p)
+ {
+ rt_memset(p, 0, length);
+ }
+
+ return p;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryFree
+ * Description : Frees the memory previously reserved.
+ *
+ *END**************************************************************************/
+void OSA_MemoryFree(void *p)
+{
+ rt_free(p);
+}
+
+void OSA_EnterCritical(uint32_t *sr)
+{
+ if (rt_thread_self() != RT_NULL)
+ rt_enter_critical();
+}
+
+void OSA_ExitCritical(uint32_t sr)
+{
+ if (rt_thread_self() != RT_NULL)
+ rt_exit_critical();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : startup_task
+ * Description : Wrapper over main_task..
+ *
+ *END**************************************************************************/
+void startup_task(void *argument)
+{
+ main_task(argument);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetCurrentHandle
+ * Description : This function is used to get current active task's handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void)
+{
+ list_element_handle_t list_element;
+ osa_freertos_task_t *ptask;
+
+ list_element = LIST_GetHead(&s_osaState.taskList);
+ while (NULL != list_element)
+ {
+ ptask = (osa_freertos_task_t *)(void *)list_element;
+ if (ptask->taskHandle == xTaskGetCurrentTaskHandle())
+ {
+ return (osa_task_handle_t)ptask;
+ }
+ list_element = LIST_GetNext(list_element);
+ }
+ return NULL;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskYield
+ * Description : When a task calls this function, it will give up CPU and put
+ * itself to the tail of ready list.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskYield(void)
+{
+ taskYIELD();
+ return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetPriority
+ * Description : This function returns task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle)
+{
+ assert(taskHandle);
+ osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+ return (osa_task_priority_t)(PRIORITY_RTOS_TO_OSA(uxTaskPriorityGet(ptask->taskHandle)));
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskSetPriority
+ * Description : This function sets task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority)
+{
+ assert(taskHandle);
+ osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+ vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(taskPriority));
+ return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskCreate
+ * Description : This function is used to create a task and make it ready.
+ * Param[in] : threadDef - Definition of the thread.
+ * task_param - Parameter to pass to the new thread.
+ * Return Thread handle of the new thread, or NULL if failed.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param)
+{
+ assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE);
+ assert(taskHandle);
+ TaskHandle_t pxCreatedTask;
+ osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+
+ if (xTaskCreate((TaskFunction_t)thread_def->pthread, /* pointer to the task */
+ (char const *)thread_def->tname, /* task name for kernel awareness debugging */
+ (configSTACK_DEPTH_TYPE)thread_def->stacksize / sizeof(portSTACK_TYPE), /* task stack size */
+ (task_param_t)task_param, /* optional task startup argument */
+ PRIORITY_OSA_TO_RTOS(thread_def->tpriority), /* initial priority */
+ &pxCreatedTask /* optional task handle to create */
+ ) == pdPASS)
+ {
+ ptask->taskHandle = pxCreatedTask;
+ OSA_InterruptDisable();
+ (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link));
+ OSA_InterruptEnable();
+ return KOSA_StatusSuccess;
+ }
+ return KOSA_StatusError;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskDestroy
+ * Description : This function destroy a task.
+ * Param[in] :taskHandle - Thread handle.
+ * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle)
+{
+ assert(taskHandle);
+ osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+ osa_status_t status;
+ uint16_t oldPriority;
+ /*Change priority to avoid context switches*/
+ oldPriority = OSA_TaskGetPriority(OSA_TaskGetCurrentHandle());
+ (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), OSA_PRIORITY_REAL_TIME);
+#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */
+ vTaskDelete((task_handler_t)ptask->taskHandle);
+ status = KOSA_StatusSuccess;
+#else
+ status = KOSA_StatusError; /* vTaskDelete() not available */
+#endif
+ (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), oldPriority);
+ OSA_InterruptDisable();
+ (void)LIST_RemoveElement(taskHandle);
+ OSA_InterruptEnable();
+ return status;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDelay
+ * Description : This function is used to suspend the active thread for the given number of milliseconds.
+ *
+ *END**************************************************************************/
+void OSA_TimeDelay(uint32_t millisec)
+{
+ rt_thread_mdelay(millisec);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeGetMsec
+ * Description : This function gets current time in milliseconds.
+ *
+ *END**************************************************************************/
+uint32_t OSA_TimeGetMsec(void)
+{
+ return rt_tick_get_millisecond();
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreCreate
+ * Description : This function is used to create a semaphore.
+ * Return : Semaphore handle of the new semaphore, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue)
+{
+ assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE);
+ assert(semaphoreHandle);
+
+ union
+ {
+ rt_sem_t sem;
+ uint32_t semhandle;
+ } xSemaHandle;
+
+ xSemaHandle.sem = rt_sem_create("osa_sem", initValue, RT_IPC_FLAG_PRIO);
+ if (NULL != xSemaHandle.sem)
+ {
+ *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle;
+ return KOSA_StatusSuccess;
+ }
+ return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreDestroy
+ * Description : This function is used to destroy a semaphore.
+ * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle)
+{
+ assert(semaphoreHandle);
+ rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+ rt_sem_delete(sem);
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreWait
+ * Description : This function checks the semaphore's counting value, if it is
+ * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout
+ * will be used for wait. The parameter timeout indicates how long should wait
+ * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will
+ * return KOSA_StatusTimeout immediately if semaphore is not positive.
+ * This function returns KOSA_StatusSuccess if the semaphore is received, returns
+ * KOSA_StatusTimeout if the semaphore is not received within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec)
+{
+ uint32_t timeoutTicks;
+ assert(semaphoreHandle);
+ rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+ /* Convert timeout from millisecond to tick. */
+ if (millisec == osaWaitForever_c)
+ {
+ timeoutTicks = RT_WAITING_FOREVER;
+ }
+ else
+ {
+ timeoutTicks = rt_tick_from_millisecond(millisec);
+ }
+
+ if (RT_EOK != rt_sem_take(sem, timeoutTicks))
+ {
+ return KOSA_StatusTimeout; /* timeout */
+ }
+ else
+ {
+ return KOSA_StatusSuccess; /* semaphore taken */
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphorePost
+ * Description : This function is used to wake up one task that wating on the
+ * semaphore. If no task is waiting, increase the semaphore. The function returns
+ * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns
+ * KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle)
+{
+ assert(semaphoreHandle);
+ rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+ rt_sem_release(sem);
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexCreate
+ * Description : This function is used to create a mutex.
+ * Return : Mutex handle of the new mutex, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle)
+{
+ assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE);
+ assert(mutexHandle);
+
+ union
+ {
+ rt_mutex_t mutex;
+ uint32_t pmutexHandle;
+ } xMutexHandle;
+
+ xMutexHandle.mutex = rt_mutex_create("osa_mutex", RT_IPC_FLAG_PRIO);
+ if (RT_NULL != xMutexHandle.mutex)
+ {
+ *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle;
+ return KOSA_StatusSuccess;
+ }
+ return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexLock
+ * Description : This function checks the mutex's status, if it is unlocked,
+ * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex.
+ * This function returns KOSA_StatusSuccess if the mutex is obtained, returns
+ * KOSA_StatusError if any errors occur during waiting. If the mutex has been
+ * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec)
+{
+ assert(mutexHandle);
+ uint32_t timeoutTicks;
+ rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+ /* Convert timeout from millisecond to tick. */
+ if (millisec == osaWaitForever_c)
+ {
+ timeoutTicks = RT_WAITING_FOREVER;
+ }
+ else
+ {
+ timeoutTicks = rt_tick_from_millisecond(millisec);
+ }
+
+ if (RT_EOK != rt_mutex_take(mutex, timeoutTicks))
+ {
+ return KOSA_StatusTimeout; /* timeout */
+ }
+ else
+ {
+ return KOSA_StatusSuccess; /* semaphore taken */
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexUnlock
+ * Description : This function is used to unlock a mutex.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle)
+{
+ assert(mutexHandle);
+ rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+ rt_mutex_release(mutex);
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexDestroy
+ * Description : This function is used to destroy a mutex.
+ * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle)
+{
+ assert(mutexHandle);
+ rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+ rt_mutex_delete(mutex);
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventCreate
+ * Description : This function is used to create a event object.
+ * Return : Event handle of the new event, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear)
+{
+ assert(eventHandle);
+ osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+ pEventStruct->handle = rt_event_create("osa_event", RT_IPC_FLAG_PRIO);
+ if (RT_NULL != pEventStruct->handle)
+ {
+ pEventStruct->autoClear = autoClear;
+ }
+ else
+ {
+ return KOSA_StatusError;
+ }
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventSet
+ * Description : Set one or more event flags of an event object.
+ * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet)
+{
+ rt_err_t result;
+ assert(eventHandle);
+ osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+ if (RT_NULL == pEventStruct->handle)
+ {
+ return KOSA_StatusError;
+ }
+
+ rt_event_send(pEventStruct->handle, (rt_uint32_t)flagsToSet);
+
+ (void)result;
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventClear
+ * Description : Clear one or more event flags of an event object.
+ * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear)
+{
+ assert(eventHandle);
+ osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+ if (RT_NULL == pEventStruct->handle)
+ {
+ return KOSA_StatusError;
+ }
+
+ rt_uint32_t recved;
+ rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToClear, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, 0, &recved);
+
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventGet
+ * Description : This function is used to get event's flags that specified by prameter
+ * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So
+ * you should pass the parameter 0xffffffff to specify you want to check all.
+ * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent)
+{
+ assert(eventHandle);
+ osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+ rt_uint32_t eventFlags;
+
+ if (RT_NULL == pEventStruct->handle)
+ {
+ return KOSA_StatusError;
+ }
+
+ if (RT_NULL == pFlagsOfEvent)
+ {
+ return KOSA_StatusError;
+ }
+
+ if (RT_EOK != rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsMask, RT_EVENT_FLAG_OR, 0, &eventFlags))
+ {
+ eventFlags = 0;
+ }
+
+ *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask;
+
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventWait
+ * Description : This function checks the event's status, if it meets the wait
+ * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value
+ * KOSA_StatusTimeout immediately if wait condition is not met. The event flags
+ * will be cleared if the event is auto clear mode. Flags that wakeup waiting
+ * task could be obtained from the parameter setFlags.
+ * This function returns KOSA_StatusSuccess if wait condition is met, returns
+ * KOSA_StatusTimeout if wait condition is not met within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+ osa_event_flags_t flagsToWait,
+ uint8_t waitAll,
+ uint32_t millisec,
+ osa_event_flags_t *pSetFlags)
+{
+ assert(eventHandle);
+ rt_uint8_t option = 0;
+ rt_uint32_t timeoutTicks;
+ rt_uint32_t flagsSave;
+ osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+ /* Clean FreeRTOS cotrol flags */
+ flagsToWait = flagsToWait & 0x00FFFFFFU;
+ if (RT_NULL == pEventStruct->handle)
+ {
+ return KOSA_StatusError;
+ }
+
+ /* Convert timeout from millisecond to tick. */
+ if (millisec == osaWaitForever_c)
+ {
+ timeoutTicks = RT_WAITING_FOREVER;
+ }
+ else
+ {
+ timeoutTicks = rt_tick_from_millisecond(millisec);
+ }
+
+ if (pEventStruct->autoClear != 0U)
+ {
+ option |= RT_EVENT_FLAG_CLEAR;
+ }
+ option |= waitAll ? RT_EVENT_FLAG_AND : RT_EVENT_FLAG_OR;
+
+ rt_err_t status = rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToWait, option, timeoutTicks, &flagsSave);
+
+ flagsSave &= (rt_uint32_t)flagsToWait;
+ if (RT_NULL != pSetFlags)
+ {
+ *pSetFlags = (osa_event_flags_t)flagsSave;
+ }
+
+ if (RT_EOK != status)
+ {
+ return KOSA_StatusTimeout;
+ }
+ else
+ {
+ return KOSA_StatusSuccess;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventDestroy
+ * Description : This function is used to destroy a event object. Return
+ * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise
+ * return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle)
+{
+ assert(eventHandle);
+ osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+ if (RT_NULL == pEventStruct->handle)
+ {
+ return KOSA_StatusError;
+ }
+ rt_event_delete(pEventStruct->handle);
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQCreate
+ * Description : This function is used to create a message queue.
+ * Return : the handle to the message queue if create successfully, otherwise
+ * return NULL.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize)
+{
+ assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE);
+ assert(msgqHandle);
+
+ union
+ {
+ rt_mq_t msgq;
+ uint32_t pmsgqHandle;
+ } xMsgqHandle;
+
+ /* Create the message queue where the number and size is specified by msgNo and msgSize */
+ xMsgqHandle.msgq = rt_mq_create("osa_mq", msgSize, msgNo, RT_IPC_FLAG_PRIO);
+ if (RT_NULL != xMsgqHandle.msgq)
+ {
+ *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle;
+ return KOSA_StatusSuccess;
+ }
+ return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQPut
+ * Description : This function is used to put a message to a message queue.
+ * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage)
+{
+ assert(msgqHandle);
+ rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+ if (RT_EOK == rt_mq_send(handler, pMessage, handler->msg_size))
+ {
+ return KOSA_StatusSuccess;
+ }
+ else
+ {
+ return KOSA_StatusError;
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQGet
+ * Description : This function checks the queue's status, if it is not empty,
+ * get message from it and return KOSA_StatusSuccess, otherwise, timeout will
+ * be used for wait. The parameter timeout indicates how long should wait in
+ * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return
+ * KOSA_StatusTimeout immediately if queue is empty.
+ * This function returns KOSA_StatusSuccess if message is got successfully,
+ * returns KOSA_StatusTimeout if message queue is empty within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec)
+{
+ osa_status_t osaStatus;
+ assert(msgqHandle);
+ rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+ uint32_t timeoutTicks;
+
+ if (millisec == osaWaitForever_c)
+ {
+ timeoutTicks = RT_WAITING_FOREVER;
+ }
+ else
+ {
+ timeoutTicks = rt_tick_from_millisecond(millisec);
+ }
+ if (RT_EOK != rt_mq_recv(handler, pMessage, handler->msg_size, timeoutTicks))
+ {
+ osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */
+ }
+ else
+ {
+ osaStatus = KOSA_StatusSuccess;
+ }
+ return osaStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQDestroy
+ * Description : This function is used to destroy the message queue.
+ * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle)
+{
+ assert(msgqHandle);
+ rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+ rt_mq_delete(handler);
+ return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptEnable
+ * Description : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptEnable(void)
+{
+ rt_exit_critical();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptDisable
+ * Description : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptDisable(void)
+{
+ rt_enter_critical();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnableIRQGlobal
+ * Description : enable interrupts using PRIMASK register.
+ *
+ *END**************************************************************************/
+void OSA_EnableIRQGlobal(void)
+{
+ if (s_osaState.interruptDisableCount > 0U)
+ {
+ s_osaState.interruptDisableCount--;
+
+ if (0U == s_osaState.interruptDisableCount)
+ {
+ __enable_irq();
+ }
+ /* call core API to enable the global interrupt*/
+ }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_DisableIRQGlobal
+ * Description : disable interrupts using PRIMASK register.
+ *
+ *END**************************************************************************/
+void OSA_DisableIRQGlobal(void)
+{
+ /* call core API to disable the global interrupt*/
+ __disable_irq();
+
+ /* update counter*/
+ s_osaState.interruptDisableCount++;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InstallIntHandler
+ * Description : This function is used to install interrupt handler.
+ *
+ *END**************************************************************************/
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void))
+{
+#if defined(__IAR_SYSTEMS_ICC__)
+ _Pragma("diag_suppress = Pm138")
+#endif
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+ (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#if defined(__IAR_SYSTEMS_ICC__)
+ _Pragma("diag_remark = PM138")
+#endif
+}
+
+/*!*********************************************************************************
+*************************************************************************************
+* Private functions
+*************************************************************************************
+********************************************************************************** */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+
+static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0);
+
+int main(void)
+{
+ extern void BOARD_InitHardware(void);
+ /* Initialize MCU clock */
+ BOARD_InitHardware();
+ LIST_Init((&s_osaState.taskList), 0);
+
+ s_osaState.basePriorityNesting = 0;
+ s_osaState.interruptDisableCount = 0;
+ (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(startup_task), NULL);
+
+ vTaskStartScheduler();
+ return 0;
+}
+#endif /* FSL_OSA_TASK_ENABLE */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_rtthread.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_rtthread.h
new file mode 100644
index 0000000000..0e0423753f
--- /dev/null
+++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_os_abstraction_rtthread.h
@@ -0,0 +1,130 @@
+/*! *********************************************************************************
+ * Copyright (c) 2013-2014, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * ile
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ********************************************************************************** */
+#if !defined(__FSL_OS_ABSTRACTION_RTTHREAD_H__)
+#define __FSL_OS_ABSTRACTION_RTTHREAD_H__
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ */
+// http://supp.iar.com/Support/?note=24725
+
+#define MISRAC_DISABLE \
+ _Pragma( \
+ "diag_suppress= \
+ Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+ Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+ Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+ Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+ Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+ Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+ Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+ Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+ Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+ Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+ Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+ Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+ Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+ Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+ Pm155")
+
+#define MISRAC_ENABLE \
+ _Pragma( \
+ "diag_default= \
+ Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+ Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+ Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+ Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+ Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+ Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+ Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+ Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+ Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+ Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+ Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+ Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+ Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+ Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+ Pm155")
+#else
+/* Empty MISRA C macros for other toolchains. */
+#define MISRAC_DISABLE
+#define MISRAC_ENABLE
+#endif
+
+MISRAC_DISABLE
+#include
+MISRAC_ENABLE
+
+/*!
+ * @addtogroup os_abstraction_free_rtos
+ * @{
+ */
+
+/*******************************************************************************
+ * Declarations
+ ******************************************************************************/
+/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
+typedef rt_thread_t task_handler_t;
+
+/*! @brief Type for a task stack.*/
+typedef rt_uint32_t task_stack_t;
+
+/*! @brief Type for task parameter */
+typedef void *task_param_t;
+
+/*! @brief Type for an event flags object.*/
+typedef rt_uint32_t event_flags_t;
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define OSA_WAIT_FOREVER 0xFFFFFFFFU
+
+/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
+#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
+
+/*! @brief The default interrupt handler installed in vector table. */
+#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
+
+extern void DefaultISR(void);
+
+/*!
+ * @name Thread management
+ * @{
+ */
+
+/*!
+ * @brief To provide unified task piority for upper layer, OSA layer makes conversion.
+ */
+#define PRIORITY_OSA_TO_RTOS(osa_prio) ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U)
+#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U)
+
+/* @}*/
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief This macro statically reserves the memory required for the queue.
+ *
+ * @param name Identifier for the memory region.
+ * @param number Number of elements in the queue.
+ * @param size Size of every elements in words.
+ */
+#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL
+
+/* @}*/
+
+/*! @}*/
+/*! @}*/
+/*! @}*/
+
+#endif // __FSL_OS_ABSTRACTION_RTTHREAD_H__
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/generic_list.c b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/generic_list.c
new file mode 100644
index 0000000000..4c0984f503
--- /dev/null
+++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/generic_list.c
@@ -0,0 +1,475 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "generic_list.h"
+
+static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
+{
+ list_status_t listStatus = kLIST_Ok;
+ list_element_handle_t element = list->head;
+
+ if ((list->max != 0U) && (list->max == list->size))
+ {
+ listStatus = kLIST_Full; /*List is full*/
+ }
+ else
+ {
+ while (element != NULL) /*Scan list*/
+ {
+ /* Determine if element is duplicated */
+ if (element == newElement)
+ {
+ listStatus = kLIST_DuplicateError;
+ break;
+ }
+ element = element->next;
+ }
+ }
+
+ return listStatus;
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+ * \brief Initialises the list descriptor.
+ *
+ * \param[in] list - LIST_ handle to init.
+ * max - Maximum number of elements in list. 0 for unlimited.
+ *
+ * \return void.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+void LIST_Init(list_handle_t list, uint32_t max)
+{
+ list->head = NULL;
+ list->tail = NULL;
+ list->max = (uint16_t)max;
+ list->size = 0;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the list that contains the given element.
+ *
+ * \param[in] element - Handle of the element.
+ *
+ * \return NULL if element is orphan.
+ * Handle of the list the element is inserted into.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_handle_t LIST_GetList(list_element_handle_t element)
+{
+ return element->list;
+}
+
+/*! *********************************************************************************
+ * \brief Links element to the tail of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ * element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+ list_status_t listStatus = kLIST_Ok;
+
+ listStatus = LIST_Error_Check(list, element);
+ if (listStatus == kLIST_Ok) /* Avoiding list status error */
+ {
+ if (list->size == 0U)
+ {
+ list->head = element;
+ }
+ else
+ {
+ list->tail->next = element;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+ element->prev = list->tail;
+#endif
+ element->list = list;
+ element->next = NULL;
+ list->tail = element;
+ list->size++;
+ }
+
+ EnableGlobalIRQ(regPrimask);
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Links element to the head of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ * element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+ list_status_t listStatus = kLIST_Ok;
+
+ listStatus = LIST_Error_Check(list, element);
+ if (listStatus == kLIST_Ok) /* Avoiding list status error */
+ {
+ /* Links element to the head of the list */
+ if (list->size == 0U)
+ {
+ list->tail = element;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+ else
+ {
+ list->head->prev = element;
+ }
+ element->prev = NULL;
+#endif
+ element->list = list;
+ element->next = list->head;
+ list->head = element;
+ list->size++;
+ }
+
+ EnableGlobalIRQ(regPrimask);
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Unlinks element from the head of the list.
+ *
+ * \param[in] list - ID of list to remove from.
+ *
+ * \return NULL if list is empty.
+ * ID of removed element(pointer) if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_RemoveHead(list_handle_t list)
+{
+ list_element_handle_t element;
+
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if ((NULL == list) || (list->size == 0U))
+ {
+ element = NULL; /*LIST_ is empty*/
+ }
+ else
+ {
+ element = list->head;
+ list->size--;
+ if (list->size == 0U)
+ {
+ list->tail = NULL;
+ }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+ else
+ {
+ element->next->prev = NULL;
+ }
+#endif
+ element->list = NULL;
+ list->head = element->next; /*Is NULL if element is head*/
+ }
+
+ EnableGlobalIRQ(regPrimask);
+ return element;
+}
+
+/*! *********************************************************************************
+ * \brief Gets head element ID.
+ *
+ * \param[in] list - ID of list.
+ *
+ * \return NULL if list is empty.
+ * ID of head element if list is not empty.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetHead(list_handle_t list)
+{
+ return list->head;
+}
+
+/*! *********************************************************************************
+ * \brief Gets next element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is tail.
+ * ID of next element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetNext(list_element_handle_t element)
+{
+ return element->next;
+}
+
+/*! *********************************************************************************
+ * \brief Gets previous element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is head.
+ * ID of previous element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)
+{
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ return NULL;
+#else
+ return element->prev;
+#endif
+}
+
+/*! *********************************************************************************
+ * \brief Unlinks an element from its list.
+ *
+ * \param[in] element - ID of the element to remove.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ * kLIST_Ok if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_RemoveElement(list_element_handle_t element)
+{
+ list_status_t listStatus = kLIST_Ok;
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if (element->list == NULL)
+ {
+ listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+ }
+ else
+ {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ list_element_handle_t element_list = element->list->head;
+ while (element_list)
+ {
+ if (element->list->head == element)
+ {
+ element->list->head = element_list->next;
+ break;
+ }
+ if (element_list->next == element)
+ {
+ element_list->next = element->next;
+ break;
+ }
+ element_list = element_list->next;
+ }
+#else
+ if (element->prev == NULL) /*Element is head or solo*/
+ {
+ element->list->head = element->next; /*is null if solo*/
+ }
+ if (element->next == NULL) /*Element is tail or solo*/
+ {
+ element->list->tail = element->prev; /*is null if solo*/
+ }
+ if (element->prev != NULL) /*Element is not head*/
+ {
+ element->prev->next = element->next;
+ }
+ if (element->next != NULL) /*Element is not tail*/
+ {
+ element->next->prev = element->prev;
+ }
+#endif
+ element->list->size--;
+ element->list = NULL;
+ }
+
+ EnableGlobalIRQ(regPrimask);
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Links an element in the previous position relative to a given member
+ * of a list.
+ *
+ * \param[in] element - ID of a member of a list.
+ * newElement - new element to insert before the given member.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ * kLIST_Full if list is full.
+ * kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)
+{
+ list_status_t listStatus = kLIST_Ok;
+ uint32_t regPrimask = DisableGlobalIRQ();
+
+ if (element->list == NULL)
+ {
+ listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+ }
+ else
+ {
+ listStatus = LIST_Error_Check(element->list, newElement);
+ if (listStatus == kLIST_Ok)
+ {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+ list_element_handle_t element_list = element->list->head;
+ while (element_list)
+ {
+ if ((element_list->next == element) || (element_list == element))
+ {
+ if (element_list == element)
+ {
+ element->list->head = newElement;
+ }
+ else
+ {
+ element_list->next = newElement;
+ }
+ newElement->list = element->list;
+ newElement->next = element;
+ element->list->size++;
+ break;
+ }
+ element_list = element_list->next;
+ }
+
+#else
+ if (element->prev == NULL) /*Element is list head*/
+ {
+ element->list->head = newElement;
+ }
+ else
+ {
+ element->prev->next = newElement;
+ }
+ newElement->list = element->list;
+ element->list->size++;
+ newElement->next = element;
+ newElement->prev = element->prev;
+ element->prev = newElement;
+#endif
+ }
+ }
+
+ EnableGlobalIRQ(regPrimask);
+ return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the current size of a list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Current size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetSize(list_handle_t list)
+{
+ return list->size;
+}
+
+/*! *********************************************************************************
+ * \brief Gets the number of free places in the list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Available size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetAvailableSize(list_handle_t list)
+{
+ return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/
+}
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/generic_list.h b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/generic_list.h
new file mode 100644
index 0000000000..0da10d338d
--- /dev/null
+++ b/bsp/imxrt/libraries/MIMXRT1050/MIMXRT1052/drivers/generic_list.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _GENERIC_LIST_H_
+#define _GENERIC_LIST_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup GenericList
+ * @{
+ */
+
+/*!*********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public macro definitions
+*************************************************************************************
+********************************************************************************** */
+#ifndef GENERIC_LIST_LIGHT
+#define GENERIC_LIST_LIGHT (0)
+#endif
+/*! *********************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+********************************************************************************** */
+/*! @brief The list status */
+typedef enum _list_status
+{
+ kLIST_Ok = kStatus_Success, /*!< Success */
+ kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
+ kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
+ kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
+ kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
+ kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */
+} list_status_t;
+
+/*! @brief The list structure*/
+typedef struct list_label
+{
+ struct list_element_tag *head; /*!< list head */
+ struct list_element_tag *tail; /*!< list tail */
+ uint16_t size; /*!< list size */
+ uint16_t max; /*!< list max number of elements */
+} list_label_t, *list_handle_t;
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+ struct list_element_tag *next; /*!< next list element */
+ struct list_label *list; /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#else
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+ struct list_element_tag *next; /*!< next list element */
+ struct list_element_tag *prev; /*!< previous list element */
+ struct list_label *list; /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#endif
+/*! *********************************************************************************
+*************************************************************************************
+* Public prototypes
+*************************************************************************************
+********************************************************************************** */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+/*!
+ * @brief Initialize the list.
+ *
+ * This function initialize the list.
+ *
+ * @param list - List handle to initialize.
+ * @param max - Maximum number of elements in list. 0 for unlimited.
+ */
+void LIST_Init(list_handle_t list, uint32_t max);
+
+/*!
+ * @brief Gets the list that contains the given element.
+ *
+ *
+ * @param element - Handle of the element.
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.
+ */
+list_handle_t LIST_GetList(list_element_handle_t element);
+
+/*!
+ * @brief Links element to the head of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Links element to the tail of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Unlinks element from the head of the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_RemoveHead(list_handle_t list);
+
+/*!
+ * @brief Gets head element handle.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetHead(list_handle_t list);
+
+/*!
+ * @brief Gets next element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetNext(list_element_handle_t element);
+
+/*!
+ * @brief Gets previous element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);
+
+/*!
+ * @brief Unlinks an element from its list.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_RemoveElement(list_element_handle_t element);
+
+/*!
+ * @brief Links an element in the previous position relative to a given member of a list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @param newElement - New element to insert before the given member.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);
+
+/*!
+ * @brief Gets the current size of a list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Current size of the list.
+ */
+uint32_t LIST_GetSize(list_handle_t list);
+
+/*!
+ * @brief Gets the number of free places in the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Available size of the list.
+ */
+uint32_t LIST_GetAvailableSize(list_handle_t list);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /*_GENERIC_LIST_H_*/
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/MIMXRT1050/SConscript b/bsp/imxrt/libraries/MIMXRT1050/SConscript
index 75fde95bc1..58a2922fe1 100644
--- a/bsp/imxrt/libraries/MIMXRT1050/SConscript
+++ b/bsp/imxrt/libraries/MIMXRT1050/SConscript
@@ -75,6 +75,17 @@ if GetDepend(['BSP_USING_DMA']):
src += ['MIMXRT1052/drivers/fsl_lpuart_edma.c']
if GetDepend(['BSP_USING_SPI']):
src += ['MIMXRT1052/drivers/fsl_lpspi_edma.c']
+
+if GetDepend(['BSP_USING_PULSE_ENCODER']):
+ src += ['MIMXRT1052/drivers/fsl_enc.c']
+
+#Adding this as XBAR is used in pin mux
+src += ['MIMXRT1052/drivers/fsl_xbara.c']
+src += ['MIMXRT1052/drivers/fsl_xbarb.c']
+
+#fsl os abstract files
+src += ['MIMXRT1052/drivers/fsl_os_abstraction_rtthread.c']
+src += ['MIMXRT1052/drivers/generic_list.c']
if rtconfig.CROSS_TOOL == 'gcc':
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS')
diff --git a/bsp/imxrt/libraries/drivers/SConscript b/bsp/imxrt/libraries/drivers/SConscript
index 3328d2af08..e166989a24 100644
--- a/bsp/imxrt/libraries/drivers/SConscript
+++ b/bsp/imxrt/libraries/drivers/SConscript
@@ -59,10 +59,17 @@ if GetDepend('BSP_USING_USB_DEVICE'):
src += ['drv_usbd.c']
src += Glob('usb/device/*.c')
-if GetDepend('BSP_USING_USB_DEVICE'):
+if GetDepend('BSP_USING_USB_DEVICE') or GetDepend('RT_USING_USB_HOST'):
src += Glob('usb/phy/*.c')
- CPPDEFINES += ['ENDIANNESS']
+ CPPDEFINES += ['ENDIANNESS','USE_RTOS']
+if GetDepend('RT_USING_USB_HOST'):
+ src += ['drv_usbh.c']
+ src += Glob('usb/host/*.c')
+
+if GetDepend('BSP_USING_PULSE_ENCODER'):
+ src += ['drv_pulse_encoder.c']
+
path = [cwd,cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES)
diff --git a/bsp/imxrt/libraries/drivers/drv_can.c b/bsp/imxrt/libraries/drivers/drv_can.c
index 829060e2d7..377e36bcc7 100644
--- a/bsp/imxrt/libraries/drivers/drv_can.c
+++ b/bsp/imxrt/libraries/drivers/drv_can.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -375,7 +375,7 @@ static int can_send(struct rt_can_device *can_dev, const void *buf, rt_uint32_t
ret = RT_EBUSY;
break;
}
-
+
return ret;
}
diff --git a/bsp/imxrt/libraries/drivers/drv_can.h b/bsp/imxrt/libraries/drivers/drv_can.h
index d5d2b13f2e..1ea524e98c 100644
--- a/bsp/imxrt/libraries/drivers/drv_can.h
+++ b/bsp/imxrt/libraries/drivers/drv_can.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -7,7 +7,7 @@
* Date Author Notes
* 2019-06-28 misonyo the first version.
*/
-
+
#ifndef DRV_CAN_H__
#define DRV_CAN_H__
diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c
index ecff2bb6ab..35de385658 100644
--- a/bsp/imxrt/libraries/drivers/drv_eth.c
+++ b/bsp/imxrt/libraries/drivers/drv_eth.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -329,7 +329,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
pbuf_copy_partial((const struct pbuf *)data, (void *)address, length, 0);
-
+
/* Set data length. */
curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -434,7 +434,7 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui
address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
-#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
+#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/* Active the transmit buffer descriptor. */
_ENET_ActiveSend(base, 0);
@@ -454,8 +454,8 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui
/* transmit packet. */
rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
{
- rt_err_t result = RT_EOK;
- enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
+ rt_err_t result = RT_EOK;
+ enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
RT_ASSERT(p != NULL);
RT_ASSERT(enet_handle != RT_NULL);
diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.c b/bsp/imxrt/libraries/drivers/drv_gpio.c
index a2e9dda3d7..3e27a1e9c3 100644
--- a/bsp/imxrt/libraries/drivers/drv_gpio.c
+++ b/bsp/imxrt/libraries/drivers/drv_gpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -70,7 +70,7 @@ const struct pin_mask mask_tab[5] =
#endif
};
-const rt_int8_t reg_offset[] =
+const rt_int8_t reg_offset[] =
{
#if defined(SOC_IMXRT1015_SERIES)
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 64, 65, 66, 67, 68, 69,
diff --git a/bsp/imxrt/libraries/drivers/drv_gpio.h b/bsp/imxrt/libraries/drivers/drv_gpio.h
index cf1a80ffbb..c2de77d933 100644
--- a/bsp/imxrt/libraries/drivers/drv_gpio.h
+++ b/bsp/imxrt/libraries/drivers/drv_gpio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -7,12 +7,12 @@
* Date Author Notes
* 2018-4-30 misonyo the first version.
*/
-
+
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
-#include
-#include
+#include
+#include
#define GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */
diff --git a/bsp/imxrt/libraries/drivers/drv_i2c.c b/bsp/imxrt/libraries/drivers/drv_i2c.c
index 1920c0d502..c2a8ec321b 100644
--- a/bsp/imxrt/libraries/drivers/drv_i2c.c
+++ b/bsp/imxrt/libraries/drivers/drv_i2c.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,7 +18,7 @@
#define LOG_TAG "drv.i2c"
#include
-#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
+#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) && !defined(BSP_USING_I2C5)&& !defined(BSP_USING_I2C6)
#error "Please define at least one BSP_USING_I2Cx"
#endif
@@ -35,6 +35,9 @@ struct imxrt_i2c_bus
volatile rt_uint32_t msg_ptr;
volatile rt_uint32_t dptr;
char *device_name;
+#ifdef SOC_IMXRT1170_SERIES
+ clock_root_t clock_root;
+#endif
};
#if defined (BSP_USING_I2C1)
@@ -55,13 +58,28 @@ struct imxrt_i2c_bus
#define I2C4BUS_NAME "i2c4"
#endif /*BSP_USING_I2C4*/
+#if defined (BSP_USING_I2C5)
+#define I2C5BUS_NAME "i2c5"
+#endif /*BSP_USING_I2C5*/
+
+#if defined (BSP_USING_I2C6)
+#define I2C6BUS_NAME "i2c6"
+#endif /*BSP_USING_I2C6*/
+
#endif /* MIMXRT1015_SERIES */
-#define LPI2C_CLOCK_SOURCE_DIVIDER 4
+/* Select USB1 PLL (360 MHz) as master lpi2c clock source */
+#define LPI2C_CLOCK_SOURCE_SELECT (1U)
+#ifdef SOC_IMXRT1170_SERIES
+/* Clock divider for master lpi2c clock source */
+#define LPI2C_CLOCK_SOURCE_DIVIDER (12U)
+#else
+#define LPI2C_CLOCK_SOURCE_DIVIDER (0U)
/* Get frequency of lpi2c clock */
-#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER))
+#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U))
+#endif
#ifdef BSP_USING_I2C1
static struct imxrt_i2c_bus lpi2c1 =
{
@@ -96,9 +114,25 @@ static struct imxrt_i2c_bus lpi2c4 =
};
#endif /* RT_USING_HW_I2C4 */
+#ifdef BSP_USING_I2C5
+static struct imxrt_i2c_bus lpi2c5 =
+{
+ .I2C = LPI2C5,
+ .device_name = I2C5BUS_NAME,
+};
+#endif /* RT_USING_HW_I2C5 */
+
+#ifdef BSP_USING_I2C6
+static struct imxrt_i2c_bus lpi2c6 =
+{
+ .I2C = LPI2C6,
+ .device_name = I2C6BUS_NAME,
+};
+#endif /* RT_USING_HW_I2C6 */
+
#endif /* MIMXRT1015_SERIES */
-#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4))
+#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) ||defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6))
static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
@@ -123,7 +157,19 @@ static rt_err_t imxrt_lpi2c_configure(struct imxrt_i2c_bus *bus, lpi2c_master_co
RT_ASSERT(cfg != RT_NULL);
bus->parent.ops = &imxrt_i2c_ops;
+#ifdef SOC_IMXRT1170_SERIES
+ clock_root_config_t rootCfg = {0};
+ rootCfg.mux = LPI2C_CLOCK_SOURCE_SELECT;
+ rootCfg.div = LPI2C_CLOCK_SOURCE_DIVIDER + 1;
+ CLOCK_SetRootClock(bus->clock_root, &rootCfg);
+ volatile uint32_t freq = CLOCK_GetRootClockFreq(bus->clock_root);
+ LPI2C_MasterInit(bus->I2C, cfg, freq);
+#else
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, LPI2C_CLOCK_SOURCE_SELECT);
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER);
LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY);
+#endif
+
return RT_EOK;
}
@@ -221,6 +267,37 @@ static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
{
if (imxrt_i2c->msg[i].flags & RT_I2C_RD)
{
+ if ((imxrt_i2c->msg[i].flags & RT_I2C_NO_START) != RT_I2C_NO_START)
+ {
+ if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
+ {
+ i = 0;
+ break;
+ }
+
+ while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
+ {
+ }
+
+ if (LPI2C_MasterRepeatedStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
+ {
+ i = 0;
+ break;
+ }
+ }
+ else
+ {
+ if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
+ {
+ i = 0;
+ break;
+ }
+
+ while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
+ {
+ }
+ }
+
if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
{
i = 0;
@@ -245,8 +322,16 @@ static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
break;
}
- while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
+ if(LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C) != kStatus_Success)
{
+ i = 0;
+ break;
+ }
+
+ if (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
+ {
+ i = 0;
+ break;
}
if (LPI2C_MasterSend(imxrt_i2c->I2C, imxrt_i2c->msg[i].buf, imxrt_i2c->msg[i].len) != kStatus_Success)
@@ -261,11 +346,12 @@ static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
break;
}
}
- }
- if (LPI2C_MasterStop(imxrt_i2c->I2C) != kStatus_Success)
- {
- i = 0;
+ if (LPI2C_MasterStop(imxrt_i2c->I2C) != kStatus_Success)
+ {
+ i = 0;
+ }
+
}
imxrt_i2c->msg = RT_NULL;
@@ -341,6 +427,31 @@ int rt_hw_i2c_init(void)
rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name);
#endif /* BSP_USING_I2C4 */
+#if defined(BSP_USING_I2C5)
+ LPI2C_MasterGetDefaultConfig(&masterConfig);
+#if defined(HW_I2C5_BADURATE_400kHZ)
+ masterConfig.baudRate_Hz = 400000U;
+#elif defined(HW_I2C5_BADURATE_100kHZ)
+ masterConfig.baudRate_Hz = 100000U;
+#endif /* HW_I2C5_BADURATE_400kHZ */
+ lpi2c5.clock_root = kCLOCK_Root_Lpi2c5;
+ imxrt_lpi2c_configure(&lpi2c5, &masterConfig);
+ rt_i2c_bus_device_register(&lpi2c5.parent, lpi2c5.device_name);
+#endif /* BSP_USING_I2C5 */
+
+#if defined(BSP_USING_I2C6)
+ LPI2C_MasterGetDefaultConfig(&masterConfig);
+#if defined(HW_I2C6_BADURATE_400kHZ)
+ masterConfig.baudRate_Hz = 400000U;
+#elif defined(HW_I2C6_BADURATE_100kHZ)
+ masterConfig.baudRate_Hz = 100000U;
+#endif /* HW_I2C6_BADURATE_400kHZ */
+ lpi2c6.clock_root = kCLOCK_Root_Lpi2c6;
+ imxrt_lpi2c_configure(&lpi2c6, &masterConfig);
+ rt_i2c_bus_device_register(&lpi2c6.parent, lpi2c6.device_name);
+#endif /* BSP_USING_I2C6 */
+
+
#endif /* MIMXRT1015_SERIES */
return 0;
diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.c b/bsp/imxrt/libraries/drivers/drv_mdio.c
index 3e98d57f29..2738877335 100644
--- a/bsp/imxrt/libraries/drivers/drv_mdio.c
+++ b/bsp/imxrt/libraries/drivers/drv_mdio.c
@@ -1,6 +1,5 @@
-
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.h b/bsp/imxrt/libraries/drivers/drv_mdio.h
index a1623cfc2c..69d8290a32 100644
--- a/bsp/imxrt/libraries/drivers/drv_mdio.h
+++ b/bsp/imxrt/libraries/drivers/drv_mdio.h
@@ -1,6 +1,5 @@
-
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c b/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c
new file mode 100644
index 0000000000..517664b73d
--- /dev/null
+++ b/bsp/imxrt/libraries/drivers/drv_pulse_encoder.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-08-23 balanceTWK first version
+ * 2021-01-19 Leslie Lee port to imxrt series
+ */
+
+#include
+#include
+#ifdef BSP_USING_PULSE_ENCODER
+
+#include "fsl_common.h"
+#include "fsl_enc.h"
+
+#define LOG_TAG "drv.pulse_encoder"
+#include
+
+#if !defined(BSP_USING_PULSE_ENCODER1) && !defined(BSP_USING_PULSE_ENCODER2) && !defined(BSP_USING_PULSE_ENCODER3) \
+ && !defined(BSP_USING_PULSE_ENCODER4)
+ #error "Please define at least one BSP_USING_PULSE_ENCODERx"
+ /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#elif (defined(BSP_USING_PULSE_ENCODER2) || defined(BSP_USING_PULSE_ENCODER3) || defined(BSP_USING_PULSE_ENCODER4)) || defined(SOC_IMXRT1015_SERIES)
+ #error "IMXRT1015 had only one quadrature decoder module"
+#elif (defined(BSP_USING_PULSE_ENCODER3) || defined(BSP_USING_PULSE_ENCODER4)) || defined(SOC_IMXRT1020_SERIES)
+ #error "IMXRT1020 had only two quadrature decoder module"
+#endif
+
+enum
+{
+#ifdef BSP_USING_PULSE_ENCODER1
+ PULSE_ENCODER1_INDEX,
+#endif
+#ifdef BSP_USING_PULSE_ENCODER2
+ PULSE_ENCODER2_INDEX,
+#endif
+#ifdef BSP_USING_PULSE_ENCODER3
+ PULSE_ENCODER3_INDEX,
+#endif
+#ifdef BSP_USING_PULSE_ENCODER4
+ PULSE_ENCODER4_INDEX,
+#endif
+};
+
+struct imxrt_pulse_encoder_device
+{
+ struct rt_pulse_encoder_device pulse_encoder;
+ ENC_Type *base;
+ char *name;
+};
+typedef struct imxrt_pulse_encoder_device imxrt_pulse_enccoder_device_t;
+
+static imxrt_pulse_enccoder_device_t imxrt_pulse_encoder_obj[] =
+{
+#ifdef BSP_USING_PULSE_ENCODER1
+ {
+ .base = ENC1,
+ .name = "pulse1"
+ },
+#endif
+#ifdef BSP_USING_PULSE_ENCODER2
+ {
+ .base = ENC2,
+ .name = "pulse2"
+ },
+#endif
+#ifdef BSP_USING_PULSE_ENCODER3
+ {
+ .base = ENC3,
+ .name = "pulse3"
+ },
+#endif
+#ifdef BSP_USING_PULSE_ENCODER4
+ {
+ .base = ENC4,
+ .name = "pulse4"
+ },
+#endif
+};
+
+
+
+rt_err_t pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ ENC_Type *base = ((imxrt_pulse_enccoder_device_t *)(pulse_encoder->parent.user_data))->base;
+ enc_config_t enc_config;
+ ENC_GetDefaultConfig(&enc_config);
+ ENC_Init(base, &enc_config);
+ ENC_DoSoftwareLoadInitialPositionValue(base); /* Update the position counter with initial value. */
+ return RT_EOK;
+}
+
+rt_err_t pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ ENC_SetInitialPositionValue(((imxrt_pulse_enccoder_device_t *)(pulse_encoder->parent.user_data))->base, 0);
+ return RT_EOK;
+}
+
+rt_int32_t pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
+{
+ return (rt_int32_t)ENC_GetPositionValue(((imxrt_pulse_enccoder_device_t *)(pulse_encoder->parent.user_data))->base);
+}
+
+rt_err_t pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
+{
+ rt_err_t result;
+
+ result = RT_EOK;
+
+ switch (cmd)
+ {
+ case PULSE_ENCODER_CMD_ENABLE:
+ result = pulse_encoder->ops->init(pulse_encoder);
+ break;
+ case PULSE_ENCODER_CMD_DISABLE:
+ ENC_Deinit(((imxrt_pulse_enccoder_device_t *)(pulse_encoder->parent.user_data))->base);
+ break;
+ default:
+ result = -RT_ENOSYS;
+ break;
+ }
+
+ return result;
+}
+
+static const struct rt_pulse_encoder_ops _ops =
+{
+ .init = pulse_encoder_init,
+ .get_count = pulse_encoder_get_count,
+ .clear_count = pulse_encoder_clear_count,
+ .control = pulse_encoder_control,
+};
+
+int rt_hw_pulse_encoder_init(void)
+{
+ int i;
+ int result;
+
+ result = RT_EOK;
+ for (i = 0; i < sizeof(imxrt_pulse_encoder_obj) / sizeof(imxrt_pulse_encoder_obj[0]); i++)
+ {
+ imxrt_pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
+ imxrt_pulse_encoder_obj[i].pulse_encoder.ops = &_ops;
+ imxrt_pulse_encoder_obj[i].pulse_encoder.parent.user_data = &(imxrt_pulse_encoder_obj[i]);
+
+ if (rt_device_pulse_encoder_register(&imxrt_pulse_encoder_obj[i].pulse_encoder, imxrt_pulse_encoder_obj[i].name, &imxrt_pulse_encoder_obj[i]) != RT_EOK)
+ {
+ LOG_E("%s register failed", imxrt_pulse_encoder_obj[i].name);
+ result = -RT_ERROR;
+ }
+ }
+
+ return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pulse_encoder_init);
+
+#endif
diff --git a/bsp/imxrt/libraries/drivers/drv_sai.c b/bsp/imxrt/libraries/drivers/drv_sai.c
index 63c2eadb32..7a682dfb34 100644
--- a/bsp/imxrt/libraries/drivers/drv_sai.c
+++ b/bsp/imxrt/libraries/drivers/drv_sai.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -7,7 +7,7 @@
* Date Author Notes
* 2018-4-30 misonyo the first version.
*/
-
+
#include
#include
#include
diff --git a/bsp/imxrt/libraries/drivers/drv_sai.h b/bsp/imxrt/libraries/drivers/drv_sai.h
index 80e4c5d5dc..1affd91101 100644
--- a/bsp/imxrt/libraries/drivers/drv_sai.h
+++ b/bsp/imxrt/libraries/drivers/drv_sai.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -30,9 +30,9 @@
/* Clock divider for sai1 clock source */
#define DEMO_SAI1_CLOCK_SOURCE_DIVIDER (63U)
/* Get frequency of sai1 clock */
-#define AUD_BLOCK_CNT 2
-#define AUD_BLOCK_SIZE 1024
-#define AUD_FIFO_SIZE (AUD_BLOCK_SIZE * AUD_BLOCK_CNT)
+#define AUD_BLOCK_CNT 2
+#define AUD_BLOCK_SIZE 1024
+#define AUD_FIFO_SIZE (AUD_BLOCK_SIZE * AUD_BLOCK_CNT)
#define DEMO_SAI_CLK_FREQ \
(CLOCK_GetFreq(kCLOCK_AudioPllClk) / (DEMO_SAI1_CLOCK_SOURCE_DIVIDER + 1U) / \
(DEMO_SAI1_CLOCK_SOURCE_PRE_DIVIDER + 1U))
diff --git a/bsp/imxrt/libraries/drivers/drv_sdram.c b/bsp/imxrt/libraries/drivers/drv_sdram.c
index a0dbe7afe2..0b7b7907b8 100644
--- a/bsp/imxrt/libraries/drivers/drv_sdram.c
+++ b/bsp/imxrt/libraries/drivers/drv_sdram.c
@@ -31,7 +31,7 @@ int rt_hw_sdram_Init(void)
/* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t));
memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
-
+
/* Initialize SEMC. */
SEMC_GetDefaultConfig(&config);
config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
@@ -68,18 +68,18 @@ int rt_hw_sdram_Init(void)
{
LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE);
#ifdef RT_USING_MEMHEAP_AS_HEAP
- /*
- * If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap.
- * The heap start address is (base + half size), and the size is (half size - 2M).
- * The reasons are:
- * 1. Reserve the half space for SDRAM link case
- * 2. Reserve the 2M for non-cache space
- */
+ /*
+ * If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap.
+ * The heap start address is (base + half size), and the size is (half size - 2M).
+ * The reasons are:
+ * 1. Reserve the half space for SDRAM link case
+ * 2. Reserve the 2M for non-cache space
+ */
rt_memheap_init(&system_heap, "sdram", (void *)(SDRAM_BANK_ADDR + (SDRAM_SIZE * 1024)/2),
- (SDRAM_SIZE * 1024)/2 - (2 * 1024 * 1024));
+ (SDRAM_SIZE * 1024)/2 - (2 * 1024 * 1024));
#endif
}
-
+
return result;
}
INIT_BOARD_EXPORT(rt_hw_sdram_Init);
diff --git a/bsp/imxrt/libraries/drivers/drv_sdram.h b/bsp/imxrt/libraries/drivers/drv_sdram.h
index f7956c6944..9eda46bcd5 100644
--- a/bsp/imxrt/libraries/drivers/drv_sdram.h
+++ b/bsp/imxrt/libraries/drivers/drv_sdram.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -7,7 +7,7 @@
* Date Author Notes
* 2018-03-27 Liuguang the first version.
*/
-
+
#ifndef DRV_SDRAM_H__
#define DRV_SDRAM_H__
diff --git a/bsp/imxrt/libraries/drivers/drv_spi.c b/bsp/imxrt/libraries/drivers/drv_spi.c
index 04c9e94020..c32d66b934 100644
--- a/bsp/imxrt/libraries/drivers/drv_spi.c
+++ b/bsp/imxrt/libraries/drivers/drv_spi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -11,10 +11,10 @@
#include
#ifdef BSP_USING_SPI
-#include "drv_spi.h"
-#include "fsl_common.h"
-#include "fsl_iomuxc.h"
-#include "fsl_lpspi.h"
+#include "drv_spi.h"
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_lpspi.h"
#include "fsl_lpspi_edma.h"
#include "fsl_dmamux.h"
@@ -177,21 +177,21 @@ void edma_xfer_callback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, st
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
{
- rt_err_t ret = RT_EOK;
-
- struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
- RT_ASSERT(spi_device != RT_NULL);
-
- struct imxrt_sw_spi_cs *cs_pin = (struct imxrt_sw_spi_cs *)rt_malloc(sizeof(struct imxrt_sw_spi_cs));
+ rt_err_t ret = RT_EOK;
+
+ struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+ RT_ASSERT(spi_device != RT_NULL);
+
+ struct imxrt_sw_spi_cs *cs_pin = (struct imxrt_sw_spi_cs *)rt_malloc(sizeof(struct imxrt_sw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
-
+
cs_pin->pin = pin;
- rt_pin_mode(pin, PIN_MODE_OUTPUT);
- rt_pin_write(pin, PIN_HIGH);
-
- ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
-
- return ret;
+ rt_pin_mode(pin, PIN_MODE_OUTPUT);
+ rt_pin_write(pin, PIN_HIGH);
+
+ ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+ return ret;
}
static uint32_t imxrt_get_lpspi_freq(void)
@@ -199,31 +199,31 @@ static uint32_t imxrt_get_lpspi_freq(void)
uint32_t freq = 0;
/* CLOCK_GetMux(kCLOCK_LpspiMux):
- 00b: derive clock from PLL3 PFD1 720M
- 01b: derive clock from PLL3 PFD0 720M
- 10b: derive clock from PLL2 528M
- 11b: derive clock from PLL2 PFD2 396M
+ 00b: derive clock from PLL3 PFD1 720M
+ 01b: derive clock from PLL3 PFD0 720M
+ 10b: derive clock from PLL2 528M
+ 11b: derive clock from PLL2 PFD2 396M
*/
switch(CLOCK_GetMux(kCLOCK_LpspiMux))
{
case 0:
- freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk);
- break;
-
+ freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk);
+ break;
+
case 1:
- freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk);
- break;
-
+ freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk);
+ break;
+
case 2:
- freq = CLOCK_GetFreq(kCLOCK_SysPllClk);
- break;
-
+ freq = CLOCK_GetFreq(kCLOCK_SysPllClk);
+ break;
+
case 3:
- freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk);
- break;
+ freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk);
+ break;
}
-
- freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U);
+
+ freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U);
return freq;
}
@@ -250,7 +250,7 @@ static void lpspi_dma_config(struct imxrt_spi *spi)
DMAMUX_SetSource(DMAMUX, spi->dma->tx_channel, spi->dma->tx_request);
DMAMUX_EnableChannel(DMAMUX, spi->dma->tx_channel);
EDMA_CreateHandle(&spi->dma->tx_edma, DMA0, spi->dma->tx_channel);
-
+
LPSPI_MasterTransferCreateHandleEDMA(spi->base,
&spi->dma->spi_edma,
edma_xfer_callback,
@@ -263,8 +263,8 @@ static void lpspi_dma_config(struct imxrt_spi *spi)
static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
{
- lpspi_master_config_t masterConfig;
- struct imxrt_spi *spi = RT_NULL;
+ lpspi_master_config_t masterConfig;
+ struct imxrt_spi *spi = RT_NULL;
RT_ASSERT(cfg != RT_NULL);
RT_ASSERT(device != RT_NULL);
@@ -274,76 +274,76 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config
if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32)
{
- return RT_EINVAL;
+ return RT_EINVAL;
}
- LPSPI_MasterGetDefaultConfig(&masterConfig);
-
+ LPSPI_MasterGetDefaultConfig(&masterConfig);
+
if(cfg->max_hz > 40*1000*1000)
{
cfg->max_hz = 40*1000*1000;
}
- masterConfig.baudRate = cfg->max_hz;
- masterConfig.bitsPerFrame = cfg->data_width;
-
+ masterConfig.baudRate = cfg->max_hz;
+ masterConfig.bitsPerFrame = cfg->data_width;
+
if(cfg->mode & RT_SPI_MSB)
{
- masterConfig.direction = kLPSPI_MsbFirst;
+ masterConfig.direction = kLPSPI_MsbFirst;
}
else
{
- masterConfig.direction = kLPSPI_LsbFirst;
+ masterConfig.direction = kLPSPI_LsbFirst;
}
-
+
if(cfg->mode & RT_SPI_CPHA)
{
- masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
+ masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
}
else
{
- masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
+ masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
}
-
+
if(cfg->mode & RT_SPI_CPOL)
{
- masterConfig.cpol = kLPSPI_ClockPolarityActiveLow;
+ masterConfig.cpol = kLPSPI_ClockPolarityActiveLow;
}
else
{
- masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
+ masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
}
- masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
+ masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
masterConfig.dataOutConfig = kLpspiDataOutTristate;
- masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
- masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
- masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
+ masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
+ masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
+ masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
- LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq());
- spi->base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK;
+ LPSPI_MasterInit(spi->base, &masterConfig, imxrt_get_lpspi_freq());
+ spi->base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK;
return RT_EOK;
}
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
- lpspi_transfer_t transfer;
+ lpspi_transfer_t transfer;
status_t status;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
- struct imxrt_spi *spi = (struct imxrt_spi *)(device->bus->parent.user_data);
- struct imxrt_sw_spi_cs *cs = device->parent.user_data;
+ struct imxrt_spi *spi = (struct imxrt_spi *)(device->bus->parent.user_data);
+ struct imxrt_sw_spi_cs *cs = device->parent.user_data;
if(message->cs_take)
{
rt_pin_write(cs->pin, PIN_LOW);
}
- transfer.dataSize = message->length;
- transfer.rxData = (uint8_t *)(message->recv_buf);
- transfer.txData = (uint8_t *)(message->send_buf);
+ transfer.dataSize = message->length;
+ transfer.rxData = (uint8_t *)(message->recv_buf);
+ transfer.txData = (uint8_t *)(message->send_buf);
if(RT_FALSE == spi->dma_flag)
{
@@ -370,10 +370,10 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
message->length = 0;
}
- return message->length;
+ return message->length;
}
-static struct rt_spi_ops imxrt_spi_ops =
+static struct rt_spi_ops imxrt_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer
@@ -405,8 +405,8 @@ int rt_hw_spi_bus_init(void)
lpspis[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO);
}
- return ret;
+ return ret;
}
-INIT_BOARD_EXPORT(rt_hw_spi_bus_init);
+INIT_BOARD_EXPORT(rt_hw_spi_bus_init);
#endif /* BSP_USING_SPI */
diff --git a/bsp/imxrt/libraries/drivers/drv_spi.h b/bsp/imxrt/libraries/drivers/drv_spi.h
index 54f1744be0..4cd4c1a2bb 100644
--- a/bsp/imxrt/libraries/drivers/drv_spi.h
+++ b/bsp/imxrt/libraries/drivers/drv_spi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -7,7 +7,7 @@
* Date Author Notes
* 2018-03-27 Liuguang the first version.
*/
-
+
#ifndef DRV_SPI_H__
#define DRV_SPI_H__
diff --git a/bsp/imxrt/libraries/drivers/drv_uart.c b/bsp/imxrt/libraries/drivers/drv_uart.c
index fd5bfd1719..0265ee215a 100644
--- a/bsp/imxrt/libraries/drivers/drv_uart.c
+++ b/bsp/imxrt/libraries/drivers/drv_uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -461,7 +461,7 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer
recv_len = uart->serial.config.bufsz - uart->dma_rx->last_index;
uart->dma_rx->last_index = 0;
}
- else
+ else
{
/* clear half interrupt */
EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel,kEDMA_InterruptFlag);
diff --git a/bsp/imxrt/libraries/drivers/drv_usbh.c b/bsp/imxrt/libraries/drivers/drv_usbh.c
new file mode 100644
index 0000000000..a7e0ad6062
--- /dev/null
+++ b/bsp/imxrt/libraries/drivers/drv_usbh.c
@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2017-10-30 ZYH the first version
+ * 2019-12-19 tyustli port to stm32 series
+ * 2021-01-19 Leslie Lee port to imxrt series
+ */
+#include
+
+#if defined(BSP_USB0_HOST) || defined(BSP_USB1_HOST)
+#include "drv_usbh.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+/* USB PHY configuration */
+#ifndef BOARD_USB_PHY_D_CAL
+#define BOARD_USB_PHY_D_CAL (0x0CU)
+#endif
+#ifndef BOARD_USB_PHY_TXCAL45DP
+#define BOARD_USB_PHY_TXCAL45DP (0x06U)
+#endif
+#ifndef BOARD_USB_PHY_TXCAL45DM
+#define BOARD_USB_PHY_TXCAL45DM (0x06U)
+#endif
+
+#define USB_HOST_INTERRUPT_PRIORITY 3
+
+enum
+{
+#ifdef BSP_USB0_HOST
+ USBH0_INDEX,
+#endif
+#ifdef BSP_USB1_HOST
+ USBH1_INDEX,
+#endif
+};
+
+struct imxrt_usb_host_pipe
+{
+ usb_host_pipe_handle pipe_handle;
+ struct rt_completion urb_completion;
+ usb_status_t transfer_status;
+};
+
+struct imxrt_usb_host
+{
+ struct uhcd uhcd;
+ usb_host_handle host_handle;
+ usb_device_handle device_handle;
+ struct imxrt_usb_host_pipe pipes[16];
+ volatile rt_bool_t connect_status;
+ char *name;
+};
+
+static struct imxrt_usb_host imxrt_usb_host_obj[] =
+{
+#ifdef BSP_USB0_HOST
+ {
+ .connect_status = RT_FALSE,
+ .name = "usbh0"
+ },
+#endif
+#ifdef BSP_USB1_HOST
+ {
+ .connect_status = RT_FALSE,
+ .name = "usbh1"
+ },
+#endif
+};
+
+static void _imxrt_usb_host_send_callback(void *param, usb_host_transfer_t *transfer, usb_status_t status)
+{
+ struct imxrt_usb_host_pipe *pipe = (struct imxrt_usb_host_pipe *)param;
+ pipe->transfer_status = status;
+ rt_completion_done(&pipe->urb_completion);
+}
+
+
+/*!
+ * @brief Initializes USB specific setting that was not set by the Clocks tool.
+ */
+static void USB_HostClockInit(usb_controller_index_t controller_id)
+{
+ usb_phy_config_struct_t phyConfig = {
+ BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
+ };
+ uint32_t notUsed = 0;
+
+ if (controller_id == kUSB_ControllerEhci0)
+ {
+ CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
+ CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
+ }
+ else
+ {
+ CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
+ CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
+ }
+
+ USB_EhciPhyInit(controller_id, 24000000U, &phyConfig);
+}
+
+/*!
+ * @brief Enables interrupt service routines for device.
+ */
+void USB_HostIsrEnable(usb_controller_index_t controller_id)
+{
+ uint8_t irqNumber;
+#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U))
+ IRQn_Type usbHOSTEhciIrq[] = USBHS_IRQS;
+ irqNumber = usbHOSTEhciIrq[controller_id - kUSB_ControllerEhci0];
+#endif
+/* Install isr, set priority, and enable IRQ. */
+#if defined(__GIC_PRIO_BITS)
+ GIC_SetPriority((IRQn_Type)irqNumber, USB_HOST_INTERRUPT_PRIORITY);
+#else
+ NVIC_SetPriority((IRQn_Type)irqNumber, USB_HOST_INTERRUPT_PRIORITY);
+#endif
+ EnableIRQ((IRQn_Type)irqNumber);
+}
+
+#ifdef BSP_USB0_HOST
+void USB_OTG1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ USB_HostEhciIsrFunction(imxrt_usb_host_obj[USBH0_INDEX].host_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+static rt_err_t _ehci0_reset_port(rt_uint8_t port)
+{
+ // No reset port function available
+ return RT_EOK;
+}
+
+static uint8_t _ehci0_pipe_buf[64];
+static uint8_t _ehci0_pipe_idx;
+
+static int _ehci0_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
+{
+ int timeout = timeouts;
+
+ if (!imxrt_usb_host_obj[USBH0_INDEX].connect_status)
+ {
+ return -1;
+ }
+ usb_host_transfer_t *transfer;
+ if (imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].pipe_handle == NULL)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error operation on null pipe\n"));
+ return -1;
+ }
+ if (USB_HostMallocTransfer(imxrt_usb_host_obj[USBH0_INDEX].host_handle, &transfer) != kStatus_USB_Success)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error to get transfer\n"));
+ return -1;
+ }
+ transfer->transferBuffer = buffer;
+ transfer->transferLength = nbytes;
+ transfer->transferSofar = 0;
+ transfer->callbackFn = _imxrt_usb_host_send_callback;
+ transfer->callbackParam = &(imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index]);
+ transfer->direction = (pipe->ep.bEndpointAddress & USB_DIR_IN) ? USB_IN : USB_OUT;
+ if (pipe->ep.bmAttributes == USB_ENDPOINT_CONTROL)
+ {
+ if (token == USBH_PID_SETUP)
+ {
+ struct urequest *setup = (struct urequest *)buffer;
+ transfer->setupStatus = 0;
+ transfer->setupPacket->bmRequestType = setup->request_type;
+ transfer->setupPacket->bRequest = setup->bRequest;
+ transfer->setupPacket->wIndex = setup->wIndex;
+ transfer->setupPacket->wLength = setup->wLength;
+ transfer->setupPacket->wValue = setup->wValue;
+ transfer->transferBuffer = RT_NULL;
+ transfer->transferLength = 0;
+ transfer->next = RT_NULL;
+ if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN)
+ {
+ transfer->direction = USB_IN;
+ transfer->transferBuffer = _ehci0_pipe_buf;
+ transfer->transferLength = setup->wLength;
+ _ehci0_pipe_idx = 0;
+ }
+ else
+ {
+ transfer->direction = USB_OUT;
+ }
+ }
+ else
+ {
+ rt_memcpy(buffer, _ehci0_pipe_buf + _ehci0_pipe_idx, nbytes);
+ imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].transfer_status = kStatus_USB_Success;
+ transfer->transferSofar = nbytes;
+ _ehci0_pipe_idx += nbytes;
+ if (_ehci0_pipe_idx >= 64)
+ {
+ _ehci0_pipe_idx = 0;
+ }
+ goto _ehci0_pipe_xfer_finish;
+ }
+
+ }
+ rt_completion_init(&(imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].urb_completion));
+ if (USB_HostEhciWritePipe(((usb_host_instance_t *)imxrt_usb_host_obj[USBH0_INDEX].host_handle)->controllerHandle, imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].pipe_handle, transfer) != kStatus_USB_Success)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb host failed to send\n"));
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH0_INDEX].host_handle, transfer);
+ return -1;
+ }
+ if (-RT_ETIMEOUT == rt_completion_wait(&(imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].urb_completion), RT_WAITING_FOREVER))
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb transfer timeout\n"));
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH0_INDEX].host_handle, transfer);
+ return -1;
+ }
+ _ehci0_pipe_xfer_finish:
+ switch (imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].transfer_status)
+ {
+ case kStatus_USB_Success:
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("ok\n"));
+ pipe->status = UPIPE_STATUS_OK;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ size_t size = transfer->transferSofar;
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH0_INDEX].host_handle, transfer);
+ if (pipe->ep.bEndpointAddress & 0x80)
+ {
+ return size;
+ }
+ else if (pipe->ep.bEndpointAddress & 0x00)
+ {
+ return size;
+ }
+ return nbytes;
+ break;
+ }
+ case kStatus_USB_TransferStall:
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("stall\n"));
+ pipe->status = UPIPE_STATUS_STALL;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH0_INDEX].host_handle, transfer);
+ return -1;
+ break;
+ }
+ case kStatus_USB_TransferFailed:
+ default:
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error\n"));
+ pipe->status = UPIPE_STATUS_ERROR;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH0_INDEX].host_handle, transfer);
+ return -1;
+ break;
+ }
+ }
+}
+
+static rt_uint16_t _ehci0_pipe_index = 0;
+static rt_uint8_t _ehci0_get_free_pipe_index(void)
+{
+ rt_uint8_t idx;
+ for (idx = 1; idx < 16; idx++)
+ {
+ if (!(_ehci0_pipe_index & (0x01 << idx)))
+ {
+ _ehci0_pipe_index |= (0x01 << idx);
+ return idx;
+ }
+ }
+ return 0xff;
+}
+
+static void _ehci0_free_pipe_index(rt_uint8_t index)
+{
+ _ehci0_pipe_index &= ~(0x01 << index);
+}
+
+static rt_err_t _ehci0_open_pipe(upipe_t pipe)
+{
+ pipe->pipe_index = _ehci0_get_free_pipe_index();
+ if (pipe->pipe_index == 0xFF)
+ {
+ return -RT_ERROR;
+ }
+ usb_host_pipe_init_t pipe_init =
+ {
+ .devInstance = imxrt_usb_host_obj[USBH0_INDEX].device_handle,
+ .pipeType = pipe->ep.bmAttributes,
+ .direction = (pipe->ep.bEndpointAddress & USB_DIR_IN) ? USB_IN : USB_OUT,
+ .endpointAddress = (pipe->ep.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK),
+ .interval = pipe->ep.bInterval,
+ .maxPacketSize = (uint16_t)(pipe->ep.wMaxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK),
+ .numberPerUframe = (uint8_t)(pipe->ep.wMaxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK),
+ .nakCount = USB_HOST_CONFIG_MAX_NAK,
+ };
+ USB_HostOpenPipe(imxrt_usb_host_obj[USBH0_INDEX].host_handle, &imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].pipe_handle, &pipe_init);
+ return RT_EOK;
+}
+
+static rt_err_t _ehci0_close_pipe(upipe_t pipe)
+{
+ (void)USB_HostClosePipe(imxrt_usb_host_obj[USBH0_INDEX].host_handle, imxrt_usb_host_obj[USBH0_INDEX].pipes[pipe->pipe_index].pipe_handle);
+ _ehci0_free_pipe_index(pipe->pipe_index);
+ return RT_EOK;
+}
+
+static struct uhcd_ops _ehci0_uhcd_ops =
+{
+ _ehci0_reset_port,
+ _ehci0_pipe_xfer,
+ _ehci0_open_pipe,
+ _ehci0_close_pipe,
+};
+
+static usb_status_t usb0_host_callback(usb_device_handle handle, usb_host_configuration_handle config_handle, rt_uint32_t event_code)
+{
+ usb_status_t status = kStatus_USB_Success;
+
+ switch (event_code)
+ {
+ case kUSB_HostEventAttach:
+ if (!imxrt_usb_host_obj[USBH0_INDEX].connect_status)
+ {
+ imxrt_usb_host_obj[USBH0_INDEX].connect_status = RT_TRUE;
+ imxrt_usb_host_obj[USBH0_INDEX].device_handle = handle;
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n"));
+ rt_usbh_root_hub_connect_handler(&(imxrt_usb_host_obj[USBH0_INDEX].uhcd), OTG_PORT, RT_TRUE);
+ }
+ break;
+
+ case kUSB_HostEventNotSupported:
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb device not supported\n"));
+ break;
+
+ case kUSB_HostEventEnumerationDone:
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("enumeration done\n"));
+ break;
+
+ case kUSB_HostEventDetach:
+ if (imxrt_usb_host_obj[USBH0_INDEX].connect_status)
+ {
+ imxrt_usb_host_obj[USBH0_INDEX].connect_status = RT_FALSE;
+ imxrt_usb_host_obj[USBH0_INDEX].device_handle = handle;
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n"));
+ rt_usbh_root_hub_disconnect_handler(&(imxrt_usb_host_obj[USBH0_INDEX].uhcd), OTG_PORT);
+ (void)USB_HostCloseDeviceInterface(handle, NULL);
+ }
+ break;
+
+ default:
+ break;
+ }
+ return status;
+}
+
+rt_thread_t usbh0_thread;
+
+static void _ehci0_usbh_thread(void* param)
+{
+ while (1)
+ {
+ USB_HostEhciTaskFunction(imxrt_usb_host_obj[USBH0_INDEX].host_handle);
+ }
+}
+
+static rt_err_t _ehci0_usbh_init(rt_device_t device)
+{
+ USB_HostClockInit(kUSB_ControllerEhci0);
+
+ if (kStatus_USB_Success == USB_HostInit(kUSB_ControllerEhci0, &imxrt_usb_host_obj[USBH0_INDEX].host_handle, usb0_host_callback))
+ {
+ usbh0_thread = rt_thread_create("ehci0", _ehci0_usbh_thread, RT_NULL, 500, 4, 9999999);
+ rt_thread_startup(usbh0_thread);
+ USB_HostIsrEnable(kUSB_ControllerEhci0);
+ }
+ else
+ {
+ rt_kprintf("USB_HostInit ehci0 error\r\n");
+ return -RT_ERROR;
+ }
+ return RT_EOK;
+}
+#endif
+
+#ifdef BSP_USB1_HOST
+void USB_OTG2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ USB_HostEhciIsrFunction(imxrt_usb_host_obj[USBH1_INDEX].host_handle);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+static rt_err_t _ehci1_reset_port(rt_uint8_t port)
+{
+ // No reset port function available
+ return RT_EOK;
+}
+
+static uint8_t _ehci1_pipe_buf[64];
+static uint8_t _ehci1_pipe_idx;
+
+static int _ehci1_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
+{
+ int timeout = timeouts;
+
+ if (!imxrt_usb_host_obj[USBH1_INDEX].connect_status)
+ {
+ return -1;
+ }
+ usb_host_transfer_t *transfer;
+ if (imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].pipe_handle == NULL)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error operation on null pipe\n"));
+ return -1;
+ }
+ if (USB_HostMallocTransfer(imxrt_usb_host_obj[USBH1_INDEX].host_handle, &transfer) != kStatus_USB_Success)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error to get transfer\n"));
+ return -1;
+ }
+ transfer->transferBuffer = buffer;
+ transfer->transferLength = nbytes;
+ transfer->transferSofar = 0;
+ transfer->callbackFn = _imxrt_usb_host_send_callback;
+ transfer->callbackParam = &(imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index]);
+ transfer->direction = (pipe->ep.bEndpointAddress & USB_DIR_IN) ? USB_IN : USB_OUT;
+ if (pipe->ep.bmAttributes == USB_ENDPOINT_CONTROL)
+ {
+ if (token == USBH_PID_SETUP)
+ {
+ struct urequest *setup = (struct urequest *)buffer;
+ transfer->setupStatus = 0;
+ transfer->setupPacket->bmRequestType = setup->request_type;
+ transfer->setupPacket->bRequest = setup->bRequest;
+ transfer->setupPacket->wIndex = setup->wIndex;
+ transfer->setupPacket->wLength = setup->wLength;
+ transfer->setupPacket->wValue = setup->wValue;
+ transfer->transferBuffer = RT_NULL;
+ transfer->transferLength = 0;
+ transfer->next = RT_NULL;
+ if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN)
+ {
+ transfer->direction = USB_IN;
+ transfer->transferBuffer = _ehci1_pipe_buf;
+ transfer->transferLength = setup->wLength;
+ _ehci1_pipe_idx = 0;
+ }
+ else
+ {
+ transfer->direction = USB_OUT;
+ }
+ }
+ else
+ {
+ rt_memcpy(buffer, _ehci1_pipe_buf + _ehci1_pipe_idx, nbytes);
+ imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].transfer_status = kStatus_USB_Success;
+ transfer->transferSofar = nbytes;
+ _ehci1_pipe_idx += nbytes;
+ if (_ehci1_pipe_idx >= 64)
+ {
+ _ehci1_pipe_idx = 0;
+ }
+ goto _ehci1_pipe_xfer_finish;
+ }
+
+ }
+ rt_completion_init(&(imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].urb_completion));
+ if (USB_HostEhciWritePipe(((usb_host_instance_t *)imxrt_usb_host_obj[USBH1_INDEX].host_handle)->controllerHandle, imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].pipe_handle, transfer) != kStatus_USB_Success)
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb host failed to send\n"));
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH1_INDEX].host_handle, transfer);
+ return -1;
+ }
+ if (-RT_ETIMEOUT == rt_completion_wait(&(imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].urb_completion), RT_WAITING_FOREVER))
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb transfer timeout\n"));
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH1_INDEX].host_handle, transfer);
+ return -1;
+ }
+ // rt_thread_mdelay(1);
+ _ehci1_pipe_xfer_finish:
+ switch (imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].transfer_status)
+ {
+ case kStatus_USB_Success:
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("ok\n"));
+ pipe->status = UPIPE_STATUS_OK;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ size_t size = transfer->transferSofar;
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH1_INDEX].host_handle, transfer);
+ if (pipe->ep.bEndpointAddress & 0x80)
+ {
+ return size;
+ }
+ else if (pipe->ep.bEndpointAddress & 0x00)
+ {
+ return size;
+ }
+ return nbytes;
+ break;
+ }
+ case kStatus_USB_TransferStall:
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("stall\n"));
+ pipe->status = UPIPE_STATUS_STALL;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH1_INDEX].host_handle, transfer);
+ return -1;
+ break;
+ }
+ case kStatus_USB_TransferFailed:
+ default:
+ {
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("error\n"));
+ pipe->status = UPIPE_STATUS_ERROR;
+ if (pipe->callback != RT_NULL)
+ {
+ pipe->callback(pipe);
+ }
+ (void)USB_HostFreeTransfer(imxrt_usb_host_obj[USBH1_INDEX].host_handle, transfer);
+ return -1;
+ break;
+ }
+ }
+}
+
+static rt_uint16_t _ehci1_pipe_index = 0;
+static rt_uint8_t _ehci1_get_free_pipe_index(void)
+{
+ rt_uint8_t idx;
+ for (idx = 1; idx < 16; idx++)
+ {
+ if (!(_ehci1_pipe_index & (0x01 << idx)))
+ {
+ _ehci1_pipe_index |= (0x01 << idx);
+ return idx;
+ }
+ }
+ return 0xff;
+}
+
+static void _ehci1_free_pipe_index(rt_uint8_t index)
+{
+ _ehci1_pipe_index &= ~(0x01 << index);
+}
+
+static rt_err_t _ehci1_open_pipe(upipe_t pipe)
+{
+ pipe->pipe_index = _ehci1_get_free_pipe_index();
+ if (pipe->pipe_index == 0xFF)
+ {
+ return -RT_ERROR;
+ }
+ usb_host_pipe_init_t pipe_init =
+ {
+ .devInstance = imxrt_usb_host_obj[USBH1_INDEX].device_handle,
+ .pipeType = pipe->ep.bmAttributes,
+ .direction = (pipe->ep.bEndpointAddress & USB_DIR_IN) ? USB_IN : USB_OUT,
+ .endpointAddress = (pipe->ep.bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK),
+ .interval = pipe->ep.bInterval,
+ .maxPacketSize = (uint16_t)(pipe->ep.wMaxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK),
+ .numberPerUframe = (uint8_t)(pipe->ep.wMaxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK),
+ .nakCount = USB_HOST_CONFIG_MAX_NAK,
+ };
+ USB_HostOpenPipe(imxrt_usb_host_obj[USBH1_INDEX].host_handle, &imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].pipe_handle, &pipe_init);
+ return RT_EOK;
+}
+
+static rt_err_t _ehci1_close_pipe(upipe_t pipe)
+{
+ (void)USB_HostClosePipe(imxrt_usb_host_obj[USBH1_INDEX].host_handle, imxrt_usb_host_obj[USBH1_INDEX].pipes[pipe->pipe_index].pipe_handle);
+ _ehci1_free_pipe_index(pipe->pipe_index);
+ return RT_EOK;
+}
+
+static struct uhcd_ops _ehci1_uhcd_ops =
+{
+ _ehci1_reset_port,
+ _ehci1_pipe_xfer,
+ _ehci1_open_pipe,
+ _ehci1_close_pipe,
+};
+
+static usb_status_t usb1_host_callback(usb_device_handle handle, usb_host_configuration_handle config_handle, rt_uint32_t event_code)
+{
+ usb_status_t status = kStatus_USB_Success;
+
+ switch (event_code)
+ {
+ case kUSB_HostEventAttach:
+ if (!imxrt_usb_host_obj[USBH1_INDEX].connect_status)
+ {
+ imxrt_usb_host_obj[USBH1_INDEX].connect_status = RT_TRUE;
+ imxrt_usb_host_obj[USBH1_INDEX].device_handle = handle;
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n"));
+ rt_usbh_root_hub_connect_handler(&(imxrt_usb_host_obj[USBH1_INDEX].uhcd), OTG_PORT, RT_TRUE);
+ }
+ break;
+
+ case kUSB_HostEventNotSupported:
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb device not supported\n"));
+ break;
+
+ case kUSB_HostEventEnumerationDone:
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("enumeration done\n"));
+ break;
+
+ case kUSB_HostEventDetach:
+ if (imxrt_usb_host_obj[USBH1_INDEX].connect_status)
+ {
+ imxrt_usb_host_obj[USBH1_INDEX].connect_status = RT_FALSE;
+ imxrt_usb_host_obj[USBH1_INDEX].device_handle = handle;
+ RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n"));
+ rt_usbh_root_hub_disconnect_handler(&(imxrt_usb_host_obj[USBH1_INDEX].uhcd), OTG_PORT);
+ (void)USB_HostCloseDeviceInterface(handle, NULL);
+ }
+ break;
+
+ default:
+ break;
+ }
+ return status;
+}
+
+rt_thread_t usbh1_thread;
+
+static void _ehci1_usbh_thread(void* param)
+{
+ while (1)
+ {
+ USB_HostEhciTaskFunction(imxrt_usb_host_obj[USBH1_INDEX].host_handle);
+ }
+}
+
+static rt_err_t _ehci1_usbh_init(rt_device_t device)
+{
+ USB_HostClockInit(kUSB_ControllerEhci1);
+
+ if (kStatus_USB_Success == USB_HostInit(kUSB_ControllerEhci1, &imxrt_usb_host_obj[USBH1_INDEX].host_handle, usb1_host_callback))
+ {
+ usbh1_thread = rt_thread_create("ehci1", _ehci1_usbh_thread, RT_NULL, 500, 4, 9999999);
+ rt_thread_startup(usbh1_thread);
+ USB_HostIsrEnable(kUSB_ControllerEhci1);
+ }
+ else
+ {
+ rt_kprintf("USB_HostInit ehci1 error\r\n");
+ return -RT_ERROR;
+ }
+ return RT_EOK;
+}
+#endif
+
+int imxrt_usbh_register(void)
+{
+ rt_err_t res = -RT_ERROR;
+ struct imxrt_usb_host *usb_host_obj;
+
+#ifdef BSP_USB0_HOST
+ usb_host_obj = &(imxrt_usb_host_obj[USBH0_INDEX]);
+ rt_memset((void *)(&(usb_host_obj->uhcd)), 0, sizeof(struct uhcd));
+ usb_host_obj->uhcd.parent.type = RT_Device_Class_USBHost;
+ usb_host_obj->uhcd.parent.init = _ehci0_usbh_init;
+ usb_host_obj->uhcd.parent.user_data = usb_host_obj;
+ usb_host_obj->uhcd.ops = &_ehci0_uhcd_ops;
+ usb_host_obj->uhcd.num_ports = OTG_PORT;
+ res = rt_device_register(&(usb_host_obj->uhcd.parent), usb_host_obj->name, RT_DEVICE_FLAG_DEACTIVATE);
+ if (res != RT_EOK)
+ {
+ rt_kprintf("register usb0 host failed res = %d\r\n", res);
+ return -RT_ERROR;
+ }
+
+ rt_usb_host_init(usb_host_obj->name);
+#endif
+#ifdef BSP_USB1_HOST
+ usb_host_obj = &(imxrt_usb_host_obj[USBH1_INDEX]);
+ rt_memset((void *)(&(usb_host_obj->uhcd)), 0, sizeof(struct uhcd));
+ usb_host_obj->uhcd.parent.type = RT_Device_Class_USBHost;
+ usb_host_obj->uhcd.parent.init = _ehci1_usbh_init;
+ usb_host_obj->uhcd.parent.user_data = usb_host_obj;
+ usb_host_obj->uhcd.ops = &_ehci1_uhcd_ops;
+ usb_host_obj->uhcd.num_ports = OTG_PORT;
+ res = rt_device_register(&(usb_host_obj->uhcd.parent), usb_host_obj->name, RT_DEVICE_FLAG_DEACTIVATE);
+ if (res != RT_EOK)
+ {
+ rt_kprintf("register usb0 host failed res = %d\r\n", res);
+ return -RT_ERROR;
+ }
+
+ rt_usb_host_init(usb_host_obj->name);
+#endif
+ return RT_EOK;
+}
+INIT_DEVICE_EXPORT(imxrt_usbh_register);
+
+#endif
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/drv_usbh.h b/bsp/imxrt/libraries/drivers/drv_usbh.h
new file mode 100644
index 0000000000..db1f2074f8
--- /dev/null
+++ b/bsp/imxrt/libraries/drivers/drv_usbh.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2017-12-12 ZYH the first version
+ * 2019-12-19 tyustli port to stm32 series
+ * 2021-01-19 Leslie Lee port to imxrt series
+ */
+#ifndef __DRV_USBH_H__
+#define __DRV_USBH_H__
+#include
+
+#define OTG_PORT 1
+
+int imxrt_usbh_register(void);
+
+#endif
+
+/************* end of file ************/
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/device/usb_device.h b/bsp/imxrt/libraries/drivers/usb/device/usb_device.h
index 99e8a879f8..dc12f0249a 100644
--- a/bsp/imxrt/libraries/drivers/usb/device/usb_device.h
+++ b/bsp/imxrt/libraries/drivers/usb/device/usb_device.h
@@ -253,7 +253,7 @@ extern "C" {
* @retval kStatus_USB_Busy Cannot allocate a device handle.
* @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id.
* @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty
- * interface entity.
+ * interface entity.
* @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number.
* Or, the device has been initialized.
* Or, the mutex or message queue is created failed.
@@ -501,8 +501,8 @@ extern usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time
*
* @param[in] handle The device handle got from #USB_DeviceInit.
*
- * @retval kStatus_USB_Success The device is stopped successfully.
- * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
+ * @retval kStatus_USB_Success The device is stopped successfully.
+ * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid.
*/
extern usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle);
#endif
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host.h
index 53be402cd3..6d338bb64b 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host.h
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host.h
@@ -1,31 +1,9 @@
/*
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016 - 2019 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _USB_HOST_H_
@@ -68,6 +46,16 @@ typedef enum _usb_host_event
kUSB_HostEventDetach, /*!< Device is detached */
kUSB_HostEventEnumerationDone, /*!< Device's enumeration is done and the device is supported */
kUSB_HostEventNotSupported, /*!< Device's enumeration is done and the device is not supported */
+ /*! Device's enumeration failed due to errors
+ * fail reason is put in the high 2 bytes of callback event code.
+ * kStatus_USB_TransferFailed - the transfer failed.
+ * kStatus_USB_TransferCancel - transfer is canceled by application.
+ * kStatus_USB_Error - parsing descriptor failed, the power cannot satisfy device's requirement,
+ * device addresss allocation failed, transfer is not enough
+ * or the transfer API failed.
+ * kStatus_USB_AllocFail - malloc failed.
+ */
+ kUSB_HostEventEnumerationFail,
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
kUSB_HostEventNotSuspended, /*!< Suspend failed */
kUSB_HostEventSuspended, /*!< Suspend successful */
@@ -103,7 +91,60 @@ typedef enum _usb_host_dev_info
kUSB_HostGetConfigurationDes, /*!< Device's configuration descriptor pointer */
kUSB_HostGetConfigurationLength, /*!< Device's configuration descriptor pointer */
} usb_host_dev_info_t;
+/*! @brief Request type */
+typedef enum _usb_host_request_type
+{
+ kRequestDevice = 1U, /*!< Control request object is device */
+ kRequestInterface, /*!< Control request object is interface */
+ kRequestEndpoint, /*!< Control request object is endpoint */
+} usb_host_request_type_t;
+/*! @brief For USB_REQUEST_STANDARD_GET_DESCRIPTOR and USB_REQUEST_STANDARD_SET_DESCRIPTOR */
+typedef struct _usb_host_process_descriptor_param
+{
+ uint8_t descriptorType; /*!< See the usb_spec.h, such as the USB_DESCRIPTOR_TYPE_DEVICE */
+ uint8_t descriptorIndex; /*!< The descriptor index is used to select a specific descriptor (only for configuration
+ and string descriptors) when several descriptors of the same type are implemented in a
+ device */
+ uint8_t languageId; /*!< It specifies the language ID for string descriptors or is reset to zero for other
+ descriptors */
+ uint8_t *descriptorBuffer; /*!< Buffer pointer */
+ uint16_t descriptorLength; /*!< Buffer data length */
+} usb_host_process_descriptor_param_t;
+/*! @brief For USB_REQUEST_STANDARD_CLEAR_FEATURE and USB_REQUEST_STANDARD_SET_FEATURE */
+typedef struct _usb_host_process_feature_param
+{
+ uint8_t requestType; /*!< See the #usb_host_request_type_t */
+ uint8_t featureSelector; /*!< Set/cleared feature */
+ uint8_t interfaceOrEndpoint; /*!< Interface or end pointer */
+} usb_host_process_feature_param_t;
+/*! @brief For USB_REQUEST_STANDARD_GET_INTERFACE */
+typedef struct _usb_host_get_interface_param
+{
+ uint8_t interface; /*!< Interface number */
+ uint8_t *alternateInterfaceBuffer; /*!< Save the transfer result */
+} usb_host_get_interface_param_t;
+/*! @brief For USB_REQUEST_STANDARD_GET_STATUS */
+typedef struct _usb_host_get_status_param
+{
+ uint16_t statusSelector; /*!< Interface number, the end pointer number or OTG status selector */
+ uint8_t requestType; /*!< See the #usb_host_request_type_t */
+ uint8_t *statusBuffer; /*!< Save the transfer result */
+} usb_host_get_status_param_t;
+
+/*! @brief For USB_REQUEST_STANDARD_SET_INTERFACE */
+typedef struct _usb_host_set_interface_param
+{
+ uint8_t alternateSetting; /*!< Alternate setting value */
+ uint8_t interface; /*!< Interface number */
+} usb_host_set_interface_param_t;
+
+/*! @brief For USB_REQUEST_STANDARD_SYNCH_FRAME */
+typedef struct _usb_host_synch_frame_param
+{
+ uint8_t endpoint; /*!< Endpoint number */
+ uint8_t *frameNumberBuffer; /*!< Frame number data buffer */
+} usb_host_synch_frame_param_t;
/*!
* @brief Host callback function typedef.
*
@@ -243,8 +284,8 @@ typedef struct _usb_host_pipe_init
/*! @brief Cancel transfer parameter structure */
typedef struct _usb_host_cancel_param
{
- usb_host_pipe_handle pipeHandle; /*!< Cancelling pipe handle*/
- usb_host_transfer_t *transfer; /*!< Cancelling transfer*/
+ usb_host_pipe_handle pipeHandle; /*!< Canceling pipe handle*/
+ usb_host_transfer_t *transfer; /*!< Canceling transfer*/
} usb_host_cancel_param_t;
/*******************************************************************************
@@ -342,7 +383,7 @@ extern usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handl
* @retval kStatus_USB_InvalidParameter The deviceHandle instance don't belong to hostHandle instance.
*/
extern usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle);
-
+#if (defined(USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI > 0U))
/*!
* @brief KHCI task function.
*
@@ -353,7 +394,8 @@ extern usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_
* @param[in] hostHandle The host handle.
*/
extern void USB_HostKhciTaskFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U))
/*!
* @brief EHCI task function.
*
@@ -364,7 +406,8 @@ extern void USB_HostKhciTaskFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostEhciTaskFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U))
/*!
* @brief OHCI task function.
*
@@ -375,7 +418,8 @@ extern void USB_HostEhciTaskFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostOhciTaskFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U))
/*!
* @brief IP3516HS task function.
*
@@ -386,7 +430,8 @@ extern void USB_HostOhciTaskFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostIp3516HsTaskFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI > 0U))
/*!
* @brief Device KHCI ISR function.
*
@@ -395,7 +440,8 @@ extern void USB_HostIp3516HsTaskFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostKhciIsrFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U))
/*!
* @brief Device EHCI ISR function.
*
@@ -404,7 +450,8 @@ extern void USB_HostKhciIsrFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostEhciIsrFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U))
/*!
* @brief Device OHCI ISR function.
*
@@ -413,7 +460,8 @@ extern void USB_HostEhciIsrFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostOhciIsrFunction(void *hostHandle);
-
+#endif
+#if (defined(USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U))
/*!
* @brief Device IP3516HS ISR function.
*
@@ -422,7 +470,7 @@ extern void USB_HostOhciIsrFunction(void *hostHandle);
* @param[in] hostHandle The host handle.
*/
extern void USB_HostIp3516HsIsrFunction(void *hostHandle);
-
+#endif
/*! @}*/
/*!
@@ -566,7 +614,7 @@ extern usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_tr
* This function sends the USB standard request packet.
*
* @param[in] deviceHandle The device handle for control transfer.
- * @param[in] usbRequest A USB standard request code. Se the usb_spec.h.
+ * @param[in] usbRequest A USB standard request code. See the usb_spec.h.
* @param[in] transfer The used transfer.
* @param[in] param The parameter structure is different for different request, see
* usb_host_framework.h.
@@ -694,10 +742,10 @@ extern usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle,
/*!
* @brief Update the lpm param.
*
- * The function is used to configuure the lpm token.
+ * The function is used to configure the lpm token.
*
* @param[in] hostHandle The host handle.
- * @param[in] lpmParam HIRD vaule and whether enable remotewakeup.
+ * @param[in] lpmParam HIRD value and whether enable remotewakeup.
*
*/
extern usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam);
@@ -715,6 +763,19 @@ extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t ti
#endif
+#if ((defined(USB_HOST_CONFIG_BATTERY_CHARGER)) && (USB_HOST_CONFIG_BATTERY_CHARGER > 0U))
+/*!
+ * @brief Set the charger type. It is only supported on RT600 currently.
+ *
+ * The set charger type becomes valid in next attach.
+ *
+ * @param[in] hostHandle The host handle.
+ * @param[in] type.
+ *
+ */
+extern usb_status_t USB_HostSetChargerType(usb_host_handle hostHandle, uint8_t type);
+#endif
+
/*! @}*/
#ifdef __cplusplus
@@ -723,4 +784,4 @@ extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t ti
/*! @}*/
-#endif /* _USB_HOST_H_ */
+#endif /* _USB_HOST_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c
index 42b16e071e..1989d6ec76 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c
@@ -1,46 +1,28 @@
/*
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016,2019 NXP
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
-#include
+#include
#include "usb_host.h"
#include "usb_host_hci.h"
#include "usb_host_devices.h"
-
+#include "usb_host_framework.h"
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
#include "usb_host_hub.h"
+#include "usb_host_hub_app.h"
#endif /* USB_HOST_CONFIG_HUB */
/*******************************************************************************
* Definitions
******************************************************************************/
+#ifndef USB_HOST_CONFIG_MAX_CONFIGURATION_DESCRIPTOR_LENGTH
+#define USB_HOST_CONFIG_MAX_CONFIGURATION_DESCRIPTOR_LENGTH (5000U)
+#endif
+
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -70,7 +52,7 @@ static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInsta
*
* @return kStatus_USB_Success or error codes
*/
-static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance);
+static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance, uint32_t dataLength);
/*!
* @brief notify the application event, the callback is registered when initializing host.
@@ -80,7 +62,10 @@ static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceIn
*
* @return kStatus_USB_Success or error codes
*/
-static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode);
+static usb_status_t USB_HostNotifyDevice(usb_host_handle hostHandle,
+ usb_host_device_instance_t *deviceInstance,
+ uint32_t eventCode,
+ uint32_t eventParameter);
/*!
* @brief allocate one address.
@@ -140,68 +125,57 @@ static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb
*/
static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType);
-extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance,
- usb_host_transfer_t *transfer,
- void *param);
-extern usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance,
- usb_host_transfer_t *transfer,
- void *param);
-extern usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance,
- usb_host_transfer_t *transfer,
- uint8_t *buffer,
- uint32_t bufferLen);
-
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
-extern usb_status_t USB_HostHubDeviceEvent(usb_host_handle hostHandle,
- usb_device_handle deviceHandle,
- usb_host_configuration_handle configurationHandle,
- uint32_t eventCode);
-
-extern uint32_t USB_HostHubGetHsHubNumber(usb_host_handle hostHandle, uint8_t parentHubNo);
-
-extern uint32_t USB_HostHubGetHsHubPort(usb_host_handle hostHandle, uint8_t parentHubNo, uint8_t parentPortNo);
-
-extern usb_status_t USB_HostHubRemovePort(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber);
-
#endif
/*******************************************************************************
* Variables
******************************************************************************/
-extern usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST];
-
/*! @brief enumeration step process array */
-static const usb_host_enum_process_entry_t s_EnumEntries[] = \
-{
+static const usb_host_enum_process_entry_t s_EnumEntries[] = {
/* kStatus_dev_initial */
{
- 0, 0, NULL,
+ kStatus_DEV_Notinit,
+ kStatus_DEV_Notinit,
+ NULL,
},
/* kStatus_DEV_GetDes8 */
{
- kStatus_DEV_SetAddress, kStatus_DEV_GetDes8, USB_HostProcessCallback,
+ kStatus_DEV_SetAddress,
+ kStatus_DEV_GetDes8,
+ USB_HostProcessCallback,
},
/* kStatus_DEV_SetAddress */
{
- kStatus_DEV_GetDes, kStatus_DEV_SetAddress, USB_HostProcessCallback,
+ kStatus_DEV_GetDes,
+ kStatus_DEV_SetAddress,
+ USB_HostProcessCallback,
},
/* kStatus_DEV_GetDes */
{
- kStatus_DEV_GetCfg9, kStatus_DEV_GetDes, NULL,
+ kStatus_DEV_GetCfg9,
+ kStatus_DEV_GetDes,
+ NULL,
},
/* kStatus_DEV_GetCfg9 */
{
- kStatus_DEV_GetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback,
+ kStatus_DEV_GetCfg,
+ kStatus_DEV_GetCfg9,
+ USB_HostProcessCallback,
},
/* kStatus_DEV_GetCfg */
{
- kStatus_DEV_SetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback,
+ kStatus_DEV_SetCfg,
+ kStatus_DEV_GetCfg9,
+ USB_HostProcessCallback,
},
/* kStatus_DEV_SetCfg */
{
- kStatus_DEV_EnumDone, kStatus_DEV_SetCfg, NULL,
+ kStatus_DEV_EnumDone,
+ kStatus_DEV_SetCfg,
+ NULL,
},
};
@@ -211,69 +185,66 @@ static const usb_host_enum_process_entry_t s_EnumEntries[] = \
static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status)
{
- uint8_t nextStep = 0;
+ /* 0 - retry current transfer, 1 - transfer success process,
+ * 2 - retry whole process, 3 - fail process
+ */
+ uint8_t nextStep = 0U;
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)param;
+ usb_status_t failReason = kStatus_USB_Success;
+ uint32_t dataLength;
- USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */
+ dataLength = transfer->transferSofar;
+ (void)USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */
if (status == kStatus_USB_Success)
{
- nextStep = 1;
+ nextStep = 1U;
}
else if (status == kStatus_USB_TransferStall)
{
#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
- usb_echo("no response from device\r\n");
-#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */
- if (deviceInstance->stallRetries > 0) /* retry same transfer when stall */
+ (void)usb_echo("no response from device\r\n");
+#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */
+ if (deviceInstance->stallRetries > 0U) /* retry same transfer when stall */
{
+ nextStep = 0U;
deviceInstance->stallRetries--;
}
- else /* process next state when all retries stall */
+ else
{
- nextStep = 1;
+ failReason = kStatus_USB_TransferFailed;
+ nextStep = 2U;
}
}
else if (status == kStatus_USB_TransferCancel)
{
- return;
+ failReason = kStatus_USB_TransferCancel;
+ nextStep = 3U;
}
else
{
- if (deviceInstance->enumRetries > 0) /* next whole retry */
- {
- deviceInstance->enumRetries--;
- deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES;
- deviceInstance->configurationValue = 0;
- deviceInstance->state = kStatus_DEV_GetDes8;
- }
- else
- {
-#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
- usb_echo("Device No Response\r\n");
-#endif
- return;
- }
+ failReason = kStatus_USB_TransferFailed;
+ nextStep = 2U;
}
- if (nextStep == 1)
+ if (nextStep == 1U)
{
deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES;
- if (s_EnumEntries[deviceInstance->state - 1].process == NULL)
+ if (s_EnumEntries[deviceInstance->state - 1U].process == NULL)
{
- deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; /* next state */
+ deviceInstance->state = (uint8_t)s_EnumEntries[deviceInstance->state - 1U].successState; /* next state */
}
else
{
- status = s_EnumEntries[deviceInstance->state - 1].process(
- deviceInstance); /* process the previous state result */
+ status = s_EnumEntries[deviceInstance->state - 1U].process(
+ deviceInstance, dataLength); /* process the previous state result */
if (status == kStatus_USB_Success) /* process success */
{
- deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState;
+ deviceInstance->state = (uint8_t)s_EnumEntries[deviceInstance->state - 1U].successState;
}
else if (status == kStatus_USB_Retry) /* need retry */
{
- deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].retryState;
+ deviceInstance->state = (uint8_t)s_EnumEntries[deviceInstance->state - 1U].retryState;
}
else if (status == kStatus_USB_NotSupported) /* device don't suport by the application */
{
@@ -281,30 +252,48 @@ static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t
}
else /* process error, next retry */
{
- if (deviceInstance->enumRetries > 0) /* next whole retry */
- {
- deviceInstance->enumRetries--;
- deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES;
- deviceInstance->configurationValue = 0;
- deviceInstance->state = kStatus_DEV_GetDes8;
- }
- else
- {
-#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
- usb_echo("Device No Response\r\n");
-#endif
- return; /* unrecoverable fail */
- }
+ /* kStatus_USB_Error or kStatus_USB_AllocFail */
+ failReason = status;
+ nextStep = 2U;
}
}
}
- if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success) /* process the new state */
+ if (nextStep == 2U)
{
-#ifdef HOST_ECHO
- usb_echo("enumation setup error\r\n");
+ if (deviceInstance->enumRetries > 0U) /* next whole retry */
+ {
+ deviceInstance->enumRetries--;
+ deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES;
+ deviceInstance->configurationValue = 0U;
+ deviceInstance->state = (uint8_t)kStatus_DEV_GetDes8;
+ }
+ else
+ {
+#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
+ usb_echo("Device No Response\r\n");
#endif
- return;
+ nextStep = 3U;
+ }
+ }
+
+ /* process the state */
+ if (nextStep != 3U)
+ {
+ if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success)
+ {
+#ifdef HOST_ECHO
+ usb_echo("enumation setup error\r\n");
+#endif
+ failReason = kStatus_USB_Error;
+ nextStep = 3U;
+ }
+ }
+
+ if (nextStep == 3U)
+ {
+ (void)USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance, (uint32_t)kUSB_HostEventEnumerationFail,
+ (uint32_t)failReason);
}
}
@@ -313,9 +302,11 @@ static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInsta
usb_status_t status = kStatus_USB_Success;
usb_host_process_descriptor_param_t getDescriptorParam;
usb_host_transfer_t *transfer;
+ usb_host_device_enumeration_status_t state;
/* malloc transfer */
- if (deviceInstance->state != kStatus_DEV_EnumDone)
+ state = (usb_host_device_enumeration_status_t)deviceInstance->state;
+ if (state != kStatus_DEV_EnumDone)
{
if (USB_HostMallocTransfer(deviceInstance->hostHandle, &transfer) != kStatus_USB_Success)
{
@@ -324,29 +315,29 @@ static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInsta
#endif
return kStatus_USB_Error;
}
- transfer->callbackFn = USB_HostEnumerationTransferCallback;
+ transfer->callbackFn = USB_HostEnumerationTransferCallback;
transfer->callbackParam = deviceInstance;
/* reset transfer fields */
- transfer->setupPacket->bmRequestType = 0x00;
- transfer->setupPacket->wIndex = 0;
- transfer->setupPacket->wLength = 0;
- transfer->setupPacket->wValue = 0;
+ transfer->setupPacket->bmRequestType = 0x00U;
+ transfer->setupPacket->wIndex = 0U;
+ transfer->setupPacket->wLength = 0U;
+ transfer->setupPacket->wValue = 0U;
}
- switch (deviceInstance->state)
+ switch (state)
{
case kStatus_DEV_GetDes8:
case kStatus_DEV_GetDes: /* get descriptor state */
getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t);
- if (deviceInstance->state == kStatus_DEV_GetDes8)
+ if (deviceInstance->state == (uint8_t)kStatus_DEV_GetDes8)
{
- getDescriptorParam.descriptorLength = 8;
+ getDescriptorParam.descriptorLength = 8U;
}
getDescriptorParam.descriptorBuffer = (uint8_t *)deviceInstance->deviceDescriptor;
- getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE;
- getDescriptorParam.descriptorIndex = 0;
- getDescriptorParam.languageId = 0;
+ getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE;
+ getDescriptorParam.descriptorIndex = 0U;
+ getDescriptorParam.languageId = 0U;
transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
@@ -359,10 +350,10 @@ static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInsta
case kStatus_DEV_GetCfg9: /* get 9 bytes configuration state */
getDescriptorParam.descriptorBuffer = deviceInstance->enumBuffer;
- getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE;
- getDescriptorParam.descriptorIndex = deviceInstance->configurationValue;
+ getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE;
+ getDescriptorParam.descriptorIndex = deviceInstance->configurationValue;
getDescriptorParam.descriptorLength = 9;
- getDescriptorParam.languageId = 0;
+ getDescriptorParam.languageId = 0;
transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
@@ -371,10 +362,10 @@ static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInsta
case kStatus_DEV_GetCfg: /* get configuration state */
getDescriptorParam.descriptorBuffer = deviceInstance->configurationDesc;
- getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE;
- getDescriptorParam.descriptorIndex = deviceInstance->configurationValue;
+ getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE;
+ getDescriptorParam.descriptorIndex = deviceInstance->configurationValue;
getDescriptorParam.descriptorLength = deviceInstance->configurationLen;
- getDescriptorParam.languageId = 0;
+ getDescriptorParam.languageId = 0;
transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
@@ -385,52 +376,71 @@ static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInsta
transfer->setupPacket->wValue =
USB_SHORT_TO_LITTLE_ENDIAN(deviceInstance->configuration.configurationDesc->bConfigurationValue);
transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_CONFIGURATION;
- status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0);
+ status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0);
break;
case kStatus_DEV_EnumDone: /* enumeration done state */
- status = USB_HostNotifyDevice(deviceInstance,
- kUSB_HostEventEnumerationDone); /* notify device enumeration done */
+ /* notify device enumeration done */
+ status = USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance,
+ (uint32_t)kUSB_HostEventEnumerationDone, (uint32_t)kStatus_USB_Success);
if (status == kStatus_USB_Success)
{
- deviceInstance->state = kStatus_DEV_AppUsed;
+ deviceInstance->state = (uint8_t)kStatus_DEV_AppUsed;
}
break;
default:
+ /*no action*/
break;
}
return status;
}
-static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance)
+static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance, uint32_t dataLength)
{
usb_host_pipe_t *pipe = (usb_host_pipe_t *)deviceInstance->controlPipe;
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_descriptor_configuration_t *configureDesc;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle;
+ void *temp;
+ usb_host_device_enumeration_status_t state;
- switch (deviceInstance->state)
+ state = (usb_host_device_enumeration_status_t)deviceInstance->state;
+ switch (state)
{
case kStatus_DEV_GetDes8: /* process get 8 bytes descriptor result */
+ if (dataLength != 8u)
+ {
+ return kStatus_USB_Error;
+ }
pipe->maxPacketSize = deviceInstance->deviceDescriptor->bMaxPacketSize0;
- hostInstance->controllerTable->controllerIoctl(
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
+ (void)hostInstance->controllerTable->controllerIoctl(
hostInstance->controllerHandle, kUSB_HostUpdateControlPacketSize, deviceInstance->controlPipe);
break;
case kStatus_DEV_SetAddress: /* process set address result */
deviceInstance->setAddress = deviceInstance->allocatedAddress;
- hostInstance->controllerTable->controllerIoctl(
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
+ (void)hostInstance->controllerTable->controllerIoctl(
hostInstance->controllerHandle, kUSB_HostUpdateControlEndpointAddress, deviceInstance->controlPipe);
break;
- case kStatus_DEV_GetDes: /* process set address result */
- /* NULL */
+ case kStatus_DEV_GetDes: /* process get full device descriptor result */
+ if (dataLength != sizeof(usb_descriptor_device_t))
+ {
+ return kStatus_USB_Error;
+ }
break;
case kStatus_DEV_GetCfg9: /* process get 9 bytes configuration result */
- configureDesc = (usb_descriptor_configuration_t *)&deviceInstance->enumBuffer[0];
+ if (dataLength != 9u)
+ {
+ return kStatus_USB_Error;
+ }
+ temp = (void *)&deviceInstance->enumBuffer[0];
+ configureDesc = (usb_descriptor_configuration_t *)temp;
deviceInstance->configurationLen = USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(configureDesc->wTotalLength);
if (deviceInstance->configurationDesc != NULL)
@@ -438,19 +448,25 @@ static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceIn
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
SDK_Free(deviceInstance->configurationDesc);
#else
- USB_OsaMemoryFree(deviceInstance->configurationDesc);
+ OSA_MemoryFree(deviceInstance->configurationDesc);
#endif
deviceInstance->configurationDesc = NULL;
}
+
+ /* fix misra 4.14 */
+ if (deviceInstance->configurationLen > USB_HOST_CONFIG_MAX_CONFIGURATION_DESCRIPTOR_LENGTH)
+ {
+ return kStatus_USB_Error;
+ }
/* for KHCI, the start address and the length should be 4 byte align */
- if ((deviceInstance->configurationLen & 0x03) != 0)
+ if ((deviceInstance->configurationLen & 0x03U) != 0U)
{
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
deviceInstance->configurationDesc =
- (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4, USB_CACHE_LINESIZE);
+ (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFCu) + 4, USB_CACHE_LINESIZE);
#else
deviceInstance->configurationDesc =
- (uint8_t *)USB_OsaMemoryAllocate((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4);
+ (uint8_t *)OSA_MemoryAllocate((((uint32_t)deviceInstance->configurationLen) & 0xFFFCU) + 4UL);
#endif
}
else
@@ -459,18 +475,22 @@ static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceIn
deviceInstance->configurationDesc =
(uint8_t *)SDK_Malloc(deviceInstance->configurationLen, USB_CACHE_LINESIZE);
#else
- deviceInstance->configurationDesc = (uint8_t *)USB_OsaMemoryAllocate(deviceInstance->configurationLen);
+ deviceInstance->configurationDesc = (uint8_t *)OSA_MemoryAllocate(deviceInstance->configurationLen);
#endif
}
if (deviceInstance->configurationDesc == NULL)
{
- return kStatus_USB_Error;
+ return kStatus_USB_AllocFail;
}
break;
- case kStatus_DEV_GetCfg: /* process get cofiguration result */
- if (((usb_descriptor_configuration_t *)deviceInstance->configurationDesc)->bMaxPower >
- USB_HOST_CONFIG_MAX_POWER)
+ case kStatus_DEV_GetCfg: /* process get configuration result */
+ if (dataLength != deviceInstance->configurationLen)
+ {
+ return kStatus_USB_Error;
+ }
+ temp = (void *)deviceInstance->configurationDesc;
+ if (((usb_descriptor_configuration_t *)temp)->bMaxPower > USB_HOST_CONFIG_MAX_POWER)
{
return kStatus_USB_Error;
}
@@ -481,7 +501,8 @@ static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceIn
return kStatus_USB_Error;
}
- status = USB_HostNotifyDevice(deviceInstance, kUSB_HostEventAttach);
+ status = USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance, (uint32_t)kUSB_HostEventAttach,
+ (uint32_t)kStatus_USB_Success);
if (status != kStatus_USB_Success)
{
@@ -492,8 +513,9 @@ static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceIn
}
else
{
- USB_HostNotifyDevice(deviceInstance,
- kUSB_HostEventNotSupported); /* notify application device is not supported */
+ /* notify application device is not supported */
+ (void)USB_HostNotifyDevice(deviceInstance->hostHandle, deviceInstance,
+ (uint32_t)kUSB_HostEventNotSupported, (uint32_t)kStatus_USB_Success);
return kStatus_USB_NotSupported;
}
}
@@ -504,13 +526,17 @@ static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceIn
break;
default:
+ /*no action*/
break;
}
return status;
}
-static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode)
+static usb_status_t USB_HostNotifyDevice(usb_host_handle hostHandle,
+ usb_host_device_instance_t *deviceInstance,
+ uint32_t eventCode,
+ uint32_t eventParameter)
{
usb_host_instance_t *hostInstance;
usb_status_t status1 = kStatus_USB_Error;
@@ -521,34 +547,37 @@ static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInsta
uint8_t interfaceIndex;
#endif /* USB_HOST_CONFIG_HUB */
+ eventCode = (((uint32_t)eventParameter << 16U) | (uint32_t)eventCode);
+ hostInstance = (usb_host_instance_t *)hostHandle;
if (deviceInstance == NULL)
{
+ (void)hostInstance->deviceCallback(NULL, NULL, eventCode);
return kStatus_USB_InvalidHandle;
}
- hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle;
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
- haveHub = 0;
- haveNoHub = 0;
- for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex)
+ haveHub = 0U;
+ haveNoHub = 0U;
+ for (interfaceIndex = 0U; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex)
{
if (((usb_descriptor_interface_t *)deviceInstance->configuration.interfaceList[interfaceIndex].interfaceDesc)
->bInterfaceClass == USB_HOST_HUB_CLASS_CODE)
{
- haveHub = 1;
+ haveHub = 1U;
}
else
{
- haveNoHub = 1;
+ haveNoHub = 1U;
}
}
- if ((haveNoHub == 1) && (hostInstance->deviceCallback != NULL))
+ if ((hostInstance->deviceCallback != NULL) &&
+ ((haveNoHub == 1U) || (deviceInstance->configuration.interfaceCount == 0U)))
{
- status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration,
- eventCode); /* notify application event */
+ /* call host callback function, function is initialized in USB_HostInit */
+ status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, eventCode);
}
- if (haveHub)
+ if (0U != haveHub)
{
status2 = USB_HostHubDeviceEvent(hostInstance, deviceInstance, &deviceInstance->configuration,
eventCode); /* notify hub event */
@@ -558,7 +587,7 @@ static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInsta
{
return kStatus_USB_Success;
}
- else if (eventCode == kUSB_HostEventAttach) /* attach event */
+ else if (eventCode == (uint32_t)kUSB_HostEventAttach) /* attach event */
{
status1 = kStatus_USB_NotSupported;
}
@@ -569,8 +598,8 @@ static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInsta
#else
if (hostInstance->deviceCallback != NULL)
{
- status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration,
- eventCode); /* call host callback function */
+ /* call host callback function, function is initialized in USB_HostInit */
+ status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, eventCode);
}
#endif
return status1;
@@ -578,24 +607,24 @@ static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInsta
static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance)
{
- uint8_t address = 0;
+ uint8_t address = 0U;
uint8_t addressIndex;
uint8_t addressBitIndex;
- for (addressIndex = 0; addressIndex < 8; ++addressIndex) /* find the idle address postion byte */
+ for (addressIndex = 0U; addressIndex < 8U; ++addressIndex) /* find the idle address position byte */
{
- if (hostInstance->addressBitMap[addressIndex] != 0xFF)
+ if (hostInstance->addressBitMap[addressIndex] != 0xFFU)
{
break;
}
}
- if (addressIndex < 8)
+ if (addressIndex < 8U)
{
- for (addressBitIndex = 0; addressBitIndex < 8; ++addressBitIndex) /* find the idle address position bit */
+ for (addressBitIndex = 0U; addressBitIndex < 8U; ++addressBitIndex) /* find the idle address position bit */
{
- if (!(hostInstance->addressBitMap[addressIndex] & (0x01u << addressBitIndex)))
+ if (0U == (hostInstance->addressBitMap[addressIndex] & (0x01U << addressBitIndex)))
{
- hostInstance->addressBitMap[addressIndex] |= (0x01u << addressBitIndex); /* set the allocated bit */
- address = addressIndex * 8 + addressBitIndex + 1; /* the address minimum is 1 */
+ hostInstance->addressBitMap[addressIndex] |= (0x01U << addressBitIndex); /* set the allocated bit */
+ address = addressIndex * 8U + addressBitIndex + 1U; /* the address minimum is 1 */
break;
}
}
@@ -605,10 +634,10 @@ static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance)
static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address)
{
- USB_HostLock();
- hostInstance->addressBitMap[(uint32_t)(address - 1) >> 3] &=
- (~(0x01u << (((uint32_t)address - 1) & 0x07U))); /* reset the allocated bit */
- USB_HostUnlock();
+ (void)USB_HostLock();
+ hostInstance->addressBitMap[((uint32_t)address - 1U) >> 3U] &=
+ (~(0x01U << (((uint32_t)address - 1U) & 0x07U))); /* reset the allocated bit */
+ (void)USB_HostUnlock();
}
static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle)
@@ -640,7 +669,7 @@ static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb
prevInstance->next = currentInstance->next;
return kStatus_USB_Success;
}
- prevInstance = currentInstance;
+ prevInstance = currentInstance;
currentInstance = currentInstance->next;
}
@@ -660,13 +689,13 @@ static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb
}
#endif
/* release device's address */
- if (deviceInstance->setAddress != 0)
+ if (deviceInstance->setAddress != 0U)
{
USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->setAddress);
}
else
{
- if (deviceInstance->allocatedAddress != 0)
+ if (deviceInstance->allocatedAddress != 0U)
{
USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->allocatedAddress);
}
@@ -675,7 +704,7 @@ static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb
/* close control pipe */
if (deviceInstance->controlPipe != NULL)
{
- USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL);
+ (void)USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL);
if (USB_HostClosePipe(hostInstance, deviceInstance->controlPipe) != kStatus_USB_Success)
{
#ifdef HOST_ECHO
@@ -691,7 +720,7 @@ static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
SDK_Free(deviceInstance->configurationDesc);
#else
- USB_OsaMemoryFree(deviceInstance->configurationDesc);
+ OSA_MemoryFree(deviceInstance->configurationDesc);
#endif
}
@@ -701,20 +730,20 @@ static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
SDK_Free(deviceInstance->deviceDescriptor);
#else
- USB_OsaMemoryFree(deviceInstance->deviceDescriptor);
+ OSA_MemoryFree(deviceInstance->deviceDescriptor);
#endif
/* free device instance buffer */
- USB_OsaMemoryFree(deviceInstance);
+ OSA_MemoryFree(deviceInstance);
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
/* enable controller attach if root hub */
- if (level == 1)
+ if (level == 1U)
{
- USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach);
+ (void)USB_HostControlBus(hostInstance, (uint8_t)kUSB_HostBusEnableAttach);
}
#else
/* enable controller attach */
- USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach);
+ USB_HostControlBus(hostInstance, (uint8_t)kUSB_HostBusEnableAttach);
#endif
}
@@ -726,35 +755,39 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
usb_host_interface_t *interfaceParse = NULL;
usb_host_ep_t *epParse;
uint8_t *buffer;
+ void *temp;
if (deviceHandle == NULL)
{
return kStatus_USB_InvalidParameter;
}
- buffer = (uint8_t *)&deviceInstance->configuration;
+ temp = (void *)&deviceInstance->configuration;
+ buffer = (uint8_t *)temp;
/* clear the previous parse result, note: end_pos means buffer index here*/
- for (endPos = 0; endPos < sizeof(usb_host_configuration_t); endPos++)
+ for (endPos = 0U; endPos < sizeof(usb_host_configuration_t); endPos++)
{
- buffer[endPos] = 0;
+ buffer[endPos] = 0U;
}
- for (endPos = 0; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos)
+ for (endPos = 0U; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos)
{
- deviceInstance->interfaceStatus[endPos] = 0;
+ deviceInstance->interfaceStatus[endPos] = 0U;
}
/* parse configuration descriptor */
- unionDes = (usb_descriptor_union_t *)deviceInstance->configurationDesc;
- endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen);
+ temp = (void *)deviceInstance->configurationDesc;
+ unionDes = (usb_descriptor_union_t *)temp;
+ endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen);
if ((unionDes->common.bLength == USB_DESCRIPTOR_LENGTH_CONFIGURE) &&
(unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_CONFIGURE))
{
/* configuration descriptor */
- deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)unionDes;
+ temp = (void *)unionDes;
+ deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)temp;
deviceInstance->configuration.configurationExtensionLength = 0;
- deviceInstance->configuration.configurationExtension = NULL;
- deviceInstance->configuration.interfaceCount = 0;
+ deviceInstance->configuration.configurationExtension = NULL;
+ deviceInstance->configuration.interfaceCount = 0;
unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength);
while ((uint32_t)unionDes < endPos)
{
@@ -764,8 +797,8 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
{
deviceInstance->configuration.configurationExtension = (uint8_t *)unionDes;
}
- if ((unionDes->common.bDescriptorType == 0x00) ||
- (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */
+ if ((unionDes->common.bDescriptorType == 0x00U) ||
+ (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -779,17 +812,17 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
}
/* interface descriptor */
- deviceInstance->configuration.interfaceCount = 0;
+ deviceInstance->configuration.interfaceCount = 0U;
while ((uint32_t)unionDes < endPos)
{
if (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE)
{
- if (unionDes->interface.bAlternateSetting == 0x00)
+ if (unionDes->interface.bAlternateSetting == 0x00U)
{
if (deviceInstance->configuration.interfaceCount >= USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE)
{
-#ifdef HOST_ECHO
- usb_echo(
+#if (((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) || defined(HOST_ECHO))
+ (void)usb_echo(
"Unsupported Device attached\r\n too many interfaces in one configuration, please increase "
"the USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE value\n");
#endif
@@ -798,13 +831,13 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
interfaceParse =
&deviceInstance->configuration.interfaceList[deviceInstance->configuration.interfaceCount];
deviceInstance->configuration.interfaceCount++;
- interfaceParse->alternateSettingNumber = 0;
- interfaceParse->epCount = 0;
- interfaceParse->interfaceDesc = &unionDes->interface;
+ interfaceParse->alternateSettingNumber = 0;
+ interfaceParse->epCount = 0;
+ interfaceParse->interfaceDesc = &unionDes->interface;
interfaceParse->interfaceExtensionLength = 0;
- interfaceParse->interfaceExtension = NULL;
- interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber;
- if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */
+ interfaceParse->interfaceExtension = NULL;
+ interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber;
+ if (unionDes->common.bLength == 0x00U) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -818,8 +851,8 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
{
interfaceParse->interfaceExtension = (uint8_t *)unionDes;
}
- if ((unionDes->common.bDescriptorType == 0x00) ||
- (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */
+ if ((unionDes->common.bDescriptorType == 0x00U) ||
+ (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -833,7 +866,7 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
}
/* endpoint descriptor */
- if (interfaceParse->interfaceDesc->bNumEndpoints != 0)
+ if (interfaceParse->interfaceDesc->bNumEndpoints != 0U)
{
if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) ||
(interfaceParse->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP))
@@ -854,11 +887,13 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
#endif
return kStatus_USB_Error;
}
- epParse = (usb_host_ep_t *)&interfaceParse->epList[interfaceParse->epCount];
- epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes;
- epParse->epExtensionLength = 0;
- epParse->epExtension = NULL;
- if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */
+ temp = (void *)&interfaceParse->epList[interfaceParse->epCount];
+ epParse = (usb_host_ep_t *)temp;
+ temp = (void *)unionDes;
+ epParse->epDesc = (usb_descriptor_endpoint_t *)temp;
+ epParse->epExtensionLength = 0U;
+ epParse->epExtension = NULL;
+ if (unionDes->common.bLength == 0x00U) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -872,8 +907,8 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
{
epParse->epExtension = (uint8_t *)unionDes;
}
- if ((unionDes->common.bDescriptorType == 0x00) ||
- (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */
+ if ((unionDes->common.bDescriptorType == 0x00U) ||
+ (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -900,7 +935,7 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
{
interfaceParse->interfaceExtension = (uint8_t *)unionDes;
}
- if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */
+ if (unionDes->common.bLength == 0x00U) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -910,8 +945,8 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
{
if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)
{
- if ((unionDes->common.bDescriptorType == 0x00) ||
- (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */
+ if ((unionDes->common.bDescriptorType == 0x00U) ||
+ (unionDes->common.bLength == 0x00U)) /* the descriptor data is wrong */
{
return kStatus_USB_Error;
}
@@ -932,9 +967,9 @@ static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle
}
}
- for (endPos = 0; endPos < deviceInstance->configuration.interfaceCount; ++endPos)
+ for (endPos = 0U; endPos < deviceInstance->configuration.interfaceCount; ++endPos)
{
- deviceInstance->interfaceStatus[endPos] = kStatus_interface_Attached;
+ deviceInstance->interfaceStatus[endPos] = (uint8_t)kStatus_interface_Attached;
}
return kStatus_USB_Success;
@@ -988,28 +1023,29 @@ usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle,
#endif
/* Allocate new device instance */
- newInstance = (usb_host_device_instance_t *)USB_OsaMemoryAllocate(sizeof(usb_host_device_instance_t));
+ newInstance = (usb_host_device_instance_t *)OSA_MemoryAllocate(sizeof(usb_host_device_instance_t));
if (newInstance == NULL)
{
#ifdef HOST_ECHO
usb_echo("allocate dev instance fail\r\n");
#endif
+ (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail,
+ (uint32_t)kStatus_USB_AllocFail);
return kStatus_USB_AllocFail;
}
/* new instance fields init */
- newInstance->hostHandle = hostHandle;
- newInstance->speed = speed;
- newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES;
- newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES;
- newInstance->setAddress = 0;
- newInstance->deviceAttachState = kStatus_device_Attached;
+ newInstance->hostHandle = hostHandle;
+ newInstance->speed = speed;
+ newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES;
+ newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES;
+ newInstance->setAddress = 0;
+ newInstance->deviceAttachState = (uint8_t)kStatus_device_Attached;
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
newInstance->deviceDescriptor =
(usb_descriptor_device_t *)SDK_Malloc(sizeof(usb_descriptor_device_t) + 9, USB_CACHE_LINESIZE);
#else
- newInstance->deviceDescriptor =
- (usb_descriptor_device_t *)USB_OsaMemoryAllocate(sizeof(usb_descriptor_device_t) + 9);
+ newInstance->deviceDescriptor = (usb_descriptor_device_t *)OSA_MemoryAllocate(sizeof(usb_descriptor_device_t) + 9U);
#endif
if (newInstance->deviceDescriptor == NULL)
{
@@ -1019,62 +1055,66 @@ usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle,
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
SDK_Free(newInstance->deviceDescriptor);
#else
- USB_OsaMemoryFree(newInstance->deviceDescriptor);
+ OSA_MemoryFree(newInstance->deviceDescriptor);
#endif
- USB_OsaMemoryFree(newInstance);
+ OSA_MemoryFree(newInstance);
+ (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail,
+ (uint32_t)kStatus_USB_AllocFail);
return kStatus_USB_AllocFail;
}
newInstance->enumBuffer = (uint8_t *)((uint8_t *)newInstance->deviceDescriptor + sizeof(usb_descriptor_device_t));
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
- newInstance->hubNumber = hubNumber;
+ newInstance->hubNumber = hubNumber;
newInstance->portNumber = portNumber;
- newInstance->level = level;
+ newInstance->level = level;
- if ((speed != USB_SPEED_HIGH) && (level > 1))
+ if ((speed != USB_SPEED_HIGH) && (level > 1U))
{
- newInstance->hsHubNumber = USB_HostHubGetHsHubNumber(hostHandle, hubNumber);
- newInstance->hsHubPort = USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber);
+ newInstance->hsHubNumber = (uint8_t)USB_HostHubGetHsHubNumber(hostHandle, hubNumber);
+ newInstance->hsHubPort = (uint8_t)USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber);
}
else
{
newInstance->hsHubNumber = hubNumber;
- newInstance->hsHubPort = portNumber;
+ newInstance->hsHubPort = portNumber;
}
#endif /* USB_HOST_CONFIG_HUB */
- USB_HostLock();
+ (void)USB_HostLock();
/* allocate address && insert to the dev list */
address = USB_HostAllocateDeviceAddress(hostInstance);
- if (address == 0)
+ if (address == 0U)
{
#ifdef HOST_ECHO
usb_echo("allocate address fail\r\n");
#endif
- USB_HostUnlock();
+ (void)USB_HostUnlock();
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
SDK_Free(newInstance->deviceDescriptor);
#else
- USB_OsaMemoryFree(newInstance->deviceDescriptor);
+ OSA_MemoryFree(newInstance->deviceDescriptor);
#endif
- USB_OsaMemoryFree(newInstance);
+ OSA_MemoryFree(newInstance);
+ (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail,
+ (uint32_t)kStatus_USB_Error);
return kStatus_USB_Error;
}
newInstance->allocatedAddress = address;
- newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList;
+ newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList;
hostInstance->deviceList = newInstance;
- newInstance->state = kStatus_DEV_Initial;
- USB_HostUnlock();
+ newInstance->state = (uint8_t)kStatus_DEV_Initial;
+ (void)USB_HostUnlock();
/* open control pipe */
- pipeInit.devInstance = newInstance;
- pipeInit.pipeType = USB_ENDPOINT_CONTROL;
- pipeInit.direction = 0;
+ pipeInit.devInstance = newInstance;
+ pipeInit.pipeType = USB_ENDPOINT_CONTROL;
+ pipeInit.direction = 0;
pipeInit.endpointAddress = 0;
- pipeInit.interval = 0;
- pipeInit.maxPacketSize = 8;
+ pipeInit.interval = 0;
+ pipeInit.maxPacketSize = 8;
pipeInit.numberPerUframe = 0;
- pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK;
+ pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK;
if (USB_HostOpenPipe(hostHandle, &newInstance->controlPipe, &pipeInit) != kStatus_USB_Success)
{
/* don't need release resource, resource is released when detach */
@@ -1082,15 +1122,22 @@ usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle,
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
SDK_Free(newInstance->deviceDescriptor);
#else
- USB_OsaMemoryFree(newInstance->deviceDescriptor);
+ OSA_MemoryFree(newInstance->deviceDescriptor);
#endif
- USB_OsaMemoryFree(newInstance);
+ OSA_MemoryFree(newInstance);
+ (void)USB_HostNotifyDevice(hostInstance, NULL, (uint32_t)kUSB_HostEventEnumerationFail,
+ (uint32_t)kStatus_USB_Error);
return kStatus_USB_Error;
}
/* start enumeration */
- newInstance->state = kStatus_DEV_GetDes8;
- USB_HostProcessState(newInstance); /* process enumeration state machine */
+ newInstance->state = (uint8_t)kStatus_DEV_GetDes8;
+ /* process enumeration state machine */
+ if (USB_HostProcessState(newInstance) != kStatus_USB_Success)
+ {
+ (void)USB_HostNotifyDevice(hostInstance, newInstance, (uint32_t)kUSB_HostEventEnumerationFail,
+ (uint32_t)kStatus_USB_Error);
+ }
*deviceHandle = newInstance;
return kStatus_USB_Success;
@@ -1106,7 +1153,7 @@ usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber,
return kStatus_USB_InvalidHandle;
}
- USB_HostLock();
+ (void)USB_HostLock();
/* search for device instance handle */
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList;
@@ -1121,7 +1168,7 @@ usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber,
#else
deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList;
#endif
- USB_HostUnlock();
+ (void)USB_HostUnlock();
if (deviceInstance != NULL)
{
return USB_HostDetachDeviceInternal(hostHandle, deviceInstance); /* device instance detach */
@@ -1132,31 +1179,33 @@ usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber,
usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle)
{
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
+ usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if ((hostHandle == NULL) || (deviceHandle == NULL))
{
return kStatus_USB_InvalidHandle;
}
- deviceInstance->deviceAttachState = kStatus_device_Detached; /* mark the device is detached from host */
+ deviceInstance->deviceAttachState = (uint8_t)kStatus_device_Detached; /* mark the device is detached from host */
- if (deviceInstance->state >= kStatus_DEV_Initial) /* device instance is valid */
+ if (deviceInstance->state >= (uint8_t)kStatus_DEV_Initial) /* device instance is valid */
{
/* detach internally */
- if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeration is not done */
+ if (deviceInstance->state < (uint8_t)kStatus_DEV_AppUsed) /* enumeration is not done */
{
if (deviceInstance->controlPipe != NULL)
{
- USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL);
+ (void)USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL);
}
/* remove device instance from host */
- USB_HostRemoveDeviceInstance(hostInstance, deviceInstance);
+ (void)USB_HostRemoveDeviceInstance(hostInstance, deviceInstance);
USB_HostReleaseDeviceResource(hostInstance, deviceInstance);
}
- else /* enumeration has be done and notifed application */
+ else /* enumeration has be done and notified application */
{
- USB_HostNotifyDevice(deviceInstance, kUSB_HostEventDetach); /* notify application device detach */
+ /* notify application device detach */
+ (void)USB_HostNotifyDevice(hostInstance, deviceInstance, (uint32_t)kUSB_HostEventDetach,
+ (uint32_t)kStatus_USB_Success);
}
}
@@ -1165,7 +1214,7 @@ usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device
uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle)
{
- return deviceHandle ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0;
+ return (NULL != deviceHandle) ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0U;
}
usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle)
@@ -1183,7 +1232,7 @@ usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handl
searchDev = searchDev->next;
}
- if (searchDev)
+ if (NULL != searchDev)
{
return kStatus_USB_Success;
}
@@ -1192,14 +1241,14 @@ usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handl
static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if (hostHandle == NULL)
{
return kStatus_USB_InvalidHandle;
}
-
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl,
&controlType);
@@ -1209,7 +1258,7 @@ static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t contr
usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle)
{
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- usb_host_instance_t *hostInstance = NULL;
+ usb_host_instance_t *hostInstance = NULL;
uint8_t interfaceIndex;
uint8_t index = 0;
@@ -1219,11 +1268,11 @@ usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_hos
}
hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle;
- USB_HostLock();
+ (void)USB_HostLock();
/* check host_instance valid? */
for (; index < USB_HOST_CONFIG_MAX_HOST; ++index)
{
- if ((g_UsbHostInstance[index].occupied == 1) &&
+ if ((g_UsbHostInstance[index].occupied == 1U) &&
((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance)))
{
break;
@@ -1231,14 +1280,14 @@ usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_hos
}
if (index >= USB_HOST_CONFIG_MAX_HOST)
{
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Error;
}
/* check deviceHandle valid? */
if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success)
{
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Error;
}
@@ -1247,11 +1296,11 @@ usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_hos
{
if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle)
{
- deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Opened;
+ deviceInstance->interfaceStatus[interfaceIndex] = (uint8_t)kStatus_interface_Opened;
break;
}
}
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Success;
}
@@ -1259,10 +1308,10 @@ usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_hos
usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle)
{
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- usb_host_instance_t *hostInstance = NULL;
+ usb_host_instance_t *hostInstance = NULL;
uint8_t interfaceIndex;
uint8_t removeLabel = 1;
- uint8_t index = 0;
+ uint8_t index = 0;
if (deviceHandle == NULL)
{
@@ -1270,11 +1319,11 @@ usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_ho
}
hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle;
- USB_HostLock();
+ (void)USB_HostLock();
/* check host_instance valid? */
for (; index < USB_HOST_CONFIG_MAX_HOST; ++index)
{
- if ((g_UsbHostInstance[index].occupied == 1) &&
+ if ((g_UsbHostInstance[index].occupied == 1U) &&
((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance)))
{
break;
@@ -1282,14 +1331,14 @@ usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_ho
}
if (index >= USB_HOST_CONFIG_MAX_HOST)
{
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Error;
}
/* check deviceHandle valid? */
if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success)
{
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Error;
}
@@ -1300,32 +1349,32 @@ usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_ho
{
if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle)
{
- deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Detached;
+ deviceInstance->interfaceStatus[interfaceIndex] = (uint8_t)kStatus_interface_Detached;
break;
}
}
}
- if (deviceInstance->deviceAttachState == kStatus_device_Detached) /* device is removed from host */
+ if (deviceInstance->deviceAttachState == (uint8_t)kStatus_device_Detached) /* device is removed from host */
{
removeLabel = 1;
/* check all the interfaces of the device are not opened */
for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex)
{
- if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened)
+ if (deviceInstance->interfaceStatus[interfaceIndex] == (uint8_t)kStatus_interface_Opened)
{
- removeLabel = 0;
+ removeLabel = 0U;
break;
}
}
- if (removeLabel == 1)
+ if (removeLabel == 1U)
{
/* remove device instance from host */
- USB_HostRemoveDeviceInstance(hostInstance, deviceInstance);
+ (void)USB_HostRemoveDeviceInstance(hostInstance, deviceInstance);
}
- USB_HostUnlock();
+ (void)USB_HostUnlock();
- if (removeLabel == 1)
+ if (removeLabel == 1U)
{
USB_HostReleaseDeviceResource((usb_host_instance_t *)deviceInstance->hostHandle,
deviceInstance); /* release device resource */
@@ -1333,7 +1382,7 @@ usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_ho
}
else
{
- USB_HostUnlock();
+ (void)USB_HostUnlock();
}
return kStatus_USB_Success;
@@ -1341,9 +1390,9 @@ usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_ho
usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle)
{
- usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
+ usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- uint8_t interfaceIndex = 0;
+ uint8_t interfaceIndex = 0;
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
uint8_t level = 0;
uint8_t devHubNo;
@@ -1362,25 +1411,26 @@ usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle
if (USB_HostValidateDevice(hostInstance, deviceInstance) == kStatus_USB_Success) /* device is valid */
{
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
- devHubNo = deviceInstance->hubNumber;
+ devHubNo = deviceInstance->hubNumber;
devPortNo = deviceInstance->portNumber;
- level = deviceInstance->level;
+ level = deviceInstance->level;
#endif
- deviceInstance->deviceAttachState = kStatus_device_Detached;
- if (deviceInstance->state >= kStatus_DEV_Initial) /* device is valid */
+ deviceInstance->deviceAttachState = (uint8_t)kStatus_device_Detached;
+ if (deviceInstance->state >= (uint8_t)kStatus_DEV_Initial) /* device is valid */
{
- if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeraion is not done or application don't use */
+ if (deviceInstance->state <
+ (uint8_t)kStatus_DEV_AppUsed) /* enumeration is not done or application don't use */
{
/* detach internally */
- USB_HostDetachDeviceInternal(hostHandle, deviceHandle);
+ (void)USB_HostDetachDeviceInternal(hostHandle, deviceHandle);
}
else /* application use the device */
{
- for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount;
+ for (interfaceIndex = 0U; interfaceIndex < deviceInstance->configuration.interfaceCount;
++interfaceIndex)
{
- if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened)
+ if (deviceInstance->interfaceStatus[interfaceIndex] == (uint8_t)kStatus_interface_Opened)
{
#ifdef HOST_ECHO
usb_echo("error: there is class instance that is not deinited\r\n");
@@ -1389,20 +1439,20 @@ usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle
}
}
/* remove device instance from host */
- USB_HostRemoveDeviceInstance(hostInstance, deviceInstance);
+ (void)USB_HostRemoveDeviceInstance(hostInstance, deviceInstance);
USB_HostReleaseDeviceResource(hostInstance, deviceInstance); /* release resource */
}
}
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
- if (level == 1)
+ if (level == 1U)
{
- USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */
- USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */
+ (void)USB_HostControlBus(hostHandle, (uint8_t)kUSB_HostBusReset); /* reset controller port */
+ (void)USB_HostControlBus(hostHandle, (uint8_t)kUSB_HostBusRestart); /* restart controller port */
}
else
{
- USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */
+ (void)USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */
}
#else
USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */
@@ -1411,4 +1461,4 @@ usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle
}
return kStatus_USB_Success;
-}
+}
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h
index 422e876a12..5612603cb0 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h
@@ -1,31 +1,9 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _USB_HOST_DEV_MNG_H_
@@ -79,11 +57,11 @@ typedef struct _usb_host_device_instance
usb_descriptor_device_t *deviceDescriptor; /*!< Standard device descriptor */
usb_host_pipe_handle controlPipe; /*!< Device's control pipe */
uint8_t *configurationDesc; /*!< Configuration descriptor pointer */
+ uint8_t *enumBuffer; /*!< Buffer for enumeration */
uint16_t configurationLen; /*!< Configuration descriptor length */
- uint16_t configurationValue; /*!< Configuration index */
uint8_t interfaceStatus[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interfaces' status, please reference to
#usb_host_interface_state_t */
- uint8_t *enumBuffer; /*!< Buffer for enumeration */
+ uint8_t configurationValue; /*!< Configuration index */
uint8_t state; /*!< Device state for enumeration */
uint8_t enumRetries; /*!< Re-enumeration when error in control transfer */
uint8_t stallRetries; /*!< Re-transfer when stall */
@@ -104,11 +82,10 @@ typedef struct _usb_host_device_instance
typedef struct _usb_host_enum_process_entry
{
- uint8_t successState; /*!< When the last step is successful, the next state value */
- uint8_t retryState; /*!< When the last step need retry, the next state value */
- usb_status_t (*process)(usb_host_device_instance_t *deviceInstance); /*!< When the last step transfer is done, the
- function is used to process the transfer
- data */
+ usb_host_device_enumeration_status_t successState; /*!< When the last step is successful, the next state value */
+ usb_host_device_enumeration_status_t retryState; /*!< When the last step need retry, the next state value */
+ /*! When the last step transfer is done, the function is used to process the transfer data */
+ usb_status_t (*process)(usb_host_device_instance_t *deviceInstance, uint32_t dataLength);
} usb_host_enum_process_entry_t;
/*******************************************************************************
@@ -175,4 +152,4 @@ extern uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle);
extern usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle);
/*! @}*/
-#endif /* _USB_HOST_DEV_MNG_H_ */
+#endif /* _USB_HOST_DEV_MNG_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c
index 8a31514b3a..9382aad979 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c
@@ -1,41 +1,22 @@
/*
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016,2019 - 2020 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
-#include
+#include
#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U))
#include "usb_host.h"
#include "usb_host_hci.h"
#include "usb_host_devices.h"
+#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
+#include "usb_host_framework.h"
+#endif
#include "fsl_device_registers.h"
#include "usb_host_ehci.h"
-#include "usb_phy.h"
+#include
#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
#include "usb_host.h"
#endif
@@ -50,16 +31,16 @@
#endif
-#define USB_HOST_EHCI_BANDWIDTH_DELAY (3500U)
-#define USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP (333U)
+#define USB_HOST_EHCI_BANDWIDTH_DELAY (3500U)
+#define USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP (333U)
#define USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME (900U)
#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
-#define USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH (18U)
-#define USB_HOST_EHCI_PORTSC_PTC_J_STATE (0x01U)
-#define USB_HOST_EHCI_PORTSC_PTC_K_STATE (0x02U)
-#define USB_HOST_EHCI_PORTSC_PTC_SE0_NAK (0x03U)
-#define USB_HOST_EHCI_PORTSC_PTC_PACKET (0x04U)
+#define USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH (18U)
+#define USB_HOST_EHCI_PORTSC_PTC_J_STATE (0x01U)
+#define USB_HOST_EHCI_PORTSC_PTC_K_STATE (0x02U)
+#define USB_HOST_EHCI_PORTSC_PTC_SE0_NAK (0x03U)
+#define USB_HOST_EHCI_PORTSC_PTC_PACKET (0x04U)
#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS (0x05U)
#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_FS (0x06U)
#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_LS (0x07U)
@@ -102,7 +83,7 @@ static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *eh
static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance,
uint32_t hubNumber,
uint16_t frameIndex,
- uint8_t frameBandwidths[8]);
+ uint16_t frameBandwidths[8]);
/*!
* @brief compute current allocated HS bandwidth when ehci work as hi-speed host.
@@ -113,7 +94,7 @@ static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *
*/
static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance,
uint16_t frameIndex,
- uint8_t frameBandwidths[8]);
+ uint16_t frameBandwidths[8]);
/*!
* @brief allocate HS bandwidth when host work as high-speed host.
@@ -175,13 +156,6 @@ static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length);
*/
static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms);
-/*!
- * @brief host ehci start async schedule.
- *
- * @param ehciInstance ehci instance pointer.
- */
-static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance);
-
/*!
* @brief host ehci stop async schedule.
*
@@ -189,13 +163,6 @@ static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance);
*/
static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance);
-/*!
- * @brief host ehci start periodic schedule.
- *
- * @param ehciInstance ehci instance pointer.
- */
-static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance);
-
/*!
* @brief host ehci stop periodic schedule.
*
@@ -515,16 +482,6 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc
usb_host_ehci_pipe_t *ehciPipePointer,
usb_host_transfer_t *transfer);
-/*!
- * @brief control ehci bus.
- *
- * @param ehciInstance ehci instance pointer.
- * @param bus_control control code.
- *
- * @return kStatus_USB_Success or error codes.
- */
-static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl);
-
/*!
* @brief ehci transaction done process function.
*
@@ -532,20 +489,7 @@ static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstanc
*/
void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance);
-/*!
- * @brief ehci port change interrupt process function.
- *
- * @param ehciInstance ehci instance pointer.
- */
-static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance);
-/*!
- * @brief ehci timer0 interrupt process function.
- * cancel control/bulk transfer that time out.
- *
- * @param ehciInstance ehci instance pointer.
- */
-static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance);
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
/*!
@@ -586,71 +530,60 @@ extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t
USB_RAM_ADDRESS_ALIGNMENT(4096)
USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4];
-#define USB_HOST_EHCI_FRAME_LIST_ARRAY \
- { \
- &s_UsbHostEhciFrameList1[0] \
- }
+static uint8_t usbHostEhciFramListStatus[1] = {0};
USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1;
-#define USB_HOST_EHCI_DATA_ARRAY \
- { \
- &s_UsbHostEhciData1 \
- }
-#elif(USB_HOST_CONFIG_EHCI == 2U)
+#elif (USB_HOST_CONFIG_EHCI == 2U)
USB_RAM_ADDRESS_ALIGNMENT(4096)
USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4];
USB_RAM_ADDRESS_ALIGNMENT(4096)
USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList2[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4];
-#define USB_HOST_EHCI_FRAME_LIST_ARRAY \
- { \
- &s_UsbHostEhciFrameList1[0], &s_UsbHostEhciFrameList2[0] \
- }
+static uint8_t usbHostEhciFramListStatus[2] = {0, 0};
USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1;
USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData2;
-#define USB_HOST_EHCI_DATA_ARRAY \
- { \
- &s_UsbHostEhciData1, &s_UsbHostEhciData2 \
- }
#else
#error "Please increase the instance count."
#endif
+#define USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE (1024U)
+#define USB_HOST_EHCI_MAX_MICRFRAME_VALUE ((USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3U) - 1U)
-static uint8_t s_SlotMaxBandwidth[8] = {125, 125, 125, 125, 125, 125, 50, 0};
+static uint8_t s_SlotMaxBandwidth[8] = {125, 125, 125, 125, 125, 125, 50, 0};
+static uint8_t s_SlotMaxBandwidthHs[8] = {100, 100, 100, 100, 100, 100, 100, 100};
/*******************************************************************************
* Code
******************************************************************************/
/*!
-* @brief EHCI NC get USB NC bass address.
-*
-* This function is used to get USB NC bass address.
-*
-* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t.
-*
-* @retval USB NC bass address.
-*/
+ * @brief EHCI NC get USB NC bass address.
+ *
+ * This function is used to get USB NC bass address.
+ *
+ * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t.
+ *
+ * @retval USB NC bass address.
+ */
#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))
-void *USB_EhciNCGetBase(uint8_t controllerId)
+static void *USB_EhciNCGetBase(uint8_t controllerId)
{
void *usbNCBase = NULL;
#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))
uint32_t instance;
- uint32_t newinstance = 0;
+ uint32_t newinstance = 0;
uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS;
- uint32_t usbnc_base[] = USBNC_BASE_ADDRS;
+ uint32_t usbnc_base[] = USBNC_BASE_ADDRS;
- if (controllerId < kUSB_ControllerEhci0)
+ if (controllerId < (uint8_t)kUSB_ControllerEhci0)
{
return NULL;
}
- controllerId = controllerId - kUSB_ControllerEhci0;
+ controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0;
for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++)
{
- if (usbnc_base_temp[instance])
+ if (usbnc_base_temp[instance] != 0U)
{
usbnc_base[newinstance++] = usbnc_base_temp[instance];
}
@@ -660,7 +593,7 @@ void *USB_EhciNCGetBase(uint8_t controllerId)
return NULL;
}
- usbNCBase = (void *)usbnc_base[controllerId];
+ usbNCBase = (void *)(uint8_t *)usbnc_base[controllerId];
#endif
return usbNCBase;
}
@@ -729,19 +662,19 @@ static void USB_HostEhciTestSingleStepGetDeviceDesc(usb_host_ehci_instance_t *eh
return;
}
- getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t);
- getDescriptorParam.descriptorLength = 18;
- getDescriptorParam.descriptorBuffer = (uint8_t *)&deviceInstance->deviceDescriptor;
- getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE;
- getDescriptorParam.descriptorIndex = 0;
- getDescriptorParam.languageId = 0;
- transfer->callbackFn = USB_HostEhciTestCallback;
- transfer->callbackParam = ehciInstance->hostHandle;
+ getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t);
+ getDescriptorParam.descriptorLength = 18;
+ getDescriptorParam.descriptorBuffer = (uint8_t *)&deviceInstance->deviceDescriptor;
+ getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE;
+ getDescriptorParam.descriptorIndex = 0;
+ getDescriptorParam.languageId = 0;
+ transfer->callbackFn = USB_HostEhciTestCallback;
+ transfer->callbackParam = ehciInstance->hostHandle;
transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN;
- transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
- transfer->setupPacket->wIndex = 0;
- transfer->setupPacket->wLength = 0;
- transfer->setupPacket->wValue = 0;
+ transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
+ transfer->setupPacket->wIndex = 0;
+ transfer->setupPacket->wLength = 0;
+ transfer->setupPacket->wValue = 0;
USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam);
}
@@ -774,8 +707,8 @@ static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *
{
qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead;
}
- qtdPointer = ehciInstance->ehciQtdHead;
- ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer;
+ qtdPointer = ehciInstance->ehciQtdHead;
+ ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer;
qtdPointer->nextQtdPointer = 0;
} while (--qtdNumber);
}
@@ -795,7 +728,7 @@ static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *
qtdPointer->transferResults[0] =
((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) |
(EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK));
- dataAddress = (uint32_t)(transfer->setupPacket);
+ dataAddress = (uint32_t)(transfer->setupPacket);
qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */
/* set buffer pointer no matter data length */
for (index = 0; index < 4; ++index)
@@ -816,7 +749,7 @@ static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *
((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) |
(EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK));
- dataAddress = (uint32_t)(transfer->transferBuffer);
+ dataAddress = (uint32_t)(transfer->transferBuffer);
qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */
/* set buffer pointer no matter data length */
for (index = 0; index < 4; ++index)
@@ -848,24 +781,24 @@ static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *
transfer->next = NULL;
if (vltQhPointer->ehciTransferHead == NULL)
{
- transfer->next = NULL;
+ transfer->next = NULL;
vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer;
}
else
{
- transfer->next = NULL;
+ transfer->next = NULL;
vltQhPointer->ehciTransferTail->next = transfer;
- vltQhPointer->ehciTransferTail = transfer;
+ vltQhPointer->ehciTransferTail = transfer;
}
USB_HostEhciLock();
/* link qtd to qh (link to end) */
entryPointer = &(vltQhPointer->nextQtdPointer);
- dataAddress = *entryPointer; /* dataAddress variable means entry value here */
+ dataAddress = *entryPointer; /* dataAddress variable means entry value here */
while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE)))
{
entryPointer = (volatile uint32_t *)dataAddress;
- dataAddress = *entryPointer;
+ dataAddress = *entryPointer;
}
*entryPointer = (uint32_t)qtdPointer;
USB_HostEhciUnlock();
@@ -888,11 +821,11 @@ static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t
{
return;
}
- transfer->callbackFn = USB_HostEhciTestCallback;
- transfer->callbackParam = ehciInstance->hostHandle;
+ transfer->callbackFn = USB_HostEhciTestCallback;
+ transfer->callbackParam = ehciInstance->hostHandle;
transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN;
- transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
- transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH);
+ transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR;
+ transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH);
transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN((uint16_t)((uint16_t)USB_DESCRIPTOR_TYPE_DEVICE << 8));
transfer->setupPacket->wIndex = 0;
USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 1);
@@ -907,8 +840,8 @@ static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t
{
return;
}
- transfer->callbackFn = USB_HostEhciTestCallback;
- transfer->callbackParam = ehciInstance->hostHandle;
+ transfer->callbackFn = USB_HostEhciTestCallback;
+ transfer->callbackParam = ehciInstance->hostHandle;
transfer->transferBuffer = buffer;
transfer->transferLength = USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH;
USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 2);
@@ -917,8 +850,8 @@ static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t
{
return;
}
- transfer->callbackFn = USB_HostEhciTestCallback;
- transfer->callbackParam = ehciInstance->hostHandle;
+ transfer->callbackFn = USB_HostEhciTestCallback;
+ transfer->callbackParam = ehciInstance->hostHandle;
transfer->transferBuffer = NULL;
transfer->transferLength = 0;
USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 3);
@@ -934,7 +867,7 @@ static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t
return;
}
-void USB_HostEhciTestModeInit(usb_device_handle deviceHandle)
+static void USB_HostEhciTestModeInit(usb_device_handle deviceHandle)
{
uint32_t productId;
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
@@ -975,6 +908,7 @@ void USB_HostEhciTestModeInit(usb_device_handle deviceHandle)
USB_HostEhciTestSingleStepGetDeviceDescData(ehciInstance, deviceHandle);
break;
default:
+ /*no action */
break;
}
@@ -1014,60 +948,62 @@ static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance)
static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength)
{
- uint32_t result = (3167 + ((1000 * dataLength) * 7U * 8U / 6U)) / 1000;
+ uint32_t result = (3167U + ((1000U * dataLength) * 7U * 8U / 6U)) / 1000U;
if (pipeType == USB_ENDPOINT_ISOCHRONOUS) /* iso */
{
if (speed == USB_SPEED_HIGH)
{
- result = 38 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
+ result = 38U * 8U * 2083U + 2083U * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
}
else if (speed == USB_SPEED_FULL)
{
if (direction == USB_IN)
{
- result = 7268000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
+ result = 7268000U + 83540U * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
}
else
{
- result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
+ result = 6265000U + 83540U * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
}
}
else
{
+ /*no action*/
}
}
else /* interrupt */
{
if (speed == USB_SPEED_HIGH)
{
- result = 55 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
+ result = 55U * 8U * 2083U + 2083U * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
}
else if (speed == USB_SPEED_FULL)
{
- result = 9107000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
+ result = 9107000U + 83540U * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
}
else if (speed == USB_SPEED_LOW)
{
if (direction == USB_IN)
{
- result = 64060000 + 2000 * USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP + 676670 * result +
+ result = 64060000U + 2000U * USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP + 676670U * result +
USB_HOST_EHCI_BANDWIDTH_DELAY;
}
else
{
- result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
+ result = 6265000U + 83540U * result + USB_HOST_EHCI_BANDWIDTH_DELAY;
}
}
else
{
+ /*no action*/
}
}
- result /= 1000000;
- if (result == 0)
+ result /= 1000000U;
+ if (result == 0U)
{
- result = 1;
+ result = 1U;
}
return result;
@@ -1078,7 +1014,7 @@ static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *eh
uint16_t *frameBandwidth)
{
usb_host_ehci_pipe_t *ehciPipePointer;
-
+ void *temp;
/* clear the bandwidth */
*frameBandwidth = 0;
@@ -1091,26 +1027,28 @@ static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *eh
{
/* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */
if ((frameIndex >= ehciPipePointer->startFrame) &&
- (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) &
- (uint32_t)(ehciPipePointer->pipeCommon.interval - 1))))
+ (0U == ((uint32_t)((uint32_t)frameIndex - ehciPipePointer->startFrame) &
+ ((uint32_t)ehciPipePointer->pipeCommon.interval - 1U))))
{
*frameBandwidth += ehciPipePointer->dataTime;
}
}
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
}
}
static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance,
uint32_t hubNumber,
uint16_t frameIndex,
- uint8_t frameBandwidths[8])
+ uint16_t frameBandwidths[8])
{
usb_host_ehci_pipe_t *ehciPipePointer;
uint8_t index;
uint32_t deviceInfo;
+ void *temp;
- for (index = 0; index < 8; ++index)
+ for (index = 0; index < 8U; ++index)
{
frameBandwidths[index] = 0;
}
@@ -1124,47 +1062,50 @@ static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *
{
/* compute FS/LS bandwidth that blong to same high-speed hub, because FS/LS bandwidth is allocated from
* first parent high-speed hub */
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
- kUSB_HostGetDeviceHSHubNumber, &deviceInfo);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHSHubNumber, &deviceInfo);
if (deviceInfo != hubNumber)
{
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
continue;
}
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &deviceInfo);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &deviceInfo);
if (deviceInfo == USB_SPEED_HIGH)
{
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
continue;
}
/* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */
if ((frameIndex >= ehciPipePointer->startFrame) &&
- (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) &
- (uint32_t)(ehciPipePointer->pipeCommon.interval - 1))))
+ (0U == ((uint32_t)((uint32_t)frameIndex - ehciPipePointer->startFrame) &
+ ((uint32_t)ehciPipePointer->pipeCommon.interval - 1U))))
{
if (ehciPipePointer->pipeCommon.pipeType ==
USB_ENDPOINT_ISOCHRONOUS) /* iso bandwidth is allocated once */
{
- frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime;
+ frameBandwidths[ehciPipePointer->startUframe + 1U] += ehciPipePointer->dataTime;
}
else /* iso bandwidth is allocated three times */
{
- frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime;
- frameBandwidths[ehciPipePointer->startUframe + 2] += ehciPipePointer->dataTime;
- frameBandwidths[ehciPipePointer->startUframe + 3] += ehciPipePointer->dataTime;
+ frameBandwidths[ehciPipePointer->startUframe + 1U] += ehciPipePointer->dataTime;
+ frameBandwidths[ehciPipePointer->startUframe + 2U] += ehciPipePointer->dataTime;
+ frameBandwidths[ehciPipePointer->startUframe + 3U] += ehciPipePointer->dataTime;
}
}
}
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
}
- for (index = 0; index < 7; ++index) /* */
+ for (index = 0; index < 7U; ++index) /* */
{
if (frameBandwidths[index] > s_SlotMaxBandwidth[index])
{
- frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]);
+ frameBandwidths[index + 1U] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]);
frameBandwidths[index] = s_SlotMaxBandwidth[index];
}
}
@@ -1172,14 +1113,14 @@ static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *
static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance,
uint16_t frameIndex,
- uint8_t frameBandwidths[8])
+ uint16_t frameBandwidths[8])
{
usb_host_ehci_pipe_t *ehciPipePointer;
- uint8_t index;
+ uint16_t index;
uint32_t deviceInfo;
uint16_t frameInterval;
-
- for (index = 0; index < 8; ++index)
+ void *temp;
+ for (index = 0; index < 8U; ++index)
{
frameBandwidths[index] = 0;
}
@@ -1192,26 +1133,26 @@ static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t
(ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT))
{
frameInterval = ehciPipePointer->pipeCommon.interval;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &deviceInfo);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &deviceInfo);
if (deviceInfo == USB_SPEED_HIGH) /* high-speed data bandwidth */
{
/* frameInterval means micro-frame here */
if (frameIndex >= ehciPipePointer->startFrame)
{
- if ((frameInterval > 8) &&
- (frameIndex * 8 - ehciPipePointer->startFrame * 8 >= ehciPipePointer->startUframe))
+ if ((frameInterval > 8U) &&
+ (frameIndex * 8U - ehciPipePointer->startFrame * 8U >= ehciPipePointer->startUframe))
{
- if (!((uint32_t)(frameIndex * 8 - ehciPipePointer->startFrame * 8 -
- ehciPipePointer->startUframe) &
- (uint32_t)(frameInterval - 1)))
+ if (0U == ((((uint32_t)frameIndex) * 8U - ehciPipePointer->startFrame * 8U -
+ ehciPipePointer->startUframe) &
+ ((uint32_t)frameInterval - 1U)))
{
frameBandwidths[ehciPipePointer->startUframe] += ehciPipePointer->dataTime;
}
}
else
{
- for (index = ehciPipePointer->startUframe; index < 8; index += frameInterval)
+ for (index = ehciPipePointer->startUframe; index < 8U; index += frameInterval)
{
frameBandwidths[index] += ehciPipePointer->dataTime;
}
@@ -1221,17 +1162,18 @@ static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t
else /* full-speed split bandwidth */
{
if ((frameIndex >= ehciPipePointer->startFrame) &&
- (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & (uint32_t)(frameInterval - 1))))
+ (0U == ((uint32_t)((uint32_t)frameIndex - ehciPipePointer->startFrame) &
+ (uint32_t)((uint32_t)frameInterval - 1U))))
{
- for (index = 0; index < 8; ++index)
+ for (index = 0; index < 8U; ++index)
{
- if ((uint32_t)(ehciPipePointer->uframeSmask) &
- (uint32_t)(0x01 << index)) /* start-split micro-frames */
+ if (0U != ((uint32_t)(ehciPipePointer->uframeSmask) &
+ (uint32_t)(0x01UL << index))) /* start-split micro-frames */
{
frameBandwidths[index] += ehciPipePointer->startSplitTime;
}
- if ((uint32_t)(ehciPipePointer->uframeCmask) &
- (uint32_t)(0x01 << index)) /* complete-split micro-frames */
+ if (0U != ((uint32_t)(ehciPipePointer->uframeCmask) &
+ (uint32_t)(0x01UL << index))) /* complete-split micro-frames */
{
frameBandwidths[index] += ehciPipePointer->completeSplitTime;
}
@@ -1239,17 +1181,20 @@ static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t
}
}
}
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
}
+#if 0
for (index = 0; index < 7; ++index) /* */
{
- if (frameBandwidths[index] > s_SlotMaxBandwidth[index])
+ if (frameBandwidths[index] > s_SlotMaxBandwidthHs[index])
{
- frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]);
- frameBandwidths[index] = s_SlotMaxBandwidth[index];
+ frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidthHs[index]);
+ frameBandwidths[index] = s_SlotMaxBandwidthHs[index];
}
}
+#endif
}
/*!
@@ -1270,15 +1215,19 @@ static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instan
uint16_t uframeIntervalIndex;
uint16_t uframeIndex;
uint16_t frameIndex;
- uint8_t frameTimes[8];
+ uint16_t frameTimes[8];
frameIndex = 0;
+ for (uint8_t i = 0; i < 8U; ++i)
+ {
+ frameTimes[i] = 0U;
+ }
USB_HostBandwidthHsHostComputeCurrentHsAll(
ehciInstance, frameIndex, frameTimes); /* compute the allocated bandwidths in the frameIndex frame */
for (uframeIntervalIndex = 0; (uframeIntervalIndex < uframeInterval); ++uframeIntervalIndex) /* start micro-frame */
{
/* for all the micro-frame in interval uframeInterval */
- for (uframeIndex = uframeIntervalIndex; uframeIndex < (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8);
+ for (uframeIndex = uframeIntervalIndex; uframeIndex < (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8U);
uframeIndex += uframeInterval)
{
if (frameIndex != (uframeIndex >> 3))
@@ -1288,13 +1237,13 @@ static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instan
ehciInstance, frameIndex,
frameTimes); /* compute the allocated bandwidths in the new frameIndex frame */
}
- if (frameTimes[uframeIndex & 0x0007] + timeData >
- s_SlotMaxBandwidth[(uframeIndex & 0x0007)]) /* micro-frame has enough idle bandwidth? */
+ if (frameTimes[uframeIndex & 0x0007U] + timeData >
+ s_SlotMaxBandwidthHs[(uframeIndex & 0x0007U)]) /* micro-frame has enough idle bandwidth? */
{
break; /* fail */
}
}
- if (uframeIndex >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8)) /* success? */
+ if (uframeIndex >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8U)) /* success? */
{
break;
}
@@ -1318,91 +1267,97 @@ static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t
usb_host_ehci_pipe_t *ehciPipePointer)
{
usb_status_t status;
- uint32_t deviceInfo;
- uint32_t hubNumber;
+ uint32_t deviceInfo = 0;
+ uint32_t hubNumber = 0;
uint16_t uframeIntervalIndex = 0;
- uint16_t frameIntervalIndex = 0;
+ uint16_t frameIntervalIndex = 0;
uint16_t frameIndex;
uint16_t timeCompleteSplit;
uint16_t timeStartSplit;
uint32_t timeData;
uint8_t SsCsNumber = 0;
uint16_t frameInterval;
- uint8_t frameTimes[8];
+ uint16_t frameTimes[8];
uint8_t allocateOk = 1;
- uint8_t index;
+ uint16_t index;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &deviceInfo);
+ for (uint8_t i = 0; i < 8U; ++i)
+ {
+ frameTimes[i] = 0U;
+ }
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &deviceInfo);
timeData = USB_HostBandwidthComputeTime(
- deviceInfo, USB_ENDPOINT_ISOCHRONOUS, ehciPipePointer->pipeCommon.direction,
- ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe);
+ (uint8_t)deviceInfo, USB_ENDPOINT_ISOCHRONOUS, ehciPipePointer->pipeCommon.direction,
+ (((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize) * ehciPipePointer->pipeCommon.numberPerUframe));
/* pipe is high-speed */
if (deviceInfo == USB_SPEED_HIGH)
{
uframeIntervalIndex = 0;
- status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData,
- &uframeIntervalIndex);
+ status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval,
+ (uint16_t)timeData, &uframeIntervalIndex);
if (status == kStatus_USB_Success)
{
- ehciPipePointer->startFrame = (uframeIntervalIndex / 8);
- ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007);
- ehciPipePointer->dataTime = timeData;
+ ehciPipePointer->startFrame = (uframeIntervalIndex / 8U);
+ ehciPipePointer->startUframe = (uint8_t)(uframeIntervalIndex & 0x0007U);
+ ehciPipePointer->dataTime = (uint16_t)timeData;
return kStatus_USB_Success;
}
}
else /* pipe is full-speed or low-speed */
{
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime,
- &deviceInfo); /* deviceInfo variable means hub think time */
- timeData += (deviceInfo * 7 / (6 * 12));
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber,
- &hubNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetHubThinkTime,
+ &deviceInfo); /* deviceInfo variable means hub think time */
+ timeData += (deviceInfo * 7U / (6U * 12U));
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHSHubNumber, &hubNumber);
frameInterval = ehciPipePointer->pipeCommon.interval;
/* compute start-split and complete-split bandwidth */
if (ehciPipePointer->pipeCommon.direction == USB_OUT)
{
- timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_OUT,
- ehciPipePointer->pipeCommon.maxPacketSize);
+ timeStartSplit = (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_OUT,
+ ehciPipePointer->pipeCommon.maxPacketSize);
timeCompleteSplit = 0;
}
else
{
- timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, 1);
- timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN,
- ehciPipePointer->pipeCommon.maxPacketSize);
+ timeStartSplit =
+ (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, 1);
+ timeCompleteSplit = (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN,
+ ehciPipePointer->pipeCommon.maxPacketSize);
}
/* note: bandwidth must put in one frame */
- for (uframeIntervalIndex = 0; uframeIntervalIndex <= 5; ++uframeIntervalIndex) /* uframe interval */
+ for (uframeIntervalIndex = 0U; uframeIntervalIndex <= 5U; ++uframeIntervalIndex) /* uframe interval */
{
- for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */
+ for (frameIntervalIndex = 0U; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */
{
allocateOk = 1;
for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE;
frameIndex += frameInterval) /* check all the frames */
{
/* compute start-split and complete-split number */
- SsCsNumber = (ehciPipePointer->pipeCommon.maxPacketSize + 187) /
- 188; /* ss number for iso out; cs number for iso in */
+ SsCsNumber = (uint8_t)((ehciPipePointer->pipeCommon.maxPacketSize + 187U) /
+ 188U); /* ss number for iso out; cs number for iso in */
if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */
{
- if (uframeIntervalIndex + SsCsNumber > 8)
+ if (uframeIntervalIndex + SsCsNumber > 8U)
{
- allocateOk = 0;
+ allocateOk = 0U;
}
}
else
{
- if (uframeIntervalIndex + 2 + SsCsNumber >
- 8) /* ISO IN: there are two micro-frame interval between start-split and complete-split */
+ if (uframeIntervalIndex + 2U + SsCsNumber >
+ 8U) /* ISO IN: there are two micro-frame interval between start-split and complete-split */
{
- allocateOk = 0;
+ allocateOk = 0U;
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
/* allocate start-split and complete-split bandwidth */
USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes);
@@ -1411,9 +1366,9 @@ static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t
index = uframeIntervalIndex;
for (; index < (uframeIntervalIndex + SsCsNumber); ++index)
{
- if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index])
+ if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidthHs[index])
{
- allocateOk = 0;
+ allocateOk = 0U;
break;
}
}
@@ -1421,20 +1376,20 @@ static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t
else /* ISO IN */
{
index = uframeIntervalIndex;
- if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index])
+ if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidthHs[index])
{
- allocateOk = 0;
+ allocateOk = 0U;
}
- if (allocateOk)
+ if (0U != allocateOk)
{
index =
uframeIntervalIndex +
- 2; /* there are two micro-frames interval between start-split and complete-split */
- for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index)
+ 2U; /* there are two micro-frames interval between start-split and complete-split */
+ for (; index < (uframeIntervalIndex + 2U + SsCsNumber); ++index)
{
- if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index])
+ if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidthHs[index])
{
- allocateOk = 0;
+ allocateOk = 0U;
break;
}
}
@@ -1443,18 +1398,18 @@ static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t
}
/* allocate data bandwidth */
- if (allocateOk)
+ if (0U != allocateOk)
{
USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes);
- index = uframeIntervalIndex + 1; /* timeData bandwidth start position */
+ index = uframeIntervalIndex + 1U; /* timeData bandwidth start position */
/* iso must occupy all the uframe bandwidth */
{
deviceInfo = timeData; /* note: deviceInfo variable means bandwidth here */
- while ((index < 8) && (deviceInfo > s_SlotMaxBandwidth[index]))
+ while ((index < 8U) && (deviceInfo > s_SlotMaxBandwidth[index]))
{
- if (frameTimes[index] > 0)
+ if (frameTimes[index] > 0U)
{
- allocateOk = 0;
+ allocateOk = 0U;
break;
}
else
@@ -1465,16 +1420,16 @@ static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t
}
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
/* data bandwidth can be put in the frame? */
- index = uframeIntervalIndex + 1; /* timeData bandwidth start position */
- frameTimes[index] += timeData;
- for (; index < 7; ++index)
+ index = uframeIntervalIndex + 1U; /* timeData bandwidth start position */
+ frameTimes[index] += (uint16_t)timeData;
+ for (; index < 7U; ++index)
{
if (frameTimes[index] > s_SlotMaxBandwidth[index])
{
- frameTimes[index + 1] += (frameTimes[index] - s_SlotMaxBandwidth[index]);
+ frameTimes[index + 1U] += (frameTimes[index] - s_SlotMaxBandwidth[index]);
frameTimes[index] = s_SlotMaxBandwidth[index];
}
else
@@ -1488,45 +1443,45 @@ static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
break;
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
break;
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
break;
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
- ehciPipePointer->startFrame = frameIntervalIndex;
- ehciPipePointer->startUframe = uframeIntervalIndex;
- ehciPipePointer->dataTime = timeData;
- ehciPipePointer->startSplitTime = timeStartSplit;
+ ehciPipePointer->startFrame = frameIntervalIndex;
+ ehciPipePointer->startUframe = (uint8_t)uframeIntervalIndex;
+ ehciPipePointer->dataTime = (uint16_t)timeData;
+ ehciPipePointer->startSplitTime = timeStartSplit;
ehciPipePointer->completeSplitTime = timeCompleteSplit;
if (ehciPipePointer->pipeCommon.direction == USB_OUT)
{
index = uframeIntervalIndex;
for (; index < (uframeIntervalIndex + SsCsNumber); ++index)
{
- ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index);
+ ehciPipePointer->uframeSmask = ehciPipePointer->uframeSmask | (uint8_t)(0x01UL << index);
}
}
else
{
- index = uframeIntervalIndex;
- ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index);
- index = uframeIntervalIndex + 2;
- for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index)
+ index = uframeIntervalIndex;
+ ehciPipePointer->uframeSmask = ehciPipePointer->uframeSmask | (uint8_t)(0x01UL << index);
+ index = uframeIntervalIndex + 2U;
+ for (; index < (uframeIntervalIndex + 2U + SsCsNumber); ++index)
{
- ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index);
+ ehciPipePointer->uframeCmask = ehciPipePointer->uframeCmask | (uint8_t)(0x01UL << index);
}
}
@@ -1543,92 +1498,100 @@ static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_insta
usb_host_ehci_pipe_t *ehciPipePointer)
{
usb_status_t status;
- uint32_t deviceInfo;
- uint32_t hubNumber;
+ uint32_t deviceInfo = 0;
+ uint32_t hubNumber = 0;
uint16_t uframeIntervalIndex = 0;
- uint16_t frameIntervalIndex = 0;
+ uint16_t frameIntervalIndex = 0;
uint16_t frameIndex;
uint16_t timeCompleteSplit;
uint16_t timeStartSplit;
uint32_t timeData;
uint8_t SsCsNumber;
uint16_t frameInterval;
- uint8_t frameTimes[8];
+ uint16_t frameTimes[8];
uint8_t allocateOk = 1;
uint8_t index;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &deviceInfo);
+ for (uint8_t i = 0; i < 8U; ++i)
+ {
+ frameTimes[i] = 0U;
+ }
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &deviceInfo);
timeData = USB_HostBandwidthComputeTime(
- deviceInfo, USB_ENDPOINT_INTERRUPT, ehciPipePointer->pipeCommon.direction,
- ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe);
+ (uint8_t)deviceInfo, USB_ENDPOINT_INTERRUPT, ehciPipePointer->pipeCommon.direction,
+ (uint32_t)ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe);
/* pipe is high-speed */
if (deviceInfo == USB_SPEED_HIGH)
{
uframeIntervalIndex = 0;
- status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData,
- &uframeIntervalIndex);
+ status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval,
+ (uint16_t)timeData, &uframeIntervalIndex);
if (status == kStatus_USB_Success)
{
- ehciPipePointer->startFrame = (uframeIntervalIndex / 8);
- ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007);
+ ehciPipePointer->startFrame = (uframeIntervalIndex / 8U);
+ ehciPipePointer->startUframe = (uint8_t)(uframeIntervalIndex & 0x0007U);
/* for HS interrupt start transaction position */
- if (ehciPipePointer->uframeInterval >= 8)
+ if (ehciPipePointer->uframeInterval >= 8U)
{
- ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe);
+ ehciPipePointer->uframeSmask = (0x01U << ehciPipePointer->startUframe);
}
else
{
- ehciPipePointer->uframeSmask = 0x00u;
- for (index = ehciPipePointer->startUframe; index < 8; index += ehciPipePointer->uframeInterval)
+ ehciPipePointer->uframeSmask = 0x00U;
+ for (index = ehciPipePointer->startUframe; index < 8U;
+ index += (uint8_t)ehciPipePointer->uframeInterval)
{
ehciPipePointer->uframeSmask |= (0x01U << index);
}
}
- ehciPipePointer->dataTime = timeData;
+ ehciPipePointer->dataTime = (uint16_t)timeData;
return kStatus_USB_Success;
}
}
else /* pipe is full-speed or low-speed */
{
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime,
- &deviceInfo);
- timeData += (deviceInfo * 7 / (6 * 12));
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber,
- &hubNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetHubThinkTime, &deviceInfo);
+ timeData += (deviceInfo * 7U / (6U * 12U));
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHSHubNumber, &hubNumber);
frameInterval = ehciPipePointer->pipeCommon.interval;
- SsCsNumber = 3; /* complete split number */
+ SsCsNumber = 3U; /* complete split number */
/* compute start-split and complete-split bandwidth */
if (ehciPipePointer->pipeCommon.direction == USB_OUT)
{
- timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT,
- ehciPipePointer->pipeCommon.maxPacketSize) +
- USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 1);
- timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 0);
+ timeStartSplit = (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT,
+ ehciPipePointer->pipeCommon.maxPacketSize);
+ timeStartSplit +=
+ (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 1U);
+ timeCompleteSplit =
+ (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 0U);
}
else
{
- timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 1);
- timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN,
- ehciPipePointer->pipeCommon.maxPacketSize) +
- USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 0);
+ timeStartSplit = (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 1U);
+ timeCompleteSplit = (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN,
+ ehciPipePointer->pipeCommon.maxPacketSize);
+ timeCompleteSplit +=
+ (uint16_t)USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 0U);
}
/* note: bandwidth must put in one frame */
- for (uframeIntervalIndex = 0; uframeIntervalIndex <= 4; ++uframeIntervalIndex) /* uframe interval */
+ for (uframeIntervalIndex = 0U; uframeIntervalIndex <= 4U; ++uframeIntervalIndex) /* uframe interval */
{
- for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */
+ for (frameIntervalIndex = 0U; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */
{
- allocateOk = 1;
+ allocateOk = 1U;
for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE;
frameIndex += frameInterval) /* check all the frames */
{
/* allocate data bandwidth */
USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes);
- index = uframeIntervalIndex + 1;
- for (; index <= (uframeIntervalIndex + 3); ++index) /* data bandwidth number is 3.
+ index = (uint8_t)(uframeIntervalIndex + 1U);
+ for (; index <= (uframeIntervalIndex + 3U); ++index) /* data bandwidth number is 3.
uframeIntervalIndex don't exceed 4, so
index cannot exceed 7 */
{
@@ -1639,60 +1602,61 @@ static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_insta
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes);
/* allocate start_split bandwidth */
- if (frameTimes[uframeIntervalIndex] + timeStartSplit > s_SlotMaxBandwidth[uframeIntervalIndex])
+ if (frameTimes[uframeIntervalIndex] + timeStartSplit >
+ s_SlotMaxBandwidthHs[uframeIntervalIndex])
{
- allocateOk = 0;
+ allocateOk = 0U;
}
- if (allocateOk)
+ if (0U != allocateOk)
{
/* allocate complete_split bandwidth */
- index = uframeIntervalIndex + 2;
+ index = (uint8_t)uframeIntervalIndex + 2U;
/* complete-split number is normal 3. When uframeIntervalIndex is 4, complete-split number
* is 2. */
- for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index)
+ for (; (index <= (uframeIntervalIndex + 1U + SsCsNumber)) && (index < 8U); ++index)
{
- if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index])
+ if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidthHs[index])
{
- allocateOk = 0;
+ allocateOk = 0U;
break;
}
}
}
}
- if (!allocateOk)
+ if (0U == allocateOk)
{
break; /* allocate fail */
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
break;
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
break;
}
}
- if (allocateOk)
+ if (0U != allocateOk)
{
- ehciPipePointer->startFrame = frameIntervalIndex;
- ehciPipePointer->startUframe = uframeIntervalIndex;
- ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe);
- ehciPipePointer->uframeCmask = 0;
- index = uframeIntervalIndex + 2;
- for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index)
+ ehciPipePointer->startFrame = frameIntervalIndex;
+ ehciPipePointer->startUframe = (uint8_t)uframeIntervalIndex;
+ ehciPipePointer->uframeSmask = (0x01u << ehciPipePointer->startUframe);
+ ehciPipePointer->uframeCmask = 0u;
+ index = (uint8_t)uframeIntervalIndex + 2u;
+ for (; (index <= (uframeIntervalIndex + 1u + SsCsNumber)) && (index < 8u); ++index)
{
- ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index);
+ ehciPipePointer->uframeCmask = ehciPipePointer->uframeCmask | (0x01U << index);
}
- ehciPipePointer->dataTime = timeData;
- ehciPipePointer->startSplitTime = timeStartSplit;
+ ehciPipePointer->dataTime = (uint16_t)timeData;
+ ehciPipePointer->startSplitTime = timeStartSplit;
ehciPipePointer->completeSplitTime = timeCompleteSplit;
return kStatus_USB_Success;
@@ -1706,17 +1670,18 @@ static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *
usb_host_ehci_pipe_t *ehciPipePointer)
{
uint32_t FslsTime = 0;
- uint32_t speed = 0;
+ uint32_t speed = 0;
uint16_t uframeIntervalIndex;
uint16_t frameIndex;
uint16_t frameInterval;
uint16_t frameTime;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime,
- &FslsTime);
- FslsTime += (FslsTime * 7 / (6 * 12));
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed);
- FslsTime = FslsTime + USB_HostBandwidthComputeTime(speed, ehciPipePointer->pipeCommon.pipeType,
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetHubThinkTime, &FslsTime);
+ FslsTime += (FslsTime * 7U / (6U * 12U));
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
+ FslsTime = FslsTime + USB_HostBandwidthComputeTime((uint8_t)speed, ehciPipePointer->pipeCommon.pipeType,
ehciPipePointer->pipeCommon.direction,
ehciPipePointer->pipeCommon.maxPacketSize);
@@ -1740,11 +1705,11 @@ static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *
}
if (uframeIntervalIndex < ehciPipePointer->uframeInterval)
{
- ehciPipePointer->startFrame = (uframeIntervalIndex >> 3);
- ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007);
+ ehciPipePointer->startFrame = (uframeIntervalIndex >> 3);
+ ehciPipePointer->startUframe = (uint8_t)(uframeIntervalIndex & 0x0007U);
ehciPipePointer->uframeSmask = 0; /* useless */
ehciPipePointer->uframeCmask = 0;
- ehciPipePointer->dataTime = FslsTime;
+ ehciPipePointer->dataTime = (uint16_t)FslsTime;
return kStatus_USB_Success;
}
@@ -1754,46 +1719,46 @@ static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *
static uint8_t USB_HostEhciGet2PowerValue(uint8_t value)
{
- if ((value == 0) || (value == 1))
+ if ((value == 0U) || (value == 1U))
{
return value;
}
- if (value & 0xf0)
+ if (0U != (value & 0xf0U))
{
- if (value & 0x80)
+ if (0U != (value & 0x80U))
{
- return 128;
+ return 128U;
}
- else if (value & 0x40)
+ else if (0U != (value & 0x40U))
{
- return 64;
+ return 64U;
}
- else if (value & 0x20)
+ else if (0U != (value & 0x20U))
{
- return 32;
+ return 32U;
}
else
{
- return 16;
+ return 16U;
}
}
else
{
- if (value & 0x08)
+ if (0U != (value & 0x08U))
{
- return 8;
+ return 8U;
}
- else if (value & 0x04)
+ else if (0U != (value & 0x04U))
{
- return 4;
+ return 4U;
}
- else if (value & 0x02)
+ else if (0U != (value & 0x02U))
{
- return 2;
+ return 2U;
}
else
{
- return 1;
+ return 1U;
}
}
}
@@ -1801,8 +1766,9 @@ static uint8_t USB_HostEhciGet2PowerValue(uint8_t value)
static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length)
{
/* note: the zero unit is uint32_t */
- while (length--)
+ while (0U != length)
{
+ length--;
*buffer = 0;
buffer++;
}
@@ -1811,24 +1777,24 @@ static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length)
static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms)
{
/* note: the max delay time cannot exceed half of max value (0x4000) */
- int32_t sofStart;
- int32_t SofEnd;
+ uint32_t sofStart;
+ uint32_t SofEnd;
uint32_t distance;
- sofStart = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
+ sofStart = (ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
do
{
- SofEnd = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
- distance = (uint32_t)(SofEnd - sofStart + EHCI_MAX_UFRAME_VALUE + 1);
- } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8)); /* compute the distance between sofStart and SofEnd */
+ SofEnd = (ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
+ distance = (SofEnd + EHCI_MAX_UFRAME_VALUE + 1U - sofStart);
+ } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8U)); /* compute the distance between sofStart and SofEnd */
}
-static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance)
+void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance)
{
uint32_t stateSync;
- if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK))
+ if (0U == (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK))
{
/* the status must be same when change USBCMD->ASE */
do
@@ -1839,7 +1805,7 @@ static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance)
ehciInstance->ehciIpBase->ASYNCLISTADDR = (uint32_t)(ehciInstance->shedFirstQh);
ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_ASE_MASK;
- while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK))
+ while (0U == (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK))
{
}
}
@@ -1857,16 +1823,16 @@ static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance)
} while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK));
ehciInstance->ehciIpBase->USBCMD &= (uint32_t)(~(uint32_t)USBHS_USBCMD_ASE_MASK); /* disable async schedule */
- while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)
+ while (0U != (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK))
{
}
}
-static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance)
+void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance)
{
uint32_t stateSync;
- if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK))
+ if (0U == (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK))
{
/* the status must be same when change USBCMD->PSE */
do
@@ -1875,11 +1841,11 @@ static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance)
(ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK));
} while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK));
ehciInstance->ehciIpBase->PERIODICLISTBASE = (uint32_t)(ehciInstance->ehciFrameList);
- if (!(ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK))
+ if (0U == (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK))
{
ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_PSE_MASK; /* start periodic schedule */
}
- while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK))
+ while (0U == (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK))
{
}
}
@@ -1898,7 +1864,7 @@ static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance)
} while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK));
ehciInstance->ehciIpBase->USBCMD &= (~USBHS_USBCMD_PSE_MASK); /* stop periodic schedule */
- while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)
+ while (0U != (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK))
{
}
}
@@ -1908,7 +1874,7 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
usb_host_transfer_t *transfer)
{
volatile usb_host_ehci_qh_t *vltQhPointer;
- usb_host_ehci_qtd_t *qtdPointer = NULL;
+ usb_host_ehci_qtd_t *qtdPointer = NULL;
usb_host_ehci_qtd_t *BaseQtdPointer = NULL;
volatile uint32_t *entryPointer;
uint32_t qtdNumber;
@@ -1921,19 +1887,23 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL)
{
/* assume setup data don't exceed one qtd data size, one qtd can transfer least 16k data */
- if (transfer->transferLength == 0)
+ if (transfer->transferLength == 0U)
{
- qtdNumber = 2;
+ qtdNumber = 2U;
}
else
{
- qtdNumber = 3;
+ qtdNumber = 3U;
}
}
else
{
- qtdNumber =
- (((transfer->transferLength) & 0xFFFFC000U) >> 14) + (((transfer->transferLength) & 0x00003FFF) ? 1 : 0);
+ qtdNumber = (((transfer->transferLength) & 0xFFFFC000U) >> 14U) +
+ (0U != ((transfer->transferLength) & 0x00003FFFU) ? 1U : 0U);
+ if (0U == qtdNumber)
+ {
+ qtdNumber = 1U;
+ }
}
vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
@@ -1941,20 +1911,21 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
USB_HostEhciLock();
if (qtdNumber <= ehciInstance->ehciQtdNumber)
{
- ehciInstance->ehciQtdNumber -= qtdNumber;
+ ehciInstance->ehciQtdNumber -= (uint8_t)qtdNumber;
BaseQtdPointer = ehciInstance->ehciQtdHead;
- qtdPointer = NULL;
+ qtdPointer = NULL;
do
{
if (qtdPointer != NULL)
{
qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead;
}
- qtdPointer = ehciInstance->ehciQtdHead;
- ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer;
+ qtdPointer = ehciInstance->ehciQtdHead;
+ ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer;
qtdPointer->nextQtdPointer = 0;
- } while (--qtdNumber);
- if (ehciInstance->ehciQtdNumber == 0)
+ --qtdNumber;
+ } while (0U != qtdNumber);
+ if (ehciInstance->ehciQtdNumber == 0U)
{
ehciInstance->ehciQtdTail = NULL;
}
@@ -1970,34 +1941,34 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL)
{
/* setup transaction qtd */
- qtdPointer = BaseQtdPointer;
+ qtdPointer = BaseQtdPointer;
qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
/* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */
- qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0;
+ qtdPointer->transferResults[1] = 0U;
qtdPointer->transferResults[0] =
- ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) |
+ ((0x00000000UL << EHCI_HOST_QTD_DT_SHIFT) | (8UL << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) |
(EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK));
- dataAddress = ((uint32_t)transfer->setupPacket);
+ dataAddress = ((uint32_t)transfer->setupPacket);
qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */
/* set buffer pointer no matter data length */
- for (index = 0; index < 4; ++index)
+ for (index = 0; index < 4U; ++index)
{
- qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U);
+ qtdPointer->bufferPointers[index] = ((dataAddress + ((uint32_t)index + 1U) * 4U * 1024U) & 0xFFFFF000U);
}
/* data transaction qtd */
dataLength = transfer->transferLength;
- if (dataLength != 0)
+ if (dataLength != 0U)
{
qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer);
qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
/* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */
- qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0;
+ qtdPointer->transferResults[1] = 0U;
if (transfer->direction == USB_OUT)
{
qtdPointer->transferResults[0] =
- ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) |
+ ((0x00000001UL << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) |
(EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK));
}
else
@@ -2007,24 +1978,24 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
(EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK));
}
- dataAddress = (uint32_t)transfer->transferBuffer;
+ dataAddress = (uint32_t)transfer->transferBuffer;
qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */
/* set buffer pointer no matter data length */
- for (index = 0; index < 4; ++index)
+ for (index = 0; index < 4U; ++index)
{
- qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U);
+ qtdPointer->bufferPointers[index] = ((dataAddress + ((uint32_t)index + 1U) * 4U * 1024U) & 0xFFFFF000U);
}
}
/* status transaction qtd */
- qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer);
+ qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer);
qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
/* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */
- qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0;
- if ((dataLength == 0) || (transfer->direction == USB_OUT))
+ qtdPointer->transferResults[1] = 0;
+ if ((dataLength == 0U) || (transfer->direction == USB_OUT))
{
qtdPointer->transferResults[0] =
- ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) |
+ ((0x00000001UL << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) |
(EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK));
}
else
@@ -2037,12 +2008,11 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
}
else
{
- dataLength = transfer->transferLength;
dataAddress = (uint32_t)transfer->transferBuffer;
- qtdPointer = BaseQtdPointer;
- while (1)
+ qtdPointer = BaseQtdPointer;
+ while (1U == 1U)
{
- endAddress = dataAddress + (16 * 1024);
+ endAddress = dataAddress + (16U * 1024U);
if (endAddress > (uint32_t)(transfer->transferBuffer + transfer->transferLength))
{
endAddress = (uint32_t)(transfer->transferBuffer + transfer->transferLength);
@@ -2050,7 +2020,7 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
/* dt: set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */
- qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0;
+ qtdPointer->transferResults[1] = 0U;
if (transfer->direction == USB_OUT)
{
qtdPointer->transferResults[0] =
@@ -2069,13 +2039,13 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
}
qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */
/* set buffer pointer no matter data length */
- for (index = 0; index < 4; ++index)
+ for (index = 0; index < 4U; ++index)
{
- qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U);
+ qtdPointer->bufferPointers[index] = ((dataAddress + ((uint32_t)index + 1U) * 4U * 1024U) & 0xFFFFF000U);
}
dataAddress = endAddress; /* for next qtd */
- if (qtdPointer->nextQtdPointer == 0)
+ if (qtdPointer->nextQtdPointer == 0U)
{
break;
}
@@ -2093,24 +2063,25 @@ static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInst
transfer->next = NULL;
if (vltQhPointer->ehciTransferHead == NULL)
{
- transfer->next = NULL;
- vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer;
+ transfer->next = NULL;
+ vltQhPointer->ehciTransferTail = transfer;
+ vltQhPointer->ehciTransferHead = transfer;
}
else
{
- transfer->next = NULL;
+ transfer->next = NULL;
vltQhPointer->ehciTransferTail->next = transfer;
- vltQhPointer->ehciTransferTail = transfer;
+ vltQhPointer->ehciTransferTail = transfer;
}
USB_HostEhciLock();
/* link qtd to qh (link to end) */
entryPointer = &(vltQhPointer->nextQtdPointer);
- dataAddress = *entryPointer; /* dataAddress variable means entry value here */
- while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE)))
+ dataAddress = *entryPointer; /* dataAddress variable means entry value here */
+ while ((0U != dataAddress) && (0U == (dataAddress & EHCI_HOST_T_INVALID_VALUE)))
{
entryPointer = (volatile uint32_t *)dataAddress;
- dataAddress = *entryPointer;
+ dataAddress = *entryPointer;
}
*entryPointer = (uint32_t)BaseQtdPointer;
USB_HostEhciUnlock();
@@ -2126,7 +2097,7 @@ static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstanc
uint32_t length = 0;
usb_host_ehci_qtd_t *qtdPointer;
- ehciQtdEnd->nextQtdPointer = 0;
+ ehciQtdEnd->nextQtdPointer = 0U;
/* compute remaining length */
qtdPointer = ehciQtdStart;
@@ -2141,7 +2112,7 @@ static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstanc
/* put releasing qtd to idle qtd list */
USB_HostEhciLock();
- if (ehciInstance->ehciQtdNumber == 0)
+ if (ehciInstance->ehciQtdNumber == 0U)
{
ehciInstance->ehciQtdHead = ehciQtdStart;
ehciInstance->ehciQtdTail = ehciQtdEnd;
@@ -2149,7 +2120,7 @@ static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstanc
else
{
ehciInstance->ehciQtdTail->nextQtdPointer = (uint32_t)ehciQtdStart;
- ehciInstance->ehciQtdTail = ehciQtdEnd;
+ ehciInstance->ehciQtdTail = ehciQtdEnd;
}
while (ehciQtdStart != ehciQtdEnd)
@@ -2169,37 +2140,41 @@ static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciIn
volatile usb_host_ehci_qh_t *vltQhPointer;
usb_host_transfer_t *transfer;
usb_host_transfer_t *nextTransfer;
- uint8_t needStop = 0;
+ uint32_t currentQtdPointer;
+ uint8_t needStop = 0U;
vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */
/* remove qtd from qh */
- if ((!((uint32_t)vltQhPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)) ||
- (!((uint32_t)vltQhPointer->currentQtdPointer & EHCI_HOST_T_INVALID_VALUE)))
+ /*for misra 13.5*/
+ currentQtdPointer = vltQhPointer->currentQtdPointer;
+ if ((0U == ((uint32_t)vltQhPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)) ||
+ (0U == ((uint32_t)currentQtdPointer & EHCI_HOST_T_INVALID_VALUE)))
{
/* need stop async schedule */
- if ((!(vltQhPointer->horizontalLinkPointer & EHCI_HOST_T_INVALID_VALUE)) &&
+ if ((0U == (vltQhPointer->horizontalLinkPointer & EHCI_HOST_T_INVALID_VALUE)) &&
(ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT))
{
- needStop = 1;
+ needStop = 1U;
}
- if (needStop)
+ if (0U != needStop)
{
USB_HostEhciStopAsync(ehciInstance);
}
vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */
- vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */
+ vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */
vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */
- if (needStop)
+ if (0U != needStop)
{
USB_HostEhciStartAsync(ehciInstance);
}
}
/* remove transfer from the QH transfer list */
- transfer = vltQhPointer->ehciTransferHead;
- vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = NULL;
+ transfer = vltQhPointer->ehciTransferHead;
+ vltQhPointer->ehciTransferTail = NULL;
+ vltQhPointer->ehciTransferHead = NULL;
USB_HostEhciUnlock();
/* release qtd and transfer callback*/
@@ -2210,8 +2185,9 @@ static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciIn
USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead),
(usb_host_ehci_qtd_t *)(transfer->union2.unitTail));
transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ?
- 0 :
+ 0U :
(transfer->transferLength - transfer->transferSofar);
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel);
transfer = nextTransfer;
}
@@ -2233,13 +2209,14 @@ static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *
USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */
/* remove qtd from qh */
- qhNextQtdValue = (uint32_t)vltQhPointer->currentQtdPointer;
+ qhNextQtdValue = (uint32_t)vltQhPointer->currentQtdPointer;
qtdPointerEntry = *((uint32_t *)qhNextQtdValue + 2); /* note: qtdPointerEntry means qtd status */
- if ((qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE) || (!(qtdPointerEntry & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)))
+ if ((0U != (qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) ||
+ (0U == (qtdPointerEntry & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)))
{
qhNextQtdValue = (uint32_t)vltQhPointer->nextQtdPointer;
}
- if (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) /* there is pending qtd in the qh */
+ if (0U == (qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) /* there is pending qtd in the qh */
{
/* this qh don't schedule temporarily */
if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT)
@@ -2255,11 +2232,11 @@ static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *
/* remove qtd from qh one by one */
qtdPointerEntry = transfer->union1.unitHead;
- while (1)
+ while (1U == 1U)
{
/* search qh's qtd list for qtdPointerEntry */
searchQtdEntryPointer = &qhNextQtdValue;
- while (!((*searchQtdEntryPointer) & EHCI_HOST_T_INVALID_VALUE))
+ while (0U == ((*searchQtdEntryPointer) & EHCI_HOST_T_INVALID_VALUE))
{
if ((*searchQtdEntryPointer) == qtdPointerEntry)
{
@@ -2306,13 +2283,15 @@ static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *
transfer->transferSofar =
USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead),
(usb_host_ehci_qtd_t *)(transfer->union2.unitTail));
- transfer->transferSofar =
- (transfer->transferLength < transfer->transferSofar) ? 0 : (transfer->transferLength - transfer->transferSofar);
+ transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ?
+ 0U :
+ (transfer->transferLength - transfer->transferSofar);
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel);
/* start this qh schedule */
vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */
- if ((qhNextQtdValue != 0) && (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)))
+ if ((qhNextQtdValue != 0U) && (0U == (qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)))
{
vltQhPointer->nextQtdPointer = qhNextQtdValue;
}
@@ -2323,9 +2302,14 @@ static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *
static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer)
{
usb_host_ehci_qh_t *qhPointer = NULL;
- uint32_t address, speed, portNumber, hubNumber;
- uint32_t controlBits1 = 0;
- uint32_t controlBits2 = 0;
+ uint32_t address = 0;
+ uint32_t speed = 0;
+ uint32_t portNumber = 0;
+ uint32_t hubNumber = 0;
+ ;
+ uint32_t controlBits1 = 0U;
+ uint32_t controlBits2 = 0U;
+
/* get qh */
USB_HostEhciLock();
if (ehciInstance->ehciQhList != NULL)
@@ -2345,26 +2329,27 @@ static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, u
ehciPipePointer->ehciQh = (void *)qhPointer;
/* initialize qh */
- USB_HostEhciZeroMem((uint32_t *)qhPointer, sizeof(usb_host_ehci_qh_t) / 4);
- qhPointer->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE;
- qhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE;
- qhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
+ USB_HostEhciZeroMem((void *)qhPointer, sizeof(usb_host_ehci_qh_t) / 4U);
+ qhPointer->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE;
+ qhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE;
+ qhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
qhPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
- qhPointer->ehciPipePointer = ehciPipePointer;
- qhPointer->timeOutLabel = 0;
- qhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed);
+ qhPointer->ehciPipePointer = ehciPipePointer;
+ qhPointer->timeOutLabel = 0;
+ qhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
/* initialize staticEndpointStates[0] */
if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)
{
/* Software should set the RL field to zero if the queue head is an interrupt endpoint. */
- controlBits1 |= ((0U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK);
+ controlBits1 |= ((0UL << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK);
}
else
{
- if (ehciPipePointer->pipeCommon.nakCount >= 16)
+ if (ehciPipePointer->pipeCommon.nakCount >= 16U)
{
- controlBits1 |= ((15U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK);
+ controlBits1 |= ((15UL << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK);
}
else
{
@@ -2376,15 +2361,15 @@ static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, u
{
if (speed != USB_SPEED_HIGH)
{
- controlBits1 |= (1 << EHCI_HOST_QH_C_SHIFT);
+ controlBits1 |= (1UL << EHCI_HOST_QH_C_SHIFT);
}
- controlBits1 |= (1 << EHCI_HOST_QH_DTC_SHIFT);
+ controlBits1 |= (1UL << EHCI_HOST_QH_DTC_SHIFT);
}
controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT);
controlBits1 |= (speed << EHCI_HOST_QH_EPS_SHIFT);
controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_QH_ENDPT_SHIFT);
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress,
- &address);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceAddress, &address);
controlBits1 |= (address << EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT);
qhPointer->staticEndpointStates[0] = controlBits1;
if (speed == USB_SPEED_HIGH)
@@ -2393,22 +2378,22 @@ static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, u
}
else
{
- controlBits2 |= (0x00000001U << EHCI_HOST_QH_MULT_SHIFT);
+ controlBits2 |= (0x00000001UL << EHCI_HOST_QH_MULT_SHIFT);
}
/*initialize staticEndpointStates[1] */
if (speed != USB_SPEED_HIGH)
{
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber,
- &hubNumber);
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubPort,
- &portNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHSHubNumber, &hubNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHSHubPort, &portNumber);
}
else
{
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber,
- &hubNumber);
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber,
- &portNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHubNumber, &hubNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDevicePortNumber, &portNumber);
}
controlBits2 |= (portNumber << EHCI_HOST_QH_PORT_NUMBER_SHIFT);
controlBits2 |= (hubNumber << EHCI_HOST_QH_HUB_ADDR_SHIFT);
@@ -2425,12 +2410,12 @@ static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance,
qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
/* de-initialize qtd from qh */
- USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer);
+ (void)USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer);
/* release QH */
USB_HostEhciLock();
qhPointer->horizontalLinkPointer = (uint32_t)ehciInstance->ehciQhList;
- ehciInstance->ehciQhList = qhPointer;
+ ehciInstance->ehciQhList = qhPointer;
USB_HostEhciUnlock();
return kStatus_USB_Success;
@@ -2443,17 +2428,19 @@ static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance,
{
volatile uint32_t *frameEntryPointer;
uint32_t frameEntryValue;
+ void *temp;
/* search for the inserting point by interval */
- frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]);
- while (frameEntryPointer)
+ temp = (void *)ehciInstance->ehciFrameList;
+ frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)temp)[framePos]);
+ while (NULL != frameEntryPointer)
{
frameEntryValue = *frameEntryPointer;
- if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE)
+ if (0U != (frameEntryValue & EHCI_HOST_T_INVALID_VALUE))
{
/* insert into the end */
*((uint32_t *)entryPointerValue) = EHCI_HOST_T_INVALID_VALUE;
- *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH);
+ *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH);
break;
}
@@ -2467,7 +2454,7 @@ static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance,
{
/* insert into this point */
*((uint32_t *)entryPointerValue) = frameEntryValue;
- *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH);
+ *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH);
return;
}
else
@@ -2483,14 +2470,15 @@ static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance,
{
volatile uint32_t *frameEntryPointer;
uint32_t frameEntryValue;
-
+ void *temp;
/* search for the qh/itd/sitd entry */
- frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]);
+ temp = (void *)ehciInstance->ehciFrameList;
+ frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)temp)[framePos]);
- while (frameEntryPointer)
+ while (NULL != frameEntryPointer)
{
frameEntryValue = *frameEntryPointer;
- if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE)
+ if (0U != (frameEntryValue & EHCI_HOST_T_INVALID_VALUE))
{
return;
}
@@ -2517,53 +2505,71 @@ static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance,
usb_host_ehci_sitd_t *sitdPointer;
uint32_t distance;
uint32_t frameInterval;
- int32_t shouldLinkFrame;
- int32_t currentFrame;
+ uint32_t shouldLinkFrame;
+ uint32_t currentFrame;
+ void *temp;
- frameInterval = (ehciPipePointer->uframeInterval >> 3);
+ frameInterval = ((uint32_t)ehciPipePointer->uframeInterval >> 3U);
- if (isoPointer->lastLinkFrame == 0xFFFF) /* first link */
+ if (isoPointer->lastLinkFrame == 0xFFFFU) /* first link */
{
- currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3);
+ currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & USB_HOST_EHCI_MAX_MICRFRAME_VALUE) >> 3U);
currentFrame = ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) &
- (EHCI_MAX_UFRAME_VALUE >> 3)); /* add USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER */
+ (USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3U)); /* add USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER */
/* frame should align with interval */
- currentFrame -= ehciPipePointer->startFrame;
- currentFrame =
- ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); /* frameInterval is power of 2 */
- currentFrame += ehciPipePointer->startFrame;
+ if (currentFrame <= ehciPipePointer->startFrame)
+ {
+ currentFrame = ehciPipePointer->startFrame;
+ }
+ else
+ {
+ currentFrame -= ehciPipePointer->startFrame;
+ currentFrame = ((currentFrame + frameInterval - 1U) & (~(frameInterval - 1U)));
+ currentFrame += ehciPipePointer->startFrame;
+ }
}
else
{
shouldLinkFrame = isoPointer->lastLinkFrame + frameInterval; /* continuous next should link frame */
- if (shouldLinkFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3))
+ if (shouldLinkFrame > USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3U)
{
- shouldLinkFrame = shouldLinkFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1);
+ shouldLinkFrame = shouldLinkFrame - ((USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3U) + 1U);
}
- currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3);
- distance = ((shouldLinkFrame - currentFrame + (EHCI_MAX_UFRAME_VALUE >> 3) + 1) &
- (EHCI_MAX_UFRAME_VALUE >> 3)); /* get the distance from shouldLinkFrame to currentFrame */
+ currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & USB_HOST_EHCI_MAX_MICRFRAME_VALUE) >> 3U);
+ distance =
+ ((shouldLinkFrame + (USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3U) + 1U - currentFrame) &
+ (USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3)); /* get the distance from shouldLinkFrame to currentFrame */
/* shouldLinkFrame has add frameInterval, think about the align with interval, so here add (frameInterval *
* 2) */
- if ((distance <= (USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER + frameInterval * 2)) && (distance > 0))
+ if ((distance <=
+ (USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER + frameInterval * USB_HOST_EHCI_ISO_MAX_CONTINUOUS_TRANSFER)) &&
+ (distance > 0U))
{
currentFrame = shouldLinkFrame;
}
else /* re-link */
{
currentFrame =
- ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & (EHCI_MAX_UFRAME_VALUE >> 3));
- if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3))
+ ((currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & (USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3));
+
+ /*if (currentFrame > (USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3))
{
- currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1);
- }
+ currentFrame = currentFrame - ((USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3) + 1U);
+ }*/
/* frame should align with interval */
- currentFrame -= ehciPipePointer->startFrame;
- currentFrame = ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1)));
- currentFrame += ehciPipePointer->startFrame;
+ if (currentFrame <= ehciPipePointer->startFrame)
+ {
+ currentFrame = ehciPipePointer->startFrame;
+ }
+ else
+ {
+ currentFrame -= ehciPipePointer->startFrame;
+ currentFrame = ((currentFrame + frameInterval - 1U) & (~(frameInterval - 1U)));
+ currentFrame += ehciPipePointer->startFrame;
+ }
}
}
- if (currentFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) /* frame turn around */
+ if (currentFrame >= USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) /* frame turn around */
{
shouldLinkFrame =
(currentFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); /* shouldLinkFrame means inserted frame position */
@@ -2574,14 +2580,14 @@ static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance,
}
sitdPointer = (usb_host_ehci_sitd_t *)startEntryPointer;
- while (sitdPointer)
+ while (NULL != sitdPointer)
{
- sitdPointer->frameEntryIndex = shouldLinkFrame;
+ sitdPointer->frameEntryIndex = (uint16_t)shouldLinkFrame;
/* add to frame list head */
- sitdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame];
- ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame] =
- ((uint32_t)sitdPointer | EHCI_HOST_POINTER_TYPE_SITD);
- if (sitdPointer->nextSitdIndex == 0xFF) /* 0xFF is invalid value */
+ temp = (void *)ehciInstance->ehciFrameList;
+ sitdPointer->nextLinkPointer = ((uint32_t *)temp)[shouldLinkFrame];
+ ((uint32_t *)temp)[shouldLinkFrame] = ((uint32_t)sitdPointer | EHCI_HOST_POINTER_TYPE_SITD);
+ if (sitdPointer->nextSitdIndex == 0xFFU) /* 0xFF is invalid value */
{
break;
}
@@ -2589,17 +2595,17 @@ static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance,
shouldLinkFrame += frameInterval;
currentFrame += frameInterval;
- if (shouldLinkFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE)
+ if (shouldLinkFrame >= USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE)
{
shouldLinkFrame = (shouldLinkFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE);
}
}
- if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3))
+ if (currentFrame > (USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3))
{
- currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1);
+ currentFrame = currentFrame - ((USB_HOST_EHCI_MAX_MICRFRAME_VALUE >> 3) + 1U);
}
- isoPointer->lastLinkFrame = currentFrame; /* save the last link frame value */
+ isoPointer->lastLinkFrame = (uint16_t)currentFrame; /* save the last link frame value */
}
static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance,
@@ -2612,33 +2618,35 @@ static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInst
uint32_t dataLength = 0;
uint32_t sitdLength = 0;
uint32_t dataBufferValue;
- uint32_t hubNumber;
- uint32_t portNumber;
- uint32_t address;
+ uint32_t hubNumber = 0U;
+ uint32_t portNumber = 0U;
+ uint32_t address = 0U;
uint32_t tmp;
- uint8_t index;
+ uint32_t *temp;
+ uint32_t index;
+ int32_t tempIndex;
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceAddress, &address);
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress,
- &address);
-
- sitdNumber = ((transfer->transferLength - 1 + (ehciPipePointer->pipeCommon.maxPacketSize)) /
+ sitdNumber = ((transfer->transferLength - 1U + (ehciPipePointer->pipeCommon.maxPacketSize)) /
(ehciPipePointer->pipeCommon.maxPacketSize));
/* get sitd array */
- tmp = ehciPipePointer - ehciInstance->ehciPipeIndexBase; /* pipe index */
/* USB_HostEhciLock(); */
if (ehciInstance->ehciSitdNumber >= sitdNumber)
{
- sitdPointer = ehciInstance->ehciSitdList;
+ sitdPointer = ehciInstance->ehciSitdList;
transfer->union1.unitHead = (uint32_t)sitdPointer;
- for (index = 1; index < sitdNumber; ++index)
+ for (index = 1U; index < sitdNumber; ++index)
{
- sitdPointer->nextSitdIndex =
- (((usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer) - ehciInstance->ehciSitdIndexBase);
- sitdPointer = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer;
+ /*misra 10.8*/
+ tempIndex = (((usb_host_ehci_sitd_t *)(sitdPointer->nextLinkPointer & 0xFFFFFFFEU)) -
+ ehciInstance->ehciSitdIndexBase);
+ sitdPointer->nextSitdIndex = (uint8_t)tempIndex;
+ sitdPointer = (usb_host_ehci_sitd_t *)(sitdPointer->nextLinkPointer & 0xFFFFFFFEU);
}
sitdPointer->nextSitdIndex = 0xFF;
- ehciInstance->ehciSitdList = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer;
- ehciInstance->ehciSitdNumber -= sitdNumber;
+ ehciInstance->ehciSitdList = (usb_host_ehci_sitd_t *)(sitdPointer->nextLinkPointer & 0xFFFFFFFEU);
+ ehciInstance->ehciSitdNumber -= (uint8_t)sitdNumber;
}
else
{
@@ -2648,15 +2656,16 @@ static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInst
/* USB_HostEhciUnlock(); */
transfer->union2.unitTail = (uint32_t)sitdPointer;
/* initialize sitd array */
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber,
- &hubNumber);
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber,
- &portNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceHubNumber, &hubNumber);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDevicePortNumber, &portNumber);
sitdPointer = (usb_host_ehci_sitd_t *)transfer->union1.unitHead;
- dataLength = transfer->transferLength;
- while (sitdNumber--)
+ dataLength = transfer->transferLength;
+ while (0U != sitdNumber)
{
- USB_HostEhciZeroMem((uint32_t *)sitdPointer, 7);
+ sitdNumber--;
+ USB_HostEhciZeroMem((void *)sitdPointer, 7);
sitdLength = dataLength;
if (sitdLength > ehciPipePointer->pipeCommon.maxPacketSize)
{
@@ -2665,7 +2674,7 @@ static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInst
dataBufferValue = (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength));
dataLength -= sitdLength; /* update left data length */
sitdPointer->transferResults[1] = dataBufferValue;
- sitdPointer->transferResults[2] = ((dataBufferValue + 4 * 1024) & 0xFFFFF000U);
+ sitdPointer->transferResults[2] = ((dataBufferValue + 4U * 1024U) & 0xFFFFF000U);
sitdPointer->endpointStates[0] =
(((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_SITD_DIRECTION_SHIFT) |
(portNumber << EHCI_HOST_SITD_PORT_NUMBER_SHIFT) | (hubNumber << EHCI_HOST_SITD_HUB_ADDR_SHIFT) |
@@ -2679,14 +2688,14 @@ static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInst
sitdPointer->endpointStates[1] = (((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_SITD_CMASK_SHIFT) |
((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_SITD_SMASK_SHIFT));
- tmp = (sitdLength + 187) / 188;
- if (tmp > 1)
+ tmp = (sitdLength + 187U) / 188U;
+ if (tmp > 1U)
{
- sitdPointer->transferResults[2] |= (0x01 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */
+ sitdPointer->transferResults[2] |= (0x01U << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */
}
else
{
- sitdPointer->transferResults[2] |= (0x00 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */
+ sitdPointer->transferResults[2] |= (0x00U << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */
}
sitdPointer->transferResults[2] |= (tmp << EHCI_HOST_SITD_TCOUNT_SHIFT); /* for iso split */
}
@@ -2696,26 +2705,29 @@ static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInst
sitdPointer = (ehciInstance->ehciSitdIndexBase + sitdPointer->nextSitdIndex);
}
sitdPointer = (usb_host_ehci_sitd_t *)transfer->union2.unitTail;
- sitdPointer->transferResults[0] |= (1U << EHCI_HOST_SITD_IOC_SHIFT); /* last set IOC */
+ sitdPointer->transferResults[0] |= (1UL << EHCI_HOST_SITD_IOC_SHIFT); /* last set IOC */
/* link transfer to usb_host_ehci_iso_t transfer list */
isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh;
USB_HostEhciLock();
if (isoPointer->ehciTransferHead == NULL)
{
- transfer->next = NULL;
- isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer;
+ transfer->next = NULL;
+ isoPointer->ehciTransferTail = transfer;
+ isoPointer->ehciTransferHead = transfer;
}
else
{
- transfer->next = NULL;
+ transfer->next = NULL;
isoPointer->ehciTransferTail->next = transfer;
- isoPointer->ehciTransferTail = transfer;
+ isoPointer->ehciTransferTail = transfer;
}
USB_HostEhciUnlock();
/* link itd to frame list (note: initialize frameEntryIndex)*/
- USB_HostEhciLinkSitd(ehciInstance, ehciPipePointer, (void *)transfer->union1.unitHead);
+ /*misra 11.6*/
+ temp = (uint32_t *)(transfer->union1.unitHead);
+ USB_HostEhciLinkSitd(ehciInstance, ehciPipePointer, (void *)temp);
return kStatus_USB_Success;
}
@@ -2725,9 +2737,9 @@ static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInsta
usb_host_ehci_sitd_t *endSitdPointer)
{
usb_host_ehci_sitd_t *sitdPointer = startSitdPointer;
- uint32_t leftLength = 0;
+ uint32_t leftLength = 0;
/* remove itd from frame list */
- while (1)
+ while (1U == 1U)
{
/* record the transfer's result length */
leftLength +=
@@ -2737,8 +2749,9 @@ static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInsta
/* release itd */
/* USB_HostEhciLock(); */
- sitdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciSitdList;
- ehciInstance->ehciSitdList = sitdPointer;
+ /*set next link pointer to invalid in case hardware access invalid sitd structure in special case*/
+ sitdPointer->nextLinkPointer = (((uint32_t)ehciInstance->ehciSitdList) | EHCI_HOST_T_INVALID_VALUE);
+ ehciInstance->ehciSitdList = sitdPointer;
ehciInstance->ehciSitdNumber++;
/* USB_HostEhciUnlock(); */
@@ -2762,8 +2775,9 @@ static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciIn
/* firstly remove the transfer (because host task may occupy to access the resource) */
USB_HostEhciLock();
- transfer = isoPointer->ehciTransferHead;
- isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL;
+ transfer = isoPointer->ehciTransferHead;
+ isoPointer->ehciTransferTail = NULL;
+ isoPointer->ehciTransferHead = NULL;
USB_HostEhciUnlock();
while (transfer != NULL)
@@ -2774,7 +2788,7 @@ static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciIn
transfer->transferLength - USB_HostEhciSitdArrayRelease(ehciInstance,
(usb_host_ehci_sitd_t *)transfer->union1.unitHead,
(usb_host_ehci_sitd_t *)transfer->union2.unitTail);
- /* transfer callback */
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel);
/* next transfer */
transfer = nextTransfer;
@@ -2790,50 +2804,66 @@ static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstan
uint16_t startUframe,
uint16_t uframeInterval)
{
- int32_t shouldLinkUframe;
- int32_t currentUframe;
- int32_t distance;
+ uint32_t shouldLinkUframe;
+ uint32_t currentUframe;
+ uint32_t distance;
- if (lastLinkUframe != 0xFFFF)
+ if (lastLinkUframe != 0xFFFFU)
{
shouldLinkUframe = lastLinkUframe + uframeInterval;
- if (shouldLinkUframe > (int32_t)EHCI_MAX_UFRAME_VALUE)
+ if (shouldLinkUframe > USB_HOST_EHCI_MAX_MICRFRAME_VALUE)
{
- shouldLinkUframe = shouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1);
+ shouldLinkUframe = shouldLinkUframe - (USB_HOST_EHCI_MAX_MICRFRAME_VALUE + 1U);
}
- currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
- distance = ((shouldLinkUframe - currentUframe + EHCI_MAX_UFRAME_VALUE + 1) &
- EHCI_MAX_UFRAME_VALUE); /* get the distance */
+ currentUframe = (ehciInstance->ehciIpBase->FRINDEX & USB_HOST_EHCI_MAX_MICRFRAME_VALUE);
+ distance = ((shouldLinkUframe + USB_HOST_EHCI_MAX_MICRFRAME_VALUE + 1U - currentUframe) &
+ USB_HOST_EHCI_MAX_MICRFRAME_VALUE); /* get the distance */
/* shouldLinkUframe has add uframeInterval, think about the align with interval, so here add (uframeInterval
* * 2) */
- if ((distance <= (int32_t)(USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER + (uframeInterval * 2))) && (distance > 2))
+ if ((distance <= ((uint32_t)USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER +
+ ((uint32_t)uframeInterval * USB_HOST_EHCI_ISO_MAX_CONTINUOUS_TRANSFER))) &&
+ (distance > 2U))
{
currentUframe = shouldLinkUframe;
}
else /* re-link */
{
currentUframe =
- ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE);
- if (currentUframe > (int32_t)EHCI_MAX_UFRAME_VALUE)
+ ((currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & USB_HOST_EHCI_MAX_MICRFRAME_VALUE);
+ /*if (currentUframe > USB_HOST_EHCI_MAX_MICRFRAME_VALUE)
{
- currentUframe = currentUframe - (EHCI_MAX_UFRAME_VALUE + 1);
- }
+ currentUframe = currentUframe - (USB_HOST_EHCI_MAX_MICRFRAME_VALUE + 1U);
+ }*/
/* uframe should align with interval */
- currentUframe -= startUframe;
- currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) &
- (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */
- currentUframe += startUframe;
+ if (currentUframe <= startUframe)
+ {
+ currentUframe = startUframe;
+ }
+ else
+ {
+ currentUframe -= startUframe;
+ currentUframe = ((uint32_t)(currentUframe + uframeInterval) &
+ (~((uint32_t)uframeInterval - 1U))); /* uframeInterval is power of 2 */
+ currentUframe += startUframe;
+ }
}
}
else
{
- currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
- currentUframe = ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE);
+ currentUframe = (ehciInstance->ehciIpBase->FRINDEX & USB_HOST_EHCI_MAX_MICRFRAME_VALUE);
+ currentUframe = ((currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & USB_HOST_EHCI_MAX_MICRFRAME_VALUE);
/* uframe should align with interval */
- currentUframe -= startUframe;
- currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) &
- (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */
- currentUframe += startUframe;
+ if (currentUframe <= startUframe)
+ {
+ currentUframe = startUframe;
+ }
+ else
+ {
+ currentUframe -= startUframe;
+ currentUframe =
+ ((currentUframe + uframeInterval) & (~(uframeInterval - 1U))); /* uframeInterval is power of 2 */
+ currentUframe += startUframe;
+ }
}
return currentUframe;
@@ -2845,27 +2875,29 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
{
usb_host_ehci_iso_t *isoPointer;
usb_host_ehci_itd_t *itdPointer = NULL;
+ usb_host_ehci_itd_t *itdHead = NULL;
usb_host_ehci_itd_t *tmpItdPointer;
uint32_t dataLength; /* the remaining data for sending */
uint32_t transactionLength; /* the initializing transaction descriptor data length */
uint32_t itdBufferValue;
uint32_t itdBufferBaseValue; /* for calculating PG value */
- uint32_t address;
+ uint32_t address = 0U;
uint32_t lastShouldLinkUframe;
uint32_t linkUframe;
- uint32_t minDataPerItd = ehciPipePointer->pipeCommon.numberPerUframe * ehciPipePointer->pipeCommon.maxPacketSize;
+ uint32_t minDataPerItd =
+ (uint32_t)ehciPipePointer->pipeCommon.numberPerUframe * ehciPipePointer->pipeCommon.maxPacketSize;
uint8_t maxItdNumber;
- uint8_t index = 0;
+ uint16_t index = 0;
isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress,
- &address);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceAddress, &address);
/* max needed itd number, the actual needed number may be less because micro-frame interval may be less than 8 */
- maxItdNumber = ((transfer->transferLength - 1 + minDataPerItd) / minDataPerItd);
- if (ehciPipePointer->uframeInterval < 8)
+ maxItdNumber = (uint8_t)((transfer->transferLength - 1U + minDataPerItd) / minDataPerItd);
+ if (ehciPipePointer->uframeInterval < 8U)
{
- maxItdNumber = ((maxItdNumber * ehciPipePointer->uframeInterval + 7) / 8) + 1;
+ maxItdNumber = (uint8_t)((maxItdNumber * ehciPipePointer->uframeInterval + 7U) / 8U) + 1U;
}
if (maxItdNumber > ehciInstance->ehciItdNumber)
{
@@ -2877,43 +2909,46 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
/* USB_HostEhciLock(); */
if (isoPointer->ehciTransferHead == NULL)
{
- isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer;
+ isoPointer->ehciTransferTail = transfer;
+ isoPointer->ehciTransferHead = transfer;
}
else
{
isoPointer->ehciTransferTail->next = transfer;
- isoPointer->ehciTransferTail = transfer;
+ isoPointer->ehciTransferTail = transfer;
}
/* USB_HostEhciUnlock(); */
- dataLength = transfer->transferLength;
- transfer->union1.unitHead = (uint32_t)NULL;
+ dataLength = transfer->transferLength;
+ transfer->union1.unitHead = 0U;
/* get the link micro-frame */
lastShouldLinkUframe = USB_HostEhciGetItdLinkFrame(
ehciInstance, isoPointer->lastLinkFrame,
(uint16_t)((ehciPipePointer->startFrame << 3) + ehciPipePointer->startUframe), ehciPipePointer->uframeInterval);
- if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE)
+ if (lastShouldLinkUframe > USB_HOST_EHCI_MAX_MICRFRAME_VALUE)
{
- linkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1);
+ linkUframe = lastShouldLinkUframe - (USB_HOST_EHCI_MAX_MICRFRAME_VALUE + 1U);
}
else
{
linkUframe = lastShouldLinkUframe;
}
- while (dataLength)
+ itdHead = ehciInstance->ehciItdList;
+ while (0U != dataLength)
{
/* get one idle itd */
tmpItdPointer = ehciInstance->ehciItdList;
- ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)tmpItdPointer->nextLinkPointer;
- ehciInstance->ehciItdNumber -= 1;
if (tmpItdPointer == NULL)
{
return kStatus_USB_Error; /* this should not reach */
}
+ ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)tmpItdPointer->nextItdPointer;
+ ehciInstance->ehciItdNumber -= 1U;
+
tmpItdPointer->nextItdPointer = NULL;
/* use the itd */
- if (transfer->union1.unitHead == (uint32_t)NULL) /* first itd */
+ if (transfer->union1.unitHead == 0U) /* first itd */
{
transfer->union1.unitHead = (uint32_t)tmpItdPointer;
}
@@ -2924,11 +2959,11 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
itdPointer = tmpItdPointer;
/* itd has been set to all zero when releasing */
- itdBufferBaseValue = itdBufferValue =
- (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength));
- for (index = 0; index < 7; ++index)
+ itdBufferValue = (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength));
+ itdBufferBaseValue = itdBufferValue;
+ for (index = 0; index < 7U; ++index)
{
- itdPointer->bufferPointers[index] = ((itdBufferBaseValue + (index * 4 * 1024)) & 0xFFFFF000U);
+ itdPointer->bufferPointers[index] = ((itdBufferBaseValue + ((uint32_t)index * 4U * 1024U)) & 0xFFFFF000U);
}
/* initialize iTD common fields */
itdPointer->bufferPointers[0] |=
@@ -2939,7 +2974,7 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT));
itdPointer->bufferPointers[2] |= (ehciPipePointer->pipeCommon.numberPerUframe);
/* initialize transaction descriptors */
- for (index = (linkUframe & 0x0007); index < 8; index += ehciPipePointer->uframeInterval)
+ for (index = (uint8_t)(linkUframe & 0x0007U); index < 8U; index += ehciPipePointer->uframeInterval)
{
transactionLength = ((dataLength > minDataPerItd) ? minDataPerItd : dataLength);
/* initialize the uframeIndex's transaction descriptor in itd */
@@ -2951,7 +2986,7 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
(itdBufferValue & EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK));
dataLength -= transactionLength;
itdBufferValue += transactionLength;
- if (dataLength <= 0)
+ if (dataLength <= 0U)
{
break;
}
@@ -2959,17 +2994,25 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
}
transfer->union2.unitTail = (uint32_t)itdPointer;
- itdPointer->transactions[index] |= (1 << EHCI_HOST_ITD_IOC_SHIFT); /* last set IOC */
+ itdPointer->transactions[index] |= (1UL << EHCI_HOST_ITD_IOC_SHIFT); /* last set IOC */
+ itdPointer = itdHead;
/* link itd to frame list (note: initialize frameEntryIndex)*/
- while (itdPointer)
+ while (NULL != itdPointer)
{
- itdPointer->frameEntryIndex = linkUframe;
- /* add to frame head */
- itdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3];
- *(uint32_t *)((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3] =
- ((uint32_t)itdPointer | EHCI_HOST_POINTER_TYPE_ITD);
- itdPointer = itdPointer->nextItdPointer;
+ void *temp = (void *)ehciInstance->ehciFrameList;
+ uint32_t *linkPointer = &((uint32_t *)temp)[linkUframe >> 3];
+ uint32_t linkValue = *linkPointer;
+ itdPointer->frameEntryIndex = linkUframe >> 3;
+ while ((0U == (linkValue & EHCI_HOST_T_INVALID_VALUE)) &&
+ ((linkValue & EHCI_HOST_POINTER_TYPE_MASK) == EHCI_HOST_POINTER_TYPE_ITD))
+ {
+ linkPointer = (uint32_t *)(linkValue & EHCI_HOST_POINTER_ADDRESS_MASK);
+ linkValue = *linkPointer;
+ }
+ itdPointer->nextLinkPointer = *linkPointer;
+ *linkPointer = ((uint32_t)itdPointer | EHCI_HOST_POINTER_TYPE_ITD);
+ itdPointer = itdPointer->nextItdPointer;
if (itdPointer == NULL)
{
break;
@@ -2983,11 +3026,11 @@ static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInsta
}
}
- if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE)
+ if (lastShouldLinkUframe > USB_HOST_EHCI_MAX_MICRFRAME_VALUE)
{
- lastShouldLinkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1);
+ lastShouldLinkUframe = lastShouldLinkUframe - (USB_HOST_EHCI_MAX_MICRFRAME_VALUE + 1U);
}
- isoPointer->lastLinkFrame = lastShouldLinkUframe;
+ isoPointer->lastLinkFrame = (uint16_t)lastShouldLinkUframe;
return kStatus_USB_Success;
}
@@ -3001,23 +3044,24 @@ static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstan
uint32_t doneLength = 0;
/* remove itd from frame list */
- while (1)
+ while (1U == 1U)
{
/* record the transfer's result length */
- for (index = 0; index < 8; ++index)
+ for (index = 0U; index < 8U; ++index)
{
doneLength += ((itdPointer->transactions[index] & EHCI_HOST_ITD_TRANSACTION_LEN_MASK) >>
EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT);
}
USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)itdPointer,
- itdPointer->frameEntryIndex); /* remove from the inserted frame list */
+ (uint16_t)itdPointer->frameEntryIndex); /* remove from the inserted frame list */
/* release itd */
/* USB_HostEhciLock(); */
- USB_HostEhciZeroMem((uint32_t *)itdPointer, sizeof(usb_host_ehci_itd_t) >> 2);
- itdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciItdList;
- ehciInstance->ehciItdList = itdPointer;
+ /*set next link pointer to invalid in case hardware access invalid itd structure in special case*/
+ itdPointer->nextLinkPointer = EHCI_HOST_T_INVALID_VALUE;
+ itdPointer->nextItdPointer = (usb_host_ehci_itd_t *)ehciInstance->ehciItdList;
+ ehciInstance->ehciItdList = itdPointer;
ehciInstance->ehciItdNumber++;
/* USB_HostEhciUnlock(); */
@@ -3041,14 +3085,15 @@ static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciIns
/* firstly remove the transfer (because host task may occupy to access the resource) */
USB_HostEhciLock();
- transfer = isoPointer->ehciTransferHead;
- isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL;
+ transfer = isoPointer->ehciTransferHead;
+ isoPointer->ehciTransferTail = NULL;
+ isoPointer->ehciTransferHead = NULL;
USB_HostEhciUnlock();
while (transfer != NULL)
{
nextTransfer = transfer->next;
- doneLength = 0;
+ doneLength = 0;
/* remove itd from frame list and release itd */
doneLength = USB_HostEhciItdArrayRelease(ehciInstance, (usb_host_ehci_itd_t *)transfer->union1.unitHead,
(usb_host_ehci_itd_t *)transfer->union2.unitTail);
@@ -3059,6 +3104,7 @@ static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciIns
doneLength = transfer->transferLength;
}
transfer->transferSofar = doneLength;
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel);
/* next transfer */
@@ -3082,7 +3128,7 @@ static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciIn
qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
/* add qh to async */
- qhPointer->horizontalLinkPointer = ehciInstance->shedFirstQh->horizontalLinkPointer;
+ qhPointer->horizontalLinkPointer = ehciInstance->shedFirstQh->horizontalLinkPointer;
ehciInstance->shedFirstQh->horizontalLinkPointer = ((uint32_t)qhPointer | EHCI_HOST_POINTER_TYPE_QH);
return kStatus_USB_Success;
@@ -3093,10 +3139,11 @@ static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciI
{
volatile usb_host_ehci_qh_t *vltPrevQhPointer;
uint32_t horizontalLinkValue;
-
+ uint32_t *temp;
/* remove qh from async schedule */
+ temp = (uint32_t *)ehciPipePointer->ehciQh;
if ((ehciInstance->shedFirstQh->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK) ==
- (uint32_t)ehciPipePointer->ehciQh) /* the removing qh is the first qh in the async list */
+ (uint32_t)temp) /* the removing qh is the first qh in the async list */
{
USB_HostEhciStopAsync(ehciInstance);
ehciInstance->shedFirstQh->horizontalLinkPointer =
@@ -3110,8 +3157,8 @@ static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciI
while (vltPrevQhPointer != NULL)
{
horizontalLinkValue = vltPrevQhPointer->horizontalLinkPointer;
- if ((horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE) ||
- ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh) ||
+ if ((0U != (horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) ||
+ ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)temp) ||
((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciInstance->shedFirstQh))
{
break;
@@ -3121,8 +3168,10 @@ static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciI
}
/* remove the qh from async list */
- if ((vltPrevQhPointer != NULL) && (!(horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) &&
- ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh))
+ /*for misra 11.6*/
+ temp = (uint32_t *)ehciPipePointer->ehciQh;
+ if ((vltPrevQhPointer != NULL) && (0U == (horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) &&
+ ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)temp))
{
USB_HostEhciStopAsync(ehciInstance);
vltPrevQhPointer->horizontalLinkPointer =
@@ -3140,6 +3189,7 @@ static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInst
{
usb_status_t status = kStatus_USB_Success;
uint32_t frameIndex;
+ uint32_t *temp;
/* allocate bandwidth */
if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH)
@@ -3163,10 +3213,10 @@ static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInst
/* insert QH to frame list */
for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE;
- frameIndex += (ehciPipePointer->uframeInterval / 8))
+ frameIndex += (((uint32_t)ehciPipePointer->uframeInterval + 7U) / 8U))
{
- USB_HostEhciAddQhToFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex,
- ehciPipePointer->uframeInterval);
+ temp = (uint32_t *)ehciPipePointer->ehciQh;
+ USB_HostEhciAddQhToFrame(ehciInstance, (uint32_t)temp, (uint16_t)frameIndex, ehciPipePointer->uframeInterval);
}
return kStatus_USB_Success;
@@ -3176,12 +3226,13 @@ static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciIns
usb_host_ehci_pipe_t *ehciPipePointer)
{
uint32_t frameIndex;
-
+ uint32_t *temp;
/* remove from frame list */
for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE;
- frameIndex += (ehciPipePointer->uframeInterval / 8))
+ frameIndex += (((uint32_t)ehciPipePointer->uframeInterval + 7U) / 8U))
{
- USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex);
+ temp = (uint32_t *)ehciPipePointer->ehciQh;
+ USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)temp, (uint16_t)frameIndex);
}
((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer |=
EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */
@@ -3219,11 +3270,11 @@ static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance,
return kStatus_USB_Error;
}
USB_HostEhciLock();
- isoPointer = ehciInstance->ehciIsoList;
+ isoPointer = ehciInstance->ehciIsoList;
ehciInstance->ehciIsoList = ehciInstance->ehciIsoList->next;
USB_HostEhciUnlock();
isoPointer->lastLinkFrame = 0xFFFF;
- ehciPipePointer->ehciQh = isoPointer;
+ ehciPipePointer->ehciQh = isoPointer;
return status;
}
@@ -3231,31 +3282,32 @@ static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance,
static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer)
{
usb_host_ehci_iso_t *isoPointer;
- uint32_t speed;
+ uint32_t speed = 0U;
isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh;
if (isoPointer->ehciTransferHead != NULL)
{
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &speed);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
if (speed == USB_SPEED_HIGH)
{
#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD))
- USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd list and free them */
+ (void)USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd list and free them */
#endif
}
else
{
#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))
- USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd list and free them */
+ (void)USB_HostEhciSitdArrayDeinit(ehciInstance,
+ ehciPipePointer); /* de-initialize sitd list and free them */
#endif
}
}
/* release usb_host_ehci_iso_t */
USB_HostEhciLock();
- isoPointer->next = ehciInstance->ehciIsoList;
+ isoPointer->next = ehciInstance->ehciIsoList;
ehciInstance->ehciIsoList = isoPointer;
USB_HostEhciUnlock();
return kStatus_USB_Success;
@@ -3267,17 +3319,17 @@ static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance)
{
/* reset controller */
ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RST_MASK;
- while (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_RST_MASK)
+ while (0U != (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_RST_MASK))
{
}
/* set host mode */
#if (ENDIANNESS == USB_LITTLE_ENDIAN)
- ehciInstance->ehciIpBase->USBMODE |= 0x03;
+ ehciInstance->ehciIpBase->USBMODE |= 0x03U;
#else
- ehciInstance->ehciIpBase->USBMODE |= (0x03 | (0x01 << USBHS_USBMODE_ES_SHIFT));
+ ehciInstance->ehciIpBase->USBMODE |= (0x03U | (0x01U << USBHS_USBMODE_ES_SHIFT));
#endif
/* check frame list size */
- if (!(ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK))
+ if (0U == (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK))
{
#if ((USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE < 8) || (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE > 1024))
return kStatus_USB_Error;
@@ -3293,7 +3345,7 @@ static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance)
{
uint32_t tmp = 0;
- if (ehciInstance->ehciIpBase->HCSPARAMS & USBHS_HCSPARAMS_PPC_MASK) /* Ports have power port switches */
+ if (0U != (ehciInstance->ehciIpBase->HCSPARAMS & USBHS_HCSPARAMS_PPC_MASK)) /* Ports have power port switches */
{
/* only has one port */
tmp = ehciInstance->ehciIpBase->PORTSC1;
@@ -3302,41 +3354,41 @@ static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance)
}
/* set frame list size */
- if (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK)
+ if (0U != (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK))
{
#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE <= 64)
ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_FS2_MASK);
#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 64)
- ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT);
-#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 32)
- ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT);
-#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 16)
- ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT);
-#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 8)
- ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT);
+ ehciInstance->ehciIpBase->USBCMD |= (0x00U << USBHS_USBCMD_FS_SHIFT);
+#elif (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 32)
+ ehciInstance->ehciIpBase->USBCMD |= (0x01U << USBHS_USBCMD_FS_SHIFT);
+#elif (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 16)
+ ehciInstance->ehciIpBase->USBCMD |= (0x02U << USBHS_USBCMD_FS_SHIFT);
+#elif (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 8)
+ ehciInstance->ehciIpBase->USBCMD |= (0x03U << USBHS_USBCMD_FS_SHIFT);
#endif
#else
#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 1024)
- ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT);
-#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 512)
- ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT);
-#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 256)
- ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT);
-#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 128)
- ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT);
+ ehciInstance->ehciIpBase->USBCMD |= (0x00U << USBHS_USBCMD_FS_SHIFT);
+#elif (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 512)
+ ehciInstance->ehciIpBase->USBCMD |= (0x01U << USBHS_USBCMD_FS_SHIFT);
+#elif (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 256)
+ ehciInstance->ehciIpBase->USBCMD |= (0x02U << USBHS_USBCMD_FS_SHIFT);
+#elif (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 128)
+ ehciInstance->ehciIpBase->USBCMD |= (0x03U << USBHS_USBCMD_FS_SHIFT);
#endif
#endif
}
/* start the controller */
- ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RS_MASK;
+ ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_RS_MASK;
/* set timer0 */
- ehciInstance->ehciIpBase->GPTIMER0LD = (300 * 1000 - 1); /* 100ms */
+ ehciInstance->ehciIpBase->GPTIMER0LD = (100U * 1000U - 1U); /* 100ms */
/* enable interrupt (USB interrupt enable + USB error interrupt enable + port change detect enable + system error
* enable + interrupt on async advance enable) + general purpos Timer 0 Interrupt enable */
- ehciInstance->ehciIpBase->USBINTR |= (0x1000037);
+ ehciInstance->ehciIpBase->USBINTR |= (0x1000037U);
return kStatus_USB_Success;
}
@@ -3349,7 +3401,7 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc
#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \
((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)))
usb_host_ehci_iso_t *isoPointer;
- uint32_t speed;
+ uint32_t speed = 0U;
#endif
uint8_t cancelPipe = 0;
@@ -3368,24 +3420,24 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc
if ((qhPointer->ehciTransferHead == transfer) &&
(qhPointer->ehciTransferHead == qhPointer->ehciTransferTail)) /* only has this one transfer */
{
- cancelPipe = 1;
+ cancelPipe = 1U;
}
else
{
- cancelPipe = 0;
+ cancelPipe = 0U;
}
}
else
{
- cancelPipe = 1;
+ cancelPipe = 1U;
}
- if (cancelPipe == 1) /* cancel all pipe */
+ if (cancelPipe == 1U) /* cancel all pipe */
{
- USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); /* release all the qtd */
+ (void)USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); /* release all the qtd */
}
else /* cancel one transfer */
{
- USB_HostEhciTransferQtdListDeinit(ehciInstance, ehciPipePointer, transfer);
+ (void)USB_HostEhciTransferQtdListDeinit(ehciInstance, ehciPipePointer, transfer);
}
break;
@@ -3398,54 +3450,55 @@ static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstanc
return kStatus_USB_Success;
}
/* cancel all pipe, don't implement canceling transfer for iso */
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &speed);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
if (speed == USB_SPEED_HIGH)
{
#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD))
- USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd */
+ (void)USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd */
#endif
}
else
{
#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))
- USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd */
+ (void)USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd */
#endif
}
break;
#endif
default:
+ /*no action*/
break;
}
return kStatus_USB_Success;
}
-static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl)
+usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl)
{
usb_status_t status = kStatus_USB_Success;
uint32_t portScRegister;
-
- switch (busControl)
+ usb_host_bus_control_t controlCode = (usb_host_bus_control_t)busControl;
+ switch (controlCode)
{
case kUSB_HostBusReset:
/* reset port */
portScRegister = ehciInstance->ehciIpBase->PORTSC1;
portScRegister &= (~EHCI_PORTSC1_W1_BITS);
ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK);
- while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)
+ while (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK))
{
}
break;
case kUSB_HostBusRestart:
- ehciInstance->deviceAttached = kEHCIDeviceDetached;
+ ehciInstance->deviceAttached = (uint8_t)kEHCIDeviceDetached;
ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */
break;
case kUSB_HostBusEnableAttach: /* enable device attach */
- if (ehciInstance->deviceAttached == kEHCIDeviceDetached)
+ if (ehciInstance->deviceAttached == (uint8_t)kEHCIDeviceDetached)
{
ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */
}
@@ -3456,7 +3509,7 @@ static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstanc
break;
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
case kUSB_HostBusSuspend:
- if (ehciInstance->ehciIpBase->PORTSC1 && USBHS_PORTSC1_CCS_MASK)
+ if (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
{
/* set timer1 */
ehciInstance->ehciIpBase->GPTIMER1LD = (1 * 1000); /* 1ms */
@@ -3465,9 +3518,9 @@ static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstanc
USB_HostEhciStopAsync(ehciInstance);
USB_HostEhciStopPeriodic(ehciInstance);
- while (ehciInstance->ehciIpBase->USBSTS & (USBHS_USBSTS_PS_MASK | USBHS_USBSTS_AS_MASK))
+ while (0U != (ehciInstance->ehciIpBase->USBSTS & (USBHS_USBSTS_PS_MASK | USBHS_USBSTS_AS_MASK)))
{
- __ASM("nop");
+ __NOP();
}
ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKCN_MASK;
ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_WKDS_MASK;
@@ -3485,7 +3538,7 @@ static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstanc
case kUSB_HostBusResume:
ehciInstance->ehciIpBase->PORTSC1 &= ~(USBHS_PORTSC1_SUSP_MASK); /* Clear Suspend bit */
ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK;
- if (ehciInstance->deviceAttached != kEHCIDeviceDetached)
+ if (ehciInstance->deviceAttached != (uint8_t)kEHCIDeviceDetached)
{
ehciInstance->busSuspendStatus = kBus_EhciStartResume;
#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))
@@ -3532,6 +3585,9 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
uint32_t dataLength;
uint32_t speed;
#endif
+ void *temp;
+ uint32_t transferResults;
+ uint32_t transferOverlayResults;
ehciPipePointer = ehciInstance->ehciRunningPipeList; /* check all the running pipes */
while (ehciPipePointer != NULL)
@@ -3542,43 +3598,45 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
case USB_ENDPOINT_INTERRUPT:
case USB_ENDPOINT_CONTROL:
vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */
- transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */
+ transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */
while (transfer != NULL)
{
nextTransfer = transfer->next;
/* normal case */
- vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail;
- if ((vltQtdPointer->transferResults[0] & (EHCI_HOST_QTD_IOC_MASK)) &&
- (!(vltQtdPointer->transferResults[0] &
- EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) /* transfer is done */
+ vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail;
+ transferResults = vltQtdPointer->transferResults[0];
+ transferOverlayResults = vltQhPointer->transferOverlayResults[0];
+ if ((0U != (transferResults & (EHCI_HOST_QTD_IOC_MASK))) &&
+ (0U == (transferResults & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) /* transfer is done */
{
- qtdStatus = (vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_STATUS_ERROR_MASK);
+ qtdStatus = (transferResults & EHCI_HOST_QTD_STATUS_ERROR_MASK);
transfer->transferSofar =
USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead),
(usb_host_ehci_qtd_t *)(transfer->union2.unitTail));
transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ?
- 0 :
+ 0U :
(transfer->transferLength - transfer->transferSofar);
vltQhPointer->ehciTransferHead = transfer->next;
- vltQhPointer->timeOutLabel = 0;
- vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
- if (qtdStatus) /* has errors */
+ vltQhPointer->timeOutLabel = 0U;
+ vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
+ if (0U != qtdStatus) /* has errors */
{
- if (!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))
+ if (0U == (transferOverlayResults & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))
{
vltQhPointer->transferOverlayResults[0] &=
(~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */
}
- if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK)
+ if (0U != (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK))
{
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer,
kStatus_USB_TransferFailed); /* transfer fail */
}
else
{
- transfer->callbackFn(transfer->callbackParam, transfer,
- kStatus_USB_TransferStall); /* transfer stall */
+ /* callback function is different from the current condition */
+ transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferStall);
}
}
else
@@ -3602,8 +3660,8 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
{
break;
}
- ehciClearPipePointer =
- (usb_host_ehci_pipe_t *)ehciClearPipePointer->pipeCommon.next;
+ temp = (void *)ehciClearPipePointer->pipeCommon.next;
+ ehciClearPipePointer = (usb_host_ehci_pipe_t *)temp;
}
if ((ehciClearPipePointer != NULL) &&
@@ -3614,18 +3672,19 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
->transferOverlayResults[0] &= (~EHCI_HOST_QTD_DT_MASK);
}
}
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer,
kStatus_USB_Success); /* transfer success */
}
}
- else if ((!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) &&
- (vltQhPointer->transferOverlayResults[0] &
- EHCI_HOST_QH_STATUS_ERROR_MASK)) /* there is error and transfer is done */
+ else if ((0U == (transferOverlayResults & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) &&
+ (0U != (transferOverlayResults &
+ EHCI_HOST_QH_STATUS_ERROR_MASK))) /* there is error and transfer is done */
{
- qtdStatus = (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QH_STATUS_ERROR_MASK);
+ qtdStatus = (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QH_STATUS_ERROR_MASK);
vltQtdPointer = (volatile usb_host_ehci_qtd_t *)(vltQhPointer->currentQtdPointer);
- if (((uint32_t)vltQtdPointer & EHCI_HOST_T_INVALID_VALUE) ||
+ if ((0U != ((uint32_t)vltQtdPointer & EHCI_HOST_T_INVALID_VALUE)) ||
(vltQtdPointer == NULL)) /* the error status is unreasonable */
{
vltQhPointer->transferOverlayResults[0] &=
@@ -3634,13 +3693,13 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
else
{
/* remove qtd from qh */
- while ((vltQtdPointer != NULL) && (!(vltQtdPointer->transferResults[0] &
- EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */
+ while ((vltQtdPointer != NULL) &&
+ (0U == (transferResults & EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */
{
vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer;
}
- vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
+ vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE;
vltQhPointer->transferOverlayResults[0] &=
(~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */
@@ -3653,18 +3712,20 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead),
(usb_host_ehci_qtd_t *)(transfer->union2.unitTail));
transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ?
- 0 :
+ 0U :
(transfer->transferLength - transfer->transferSofar);
vltQhPointer->ehciTransferHead = transfer->next;
- vltQhPointer->timeOutLabel = 0;
- vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
- if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK)
+ vltQhPointer->timeOutLabel = 0U;
+ vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
+ if (0U != (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK))
{
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer,
kStatus_USB_TransferFailed); /* transfer fail */
}
else
{
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer,
kStatus_USB_TransferStall); /* transfer stall */
}
@@ -3680,41 +3741,42 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \
((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)))
case USB_ENDPOINT_ISOCHRONOUS:
- qtdStatus = 0; /* qtdStatus means break here, because there is only one break in while for misra */
+ qtdStatus = 0; /* qtdStatus means break here, because there is only one break in while for misra */
isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; /* pipe's usb_host_ehci_iso_t */
- transfer = isoPointer->ehciTransferHead; /* usb_host_ehci_iso_t's transfer */
+ transfer = isoPointer->ehciTransferHead; /* usb_host_ehci_iso_t's transfer */
while (transfer != NULL)
{
nextTransfer = transfer->next;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
- kUSB_HostGetDeviceSpeed, &speed);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
if (speed == USB_SPEED_HIGH)
{
#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD))
vltItdPointer =
(volatile usb_host_ehci_itd_t *)(transfer->union2.unitTail); /* transfer's last itd */
- for (index = 0; index < 8; ++index)
+ for (index = 0; index < 8U; ++index)
{
- if (vltItdPointer->transactions[index] & EHCI_HOST_ITD_STATUS_ACTIVE_MASK)
+ if (0U != (vltItdPointer->transactions[index] & EHCI_HOST_ITD_STATUS_ACTIVE_MASK))
{
break;
}
}
- if (index == 8) /* transfer is done */
+ if (index == 8U) /* transfer is done */
{
/* remove itd from frame list and release itd */
- dataLength = USB_HostEhciItdArrayRelease(ehciInstance,
+ dataLength = USB_HostEhciItdArrayRelease(ehciInstance,
(usb_host_ehci_itd_t *)transfer->union1.unitHead,
(usb_host_ehci_itd_t *)transfer->union2.unitTail);
- transfer->transferSofar = dataLength;
+ transfer->transferSofar = dataLength;
isoPointer->ehciTransferHead = transfer->next;
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer,
kStatus_USB_Success); /* transfer callback success */
/* TODO: iso callback error */
}
else
{
- qtdStatus = 1; /* break */
+ qtdStatus = 1U; /* break */
}
#endif
}
@@ -3723,26 +3785,27 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))
vltSitdPointer =
(volatile usb_host_ehci_sitd_t *)(transfer->union2.unitTail); /* transfer's last sitd */
- if (!(vltSitdPointer->transferResults[0] &
- EHCI_HOST_SITD_STATUS_ACTIVE_MASK)) /* transfer is done */
+ if (0U == (vltSitdPointer->transferResults[0] &
+ EHCI_HOST_SITD_STATUS_ACTIVE_MASK)) /* transfer is done */
{
/* remove sitd from frame list and release itd */
dataLength = USB_HostEhciSitdArrayRelease(
ehciInstance, (usb_host_ehci_sitd_t *)transfer->union1.unitHead,
(usb_host_ehci_sitd_t *)transfer->union2.unitTail);
- transfer->transferSofar = dataLength;
+ transfer->transferSofar = transfer->transferLength - dataLength;
isoPointer->ehciTransferHead = transfer->next;
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer,
kStatus_USB_Success); /* transfer callback success */
/* TODO: iso callback error */
}
else
{
- qtdStatus = 1; /* break */
+ qtdStatus = 1U; /* break */
}
#endif
}
- if (qtdStatus == 1)
+ if (qtdStatus == 1U)
{
break;
}
@@ -3752,38 +3815,40 @@ void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance)
#endif
default:
+ /*no action*/
break;
}
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
}
}
-static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance)
+void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance)
{
/* note: only has one port */
uint32_t portScRegister = ehciInstance->ehciIpBase->PORTSC1;
- int32_t sofStart = 0;
- int32_t sofCount = 0;
+ uint32_t sofStart = 0;
+ uint32_t sofCount = 0;
uint32_t index;
- if (portScRegister & USBHS_PORTSC1_CSC_MASK) /* connection status change */
+ if (0U != (portScRegister & USBHS_PORTSC1_CSC_MASK)) /* connection status change */
{
- sofStart = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
+ sofStart = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
/* process CSC bit */
- while (1)
+ while (1U == 1U)
{
portScRegister = ehciInstance->ehciIpBase->PORTSC1;
- if (portScRegister & USBHS_PORTSC1_CSC_MASK)
+ if (0U != (portScRegister & USBHS_PORTSC1_CSC_MASK))
{
/* clear csc bit */
portScRegister = ehciInstance->ehciIpBase->PORTSC1;
portScRegister &= (~EHCI_PORTSC1_W1_BITS);
ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_CSC_MASK);
}
- sofCount = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
- if (((sofCount - sofStart + EHCI_MAX_UFRAME_VALUE + 1) & EHCI_MAX_UFRAME_VALUE) >
- (1 * 8)) /* delay 1ms to clear CSC */
+ sofCount = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE);
+ if (((sofCount + EHCI_MAX_UFRAME_VALUE + 1U - sofStart) & EHCI_MAX_UFRAME_VALUE) >
+ (1U * 8U)) /* delay 1ms to clear CSC */
{
break;
}
@@ -3792,10 +3857,10 @@ static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance)
/* process CCS bit */
portScRegister = ehciInstance->ehciIpBase->PORTSC1;
- if (portScRegister & USBHS_PORTSC1_CCS_MASK) /* process attach */
+ if (0U != (portScRegister & USBHS_PORTSC1_CCS_MASK)) /* process attach */
{
- if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) ||
- (ehciInstance->deviceAttached == kEHCIDeviceAttached))
+ if ((ehciInstance->deviceAttached == (uint8_t)kEHCIDevicePhyAttached) ||
+ (ehciInstance->deviceAttached == (uint8_t)kEHCIDeviceAttached))
{
return;
}
@@ -3806,25 +3871,25 @@ static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance)
for (index = 0; index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY; ++index)
{
USB_HostEhciDelay(ehciInstance->ehciIpBase, 1);
- if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
+ if (0U == (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
{
break;
}
}
if (index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY) /* CCS is cleared */
{
- ehciInstance->deviceAttached = kEHCIDeviceDetached;
+ ehciInstance->deviceAttached = (uint8_t)kEHCIDeviceDetached;
return;
}
/* reset port */
portScRegister = ehciInstance->ehciIpBase->PORTSC1;
portScRegister &= (~EHCI_PORTSC1_W1_BITS);
ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK);
- while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)
+ while (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK))
{
}
ehciInstance->firstDeviceSpeed =
- ((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT);
+ (uint8_t)((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT);
/* enable ehci phy disconnection */
if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH)
{
@@ -3834,16 +3899,16 @@ static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance)
/* wait for reset */
USB_HostEhciDelay(ehciInstance->ehciIpBase, USB_HOST_EHCI_PORT_RESET_DELAY);
/* process attach */
- USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_ATTACH);
+ (void)OSA_EventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_ATTACH);
/* gpt timer start */
ehciInstance->ehciIpBase->GPTIMER0CTL |=
(USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK);
- ehciInstance->deviceAttached = kEHCIDevicePhyAttached;
+ ehciInstance->deviceAttached = (uint8_t)kEHCIDevicePhyAttached;
}
else
{
- if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) ||
- (ehciInstance->deviceAttached == kEHCIDeviceAttached))
+ if ((ehciInstance->deviceAttached == (uint8_t)kEHCIDevicePhyAttached) ||
+ (ehciInstance->deviceAttached == (uint8_t)kEHCIDeviceAttached))
{
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
ehciInstance->busSuspendStatus = kBus_EhciIdle;
@@ -3854,19 +3919,20 @@ static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance)
/* disable async and periodic */
USB_HostEhciStopAsync(ehciInstance);
USB_HostEhciStopPeriodic(ehciInstance);
- USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_DETACH);
+ (void)OSA_EventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_DETACH);
}
}
}
-static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
+void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
{
volatile usb_host_ehci_qh_t *vltQhPointer;
- volatile usb_host_ehci_qtd_t *vltQtdPointer;
+ usb_host_ehci_qtd_t *vltQtdPointer;
usb_host_transfer_t *transfer;
uint32_t backValue;
- volatile uint32_t *totalBytesAddress = NULL;
+ volatile uint32_t *totalBytesAddress = NULL;
usb_host_ehci_pipe_t *ehciPipePointer = ehciInstance->ehciRunningPipeList;
+ void *temp;
uint8_t timeoutLabel;
while (ehciPipePointer != NULL)
@@ -3876,13 +3942,13 @@ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
case USB_ENDPOINT_BULK:
case USB_ENDPOINT_CONTROL:
vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */
- transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */
+ transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */
if ((transfer != NULL)) /* there is transfering data */
{
- timeoutLabel = 0;
- if (ehciInstance->deviceAttached != kEHCIDeviceAttached)
+ timeoutLabel = 0U;
+ if (ehciInstance->deviceAttached != (uint8_t)kEHCIDeviceAttached)
{
- vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail;
+ vltQtdPointer = (usb_host_ehci_qtd_t *)transfer->union2.unitTail;
vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */
vltQhPointer->transferOverlayResults[0] &=
@@ -3891,15 +3957,15 @@ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
}
else
{
- if (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)
+ if (0U != (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))
{
- vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQhPointer->currentQtdPointer;
+ vltQtdPointer = (usb_host_ehci_qtd_t *)vltQhPointer->currentQtdPointer;
totalBytesAddress = &(vltQhPointer->transferOverlayResults[0]);
}
else
{
- vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail;
- totalBytesAddress = ((uint32_t *)vltQtdPointer + 2);
+ vltQtdPointer = (usb_host_ehci_qtd_t *)transfer->union2.unitTail;
+ totalBytesAddress = &(vltQtdPointer->transferResults[0]);
}
backValue =
@@ -3908,7 +3974,7 @@ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
if (vltQhPointer->timeOutLabel != backValue) /* use total bytes to reflect the time out */
{
vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
- vltQhPointer->timeOutLabel = backValue;
+ vltQhPointer->timeOutLabel = (uint16_t)backValue;
}
else
{
@@ -3916,7 +3982,7 @@ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
* USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE
*/
(vltQhPointer->timeOutValue)--;
- if (vltQhPointer->timeOutValue == 0)
+ if (vltQhPointer->timeOutValue == 0U)
{
/* stop the qh schedule */
USB_HostEhciStopAsync(ehciInstance);
@@ -3931,22 +3997,24 @@ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
vltQhPointer->transferOverlayResults[0] &=
(~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */
USB_HostEhciStartAsync(ehciInstance);
- timeoutLabel = 1;
+ timeoutLabel = 1U;
}
}
}
}
- if (timeoutLabel == 1)
+ if (timeoutLabel == 1U)
{
/* remove qtd from qh */
+ temp = (void *)vltQhPointer->ehciTransferTail;
while ((vltQtdPointer != NULL) &&
- (!(vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_IOC_MASK)) &&
- (vltQtdPointer != (usb_host_ehci_qtd_t *)vltQhPointer->ehciTransferTail))
+ (0U == (vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_IOC_MASK)) &&
+ (vltQtdPointer != (usb_host_ehci_qtd_t *)temp))
{
- vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer;
+ vltQtdPointer = (usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer;
}
- if ((vltQtdPointer != NULL) && (!(vltQtdPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)))
+ if ((vltQtdPointer != NULL) &&
+ (0U == (vltQtdPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)))
{
vltQhPointer->nextQtdPointer =
vltQtdPointer->nextQtdPointer; /* start qh if there are other qtd that don't belong to
@@ -3956,38 +4024,41 @@ static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance)
USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead),
(usb_host_ehci_qtd_t *)(transfer->union2.unitTail));
transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ?
- 0 :
+ 0U :
(transfer->transferLength - transfer->transferSofar);
vltQhPointer->ehciTransferHead = transfer->next;
- vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
+ vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE;
+ /* callback function is different from the current condition */
transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferFailed);
}
}
break;
default:
+ /*no action*/
break;
}
- ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = (usb_host_ehci_pipe_t *)temp;
}
}
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance)
{
- if (ehciInstance->deviceAttached != kEHCIDeviceDetached)
+ if (ehciInstance->deviceAttached != (uint8_t)kEHCIDeviceDetached)
{
if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus)
{
usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle;
- if (0 == ehciInstance->matchTick)
+ if (0U == ehciInstance->matchTick)
{
ehciInstance->matchTick = hostPointer->hwTick;
}
else
{
- if ((hostPointer->hwTick - ehciInstance->matchTick) >= 5)
+ if ((hostPointer->hwTick - ehciInstance->matchTick) >= 5U)
{
ehciInstance->ehciIpBase->USBCMD &= ~USBHS_USBCMD_RS_MASK;
ehciInstance->ehciIpBase->USBSTS |= USBHS_USBSTS_SRI_MASK;
@@ -4004,9 +4075,9 @@ static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance)
ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU;
- while (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK))
+ while (0U != (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)))
{
- __ASM("nop");
+ __NOP();
}
#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))
@@ -4018,8 +4089,8 @@ static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance)
ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK;
#endif
ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK;
- hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
- kUSB_HostEventSuspended); /* call host callback function */
+ (void)hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
+ kUSB_HostEventSuspended); /* call host callback function */
ehciInstance->busSuspendStatus = kBus_EhciSuspended;
}
}
@@ -4027,17 +4098,17 @@ static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance)
else if (kBus_EhciStartResume == ehciInstance->busSuspendStatus)
{
usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle;
- if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK))
+ if (0U == (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK))
{
ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKDS_MASK;
- if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)
+ if (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
{
USB_HostEhciStartAsync(ehciInstance);
USB_HostEhciStartPeriodic(ehciInstance);
}
- hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
- kUSB_HostEventResumed); /* call host callback function */
- hostPointer->suspendedDevice = NULL;
+ (void)hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
+ kUSB_HostEventResumed); /* call host callback function */
+ hostPointer->suspendedDevice = NULL;
ehciInstance->busSuspendStatus = kBus_EhciIdle;
ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK);
}
@@ -4059,30 +4130,31 @@ usb_status_t USB_HostEhciCreate(uint8_t controllerId,
usb_host_controller_handle *controllerHandle)
{
uint32_t index = 0;
- usb_osa_status_t osaStatus;
+ osa_status_t osaStatus;
usb_host_ehci_instance_t *ehciInstance;
uint32_t usbhsBaseAddrs[] = USBHS_BASE_ADDRS;
- usb_host_ehci_data_t *usbHostEhciData[] = USB_HOST_EHCI_DATA_ARRAY;
- uint8_t *usbHostEhciFrameList[] = USB_HOST_EHCI_FRAME_LIST_ARRAY;
+ usb_host_ehci_data_t *usbHostEhciData[USB_HOST_CONFIG_EHCI];
uint32_t *framePointer;
+ void *temp;
+ uint8_t instanceIndex = 0U;
- if ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(usbhsBaseAddrs) / sizeof(usbhsBaseAddrs[0])))
+ if ((controllerId - (uint8_t)kUSB_ControllerEhci0) >= (sizeof(usbhsBaseAddrs) / sizeof(usbhsBaseAddrs[0])))
{
return kStatus_USB_ControllerNotFound;
}
*controllerHandle = NULL;
- ehciInstance = (usb_host_ehci_instance_t *)USB_OsaMemoryAllocate(
+ ehciInstance = (usb_host_ehci_instance_t *)OSA_MemoryAllocate(
sizeof(usb_host_ehci_instance_t)); /* malloc host ehci instance */
if (ehciInstance == NULL)
{
return kStatus_USB_AllocFail;
}
- ehciInstance->controllerId = controllerId;
- ehciInstance->hostHandle = upperLayerHandle;
- ehciInstance->deviceAttached = kEHCIDeviceDetached;
- ehciInstance->ehciIpBase = (USBHS_Type *)
- usbhsBaseAddrs[controllerId - kUSB_ControllerEhci0]; /* operate ehci ip through the base address */
+ ehciInstance->controllerId = controllerId;
+ ehciInstance->hostHandle = upperLayerHandle;
+ ehciInstance->deviceAttached = (uint8_t)kEHCIDeviceDetached;
+ ehciInstance->ehciIpBase = (USBHS_Type *)
+ usbhsBaseAddrs[controllerId - (uint8_t)kUSB_ControllerEhci0]; /* operate ehci ip through the base address */
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
ehciInstance->busSuspendStatus = kBus_EhciIdle;
@@ -4097,95 +4169,150 @@ usb_status_t USB_HostEhciCreate(uint8_t controllerId,
#endif
- if (USB_HostEhciResetIP(ehciInstance) != kStatus_USB_Success) /* reset ehci ip */
+ if ((USB_HostEhciResetIP(ehciInstance) != kStatus_USB_Success) ||
+ ((ehciInstance->controllerId < (uint8_t)kUSB_ControllerEhci0))) /* reset ehci ip */
{
- USB_OsaMemoryFree(ehciInstance);
+ OSA_MemoryFree(ehciInstance);
return kStatus_USB_Error;
}
- /* initialize ehci frame list */
- ehciInstance->ehciFrameList = usbHostEhciFrameList[ehciInstance->controllerId - kUSB_ControllerEhci0];
+#if (USB_HOST_CONFIG_EHCI == 1U)
+ if (0U == usbHostEhciFramListStatus[0])
+ {
+ usbHostEhciFramListStatus[0] = 1U;
+ instanceIndex = 0U;
+ ehciInstance->ehciFrameList = &s_UsbHostEhciFrameList1[0];
+ }
+#elif (USB_HOST_CONFIG_EHCI == 2U)
+ if (0U == usbHostEhciFramListStatus[0])
+ {
+ usbHostEhciFramListStatus[0] = 1U;
+ instanceIndex = 0U;
+ ehciInstance->ehciFrameList = &s_UsbHostEhciFrameList1[0];
+ }
+ else if (0U == usbHostEhciFramListStatus[1])
+ {
+ usbHostEhciFramListStatus[1] = 1U;
+ instanceIndex = 1U;
+ ehciInstance->ehciFrameList = &s_UsbHostEhciFrameList2[0];
+ }
+ else
+ {
+ /*no action*/
+ }
+#endif
+ if (ehciInstance->ehciFrameList == NULL)
+ {
+ OSA_MemoryFree(ehciInstance);
+ return kStatus_USB_Error;
+ }
- /* initialize ehci units */
- ehciInstance->ehciUnitBase = (uint32_t *)(usbHostEhciData[ehciInstance->controllerId - kUSB_ControllerEhci0]);
+#if (USB_HOST_CONFIG_EHCI == 1U)
+ usbHostEhciData[0] = &s_UsbHostEhciData1;
+#elif (USB_HOST_CONFIG_EHCI == 2U)
+ usbHostEhciData[0] = &s_UsbHostEhciData1;
+ usbHostEhciData[1] = &s_UsbHostEhciData2;
+#else
+#error "Please increase the instance count."
+#endif
+
+ temp = (void *)usbHostEhciData[instanceIndex];
+ ehciInstance->ehciUnitBase = (uint32_t *)(temp);
/* initialize qh/qtd/itd/sitd/iso list */
- ehciInstance->ehciQhList = (usb_host_ehci_qh_t *)((uint32_t)(ehciInstance->ehciUnitBase));
+ ehciInstance->ehciQhList = (usb_host_ehci_qh_t *)((uint32_t)(ehciInstance->ehciUnitBase));
ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)((uint32_t)ehciInstance->ehciQhList +
(sizeof(usb_host_ehci_qh_t) * USB_HOST_CONFIG_EHCI_MAX_QH));
ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)((uint32_t)ehciInstance->ehciQtdHead +
(sizeof(usb_host_ehci_qtd_t) * USB_HOST_CONFIG_EHCI_MAX_QTD));
- ehciInstance->ehciSitdList = ehciInstance->ehciSitdIndexBase =
+#if ((defined(USB_HOST_CONFIG_EHCI_MAX_ITD)) && (USB_HOST_CONFIG_EHCI_MAX_ITD > 0U))
+ /* If one ITD's first 32 bytes and next 32 bytes are in different 4K region,
+ * the ITD need move 32 bytes because the ITD cannot cross over 4K boundary.
+ */
+ index = ((((((uint32_t)(ehciInstance->ehciItdList)) + 4095U) & 0xFFFFF000U) -
+ ((uint32_t)(ehciInstance->ehciItdList))) >>
+ 5U);
+ if (((index / 3U) < USB_HOST_CONFIG_EHCI_MAX_ITD) && ((index % 3U) == 1U))
+ {
+ ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)(((uint32_t)(ehciInstance->ehciItdList)) + 32U);
+ }
+#endif
+ ehciInstance->ehciSitdIndexBase =
(usb_host_ehci_sitd_t *)((uint32_t)ehciInstance->ehciItdList +
(sizeof(usb_host_ehci_itd_t) * USB_HOST_CONFIG_EHCI_MAX_ITD));
- ehciInstance->ehciIsoList = (usb_host_ehci_iso_t *)((uint32_t)ehciInstance->ehciSitdList +
+ ehciInstance->ehciSitdList = ehciInstance->ehciSitdIndexBase;
+ ehciInstance->ehciIsoList = (usb_host_ehci_iso_t *)((uint32_t)ehciInstance->ehciSitdList +
(sizeof(usb_host_ehci_sitd_t) * USB_HOST_CONFIG_EHCI_MAX_SITD));
ehciInstance->ehciPipeIndexBase =
(usb_host_ehci_pipe_t *)((uint32_t)ehciInstance->ehciIsoList +
(sizeof(usb_host_ehci_iso_t) * USB_HOST_EHCI_ISO_NUMBER));
- for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QH; ++index)
+ for (index = 1U; index < USB_HOST_CONFIG_EHCI_MAX_QH; ++index)
{
- ehciInstance->ehciQhList[index - 1].horizontalLinkPointer = (uint32_t)(&ehciInstance->ehciQhList[index]);
+ ehciInstance->ehciQhList[index - 1U].horizontalLinkPointer = (uint32_t)(&ehciInstance->ehciQhList[index]);
}
- ehciInstance->ehciQhList[USB_HOST_CONFIG_EHCI_MAX_QH - 1].horizontalLinkPointer = (uint32_t)NULL;
+ ehciInstance->ehciQhList[USB_HOST_CONFIG_EHCI_MAX_QH - 1U].horizontalLinkPointer = 0U;
for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QTD; ++index)
{
- ehciInstance->ehciQtdHead[index - 1].nextQtdPointer = (uint32_t)(&ehciInstance->ehciQtdHead[index]);
+ ehciInstance->ehciQtdHead[index - 1U].nextQtdPointer = (uint32_t)(&ehciInstance->ehciQtdHead[index]);
}
- ehciInstance->ehciQtdNumber = USB_HOST_CONFIG_EHCI_MAX_QTD;
- ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1].nextQtdPointer = (uint32_t)NULL;
- ehciInstance->ehciQtdTail = &ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1];
+ ehciInstance->ehciQtdNumber = USB_HOST_CONFIG_EHCI_MAX_QTD;
+ ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1U].nextQtdPointer = 0U;
+ ehciInstance->ehciQtdTail = &ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1U];
#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD))
for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_ITD; ++index)
{
- ehciInstance->ehciItdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciItdList[index]);
+ ehciInstance->ehciItdList[index - 1U].nextItdPointer =
+ (usb_host_ehci_itd_t *)(&ehciInstance->ehciItdList[index]);
}
- ehciInstance->ehciItdNumber = USB_HOST_CONFIG_EHCI_MAX_ITD;
- ehciInstance->ehciItdList[USB_HOST_CONFIG_EHCI_MAX_ITD - 1].nextLinkPointer = (uint32_t)NULL;
+ ehciInstance->ehciItdNumber = USB_HOST_CONFIG_EHCI_MAX_ITD;
+ ehciInstance->ehciItdList[USB_HOST_CONFIG_EHCI_MAX_ITD - 1U].nextItdPointer = NULL;
#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */
#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))
for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_SITD; ++index)
{
- ehciInstance->ehciSitdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciSitdList[index]);
+ ehciInstance->ehciSitdList[index - 1U].nextLinkPointer = (uint32_t)(&ehciInstance->ehciSitdList[index]);
}
- ehciInstance->ehciSitdNumber = USB_HOST_CONFIG_EHCI_MAX_SITD;
- ehciInstance->ehciSitdList[USB_HOST_CONFIG_EHCI_MAX_SITD - 1].nextLinkPointer = (uint32_t)NULL;
+ ehciInstance->ehciSitdNumber = USB_HOST_CONFIG_EHCI_MAX_SITD;
+ ehciInstance->ehciSitdList[USB_HOST_CONFIG_EHCI_MAX_SITD - 1U].nextLinkPointer = 0U;
#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */
#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD))
for (index = 1; index < USB_HOST_EHCI_ISO_NUMBER; ++index)
{
- ehciInstance->ehciIsoList[index - 1].next = &ehciInstance->ehciIsoList[index];
+ ehciInstance->ehciIsoList[index - 1U].next = &ehciInstance->ehciIsoList[index];
}
- ehciInstance->ehciIsoList[USB_HOST_EHCI_ISO_NUMBER - 1].next = NULL;
+ ehciInstance->ehciIsoList[USB_HOST_EHCI_ISO_NUMBER - 1U].next = NULL;
#endif
/* initialize pipes */
ehciInstance->ehciPipeList = ehciInstance->ehciPipeIndexBase;
for (index = 1; index < USB_HOST_CONFIG_MAX_PIPES; ++index)
{
- ehciInstance->ehciPipeList[index - 1].pipeCommon.next = (usb_host_pipe_t *)&ehciInstance->ehciPipeList[index];
+ temp = (void *)&ehciInstance->ehciPipeList[index];
+ ehciInstance->ehciPipeList[index - 1U].pipeCommon.next = (usb_host_pipe_t *)temp;
}
/* initialize mutext */
- osaStatus = USB_OsaMutexCreate(&ehciInstance->ehciMutex);
- if (osaStatus != kStatus_USB_OSA_Success)
+ ehciInstance->ehciMutex = (osa_mutex_handle_t)(&ehciInstance->mutexBuffer[0]);
+ osaStatus = OSA_MutexCreate(ehciInstance->ehciMutex);
+ if (osaStatus != KOSA_StatusSuccess)
{
#ifdef HOST_ECHO
usb_echo("ehci mutex init fail\r\n");
#endif
- USB_OsaMemoryFree(ehciInstance);
+ OSA_MemoryFree(ehciInstance);
return kStatus_USB_Error;
}
/* initialize task event */
- osaStatus = USB_OsaEventCreate(&ehciInstance->taskEventHandle, 1);
- if (osaStatus != kStatus_USB_OSA_Success)
+ ehciInstance->taskEventHandle = (osa_event_handle_t)&ehciInstance->taskEventHandleBuffer[0];
+ osaStatus = OSA_EventCreate(ehciInstance->taskEventHandle, 1);
+ if (osaStatus != KOSA_StatusSuccess)
{
#ifdef HOST_ECHO
usb_echo("ehci event init fail\r\n");
#endif
- USB_OsaMutexDestroy(ehciInstance->ehciMutex);
- USB_OsaMemoryFree(ehciInstance);
+ (void)OSA_MutexDestroy(ehciInstance->ehciMutex);
+ OSA_MemoryFree(ehciInstance);
return kStatus_USB_Error;
}
@@ -4193,22 +4320,23 @@ usb_status_t USB_HostEhciCreate(uint8_t controllerId,
ehciInstance->shedFirstQh = ehciInstance->ehciQhList;
ehciInstance->ehciQhList =
(usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK);
- ehciInstance->shedFirstQh->staticEndpointStates[0] |= (1 << EHCI_HOST_QH_H_SHIFT); /* first qh */
- ehciInstance->shedFirstQh->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE;
- ehciInstance->shedFirstQh->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE;
- ehciInstance->shedFirstQh->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
+ ehciInstance->shedFirstQh->staticEndpointStates[0] |= (1UL << EHCI_HOST_QH_H_SHIFT); /* first qh */
+ ehciInstance->shedFirstQh->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE;
+ ehciInstance->shedFirstQh->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE;
+ ehciInstance->shedFirstQh->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
ehciInstance->shedFirstQh->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE;
ehciInstance->shedFirstQh->horizontalLinkPointer =
(uint32_t)((uint32_t)(ehciInstance->shedFirstQh) | EHCI_HOST_POINTER_TYPE_QH);
/* initialize periodic list */
- framePointer = (uint32_t *)ehciInstance->ehciFrameList;
+ temp = (void *)ehciInstance->ehciFrameList;
+ framePointer = (uint32_t *)temp;
for (index = 0; index < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; ++index)
{
framePointer[index] = EHCI_HOST_T_INVALID_VALUE;
}
- USB_HostEhciStartIP(ehciInstance); /* start ehci ip */
+ (void)USB_HostEhciStartIP(ehciInstance); /* start ehci ip */
*controllerHandle = ehciInstance;
@@ -4223,10 +4351,29 @@ usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle)
ehciInstance->ehciIpBase->USBINTR = 0;
/* stop the controller */
ehciInstance->ehciIpBase->USBCMD = 0;
- /* free memory */
- USB_OsaMutexDestroy(ehciInstance->ehciMutex);
- USB_OsaEventDestroy(ehciInstance->taskEventHandle);
- USB_OsaMemoryFree(ehciInstance);
+/* free memory */
+#if (USB_HOST_CONFIG_EHCI == 1U)
+ if (ehciInstance->ehciFrameList == &s_UsbHostEhciFrameList1[0])
+ {
+ usbHostEhciFramListStatus[0] = 0;
+ }
+#elif (USB_HOST_CONFIG_EHCI == 2U)
+ if (ehciInstance->ehciFrameList == &s_UsbHostEhciFrameList1[0])
+ {
+ usbHostEhciFramListStatus[0] = 0;
+ }
+ else if (ehciInstance->ehciFrameList == &s_UsbHostEhciFrameList2[0])
+ {
+ usbHostEhciFramListStatus[1] = 0;
+ }
+ else
+ {
+ /*no action*/
+ }
+#endif
+ (void)OSA_MutexDestroy(ehciInstance->ehciMutex);
+ (void)OSA_EventDestroy(ehciInstance->taskEventHandle);
+ OSA_MemoryFree(ehciInstance);
return kStatus_USB_Success;
}
@@ -4237,15 +4384,17 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle,
{
usb_host_ehci_pipe_t *ehciPipePointer = NULL;
usb_status_t status;
- uint32_t speed;
+ uint32_t speed = 0;
usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle;
-
+ uint32_t val32;
+ void *temp;
/* get one pipe */
USB_HostEhciLock();
if (ehciInstance->ehciPipeList != NULL)
{
- ehciPipePointer = ehciInstance->ehciPipeList;
- ehciInstance->ehciPipeList = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next;
+ ehciPipePointer = ehciInstance->ehciPipeList;
+ temp = (void *)ehciPipePointer->pipeCommon.next;
+ ehciInstance->ehciPipeList = (usb_host_ehci_pipe_t *)temp;
}
USB_HostEhciUnlock();
if (ehciPipePointer == NULL)
@@ -4257,43 +4406,53 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle,
}
/* initialize pipe informations */
- USB_HostEhciZeroMem((uint32_t *)ehciPipePointer, sizeof(usb_host_ehci_pipe_t) / 4);
- ehciPipePointer->pipeCommon.deviceHandle = pipeInit->devInstance;
+ USB_HostEhciZeroMem((void *)ehciPipePointer, sizeof(usb_host_ehci_pipe_t) / 4U);
+ ehciPipePointer->pipeCommon.deviceHandle = pipeInit->devInstance;
ehciPipePointer->pipeCommon.endpointAddress = pipeInit->endpointAddress;
- ehciPipePointer->pipeCommon.direction = pipeInit->direction;
- ehciPipePointer->pipeCommon.interval = pipeInit->interval;
- ehciPipePointer->pipeCommon.maxPacketSize = pipeInit->maxPacketSize;
- ehciPipePointer->pipeCommon.pipeType = pipeInit->pipeType;
- ehciPipePointer->pipeCommon.numberPerUframe = pipeInit->numberPerUframe;
- if (ehciPipePointer->pipeCommon.numberPerUframe == 0)
+ ehciPipePointer->pipeCommon.direction = pipeInit->direction;
+ ehciPipePointer->pipeCommon.interval = pipeInit->interval;
+ ehciPipePointer->pipeCommon.maxPacketSize = pipeInit->maxPacketSize;
+ ehciPipePointer->pipeCommon.pipeType = pipeInit->pipeType;
+ ehciPipePointer->pipeCommon.numberPerUframe = pipeInit->numberPerUframe + 1U;
+ if (ehciPipePointer->pipeCommon.numberPerUframe > 3U)
{
- ehciPipePointer->pipeCommon.numberPerUframe = 1;
+ ehciPipePointer->pipeCommon.numberPerUframe = 3U;
}
- ehciPipePointer->pipeCommon.nakCount = pipeInit->nakCount;
- ehciPipePointer->pipeCommon.nextdata01 = 0;
- ehciPipePointer->ehciQh = NULL;
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed);
- if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS)
+ ehciPipePointer->pipeCommon.nakCount = pipeInit->nakCount;
+ ehciPipePointer->pipeCommon.nextdata01 = 0U;
+ ehciPipePointer->ehciQh = NULL;
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
+ if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) ||
+ (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT))
{
- ehciPipePointer->pipeCommon.interval =
- (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* iso interval is the power of 2 */
- }
- else if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)
- {
- if (speed == USB_SPEED_HIGH)
+ if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS)
{
ehciPipePointer->pipeCommon.interval =
- (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* HS interrupt interval is the power of 2 */
+ (uint16_t)(1UL << (ehciPipePointer->pipeCommon.interval - 1U)); /* iso interval is the power of 2 */
}
else
{
- ehciPipePointer->pipeCommon.interval = USB_HostEhciGet2PowerValue(
- ehciPipePointer->pipeCommon
- .interval); /* FS/LS interrupt interval should be the power of 2, it is used for ehci bandwidth */
+ if (speed == USB_SPEED_HIGH)
+ {
+ ehciPipePointer->pipeCommon.interval = (uint16_t)(
+ 1UL << (ehciPipePointer->pipeCommon.interval - 1U)); /* HS interrupt interval is the power of 2 */
+ }
+ else
+ {
+ ehciPipePointer->pipeCommon.interval = USB_HostEhciGet2PowerValue(
+ (uint8_t)ehciPipePointer->pipeCommon.interval); /* FS/LS interrupt interval should be the power of
+ 2, it is used for ehci bandwidth */
+ }
+ }
+
+ if ((speed == USB_SPEED_HIGH) && (ehciPipePointer->pipeCommon.interval < 8U))
+ {
+ val32 = ehciInstance->ehciIpBase->USBCMD;
+ val32 &= (~USBHS_USBCMD_ITC_MASK);
+ val32 |= USBHS_USBCMD_ITC((ehciPipePointer->pipeCommon.interval));
+ ehciInstance->ehciIpBase->USBCMD = val32;
}
- }
- else
- {
}
/* save the micro-frame interval, it is convenient for the interval process */
@@ -4303,7 +4462,7 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle,
}
else
{
- ehciPipePointer->uframeInterval = 8 * ehciPipePointer->pipeCommon.interval;
+ ehciPipePointer->uframeInterval = 8U * ehciPipePointer->pipeCommon.interval;
}
/* open pipe */
@@ -4334,15 +4493,17 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle,
{
/* release pipe */
USB_HostEhciLock();
- ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList;
- ehciInstance->ehciPipeList = ehciPipePointer;
+ temp = (void *)ehciInstance->ehciPipeList;
+ ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)temp;
+ ehciInstance->ehciPipeList = ehciPipePointer;
USB_HostEhciUnlock();
return status;
}
/* add pipe to run pipe list */
USB_HostEhciLock();
- ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList;
+ temp = (void *)ehciInstance->ehciRunningPipeList;
+ ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)temp;
ehciInstance->ehciRunningPipeList = ehciPipePointer;
USB_HostEhciUnlock();
@@ -4353,43 +4514,50 @@ usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle,
usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle)
{
usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle;
- usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle;
- usb_host_pipe_t *prevPointer = NULL;
+ usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle;
+ usb_host_pipe_t *prevPointer = NULL;
+ void *temp;
+ void *tempCurrent;
switch (ehciPipePointer->pipeCommon.pipeType)
{
case USB_ENDPOINT_BULK:
case USB_ENDPOINT_CONTROL:
- USB_HostEhciCloseControlBulk(ehciInstance, ehciPipePointer);
+ (void)USB_HostEhciCloseControlBulk(ehciInstance, ehciPipePointer);
break;
case USB_ENDPOINT_INTERRUPT:
- USB_HostEhciCloseInterrupt(ehciInstance, ehciPipePointer);
+ (void)USB_HostEhciCloseInterrupt(ehciInstance, ehciPipePointer);
break;
#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \
((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)))
case USB_ENDPOINT_ISOCHRONOUS:
- USB_HostEhciCloseIso(ehciInstance, ehciPipePointer);
+ (void)USB_HostEhciCloseIso(ehciInstance, ehciPipePointer);
break;
#endif
default:
+ /*no action*/
break;
}
/* delete pipe from run pipe list */
USB_HostEhciLock();
- prevPointer = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList;
- if (prevPointer == (usb_host_pipe_t *)ehciPipePointer)
+ temp = (void *)ehciInstance->ehciRunningPipeList;
+ prevPointer = (usb_host_pipe_t *)temp;
+ tempCurrent = (void *)ehciPipePointer;
+ if (prevPointer == (usb_host_pipe_t *)tempCurrent)
{
- ehciInstance->ehciRunningPipeList = (usb_host_ehci_pipe_t *)(prevPointer->next);
+ temp = (void *)prevPointer->next;
+ ehciInstance->ehciRunningPipeList = (usb_host_ehci_pipe_t *)(temp);
}
else
{
while (prevPointer != NULL)
{
- if (prevPointer->next == (usb_host_pipe_t *)ehciPipePointer)
+ temp = (void *)ehciPipePointer;
+ if (prevPointer->next == (usb_host_pipe_t *)temp)
{
prevPointer->next = ehciPipePointer->pipeCommon.next;
break;
@@ -4404,8 +4572,9 @@ usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle,
/* release pipe */
USB_HostEhciLock();
- ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList;
- ehciInstance->ehciPipeList = ehciPipePointer;
+ temp = (void *)ehciInstance->ehciPipeList;
+ ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)temp;
+ ehciInstance->ehciPipeList = ehciPipePointer;
USB_HostEhciUnlock();
return kStatus_USB_Success;
@@ -4416,11 +4585,11 @@ usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle,
usb_host_transfer_t *transfer)
{
usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle;
- usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle;
- usb_status_t status = kStatus_USB_Success;
+ usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle;
+ usb_status_t status = kStatus_USB_Success;
#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \
((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)))
- uint32_t speed;
+ uint32_t speed = 0U;
#endif
switch (ehciPipePointer->pipeCommon.pipeType)
@@ -4435,8 +4604,8 @@ usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle,
#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \
((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)))
case USB_ENDPOINT_ISOCHRONOUS:
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed,
- &speed);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceSpeed, &speed);
if (speed == USB_SPEED_HIGH)
{
#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD))
@@ -4455,6 +4624,7 @@ usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle,
#endif
default:
+ /*no action*/
break;
}
return status;
@@ -4469,22 +4639,22 @@ usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle,
usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint32_t ioctlEvent, void *ioctlParam)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle;
usb_host_cancel_param_t *param;
usb_host_ehci_pipe_t *ehciPipePointer;
volatile usb_host_ehci_qh_t *vltQhPointer;
- uint32_t deviceAddress;
-
+ uint32_t deviceAddress = 0;
+ usb_host_controller_control_t controlCode = (usb_host_controller_control_t)ioctlEvent;
if (controllerHandle == NULL)
{
return kStatus_USB_InvalidHandle;
}
- switch (ioctlEvent)
+ switch (controlCode)
{
case kUSB_HostCancelTransfer: /* cancel pipe or one transfer */
- param = (usb_host_cancel_param_t *)ioctlParam;
+ param = (usb_host_cancel_param_t *)ioctlParam;
status = USB_HostEhciCancelPipe(ehciInstance, (usb_host_ehci_pipe_t *)param->pipeHandle, param->transfer);
break;
@@ -4498,18 +4668,19 @@ usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint
case kUSB_HostUpdateControlEndpointAddress:
ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam;
- vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
+ vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
/* update address */
- USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress,
- &deviceAddress);
+ (void)USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle,
+ (uint32_t)kUSB_HostGetDeviceAddress, &deviceAddress);
vltQhPointer->staticEndpointStates[0] |= deviceAddress;
+ USB_HostEhciDelay(ehciInstance->ehciIpBase, 2U);
break;
case kUSB_HostUpdateControlPacketSize:
ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam;
- vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
+ vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh;
USB_HostEhciLock();
- if (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)
+ if (0U != (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK))
{
USB_HostEhciStopAsync(ehciInstance);
/* update max packet size */
@@ -4527,8 +4698,13 @@ usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint
}
USB_HostEhciUnlock();
break;
-
+#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
+ case kUSB_HostTestModeInit: /* test mode control */
+ USB_HostEhciTestModeInit((usb_host_device_instance_t *)ioctlParam);
+ break;
+#endif
default:
+ status = kStatus_USB_NotSupported;
break;
}
return status;
@@ -4546,44 +4722,44 @@ void USB_HostEhciTaskFunction(void *hostHandle)
}
ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle;
- if (USB_OsaEventWait(ehciInstance->taskEventHandle, 0xFF, 0, 0, &bitSet) ==
- kStatus_USB_OSA_Success) /* wait all event */
+ if (OSA_EventWait(ehciInstance->taskEventHandle, 0xFF, 0, USB_OSA_WAIT_TIMEOUT, &bitSet) ==
+ KOSA_StatusSuccess) /* wait all event */
{
- if (bitSet & EHCI_TASK_EVENT_PORT_CHANGE) /* port change */
+ if (0U != (bitSet & EHCI_TASK_EVENT_PORT_CHANGE)) /* port change */
{
USB_HostEhciPortChange(ehciInstance);
}
- if (bitSet & EHCI_TASK_EVENT_TIMER0) /* timer0 */
+ if (0U != (bitSet & EHCI_TASK_EVENT_TIMER0)) /* timer0 */
{
USB_HostEhciTimer0(ehciInstance);
}
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
- if (bitSet & EHCI_TASK_EVENT_TIMER1) /* timer1 */
+ if (0U != (bitSet & EHCI_TASK_EVENT_TIMER1)) /* timer1 */
{
USB_HostEhciTimer1(ehciInstance);
}
#endif
- if (ehciInstance->deviceAttached == kEHCIDeviceAttached)
+ if ((ehciInstance->deviceAttached == (uint8_t)kEHCIDeviceAttached))
{
- if (bitSet & EHCI_TASK_EVENT_TRANSACTION_DONE) /* transaction done */
+ if (0U != (bitSet & EHCI_TASK_EVENT_TRANSACTION_DONE)) /* transaction done */
{
USB_HostEhciTransactionDone(ehciInstance);
}
- if (bitSet & EHCI_TASK_EVENT_DEVICE_DETACH) /* device detach */
+ if (0U != (bitSet & EHCI_TASK_EVENT_DEVICE_DETACH)) /* device detach */
{
ehciInstance->ehciIpBase->USBINTR &=
(~USBHS_USBINTR_PCE_MASK); /* disable attach, enable when the detach process is done */
- ehciInstance->deviceAttached = kEHCIDeviceDetached;
- USB_HostDetachDevice(ehciInstance->hostHandle, 0, 0);
+ ehciInstance->deviceAttached = (uint8_t)kEHCIDeviceDetached;
+ (void)USB_HostDetachDevice(ehciInstance->hostHandle, 0, 0);
}
}
- else if (ehciInstance->deviceAttached != kEHCIDeviceAttached)
+ else if (ehciInstance->deviceAttached != (uint8_t)kEHCIDeviceAttached)
{
- if (bitSet & EHCI_TASK_EVENT_DEVICE_ATTACH) /* device is attached */
+ if (0U != (bitSet & EHCI_TASK_EVENT_DEVICE_ATTACH)) /* device is attached */
{
USB_HostEhciStartAsync(ehciInstance);
USB_HostEhciStartPeriodic(ehciInstance);
@@ -4591,12 +4767,13 @@ void USB_HostEhciTaskFunction(void *hostHandle)
if (USB_HostAttachDevice(ehciInstance->hostHandle, ehciInstance->firstDeviceSpeed, 0, 0, 1,
&deviceHandle) == kStatus_USB_Success)
{
- ehciInstance->deviceAttached = kEHCIDeviceAttached;
+ ehciInstance->deviceAttached = (uint8_t)kEHCIDeviceAttached;
}
}
}
else
{
+ /*no action*/
}
}
}
@@ -4616,18 +4793,18 @@ void USB_HostEhciIsrFunction(void *hostHandle)
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))
- if (ehciInstance->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK)
+ if (0U != (ehciInstance->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK))
{
usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle;
ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK;
- hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
- kUSB_HostEventDetectResume); /* call host callback function */
-
- while (!(ehciInstance->registerNcBase->USB_OTGn_PHY_CTRL_0 & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK))
+ (void)hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
+ kUSB_HostEventDetectResume); /* call host callback function */
+#if (defined(USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK))
+ while (0U == (ehciInstance->registerNcBase->USB_OTGn_PHY_CTRL_0 & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK))
{
}
-
- if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)
+#endif
+ if (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
{
USB_HostEhciStartAsync(ehciInstance);
USB_HostEhciStartPeriodic(ehciInstance);
@@ -4640,25 +4817,27 @@ void USB_HostEhciIsrFunction(void *hostHandle)
}
else
{
+ /*no action*/
}
}
else
{
+ /*no action*/
}
#else
- if (ehciInstance->ehciIpBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK)
+ if (0U != (ehciInstance->ehciIpBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK))
{
usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle;
- hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
- kUSB_HostEventDetectResume); /* call host callback function */
+ (void)hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
+ kUSB_HostEventDetectResume); /* call host callback function */
- while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
+ while (0U == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
{
}
ehciInstance->ehciIpBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK;
ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK;
- if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)
+ if (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
{
USB_HostEhciStartAsync(ehciInstance);
USB_HostEhciStartPeriodic(ehciInstance);
@@ -4671,10 +4850,12 @@ void USB_HostEhciIsrFunction(void *hostHandle)
}
else
{
+ /*no action*/
}
}
else
{
+ /*no action*/
}
#endif /* FSL_FEATURE_SOC_USBNC_COUNT */
@@ -4682,60 +4863,61 @@ void USB_HostEhciIsrFunction(void *hostHandle)
interruptStatus = ehciInstance->ehciIpBase->USBSTS;
interruptStatus &= ehciInstance->ehciIpBase->USBINTR;
- while (interruptStatus) /* there are usb interrupts */
+ while (0U != interruptStatus) /* there are usb interrupts */
{
ehciInstance->ehciIpBase->USBSTS = interruptStatus; /* clear interrupt */
- if (interruptStatus & USBHS_USBSTS_SRI_MASK) /* SOF interrupt */
+ if (0U != (interruptStatus & USBHS_USBSTS_SRI_MASK)) /* SOF interrupt */
{
}
- if (interruptStatus & USBHS_USBSTS_SEI_MASK) /* system error interrupt */
+ if (0U != (interruptStatus & USBHS_USBSTS_SEI_MASK)) /* system error interrupt */
{
}
- if ((interruptStatus & USBHS_USBSTS_UI_MASK) ||
- (interruptStatus & USBHS_USBSTS_UEI_MASK)) /* USB interrupt or USB error interrupt */
+ if ((0U != (interruptStatus & USBHS_USBSTS_UI_MASK)) ||
+ (0U != (interruptStatus & USBHS_USBSTS_UEI_MASK))) /* USB interrupt or USB error interrupt */
{
- USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TRANSACTION_DONE);
+ (void)OSA_EventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TRANSACTION_DONE);
}
- if (interruptStatus & USBHS_USBSTS_PCI_MASK) /* port change detect interrupt */
+ if (0U != (interruptStatus & USBHS_USBSTS_PCI_MASK)) /* port change detect interrupt */
{
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle;
- if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK)
+ if (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK))
{
if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus)
{
- if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)
+ if (0U != (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK))
{
USB_HostEhciStartAsync(ehciInstance);
USB_HostEhciStartPeriodic(ehciInstance);
}
- hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
- kUSB_HostEventNotSuspended); /* call host callback function */
- hostPointer->suspendedDevice = NULL;
+ (void)hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL,
+ kUSB_HostEventNotSuspended); /* call host callback function */
+ hostPointer->suspendedDevice = NULL;
ehciInstance->busSuspendStatus = kBus_EhciIdle;
ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK);
}
else
{
+ /*no action */
}
}
#endif
- USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_PORT_CHANGE);
+ (void)OSA_EventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_PORT_CHANGE);
}
- if (interruptStatus & USBHS_USBSTS_TI0_MASK) /* timer 0 interrupt */
+ if (0U != (interruptStatus & USBHS_USBSTS_TI0_MASK)) /* timer 0 interrupt */
{
- USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER0);
+ (void)OSA_EventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER0);
}
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
- if (interruptStatus & USBHS_USBSTS_TI1_MASK) /* timer 1 interrupt */
+ if (0U != (interruptStatus & USBHS_USBSTS_TI1_MASK)) /* timer 1 interrupt */
{
- USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER1);
+ (void)OSA_EventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER1);
}
#endif
@@ -4744,4 +4926,4 @@ void USB_HostEhciIsrFunction(void *hostHandle)
}
}
-#endif /* USB_HOST_CONFIG_EHCI */
+#endif /* USB_HOST_CONFIG_EHCI */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h
index 162d6576cd..c67f8baa40 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h
@@ -1,31 +1,9 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016,2019 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _USB_HOST_CONTROLLER_EHCI_H_
@@ -39,95 +17,95 @@
* Definitions
******************************************************************************/
/* EHCI host macros */
-#define EHCI_HOST_T_INVALID_VALUE (1U)
-#define EHCI_HOST_POINTER_TYPE_ITD (0x00U)
-#define EHCI_HOST_POINTER_TYPE_QH (0x00000002U)
-#define EHCI_HOST_POINTER_TYPE_SITD (0x00000004U)
-#define EHCI_HOST_POINTER_TYPE_FSTN (0x00000006U)
-#define EHCI_HOST_POINTER_TYPE_MASK (0x00000006U)
+#define EHCI_HOST_T_INVALID_VALUE (1U)
+#define EHCI_HOST_POINTER_TYPE_ITD (0x00U)
+#define EHCI_HOST_POINTER_TYPE_QH (0x00000002U)
+#define EHCI_HOST_POINTER_TYPE_SITD (0x00000004U)
+#define EHCI_HOST_POINTER_TYPE_FSTN (0x00000006U)
+#define EHCI_HOST_POINTER_TYPE_MASK (0x00000006U)
#define EHCI_HOST_POINTER_ADDRESS_MASK (0xFFFFFFE0U)
-#define EHCI_HOST_PID_OUT (0U)
-#define EHCI_HOST_PID_IN (1U)
-#define EHCI_HOST_PID_SETUP (2U)
+#define EHCI_HOST_PID_OUT (0UL)
+#define EHCI_HOST_PID_IN (1UL)
+#define EHCI_HOST_PID_SETUP (2UL)
-#define EHCI_HOST_QH_RL_SHIFT (28U)
-#define EHCI_HOST_QH_RL_MASK (0xF0000000U)
-#define EHCI_HOST_QH_C_SHIFT (27U)
-#define EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT (16U)
-#define EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK (0x07FF0000U)
-#define EHCI_HOST_QH_H_SHIFT (15U)
-#define EHCI_HOST_QH_DTC_SHIFT (14U)
-#define EHCI_HOST_QH_EPS_SHIFT (12U)
-#define EHCI_HOST_QH_ENDPT_SHIFT (8U)
-#define EHCI_HOST_QH_I_SHIFT (7U)
-#define EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT (0U)
-#define EHCI_HOST_QH_MULT_SHIFT (30U)
-#define EHCI_HOST_QH_PORT_NUMBER_SHIFT (23U)
-#define EHCI_HOST_QH_HUB_ADDR_SHIFT (16U)
-#define EHCI_HOST_QH_UFRAME_CMASK_SHIFT (8U)
-#define EHCI_HOST_QH_UFRAME_SMASK_SHIFT (0U)
-#define EHCI_HOST_QH_STATUS_ERROR_MASK (0x0000007EU)
+#define EHCI_HOST_QH_RL_SHIFT (28U)
+#define EHCI_HOST_QH_RL_MASK (0xF0000000U)
+#define EHCI_HOST_QH_C_SHIFT (27U)
+#define EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT (16U)
+#define EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK (0x07FF0000U)
+#define EHCI_HOST_QH_H_SHIFT (15U)
+#define EHCI_HOST_QH_DTC_SHIFT (14U)
+#define EHCI_HOST_QH_EPS_SHIFT (12U)
+#define EHCI_HOST_QH_ENDPT_SHIFT (8U)
+#define EHCI_HOST_QH_I_SHIFT (7U)
+#define EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT (0U)
+#define EHCI_HOST_QH_MULT_SHIFT (30U)
+#define EHCI_HOST_QH_PORT_NUMBER_SHIFT (23U)
+#define EHCI_HOST_QH_HUB_ADDR_SHIFT (16U)
+#define EHCI_HOST_QH_UFRAME_CMASK_SHIFT (8U)
+#define EHCI_HOST_QH_UFRAME_SMASK_SHIFT (0U)
+#define EHCI_HOST_QH_STATUS_ERROR_MASK (0x0000007EU)
#define EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK (0x0000003EU)
-#define EHCI_HOST_QTD_DT_SHIFT (31U)
-#define EHCI_HOST_QTD_DT_MASK (0x80000000U)
-#define EHCI_HOST_QTD_TOTAL_BYTES_SHIFT (16U)
-#define EHCI_HOST_QTD_TOTAL_BYTES_MASK (0x7FFF0000U)
-#define EHCI_HOST_QTD_IOC_MASK (0x00008000U)
-#define EHCI_HOST_QTD_C_PAGE_SHIFT (12U)
-#define EHCI_HOST_QTD_CERR_SHIFT (10U)
-#define EHCI_HOST_QTD_CERR_MAX_VALUE (0x00000003U)
-#define EHCI_HOST_QTD_PID_CODE_SHIFT (8U)
-#define EHCI_HOST_QTD_STATUS_SHIFT (0U)
-#define EHCI_HOST_QTD_CURRENT_OFFSET_MASK (0x00000FFFU)
-#define EHCI_HOST_QTD_BUFFER_POINTER_SHIFT (12U)
-#define EHCI_HOST_QTD_STATUS_ACTIVE_MASK (0x00000080U)
-#define EHCI_HOST_QTD_STATUS_MASK (0x000000ffU)
-#define EHCI_HOST_QTD_STATUS_ERROR_MASK (0x0000007EU)
+#define EHCI_HOST_QTD_DT_SHIFT (31U)
+#define EHCI_HOST_QTD_DT_MASK (0x80000000U)
+#define EHCI_HOST_QTD_TOTAL_BYTES_SHIFT (16U)
+#define EHCI_HOST_QTD_TOTAL_BYTES_MASK (0x7FFF0000U)
+#define EHCI_HOST_QTD_IOC_MASK (0x00008000U)
+#define EHCI_HOST_QTD_C_PAGE_SHIFT (12U)
+#define EHCI_HOST_QTD_CERR_SHIFT (10U)
+#define EHCI_HOST_QTD_CERR_MAX_VALUE (0x00000003UL)
+#define EHCI_HOST_QTD_PID_CODE_SHIFT (8U)
+#define EHCI_HOST_QTD_STATUS_SHIFT (0U)
+#define EHCI_HOST_QTD_CURRENT_OFFSET_MASK (0x00000FFFU)
+#define EHCI_HOST_QTD_BUFFER_POINTER_SHIFT (12U)
+#define EHCI_HOST_QTD_STATUS_ACTIVE_MASK (0x00000080U)
+#define EHCI_HOST_QTD_STATUS_MASK (0x000000ffU)
+#define EHCI_HOST_QTD_STATUS_ERROR_MASK (0x0000007EU)
#define EHCI_HOST_QTD_STATUS_STALL_ERROR_MASK (0x00000040U)
-#define EHCI_HOST_ITD_STATUS_ACTIVE_MASK (0x80000000U)
-#define EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT (16U)
-#define EHCI_HOST_ITD_TRANSACTION_LEN_MASK (0x0FFF0000U)
-#define EHCI_HOST_ITD_IOC_SHIFT (15U)
-#define EHCI_HOST_ITD_PG_SHIFT (12U)
+#define EHCI_HOST_ITD_STATUS_ACTIVE_MASK (0x80000000U)
+#define EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT (16U)
+#define EHCI_HOST_ITD_TRANSACTION_LEN_MASK (0x0FFF0000U)
+#define EHCI_HOST_ITD_IOC_SHIFT (15U)
+#define EHCI_HOST_ITD_PG_SHIFT (12U)
#define EHCI_HOST_ITD_TRANSACTION_OFFSET_SHIFT (0U)
-#define EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK (0x00000FFFU)
-#define EHCI_HOST_ITD_BUFFER_POINTER_SHIFT (12U)
-#define EHCI_HOST_ITD_ENDPT_SHIFT (8U)
-#define EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT (0U)
-#define EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT (0U)
-#define EHCI_HOST_ITD_MULT_SHIFT (0U)
-#define EHCI_HOST_ITD_DIRECTION_SHIFT (11U)
+#define EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK (0x00000FFFU)
+#define EHCI_HOST_ITD_BUFFER_POINTER_SHIFT (12U)
+#define EHCI_HOST_ITD_ENDPT_SHIFT (8U)
+#define EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT (0U)
+#define EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT (0U)
+#define EHCI_HOST_ITD_MULT_SHIFT (0U)
+#define EHCI_HOST_ITD_DIRECTION_SHIFT (11U)
-#define EHCI_HOST_SITD_STATUS_ACTIVE_MASK (0x00000080U)
-#define EHCI_HOST_SITD_DIRECTION_SHIFT (31U)
-#define EHCI_HOST_SITD_PORT_NUMBER_SHIFT (24U)
-#define EHCI_HOST_SITD_HUB_ADDR_SHIFT (16U)
-#define EHCI_HOST_SITD_ENDPT_SHIFT (8U)
+#define EHCI_HOST_SITD_STATUS_ACTIVE_MASK (0x00000080U)
+#define EHCI_HOST_SITD_DIRECTION_SHIFT (31U)
+#define EHCI_HOST_SITD_PORT_NUMBER_SHIFT (24U)
+#define EHCI_HOST_SITD_HUB_ADDR_SHIFT (16U)
+#define EHCI_HOST_SITD_ENDPT_SHIFT (8U)
#define EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT (0U)
-#define EHCI_HOST_SITD_CMASK_SHIFT (8U)
-#define EHCI_HOST_SITD_SMASK_SHIFT (0U)
-#define EHCI_HOST_SITD_TOTAL_BYTES_SHIFT (16U)
-#define EHCI_HOST_SITD_TOTAL_BYTES_MASK (0x03FF0000U)
-#define EHCI_HOST_SITD_TP_SHIFT (3U)
-#define EHCI_HOST_SITD_TCOUNT_SHIFT (0U)
-#define EHCI_HOST_SITD_IOC_SHIFT (31U)
+#define EHCI_HOST_SITD_CMASK_SHIFT (8U)
+#define EHCI_HOST_SITD_SMASK_SHIFT (0U)
+#define EHCI_HOST_SITD_TOTAL_BYTES_SHIFT (16U)
+#define EHCI_HOST_SITD_TOTAL_BYTES_MASK (0x03FF0000U)
+#define EHCI_HOST_SITD_TP_SHIFT (3U)
+#define EHCI_HOST_SITD_TCOUNT_SHIFT (0U)
+#define EHCI_HOST_SITD_IOC_SHIFT (31U)
/* register related MACROs */
-#define EHCI_PORTSC1_W1_BITS (0x0000002AU)
+#define EHCI_PORTSC1_W1_BITS (0x0000002AU)
#define EHCI_MAX_UFRAME_VALUE (0x00003FFFU)
/* task event */
-#define EHCI_TASK_EVENT_DEVICE_ATTACH (0x01U)
+#define EHCI_TASK_EVENT_DEVICE_ATTACH (0x01U)
#define EHCI_TASK_EVENT_TRANSACTION_DONE (0x02U)
-#define EHCI_TASK_EVENT_DEVICE_DETACH (0x04U)
-#define EHCI_TASK_EVENT_PORT_CHANGE (0x08U)
-#define EHCI_TASK_EVENT_TIMER0 (0x10U)
-#define EHCI_TASK_EVENT_TIMER1 (0x20U)
+#define EHCI_TASK_EVENT_DEVICE_DETACH (0x04U)
+#define EHCI_TASK_EVENT_PORT_CHANGE (0x08U)
+#define EHCI_TASK_EVENT_TIMER0 (0x10U)
+#define EHCI_TASK_EVENT_TIMER1 (0x20U)
-#define USB_HostEhciLock() USB_OsaMutexLock(ehciInstance->ehciMutex)
-#define USB_HostEhciUnlock() USB_OsaMutexUnlock(ehciInstance->ehciMutex)
+#define USB_HostEhciLock() (void)OSA_MutexLock(ehciInstance->ehciMutex, USB_OSA_WAIT_TIMEOUT)
+#define USB_HostEhciUnlock() (void)OSA_MutexUnlock(ehciInstance->ehciMutex)
/*******************************************************************************
* KHCI driver public structures, enumerations, macros, functions
@@ -144,6 +122,8 @@
#define USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY (101U)
/*! @brief Delay for port reset */
#define USB_HOST_EHCI_PORT_RESET_DELAY (11U)
+/*! @brief The MAX continuous transfers that application can send. */
+#define USB_HOST_EHCI_ISO_MAX_CONTINUOUS_TRANSFER (8U)
/*! @brief The SITD inserts a frame interval for putting more SITD continuously.
* There is an interval when an application sends two FS/LS ISO transfers.
* When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two
@@ -171,7 +151,7 @@
*/
#define USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER (16U)
/*! @brief Control or bulk transaction timeout value (unit: 100 ms) */
-#define USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE (20U)
+#define USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE (50U)
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
typedef enum _bus_ehci_suspend_request_state
@@ -323,8 +303,10 @@ typedef struct _usb_host_ehci_instance
usb_host_ehci_pipe_t *ehciPipeIndexBase; /*!< Pipe buffer's start pointer*/
usb_host_ehci_pipe_t *ehciPipeList; /*!< Idle pipe list pointer*/
usb_host_ehci_pipe_t *ehciRunningPipeList; /*!< Running pipe list pointer*/
- usb_osa_mutex_handle ehciMutex; /*!< EHCI mutex*/
- usb_osa_event_handle taskEventHandle; /*!< EHCI task event*/
+ osa_mutex_handle_t ehciMutex; /*!< EHCI mutex*/
+ uint32_t mutexBuffer[(OSA_MUTEX_HANDLE_SIZE + 3) / 4]; /*!< The mutex buffer. */
+ osa_event_handle_t taskEventHandle; /*!< EHCI task event*/
+ uint32_t taskEventHandleBuffer[(OSA_EVENT_HANDLE_SIZE + 3) / 4]; /*!< EHCI task event handle buffer*/
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
uint64_t matchTick;
USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */
@@ -355,6 +337,10 @@ typedef struct _usb_host_ehci_data
#endif
#if ((defined(USB_HOST_CONFIG_EHCI_MAX_ITD)) && (USB_HOST_CONFIG_EHCI_MAX_ITD > 0U))
usb_host_ehci_itd_t ehciItd[USB_HOST_CONFIG_EHCI_MAX_ITD]; /*!< Idle ITD list array*/
+ /* add additional 32bytes because the itd cannot cross over 4K boundary,
+ * If one ITD cross over 4K boundary, the code will move 32 bytes for ITD.
+ */
+ uint32_t reserved[8];
#endif
#if ((defined(USB_HOST_CONFIG_EHCI_MAX_SITD)) && (USB_HOST_CONFIG_EHCI_MAX_SITD > 0U))
usb_host_ehci_sitd_t ehciSitd[USB_HOST_CONFIG_EHCI_MAX_SITD]; /*!< Idle SITD list array*/
@@ -463,7 +449,6 @@ extern usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerH
* @param[in] controllerHandle The controller handle.
* @param[in] pipeHandle The receiving pipe handle.
* @param[in] transfer The transfer information.
-
* @retval kStatus_USB_Success Send successfully.
* @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI.
* @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI.
@@ -488,6 +473,45 @@ extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandl
uint32_t ioctlEvent,
void *ioctlParam);
+/*!
+ * @brief control ehci bus.
+ *
+ * @param ehciInstance ehci instance pointer.
+ * @param bus_control control code.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+extern usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl);
+
+/*!
+ * @brief ehci port change interrupt process function.
+ *
+ * @param ehciInstance ehci instance pointer.
+ */
+extern void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance);
+
+/*!
+ * @brief ehci timer0 interrupt process function.
+ * cancel control/bulk transfer that time out.
+ *
+ * @param ehciInstance ehci instance pointer.
+ */
+extern void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance);
+
+/*!
+ * @brief host ehci start async schedule.
+ *
+ * @param ehciInstance ehci instance pointer.
+ */
+extern void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance);
+
+/*!
+ * @brief host ehci start periodic schedule.
+ *
+ * @param ehciInstance ehci instance pointer.
+ */
+extern void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance);
+
/*! @}*/
#ifdef __cplusplus
@@ -496,4 +520,4 @@ extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandl
/*! @}*/
-#endif /* _USB_HOST_CONTROLLER_EHCI_H_ */
+#endif /* _USB_HOST_CONTROLLER_EHCI_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_framework.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_framework.c
new file mode 100644
index 0000000000..d637a6f3cb
--- /dev/null
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_framework.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include
+#include "usb_host.h"
+#include "usb_host_hci.h"
+#include "usb_host_devices.h"
+#include "usb_host_framework.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "middleware.usb.host.fatfs_usb_stack"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ uint8_t *buffer,
+ uint32_t bufferLen)
+{
+ /* initialize transfer */
+ transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN((uint16_t)bufferLen);
+ transfer->transferBuffer = buffer;
+ transfer->transferLength = bufferLen;
+
+ if (USB_HostSendSetup(deviceInstance->hostHandle, deviceInstance->controlPipe, transfer) !=
+ kStatus_USB_Success) /* send setup transfer */
+ {
+#ifdef HOST_ECHO
+ usb_echo("failed for USB_HostSendSetup\r\n");
+#endif
+ (void)USB_HostFreeTransfer(deviceInstance->hostHandle, transfer);
+ return kStatus_USB_Error;
+ }
+ return kStatus_USB_Success;
+}
+
+usb_status_t USB_HostStandardGetStatus(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_get_status_param_t *statusParam;
+ uint8_t length;
+
+ /* initialize transfer */
+ statusParam = (usb_host_get_status_param_t *)param;
+ transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN | USB_REQUEST_TYPE_TYPE_STANDARD;
+ if (statusParam->requestType == (uint8_t)kRequestDevice)
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_DEVICE;
+ }
+ else if (statusParam->requestType == (uint8_t)kRequestInterface)
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_INTERFACE;
+ }
+ else
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_ENDPOINT;
+ }
+ transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(statusParam->statusSelector);
+
+ length = 2;
+ if (statusParam->statusSelector == USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR)
+ {
+ length = 1;
+ }
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, statusParam->statusBuffer, length);
+}
+
+usb_status_t USB_HostStandardSetClearFeature(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_process_feature_param_t *featureParam;
+
+ /* initialize transfer */
+ featureParam = (usb_host_process_feature_param_t *)param;
+ if (featureParam->requestType == (uint8_t)kRequestDevice)
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_DEVICE;
+ }
+ else if (featureParam->requestType == (uint8_t)kRequestInterface)
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_INTERFACE;
+ }
+ else
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_ENDPOINT;
+ }
+ transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(featureParam->featureSelector);
+ transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(featureParam->interfaceOrEndpoint);
+
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0);
+}
+
+usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ uint8_t address;
+
+ /* initialize transfer */
+ address = *(uint8_t *)param;
+ transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(address);
+
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0);
+}
+
+usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_process_descriptor_param_t *descriptorParam;
+
+ /* initialize transfer */
+ descriptorParam = (usb_host_process_descriptor_param_t *)param;
+ transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(
+ (uint16_t)((uint16_t)descriptorParam->descriptorType << 8) | descriptorParam->descriptorIndex);
+ transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(descriptorParam->languageId);
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, descriptorParam->descriptorBuffer,
+ descriptorParam->descriptorLength);
+}
+
+usb_status_t USB_HostStandardGetInterface(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_get_interface_param_t *interfaceParam;
+
+ /* initialize transfer */
+ interfaceParam = (usb_host_get_interface_param_t *)param;
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_INTERFACE;
+ transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(interfaceParam->interface);
+
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, interfaceParam->alternateInterfaceBuffer, 1);
+}
+
+usb_status_t USB_HostStandardSetInterface(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_set_interface_param_t *setParam;
+
+ /* initialize transfer */
+ setParam = (usb_host_set_interface_param_t *)param;
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_INTERFACE;
+ transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(setParam->interface);
+ transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(setParam->alternateSetting);
+
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0);
+}
+
+usb_status_t USB_HostStandardSyncFrame(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_synch_frame_param_t *frameParam;
+
+ /* initialize transfer */
+ frameParam = (usb_host_synch_frame_param_t *)param;
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_RECIPIENT_ENDPOINT;
+ transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(frameParam->endpoint);
+
+ return USB_HostCh9RequestCommon(deviceInstance, transfer, frameParam->frameNumberBuffer, 2);
+}
+
+usb_status_t USB_HostRequestControl(usb_device_handle deviceHandle,
+ uint8_t usbRequest,
+ usb_host_transfer_t *transfer,
+ void *param)
+{
+ usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
+ usb_status_t status = kStatus_USB_Error;
+
+ if (deviceHandle == NULL)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+
+ /* reset transfer fields */
+ transfer->setupPacket->bmRequestType = 0x00;
+ transfer->setupPacket->bRequest = usbRequest;
+ transfer->setupPacket->wIndex = 0;
+ transfer->setupPacket->wLength = 0;
+ transfer->setupPacket->wValue = 0;
+
+ switch (usbRequest)
+ {
+ case USB_REQUEST_STANDARD_GET_STATUS: /* standard get status request */
+ status = USB_HostStandardGetStatus(deviceInstance, transfer, param);
+ break;
+
+ case USB_REQUEST_STANDARD_CLEAR_FEATURE: /* standard clear status request */
+ case USB_REQUEST_STANDARD_SET_FEATURE: /* standard set feature request */
+ status = USB_HostStandardSetClearFeature(deviceInstance, transfer, param);
+ break;
+
+ case USB_REQUEST_STANDARD_SET_ADDRESS: /* standard set address request */
+ status = USB_HostStandardSetAddress(deviceInstance, transfer, param);
+ break;
+
+ case USB_REQUEST_STANDARD_GET_DESCRIPTOR: /* standard get descriptor request */
+ case USB_REQUEST_STANDARD_SET_DESCRIPTOR: /* standard set descriptor request */
+ if (usbRequest == USB_REQUEST_STANDARD_GET_DESCRIPTOR)
+ {
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
+ }
+ status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, param);
+ break;
+
+ case USB_REQUEST_STANDARD_GET_CONFIGURATION: /* standard get configuration descriptor request */
+ transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN;
+ status =
+ USB_HostCh9RequestCommon((usb_host_device_instance_t *)deviceHandle, transfer, (uint8_t *)param, 1);
+ break;
+
+ case USB_REQUEST_STANDARD_SET_CONFIGURATION: /* standard set configuration request */
+ transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(*((uint8_t *)param));
+ status = USB_HostCh9RequestCommon((usb_host_device_instance_t *)deviceHandle, transfer, NULL, 0);
+ break;
+
+ case USB_REQUEST_STANDARD_GET_INTERFACE: /* standard get interface request */
+ status = USB_HostStandardGetInterface(deviceInstance, transfer, param);
+ break;
+
+ case USB_REQUEST_STANDARD_SET_INTERFACE: /* standard set interface request */
+ status = USB_HostStandardSetInterface(deviceInstance, transfer, param);
+ break;
+
+ case USB_REQUEST_STANDARD_SYNCH_FRAME: /* standard synch frame request */
+ status = USB_HostStandardSyncFrame(deviceInstance, transfer, param);
+ break;
+
+ default:
+ /*no action*/
+ break;
+ }
+
+ return status;
+}
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_framework.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_framework.h
new file mode 100644
index 0000000000..b0d8d298e3
--- /dev/null
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_framework.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _USB_HOST_CH9_H_
+#define _USB_HOST_CH9_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup usb_host_drv
+ * @{
+ */
+
+/*! @}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @brief standard control transfer common code.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param buffer data buffer pointer.
+ * @param bufferLen data length.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ uint8_t *buffer,
+ uint32_t bufferLen);
+
+/*!
+ * @brief standard get status implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardGetStatus(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+
+/*!
+ * @brief standard set/clear feature implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardSetClearFeature(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+
+/*!
+ * @brief standard set address implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+
+/*!
+ * @brief standard set/get descriptor implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+
+/*!
+ * @brief standard get interface implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardGetInterface(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+
+/*!
+ * @brief standard set interface implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardSetInterface(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+
+/*!
+ * @brief standard sync frame implementation.
+ *
+ * @param deviceInstance device instance handle.
+ * @param transfer transfer.
+ * @param param parameter.
+ *
+ * @return kStatus_USB_Success or error codes.
+ */
+usb_status_t USB_HostStandardSyncFrame(usb_host_device_instance_t *deviceInstance,
+ usb_host_transfer_t *transfer,
+ void *param);
+#endif /* _USB_HOST_CH9_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c
index 927bf8bd9c..a29a4ea08e 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c
@@ -1,34 +1,12 @@
/*
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016 - 2019 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
-#include
+#include
#include "fsl_common.h"
#include "usb_host.h"
#include "usb_host_hci.h"
@@ -42,16 +20,24 @@
* Definitions
******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "middleware.usb.host_stack"
+#endif
+
+#if defined __CORTEX_M && (__CORTEX_M == 7U)
+#if (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
+#warning USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE is not supported.
+#endif
+#endif
+
/*******************************************************************************
* Prototypes
******************************************************************************/
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
-extern uint32_t USB_HostHubGetTotalThinkTime(usb_host_handle hostHandle, uint8_t parentHubNo);
-
-extern usb_status_t USB_HostHubSuspendDevice(usb_host_handle hostHandle);
-
-extern usb_status_t USB_HostHubResumeDevice(usb_host_handle hostHandle);
+#include "usb_host_hub.h"
+#include "usb_host_hub_app.h"
#endif
/*!
@@ -77,15 +63,6 @@ static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance);
static void USB_HostGetControllerInterface(uint8_t controllerId,
const usb_host_controller_interface_t **controllerTable);
-#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
-#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
-extern void USB_HostEhciTestModeInit(usb_device_handle devHandle);
-#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */
-#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))
-extern void USB_HostIp3516HsTestModeInit(usb_device_handle devHandle);
-#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */
-#endif /* USB_HOST_CONFIG_EHCI */
-
/*******************************************************************************
* Variables
******************************************************************************/
@@ -94,8 +71,7 @@ usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST];
#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
#include "usb_host_ehci.h"
-static const usb_host_controller_interface_t s_EhciInterface = \
-{
+static const usb_host_controller_interface_t s_EhciInterface = {
USB_HostEhciCreate, USB_HostEhciDestory, USB_HostEhciOpenPipe, USB_HostEhciClosePipe,
USB_HostEhciWritePipe, USB_HostEhciReadpipe, USB_HostEhciIoctl,
};
@@ -103,8 +79,7 @@ static const usb_host_controller_interface_t s_EhciInterface = \
#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI))
#include "usb_host_khci.h"
-static const usb_host_controller_interface_t s_KhciInterface = \
-{
+static const usb_host_controller_interface_t s_KhciInterface = {
USB_HostKhciCreate, USB_HostKhciDestory, USB_HostKhciOpenPipe, USB_HostKhciClosePipe,
USB_HostKhciWritePipe, USB_HostKhciReadpipe, USB_HostKciIoctl,
};
@@ -112,8 +87,7 @@ static const usb_host_controller_interface_t s_KhciInterface = \
#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U))
#include "usb_host_ohci.h"
-static const usb_host_controller_interface_t s_OhciInterface = \
-{
+static const usb_host_controller_interface_t s_OhciInterface = {
USB_HostOhciCreate, USB_HostOhciDestory, USB_HostOhciOpenPipe, USB_HostOhciClosePipe,
USB_HostOhciWritePipe, USB_HostOhciReadPipe, USB_HostOhciIoctl,
};
@@ -121,65 +95,67 @@ static const usb_host_controller_interface_t s_OhciInterface = \
#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U))
#include "usb_host_ip3516hs.h"
-static const usb_host_controller_interface_t s_Ip3516HsInterface = \
-{
+static const usb_host_controller_interface_t s_Ip3516HsInterface = {
USB_HostIp3516HsCreate, USB_HostIp3516HsDestory, USB_HostIp3516HsOpenPipe, USB_HostIp3516HsClosePipe,
USB_HostIp3516HsWritePipe, USB_HostIp3516HsReadPipe, USB_HostIp3516HsIoctl,
};
#endif /* USB_HOST_CONFIG_IP3516HS */
-USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE) static uint8_t s_Setupbuffer[USB_HOST_CONFIG_MAX_HOST][USB_HOST_CONFIG_MAX_TRANSFERS][USB_DATA_ALIGN_SIZE_MULTIPLE(8)];
+USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE)
+static uint8_t s_Setupbuffer[USB_HOST_CONFIG_MAX_HOST][USB_HOST_CONFIG_MAX_TRANSFERS][USB_DATA_ALIGN_SIZE_MULTIPLE(8)];
/*******************************************************************************
-* Code
-******************************************************************************/
+ * Code
+ ******************************************************************************/
#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
/*FUNCTION*----------------------------------------------------------------
-*
-* Function Name : usb_test_mode_init
-* Returned Value : None
-* Comments :
-* This function is called by common class to initialize the class driver. It
-* is called in response to a select interface call by application
-*
-*END*--------------------------------------------------------------------*/
+ *
+ * Function Name : usb_test_mode_init
+ * Returned Value : None
+ * Comments :
+ * This function is called by common class to initialize the class driver. It
+ * is called in response to a select interface call by application
+ *
+ *END*--------------------------------------------------------------------*/
usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle)
{
#if (((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) || \
((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)))
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle;
+ usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle;
#endif
uint32_t productId;
uint32_t vendorId;
- usb_echo("usb host test init\r\n");
- USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId);
- USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceVID, &vendorId);
- usb_echo(" vendor id :0x%x product id:0x%x \r\n", vendorId, productId);
+ (void)usb_echo("usb host test init\r\n");
+ (void)USB_HostHelperGetPeripheralInformation(deviceHandle, (uint32_t)kUSB_HostGetDevicePID, &productId);
+ (void)USB_HostHelperGetPeripheralInformation(deviceHandle, (uint32_t)kUSB_HostGetDeviceVID, &vendorId);
+ (void)usb_echo(" vendor id :0x%x product id:0x%x \r\n", vendorId, productId);
- if ((productId != 0x0200U) && (productId != 0x0101) && (productId != 0x0102) && (productId != 0x0103) &&
- (productId != 0x0104) && (productId != 0x0105) && (productId != 0x0106) && (productId != 0x0107) &&
- (productId != 0x0108))
+ if ((productId != 0x0200U) && (productId != 0x0101U) && (productId != 0x0102U) && (productId != 0x0103U) &&
+ (productId != 0x0104U) && (productId != 0x0105U) && (productId != 0x0106U) && (productId != 0x0107U) &&
+ (productId != 0x0108U))
{
- usb_echo("Unsupported Device\r\n");
+ (void)usb_echo("Unsupported Device\r\n");
}
if (productId == 0x0200U)
{
- usb_echo("PET test device attached\r\n");
+ (void)usb_echo("PET test device attached\r\n");
}
else
{
#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
if (hostInstance->controllerTable == &s_EhciInterface)
{
- USB_HostEhciTestModeInit(deviceHandle);
+ (void)hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostTestModeInit,
+ (void *)deviceHandle);
}
-#elif((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))
+#elif ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))
if (hostInstance->controllerTable == &s_Ip3516HsInterface)
{
- USB_HostIp3516HsTestModeInit(deviceHandle);
+ (void)hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostTestModeInit,
+ (void *)deviceHandle);
}
#endif
}
@@ -190,13 +166,14 @@ usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle)
static usb_host_instance_t *USB_HostGetInstance(void)
{
- uint8_t i = 0;
+ uint8_t i = 0;
uint32_t index = 0;
- USB_OSA_SR_ALLOC();
- USB_OSA_ENTER_CRITICAL();
+ void *temp;
+ OSA_SR_ALLOC();
+ OSA_ENTER_CRITICAL();
for (; i < USB_HOST_CONFIG_MAX_HOST; i++)
{
- if (g_UsbHostInstance[i].occupied != 1)
+ if (g_UsbHostInstance[i].occupied != 1U)
{
uint8_t *buffer = (uint8_t *)&g_UsbHostInstance[i];
for (uint32_t j = 0U; j < sizeof(usb_host_instance_t); j++)
@@ -204,53 +181,53 @@ static usb_host_instance_t *USB_HostGetInstance(void)
buffer[j] = 0x00U;
}
g_UsbHostInstance[i].occupied = 1;
- USB_OSA_EXIT_CRITICAL();
+ OSA_EXIT_CRITICAL();
for (index = 0; index < USB_HOST_CONFIG_MAX_TRANSFERS; ++index)
{
- g_UsbHostInstance[i].transferList[index].setupPacket =
- (usb_setup_struct_t *)&(s_Setupbuffer[i][index][0]);
+ temp = (void *)&(s_Setupbuffer[i][index][0]);
+ g_UsbHostInstance[i].transferList[index].setupPacket = (usb_setup_struct_t *)temp;
}
return &g_UsbHostInstance[i];
}
}
- USB_OSA_EXIT_CRITICAL();
+ OSA_EXIT_CRITICAL();
return NULL;
}
static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance)
{
- USB_OSA_SR_ALLOC();
- USB_OSA_ENTER_CRITICAL();
+ OSA_SR_ALLOC();
+ OSA_ENTER_CRITICAL();
hostInstance->occupied = 0;
- USB_OSA_EXIT_CRITICAL();
+ OSA_EXIT_CRITICAL();
}
static void USB_HostGetControllerInterface(uint8_t controllerId,
const usb_host_controller_interface_t **controllerTable)
{
#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI))
- if (controllerId == kUSB_ControllerKhci0)
+ if (controllerId == (uint8_t)kUSB_ControllerKhci0)
{
*controllerTable = &s_KhciInterface;
}
#endif /* USB_HOST_CONFIG_KHCI */
#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
- if ((controllerId == kUSB_ControllerEhci0) || (controllerId == kUSB_ControllerEhci1))
+ if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1))
{
*controllerTable = &s_EhciInterface;
}
#endif /* USB_HOST_CONFIG_EHCI */
#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U))
- if (controllerId == kUSB_ControllerOhci0)
+ if (controllerId == (uint8_t)kUSB_ControllerOhci0)
{
*controllerTable = &s_OhciInterface;
}
#endif /* USB_HOST_CONFIG_OHCI */
#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U))
- if (controllerId == kUSB_ControllerIp3516Hs0)
+ if (controllerId == (uint8_t)kUSB_ControllerIp3516Hs0)
{
*controllerTable = &s_Ip3516HsInterface;
}
@@ -259,10 +236,10 @@ static void USB_HostGetControllerInterface(uint8_t controllerId,
usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, host_callback_t callbackFn)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = NULL;
usb_host_transfer_t *transferPrev = NULL;
- uint8_t i = 0;
+ uint8_t i = 0;
hostInstance = USB_HostGetInstance(); /* get one host instance */
if (hostInstance == NULL)
@@ -291,10 +268,11 @@ usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, hos
}
/* HOST instance init*/
- hostInstance->controllerId = controllerId;
+ hostInstance->controllerId = controllerId;
hostInstance->deviceCallback = callbackFn;
- hostInstance->deviceList = NULL;
- if (kStatus_USB_OSA_Success != USB_OsaMutexCreate(&hostInstance->hostMutex))
+ hostInstance->deviceList = NULL;
+ hostInstance->hostMutex = (osa_mutex_handle_t)(&hostInstance->mutexBuffer[0]);
+ if (KOSA_StatusSuccess != OSA_MutexCreate(hostInstance->hostMutex))
{
USB_HostReleaseInstance(hostInstance);
#ifdef HOST_ECHO
@@ -306,19 +284,19 @@ usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, hos
/* initialize transfer list */
hostInstance->transferHead = &hostInstance->transferList[0];
- transferPrev = hostInstance->transferHead;
+ transferPrev = hostInstance->transferHead;
for (i = 1; i < USB_HOST_CONFIG_MAX_TRANSFERS; ++i)
{
transferPrev->next = &hostInstance->transferList[i];
- transferPrev = transferPrev->next;
+ transferPrev = transferPrev->next;
}
- /* controller create */
+ /* controller create, the callbackFn is initialized in USB_HostGetControllerInterface */
status =
hostInstance->controllerTable->controllerCreate(controllerId, hostInstance, &(hostInstance->controllerHandle));
if ((status != kStatus_USB_Success) || (hostInstance->controllerHandle == NULL))
{
- USB_OsaMutexDestroy(hostInstance->hostMutex);
+ (void)OSA_MutexDestroy(hostInstance->hostMutex);
USB_HostReleaseInstance(hostInstance);
#ifdef HOST_ECHO
usb_echo("host init: controller init fail\r\n");
@@ -332,8 +310,8 @@ usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, hos
usb_status_t USB_HostDeinit(usb_host_handle hostHandle)
{
- usb_status_t status = kStatus_USB_Success;
- usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
+ usb_status_t status = kStatus_USB_Success;
+ usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
usb_host_device_instance_t *deviceInstance = NULL;
if (hostHandle == NULL)
@@ -346,23 +324,23 @@ usb_status_t USB_HostDeinit(usb_host_handle hostHandle)
while (deviceInstance != NULL)
{
deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList;
- USB_HostDetachDeviceInternal(hostHandle, deviceInstance);
+ (void)USB_HostDetachDeviceInternal(hostHandle, deviceInstance);
}
- /* controller instance destory */
- status = hostInstance->controllerTable->controllerDestory(hostInstance->controllerHandle);
+ /* controller instance destroy, the callbackFn is initialized in USB_HostGetControllerInterface */
+ status = hostInstance->controllerTable->controllerDestory(hostInstance->controllerHandle);
hostInstance->controllerHandle = NULL;
if (status != kStatus_USB_Success)
{
#ifdef HOST_ECHO
- usb_echo("host controller destory fail\r\n");
+ usb_echo("host controller destroy fail\r\n");
#endif
}
/* resource release */
- if (hostInstance->hostMutex)
+ if (NULL != hostInstance->hostMutex)
{
- USB_OsaMutexDestroy(hostInstance->hostMutex);
+ (void)OSA_MutexDestroy(hostInstance->hostMutex);
hostInstance->hostMutex = NULL;
}
USB_HostReleaseInstance(hostInstance);
@@ -374,7 +352,7 @@ usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle,
usb_host_pipe_handle *pipeHandle,
usb_host_pipe_init_t *pipeInit)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if ((hostHandle == NULL) || (pipeInit == NULL))
@@ -382,7 +360,7 @@ usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle,
return kStatus_USB_InvalidHandle;
}
- /* call controller open pipe interface */
+ /* call controller open pipe interface, the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerOpenPipe(hostInstance->controllerHandle, pipeHandle, pipeInit);
return status;
@@ -390,7 +368,7 @@ usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle,
usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if ((hostHandle == NULL) || (pipeHandle == NULL))
@@ -398,7 +376,7 @@ usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle
return kStatus_USB_InvalidHandle;
}
- /* call controller close pipe interface */
+ /* call controller close pipe interface, the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerClosePipe(hostInstance->controllerHandle, pipeHandle);
return status;
@@ -406,7 +384,7 @@ usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle
usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL))
@@ -416,9 +394,9 @@ usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeH
/* initialize transfer */
transfer->transferSofar = 0;
- transfer->direction = USB_OUT;
+ transfer->direction = USB_OUT;
- USB_HostLock(); /* This api can be called by host task and app task */
+ (void)USB_HostLock(); /* This api can be called by host task and app task */
/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function
*/
#if 0
@@ -435,9 +413,10 @@ usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeH
DCACHE_CleanByRange((uint32_t)transfer->transferBuffer, transfer->transferLength);
}
#endif
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer);
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return status;
}
@@ -445,7 +424,7 @@ usb_status_t USB_HostSendSetup(usb_host_handle hostHandle,
usb_host_pipe_handle pipeHandle,
usb_host_transfer_t *transfer)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL))
@@ -455,8 +434,8 @@ usb_status_t USB_HostSendSetup(usb_host_handle hostHandle,
/* initialize transfer */
transfer->transferSofar = 0;
- transfer->next = NULL;
- transfer->setupStatus = 0;
+ transfer->next = NULL;
+ transfer->setupStatus = 0;
if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN)
{
transfer->direction = USB_IN;
@@ -466,7 +445,7 @@ usb_status_t USB_HostSendSetup(usb_host_handle hostHandle,
transfer->direction = USB_OUT;
}
- USB_HostLock(); /* This API can be called by host task and application task */
+ (void)USB_HostLock(); /* This API can be called by host task and application task */
/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function
*/
#if 0
@@ -484,15 +463,16 @@ usb_status_t USB_HostSendSetup(usb_host_handle hostHandle,
DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength);
}
#endif
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer);
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return status;
}
usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL))
@@ -502,9 +482,9 @@ usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeH
/* initialize transfer */
transfer->transferSofar = 0;
- transfer->direction = USB_IN;
+ transfer->direction = USB_IN;
- USB_HostLock(); /* This API can be called by host task and application task */
+ (void)USB_HostLock(); /* This API can be called by host task and application task */
/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function
*/
#if 0
@@ -521,9 +501,10 @@ usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeH
DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength);
}
#endif
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerReadPipe(hostInstance->controllerHandle, pipeHandle, transfer);
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return status;
}
@@ -531,7 +512,7 @@ usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle,
usb_host_pipe_handle pipeHandle,
usb_host_transfer_t *transfer)
{
- usb_status_t status = kStatus_USB_Success;
+ usb_status_t status = kStatus_USB_Success;
usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle;
usb_host_cancel_param_t cancelParam;
@@ -542,9 +523,10 @@ usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle,
/* initialize cancel parameter */
cancelParam.pipeHandle = pipeHandle;
- cancelParam.transfer = transfer;
+ cancelParam.transfer = transfer;
/* USB_HostLock(); This api can be called by host task and app task */
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostCancelTransfer,
&cancelParam);
/* USB_HostUnlock(); */
@@ -562,18 +544,18 @@ usb_status_t USB_HostMallocTransfer(usb_host_handle hostHandle, usb_host_transfe
}
/* get one from the transfer_head */
- USB_HostLock();
+ (void)USB_HostLock();
if (hostInstance->transferHead != NULL)
{
- *transfer = hostInstance->transferHead;
+ *transfer = hostInstance->transferHead;
hostInstance->transferHead = hostInstance->transferHead->next;
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Success;
}
else
{
*transfer = NULL;
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Error;
}
}
@@ -592,10 +574,10 @@ usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_transfer_
}
/* release one to the transfer_head */
- USB_HostLock();
- transfer->next = hostInstance->transferHead;
+ (void)USB_HostLock();
+ transfer->next = hostInstance->transferHead;
hostInstance->transferHead = transfer;
- USB_HostUnlock();
+ (void)USB_HostUnlock();
return kStatus_USB_Success;
}
@@ -604,23 +586,28 @@ usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHand
uint32_t *infoValue)
{
usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle;
+ uint32_t *temp;
+ usb_host_dev_info_t devInfo;
if ((deviceHandle == NULL) || (infoValue == NULL))
{
return kStatus_USB_InvalidParameter;
}
-
- switch (infoCode)
+ devInfo = (usb_host_dev_info_t)infoCode;
+ switch (devInfo)
{
case kUSB_HostGetDeviceAddress: /* device address */
+
*infoValue = (uint32_t)deviceInstance->setAddress;
break;
case kUSB_HostGetDeviceControlPipe: /* device control pipe */
- *infoValue = (uint32_t)deviceInstance->controlPipe;
+ temp = (uint32_t *)deviceInstance->controlPipe;
+ *infoValue = (uint32_t)temp;
break;
case kUSB_HostGetHostHandle: /* device host handle */
- *infoValue = (uint32_t)deviceInstance->hostHandle;
+ temp = (uint32_t *)deviceInstance->hostHandle;
+ *infoValue = (uint32_t)temp;
break;
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
@@ -685,7 +672,8 @@ usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHand
break;
default:
- return kStatus_USB_Error;
+ /*no action*/
+ break;
}
return kStatus_USB_Success;
@@ -698,26 +686,27 @@ usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle inter
uint32_t endPosition;
usb_descriptor_union_t *unionDes;
usb_host_ep_t *epParse;
-
+ void *temp;
if (interfaceHandle == NULL)
{
return kStatus_USB_InvalidHandle;
}
- if (alternateSetting == 0)
+ if (alternateSetting == 0U)
{
return kStatus_USB_InvalidParameter;
}
/* parse configuration descriptor */
- unionDes = (usb_descriptor_union_t *)((usb_host_interface_t *)interfaceHandle)
- ->interfaceDesc; /* interface extend descriptor start */
+ temp = (void *)((usb_host_interface_t *)interfaceHandle)->interfaceDesc;
+ ;
+ unionDes = (usb_descriptor_union_t *)temp; /* interface extend descriptor start */
endPosition =
(uint32_t)unionDes +
((usb_host_interface_t *)interfaceHandle)->interfaceExtensionLength; /* interface extend descriptor end */
unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength);
- /* search for the alternate setting interface descritpor */
+ /* search for the alternate setting interface descriptor */
while ((uint32_t)unionDes < endPosition)
{
if (unionDes->interface.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE)
@@ -742,12 +731,12 @@ usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle inter
}
/* initialize interface handle structure instance */
- interface->interfaceDesc = &unionDes->interface;
- interface->alternateSettingNumber = 0;
- interface->epCount = 0;
- interface->interfaceExtension = NULL;
- interface->interfaceExtensionLength = 0;
- interface->interfaceIndex = unionDes->interface.bInterfaceNumber;
+ interface->interfaceDesc = &unionDes->interface;
+ interface->alternateSettingNumber = 0U;
+ interface->epCount = 0U;
+ interface->interfaceExtension = NULL;
+ interface->interfaceExtensionLength = 0U;
+ interface->interfaceIndex = unionDes->interface.bInterfaceNumber;
/* search for endpoint descriptor start position */
unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength);
@@ -770,7 +759,7 @@ usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle inter
}
/* parse endpoint descriptor */
- if (interface->interfaceDesc->bNumEndpoints != 0)
+ if (interface->interfaceDesc->bNumEndpoints != 0U)
{
if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) ||
(interface->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP))
@@ -790,11 +779,12 @@ usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle inter
#endif
return kStatus_USB_Error;
}
- epParse = (usb_host_ep_t *)&interface->epList[interface->epCount];
- epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes;
+ epParse = (usb_host_ep_t *)&interface->epList[interface->epCount];
+ temp = (void *)unionDes;
+ epParse->epDesc = (usb_descriptor_endpoint_t *)temp;
epParse->epExtensionLength = 0;
- epParse->epExtension = NULL;
- unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength);
+ epParse->epExtension = NULL;
+ unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength);
while ((uint32_t)unionDes < endPosition)
{
if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) &&
@@ -820,7 +810,7 @@ usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle inter
void USB_HostGetVersion(uint32_t *version)
{
- if (version)
+ if (NULL != version)
{
*version =
(uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX);
@@ -828,12 +818,12 @@ void USB_HostGetVersion(uint32_t *version)
}
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
-/* Send BUS or specific device suepend request */
+/* Send BUS or specific device suspend request */
usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle)
{
usb_host_instance_t *hostInstance;
usb_host_device_instance_t *deviceInstance;
- usb_status_t status = kStatus_USB_Error;
+ usb_status_t status = kStatus_USB_Error;
usb_host_bus_control_t type = kUSB_HostBusSuspend;
if (hostHandle == NULL)
@@ -849,6 +839,7 @@ usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_devic
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
status = USB_HostHubSuspendDevice(hostInstance);
#else
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status =
hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type);
#endif
@@ -857,11 +848,12 @@ usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_devic
{
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- if (0 == deviceInstance->hubNumber)
+ if (0U == deviceInstance->hubNumber)
{
#endif
if (hostInstance->deviceList == deviceHandle)
{
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle,
kUSB_HostBusControl, &type);
}
@@ -888,7 +880,7 @@ usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device
{
usb_host_instance_t *hostInstance;
usb_host_device_instance_t *deviceInstance;
- usb_status_t status = kStatus_USB_Error;
+ usb_status_t status = kStatus_USB_Error;
usb_host_bus_control_t type = kUSB_HostBusResume;
if (hostHandle == NULL)
@@ -905,6 +897,7 @@ usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device
if (NULL == deviceHandle)
{
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status =
hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type);
}
@@ -912,11 +905,12 @@ usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device
{
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
deviceInstance = (usb_host_device_instance_t *)deviceHandle;
- if (0 == deviceInstance->hubNumber)
+ if (0U == deviceInstance->hubNumber)
{
#endif
if (hostInstance->deviceList == deviceHandle)
{
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle,
kUSB_HostBusControl, &type);
}
@@ -935,13 +929,13 @@ usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device
return status;
}
#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U))
-/* Send BUS or specific device suepend request */
+/* Send BUS or specific device suspend request */
usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle,
usb_device_handle deviceHandle,
uint8_t sleepType)
{
usb_host_instance_t *hostInstance;
- usb_status_t status = kStatus_USB_Error;
+ usb_status_t status = kStatus_USB_Error;
usb_host_bus_control_t type = kUSB_HostBusL1Sleep;
if (hostHandle == NULL)
@@ -955,8 +949,9 @@ usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle,
if (1U == sleepType)
{
/*#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))*/
- /*To do, implete hub L1 suspend device*/
+ /*To do, incomplete hub L1 suspend device*/
/*#else*/
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status =
hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type);
/*#endif*/
@@ -968,6 +963,7 @@ usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle,
#endif
if (hostInstance->deviceList == deviceHandle)
{
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl,
&type);
}
@@ -978,7 +974,7 @@ usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle,
}
return status;
}
-/* Send BUS or specific device suepend request */
+/* Send BUS or specific device suspend request */
usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam)
{
usb_host_instance_t *hostInstance;
@@ -989,7 +985,7 @@ usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uin
return kStatus_USB_InvalidHandle;
}
hostInstance = (usb_host_instance_t *)hostHandle;
-
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status =
hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostL1Config, lpmParam);
@@ -1003,7 +999,7 @@ usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle,
{
usb_host_instance_t *hostInstance;
- usb_status_t status = kStatus_USB_Error;
+ usb_status_t status = kStatus_USB_Error;
usb_host_bus_control_t type = kUSB_HostBusL1Resume;
if (hostHandle == NULL)
@@ -1014,17 +1010,19 @@ usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle,
if (1U == sleepType)
{
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status =
hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type);
}
else
{
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
-/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/
+ /*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/
#endif
if (hostInstance->deviceList == deviceHandle)
{
+ /* the callbackFn is initialized in USB_HostGetControllerInterface */
status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl,
&type);
}
@@ -1050,3 +1048,18 @@ usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick)
return status;
}
#endif
+
+#if ((defined(USB_HOST_CONFIG_BATTERY_CHARGER)) && (USB_HOST_CONFIG_BATTERY_CHARGER > 0U))
+usb_status_t USB_HostSetChargerType(usb_host_handle hostHandle, uint8_t type)
+{
+ usb_host_instance_t *hostInstance;
+
+ if (hostHandle == NULL)
+ {
+ return kStatus_USB_InvalidHandle;
+ }
+ hostInstance = (usb_host_instance_t *)hostHandle;
+ return hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostSetChargerType,
+ &type);
+}
+#endif
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h
index 26b6d4a9c5..f9ac8b6a7f 100644
--- a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h
+++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h
@@ -1,31 +1,9 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016 - 2019 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _USB_HOST_HCI_H_
@@ -36,9 +14,9 @@
******************************************************************************/
/*! @brief USB host lock */
-#define USB_HostLock() USB_OsaMutexLock(hostInstance->hostMutex)
+#define USB_HostLock() OSA_MutexLock(hostInstance->hostMutex, USB_OSA_WAIT_TIMEOUT)
/*! @brief USB host unlock */
-#define USB_HostUnlock() USB_OsaMutexUnlock(hostInstance->hostMutex)
+#define USB_HostUnlock() OSA_MutexUnlock(hostInstance->hostMutex)
/*!
* @addtogroup usb_host_controller_driver
@@ -56,6 +34,10 @@ typedef enum _usb_host_controller_control
kUSB_HostPortAttachDisable, /*!< Disable the port attach event */
kUSB_HostPortAttachEnable, /*!< Enable the port attach event */
kUSB_HostL1Config, /*!< L1 suspend Bus control code */
+ kUSB_HostSetChargerType, /*!< set charger type */
+#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
+ kUSB_HostTestModeInit, /*!< intialize charger type */
+#endif
} usb_host_controller_control_t;
/*! @brief USB host controller bus control code */
@@ -97,7 +79,9 @@ typedef struct _usb_host_controller_interface
uint32_t ioctlEvent,
void *ioctlParam); /*!< Control a controller function prototype*/
} usb_host_controller_interface_t;
-
+#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST))
+usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle);
+#endif
/*! @}*/
/*!
@@ -110,7 +94,8 @@ typedef struct _usb_host_instance
{
void *controllerHandle; /*!< The low level controller handle*/
host_callback_t deviceCallback; /*!< Device attach/detach callback*/
- usb_osa_mutex_handle hostMutex; /*!< Host layer mutex*/
+ osa_mutex_handle_t hostMutex; /*!< Host layer mutex*/
+ uint32_t mutexBuffer[(OSA_MUTEX_HANDLE_SIZE + 3) / 4]; /*!< Host layer mutex*/
usb_host_transfer_t transferList[USB_HOST_CONFIG_MAX_TRANSFERS]; /*!< Transfer resource*/
usb_host_transfer_t *transferHead; /*!< Idle transfer head*/
const usb_host_controller_interface_t *controllerTable; /*!< KHCI/EHCI interface*/
@@ -126,6 +111,7 @@ typedef struct _usb_host_instance
uint8_t controllerId; /*!< The controller ID*/
} usb_host_instance_t;
+extern usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST];
/*! @}*/
-#endif /* _USB_HOST_HCI_H_ */
+#endif /* _USB_HOST_HCI_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb.h b/bsp/imxrt/libraries/drivers/usb/include/usb.h
index 256896b472..a5d0550ce0 100644
--- a/bsp/imxrt/libraries/drivers/usb/include/usb.h
+++ b/bsp/imxrt/libraries/drivers/usb/include/usb.h
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include "usb_misc.h"
#include "usb_spec.h"
@@ -137,4 +138,4 @@ typedef struct _usb_version
/*! @} */
-#endif /* __USB_H__ */
+#endif /* __USB_H__ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h b/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h
new file mode 100644
index 0000000000..73bc46a8e6
--- /dev/null
+++ b/bsp/imxrt/libraries/drivers/usb/include/usb_host_config.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _USB_HOST_CONFIG_H_
+#define _USB_HOST_CONFIG_H_
+
+/* Host Controller Enable */
+/*!
+ * @brief host khci instance count, meantime it indicates khci enable or disable.
+ * - if 0, host khci driver is disable.
+ * - if greater than 0, host khci driver is enable.
+ */
+#define USB_HOST_CONFIG_KHCI (0U)
+
+/*!
+ * @brief host ehci instance count, meantime it indicates ehci enable or disable.
+ * - if 0, host ehci driver is disable.
+ * - if greater than 0, host ehci driver is enable.
+ */
+#define USB_HOST_CONFIG_EHCI (2U)
+
+/*!
+ * @brief host ohci instance count, meantime it indicates ohci enable or disable.
+ * - if 0, host ohci driver is disable.
+ * - if greater than 0, host ohci driver is enable.
+ */
+#define USB_HOST_CONFIG_OHCI (0U)
+
+/*!
+ * @brief host ip3516hs instance count, meantime it indicates ohci enable or disable.
+ * - if 0, host ip3516hs driver is disable.
+ * - if greater than 0, host ip3516hs driver is enable.
+ */
+#define USB_HOST_CONFIG_IP3516HS (0U)
+
+/* Common configuration macros for all controllers */
+
+/*!
+ * @brief host driver instance max count.
+ * for example: 2 - one for khci, one for ehci.
+ */
+#define USB_HOST_CONFIG_MAX_HOST \
+ (USB_HOST_CONFIG_KHCI + USB_HOST_CONFIG_EHCI + USB_HOST_CONFIG_OHCI + USB_HOST_CONFIG_IP3516HS)
+
+/*!
+ * @brief host pipe max count.
+ * pipe is the host driver resource for device endpoint, one endpoint need one pipe.
+ */
+#define USB_HOST_CONFIG_MAX_PIPES (16U)
+
+/*!
+ * @brief host transfer max count.
+ * transfer is the host driver resource for data transmission mission, one transmission mission need one transfer.
+ */
+#define USB_HOST_CONFIG_MAX_TRANSFERS (16U)
+
+/*!
+ * @brief the max endpoint for one interface.
+ * the max endpoint descriptor number that one interface descriptor contain.
+ */
+#define USB_HOST_CONFIG_INTERFACE_MAX_EP (4U)
+
+/*!
+ * @brief the max interface for one configuration.
+ * the max interface descriptor number that one configuration descriptor can contain.
+ */
+#define USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE (5U)
+
+/*!
+ * @brief the max power for one device.
+ * the max power the host can provide for one device.
+ */
+#define USB_HOST_CONFIG_MAX_POWER (250U)
+
+/*!
+ * @brief the max retries for enumeration.
+ * retry time when enumeration fail.
+ */
+#define USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES (3U)
+
+/*!
+ * @brief the max retries for enumeration setup stall.
+ * the max times for one transfer can stall.
+ */
+#define USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES (1U)
+
+/*!
+ * @brief the max NAK count for one transaction.
+ * when nak count reach to the value, the transaction fail.
+ */
+#define USB_HOST_CONFIG_MAX_NAK (3000U)
+
+/*! @brief Whether the transfer buffer is cache-enabled or not. */
+#ifndef USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE
+#define USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
+#endif
+/*! @brief if 1, enable usb compliance test codes; if 0, disable usb compliance test codes. */
+#define USB_HOST_CONFIG_COMPLIANCE_TEST (0U)
+
+/*! @brief if 1, class driver clear stall automatically; if 0, class driver don't clear stall. */
+#define USB_HOST_CONFIG_CLASS_AUTO_CLEAR_STALL (0U)
+
+/* KHCI configuration */
+#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI))
+
+/*!
+ * @brief khci dma align fix buffer size.
+ */
+#define USB_HOST_CONFIG_KHCI_DMA_ALIGN_BUFFER (64U)
+
+#endif
+
+/* EHCI configuration */
+#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI))
+
+/*!
+ * @brief ehci periodic frame list size.
+ * the value can be 1024, 512, 256, 128, 64, 32, 16 or 8.
+ */
+#define USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE (1024U)
+
+/*!
+ * @brief ehci QH max count.
+ */
+#define USB_HOST_CONFIG_EHCI_MAX_QH (8U)
+
+/*!
+ * @brief ehci QTD max count.
+ */
+#define USB_HOST_CONFIG_EHCI_MAX_QTD (8U)
+
+/*!
+ * @brief ehci ITD max count.
+ */
+#define USB_HOST_CONFIG_EHCI_MAX_ITD (0U)
+
+/*!
+ * @brief ehci SITD max count.
+ */
+#define USB_HOST_CONFIG_EHCI_MAX_SITD (0U)
+
+#endif
+
+/* OHCI configuration */
+#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI))
+
+/*!
+ * @brief ohci ED max count.
+ */
+#define USB_HOST_CONFIG_OHCI_MAX_ED (8U)
+
+/*!
+ * @brief ohci GTD max count.
+ */
+#define USB_HOST_CONFIG_OHCI_MAX_GTD (8U)
+
+/*!
+ * @brief ohci ITD max count.
+ */
+#define USB_HOST_CONFIG_OHCI_MAX_ITD (8U)
+
+#endif
+
+/* OHCI configuration */
+#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))
+
+#define USB_HOST_CONFIG_IP3516HS_MAX_PIPE (32U)
+
+/*!
+ * @brief ohci ED max count.
+ */
+#define USB_HOST_CONFIG_IP3516HS_MAX_ATL (32U)
+
+/*!
+ * @brief ohci GTD max count.
+ */
+#define USB_HOST_CONFIG_IP3516HS_MAX_INT (32U)
+
+/*!
+ * @brief ohci ITD max count.
+ */
+#define USB_HOST_CONFIG_IP3516HS_MAX_ISO (0U)
+
+#endif
+
+/*!
+ * @brief host HUB class instance count, meantime it indicates HUB class enable or disable.
+ * - if 0, host HUB class driver is disable.
+ * - if greater than 0, host HUB class driver is enable.
+ */
+#define USB_HOST_CONFIG_HUB (0U)
+
+/*!
+ * @brief host HID class instance count, meantime it indicates HID class enable or disable.
+ * - if 0, host HID class driver is disable.
+ * - if greater than 0, host HID class driver is enable.
+ */
+#define USB_HOST_CONFIG_HID (0U)
+
+/*!
+ * @brief host MSD class instance count, meantime it indicates MSD class enable or disable.
+ * - if 0, host MSD class driver is disable.
+ * - if greater than 0, host MSD class driver is enable.
+ */
+#define USB_HOST_CONFIG_MSD (0U)
+
+/*!
+ * @brief host CDC class instance count, meantime it indicates CDC class enable or disable.
+ * - if 0, host CDC class driver is disable.
+ * - if greater than 0, host CDC class driver is enable.
+ */
+#define USB_HOST_CONFIG_CDC (0U)
+
+/*!
+ * @brief host AUDIO class instance count, meantime it indicates AUDIO class enable or disable.
+ * - if 0, host AUDIO class driver is disable.
+ * - if greater than 0, host AUDIO class driver is enable.
+ */
+#define USB_HOST_CONFIG_AUDIO (0U)
+
+/*!
+ * @brief host PHDC class instance count, meantime it indicates PHDC class enable or disable.
+ * - if 0, host PHDC class driver is disable.
+ * - if greater than 0, host PHDC class driver is enable.
+ */
+#define USB_HOST_CONFIG_PHDC (0U)
+
+/*!
+ * @brief host printer class instance count, meantime it indicates printer class enable or disable.
+ * - if 0, host printer class driver is disable.
+ * - if greater than 0, host printer class driver is enable.
+ */
+#define USB_HOST_CONFIG_PRINTER (0U)
+
+/*!
+ * @brief host charger detect enable or disable. It is only supported on RT600 currently.
+ * - if 0, host charger detect is disable.
+ * - if greater than 0, host charger detect is enable.
+ */
+#define USB_HOST_CONFIG_BATTERY_CHARGER (0U)
+
+#endif /* _USB_HOST_CONFIG_H_ */
\ No newline at end of file
diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h b/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h
index 4e65cfa94b..382c5d3619 100644
--- a/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h
+++ b/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h
@@ -1,46 +1,34 @@
/*
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016, 2019 NXP
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __USB_MISC_H__
#define __USB_MISC_H__
-#ifndef ENDIANNESS
-
-#error ENDIANNESS should be defined, and then rebulid the project.
-
-#endif
-
/*******************************************************************************
* Definitions
******************************************************************************/
+/*! @brief Define big endian */
+#define USB_BIG_ENDIAN (0U)
+/*! @brief Define little endian */
+#define USB_LITTLE_ENDIAN (1U)
+
+/*! @brief Define current endian */
+#ifndef ENDIANNESS
+#define ENDIANNESS USB_LITTLE_ENDIAN
+#endif
+/*! @brief Define default timeout value */
+#if (defined(USE_RTOS) && (USE_RTOS > 0))
+#define USB_OSA_WAIT_TIMEOUT (osaWaitForever_c)
+#else
+#define USB_OSA_WAIT_TIMEOUT (0U)
+#endif /* (defined(USE_RTOS) && (USE_RTOS > 0)) */
+
/*! @brief Define USB printf */
#if defined(__cplusplus)
extern "C" {
@@ -52,10 +40,14 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
}
#endif /* __cplusplus */
+#ifndef __DSC__
#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1)
#define usb_echo printf
#else
-#define usb_echo DbgConsole_Printf
+#define usb_echo rt_kprintf
+#endif
+#else
+#define usb_echo
#endif
#if defined(__ICCARM__)
@@ -78,7 +70,7 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
#define STRUCT_UNPACKED __attribute__((__packed__))
#endif
-#elif defined(__CC_ARM)
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION))
#ifndef STRUCT_PACKED
#define STRUCT_PACKED _Pragma("pack(1U)")
@@ -112,7 +104,7 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \
{ \
- *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
+ *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
*((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \
*((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \
*((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \
@@ -120,13 +112,13 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \
{ \
- *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
+ *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \
*((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \
}
#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \
{ \
- *((uint8_t *)&(n)) = (uint8_t)m; \
+ *((uint8_t *)&(n)) = (uint8_t)m; \
*((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \
*((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \
*((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \
@@ -134,7 +126,7 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \
{ \
- *((uint8_t *)&(n)) = (uint8_t)m; \
+ *((uint8_t *)&(n)) = (uint8_t)m; \
*((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \
}
@@ -150,65 +142,66 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
#define USB_SHORT_FROM_BIG_ENDIAN(n) (n)
#define USB_LONG_FROM_BIG_ENDIAN(n) (n)
-#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
- { \
- m[3] = ((n >> 24U) & 0xFFU); \
- m[2] = ((n >> 16U) & 0xFFU); \
- m[1] = ((n >> 8U) & 0xFFU); \
- m[0] = (n & 0xFFU); \
+#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \
}
-#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
- ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \
- (((uint8_t)n[0]) << 0U)))
+#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \
+ (((uint32_t)n[0]) << 0U)))
-#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
- { \
- m[0] = ((n >> 24U) & 0xFFU); \
- m[1] = ((n >> 16U) & 0xFFU); \
- m[2] = ((n >> 8U) & 0xFFU); \
- m[3] = (n & 0xFFU); \
+#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[3] = (((uint32_t)(n)) & 0xFFU); \
}
-#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
- ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \
- (((uint8_t)n[3]) << 0U)))
+#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \
+ (((uint32_t)n[3]) << 0U)))
-#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
- { \
- m[1] = ((n >> 8U) & 0xFFU); \
- m[0] = (n & 0xFFU); \
+#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint16_t)(n)) & 0xFFU); \
}
-#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U)))
+#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U)))
-#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
- { \
- m[0] = ((n >> 8U) & 0xFFU); \
- m[1] = (n & 0xFFU); \
+#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[1] = (((uint16_t)(n)) & 0xFFU); \
}
-#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U)))
+#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U)))
-#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
- { \
- *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \
- *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \
- *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \
- *((uint8_t *)&(m) + 0) = (n & 0xFFU); \
+#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \
}
-#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
- ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \
- ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U)))
+#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \
+ ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U)))
-#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
- { \
- *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \
- *((uint8_t *)&(m)) = ((n)&0xFFU); \
+#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \
}
-#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))))))
+#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint16_t)((uint16_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n)))))
#else
@@ -222,75 +215,76 @@ extern int DbgConsole_Printf(const char *fmt_s, ...);
#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n)
#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n)
-#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
- { \
- m[3] = ((n >> 24U) & 0xFFU); \
- m[2] = ((n >> 16U) & 0xFFU); \
- m[1] = ((n >> 8U) & 0xFFU); \
- m[0] = (n & 0xFFU); \
+#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \
}
-#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
- ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \
- (((uint8_t)n[0]) << 0U)))
+#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \
+ (((uint32_t)n[0]) << 0U)))
-#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
- { \
- m[0] = ((n >> 24U) & 0xFFU); \
- m[1] = ((n >> 16U) & 0xFFU); \
- m[2] = ((n >> 8U) & 0xFFU); \
- m[3] = (n & 0xFFU); \
+#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ m[3] = (((uint32_t)(n)) & 0xFFU); \
}
-#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
- ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \
- (((uint8_t)n[3]) << 0U)))
+#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \
+ ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \
+ (((uint32_t)n[3]) << 0U)))
-#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
- { \
- m[1] = ((n >> 8U) & 0xFFU); \
- m[0] = (n & 0xFFU); \
+#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[0] = (((uint16_t)(n)) & 0xFFU); \
}
-#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U)))
+#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U)))
-#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
- { \
- m[0] = ((n >> 8U) & 0xFFU); \
- m[1] = (n & 0xFFU); \
+#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \
+ { \
+ m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ m[1] = (((uint16_t)(n)) & 0xFFU); \
}
-#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U)))
+#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U)))
-#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
- { \
- *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \
- *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \
- *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \
- *((uint8_t *)&(m) + 0) = (n & 0xFFU); \
+#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \
+ *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \
+ *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \
}
-#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
- ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \
- ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U)))
+#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \
+ ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U)))
-#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
- { \
- *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \
- *((uint8_t *)&(m)) = ((n)&0xFFU); \
+#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \
+ { \
+ *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \
+ *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \
}
-#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))))))
+#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \
+ ((uint16_t)(((uint16_t)(*(((uint8_t *)&(n)) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n))))))
#endif
/*
* The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack.
- * The USB device global variables are put into the section m_usb_global and m_usb_bdt or the section
- * .bss.m_usb_global and .bss.m_usb_bdt by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device
+ * The USB device global variables are put into the section m_usb_global and m_usb_bdt
+ * by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device
* global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM.
* The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of
- * the marco can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT.
+ * the macro can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT.
* The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and
* USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM
* is not less than 2K Bytes.
@@ -313,40 +307,63 @@ _Pragma("diag_suppress=Pm120")
#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n)
_Pragma("diag_suppress=Pm120")
#define USB_LINK_SECTION_PART(str) _Pragma(#str)
-#define USB_LINK_SECTION_SUB(sec) USB_LINK_SECTION_PART(location = #sec)
+#define USB_LINK_DMA_INIT_DATA(sec) USB_LINK_SECTION_PART(location = #sec)
#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"")
#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"")
-#define USB_LINK_USB_GLOBAL_BSS _Pragma("location = \".bss.m_usb_global\"")
-#define USB_LINK_USB_BDT_BSS _Pragma("location = \".bss.m_usb_bdt\"")
+#define USB_LINK_USB_GLOBAL_BSS
+#define USB_LINK_USB_BDT_BSS
_Pragma("diag_default=Pm120")
#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"")
#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"")
-#elif defined(__CC_ARM)
+#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION))
#define USB_WEAK_VAR __attribute__((weak))
-#define USB_WEAK_FUN __weak
+#define USB_WEAK_FUN __attribute__((weak))
#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
-#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec)))
+#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
+#if defined(__CC_ARM)
#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init))
+#else
+#define USB_LINK_USB_GLOBAL __attribute__((section(".bss.m_usb_global")))
+#endif
+#if defined(__CC_ARM)
#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init))
-#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global"))) __attribute__((zero_init))
-#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt"))) __attribute__((zero_init))
+#else
+#define USB_LINK_USB_BDT __attribute__((section(".bss.m_usb_bdt")))
+#endif
+#define USB_LINK_USB_GLOBAL_BSS
+#define USB_LINK_USB_BDT_BSS
+#if defined(__CC_ARM)
#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init))
+#else
+#define USB_LINK_DMA_NONINIT_DATA __attribute__((section(".bss.m_usb_dma_noninit_data")))
+#endif
+#if defined(__CC_ARM)
#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init))
+#else
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section(".bss.NonCacheable")))
+#endif
#elif defined(__GNUC__)
#define USB_WEAK_VAR __attribute__((weak))
#define USB_WEAK_FUN __attribute__((weak))
#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
-#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec)))
+#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @")))
#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @")))
-#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global, \"aw\", %nobits @")))
-#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt, \"aw\", %nobits @")))
+#define USB_LINK_USB_GLOBAL_BSS
+#define USB_LINK_USB_BDT_BSS
#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @")))
#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @")))
+#elif (defined(__DSC__) && defined(__CW__))
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define USB_WEAK_VAR __attribute__((weak))
+#define USB_WEAK_FUN __attribute__((weak))
+#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
+#define USB_LINK_USB_BDT_BSS
+#define USB_LINK_USB_GLOBAL_BSS
#else
#error The tool-chain is not supported.
#endif
@@ -356,28 +373,32 @@ _Pragma("diag_suppress=Pm120")
#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#elif(defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))
+#elif (defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))
#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0)
-#elif(defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))
+#elif (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))
#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#else
-#define USB_CACHE_LINESIZE 4
+#define USB_CACHE_LINESIZE 4U
#endif
#else
-#define USB_CACHE_LINESIZE 4
+#define USB_CACHE_LINESIZE 4U
#endif
#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \
((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)))
-#define USB_DATA_ALIGN 64
+#define USB_DATA_ALIGN 64U
#else
-#define USB_DATA_ALIGN 4
+#define USB_DATA_ALIGN 4U
#endif
-#define USB_DATA_ALIGN_SIZE MAX(USB_CACHE_LINESIZE, USB_DATA_ALIGN)
+#if (USB_CACHE_LINESIZE > USB_DATA_ALIGN)
+#define USB_DATA_ALIGN_SIZE USB_CACHE_LINESIZE
+#else
+#define USB_DATA_ALIGN_SIZE USB_DATA_ALIGN
+#endif
-#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) ((n + USB_DATA_ALIGN_SIZE - 1) & (~(USB_DATA_ALIGN_SIZE - 1)))
+#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) (((n) + USB_DATA_ALIGN_SIZE - 1U) & (~(USB_DATA_ALIGN_SIZE - 1U)))
#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL)
@@ -387,13 +408,19 @@ _Pragma("diag_suppress=Pm120")
#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
(defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
-#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data)
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
#else
#define USB_DMA_DATA_NONINIT_SUB
#define USB_DMA_DATA_INIT_SUB
#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL
#endif
+#endif
#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT)
@@ -403,7 +430,13 @@ _Pragma("diag_suppress=Pm120")
(defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA
#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
-#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data)
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
+#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
#else
#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS
@@ -411,6 +444,7 @@ _Pragma("diag_suppress=Pm120")
#define USB_DMA_DATA_INIT_SUB
#define USB_CONTROLLER_DATA
#endif
+#endif
#else
@@ -420,9 +454,17 @@ _Pragma("diag_suppress=Pm120")
#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA
#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA
#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
-#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data)
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
+#else
+
+#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
+#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
+#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
+#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
#else
#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS
#define USB_BDT USB_LINK_USB_BDT_BSS
@@ -433,6 +475,8 @@ _Pragma("diag_suppress=Pm120")
#endif
+#endif
+
#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB
#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB
@@ -449,4 +493,4 @@ _Pragma("diag_suppress=Pm120")
/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */
/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */
-#endif /* __USB_MISC_H__ */
+#endif /* __USB_MISC_H__ */
\ No newline at end of file
diff --git a/bsp/lpc54114-lite/applications/mnt.c b/bsp/lpc54114-lite/applications/mnt.c
index 49852b2025..f67c5c21ea 100644
--- a/bsp/lpc54114-lite/applications/mnt.c
+++ b/bsp/lpc54114-lite/applications/mnt.c
@@ -11,7 +11,10 @@
#if defined(RT_USING_DFS)
#include
-#include
+#include
+#include
+#include
+#include
#endif
#define BSP_FLASH_MOUNT_PATH "/mnt/flash"
diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config
index 2e2dcca70b..a273e07a43 100644
--- a/bsp/ls2kdev/.config
+++ b/bsp/ls2kdev/.config
@@ -264,8 +264,7 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=8
@@ -501,6 +500,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -511,7 +511,6 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -562,6 +561,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -673,6 +673,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -760,6 +761,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
CONFIG_SOC_LS2K1000=y
CONFIG_RT_USING_UART0=y
# CONFIG_RT_USING_UART4 is not set
diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h
index dceb19ed54..27fd9b0766 100644
--- a/bsp/ls2kdev/rtconfig.h
+++ b/bsp/ls2kdev/rtconfig.h
@@ -151,7 +151,7 @@
/* light weight TCP/IP stack */
#define RT_USING_LWIP
-#define RT_USING_LWIP202
+#define RT_USING_LWIP203
#define RT_LWIP_MEM_ALIGNMENT 8
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
diff --git a/bsp/mini4020/applications/application.c b/bsp/mini4020/applications/application.c
index f5a77d8c60..722443ac7c 100644
--- a/bsp/mini4020/applications/application.c
+++ b/bsp/mini4020/applications/application.c
@@ -22,7 +22,11 @@
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#endif
#ifdef RT_USING_RTGUI
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c
index 8223a54e6a..992af05e52 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_adc.c
@@ -124,9 +124,9 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
ADC_InitStructure.ChsNumber = 1;
ADC_Init(n32_adc_handler, &ADC_InitStructure);
- if (((n32_adc_handler == ADC2) || (n32_adc_handler == ADC2))
- && ((n32_adc_get_channel(channel) == ADC_CH_16)
- || (n32_adc_get_channel(channel) == ADC_CH_18)))
+ if (((n32_adc_handler == ADC1) || (n32_adc_handler == ADC2))
+ && ((n32_adc_get_channel(channel) == ADC_CH_16)
+ || (n32_adc_get_channel(channel) == ADC_CH_18)))
{
ADC_EnableTempSensorVrefint(ENABLE);
}
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
index 56cdfadf6c..eece7aa780 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
@@ -15,14 +15,16 @@
#ifdef RT_USING_PIN
-#define N32G45X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
+#ifndef N32G45X_PIN_NUMBERS
+ #define N32G45X_PIN_NUMBERS 64//[48, 64, 80, 100, 128 ]
+#endif
#define __N32_PIN(index, rcc, gpio, gpio_index) \
{ \
0, RCC_##rcc##_PERIPH_GPIO##gpio, GPIO##gpio, GPIO_PIN_##gpio_index \
-, GPIO##gpio##_PORT_SOURCE, GPIO_PIN_SOURCE##gpio_index \
+, GPIO##gpio##_PORT_SOURCE, GPIO_PIN_SOURCE##gpio_index, "P" #gpio "." #gpio_index \
}
-#define __N32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0}
+#define __N32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0, ""}
/* N32 GPIO driver */
struct pin_index
@@ -33,6 +35,7 @@ struct pin_index
uint32_t pin;
uint8_t port_source;
uint8_t pin_source;
+ const char* name;
};
static const struct pin_index pins[] =
@@ -87,16 +90,15 @@ static const struct pin_index pins[] =
__N32_PIN(46, APB2, B, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
-
-#endif
-#if (N32G45X_PIN_NUMBERS == 64)
+ #endif
+ #if (N32G45X_PIN_NUMBERS == 64)
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(2, APB2, C, 13),
__N32_PIN(3, APB2, C, 14),
__N32_PIN(4, APB2, C, 15),
- __N32_PIN(5, APB2, D, 0),
- __N32_PIN(6, APB2, D, 1),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN(8, APB2, C, 0),
__N32_PIN(9, APB2, C, 1),
@@ -155,6 +157,89 @@ static const struct pin_index pins[] =
__N32_PIN(62, APB2, B, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
+ #endif
+ #if (N32G45X_PIN_NUMBERS == 80)
+ __N32_PIN_DEFAULT,
+ __N32_PIN(1, APB2, E, 2),
+ __N32_PIN(2, APB2, E, 3),
+ __N32_PIN_DEFAULT,
+ __N32_PIN(4, APB2, C, 13),
+ __N32_PIN(5, APB2, C, 14),
+ __N32_PIN(6, APB2, C, 15),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
+ __N32_PIN(10, APB2, C, 0),
+ __N32_PIN(11, APB2, C, 1),
+ __N32_PIN(12, APB2, C, 2),
+ __N32_PIN(13, APB2, C, 3),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
+ __N32_PIN(16, APB2, A, 0),
+ __N32_PIN(17, APB2, A, 1),
+ __N32_PIN(18, APB2, A, 2),
+ __N32_PIN(19, APB2, A, 3),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
+ __N32_PIN(22, APB2, A, 4),
+ __N32_PIN(23, APB2, A, 5),
+ __N32_PIN(24, APB2, A, 6),
+ __N32_PIN(25, APB2, A, 7),
+ __N32_PIN(26, APB2, C, 4),
+ __N32_PIN(27, APB2, C, 5),
+ __N32_PIN(28, APB2, B, 0),
+ __N32_PIN(29, APB2, B, 1),
+ __N32_PIN(30, APB2, B, 2),
+ __N32_PIN(31, APB2, E, 7),
+ __N32_PIN(32, APB2, E, 8),
+ __N32_PIN(33, APB2, E, 9),
+ __N32_PIN(34, APB2, E, 10),
+ __N32_PIN(35, APB2, E, 11),
+ __N32_PIN(36, APB2, E, 12),
+ __N32_PIN(37, APB2, E, 13),
+ __N32_PIN(38, APB2, B, 10),
+ __N32_PIN(39, APB2, B, 11),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
+ __N32_PIN(42, APB2, B, 12),
+ __N32_PIN(43, APB2, B, 13),
+ __N32_PIN(44, APB2, B, 14),
+ __N32_PIN(45, APB2, B, 15),
+ __N32_PIN(46, APB2, D, 8),
+ __N32_PIN(47, APB2, D, 9),
+ __N32_PIN(48, APB2, D, 10),
+ __N32_PIN(49, APB2, D, 14),
+ __N32_PIN(50, APB2, D, 15),
+ __N32_PIN(51, APB2, C, 6),
+ __N32_PIN(52, APB2, C, 7),
+ __N32_PIN(53, APB2, C, 8),
+ __N32_PIN(54, APB2, C, 9),
+ __N32_PIN(55, APB2, A, 8),
+ __N32_PIN(56, APB2, A, 9),
+ __N32_PIN(57, APB2, A, 10),
+ __N32_PIN(58, APB2, A, 11),
+ __N32_PIN(59, APB2, A, 12),
+ __N32_PIN(60, APB2, A, 13),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
+ __N32_PIN(63, APB2, A, 14),
+ __N32_PIN(64, APB2, A, 15),
+ __N32_PIN(65, APB2, C, 10),
+ __N32_PIN(66, APB2, C, 11),
+ __N32_PIN(67, APB2, C, 12),
+ __N32_PIN(68, APB2, D, 0),
+ __N32_PIN(69, APB2, D, 1),
+ __N32_PIN(70, APB2, D, 2),
+ __N32_PIN(71, APB2, B, 3),
+ __N32_PIN(72, APB2, B, 4),
+ __N32_PIN(73, APB2, B, 5),
+ __N32_PIN(74, APB2, B, 6),
+ __N32_PIN(75, APB2, B, 7),
+ __N32_PIN_DEFAULT,
+ __N32_PIN(77, APB2, B, 8),
+ __N32_PIN(78, APB2, B, 9),
+ __N32_PIN_DEFAULT,
+ __N32_PIN_DEFAULT,
#endif
#if (N32G45X_PIN_NUMBERS == 100)
__N32_PIN_DEFAULT,
@@ -258,8 +343,8 @@ static const struct pin_index pins[] =
__N32_PIN(98, APB2, E, 1),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
-#endif
-#if (N32G45X_PIN_NUMBERS == 144)
+ #endif
+ #if (N32G45X_PIN_NUMBERS == 128)
__N32_PIN_DEFAULT,
__N32_PIN(1, APB2, E, 2),
__N32_PIN(2, APB2, E, 3),
@@ -270,7 +355,6 @@ static const struct pin_index pins[] =
__N32_PIN(7, APB2, C, 13),
__N32_PIN(8, APB2, C, 14),
__N32_PIN(9, APB2, C, 15),
-
__N32_PIN(10, APB2, F, 0),
__N32_PIN(11, APB2, F, 1),
__N32_PIN(12, APB2, F, 2),
@@ -279,131 +363,115 @@ static const struct pin_index pins[] =
__N32_PIN(15, APB2, F, 5),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(18, APB2, F, 6),
- __N32_PIN(19, APB2, F, 7),
- __N32_PIN(20, APB2, F, 8),
- __N32_PIN(21, APB2, F, 9),
- __N32_PIN(22, APB2, F, 10),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(26, APB2, C, 0),
- __N32_PIN(27, APB2, C, 1),
- __N32_PIN(28, APB2, C, 2),
- __N32_PIN(29, APB2, C, 3),
+ __N32_PIN(21, APB2, C, 0),
+ __N32_PIN(22, APB2, C, 1),
+ __N32_PIN(23, APB2, C, 2),
+ __N32_PIN(24, APB2, C, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(34, APB2, A, 0),
- __N32_PIN(35, APB2, A, 1),
- __N32_PIN(36, APB2, A, 2),
- __N32_PIN(37, APB2, A, 3),
+ __N32_PIN(29, APB2, A, 0),
+ __N32_PIN(30, APB2, A, 1),
+ __N32_PIN(31, APB2, A, 2),
+ __N32_PIN(32, APB2, A, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(40, APB2, A, 4),
- __N32_PIN(41, APB2, A, 5),
- __N32_PIN(42, APB2, A, 6),
- __N32_PIN(43, APB2, A, 7),
- __N32_PIN(44, APB2, C, 4),
- __N32_PIN(45, APB2, C, 5),
- __N32_PIN(46, APB2, B, 0),
- __N32_PIN(47, APB2, B, 1),
- __N32_PIN(48, APB2, B, 2),
- __N32_PIN(49, APB2, F, 11),
- __N32_PIN(50, APB2, F, 12),
+ __N32_PIN(35, APB2, A, 4),
+ __N32_PIN(36, APB2, A, 5),
+ __N32_PIN(37, APB2, A, 6),
+ __N32_PIN(38, APB2, A, 7),
+ __N32_PIN(39, APB2, C, 4),
+ __N32_PIN(40, APB2, C, 5),
+ __N32_PIN(41, APB2, B, 0),
+ __N32_PIN(42, APB2, B, 1),
+ __N32_PIN(43, APB2, B, 2),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(53, APB2, F, 13),
- __N32_PIN(54, APB2, F, 14),
- __N32_PIN(55, APB2, F, 15),
- __N32_PIN(56, APB2, G, 0),
- __N32_PIN(57, APB2, G, 1),
- __N32_PIN(58, APB2, E, 7),
- __N32_PIN(59, APB2, E, 8),
- __N32_PIN(60, APB2, E, 9),
+ __N32_PIN(46, APB2, F, 12),
+ __N32_PIN(47, APB2, F, 13),
+ __N32_PIN(48, APB2, F, 14),
+ __N32_PIN(49, APB2, F, 15),
+ __N32_PIN(50, APB2, E, 7),
+ __N32_PIN(51, APB2, E, 8),
+ __N32_PIN(52, APB2, E, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(63, APB2, E, 10),
- __N32_PIN(64, APB2, E, 11),
- __N32_PIN(65, APB2, E, 12),
- __N32_PIN(66, APB2, E, 13),
- __N32_PIN(67, APB2, E, 14),
- __N32_PIN(68, APB2, E, 15),
- __N32_PIN(69, APB2, B, 10),
- __N32_PIN(70, APB2, B, 11),
+ __N32_PIN(55, APB2, E, 10),
+ __N32_PIN(56, APB2, E, 11),
+ __N32_PIN(57, APB2, E, 12),
+ __N32_PIN(58, APB2, E, 13),
+ __N32_PIN(59, APB2, E, 14),
+ __N32_PIN(60, APB2, E, 15),
+ __N32_PIN(61, APB2, B, 10),
+ __N32_PIN(62, APB2, B, 11),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(73, APB2, B, 12),
- __N32_PIN(74, APB2, B, 13),
- __N32_PIN(75, APB2, B, 14),
- __N32_PIN(76, APB2, B, 15),
- __N32_PIN(77, APB2, D, 8),
- __N32_PIN(78, APB2, D, 9),
- __N32_PIN(79, APB2, D, 10),
- __N32_PIN(80, APB2, D, 11),
- __N32_PIN(81, APB2, D, 12),
- __N32_PIN(82, APB2, D, 13),
+ __N32_PIN(65, APB2, B, 12),
+ __N32_PIN(66, APB2, B, 13),
+ __N32_PIN(67, APB2, B, 14),
+ __N32_PIN(68, APB2, B, 15),
+ __N32_PIN(69, APB2, D, 8),
+ __N32_PIN(70, APB2, D, 9),
+ __N32_PIN(71, APB2, D, 10),
+ __N32_PIN(72, APB2, D, 11),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(85, APB2, D, 14),
- __N32_PIN(86, APB2, D, 15),
- __N32_PIN(87, APB2, G, 2),
- __N32_PIN(88, APB2, G, 3),
- __N32_PIN(89, APB2, G, 4),
- __N32_PIN(90, APB2, G, 5),
- __N32_PIN(91, APB2, G, 6),
- __N32_PIN(92, APB2, G, 7),
- __N32_PIN(93, APB2, G, 8),
+ __N32_PIN(75, APB2, D, 12),
+ __N32_PIN(76, APB2, D, 13),
+ __N32_PIN(77, APB2, D, 14),
+ __N32_PIN(78, APB2, D, 15),
+ __N32_PIN(79, APB2, G, 0),
+ __N32_PIN(80, APB2, G, 1),
+ __N32_PIN(81, APB2, G, 2),
+ __N32_PIN(82, APB2, G, 3),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(96, APB2, C, 6),
- __N32_PIN(97, APB2, C, 7),
- __N32_PIN(98, APB2, C, 8),
- __N32_PIN(99, APB2, C, 9),
- __N32_PIN(100, APB2, A, 8),
- __N32_PIN(101, APB2, A, 9),
- __N32_PIN(102, APB2, A, 10),
- __N32_PIN(103, APB2, A, 11),
- __N32_PIN(104, APB2, A, 12),
- __N32_PIN(105, APB2, A, 13),
+ __N32_PIN(85, APB2, C, 6),
+ __N32_PIN(86, APB2, C, 7),
+ __N32_PIN(87, APB2, C, 8),
+ __N32_PIN(88, APB2, C, 9),
+ __N32_PIN(89, APB2, A, 8),
+ __N32_PIN(90, APB2, A, 9),
+ __N32_PIN(91, APB2, A, 10),
+ __N32_PIN(92, APB2, A, 11),
+ __N32_PIN(93, APB2, A, 12),
+ __N32_PIN(94, APB2, A, 13),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN_DEFAULT,
- __N32_PIN(109, APB2, A, 14),
- __N32_PIN(110, APB2, A, 15),
- __N32_PIN(111, APB2, C, 10),
- __N32_PIN(112, APB2, C, 11),
- __N32_PIN(113, APB2, C, 12),
- __N32_PIN(114, APB2, D, 0),
- __N32_PIN(115, APB2, D, 1),
- __N32_PIN(116, APB2, D, 2),
- __N32_PIN(117, APB2, D, 3),
- __N32_PIN(118, APB2, D, 4),
- __N32_PIN(119, APB2, D, 5),
+ __N32_PIN(97, APB2, A, 14),
+ __N32_PIN(98, APB2, A, 15),
+ __N32_PIN(99, APB2, C, 10),
+ __N32_PIN(100, APB2, C, 11),
+ __N32_PIN(101, APB2, C, 12),
+ __N32_PIN(102, APB2, D, 0),
+ __N32_PIN(103, APB2, D, 1),
+ __N32_PIN(104, APB2, D, 2),
+ __N32_PIN(105, APB2, D, 3),
+ __N32_PIN(106, APB2, D, 4),
+ __N32_PIN(107, APB2, D, 5),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(122, APB2, D, 6),
- __N32_PIN(123, APB2, D, 7),
- __N32_PIN(124, APB2, G, 9),
- __N32_PIN(125, APB2, G, 10),
- __N32_PIN(126, APB2, G, 11),
- __N32_PIN(127, APB2, G, 12),
- __N32_PIN(128, APB2, G, 13),
- __N32_PIN(129, APB2, G, 14),
+ __N32_PIN(110, APB2, D, 6),
+ __N32_PIN(111, APB2, D, 7),
+ __N32_PIN(112, APB2, G, 4),
+ __N32_PIN(113, APB2, G, 5),
+ __N32_PIN(114, APB2, G, 9),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
- __N32_PIN(132, APB2, G, 15),
- __N32_PIN(133, APB2, B, 3),
- __N32_PIN(134, APB2, B, 4),
- __N32_PIN(135, APB2, B, 5),
- __N32_PIN(136, APB2, B, 6),
- __N32_PIN(137, APB2, B, 7),
+ __N32_PIN(117, APB2, B, 3),
+ __N32_PIN(118, APB2, B, 4),
+ __N32_PIN(119, APB2, B, 5),
+ __N32_PIN(120, APB2, B, 6),
+ __N32_PIN(121, APB2, B, 7),
__N32_PIN_DEFAULT,
- __N32_PIN(139, APB2, B, 8),
- __N32_PIN(140, APB2, B, 9),
- __N32_PIN(141, APB2, E, 0),
- __N32_PIN(142, APB2, E, 1),
+ __N32_PIN(123, APB2, B, 8),
+ __N32_PIN(124, APB2, B, 9),
+ __N32_PIN(125, APB2, E, 0),
+ __N32_PIN(126, APB2, E, 1),
__N32_PIN_DEFAULT,
__N32_PIN_DEFAULT,
#endif
@@ -473,6 +541,23 @@ const struct pin_index *get_pin(uint8_t pin)
return index;
};
+rt_base_t n32_pin_get(const char *name)
+{
+ rt_base_t i;
+
+ for (i = 0; i < ITEM_NUM(pins); i++)
+ {
+ if (rt_strcmp(pins[i].name, name) == 0)
+ {
+ /* in get_pin function, use pin parameter as index of pins array */
+ return i;
+ }
+ }
+
+ /* refers content of pins array, map to __N32_PIN_DEFAULT */
+ return 0;
+}
+
void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
@@ -754,6 +839,7 @@ const static struct rt_pin_ops _n32_pin_ops =
n32_pin_attach_irq,
n32_pin_dettach_irq,
n32_pin_irq_enable,
+ n32_pin_get
};
int n32_hw_pin_init(void)
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
index 99fd087498..a5dadf573d 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
@@ -212,10 +212,6 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration
rt_uint64_t psc;
rt_uint32_t pulse;
- /* Init timer pin and enable clock */
- void n32_msp_tim_init(void *Instance);
- n32_msp_tim_init(TIMx);
-
RCC_ClocksType RCC_Clock;
RCC_GetClocksFreqValue(&RCC_Clock);
rt_uint64_t input_clock;
@@ -332,6 +328,9 @@ static int rt_hw_pwm_init(void)
if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device,
n32_pwm_obj[i].name, &drv_ops, &(n32_pwm_obj[i])) == RT_EOK)
{
+ /* Init timer pin and enable clock */
+ void n32_msp_tim_init(void *Instance);
+ n32_msp_tim_init(n32_pwm_obj[i].tim_handle);
}
else
{
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
index 98e0193a77..2f15585970 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
@@ -477,6 +477,76 @@ void DMA1_Channel8_IRQHandler(void)
}
#endif /* BSP_USING_UART5 */
+#if defined(BSP_USING_UART6)
+/* UART6 device driver structure */
+struct n32_uart uart6 =
+{
+ UART6,
+ UART6_IRQn,
+ {
+ DMA2_CH1,
+ DMA2,
+ DMA2_FLAG_GL1,
+ DMA2_Channel1_IRQn,
+ 0,
+ },
+};
+struct rt_serial_device serial6;
+
+void UART6_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ uart_isr(&serial6);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void DMA2_Channel1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ dma_rx_done_isr(&serial6);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+/* UART7 device driver structure */
+struct n32_uart uart7 =
+{
+ UART7,
+ UART7_IRQn,
+ {
+ DMA2_CH6,
+ DMA2,
+ DMA2_FLAG_GL6,
+ DMA2_Channel6_IRQn,
+ 0,
+ },
+};
+struct rt_serial_device serial7;
+
+void UART7_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ uart_isr(&serial7);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void DMA2_Channel6_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+ dma_rx_done_isr(&serial7);
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART7 */
+
static void NVIC_Configuration(struct n32_uart *uart)
{
NVIC_InitType NVIC_InitStructure;
@@ -582,7 +652,7 @@ int rt_hw_usart_init(void)
/* register UART3 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
- RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
+ RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
uart);
#endif /* BSP_USING_UART3 */
@@ -592,7 +662,7 @@ int rt_hw_usart_init(void)
serial4.ops = &n32_uart_ops;
serial4.config = config;
NVIC_Configuration(uart);
- /* register UART3 device */
+ /* register UART4 device */
rt_hw_serial_register(&serial4, "uart4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
@@ -605,12 +675,40 @@ int rt_hw_usart_init(void)
serial5.ops = &n32_uart_ops;
serial5.config = config;
NVIC_Configuration(uart);
- /* register UART3 device */
+ /* register UART5 device */
rt_hw_serial_register(&serial5, "uart5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
uart);
#endif /* BSP_USING_UART5 */
+
+ #if defined(BSP_USING_UART6)
+ uart = &uart6;
+ config.baud_rate = BAUD_RATE_115200;
+ serial6.ops = &n32_uart_ops;
+ serial6.config = config;
+ NVIC_Configuration(uart);
+ /* register UART6 device */
+ rt_hw_serial_register(&serial6, "uart6",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+ RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
+ uart);
+ #endif /* BSP_USING_UART6 */
+
+ #if defined(BSP_USING_UART7)
+ uart = &uart7;
+ config.baud_rate = BAUD_RATE_115200;
+ serial7.ops = &n32_uart_ops;
+ serial7.config = config;
+ NVIC_Configuration(uart);
+ /* register UART7 device */
+ rt_hw_serial_register(&serial7, "uart7",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+ RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
+ uart);
+ #endif /* BSP_USING_UART7 */
+
+
return RT_EOK;
}
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/.config b/bsp/n32g452xx/n32g452xx-mini-system/.config
index 9921e8b35d..d987bd9b79 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/.config
+++ b/bsp/n32g452xx/n32g452xx-mini-system/.config
@@ -139,16 +139,16 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
-CONFIG_RT_USING_ADC=y
+# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
-CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
-CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
@@ -292,7 +292,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@@ -326,14 +325,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
-# CONFIG_PKG_USING_SMALL_MODBUS is not set
-# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
@@ -341,7 +338,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# language packages
#
-# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
@@ -354,15 +350,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# LVGL: powerful and easy-to-use embedded GUI library
#
-# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
-
-#
-# u8g2: a monochrome graphic library
-#
-# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
-# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
@@ -378,13 +367,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_UGUI is not set
#
-# PainterEngine: A cross-platform graphics application framework written in C language
+# u8g2: a monochrome graphic library
#
-# CONFIG_PKG_USING_PAINTERENGINE is not set
-# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
-# CONFIG_PKG_USING_MCURSES is not set
-# CONFIG_PKG_USING_TERMBOX is not set
-# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
#
# tools packages
@@ -427,39 +413,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
-# CONFIG_PKG_USING_FDT is not set
#
# system packages
#
-#
-# enhanced kernel services
-#
-# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
-# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
-# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
-
-#
-# POSIX extension functions
-#
-# CONFIG_PKG_USING_POSIX_GETLINE is not set
-# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
-# CONFIG_PKG_USING_POSIX_ITOA is not set
-
#
# acceleration: Assembly language or algorithmic acceleration packages
#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
-#
-# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
-#
-# CONFIG_PKG_USING_CMSIS_5 is not set
-# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
-
#
# Micrium: Micrium software products porting for RT-Thread
#
@@ -469,7 +435,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
-# CONFIG_RT_USING_ARDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@@ -478,6 +443,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
@@ -494,13 +460,14 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
-# CONFIG_PKG_USING_USB_STACK is not set
#
# peripheral libraries and drivers
@@ -574,11 +541,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
-# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
-# CONFIG_PKG_USING_MB85RS16 is not set
-# CONFIG_PKG_USING_CW2015 is not set
#
# AI packages
@@ -617,7 +581,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
-# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@@ -639,11 +602,14 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
-# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
#
# Hardware Drivers Config
@@ -658,14 +624,31 @@ CONFIG_BSP_USING_UART=y
#
# On-chip Peripheral Drivers
#
+# CONFIG_N32G45X_PIN_NUMBERS_48 is not set
+CONFIG_N32G45X_PIN_NUMBERS_64=y
+# CONFIG_N32G45X_PIN_NUMBERS_100 is not set
+# CONFIG_N32G45X_PIN_NUMBERS_128 is not set
+CONFIG_N32G45X_PIN_NUMBERS=64
CONFIG_BSP_USING_GPIO=y
+
+#
+# Remap JTAG Port
+#
+# CONFIG_BSP_RMP_SW_JTAG_FULL_ENABLE is not set
+# CONFIG_BSP_RMP_SW_JTAG_NO_NJTRST is not set
+CONFIG_BSP_RMP_SW_JTAG_SW_ENABLE=y
+# CONFIG_BSP_RMP_SW_JTAG_DISABLE is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART1_PIN_RMP is not set
+CONFIG_BSP_USING_UART1_NO_RMP=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_HWTIMER is not set
# CONFIG_BSP_USING_SPI is not set
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c b/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c
index 11fdf6f84b..fcb0110413 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c
+++ b/bsp/n32g452xx/n32g452xx-mini-system/applications/main.c
@@ -12,19 +12,24 @@
#include
/* defined the LED1 pin: PB5 */
-#define LED1_PIN 57
+#define LED1_NAME "PB.5"
+rt_base_t led1_pin;
int main(void)
{
uint32_t Speed = 200;
+
+ /* get LED1 pin id by name */
+ led1_pin = rt_pin_get(LED1_NAME);
+
/* set LED1 pin mode to output */
- rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+ rt_pin_mode(led1_pin, PIN_MODE_OUTPUT);
while (1)
{
- rt_pin_write(LED1_PIN, PIN_LOW);
+ rt_pin_write(led1_pin, PIN_LOW);
rt_thread_mdelay(Speed);
- rt_pin_write(LED1_PIN, PIN_HIGH);
+ rt_pin_write(led1_pin, PIN_HIGH);
rt_thread_mdelay(Speed);
}
}
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
index 0b77f8ca90..59a042bf99 100755
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
@@ -19,10 +19,49 @@ endmenu
menu "On-chip Peripheral Drivers"
+ choice
+ prompt "Package of N32G45NXX chip:"
+ default N32G45X_PIN_NUMBERS_64
+ config N32G45X_PIN_NUMBERS_48
+ bool "LQFP48/TQFP48(QFN48 is not supported.)"
+ config N32G45X_PIN_NUMBERS_64
+ bool "LQFP64"
+ config N32G45X_PIN_NUMBERS_100
+ bool "LQFP100"
+ config N32G45X_PIN_NUMBERS_128
+ bool "LQFP128"
+ endchoice
+
+ config N32G45X_PIN_NUMBERS
+ int
+ range 0 128
+ default 48 if N32G45X_PIN_NUMBERS_48
+ default 64 if N32G45X_PIN_NUMBERS_64
+ default 100 if N32G45X_PIN_NUMBERS_100
+ default 128 if N32G45X_PIN_NUMBERS_128
+
+
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
+ if BSP_USING_GPIO
+
+ menu "Remap JTAG Port"
+ choice
+ prompt "Remap JTAG Port"
+ default BSP_RMP_SW_JTAG_SW_ENABLE
+ config BSP_RMP_SW_JTAG_FULL_ENABLE
+ bool "Full SWJ Enabled (JTAG-DP+SW-DP). No GPIO available."
+ config BSP_RMP_SW_JTAG_NO_NJTRST
+ bool "Full SWJ Enabled (JTAG-DP+SW-DP) without JTRST. PB4 available."
+ config BSP_RMP_SW_JTAG_SW_ENABLE
+ bool "JTAG-DP Disabled and SW-DP Enabled. PA15,PB3,PB4 available."
+ config BSP_RMP_SW_JTAG_DISABLE
+ bool "Full SWJ Disabled (JTAG-DP+SW-DP). PA13,PA14,PA15,PB3,PB4 available."
+ endchoice
+ endmenu
+ endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
@@ -39,25 +78,121 @@ menu "On-chip Peripheral Drivers"
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
- bool "Enable UART1"
+ bool "Enable USART1"
default y
+ if BSP_USING_UART1
+ choice
+ prompt "Select TX/RX Pin of USART1"
+ default BSP_USING_UART1_NO_RMP
+ config BSP_USING_UART1_PIN_RMP
+ bool "USART1(Remap):(TX:PB6,RX:PB7)"
+ config BSP_USING_UART1_NO_RMP
+ bool "USART1(Default):(TX:PA9,RX:PA10)"
+ endchoice
+ endif
config BSP_USING_UART2
- bool "Enable UART2"
+ bool "Enable USART2"
default n
+ if BSP_USING_UART2
+ choice
+ prompt "Select TX/RX Pin of USART2"
+ default BSP_USING_UART2_NO_RMP
+ config BSP_USING_UART2_NO_RMP
+ bool "USART2(Default):(TX:PA2, RX:PA3)"
+ config BSP_USING_UART2_PIN_RMP1
+ bool "USART2:(TX:PD5, RX:PD6)"
+ config BSP_USING_UART2_PIN_RMP2
+ bool "USART2:(TX:PC8, RX:PC9)"
+ config BSP_USING_UART2_PIN_RMP3
+ bool "USART2:(TX:PB4, RX:PB5)"
+ endchoice
+ endif
+
config BSP_USING_UART3
- bool "Enable UART3"
+ bool "Enable USART3"
default n
+ if BSP_USING_UART3
+ choice
+ prompt "Select TX/RX Pin of USART3"
+ default BSP_USING_UART3_PIN_NO_RMP
+ config BSP_USING_UART3_PIN_NO_RMP
+ bool "USART3:Default (TX:PB10, RX:PB11)"
+ config BSP_USING_UART3_PIN_PART_RMP
+ bool "USART3:Partial remap (TX:PC10, RX:PC11)"
+ config BSP_USING_UART3_PIN_ALL_RMP
+ bool "USART3:Full remap (TX:PD8, RX:PD9)"
+ endchoice
+ endif
config BSP_USING_UART4
bool "Enable UART4"
default n
+ if BSP_USING_UART4
+ choice
+ prompt "Select TX/RX Pin of UART4"
+ default BSP_USING_UART4_PIN_NORMP
+ config BSP_USING_UART4_PIN_NORMP
+ bool "UART4(Default):TX:PC10, RX:PC11"
+ config BSP_USING_UART4_PIN_RMP1
+ bool "UART4:TX:PB2, RX:PE7"
+ config BSP_USING_UART4_PIN_RMP2
+ bool "UART4:TX:PA13, RX:PA14"
+ config BSP_USING_UART4_PIN_RMP3
+ bool "UART4:TX:PD0, RX:PD1"
+ endchoice
+ endif
config BSP_USING_UART5
bool "Enable UART5"
default n
-
+ if BSP_USING_UART5
+ choice
+ prompt "Select TX/RX Pin of UART5"
+ default BSP_USING_UART5_PIN_NORMP
+ config BSP_USING_UART5_PIN_NORMP
+ bool "UART5(Default):TX:PC12, RX:PD2"
+ config BSP_USING_UART5_PIN_RMP1
+ bool "UART5:TX:PB13, RX:PB14"
+ config BSP_USING_UART5_PIN_RMP2
+ bool "UART5:TX:PE8, RX:PE9"
+ config BSP_USING_UART5_PIN_RMP3
+ bool "UART5:TX:PB8, RX:PB9"
+ endchoice
+ endif
+
+ config BSP_USING_UART6
+ bool "Enable UART6"
+ default n
+ if BSP_USING_UART6
+ choice
+ prompt "Select TX/RX Pin of UART6"
+ default BSP_USING_UART6_PIN_NORMP
+ config BSP_USING_UART6_PIN_NORMP
+ bool "UART6(Default):TX:PE2, RX:PE3"
+ config BSP_USING_UART6_PIN_RMP2
+ bool "UART6:TX:PC0, RX:PC1"
+ config BSP_USING_UART6_PIN_RMP3
+ bool "UART6:TX:PB0, RX:PB1"
+ endchoice
+ endif
+
+ config BSP_USING_UART7
+ bool "Enable UART7"
+ default n
+ if BSP_USING_UART7
+ choice
+ prompt "Select TX/RX Pin of UART7"
+ default BSP_USING_UART7_PIN_NORMP
+ config BSP_USING_UART7_PIN_NORMP
+ bool "UART7(Default):TX:PC4, RX:PC5"
+ config BSP_USING_UART7_PIN_RMP1
+ bool "UART7:TX:PC2, RX:PC3"
+ config BSP_USING_UART7_PIN_RMP3
+ bool "UART7:TX:PG0, RX:PG1"
+ endchoice
+ endif
endif
menuconfig BSP_USING_PWM
@@ -213,13 +348,13 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
- int "i2c1 scl pin number"
- range 0 63
- default 22
+ int "I2C1 scl pin number"
+ range 1 N32G45X_PIN_NUMBERS
+ default 29
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
- range 0 63
- default 23
+ range 1 N32G45X_PIN_NUMBERS
+ default 30
endif
menuconfig BSP_USING_ADC
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c
index ca6e55fb4e..9048415752 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c
@@ -76,6 +76,7 @@ void rt_hw_board_init()
#ifdef RT_USING_PIN
int n32_hw_pin_init(void);
n32_hw_pin_init();
+ n32_msp_jtag_init(RT_NULL);
#endif
#ifdef RT_USING_SERIAL
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/board.h b/bsp/n32g452xx/n32g452xx-mini-system/board/board.h
index 0a3b0fa661..fd5fa543f4 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/board.h
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/board.h
@@ -25,7 +25,7 @@ extern "C" {
#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
/* Internal SRAM memory size[Kbytes] <80>, Default: 80*/
-#define N32_SRAM_SIZE (80)
+#define N32_SRAM_SIZE (144)
#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
#if defined(__ARMCC_VERSION)
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
index bd79fbd756..84ff210461 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
@@ -27,58 +27,283 @@ void n32_msp_usart_init(void *Instance)
if (USART1 == USARTx)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
+#ifdef BSP_USING_UART1_PIN_RMP
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP_USART1, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_6;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_7;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
-
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
- }
#endif
+ }
+
+#endif /* BSP_USING_UART1 */
#ifdef BSP_USING_UART2
+
if (USART2 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
+#ifdef BSP_USING_UART2_PIN_RMP1
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP1_USART2, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_6;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+
+#elif defined (BSP_USING_UART2_PIN_RMP2)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMCP2_USART2, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+
+#elif defined (BSP_USING_UART2_PIN_RMP3)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP3_USART2, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+
+#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
-
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
- }
#endif
+ }
+
+#endif /* BSP_USING_UART2 */
#ifdef BSP_USING_UART3
+
if (USART3 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
+#if defined(BSP_USING_UART3_PIN_PART_RMP)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_PART_RMP_USART3, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_11;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART3_PIN_ALL_RMP)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_ALL_RMP_USART3, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+#else
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
-
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_11;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
- }
#endif
+ }
+
+#endif /* BSP_USING_UART3 */
#ifdef BSP_USING_UART4
+
if (UART4 == USARTx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE);
- RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+#if defined(BSP_USING_UART4_PIN_RMP1)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP1_UART4, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_GPIOE, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_7;
+ GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART4_PIN_RMP2)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP2_UART4, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_14;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART4_PIN_RMP3)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP3_UART4, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+#else
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_10;
- GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
-
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitCtlStruct.Pin = GPIO_PIN_11;
- GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
- }
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
#endif
+ }
+
+#endif /* BSP_USING_UART4 */
+#ifdef BSP_USING_UART5
+
+ if (UART5 == USARTx)
+ {
+ RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE);
+#if defined(BSP_USING_UART5_PIN_RMP1)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP1_UART5, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_14;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART5_PIN_RMP2)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP2_UART5, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
+ GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
+ GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART5_PIN_RMP3)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP3_UART5, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_8;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_9;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+#else
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_GPIOD, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_12;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
+ GPIO_InitPeripheral(GPIOD, &GPIO_InitCtlStruct);
+#endif
+ }
+
+#endif /* BSP_USING_UART5 */
+#ifdef BSP_USING_UART6
+
+ if (UART6 == USARTx)
+ {
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART6, ENABLE);
+#if defined(BSP_USING_UART6_PIN_RMP2)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP2_UART6, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART6_PIN_RMP3)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP3_UART6, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+#else /* BSP_USING_UART6_PIN_NORMP */
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
+ GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
+ GPIO_InitPeripheral(GPIOE, &GPIO_InitCtlStruct);
+#endif
+ }
+
+#endif /* BSP_USING_UART6 */
+#ifdef BSP_USING_UART7
+
+ if (UART7 == USARTx)
+ {
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART7, ENABLE);
+#if defined(BSP_USING_UART7_PIN_RMP1)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP1_UART7, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_2;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+#elif defined(BSP_USING_UART7_PIN_RMP3)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP3_UART7, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_0;
+ GPIO_InitPeripheral(GPIOG, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
+ GPIO_InitPeripheral(GPIOG, &GPIO_InitCtlStruct);
+#else /* BSP_USING_UART7_PIN_NORMP */
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
+ GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
+#endif
+ }
+
+#endif /* BSP_USING_UART7 */
/* Add others */
}
#endif /* BSP_USING_SERIAL */
@@ -113,7 +338,6 @@ void n32_msp_spi_init(void *Instance)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
-
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitCtlStruct.Pin = GPIO_PIN_12;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
@@ -167,7 +391,7 @@ void n32_msp_tim_init(void *Instance)
{
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
- GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_11;
+ GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11;
GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
@@ -244,7 +468,7 @@ void n32_msp_adc_init(void *Instance)
/* Configure ADC Channel as analog input */
GPIO_InitCtlStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
- GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitCtlStruct.GPIO_Speed = GPIO_INPUT;
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
}
@@ -260,7 +484,7 @@ void n32_msp_adc_init(void *Instance)
/* Configure ADC Channel as analog input */
GPIO_InitCtlStruct.Pin = GPIO_PIN_1;
- GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitCtlStruct.GPIO_Speed = GPIO_INPUT;
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AIN;
GPIO_InitPeripheral(GPIOC, &GPIO_InitCtlStruct);
}
@@ -341,21 +565,73 @@ void n32_msp_can_init(void *Instance)
if (CAN2 == CANx)
{
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_CAN2, ENABLE);
- RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
- // GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitCtlStruct.Pin = GPIO_PIN_6;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
-
GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
- GPIO_InitCtlStruct.Pin = GPIO_PIN_5;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_12;
GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
}
#endif
}
#endif /* BSP_USING_CAN */
+void n32_msp_jtag_init(void *Instance)
+{
+ GPIO_InitType GPIO_InitCtlStruct;
+ GPIO_InitStruct(&GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Speed = GPIO_Speed_50MHz;
+#if defined(BSP_RMP_SW_JTAG_NO_NJTRST)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_NO_NJTRST, ENABLE);
+ /* Available pin: PB4 */
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+#elif defined(BSP_RMP_SW_JTAG_SW_ENABLE)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE);
+ /* Available pin: PB3, PB4, PA15 */
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_OD;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_4;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_15;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
+#elif defined(BSP_RMP_SW_JTAG_DISABLE)
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
+ GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_DISABLE, ENABLE);
+ /* Available pin: PB3, PB4, PA13, PA14, PA15 */
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+ RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_Out_OD;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_3;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GDPIO_InitCtlStruct.Pin = GPIO_PIN_4;
+ GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_13;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPD;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_14;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
+ GPIO_InitCtlStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_InitCtlStruct.Pin = GPIO_PIN_15;
+ GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStruct);
+#else
+ return;
+#endif
+}
+
+
#ifdef RT_USING_FINSH
#include
#if defined(BSP_USING_UART2) || defined(BSP_USING_UART3)
@@ -413,7 +689,7 @@ static int adc_vol_sample(int argc, char *argv[])
return RT_ERROR;
}
- for (int i = 6; i <= 9; ++i)
+ for (int i = 1; i <= 18; ++i)
{
ret = rt_adc_enable(adc_dev, i);
value = rt_adc_read(adc_dev, i);
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h
index b92c62a69f..5d911a9ca4 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h
@@ -18,6 +18,7 @@ void n32_msp_sdio_init(void *Instance);
void n32_msp_adc_init(void *Instance);
void n32_msp_hwtim_init(void *Instance);
void n32_msp_can_init(void *Instance);
+void n32_msp_jtag_init(void *Instance);
#endif /* __N32_MSP_H__ */
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
index 14a3c468b7..e191c2d43d 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
+++ b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
@@ -76,6 +76,12 @@
/* Device virtual file system */
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
/* Device Drivers */
@@ -85,9 +91,6 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_WDT
/* Using USB */
@@ -157,26 +160,14 @@
/* u8g2: a monochrome graphic library */
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
/* tools packages */
/* system packages */
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
/* acceleration: Assembly language or algorithmic acceleration packages */
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
/* Micrium: Micrium software products porting for RT-Thread */
@@ -204,7 +195,14 @@
/* On-chip Peripheral Drivers */
+#define N32G45X_PIN_NUMBERS_64
+#define N32G45X_PIN_NUMBERS 64
#define BSP_USING_GPIO
+
+/* Remap JTAG Port */
+
+#define BSP_RMP_SW_JTAG_SW_ENABLE
#define BSP_USING_UART1
+#define BSP_USING_UART1_NO_RMP
#endif
diff --git a/bsp/nrf5x/nrf52832/applications/mnt.c b/bsp/nrf5x/nrf52832/applications/mnt.c
index c7e4d10235..d4af1d2b6c 100644
--- a/bsp/nrf5x/nrf52832/applications/mnt.c
+++ b/bsp/nrf5x/nrf52832/applications/mnt.c
@@ -35,7 +35,11 @@
#endif
#include "fal.h"
-#include
+#include
+#include
+#include
+#include
+#include
#define LOG_TAG "drv.fs"
#define DBG_LVL DBG_LOG
diff --git a/bsp/nuvoton/libraries/m031/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m031/rtt_port/drv_i2c.c
index e507ca6cbe..7487414dec 100644
--- a/bsp/nuvoton/libraries/m031/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/m031/rtt_port/drv_i2c.c
@@ -90,7 +90,7 @@ static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u3
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
- switch (RT_I2C_DEV_CTRL_CLK)
+ switch (u32Cmd)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig b/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig
index bf7d2da98d..5d06999d6b 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig
@@ -470,6 +470,7 @@ config SOC_SERIES_M2354
menuconfig BSP_USING_SDH
bool "Enable Secure Digital Host Controller(SDH)"
select RT_USING_DFS
+ select DFS_USING_POSIX
if BSP_USING_SDH
config BSP_USING_SDH0
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c
index 614705fcc5..511fb592a2 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c
@@ -7,6 +7,7 @@
* Change Logs:
* Date Author Notes
* 2020-6-22 ChingI First version
+* 2022-1-8 Wayne Fix IE issue
*
******************************************************************************/
@@ -42,7 +43,7 @@ enum
#if defined(BSP_USING_CAN0)
CAN0_IDX,
#endif
- CAN_CNT,
+ CAN_CNT
};
/* Private Typedef --------------------------------------------------------------*/
@@ -50,9 +51,10 @@ struct nu_can
{
struct rt_can_device dev;
char *name;
- CAN_T *can_base;
- uint32_t can_rst;
- IRQn_Type can_irq_n;
+ CAN_T *base;
+ IRQn_Type irqn;
+ uint32_t rstidx;
+ uint32_t int_flag;
};
typedef struct nu_can *nu_can_t;
@@ -68,12 +70,11 @@ static struct nu_can nu_can_arr[] =
#if defined(BSP_USING_CAN0)
{
.name = "can0",
- .can_base = CAN0,
- .can_rst = CAN0_RST,
- .can_irq_n = CAN0_IRQn,
+ .base = CAN0,
+ .rstidx = CAN0_RST,
+ .irqn = CAN0_IRQn,
},
#endif
- {0}
}; /* struct nu_can */
/* Public functions ------------------------------------------------------------*/
@@ -106,266 +107,271 @@ void CAN0_IRQHandler(void)
/* Private Variables ------------------------------------------------------------*/
-static void nu_can_isr(nu_can_t can)
+static void nu_can_isr(nu_can_t psNuCAN)
{
- uint32_t u32IIDRstatus;
/* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
+ CAN_T *base = psNuCAN->base;
/* Get interrupt event */
- u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(can_base);
+ uint32_t u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(base) & CAN_IIDR_INTID_Msk;
- if (u32IIDRstatus == 0x00008000) /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ if (u32IIDRstatus == 0x00008000)
{
/**************************/
/* Status Change interrupt*/
/**************************/
- if (can_base->STATUS & CAN_STATUS_TXOK_Msk)
+ if (base->STATUS & CAN_STATUS_TXOK_Msk)
{
- can_base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
+ base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
+ }
#endif
- //rt_kprintf("[%s]TX OK INT\n", can->name) ;
}
- if (can_base->STATUS & CAN_STATUS_RXOK_Msk)
+ if (base->STATUS & CAN_STATUS_RXOK_Msk)
{
- can_base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
+ base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&can->dev, RT_CAN_EVENT_RX_IND);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_RX_IND);
+ }
#endif
- //rt_kprintf("[%s]RX OK INT\n", can->name) ;
}
/**************************/
/* Error Status interrupt */
/**************************/
- if (can_base->STATUS & CAN_STATUS_EWARN_Msk)
+ if (base->STATUS & CAN_STATUS_EWARN_Msk)
{
- rt_kprintf("[%s]EWARN INT\n", can->name) ;
+ rt_kprintf("[%s]EWARN INT\n", psNuCAN->name) ;
}
- if (can_base->STATUS & CAN_STATUS_BOFF_Msk)
+ if (base->STATUS & CAN_STATUS_BOFF_Msk)
{
- rt_kprintf("[%s]BUSOFF INT\n", can->name) ;
+ rt_kprintf("[%s]BUSOFF INT\n", psNuCAN->name) ;
- /* Do Init to release busoff pin */
- can_base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
- can_base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
- while (can_base->CON & CAN_CON_INIT_Msk);
+ /* To release busoff pin */
+ CAN_EnterInitMode(base, CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+ CAN_LeaveInitMode(base);
}
+
+ if (base->STATUS & CAN_STATUS_LEC_Msk)
+ {
+ rt_kprintf("[%s] Last Error Code %03x\n", psNuCAN->name, base->STATUS & CAN_STATUS_LEC_Msk) ;
+ }
+
}
#ifdef RT_CAN_USING_HDR
/*IntId: 0x0001-0x0020, Number of Message Object which caused the interrupt.*/
else if (u32IIDRstatus > 0 && u32IIDRstatus <= 32)
{
- /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
- if (u32IIDRstatus <= RX_MSG_ID_INDEX)
+ if ((psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX) &&
+ (u32IIDRstatus <= RX_MSG_ID_INDEX))
{
- //rt_kprintf("[%s-Tx]IntId = %d\n", can->name, u32IIDRstatus);
- rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+ /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
}
- else /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+ else if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
{
- //rt_kprintf("[%s-Rx]IntId = %d\n", can->name, u32IIDRstatus);
- rt_hw_can_isr(&can->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
+ /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+ rt_hw_can_isr(&psNuCAN->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
}
- CAN_CLR_INT_PENDING_BIT(can_base, (u32IIDRstatus - 1)); /* Clear Interrupt Pending */
+ CAN_CLR_INT_PENDING_BIT(base, (u32IIDRstatus - 1)); /* Clear Interrupt Pending */
}
#endif
-
}
+static void nu_can_ie(nu_can_t psNuCAN)
+{
+ uint32_t u32CanIE = CAN_CON_IE_Msk;
+
+ if (psNuCAN->int_flag & (RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX))
+ {
+ u32CanIE |= CAN_CON_SIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_SIE_Msk;
+ }
+
+ if (psNuCAN->int_flag & RT_DEVICE_CAN_INT_ERR)
+ {
+ u32CanIE |= CAN_CON_EIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_EIE_Msk;
+ }
+
+ if (u32CanIE & (CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))
+ {
+ CAN_EnableInt(psNuCAN->base, u32CanIE);
+
+ /* Enable interrupt. */
+ NVIC_EnableIRQ(psNuCAN->irqn);
+ }
+ else
+ {
+ u32CanIE |= (CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+ CAN_DisableInt(psNuCAN->base, u32CanIE);
+
+ /* Disable interrupt. */
+ NVIC_DisableIRQ(psNuCAN->irqn);
+ }
+}
static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg)
{
+ nu_can_t psNuCAN = (nu_can_t)can;
+ uint32_t u32CANMode;
- RT_ASSERT(can != RT_NULL);
- RT_ASSERT(cfg != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(cfg);
/* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
-
- RT_ASSERT(can_base != RT_NULL);
+ CAN_T *base = psNuCAN->base;
/* Reset this module */
- SYS_ResetModule(((nu_can_t)can)->can_rst);
+ SYS_ResetModule(psNuCAN->rstidx);
- switch (cfg->mode)
- {
- /* CAN default Normal mode */
- case RT_CAN_MODE_NORMAL:
- can->config.mode = CAN_NORMAL_MODE;
- break;
- case RT_CAN_MODE_LISEN:
- can->config.mode = RT_CAN_MODE_LISEN;
- break;
- case RT_CAN_MODE_LOOPBACK:
- can->config.mode = RT_CAN_MODE_LOOPBACK;
- break;
- case RT_CAN_MODE_LOOPBACKANLISEN:
- can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN;
- break;
- default:
- rt_kprintf("Unsupported Operating mode");
- goto exit_nu_can_configure;
- }
+ u32CANMode = (cfg->mode == RT_CAN_MODE_NORMAL) ? CAN_NORMAL_MODE : CAN_BASIC_MODE;
/*Set the CAN Bit Rate and Operating mode*/
- if (CAN_Open(can_base, can->config.baud_rate, can->config.mode) < 1)
- return -(RT_ERROR);
-
+ if (CAN_Open(base, cfg->baud_rate, u32CANMode) != cfg->baud_rate)
+ goto exit_nu_can_configure;
switch (cfg->mode)
{
- /* CAN default Normal mode */
case RT_CAN_MODE_NORMAL:
#ifdef RT_CAN_USING_HDR
- CAN_LeaveTestMode(can_base);
+ CAN_LeaveTestMode(base);
#else
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk);
#endif
break;
case RT_CAN_MODE_LISEN:
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk);
break;
case RT_CAN_MODE_LOOPBACK:
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk);
break;
case RT_CAN_MODE_LOOPBACKANLISEN:
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
break;
default:
rt_kprintf("Unsupported Operating mode");
goto exit_nu_can_configure;
}
+ nu_can_ie(psNuCAN);
return RT_EOK;
exit_nu_can_configure:
- CAN_Close(can_base);
+ CAN_Close(base);
return -(RT_ERROR);
}
static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
- rt_uint32_t argval;
+ rt_uint32_t argval = (rt_uint32_t)arg;
+ nu_can_t psNuCAN = (nu_can_t)can;
-#ifdef RT_CAN_USING_HDR
- struct rt_can_filter_config *filter_cfg;
-#endif
- /* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
-
- RT_ASSERT(can_base != RT_NULL);
- /* Check baud rate */
- RT_ASSERT(can->config.baud_rate != 0);
+ RT_ASSERT(can);
switch (cmd)
{
- case RT_DEVICE_CTRL_CLR_INT:
- argval = (rt_uint32_t) arg;
- if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Disable NVIC interrupt. */
- NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
- /* Disable Status Change Interrupt */
- CAN_DisableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
-
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Disable NVIC interrupt. */
- NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
- /* Disable Error Interrupt */
- CAN_DisableInt(can_base, CAN_CON_EIE_Msk);
- }
- break;
-
case RT_DEVICE_CTRL_SET_INT:
- argval = (rt_uint32_t) arg;
- if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Enable Status Change Interrupt */
- CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
- /* Enable NVIC interrupt. */
- NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
-
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Enable Error Status and Status Change Interrupt */
- CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
- /* Enable NVIC interrupt. */
- NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
- }
+ psNuCAN->int_flag |= argval;
+ nu_can_ie(psNuCAN);
+ break;
+
+ case RT_DEVICE_CTRL_CLR_INT:
+ psNuCAN->int_flag &= ~argval;
+ nu_can_ie(psNuCAN);
break;
-#ifdef RT_CAN_USING_HDR
case RT_CAN_CMD_SET_FILTER:
- filter_cfg = (struct rt_can_filter_config *)arg;
+ {
+ struct rt_can_filter_config *filter_cfg = (struct rt_can_filter_config *)arg;
for (int i = 0; i < filter_cfg->count; i++)
{
-
/*set the filter message object*/
if (filter_cfg->items[i].mode == 1)
{
- if (CAN_SetRxMsgObjAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
+ if (CAN_SetRxMsgObjAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
{
return -(RT_ERROR);
}
}
else
-
{
/*set the filter message object*/
- if (CAN_SetRxMsgAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
+ if (CAN_SetRxMsgAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
{
return -(RT_ERROR);
}
}
}
- break;
-#endif
+ }
+ break;
case RT_CAN_CMD_SET_MODE:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN &&
- argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN)
+ if ((argval == RT_CAN_MODE_NORMAL) ||
+ (argval == RT_CAN_MODE_LISEN) ||
+ (argval == RT_CAN_MODE_LOOPBACK) ||
+ (argval == RT_CAN_MODE_LOOPBACKANLISEN))
+ {
+ if (argval != can->config.mode)
+ {
+ can->config.mode = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.mode)
- {
- can->config.mode = argval;
- return nu_can_configure(can, &can->config);
- }
break;
case RT_CAN_CMD_SET_BAUD:
- argval = (rt_uint32_t) arg;
- if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud &&
- argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud && argval != CAN20kBaud && argval != CAN10kBaud)
+ {
+ if ((argval == CAN1MBaud) ||
+ (argval == CAN800kBaud) ||
+ (argval == CAN500kBaud) ||
+ (argval == CAN250kBaud) ||
+ (argval == CAN125kBaud) ||
+ (argval == CAN100kBaud) ||
+ (argval == CAN50kBaud) ||
+ (argval == CAN20kBaud) ||
+ (argval == CAN10kBaud))
+ {
+ if (argval != can->config.baud_rate)
+ {
+ can->config.baud_rate = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.baud_rate)
- {
- can->config.baud_rate = argval;
- return nu_can_configure(can, &can->config);
- }
- break;
+ }
+ break;
case RT_CAN_CMD_SET_PRIV:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV)
+ if (argval != RT_CAN_MODE_PRIV &&
+ argval != RT_CAN_MODE_NOPRIV)
{
return -(RT_ERROR);
}
@@ -375,20 +381,29 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
return nu_can_configure(can, &can->config);
}
break;
+
case RT_CAN_CMD_GET_STATUS:
{
- rt_uint32_t errtype;
- errtype = can_base->ERR;
- /*Receive Error Counter*/
+ rt_uint32_t errtype = psNuCAN->base->ERR;
+
+ RT_ASSERT(arg);
+
+ /*Receive Error Counter, return value is with Receive Error Passive.*/
can->status.rcverrcnt = (errtype >> 8);
+
/*Transmit Error Counter*/
- can->status.snderrcnt = ((errtype >> 24) & 0xFF);
- can->status.lasterrtype = CAN_GET_INT_STATUS(can_base) & 0x8000;
- /*status error code*/
- can->status.errcode = CAN_GET_INT_STATUS(can_base) & 0x07;
- rt_memcpy(arg, &can->status, sizeof(can->status));
+ can->status.snderrcnt = (errtype & 0xFF);
+
+ /*Last Error Type*/
+ can->status.lasterrtype = CAN_GET_INT_STATUS(psNuCAN->base) & 0x8000;
+
+ /*Status error code*/
+ can->status.errcode = CAN_GET_INT_STATUS(psNuCAN->base) & 0x07;
+
+ rt_memcpy(arg, &can->status, sizeof(struct rt_can_status));
}
break;
+
default:
return -(RT_EINVAL);
@@ -400,61 +415,91 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- /* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- RT_ASSERT(can_base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
- /* Check the parameters */
- RT_ASSERT(IS_CAN_DLC(pmsg->len));
- /* Standard ID (11 bits)*/
- if (pmsg->ide == RT_CAN_STDID)
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pmsg = (struct rt_can_msg *) buf;
+
+ if (pmsg->ide == RT_CAN_STDID && IS_CAN_STDID(pmsg->id))
{
+ /* Standard ID (11 bits)*/
tMsg.IdType = CAN_STD_ID;
- RT_ASSERT(IS_CAN_STDID(pmsg->id))
tMsg.Id = pmsg->id ;
}
- else
+ else if (pmsg->ide == RT_CAN_EXTID && IS_CAN_EXTID(pmsg->id))
{
/* Extended ID (29 bits)*/
tMsg.IdType = CAN_EXT_ID;
- RT_ASSERT(IS_CAN_EXTID(pmsg->id));
tMsg.Id = pmsg->id ;
}
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
if (pmsg->rtr == RT_CAN_DTR)
{
/* Data frame */
tMsg.FrameType = CAN_DATA_FRAME;
}
- else
+ else if (pmsg->rtr == RT_CAN_RTR)
{
/* Remote frame */
tMsg.FrameType = CAN_REMOTE_FRAME;
}
- tMsg.DLC = pmsg->len;
- rt_memcpy(tMsg.Data, pmsg->data, pmsg->len);
-
- if (CAN_Transmit(can_base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM
+ else
{
- return -(RT_ERROR);
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Check the parameters */
+ if (IS_CAN_DLC(pmsg->len))
+ {
+ tMsg.DLC = pmsg->len;
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ if (pmsg->data && pmsg->len)
+ {
+ rt_memcpy(&tMsg.Data[0], pmsg->data, pmsg->len);
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Configure Msg RAM and send the Msg in the RAM. */
+ if (CAN_Transmit(psNuCAN->base, MSG(boxno), &tMsg) == FALSE)
+ {
+ goto exit_nu_can_sendmsg;
}
return RT_EOK;
+
+exit_nu_can_sendmsg:
+
+ return -(RT_ERROR);
}
+
static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- /* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- RT_ASSERT(can_base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pmsg = (struct rt_can_msg *) buf;
/* get data */
- if (CAN_Receive(can_base, boxno, &tMsg) == FALSE)
+ if (CAN_Receive(psNuCAN->base, boxno, &tMsg) == FALSE)
{
rt_kprintf("No available RX Msg.\n");
return -(RT_ERROR);
@@ -466,32 +511,13 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn
can->hdr[pmsg->hdr].connected = 1;
#endif
- /* Standard ID (11 bits)*/
- if (tMsg.IdType == CAN_STD_ID)
- {
- pmsg->ide = RT_CAN_STDID;
- pmsg->id = tMsg.Id;
- }
- else /* Extended ID (29 bits)*/
- {
- pmsg->ide = RT_CAN_EXTID;
- pmsg->id = tMsg.Id;
- }
-
- if (tMsg.FrameType == CAN_DATA_FRAME)
- {
- /* Data frame */
- pmsg->rtr = RT_CAN_DTR;
- }
- else
- {
- /* Remote frame */
- pmsg->rtr = RT_CAN_RTR;
- }
-
+ pmsg->ide = (tMsg.IdType == CAN_STD_ID) ? RT_CAN_STDID : RT_CAN_EXTID;
+ pmsg->rtr = (tMsg.FrameType == CAN_DATA_FRAME) ? RT_CAN_DTR : RT_CAN_RTR;
+ pmsg->id = tMsg.Id;
pmsg->len = tMsg.DLC ;
- rt_memcpy(pmsg->data, tMsg.Data, pmsg->len);
+ if (pmsg->data && pmsg->len)
+ rt_memcpy(pmsg->data, &tMsg.Data[0], pmsg->len);
return RT_EOK;
}
@@ -506,13 +532,12 @@ static int rt_hw_can_init(void)
for (i = (CAN_START + 1); i < CAN_CNT; i++)
{
-
- nu_can_arr[i].dev.ops = &nu_can_ops;
nu_can_arr[i].dev.config = nu_can_default_config;
#ifdef RT_CAN_USING_HDR
nu_can_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ;
#endif
+ /* Register can device */
ret = rt_hw_can_register(&nu_can_arr[i].dev, nu_can_arr[i].name, &nu_can_ops, NULL);
RT_ASSERT(ret == RT_EOK);
}
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c
index 5e82c82367..48b91099f1 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c
@@ -44,8 +44,10 @@ static rt_uint32_t nu_crc_run(
{
uint32_t u32CalChecksum = 0;
uint32_t i = 0;
+ rt_err_t result;
- rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
+ result = rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
/* Configure CRC controller */
CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_CPU_WDATA_8);
@@ -85,7 +87,9 @@ static rt_uint32_t nu_crc_run(
/* Get checksum value */
u32CalChecksum = CRC_GetChecksum();
- rt_mutex_release(&s_CRC_mutex);
+
+ result = rt_mutex_release(&s_CRC_mutex);
+ RT_ASSERT(result == RT_EOK);
return u32CalChecksum;
}
@@ -93,9 +97,7 @@ static rt_uint32_t nu_crc_run(
rt_err_t nu_crc_init(void)
{
SYS_ResetModule(CRC_RST);
-
- rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
- return RT_EOK;
+ return rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
}
rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c
index 91f1d26819..543ac7f521 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c
@@ -37,7 +37,6 @@ typedef struct
uint32_t u32BlockSize;
} S_SHA_CONTEXT;
-
/* Private functions ------------------------------------------------------------*/
static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx);
static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx);
@@ -67,57 +66,32 @@ static struct rt_mutex s_SHA_mutex;
#if !defined(BSP_USING_TRNG)
static struct rt_mutex s_PRNG_mutex;
- static volatile int s_PRNG_done;
#endif
-static volatile int s_AES_done;
-static volatile int s_SHA_done;
-
static rt_err_t nu_crypto_init(void)
{
- /* Enable Crypto engine interrupt */
- NVIC_EnableIRQ(CRPT_IRQn);
+ rt_err_t result = RT_EOK;
+ /* init cipher mutex */
+#if defined(RT_HWCRYPTO_USING_AES)
+ result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
+ RT_ASSERT(result == RT_EOK);
AES_ENABLE_INT(CRPT);
+#endif
+
+#if defined(RT_HWCRYPTO_USING_SHA1) || defined(RT_HWCRYPTO_USING_SHA2)
+ result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
+ RT_ASSERT(result == RT_EOK);
SHA_ENABLE_INT(CRPT);
+#endif
- //init cipher mutex
- rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
- rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
-#if !defined(BSP_USING_TRNG)
+#if defined(RT_HWCRYPTO_USING_RNG) && !defined(BSP_USING_TRNG)
+ result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
+ RT_ASSERT(result == RT_EOK);
PRNG_ENABLE_INT(CRPT);
- rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
#endif
- return RT_EOK;
-}
-
-//Crypto engine IRQ handler
-void CRPT_IRQHandler()
-{
- if (AES_GET_INT_FLAG(CRPT))
- {
- if (CRPT->INTSTS & (CRPT_INTSTS_AESEIF_Msk) || (CRPT->AES_STS & (CRPT_AES_STS_BUSERR_Msk | CRPT_AES_STS_CNTERR_Msk | (0x1ul << 21))))
- rt_kprintf("AES ERROR\n");
- s_AES_done = 1;
- AES_CLR_INT_FLAG(CRPT);
- }
-
- if (SHA_GET_INT_FLAG(CRPT))
- {
- if (CRPT->INTSTS & (CRPT_INTSTS_HMACEIF_Msk) || (CRPT->HMAC_STS & (CRPT_HMAC_STS_DMAERR_Msk | (0x1ul << 9))))
- rt_kprintf("SHA ERROR\n");
- s_SHA_done = 1;
- SHA_CLR_INT_FLAG(CRPT);
- }
-
-#if !defined(BSP_USING_TRNG)
- if (PRNG_GET_INT_FLAG(CRPT))
- {
- s_PRNG_done = 1;
- PRNG_CLR_INT_FLAG(CRPT);
- }
-#endif
+ return result;
}
static rt_err_t nu_aes_crypt_run(
@@ -133,6 +107,7 @@ static rt_err_t nu_aes_crypt_run(
{
uint32_t au32SwapKey[8];
uint32_t au32SwapIV[4];
+ rt_err_t result;
au32SwapKey[0] = nu_get32_be(&pu8Key[0]);
au32SwapKey[1] = nu_get32_be(&pu8Key[4]);
@@ -156,22 +131,34 @@ static rt_err_t nu_aes_crypt_run(
au32SwapIV[2] = nu_get32_be(&pu8IV[8]);
au32SwapIV[3] = nu_get32_be(&pu8IV[12]);
- rt_mutex_take(&s_AES_mutex, RT_WAITING_FOREVER);
+ result = rt_mutex_take(&s_AES_mutex, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
//Using Channel 0
AES_Open(CRPT, 0, bEncrypt, u32OpMode, u32KeySize, AES_IN_OUT_SWAP);
- AES_SetKey(CRPT, 0, (uint32_t *)au32SwapKey, u32KeySize);
+ AES_SetKey(CRPT, 0, (uint32_t *)&au32SwapKey[0], u32KeySize);
AES_SetInitVect(CRPT, 0, (uint32_t *)au32SwapIV);
//Setup AES DMA
AES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen);
AES_CLR_INT_FLAG(CRPT);
- //Start AES encryption/decryption
- s_AES_done = 0;
- AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
- while (!s_AES_done) {};
- rt_mutex_release(&s_AES_mutex);
+ /* Start AES encryption/decryption */
+ AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
+
+ /* Wait done */
+ while (!(CRPT->INTSTS & CRPT_INTEN_AESIEN_Msk)) {};
+
+ if ((u32DataLen % 16) && (CRPT->AES_STS & (CRPT_AES_STS_OUTBUFEMPTY_Msk | CRPT_AES_STS_INBUFEMPTY_Msk)))
+ rt_kprintf("AES WARNING - AES Data length(%d) is not enough. -> %d \n", u32DataLen, RT_ALIGN(u32DataLen, 16));
+ else if (CRPT->INTSTS & (CRPT_INTSTS_AESEIF_Msk) || (CRPT->AES_STS & (CRPT_AES_STS_BUSERR_Msk | CRPT_AES_STS_CNTERR_Msk)))
+ rt_kprintf("AES ERROR - CRPT->INTSTS-%08x, CRPT->AES_STS-%08x\n", CRPT->INTSTS, CRPT->AES_STS);
+
+ /* Clear AES interrupt status */
+ AES_CLR_INT_FLAG(CRPT);
+
+ result = rt_mutex_release(&s_AES_mutex);
+ RT_ASSERT(result == RT_EOK);
return RT_EOK;
}
@@ -180,28 +167,38 @@ static rt_err_t nu_aes_crypt_run(
//Using PRNG instead of TRNG
static void nu_prng_open(uint32_t u32Seed)
{
- rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+ rt_err_t result;
- //Open PRNG 128 bits. But always return 32 bits
+ result = rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
+
+ //Open PRNG 128 bits.
PRNG_Open(CRPT, PRNG_KEY_SIZE_128, PRNG_SEED_RELOAD, u32Seed);
- rt_mutex_release(&s_PRNG_mutex);
+ result = rt_mutex_release(&s_PRNG_mutex);
+ RT_ASSERT(result == RT_EOK);
}
static rt_uint32_t nu_prng_run(void)
{
- uint32_t au32RNGValue[2];
+ uint32_t au32RNGValue[4];
+ rt_err_t result;
- rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+ result = rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
- s_PRNG_done = 0;
PRNG_Start(CRPT);
- while (!s_PRNG_done) {};
+ while ((CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)) {};
- PRNG_Read(CRPT, au32RNGValue);
+ /* Clear PRNG interrupt status */
+ PRNG_CLR_INT_FLAG(CRPT);
- rt_mutex_release(&s_PRNG_mutex);
- return au32RNGValue[0];
+ PRNG_Read(CRPT, &au32RNGValue[0]);
+
+ result = rt_mutex_release(&s_PRNG_mutex);
+ RT_ASSERT(result == RT_EOK);
+
+ return au32RNGValue[0] ^ au32RNGValue[1] ^ au32RNGValue[2] ^ au32RNGValue[3];
}
#endif
@@ -214,6 +211,8 @@ static rt_err_t nu_aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hw
unsigned char in_align_flag = 0;
unsigned char out_align_flag = 0;
unsigned char iv_temp[16];
+ RT_ASSERT(symmetric_ctx != RT_NULL);
+ RT_ASSERT(symmetric_info != RT_NULL);
if ((symmetric_info->length % 4) != 0)
{
@@ -336,18 +335,23 @@ static void SHABlockUpdate(uint32_t u32OpMode, uint32_t u32SrcAddr, uint32_t u32
//Setup SHA DMA
SHA_SetDMATransfer(CRPT, u32SrcAddr, u32Len);
- SHA_CLR_INT_FLAG(CRPT);
-
- //Start SHA
- s_SHA_done = 0;
if (u32Mode == CRYPTO_DMA_FIRST)
CRPT->HMAC_CTL |= CRPT_HMAC_CTL_DMAFIRST_Msk;
else
CRPT->HMAC_CTL &= ~CRPT_HMAC_CTL_DMAFIRST_Msk;
+ //Start SHA
+ SHA_CLR_INT_FLAG(CRPT);
SHA_Start(CRPT, u32Mode);
- while (!s_SHA_done) {};
+ /* Wait done */
+ while (!(CRPT->INTSTS & CRPT_INTSTS_HMACIF_Msk)) {};
+
+ if (CRPT->INTSTS & (CRPT_INTSTS_HMACEIF_Msk) || (CRPT->HMAC_STS & (CRPT_HMAC_STS_DMAERR_Msk)))
+ rt_kprintf("SHA ERROR - CRPT->INTSTS-%08x, CRPT->HMAC_STS-%08x\n", CRPT->INTSTS, CRPT->HMAC_STS);
+
+ /* Clear SHA interrupt status */
+ SHA_CLR_INT_FLAG(CRPT);
}
static rt_err_t nu_sha_hash_run(
@@ -357,12 +361,18 @@ static rt_err_t nu_sha_hash_run(
uint32_t u32DataLen
)
{
- rt_mutex_take(&s_SHA_mutex, RT_WAITING_FOREVER);
+ rt_err_t result;
+
+ RT_ASSERT(psSHACtx != RT_NULL);
+ RT_ASSERT(pu8InData != RT_NULL);
+
+ result = rt_mutex_take(&s_SHA_mutex, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
uint8_t *pu8SrcAddr = (uint8_t *)pu8InData;
uint32_t u32CopyLen = 0;
- while ((psSHACtx->u32SHATempBufLen + u32DataLen) >= psSHACtx->u32BlockSize)
+ while ((psSHACtx->u32SHATempBufLen + u32DataLen) > psSHACtx->u32BlockSize)
{
if (psSHACtx->pu8SHATempBuf)
{
@@ -397,7 +407,8 @@ static rt_err_t nu_sha_hash_run(
if (psSHACtx->pu8SHATempBuf == RT_NULL)
{
LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, psSHACtx->u32BlockSize);
- rt_mutex_release(&s_SHA_mutex);
+ result = rt_mutex_release(&s_SHA_mutex);
+ RT_ASSERT(result == RT_EOK);
return -RT_ENOMEM;
}
@@ -425,7 +436,8 @@ static rt_err_t nu_sha_hash_run(
if (psSHACtx->pu8SHATempBuf == RT_NULL)
{
LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, psSHACtx->u32BlockSize);
- rt_mutex_release(&s_SHA_mutex);
+ result = rt_mutex_release(&s_SHA_mutex);
+ RT_ASSERT(result == RT_EOK);
return -RT_ENOMEM;
}
@@ -436,7 +448,8 @@ static rt_err_t nu_sha_hash_run(
psSHACtx->u32SHATempBufLen += u32DataLen;
}
- rt_mutex_release(&s_SHA_mutex);
+ result = rt_mutex_release(&s_SHA_mutex);
+ RT_ASSERT(result == RT_EOK);
return RT_EOK;
}
@@ -446,6 +459,8 @@ static rt_err_t nu_sha_update(struct hwcrypto_hash *hash_ctx, const rt_uint8_t *
uint32_t u32SHAOpMode;
unsigned char *nu_in;
unsigned char in_align_flag = 0;
+ RT_ASSERT(hash_ctx != RT_NULL);
+ RT_ASSERT(in != RT_NULL);
//Select SHA operation mode
switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
@@ -500,7 +515,11 @@ static rt_err_t nu_sha_finish(struct hwcrypto_hash *hash_ctx, rt_uint8_t *out, r
unsigned char *nu_out;
unsigned char out_align_flag = 0;
uint32_t u32SHAOpMode;
- S_SHA_CONTEXT *psSHACtx = hash_ctx->parent.contex;
+ S_SHA_CONTEXT *psSHACtx = RT_NULL;
+ RT_ASSERT(hash_ctx != RT_NULL);
+ RT_ASSERT(out != RT_NULL);
+
+ psSHACtx = hash_ctx->parent.contex;
//Check SHA Hash value buffer length
switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
@@ -639,6 +658,7 @@ static const struct hwcrypto_rng_ops nu_rng_ops =
static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
{
rt_err_t res = RT_EOK;
+ RT_ASSERT(ctx != RT_NULL);
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
@@ -672,18 +692,6 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
}
case HWCRYPTO_TYPE_SHA1:
- {
- ctx->contex = rt_malloc(sizeof(S_SHA_CONTEXT));
-
- if (ctx->contex == RT_NULL)
- return -RT_ERROR;
-
- rt_memset(ctx->contex, 0, sizeof(S_SHA_CONTEXT));
- //Setup SHA1 operation
- ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
- break;
- }
-
case HWCRYPTO_TYPE_SHA2:
{
ctx->contex = rt_malloc(sizeof(S_SHA_CONTEXT));
@@ -692,7 +700,7 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
return -RT_ERROR;
rt_memset(ctx->contex, 0, sizeof(S_SHA_CONTEXT));
- //Setup SHA2 operation
+ //Setup operation
((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
break;
}
@@ -718,11 +726,15 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
break;
}
+ nu_hwcrypto_reset(ctx);
+
return res;
}
static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx)
{
+ RT_ASSERT(ctx != RT_NULL);
+
if (ctx->contex)
rt_free(ctx->contex);
}
@@ -730,6 +742,8 @@ static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx)
static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
rt_err_t res = RT_EOK;
+ RT_ASSERT(des != RT_NULL);
+ RT_ASSERT(src != RT_NULL);
if (des->contex && src->contex)
{
@@ -791,6 +805,7 @@ static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx)
int nu_hwcrypto_device_init(void)
{
+ rt_err_t result;
static struct rt_hwcrypto_device nu_hwcrypto_dev;
nu_hwcrypto_dev.ops = &nu_hwcrypto_ops;
@@ -809,11 +824,9 @@ int nu_hwcrypto_device_init(void)
nu_trng_init();
#endif
- // register hwcrypto operation
- if (rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
- {
- return -1;
- }
+ /* register hwcrypto operation */
+ result = rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME);
+ RT_ASSERT(result == RT_EOK);
return 0;
}
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
index fbc38e6e2a..30bffc49bf 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
@@ -99,7 +99,7 @@ static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u3
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
- switch (RT_I2C_DEV_CTRL_CLK)
+ switch (u32Cmd)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c
index 708f653d36..e71677a917 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c
@@ -19,10 +19,12 @@
#include
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
/* Private define ---------------------------------------------------------------*/
@@ -232,11 +234,13 @@ static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_siz
{
rt_uint32_t ret = 0;
nu_sdh_t sdh = (nu_sdh_t)dev;
+ rt_err_t result;
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(buffer != RT_NULL);
- rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+ result = rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
/* Check alignment. */
if (((uint32_t)buffer & 0x03) != 0)
@@ -277,7 +281,8 @@ exit_nu_sdh_read:
sdh->pbuf = RT_NULL;
}
- rt_sem_release(&sdh->lock);
+ result = rt_sem_release(&sdh->lock);
+ RT_ASSERT(result == RT_EOK);
if (ret == Successful)
return blk_nb;
@@ -291,11 +296,13 @@ static rt_size_t nu_sdh_write(rt_device_t dev, rt_off_t pos, const void *buffer,
{
rt_uint32_t ret = 0;
nu_sdh_t sdh = (nu_sdh_t)dev;
+ rt_err_t result;
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(buffer != RT_NULL);
- rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+ result = rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+ RT_ASSERT(result == RT_EOK);
/* Check alignment. */
if (((uint32_t)buffer & 0x03) != 0)
@@ -334,7 +341,8 @@ exit_nu_sdh_write:
sdh->pbuf = RT_NULL;
}
- rt_sem_release(&sdh->lock);
+ result = rt_sem_release(&sdh->lock);
+ RT_ASSERT(result == RT_EOK);
if (ret == Successful) return blk_nb;
@@ -389,7 +397,8 @@ static int rt_hw_sdh_init(void)
/* Private */
nu_sdh_arr[i].dev.user_data = (void *)&nu_sdh_arr[i];
- rt_sem_init(&nu_sdh_arr[i].lock, "sdhlock", 1, RT_IPC_FLAG_FIFO);
+ ret = rt_sem_init(&nu_sdh_arr[i].lock, "sdhlock", 1, RT_IPC_FLAG_FIFO);
+ RT_ASSERT(ret == RT_EOK);
SDH_Open(nu_sdh_arr[i].base, CardDetect_From_GPIO);
@@ -398,6 +407,7 @@ static int rt_hw_sdh_init(void)
NVIC_EnableIRQ(SDH0_IRQn);
nu_sdh_arr[i].pbuf = RT_NULL;
+
ret = rt_device_register(&nu_sdh_arr[i].dev, nu_sdh_arr[i].name, flags);
RT_ASSERT(ret == RT_EOK);
}
@@ -411,8 +421,6 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
{
rt_bool_t ret = RT_FALSE;
-#if defined(RT_USING_DFS)
-
struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path);
if (psFS == RT_NULL)
{
@@ -427,8 +435,6 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
ret = RT_FALSE;
}
-#endif
-
exit_nu_sdh_hotplug_is_mounted:
return ret;
@@ -438,8 +444,6 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
rt_err_t ret = RT_ERROR;
DIR *t;
-#if defined(RT_USING_DFS)
-
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE)
{
ret = RT_EOK;
@@ -487,7 +491,6 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
exit_nu_sdh_hotplug_mount:
-#endif
return -(ret);
}
@@ -495,7 +498,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
{
rt_err_t ret = RT_ERROR;
-#if defined(RT_USING_DFS)
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE)
{
ret = RT_EOK;
@@ -512,7 +514,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
rt_kprintf("Succeed to unmount %s.\n", sdh->mounted_point);
ret = RT_EOK;
}
-#endif
exit_nu_sdh_hotplug_unmount:
@@ -581,7 +582,11 @@ static void sdh_hotplugger(void *param)
int mnt_init_sdcard_hotplug(void)
{
- rt_thread_init(&sdh_tid, "hotplug", sdh_hotplugger, NULL, sdh_stack, sizeof(sdh_stack), RT_THREAD_PRIORITY_MAX - 2, 10);
+ rt_err_t result;
+
+ result = rt_thread_init(&sdh_tid, "hotplug", sdh_hotplugger, NULL, sdh_stack, sizeof(sdh_stack), RT_THREAD_PRIORITY_MAX - 2, 10);
+ RT_ASSERT(result == RT_EOK);
+
rt_thread_startup(&sdh_tid);
return 0;
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c
index 485ff8fea2..e6c0d514c4 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c
@@ -71,10 +71,8 @@ rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx)
{
if (!s_i32TRNGEnable)
{
- uint32_t u32RNGValue;
- //use software rand
- u32RNGValue = rand();
- return u32RNGValue;
+ /* Use software rand */
+ return (rt_uint32_t)rand();
}
return nu_trng_run();
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
index 964bb7ba05..e54580d671 100644
--- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
@@ -469,7 +469,7 @@ static void int_xfer_done_cb(UTR_T *psUTR)
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
- rt_usbh_event_signal(&msg);
+ rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
@@ -866,7 +866,7 @@ int nu_usbh_register(void)
RT_ASSERT(res == RT_EOK);
/*initialize the usb host function */
- res = rt_usb_host_init();
+ res = rt_usb_host_init("usbh");
RT_ASSERT(res == RT_EOK);
#if defined(RT_USING_PM)
diff --git a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h
index 86340d99d8..b0152f8011 100644
--- a/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h
+++ b/bsp/nuvoton/libraries/m480/Device/Nuvoton/M480/Include/can_reg.h
@@ -10,7 +10,7 @@
#define __CAN_REG_H__
#if defined ( __CC_ARM )
-#pragma anon_unions
+ #pragma anon_unions
#endif
/**
@@ -586,8 +586,8 @@ typedef struct
#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */
#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */
-#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */
-#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */
+#define CAN_IIDR_INTID_Pos (0) /*!< CAN_T::IIDR: IntId Position */
+#define CAN_IIDR_INTID_Msk (0xfffful << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: IntId Mask */
#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */
#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
@@ -753,7 +753,7 @@ typedef struct
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
-#pragma no_anon_unions
+ #pragma no_anon_unions
#endif
#endif /* __CAN_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig
index 22523e90b4..0d529462a3 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig
+++ b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig
@@ -447,6 +447,7 @@ config SOC_SERIES_M480
menuconfig BSP_USING_SDH
bool "Enable Secure Digital Host Controller(SDH)"
select RT_USING_DFS
+ select DFS_USING_POSIX
if BSP_USING_SDH
config BSP_USING_SDH0
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
index a667e34979..14926076c3 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
@@ -1,12 +1,13 @@
/**************************************************************************//**
*
-* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
-* 2020-2-07 ChingI First version
+* 2020-6-22 ChingI First version
+* 2022-1-8 Wayne Fix IE issue
*
******************************************************************************/
@@ -56,9 +57,10 @@ struct nu_can
{
struct rt_can_device dev;
char *name;
- CAN_T *can_base;
- uint32_t can_rst;
- IRQn_Type can_irq_n;
+ CAN_T *base;
+ IRQn_Type irqn;
+ uint32_t rstidx;
+ uint32_t int_flag;
};
typedef struct nu_can *nu_can_t;
@@ -74,29 +76,27 @@ static struct nu_can nu_can_arr[] =
#if defined(BSP_USING_CAN0)
{
.name = "can0",
- .can_base = CAN0,
- .can_rst = CAN0_RST,
- .can_irq_n = CAN0_IRQn,
+ .base = CAN0,
+ .rstidx = CAN0_RST,
+ .irqn = CAN0_IRQn,
},
#endif
#if defined(BSP_USING_CAN1)
{
.name = "can1",
- .can_base = CAN1,
- .can_rst = CAN1_RST,
- .can_irq_n = CAN1_IRQn,
+ .base = CAN1,
+ .rstidx = CAN1_RST,
+ .irqn = CAN1_IRQn,
},
#endif
-
#if defined(BSP_USING_CAN2)
{
.name = "can2",
- .can_base = CAN2,
- .can_rst = CAN2_RST,
- .can_irq_n = CAN2_IRQn,
+ .base = CAN2,
+ .rstidx = CAN2_RST,
+ .irqn = CAN2_IRQn,
},
#endif
- {0}
}; /* struct nu_can */
/* Public functions ------------------------------------------------------------*/
@@ -158,267 +158,271 @@ void CAN2_IRQHandler(void)
/* Private Variables ------------------------------------------------------------*/
-
-static void nu_can_isr(nu_can_t can)
+static void nu_can_isr(nu_can_t psNuCAN)
{
- uint32_t u32IIDRstatus;
/* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
+ CAN_T *base = psNuCAN->base;
/* Get interrupt event */
- u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(can_base);
+ uint32_t u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(base) & CAN_IIDR_INTID_Msk;
- if (u32IIDRstatus == 0x00008000) /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ if (u32IIDRstatus == 0x00008000)
{
/**************************/
/* Status Change interrupt*/
/**************************/
- if (can_base->STATUS & CAN_STATUS_TXOK_Msk)
+ if (base->STATUS & CAN_STATUS_TXOK_Msk)
{
- can_base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
+ base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
+ }
#endif
- //rt_kprintf("[%s]TX OK INT\n", can->name) ;
}
- if (can_base->STATUS & CAN_STATUS_RXOK_Msk)
+ if (base->STATUS & CAN_STATUS_RXOK_Msk)
{
- can_base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
+ base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&can->dev, RT_CAN_EVENT_RX_IND);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_RX_IND);
+ }
#endif
- //rt_kprintf("[%s]RX OK INT\n", can->name) ;
}
/**************************/
/* Error Status interrupt */
/**************************/
- if (can_base->STATUS & CAN_STATUS_EWARN_Msk)
+ if (base->STATUS & CAN_STATUS_EWARN_Msk)
{
- rt_kprintf("[%s]EWARN INT\n", can->name) ;
+ rt_kprintf("[%s]EWARN INT\n", psNuCAN->name) ;
}
- if (can_base->STATUS & CAN_STATUS_BOFF_Msk)
+ if (base->STATUS & CAN_STATUS_BOFF_Msk)
{
- rt_kprintf("[%s]BUSOFF INT\n", can->name) ;
+ rt_kprintf("[%s]BUSOFF INT\n", psNuCAN->name) ;
- /* Do Init to release busoff pin */
- can_base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
- can_base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
- while (can_base->CON & CAN_CON_INIT_Msk);
+ /* To release busoff pin */
+ CAN_EnterInitMode(base, CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+ CAN_LeaveInitMode(base);
}
+
+ if (base->STATUS & CAN_STATUS_LEC_Msk)
+ {
+ rt_kprintf("[%s] Last Error Code %03x\n", psNuCAN->name, base->STATUS & CAN_STATUS_LEC_Msk) ;
+ }
+
}
#ifdef RT_CAN_USING_HDR
/*IntId: 0x0001-0x0020, Number of Message Object which caused the interrupt.*/
else if (u32IIDRstatus > 0 && u32IIDRstatus <= 32)
{
- /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
- if (u32IIDRstatus <= RX_MSG_ID_INDEX)
+ if ((psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX) &&
+ (u32IIDRstatus <= RX_MSG_ID_INDEX))
{
- //rt_kprintf("[%s-Tx]IntId = %d\n", can->name, u32IIDRstatus);
- rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+ /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
}
- else /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+ else if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
{
- //rt_kprintf("[%s-Rx]IntId = %d\n", can->name, u32IIDRstatus);
- rt_hw_can_isr(&can->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
+ /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+ rt_hw_can_isr(&psNuCAN->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
}
- CAN_CLR_INT_PENDING_BIT(can_base, (u32IIDRstatus - 1)); /* Clear Interrupt Pending */
+ CAN_CLR_INT_PENDING_BIT(base, (u32IIDRstatus - 1)); /* Clear Interrupt Pending */
}
#endif
-
}
+static void nu_can_ie(nu_can_t psNuCAN)
+{
+ uint32_t u32CanIE = CAN_CON_IE_Msk;
+
+ if (psNuCAN->int_flag & (RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX))
+ {
+ u32CanIE |= CAN_CON_SIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_SIE_Msk;
+ }
+
+ if (psNuCAN->int_flag & RT_DEVICE_CAN_INT_ERR)
+ {
+ u32CanIE |= CAN_CON_EIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_EIE_Msk;
+ }
+
+ if (u32CanIE & (CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))
+ {
+ CAN_EnableInt(psNuCAN->base, u32CanIE);
+
+ /* Enable interrupt. */
+ NVIC_EnableIRQ(psNuCAN->irqn);
+ }
+ else
+ {
+ u32CanIE |= (CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+ CAN_DisableInt(psNuCAN->base, u32CanIE);
+
+ /* Disable interrupt. */
+ NVIC_DisableIRQ(psNuCAN->irqn);
+ }
+}
static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg)
{
+ nu_can_t psNuCAN = (nu_can_t)can;
+ uint32_t u32CANMode;
- RT_ASSERT(can != RT_NULL);
- RT_ASSERT(cfg != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(cfg);
/* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
-
- RT_ASSERT(can_base != RT_NULL);
+ CAN_T *base = psNuCAN->base;
/* Reset this module */
- SYS_ResetModule(((nu_can_t)can)->can_rst);
+ SYS_ResetModule(psNuCAN->rstidx);
- switch (cfg->mode)
- {
- /* CAN default Normal mode */
- case RT_CAN_MODE_NORMAL:
- can->config.mode = CAN_NORMAL_MODE;
- break;
- case RT_CAN_MODE_LISEN:
- can->config.mode = RT_CAN_MODE_LISEN;
- break;
- case RT_CAN_MODE_LOOPBACK:
- can->config.mode = RT_CAN_MODE_LOOPBACK;
- break;
- case RT_CAN_MODE_LOOPBACKANLISEN:
- can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN;
- break;
- default:
- rt_kprintf("Unsupported Operating mode");
- goto exit_nu_can_configure;
- }
+ u32CANMode = (cfg->mode == RT_CAN_MODE_NORMAL) ? CAN_NORMAL_MODE : CAN_BASIC_MODE;
/*Set the CAN Bit Rate and Operating mode*/
- if (CAN_Open(can_base, can->config.baud_rate, can->config.mode) < 1)
- return -(RT_ERROR);
-
+ if (CAN_Open(base, cfg->baud_rate, u32CANMode) != cfg->baud_rate)
+ goto exit_nu_can_configure;
switch (cfg->mode)
{
- /* CAN default Normal mode */
case RT_CAN_MODE_NORMAL:
#ifdef RT_CAN_USING_HDR
- CAN_LeaveTestMode(can_base);
+ CAN_LeaveTestMode(base);
#else
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk);
#endif
break;
case RT_CAN_MODE_LISEN:
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk);
break;
case RT_CAN_MODE_LOOPBACK:
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk);
break;
case RT_CAN_MODE_LOOPBACKANLISEN:
- CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+ CAN_EnterTestMode(base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
break;
default:
rt_kprintf("Unsupported Operating mode");
goto exit_nu_can_configure;
}
+ nu_can_ie(psNuCAN);
return RT_EOK;
exit_nu_can_configure:
- CAN_Close(can_base);
+ CAN_Close(base);
return -(RT_ERROR);
}
static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
- rt_uint32_t argval;
+ rt_uint32_t argval = (rt_uint32_t)arg;
+ nu_can_t psNuCAN = (nu_can_t)can;
-#ifdef RT_CAN_USING_HDR
- struct rt_can_filter_config *filter_cfg;
-#endif
- /* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
-
- RT_ASSERT(can_base != RT_NULL);
- /* Check baud rate */
- RT_ASSERT(can->config.baud_rate != 0);
+ RT_ASSERT(can);
switch (cmd)
{
- case RT_DEVICE_CTRL_CLR_INT:
- argval = (rt_uint32_t) arg;
- if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Disable NVIC interrupt. */
- NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
- /* Disable Status Change Interrupt */
- CAN_DisableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
-
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Disable NVIC interrupt. */
- NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
- /* Disable Error Interrupt */
- CAN_DisableInt(can_base, CAN_CON_EIE_Msk);
- }
- break;
-
case RT_DEVICE_CTRL_SET_INT:
- argval = (rt_uint32_t) arg;
- if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Enable Status Change Interrupt */
- CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
- /* Enable NVIC interrupt. */
- NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
-
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Enable Error Status and Status Change Interrupt */
- CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
- /* Enable NVIC interrupt. */
- NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
- }
+ psNuCAN->int_flag |= argval;
+ nu_can_ie(psNuCAN);
+ break;
+
+ case RT_DEVICE_CTRL_CLR_INT:
+ psNuCAN->int_flag &= ~argval;
+ nu_can_ie(psNuCAN);
break;
-#ifdef RT_CAN_USING_HDR
case RT_CAN_CMD_SET_FILTER:
- filter_cfg = (struct rt_can_filter_config *)arg;
+ {
+ struct rt_can_filter_config *filter_cfg = (struct rt_can_filter_config *)arg;
for (int i = 0; i < filter_cfg->count; i++)
{
-
/*set the filter message object*/
if (filter_cfg->items[i].mode == 1)
{
- if (CAN_SetRxMsgObjAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
+ if (CAN_SetRxMsgObjAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
{
return -(RT_ERROR);
}
}
else
-
{
/*set the filter message object*/
- if (CAN_SetRxMsgAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
+ if (CAN_SetRxMsgAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
{
return -(RT_ERROR);
}
}
}
- break;
-#endif
+ }
+ break;
case RT_CAN_CMD_SET_MODE:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN &&
- argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN)
+ if ((argval == RT_CAN_MODE_NORMAL) ||
+ (argval == RT_CAN_MODE_LISEN) ||
+ (argval == RT_CAN_MODE_LOOPBACK) ||
+ (argval == RT_CAN_MODE_LOOPBACKANLISEN))
+ {
+ if (argval != can->config.mode)
+ {
+ can->config.mode = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.mode)
- {
- can->config.mode = argval;
- return nu_can_configure(can, &can->config);
- }
break;
case RT_CAN_CMD_SET_BAUD:
- argval = (rt_uint32_t) arg;
- if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud &&
- argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud && argval != CAN20kBaud && argval != CAN10kBaud)
+ {
+ if ((argval == CAN1MBaud) ||
+ (argval == CAN800kBaud) ||
+ (argval == CAN500kBaud) ||
+ (argval == CAN250kBaud) ||
+ (argval == CAN125kBaud) ||
+ (argval == CAN100kBaud) ||
+ (argval == CAN50kBaud) ||
+ (argval == CAN20kBaud) ||
+ (argval == CAN10kBaud))
+ {
+ if (argval != can->config.baud_rate)
+ {
+ can->config.baud_rate = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.baud_rate)
- {
- can->config.baud_rate = argval;
- return nu_can_configure(can, &can->config);
- }
- break;
+ }
+ break;
case RT_CAN_CMD_SET_PRIV:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV)
+ if (argval != RT_CAN_MODE_PRIV &&
+ argval != RT_CAN_MODE_NOPRIV)
{
return -(RT_ERROR);
}
@@ -428,20 +432,29 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
return nu_can_configure(can, &can->config);
}
break;
+
case RT_CAN_CMD_GET_STATUS:
{
- rt_uint32_t errtype;
- errtype = can_base->ERR;
- /*Receive Error Counter*/
+ rt_uint32_t errtype = psNuCAN->base->ERR;
+
+ RT_ASSERT(arg);
+
+ /*Receive Error Counter, return value is with Receive Error Passive.*/
can->status.rcverrcnt = (errtype >> 8);
+
/*Transmit Error Counter*/
- can->status.snderrcnt = ((errtype >> 24) & 0xFF);
- can->status.lasterrtype = CAN_GET_INT_STATUS(can_base) & 0x8000;
- /*status error code*/
- can->status.errcode = CAN_GET_INT_STATUS(can_base) & 0x07;
- rt_memcpy(arg, &can->status, sizeof(can->status));
+ can->status.snderrcnt = (errtype & 0xFF);
+
+ /*Last Error Type*/
+ can->status.lasterrtype = CAN_GET_INT_STATUS(psNuCAN->base) & 0x8000;
+
+ /*Status error code*/
+ can->status.errcode = CAN_GET_INT_STATUS(psNuCAN->base) & 0x07;
+
+ rt_memcpy(arg, &can->status, sizeof(struct rt_can_status));
}
break;
+
default:
return -(RT_EINVAL);
@@ -453,61 +466,91 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- /* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- RT_ASSERT(can_base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
- /* Check the parameters */
- RT_ASSERT(IS_CAN_DLC(pmsg->len));
- /* Standard ID (11 bits)*/
- if (pmsg->ide == RT_CAN_STDID)
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pmsg = (struct rt_can_msg *) buf;
+
+ if (pmsg->ide == RT_CAN_STDID && IS_CAN_STDID(pmsg->id))
{
+ /* Standard ID (11 bits)*/
tMsg.IdType = CAN_STD_ID;
- RT_ASSERT(IS_CAN_STDID(pmsg->id))
tMsg.Id = pmsg->id ;
}
- else
+ else if (pmsg->ide == RT_CAN_EXTID && IS_CAN_EXTID(pmsg->id))
{
/* Extended ID (29 bits)*/
tMsg.IdType = CAN_EXT_ID;
- RT_ASSERT(IS_CAN_EXTID(pmsg->id));
tMsg.Id = pmsg->id ;
}
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
if (pmsg->rtr == RT_CAN_DTR)
{
/* Data frame */
tMsg.FrameType = CAN_DATA_FRAME;
}
- else
+ else if (pmsg->rtr == RT_CAN_RTR)
{
/* Remote frame */
tMsg.FrameType = CAN_REMOTE_FRAME;
}
- tMsg.DLC = pmsg->len;
- rt_memcpy(tMsg.Data, pmsg->data, pmsg->len);
-
- if (CAN_Transmit(can_base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM
+ else
{
- return -(RT_ERROR);
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Check the parameters */
+ if (IS_CAN_DLC(pmsg->len))
+ {
+ tMsg.DLC = pmsg->len;
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ if (pmsg->data && pmsg->len)
+ {
+ rt_memcpy(&tMsg.Data[0], pmsg->data, pmsg->len);
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Configure Msg RAM and send the Msg in the RAM. */
+ if (CAN_Transmit(psNuCAN->base, MSG(boxno), &tMsg) == FALSE)
+ {
+ goto exit_nu_can_sendmsg;
}
return RT_EOK;
+
+exit_nu_can_sendmsg:
+
+ return -(RT_ERROR);
}
+
static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- /* Get base address of CAN register */
- CAN_T *can_base = ((nu_can_t)can)->can_base;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- RT_ASSERT(can_base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pmsg = (struct rt_can_msg *) buf;
/* get data */
- if (CAN_Receive(can_base, boxno, &tMsg) == FALSE)
+ if (CAN_Receive(psNuCAN->base, boxno, &tMsg) == FALSE)
{
rt_kprintf("No available RX Msg.\n");
return -(RT_ERROR);
@@ -519,32 +562,13 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn
can->hdr[pmsg->hdr].connected = 1;
#endif
- /* Standard ID (11 bits)*/
- if (tMsg.IdType == CAN_STD_ID)
- {
- pmsg->ide = RT_CAN_STDID;
- pmsg->id = tMsg.Id;
- }
- else /* Extended ID (29 bits)*/
- {
- pmsg->ide = RT_CAN_EXTID;
- pmsg->id = tMsg.Id;
- }
-
- if (tMsg.FrameType == CAN_DATA_FRAME)
- {
- /* Data frame */
- pmsg->rtr = RT_CAN_DTR;
- }
- else
- {
- /* Remote frame */
- pmsg->rtr = RT_CAN_RTR;
- }
-
+ pmsg->ide = (tMsg.IdType == CAN_STD_ID) ? RT_CAN_STDID : RT_CAN_EXTID;
+ pmsg->rtr = (tMsg.FrameType == CAN_DATA_FRAME) ? RT_CAN_DTR : RT_CAN_RTR;
+ pmsg->id = tMsg.Id;
pmsg->len = tMsg.DLC ;
- rt_memcpy(pmsg->data, tMsg.Data, pmsg->len);
+ if (pmsg->data && pmsg->len)
+ rt_memcpy(pmsg->data, &tMsg.Data[0], pmsg->len);
return RT_EOK;
}
@@ -559,13 +583,12 @@ static int rt_hw_can_init(void)
for (i = (CAN_START + 1); i < CAN_CNT; i++)
{
-
- nu_can_arr[i].dev.ops = &nu_can_ops;
nu_can_arr[i].dev.config = nu_can_default_config;
#ifdef RT_CAN_USING_HDR
nu_can_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ;
#endif
+ /* Register can device */
ret = rt_hw_can_register(&nu_can_arr[i].dev, nu_can_arr[i].name, &nu_can_ops, NULL);
RT_ASSERT(ret == RT_EOK);
}
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
index 3eb2a19356..64a3595d91 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crc.c
@@ -96,14 +96,8 @@ static rt_uint32_t nu_crc_run(
rt_err_t nu_crc_init(void)
{
- rt_err_t result;
-
SYS_ResetModule(CRC_RST);
-
- result = rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
- RT_ASSERT(result == RT_EOK);
-
- return RT_EOK;
+ return rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
}
rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
index eda0392c53..6cb252068f 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_crypto.c
@@ -30,7 +30,6 @@
#endif
/* Private typedef --------------------------------------------------------------*/
-
typedef struct
{
uint8_t *pu8SHATempBuf;
@@ -72,76 +71,38 @@ static struct rt_mutex s_SHA_mutex;
#if !defined(BSP_USING_TRNG)
static struct rt_mutex s_PRNG_mutex;
- static volatile int s_PRNG_done;
#endif
-static volatile int s_AES_done;
-static volatile int s_TDES_done;
-static volatile int s_SHA_done;
-
static rt_err_t nu_crypto_init(void)
{
- rt_err_t result;
+ rt_err_t result = RT_EOK;
- /* Enable Crypto engine interrupt */
- NVIC_EnableIRQ(CRPT_IRQn);
-
- AES_ENABLE_INT(CRPT);
- TDES_ENABLE_INT(CRPT);
- SHA_ENABLE_INT(CRPT);
-
- //init cipher mutex
+ /* init cipher mutex */
+#if defined(RT_HWCRYPTO_USING_AES)
result = rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
+ AES_ENABLE_INT(CRPT);
+#endif
+#if defined(RT_HWCRYPTO_USING_3DES)
result = rt_mutex_init(&s_TDES_mutex, NU_HWCRYPTO_TDES_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
+ TDES_ENABLE_INT(CRPT);
+#endif
+#if defined(RT_HWCRYPTO_USING_SHA1) || defined(RT_HWCRYPTO_USING_SHA2)
result = rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
+ SHA_ENABLE_INT(CRPT);
+#endif
-#if !defined(BSP_USING_TRNG)
- PRNG_ENABLE_INT(CRPT);
+#if defined(RT_HWCRYPTO_USING_RNG) && !defined(BSP_USING_TRNG)
result = rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_PRIO);
RT_ASSERT(result == RT_EOK);
+ PRNG_ENABLE_INT(CRPT);
#endif
- return RT_EOK;
-}
-
-//Crypto engine IRQ handler
-
-void CRYPTO_IRQHandler()
-{
- if (AES_GET_INT_FLAG(CRPT))
- {
- if (CRPT->INTSTS & (CRPT_INTSTS_AESEIF_Msk) || (CRPT->AES_STS & (CRPT_AES_STS_BUSERR_Msk | CRPT_AES_STS_CNTERR_Msk | (0x1ul << 21))))
- rt_kprintf("AES ERROR\n");
- s_AES_done = 1;
- AES_CLR_INT_FLAG(CRPT);
- }
-
- if (TDES_GET_INT_FLAG(CRPT))
- {
- s_TDES_done = 1;
- TDES_CLR_INT_FLAG(CRPT);
- }
-
- if (SHA_GET_INT_FLAG(CRPT))
- {
- if (CRPT->INTSTS & (CRPT_INTSTS_HMACEIF_Msk) || (CRPT->HMAC_STS & (CRPT_HMAC_STS_DMAERR_Msk | (0x1ul << 9))))
- rt_kprintf("SHA ERROR\n");
- s_SHA_done = 1;
- SHA_CLR_INT_FLAG(CRPT);
- }
-
-#if !defined(BSP_USING_TRNG)
- if (PRNG_GET_INT_FLAG(CRPT))
- {
- s_PRNG_done = 1;
- PRNG_CLR_INT_FLAG(CRPT);
- }
-#endif
+ return result;
}
static rt_err_t nu_aes_crypt_run(
@@ -155,10 +116,9 @@ static rt_err_t nu_aes_crypt_run(
uint32_t u32DataLen
)
{
- rt_err_t result;
-
uint32_t au32SwapKey[8];
uint32_t au32SwapIV[4];
+ rt_err_t result;
au32SwapKey[0] = nu_get32_be(&pu8Key[0]);
au32SwapKey[1] = nu_get32_be(&pu8Key[4]);
@@ -187,16 +147,26 @@ static rt_err_t nu_aes_crypt_run(
//Using Channel 0
AES_Open(CRPT, 0, bEncrypt, u32OpMode, u32KeySize, AES_IN_OUT_SWAP);
- AES_SetKey(CRPT, 0, (uint32_t *)au32SwapKey, u32KeySize);
+ AES_SetKey(CRPT, 0, (uint32_t *)&au32SwapKey[0], u32KeySize);
AES_SetInitVect(CRPT, 0, (uint32_t *)au32SwapIV);
//Setup AES DMA
AES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen);
AES_CLR_INT_FLAG(CRPT);
- //Start AES encryption/decryption
- s_AES_done = 0;
+
+ /* Start AES encryption/decryption */
AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
- while (!s_AES_done) {};
+
+ /* Wait done */
+ while (!(CRPT->INTSTS & CRPT_INTEN_AESIEN_Msk)) {};
+
+ if ((u32DataLen % 16) && (CRPT->AES_STS & (CRPT_AES_STS_OUTBUFEMPTY_Msk | CRPT_AES_STS_INBUFEMPTY_Msk)))
+ rt_kprintf("AES WARNING - AES Data length(%d) is not enough. -> %d \n", u32DataLen, RT_ALIGN(u32DataLen, 16));
+ else if (CRPT->INTSTS & (CRPT_INTSTS_AESEIF_Msk) || (CRPT->AES_STS & (CRPT_AES_STS_BUSERR_Msk | CRPT_AES_STS_CNTERR_Msk)))
+ rt_kprintf("AES ERROR - CRPT->INTSTS-%08x, CRPT->AES_STS-%08x\n", CRPT->INTSTS, CRPT->AES_STS);
+
+ /* Clear AES interrupt status */
+ AES_CLR_INT_FLAG(CRPT);
result = rt_mutex_release(&s_AES_mutex);
RT_ASSERT(result == RT_EOK);
@@ -213,32 +183,33 @@ static void nu_prng_open(uint32_t u32Seed)
result = rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
- //Open PRNG 64 bits. But always return 32 bits
+ //Open PRNG 64 bits.
PRNG_Open(CRPT, PRNG_KEY_SIZE_64, PRNG_SEED_RELOAD, u32Seed);
result = rt_mutex_release(&s_PRNG_mutex);
RT_ASSERT(result == RT_EOK);
-
}
static rt_uint32_t nu_prng_run(void)
{
- rt_err_t result;
uint32_t au32RNGValue[2];
+ rt_err_t result;
result = rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
- s_PRNG_done = 0;
PRNG_Start(CRPT);
- while (!s_PRNG_done) {};
+ while ((CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)) {};
- PRNG_Read(CRPT, au32RNGValue);
+ /* Clear PRNG interrupt status */
+ PRNG_CLR_INT_FLAG(CRPT);
+
+ PRNG_Read(CRPT, &au32RNGValue[0]);
result = rt_mutex_release(&s_PRNG_mutex);
RT_ASSERT(result == RT_EOK);
- return au32RNGValue[0];
+ return au32RNGValue[0] ^ au32RNGValue[1];
}
#endif
@@ -251,6 +222,8 @@ static rt_err_t nu_aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hw
unsigned char in_align_flag = 0;
unsigned char out_align_flag = 0;
unsigned char iv_temp[16];
+ RT_ASSERT(symmetric_ctx != RT_NULL);
+ RT_ASSERT(symmetric_info != RT_NULL);
if ((symmetric_info->length % 4) != 0)
{
@@ -408,10 +381,11 @@ static rt_err_t nu_des_crypt_run(
//Setup TDES DMA
TDES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen);
TDES_CLR_INT_FLAG(CRPT);
+
//Start TDES encryption/decryption
- s_TDES_done = 0;
TDES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
- while (!s_TDES_done) {};
+ /* Wait done */
+ while (!(CRPT->INTSTS & CRPT_INTEN_TDESIEN_Msk)) {};
result = rt_mutex_release(&s_TDES_mutex);
RT_ASSERT(result == RT_EOK);
@@ -521,10 +495,6 @@ static void SHABlockUpdate(uint32_t u32OpMode, uint32_t u32SrcAddr, uint32_t u32
//Setup SHA DMA
SHA_SetDMATransfer(CRPT, u32SrcAddr, u32Len);
- SHA_CLR_INT_FLAG(CRPT);
-
- //Start SHA
- s_SHA_done = 0;
if (u32Mode == CRYPTO_DMA_FIRST)
{
@@ -547,10 +517,18 @@ static void SHABlockUpdate(uint32_t u32OpMode, uint32_t u32SrcAddr, uint32_t u32
CRPT->HMAC_CTL &= ~CRPT_HMAC_CTL_DMAFIRST_Msk;
}
}
-
+ //Start SHA
+ SHA_CLR_INT_FLAG(CRPT);
SHA_Start(CRPT, u32Mode);
- while (!s_SHA_done) {};
+ /* Wait done */
+ while (!(CRPT->INTSTS & CRPT_INTSTS_HMACIF_Msk)) {};
+
+ if (CRPT->INTSTS & (CRPT_INTSTS_HMACEIF_Msk) || (CRPT->HMAC_STS & (CRPT_HMAC_STS_DMAERR_Msk)))
+ rt_kprintf("SHA ERROR - CRPT->INTSTS-%08x, CRPT->HMAC_STS-%08x\n", CRPT->INTSTS, CRPT->HMAC_STS);
+
+ /* Clear SHA interrupt status */
+ SHA_CLR_INT_FLAG(CRPT);
}
static rt_err_t nu_sha_hash_run(
@@ -562,6 +540,9 @@ static rt_err_t nu_sha_hash_run(
{
rt_err_t result;
+ RT_ASSERT(psSHACtx != RT_NULL);
+ RT_ASSERT(pu8InData != RT_NULL);
+
result = rt_mutex_take(&s_SHA_mutex, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
@@ -603,10 +584,8 @@ static rt_err_t nu_sha_hash_run(
if (psSHACtx->pu8SHATempBuf == RT_NULL)
{
LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, psSHACtx->u32BlockSize);
-
result = rt_mutex_release(&s_SHA_mutex);
RT_ASSERT(result == RT_EOK);
-
return -RT_ENOMEM;
}
@@ -634,10 +613,8 @@ static rt_err_t nu_sha_hash_run(
if (psSHACtx->pu8SHATempBuf == RT_NULL)
{
LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, psSHACtx->u32BlockSize);
-
result = rt_mutex_release(&s_SHA_mutex);
RT_ASSERT(result == RT_EOK);
-
return -RT_ENOMEM;
}
@@ -659,6 +636,8 @@ static rt_err_t nu_sha_update(struct hwcrypto_hash *hash_ctx, const rt_uint8_t *
uint32_t u32SHAOpMode;
unsigned char *nu_in;
unsigned char in_align_flag = 0;
+ RT_ASSERT(hash_ctx != RT_NULL);
+ RT_ASSERT(in != RT_NULL);
//Select SHA operation mode
switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
@@ -713,7 +692,11 @@ static rt_err_t nu_sha_finish(struct hwcrypto_hash *hash_ctx, rt_uint8_t *out, r
unsigned char *nu_out;
unsigned char out_align_flag = 0;
uint32_t u32SHAOpMode;
- S_SHA_CONTEXT *psSHACtx = hash_ctx->parent.contex;
+ S_SHA_CONTEXT *psSHACtx = RT_NULL;
+ RT_ASSERT(hash_ctx != RT_NULL);
+ RT_ASSERT(out != RT_NULL);
+
+ psSHACtx = hash_ctx->parent.contex;
//Check SHA Hash value buffer length
switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
@@ -857,6 +840,7 @@ static const struct hwcrypto_rng_ops nu_rng_ops =
static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
{
rt_err_t res = RT_EOK;
+ RT_ASSERT(ctx != RT_NULL);
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
@@ -890,35 +874,16 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
}
case HWCRYPTO_TYPE_DES:
- {
- ctx->contex = RT_NULL;
- //Setup DES operation
- ((struct hwcrypto_symmetric *)ctx)->ops = &nu_des_ops;
- break;
- }
-
case HWCRYPTO_TYPE_3DES:
{
ctx->contex = RT_NULL;
- //Setup 3DES operation
+ //Setup operation
((struct hwcrypto_symmetric *)ctx)->ops = &nu_des_ops;
break;
}
case HWCRYPTO_TYPE_SHA1:
- {
- ctx->contex = rt_malloc(sizeof(S_SHA_CONTEXT));
-
- if (ctx->contex == RT_NULL)
- return -RT_ERROR;
-
- rt_memset(ctx->contex, 0, sizeof(S_SHA_CONTEXT));
- //Setup SHA1 operation
- ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
- break;
- }
-
case HWCRYPTO_TYPE_SHA2:
{
ctx->contex = rt_malloc(sizeof(S_SHA_CONTEXT));
@@ -927,7 +892,7 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
return -RT_ERROR;
rt_memset(ctx->contex, 0, sizeof(S_SHA_CONTEXT));
- //Setup SHA2 operation
+ //Setup operation
((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
break;
}
@@ -953,11 +918,15 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
break;
}
+ nu_hwcrypto_reset(ctx);
+
return res;
}
static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx)
{
+ RT_ASSERT(ctx != RT_NULL);
+
if (ctx->contex)
rt_free(ctx->contex);
}
@@ -965,6 +934,8 @@ static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx)
static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
rt_err_t res = RT_EOK;
+ RT_ASSERT(des != RT_NULL);
+ RT_ASSERT(src != RT_NULL);
if (des->contex && src->contex)
{
@@ -1015,8 +986,8 @@ static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx)
}
break;
}
-#endif
+#endif
default:
break;
}
@@ -1026,6 +997,7 @@ static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx)
int nu_hwcrypto_device_init(void)
{
+ rt_err_t result;
static struct rt_hwcrypto_device nu_hwcrypto_dev;
nu_hwcrypto_dev.ops = &nu_hwcrypto_ops;
@@ -1044,11 +1016,9 @@ int nu_hwcrypto_device_init(void)
nu_trng_init();
#endif
- // register hwcrypto operation
- if (rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
- {
- return -1;
- }
+ /* register hwcrypto operation */
+ result = rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME);
+ RT_ASSERT(result == RT_EOK);
return 0;
}
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
index d1f71407ac..b7082d1ae4 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
@@ -99,7 +99,7 @@ static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u3
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
- switch (RT_I2C_DEV_CTRL_CLK)
+ switch (u32Cmd)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
index 7c92743bd3..a4f49958c4 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
@@ -19,10 +19,12 @@
#include
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
/* Private define ---------------------------------------------------------------*/
@@ -453,8 +455,6 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
{
rt_bool_t ret = RT_FALSE;
-#if defined(RT_USING_DFS)
-
struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path);
if (psFS == RT_NULL)
{
@@ -469,8 +469,6 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
ret = RT_FALSE;
}
-#endif
-
exit_nu_sdh_hotplug_is_mounted:
return ret;
@@ -480,8 +478,6 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
rt_err_t ret = RT_ERROR;
DIR *t;
-#if defined(RT_USING_DFS)
-
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE)
{
ret = RT_EOK;
@@ -529,7 +525,6 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
exit_nu_sdh_hotplug_mount:
-#endif
return -(ret);
}
@@ -537,7 +532,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
{
rt_err_t ret = RT_ERROR;
-#if defined(RT_USING_DFS)
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE)
{
ret = RT_EOK;
@@ -554,7 +548,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
rt_kprintf("Succeed to unmount %s.\n", sdh->mounted_point);
ret = RT_EOK;
}
-#endif
exit_nu_sdh_hotplug_unmount:
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c
index dfffc0ebb3..a7bfdb4cb9 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_trng.c
@@ -77,10 +77,8 @@ rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx)
{
if (!s_i32TRNGEnable)
{
- uint32_t u32RNGValue;
- //use software rand
- u32RNGValue = rand();
- return u32RNGValue;
+ /* Use software rand */
+ return (rt_uint32_t)rand();
}
return nu_trng_run();
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
index c82a706c9b..0df76a63ad 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
@@ -472,7 +472,7 @@ static void int_xfer_done_cb(UTR_T *psUTR)
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
- rt_usbh_event_signal(&msg);
+ rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
@@ -880,7 +880,7 @@ int nu_usbh_register(void)
RT_ASSERT(res == RT_EOK);
/*initialize the usb host function */
- res = rt_usb_host_init();
+ res = rt_usb_host_init("usbh");
RT_ASSERT(res == RT_EOK);
#if defined(RT_USING_PM)
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_can.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_can.h
index b13064996d..8eb3a1463c 100644
--- a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_can.h
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_can.h
@@ -151,8 +151,8 @@ typedef struct
#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */
#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */
-#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */
-#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */
+#define CAN_IIDR_INTID_Pos (0) /*!< CAN_T::IIDR: IntId Position */
+#define CAN_IIDR_INTID_Msk (0xfffful << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: IntId Mask */
#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */
#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_lcd.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_lcd.h
index bf05c3f9a9..69b7c747a8 100644
--- a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_lcd.h
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_lcd.h
@@ -171,11 +171,17 @@ typedef struct
uint32_t *pFrameBuffer; /*!< User input, The address of OSD source image */
} OSDFORMATEX;
-#define DIS_PANEL_E50A2V1 0
-#define DIS_PANEL_ILI9341_MPU80 1
-#define DIS_LSA40AT9001 2
-#define DIS_PANEL_FW070TFT 3
-#define DIS_PANEL_FW043TFT 4
+enum DIS_PANEL
+{
+ DIS_PANEL_E50A2V1 = 0,
+ DIS_PANEL_ILI9341_MPU80,
+ DIS_LSA40AT9001,
+ DIS_PANEL_FW070TFT,
+ DIS_PANEL_FW043TFT,
+ DIS_PANEL_FW070TFT_WSVGA,
+ DIS_PANEL_CNT
+};
+
typedef struct
{
uint32_t u32DevWidth; /*!< Panel width */
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_uart.h b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_uart.h
index 4f24a2d10d..898c181eb5 100644
--- a/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_uart.h
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Include/nu_uart.h
@@ -770,4 +770,8 @@ void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_wid
/*@}*/ /* end of group N9H30_Device_Driver */
+#ifdef __cplusplus
+}
+#endif
+
#endif
diff --git a/bsp/nuvoton/libraries/n9h30/Driver/Source/nu_lcd.c b/bsp/nuvoton/libraries/n9h30/Driver/Source/nu_lcd.c
index d71d110096..82887e427f 100644
--- a/bsp/nuvoton/libraries/n9h30/Driver/Source/nu_lcd.c
+++ b/bsp/nuvoton/libraries/n9h30/Driver/Source/nu_lcd.c
@@ -168,9 +168,82 @@ static VPOST_T DEF_FW043TFT =
}
};
+#define FW070TFT_WSVGA_WIDTH 1024 /*!< XRES */
+#define FW070TFT_WSVGA_HEIGHT 600 /*!< YRES */
+#define FW070TFT_WSVGA_MARGIN_LEFT 160 /*!< HBP (Horizontal Back Porch) */
+#define FW070TFT_WSVGA_MARGIN_RIGHT 160 /*!< HFP (Horizontal Front Porch) */
+#define FW070TFT_WSVGA_MARGIN_UPPER 12 /*!< VBP (Vertical Back Porch) */
+#define FW070TFT_WSVGA_MARGIN_LOWER 23 /*!< VFP (Vertical Front Porch) */
+#define FW070TFT_WSVGA_HSYNC_LEN 1 /*!< HPW (HSYNC plus width) */
+#define FW070TFT_WSVGA_VSYNC_LEN 1 /*!< VPW (VSYNC width) */
+static VPOST_T DEF_FW070TFT_WSVGA =
+{
+ FW070TFT_WSVGA_WIDTH, /*!< Panel width */
+ FW070TFT_WSVGA_HEIGHT, /*!< Panel height */
+ 0, /*!< MPU command line low indicator */
+ 0, /*!< MPU command width */
+ 0, /*!< MPU bus width */
+ VPOSTB_DATA16or18, /*!< Display bus width */
+ 0, /*!< MPU mode */
+ VPOSTB_COLORTYPE_16M, /*!< Display colors */
+ VPOSTB_DEVICE_SYNC_HIGHCOLOR, /*!< Type of display panel */
+
+ .sCRTCSIZE =
+ {
+ /*!< Horizontal Total */
+ .HTT = FW070TFT_WSVGA_MARGIN_LEFT + FW070TFT_WSVGA_WIDTH + FW070TFT_WSVGA_MARGIN_RIGHT,
+
+ /*!< Vertical Total */
+ .VTT = FW070TFT_WSVGA_MARGIN_UPPER + FW070TFT_WSVGA_HEIGHT + FW070TFT_WSVGA_MARGIN_LOWER,
+ },
+ .sCRTCDEND =
+ {
+ /*!< Horizontal Display Enable End */
+ .HDEND = FW070TFT_WSVGA_WIDTH,
+
+ /*!< Vertical Display Enable End */
+ .VDEND = FW070TFT_WSVGA_HEIGHT,
+ },
+ .sCRTCHR =
+ {
+ /*!< Internal Horizontal Retrace Start Timing */
+ .HRS = FW070TFT_WSVGA_WIDTH + 1,
+
+ /*!< Internal Horizontal Retrace End Low */
+ .HRE = FW070TFT_WSVGA_WIDTH + 5,
+ },
+ .sCRTCHSYNC =
+ {
+ /*!< Horizontal Sync Start Timing */
+ .HSYNC_S = FW070TFT_WSVGA_WIDTH + FW070TFT_WSVGA_MARGIN_LEFT,
+
+ /*!< Horizontal Sync End Timing */
+ .HSYNC_E = FW070TFT_WSVGA_WIDTH + FW070TFT_WSVGA_MARGIN_LEFT + FW070TFT_WSVGA_HSYNC_LEN,
+
+ /*!< Hsync Signal Adjustment For Multi-Cycles Per Pixel Mode Of Sync-Based Unipac-LCD */
+ .HSYNC_SHIFT = 0,
+ },
+ .sCRTCVR =
+ {
+ /*!< Vertical Internal Retrace Start Timing */
+ .VRS = FW070TFT_WSVGA_HEIGHT + FW070TFT_WSVGA_MARGIN_UPPER,
+
+ /*!< Vertical Internal Retrace End Low */
+ .VRE = FW070TFT_WSVGA_HEIGHT + FW070TFT_WSVGA_MARGIN_UPPER + FW070TFT_WSVGA_VSYNC_LEN,
+ }
+};
/* LCD build-in support list */
-static VPOST_T *DisplayDevList[5] = {&DEF_E50A2V1, &DEF_ILI9341_MPU80, &DEF_LSA40AT9001, &DEF_FW070TFT, &DEF_FW043TFT};
+static VPOST_T *DisplayDevList[DIS_PANEL_CNT] =
+{
+ &DEF_E50A2V1,
+ &DEF_ILI9341_MPU80,
+ &DEF_LSA40AT9001,
+ &DEF_FW070TFT,
+ &DEF_FW043TFT,
+ &DEF_FW070TFT_WSVGA
+};
+
static VPOST_T curDisplayDev;
static OSDFORMATEX curOSDDev = {0};
static LCDFORMATEX curVADev = {0};
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig b/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig
index f57b439f00..8d480dacf1 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig
@@ -273,6 +273,7 @@ config SOC_SERIES_N9H30
menuconfig BSP_USING_SDH
bool "Enable Secure Digital Host Controller(SDH)"
select RT_USING_DFS
+ select DFS_USING_POSIX
if BSP_USING_SDH
@@ -475,6 +476,9 @@ config SOC_SERIES_N9H30
config LCM_USING_FW043TFT
bool "LCM_FW043TFT(480x272-RGB888)"
+ config LCM_USING_FW070TFT_WSVGA
+ bool "LCM_USING_FW070TFT_WSVGA(1024x600-RGB888)"
+
endchoice
config VPOST_USING_LCD_IDX
@@ -483,6 +487,7 @@ config SOC_SERIES_N9H30
default 2 if LCM_USING_LSA40AT9001
default 3 if LCM_USING_FW070TFT
default 4 if LCM_USING_FW043TFT
+ default 5 if LCM_USING_FW070TFT_WSVGA
config BSP_LCD_BPP
int
@@ -490,6 +495,7 @@ config SOC_SERIES_N9H30
default 16 if LCM_USING_LSA40AT9001
default 32 if LCM_USING_FW070TFT
default 32 if LCM_USING_FW043TFT
+ default 32 if LCM_USING_FW070TFT_WSVGA
config BSP_LCD_WIDTH
int
@@ -497,6 +503,7 @@ config SOC_SERIES_N9H30
default 800 if LCM_USING_LSA40AT9001
default 800 if LCM_USING_FW070TFT
default 480 if LCM_USING_FW043TFT
+ default 1024 if LCM_USING_FW070TFT_WSVGA
config BSP_LCD_HEIGHT
int
@@ -504,6 +511,7 @@ config SOC_SERIES_N9H30
default 600 if LCM_USING_LSA40AT9001
default 480 if LCM_USING_FW070TFT
default 272 if LCM_USING_FW043TFT
+ default 600 if LCM_USING_FW070TFT_WSVGA
config BSP_USING_VPOST_OSD
bool "Enable VPOST OSD layer"
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c
index 5ce1c64276..d1dcba7d5b 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c
@@ -35,24 +35,27 @@ struct nu_adc
uint32_t chn_mask;
rt_sem_t m_psSem;
+#if defined(BSP_USING_ADC_TOUCH)
rt_touch_t psRtTouch;
rt_timer_t psRtTouchMenuTimer;
+ rt_mq_t m_pmqTouchXYZ;
+#endif
nu_adc_cb m_isr[eAdc_ISR_CNT];
nu_adc_cb m_wkisr[eAdc_WKISR_CNT];
-
- rt_mq_t m_pmqTouchXYZ;
};
typedef struct nu_adc *nu_adc_t;
+#if defined(BSP_USING_ADC_TOUCH)
struct nu_adc_touch_data
{
- uint16_t u16X;
- uint16_t u16Y;
- uint16_t u16Z0;
- uint16_t u16Z1;
+ uint32_t u32X;
+ uint32_t u32Y;
+ uint32_t u32Z0;
+ uint32_t u32Z1;
};
typedef struct nu_adc_touch_data *nu_adc_touch_data_t;
+#endif
/* Private functions ------------------------------------------------------------*/
static rt_err_t nu_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled);
@@ -134,6 +137,64 @@ static rt_err_t _nu_adc_init(rt_device_t dev)
return RT_EOK;
}
+static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)userData;
+
+#if defined(BSP_USING_ADC_TOUCH)
+
+ static struct nu_adc_touch_data point;
+ static rt_bool_t bDrop = RT_FALSE;
+ static uint32_t u32LastZ0 = 0xffffu;
+
+ if (psNuAdc->psRtTouch != RT_NULL)
+ {
+ uint32_t value;
+
+ value = inpw(REG_ADC_XYDATA);
+ point.u32X = (value & 0x0ffful);
+ point.u32Y = ((value >> 16) & 0x0ffful);
+
+ value = inpw(REG_ADC_ZDATA);
+ point.u32Z0 = (value & 0x0ffful);
+ point.u32Z1 = ((value >> 16) & 0x0ffful);
+
+ /* Trigger next or not. */
+ if (point.u32Z0 == 0)
+ {
+ /* Stop sampling procedure. */
+ rt_timer_stop(g_sNuADC.psRtTouchMenuTimer);
+
+ /* Re-start pendown detection */
+ nu_adc_touch_detect(RT_TRUE);
+
+ bDrop = RT_TRUE;
+ }
+ else
+ {
+ bDrop = RT_FALSE;
+ }
+
+ /* Notify upper layer. */
+ if ((!bDrop || (u32LastZ0 != 0)) && rt_mq_send(psNuAdc->m_pmqTouchXYZ, (const void *)&point, sizeof(struct nu_adc_touch_data)) == RT_EOK)
+ {
+ rt_hw_touch_isr(psNuAdc->psRtTouch);
+ }
+
+ u32LastZ0 = point.u32Z0;
+ }
+ else
+#endif
+ {
+ rt_err_t result = rt_sem_release(psNuAdc->m_psSem);
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ return 0;
+}
+
+#if defined(BSP_USING_ADC_TOUCH)
+
void nu_adc_touch_detect(rt_bool_t bStartDetect)
{
nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
@@ -150,60 +211,6 @@ void nu_adc_touch_detect(rt_bool_t bStartDetect)
}
}
-static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData)
-{
- static struct nu_adc_touch_data point;
- static rt_bool_t bDrop = RT_FALSE;
- static uint16_t u16LastZ0 = 0xfffful;
-
- nu_adc_t psNuAdc = (nu_adc_t)userData;
-
- if (psNuAdc->psRtTouch != RT_NULL)
- {
- uint32_t value;
-
- value = inpw(REG_ADC_XYDATA);
- point.u16X = (uint16_t)(value & 0x0ffful);
- point.u16Y = (uint16_t)((value >> 16) & 0x0ffful);
-
- value = inpw(REG_ADC_ZDATA);
- point.u16Z0 = (uint16_t)(value & 0x0ffful);
- point.u16Z1 = (uint16_t)((value >> 16) & 0x0ffful);
-
- /* Trigger next or not. */
- if (point.u16Z0 == 0)
- {
- /* Stop sampling procedure. */
- rt_timer_stop(g_sNuADC.psRtTouchMenuTimer);
-
- /* Re-start pendown detection */
- nu_adc_touch_detect(RT_TRUE);
-
- bDrop = RT_TRUE;
- }
- else
- {
- bDrop = RT_FALSE;
- }
-
- /* Notify upper layer. */
- if ((!bDrop || (u16LastZ0 != 0)) && rt_mq_send(psNuAdc->m_pmqTouchXYZ, (const void *)&point, sizeof(struct nu_adc_touch_data)) == RT_EOK)
- {
- rt_hw_touch_isr(psNuAdc->psRtTouch);
- }
-
- u16LastZ0 = point.u16Z0;
- }
- else
- {
- rt_err_t result = rt_sem_release(psNuAdc->m_psSem);
- RT_ASSERT(result == RT_EOK);
- }
-
- return 0;
-}
-
-
static int32_t PenDownCallback(uint32_t status, uint32_t userData)
{
nu_adc_touch_detect(RT_FALSE);
@@ -213,7 +220,7 @@ static int32_t PenDownCallback(uint32_t status, uint32_t userData)
return 0;
}
-int32_t nu_adc_read_touch_xyz(uint16_t *bufX, uint16_t *bufY, uint16_t *bufZ0, uint16_t *bufZ1, int32_t dataCnt)
+int32_t nu_adc_touch_read_xyz(uint32_t *bufX, uint32_t *bufY, uint32_t *bufZ0, uint32_t *bufZ1, int32_t dataCnt)
{
int i;
struct nu_adc_touch_data value;
@@ -223,14 +230,71 @@ int32_t nu_adc_read_touch_xyz(uint16_t *bufX, uint16_t *bufY, uint16_t *bufZ0, u
if (rt_mq_recv(g_sNuADC.m_pmqTouchXYZ, (void *)&value, sizeof(struct nu_adc_touch_data), 0) == -RT_ETIMEOUT)
break;
- bufX[i] = value.u16X;
- bufY[i] = value.u16Y;
- bufZ0[i] = value.u16Z0;
- bufZ1[i] = value.u16Z1;
+ bufX[i] = value.u32X;
+ bufY[i] = value.u32Y;
+ bufZ0[i] = value.u32Z0;
+ bufZ1[i] = value.u32Z1;
}
return i;
}
+void nu_adc_touch_start_conv(void)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+ _nu_adc_control((rt_device_t)psNuAdc, START_MST, RT_NULL);
+}
+
+rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+ nu_adc_cb sNuAdcCb;
+
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 4);
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 5);
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 6);
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 7);
+
+ outpw(REG_ADC_CONF, (inpw(REG_ADC_CONF) & ~(0xfful << 24)) | 0xfful << 24);
+
+ /* Register touch device. */
+ psNuAdc->psRtTouch = psRtTouch;
+
+ /* Enable TouchXY. */
+ _nu_adc_control((rt_device_t)psNuAdc, T_ON, RT_NULL);
+
+ /* Enable TouchZZ. */
+ _nu_adc_control((rt_device_t)psNuAdc, Z_ON, RT_NULL);
+
+ /* Register PenDown callback. */
+ sNuAdcCb.cbfunc = PenDownCallback;
+ sNuAdcCb.private_data = (rt_uint32_t)psRtTouch;
+ _nu_adc_control((rt_device_t)psNuAdc, PEDEF_ON, (void *)&sNuAdcCb);
+
+ nu_adc_touch_detect(RT_TRUE);
+
+ return RT_EOK;
+}
+
+rt_err_t nu_adc_touch_disable(void)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+
+ nu_adc_touch_detect(RT_FALSE);
+
+ _nu_adc_control((rt_device_t)psNuAdc, T_OFF, RT_NULL);
+ _nu_adc_control((rt_device_t)psNuAdc, Z_OFF, RT_NULL);
+ _nu_adc_control((rt_device_t)psNuAdc, PEDEF_OFF, RT_NULL);
+
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 4);
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 5);
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 6);
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 7);
+
+ return RT_EOK;
+}
+
+#endif
+
static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EINVAL ;
@@ -443,7 +507,9 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args)
case Z_OFF: /* Disable Press measure function */
{
outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_ZEN);
+#if defined(BSP_USING_ADC_TOUCH)
rt_mq_control(psNuAdc->m_pmqTouchXYZ, RT_IPC_CMD_RESET, RT_NULL);
+#endif
}
break;
@@ -522,61 +588,6 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args)
return RT_EOK;
}
-void nu_adc_touch_start_conv(void)
-{
- nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
- _nu_adc_control((rt_device_t)psNuAdc, START_MST, RT_NULL);
-}
-
-rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch)
-{
- nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
- nu_adc_cb sNuAdcCb;
-
- rt_adc_enable((rt_adc_device_t)psNuAdc, 4);
- rt_adc_enable((rt_adc_device_t)psNuAdc, 5);
- rt_adc_enable((rt_adc_device_t)psNuAdc, 6);
- rt_adc_enable((rt_adc_device_t)psNuAdc, 7);
-
- outpw(REG_ADC_CONF, (inpw(REG_ADC_CONF) & ~(0xfful << 24)) | 0xfful << 24);
-
- /* Register touch device. */
- psNuAdc->psRtTouch = psRtTouch;
-
- /* Enable TouchXY. */
- _nu_adc_control((rt_device_t)psNuAdc, T_ON, RT_NULL);
-
- /* Enable TouchZZ. */
- _nu_adc_control((rt_device_t)psNuAdc, Z_ON, RT_NULL);
-
- /* Register PenDown callback. */
- sNuAdcCb.cbfunc = PenDownCallback;
- sNuAdcCb.private_data = (rt_uint32_t)psRtTouch;
- _nu_adc_control((rt_device_t)psNuAdc, PEDEF_ON, (void *)&sNuAdcCb);
-
- nu_adc_touch_detect(RT_TRUE);
-
- return RT_EOK;
-}
-
-rt_err_t nu_adc_touch_disable(void)
-{
- nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
-
- nu_adc_touch_detect(RT_FALSE);
-
- _nu_adc_control((rt_device_t)psNuAdc, T_OFF, RT_NULL);
- _nu_adc_control((rt_device_t)psNuAdc, Z_OFF, RT_NULL);
- _nu_adc_control((rt_device_t)psNuAdc, PEDEF_OFF, RT_NULL);
-
- rt_adc_disable((rt_adc_device_t)psNuAdc, 4);
- rt_adc_disable((rt_adc_device_t)psNuAdc, 5);
- rt_adc_disable((rt_adc_device_t)psNuAdc, 6);
- rt_adc_disable((rt_adc_device_t)psNuAdc, 7);
-
- return RT_EOK;
-}
-
static rt_err_t _nu_adc_open(rt_device_t dev, rt_uint16_t oflag)
{
nu_adc_t psNuAdc = (nu_adc_t)dev;
@@ -709,11 +720,13 @@ int rt_hw_adc_init(void)
g_sNuADC.m_psSem = rt_sem_create("adc_mst_sem", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(g_sNuADC.m_psSem != RT_NULL);
+#if defined(BSP_USING_ADC_TOUCH)
g_sNuADC.m_pmqTouchXYZ = rt_mq_create("ADC_TOUCH_XYZ", sizeof(struct nu_adc_touch_data), TOUCH_MQ_LENGTH, RT_IPC_FLAG_FIFO);
RT_ASSERT(g_sNuADC.m_pmqTouchXYZ != RT_NULL);
g_sNuADC.psRtTouchMenuTimer = rt_timer_create("TOUCH_SMPL_TIMER", nu_adc_touch_smpl, (void *)&g_sNuADC, DEF_ADC_TOUCH_SMPL_TICK, RT_TIMER_FLAG_PERIODIC);
RT_ASSERT(g_sNuADC.psRtTouchMenuTimer != RT_NULL);
+#endif
rt_memset(&g_sNuADC.m_isr, 0, sizeof(g_sNuADC.m_isr));
rt_memset(&g_sNuADC.m_wkisr, 0, sizeof(g_sNuADC.m_wkisr));
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.h b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.h
index 2269f1f35c..ead185e0c1 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.h
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.h
@@ -15,9 +15,13 @@
#include
#include "nu_adc.h"
-#include "touch.h"
+#if defined(BSP_USING_ADC_TOUCH)
+ #include "touch.h"
+#endif
-#define TOUCH_MQ_LENGTH 128
+#define TOUCH_MQ_LENGTH 64
+
+#define DEF_CAL_POINT_NUM 5
typedef enum
{
@@ -52,13 +56,29 @@ typedef struct
typedef nu_adc_cb *nu_adc_cb_t;
-int32_t nu_adc_read_touch_xyz(uint16_t *bufX, uint16_t *bufY, uint16_t *bufZ0, uint16_t *bufZ1, int32_t dataCnt);
+#if defined(BSP_USING_ADC_TOUCH)
+typedef struct
+{
+ int32_t x;
+ int32_t y;
+} S_COORDINATE_POINT;
+
+typedef struct
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ int32_t d;
+ int32_t e;
+ int32_t f;
+ int32_t div;
+} S_CALIBRATION_MATRIX;
+
+int32_t nu_adc_touch_read_xyz(uint32_t *bufX, uint32_t *bufY, uint32_t *bufZ0, uint32_t *bufZ1, int32_t dataCnt);
rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch);
rt_err_t nu_adc_touch_disable(void);
void nu_adc_touch_detect(rt_bool_t bStartDetect);
void nu_adc_touch_start_conv(void);
-
-void nu_adc_touch_update_caldata(int *psi32NewValue);
-void nu_adc_touch_reset_caldata(int *psi32NewValue);
+#endif
#endif /* __DRV_ADC_H__ */
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc_touch.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc_touch.c
index fb1f4433cf..5eeea0eb05 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc_touch.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc_touch.c
@@ -15,9 +15,19 @@
#include "NuMicro.h"
#include
+#include
+#include
+#include
+#include
+#include
#include "drv_adc.h"
#include "touch.h"
+#if !defined(PATH_CALIBRATION_FILE)
+ #define PATH_CALIBRATION_FILE "/mnt/filesystem/ts_calibration"
+#endif
+
+
typedef struct
{
struct rt_touch_device dev;
@@ -28,41 +38,135 @@ typedef nu_adc_touch *nu_adc_touch_t;
static nu_adc_touch s_NuAdcTouch = {0};
-#define DEF_CALDATA_LENGTH 7
-
-#if defined(LCM_USING_FW043TFT)
- #define LCM_WIDTH 480
- #define LCM_HEIGHT 272
- static int cal_data_a[DEF_CALDATA_LENGTH] = { 8824, -34, -2261272, -70, -6302, 21805816, 65536 };
+#if (BSP_LCD_WIDTH==480) && (BSP_LCD_HEIGHT==272)
+static S_CALIBRATION_MATRIX g_sCalMat = { 8824, -34, -2261272, -70, -6302, 21805816, 65536 };
+static volatile uint32_t g_u32Calibrated = 1;
+#elif (BSP_LCD_WIDTH==800) && (BSP_LCD_HEIGHT==480)
+static S_CALIBRATION_MATRIX g_sCalMat = { 13230, -66, -1161952, -85, 8600, -1636996, 65536 };
+static volatile uint32_t g_u32Calibrated = 1;
#else
- #define LCM_WIDTH 800
- #define LCM_HEIGHT 480
- #if defined(LCM_USING_FW070TFT)
- static int cal_data_a[DEF_CALDATA_LENGTH] = { 13230, -66, -1161952, -85, 8600, -1636996, 65536 };
- #else
- static int cal_data_a[DEF_CALDATA_LENGTH] = { 1, 0, 0, 0, 1, 0, 1 };
- #endif
+static S_CALIBRATION_MATRIX g_sCalMat = { 1, 0, 0, 0, 1, 0, 1 };
+static volatile uint32_t g_u32Calibrated = 0;
#endif
-static const int cal_zero[DEF_CALDATA_LENGTH] = { 1, 0, 0, 0, 1, 0, 1 };
+static int nu_adc_touch_readfile(void);
-static void nu_adc_touch_cal(int *sumx, int *sumy)
+static const S_CALIBRATION_MATRIX g_sCalZero = { 1, 0, 0, 0, 1, 0, 1 };
+
+static int nu_adc_cal_mat_get(const S_COORDINATE_POINT *psDispCP, S_COORDINATE_POINT *psADCCP, S_CALIBRATION_MATRIX *psCM)
{
- int xtemp, ytemp;
+#if (DEF_CAL_POINT_NUM==3)
+
+ psCM->div = ((psADCCP[0].x - psADCCP[2].x) * (psADCCP[1].y - psADCCP[2].y)) -
+ ((psADCCP[1].x - psADCCP[2].x) * (psADCCP[0].y - psADCCP[2].y)) ;
+
+ if (psCM->div == 0)
+ {
+ return -1;
+ }
+ else
+ {
+ psCM->a = ((psDispCP[0].x - psDispCP[2].x) * (psADCCP[1].y - psADCCP[2].y)) -
+ ((psDispCP[1].x - psDispCP[2].x) * (psADCCP[0].y - psADCCP[2].y)) ;
+
+ psCM->b = ((psADCCP[0].x - psADCCP[2].x) * (psDispCP[1].x - psDispCP[2].x)) -
+ ((psDispCP[0].x - psDispCP[2].x) * (psADCCP[1].x - psADCCP[2].x)) ;
+
+ psCM->c = (psADCCP[2].x * psDispCP[1].x - psADCCP[1].x * psDispCP[2].x) * psADCCP[0].y +
+ (psADCCP[0].x * psDispCP[2].x - psADCCP[2].x * psDispCP[0].x) * psADCCP[1].y +
+ (psADCCP[1].x * psDispCP[0].x - psADCCP[0].x * psDispCP[1].x) * psADCCP[2].y ;
+
+ psCM->d = ((psDispCP[0].y - psDispCP[2].y) * (psADCCP[1].y - psADCCP[2].y)) -
+ ((psDispCP[1].y - psDispCP[2].y) * (psADCCP[0].y - psADCCP[2].y)) ;
+
+ psCM->e = ((psADCCP[0].x - psADCCP[2].x) * (psDispCP[1].y - psDispCP[2].y)) -
+ ((psDispCP[0].y - psDispCP[2].y) * (psADCCP[1].x - psADCCP[2].x)) ;
+
+ psCM->f = (psADCCP[2].x * psDispCP[1].y - psADCCP[1].x * psDispCP[2].y) * psADCCP[0].y +
+ (psADCCP[0].x * psDispCP[2].y - psADCCP[2].x * psDispCP[0].y) * psADCCP[1].y +
+ (psADCCP[1].x * psDispCP[0].y - psADCCP[0].x * psDispCP[1].y) * psADCCP[2].y ;
+ }
+
+#elif (DEF_CAL_POINT_NUM==5)
+
+ int i;
+ float n, x, y, xx, yy, xy, z, zx, zy;
+ float a, b, c, d, e, f, g;
+ float scaling = 65536.0f;
+
+ n = x = y = xx = yy = xy = 0;
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ n += 1.0;
+ x += (float)psADCCP[i].x;
+ y += (float)psADCCP[i].y;
+ xx += (float)psADCCP[i].x * psADCCP[i].x;
+ yy += (float)psADCCP[i].y * psADCCP[i].y;
+ xy += (float)psADCCP[i].x * psADCCP[i].y;
+ }
+
+ d = n * (xx * yy - xy * xy) + x * (xy * y - x * yy) + y * (x * xy - y * xx);
+ if (d < 0.1 && d > -0.1)
+ {
+ return -1;
+ }
+
+ a = (xx * yy - xy * xy) / d;
+ b = (xy * y - x * yy) / d;
+ c = (x * xy - y * xx) / d;
+ e = (n * yy - y * y) / d;
+ f = (x * y - n * xy) / d;
+ g = (n * xx - x * x) / d;
+
+ z = zx = zy = 0;
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ z += (float)psDispCP[i].x;
+ zx += (float)psDispCP[i].x * psADCCP[i].x;
+ zy += (float)psDispCP[i].x * psADCCP[i].y;
+ }
+
+ psCM->c = (int32_t)((a * z + b * zx + c * zy) * scaling);
+ psCM->a = (int32_t)((b * z + e * zx + f * zy) * scaling);
+ psCM->b = (int32_t)((c * z + f * zx + g * zy) * scaling);
+
+ z = zx = zy = 0;
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ z += (float)psDispCP[i].y;
+ zx += (float)psDispCP[i].y * psADCCP[i].x;
+ zy += (float)psDispCP[i].y * psADCCP[i].y;
+ }
+
+ psCM->f = (int32_t)((a * z + b * zx + c * zy) * scaling);
+ psCM->d = (int32_t)((b * z + e * zx + f * zy) * scaling);
+ psCM->e = (int32_t)((c * z + f * zx + g * zy) * scaling);
+
+ psCM->div = (int32_t)scaling;
+
+#else
+#error "Not supported calibration method"
+#endif
+ return 0;
+}
+
+static void nu_adc_touch_cal(int32_t *sumx, int32_t *sumy)
+{
+ int32_t xtemp, ytemp;
xtemp = *sumx;
ytemp = *sumy;
- *sumx = (cal_data_a[2] +
- cal_data_a[0] * xtemp +
- cal_data_a[1] * ytemp) / cal_data_a[6];
- *sumy = (cal_data_a[5] +
- cal_data_a[3] * xtemp +
- cal_data_a[4] * ytemp) / cal_data_a[6];
+ *sumx = (g_sCalMat.c +
+ g_sCalMat.a * xtemp +
+ g_sCalMat.b * ytemp) / g_sCalMat.div;
+ *sumy = (g_sCalMat.f +
+ g_sCalMat.d * xtemp +
+ g_sCalMat.e * ytemp) / g_sCalMat.div;
}
static rt_size_t nu_adc_touch_readpoint(struct rt_touch_device *device, void *buf, rt_size_t read_num)
{
- static int last_report_x = 0, last_report_y = 0;
+ static uint32_t last_report_x = 0, last_report_y = 0;
struct rt_touch_data *pPoint = (struct rt_touch_data *)buf;
nu_adc_touch_t psNuAdcTouch = (nu_adc_touch_t)device;
@@ -73,38 +177,44 @@ static rt_size_t nu_adc_touch_readpoint(struct rt_touch_device *device, void *bu
for (i = 0; i < read_num; i++)
{
- int bufZ0 = 0, bufZ1 = 0;
- int sumx = 0, sumy = 0;
+ uint32_t bufZ0 = 0, bufZ1 = 0;
+ int32_t sumx = 0, sumy = 0;
pPoint[i].timestamp = rt_touch_get_ts();
pPoint[i].track_id = 0;
- if (nu_adc_read_touch_xyz((uint16_t *)&sumx, (uint16_t *)&sumy, (uint16_t *)&bufZ0, (uint16_t *)&bufZ1, 1) != 1)
+ if (nu_adc_touch_read_xyz((uint32_t *)&sumx, (uint32_t *)&sumy, &bufZ0, &bufZ1, 1) != 1)
break;
if (bufZ0 == 0)
{
/* Workaround: In this case, x, y values are unstable. so, report last point's coordinate.*/
pPoint[i].event = RT_TOUCH_EVENT_UP;
- pPoint[i].x_coordinate = last_report_x;
- pPoint[i].y_coordinate = last_report_y;
+ pPoint[i].x_coordinate = (uint16_t)last_report_x;
+ pPoint[i].y_coordinate = (uint16_t)last_report_y;
}
else
{
- nu_adc_touch_cal(&sumx, &sumy);
- pPoint[i].event = RT_TOUCH_EVENT_DOWN;
- pPoint[i].x_coordinate = sumx;
- pPoint[i].y_coordinate = sumy;
+ if (g_u32Calibrated)
+ {
+ nu_adc_touch_cal(&sumx, &sumy);
+ }
last_report_x = sumx;
last_report_y = sumy;
+
+ pPoint[i].event = RT_TOUCH_EVENT_DOWN;
+ pPoint[i].x_coordinate = (uint16_t)sumx;
+ pPoint[i].y_coordinate = (uint16_t)sumy;
}
- bufZ0 = bufZ0 >> 3;
+ if (g_u32Calibrated)
+ {
+ bufZ0 = bufZ0 >> 3;
+ pPoint[i].width = (bufZ0 > 255) ? 255 : bufZ0;
- pPoint[i].width = (bufZ0 > 255) ? 255 : bufZ0;
-
- //Limit max x, y coordinate if value is over its range.
- pPoint[i].x_coordinate = (pPoint[i].x_coordinate > psNuAdcTouch->x_range) ? psNuAdcTouch->x_range : pPoint[i].x_coordinate;
- pPoint[i].y_coordinate = (pPoint[i].y_coordinate > psNuAdcTouch->y_range) ? psNuAdcTouch->y_range : pPoint[i].y_coordinate;
+ //Limit max x, y coordinate if value is over its range.
+ pPoint[i].x_coordinate = (pPoint[i].x_coordinate > psNuAdcTouch->x_range) ? psNuAdcTouch->x_range : pPoint[i].x_coordinate;
+ pPoint[i].y_coordinate = (pPoint[i].y_coordinate > psNuAdcTouch->y_range) ? psNuAdcTouch->y_range : pPoint[i].y_coordinate;
+ }
}
return (rt_size_t)i;
}
@@ -150,14 +260,29 @@ static struct rt_touch_ops touch_ops =
.touch_control = nu_adc_touch_control,
};
-void nu_adc_touch_update_caldata(int *psi32NewValue)
+static void nu_adc_touch_update_calmat(S_CALIBRATION_MATRIX *psNewCalMat)
{
- rt_memcpy(&cal_data_a[0], &psi32NewValue[0], sizeof(cal_data_a));
+ if (psNewCalMat &&
+ psNewCalMat->div != 0)
+ {
+ rt_memcpy(&g_sCalMat, psNewCalMat, sizeof(S_CALIBRATION_MATRIX));
+ g_u32Calibrated = 1;
+ rt_kprintf("Applied calibration data: %d, %d, %d, %d, %d, %d, %d\n",
+ g_sCalMat.a,
+ g_sCalMat.b,
+ g_sCalMat.c,
+ g_sCalMat.d,
+ g_sCalMat.e,
+ g_sCalMat.f,
+ g_sCalMat.div);
+
+ }
}
-void nu_adc_touch_reset_caldata(int *psi32NewValue)
+static void nu_adc_touch_reset_calmat(void)
{
- rt_memcpy(&cal_data_a[0], &cal_zero[0], sizeof(cal_data_a));
+ rt_memcpy(&g_sCalMat, &g_sCalZero, sizeof(S_CALIBRATION_MATRIX));
+ g_u32Calibrated = 0;
}
int rt_hw_adc_touch_init(void)
@@ -166,8 +291,8 @@ int rt_hw_adc_touch_init(void)
s_NuAdcTouch.dev.info.type = RT_TOUCH_TYPE_RESISTANCE;
s_NuAdcTouch.dev.info.vendor = RT_TOUCH_VENDOR_UNKNOWN;
s_NuAdcTouch.dev.info.point_num = 1;
- s_NuAdcTouch.dev.info.range_x = LCM_WIDTH;
- s_NuAdcTouch.dev.info.range_y = LCM_HEIGHT;
+ s_NuAdcTouch.dev.info.range_x = BSP_LCD_WIDTH;
+ s_NuAdcTouch.dev.info.range_y = BSP_LCD_HEIGHT;
s_NuAdcTouch.dev.ops = &touch_ops;
@@ -179,10 +304,268 @@ INIT_DEVICE_EXPORT(rt_hw_adc_touch_init);
static rt_thread_t adc_touch_thread = RT_NULL;
static rt_sem_t adc_touch_sem = RT_NULL;
static int adc_touch_worker_run = 0;
+
static rt_err_t adc_touch_rx_callback(rt_device_t dev, rt_size_t size)
{
- rt_sem_release(adc_touch_sem);
+ //rt_kprintf("[%s %d] %d\n", __func__, __LINE__, size);
+ return rt_sem_release(adc_touch_sem);
+}
+
+static rt_err_t adc_request_point(rt_device_t pdev, struct rt_touch_data *psTouchPoint)
+{
+ rt_err_t ret = -RT_ERROR;
+
+ if ((ret = rt_sem_take(adc_touch_sem, rt_tick_from_millisecond(500))) == RT_EOK)
+ {
+ rt_memset(psTouchPoint, 0, sizeof(struct rt_touch_data));
+
+ if (rt_device_read(pdev, 0, psTouchPoint, s_NuAdcTouch.dev.info.point_num) == s_NuAdcTouch.dev.info.point_num)
+ {
+ ret = RT_EOK;
+ }
+
+ }
+
+ return ret;
+}
+
+RT_WEAK void nu_touch_inputevent_cb(rt_int16_t x, rt_int16_t y, rt_uint8_t event)
+{
+}
+
+static rt_device_t lcd_device = 0;
+static struct rt_device_graphic_info info;
+
+static void lcd_cleanscreen(void)
+{
+ if (info.framebuffer != RT_NULL)
+ {
+ /* Rendering */
+ struct rt_device_rect_info rect;
+
+ rt_memset(info.framebuffer, 0, (info.pitch * info.height));
+ rect.x = 0;
+ rect.y = 0;
+ rect.width = info.width;
+ rect.height = info.height;
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
+ }
+ else
+ {
+ // TODO
+ }
+}
+
+#define DEF_DOT_NUMBER 9
+#define DOTS_NUMBER (DEF_DOT_NUMBER*DEF_DOT_NUMBER)
+static void nu_draw_bots(int x, int y)
+{
+ if (info.framebuffer != RT_NULL)
+ {
+ /* Rendering */
+ struct rt_device_rect_info rect;
+ int i, j;
+ int start_x = x - (DEF_DOT_NUMBER / 2);
+ int start_y = y - (DEF_DOT_NUMBER / 2);
+
+ if (info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565)
+ {
+ uint16_t *pu16Start = (uint16_t *)((uint32_t)info.framebuffer + (start_y) * info.pitch + (start_x * 2));
+ for (j = 0; j < DEF_DOT_NUMBER; j++)
+ {
+ for (i = 0; i < DEF_DOT_NUMBER; i++)
+ pu16Start[i] = 0x07E0; //Green, RGB
+ pu16Start += info.width;
+ }
+ }
+ else if (info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888)
+ {
+ uint32_t *pu32Start = (uint32_t *)((uint32_t)info.framebuffer + (start_y) * info.pitch + (start_x * 4));
+ for (j = 0; j < DEF_DOT_NUMBER; j++)
+ {
+ for (i = 0; i < DEF_DOT_NUMBER; i++)
+ pu32Start[i] = 0xff00ff00; //Green, ARGB
+ pu32Start += info.width;
+ }
+ }
+ else
+ {
+ //Not supported
+ }
+
+ rect.x = 0;
+ rect.y = 0;
+ rect.width = info.width;
+ rect.height = info.height;
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
+ }
+ else
+ {
+ // TODO
+ }
+}
+
+#if (DEF_CAL_POINT_NUM==3)
+const S_COORDINATE_POINT sDispPoints[DEF_CAL_POINT_NUM] =
+{
+ {BSP_LCD_WIDTH / 4, BSP_LCD_HEIGHT / 2},
+ {BSP_LCD_WIDTH - BSP_LCD_WIDTH / 4, BSP_LCD_HEIGHT / 4},
+ {BSP_LCD_WIDTH / 2, BSP_LCD_HEIGHT - BSP_LCD_HEIGHT / 4}
+};
+#elif (DEF_CAL_POINT_NUM==5)
+const static S_COORDINATE_POINT sDispPoints[DEF_CAL_POINT_NUM] =
+{
+#define DEF_CUT_PIECES 8
+ {BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+ {BSP_LCD_WIDTH - BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+ {BSP_LCD_WIDTH - BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT - BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+ {BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT - BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+
+ {BSP_LCD_WIDTH / 2, BSP_LCD_HEIGHT / 2}
+};
+#endif
+
+static int nu_adc_touch_readfile(void)
+{
+ int fd;
+
+ S_CALIBRATION_MATRIX sCalMat;
+
+ if ((fd = open(PATH_CALIBRATION_FILE, O_RDONLY, 0)) < 0)
+ {
+ goto exit_nu_adc_touch_readfile;
+ }
+ else if (read(fd, &sCalMat, sizeof(S_CALIBRATION_MATRIX)) == sizeof(S_CALIBRATION_MATRIX))
+ {
+ rt_kprintf("[%s] %s\n", __func__, PATH_CALIBRATION_FILE);
+ }
+
+ close(fd);
+
+ nu_adc_touch_update_calmat(&sCalMat);
+
return 0;
+
+exit_nu_adc_touch_readfile:
+
+ return -1;
+}
+
+static int nu_adc_touch_writefile(void *buf, int buf_len)
+{
+ int fd;
+
+ if ((fd = open(PATH_CALIBRATION_FILE, O_WRONLY | O_CREAT, 0)) < 0)
+ {
+ goto exit_nu_adc_touch_writefile;
+ }
+ else if (write(fd, buf, buf_len) == buf_len)
+ {
+ rt_kprintf("[%s] %s\n", __func__, PATH_CALIBRATION_FILE);
+ }
+
+ close(fd);
+
+ return 0;
+
+exit_nu_adc_touch_writefile:
+
+ return -1;
+}
+
+static void nu_touch_do_calibration(rt_device_t pdev)
+{
+ int i;
+ rt_err_t result;
+
+ S_CALIBRATION_MATRIX sCalMat;
+ S_COORDINATE_POINT sADCPoints[DEF_CAL_POINT_NUM];
+
+ lcd_device = rt_device_find("lcd");
+ if (!lcd_device)
+ {
+ rt_kprintf("Not supported graphics ops\n");
+ return;
+ }
+
+ result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info);
+ if (result != RT_EOK)
+ {
+ rt_kprintf("error!");
+ return;
+ }
+
+ result = rt_device_open(lcd_device, 0);
+ if (result != RT_EOK)
+ {
+ rt_kprintf("opened?");
+ }
+
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, info.framebuffer);
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL);
+
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ struct rt_touch_data sTouchPoint;
+ int count = 0;
+
+ lcd_cleanscreen();
+
+ /* Drain RX queue before doing calibrate. */
+ while (adc_request_point(pdev, &sTouchPoint) == RT_EOK);
+
+ rt_thread_mdelay(100);
+
+ /* Ready to calibrate */
+ nu_draw_bots(sDispPoints[i].x, sDispPoints[i].y);
+
+#define DEF_MAX_GET_POINT_NUM 5
+
+ sADCPoints[i].x = 0;
+ sADCPoints[i].y = 0;
+
+ while (count < DEF_MAX_GET_POINT_NUM)
+ {
+ if (adc_request_point(pdev, &sTouchPoint) == RT_EOK)
+ {
+ sADCPoints[i].x += (int32_t)sTouchPoint.x_coordinate;
+ sADCPoints[i].y += (int32_t)sTouchPoint.y_coordinate;
+ rt_kprintf("[%d %d] - Disp:[%d, %d] -> ADC:[%d, %d]\n", i, count, sDispPoints[i].x, sDispPoints[i].y, sADCPoints[i].x, sADCPoints[i].y);
+ count++;
+ }
+ }
+
+ sADCPoints[i].x = (int32_t)((float)sADCPoints[i].x / DEF_MAX_GET_POINT_NUM);
+ sADCPoints[i].y = (int32_t)((float)sADCPoints[i].y / DEF_MAX_GET_POINT_NUM);
+ rt_kprintf("[%d] - Disp:[%d, %d], ADC:[%d, %d]\n", i, sDispPoints[i].x, sDispPoints[i].y, sADCPoints[i].x, sADCPoints[i].y);
+
+ rt_thread_mdelay(300);
+ }
+
+ lcd_cleanscreen();
+
+ /* Get calibration matrix. */
+ if (nu_adc_cal_mat_get(&sDispPoints[0], &sADCPoints[0], &sCalMat) == 0)
+ {
+ /* Finally, update calibration matrix to drivers. */
+ nu_adc_touch_update_calmat(&sCalMat);
+
+ nu_adc_touch_writefile(&sCalMat, sizeof(sCalMat));
+
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ rt_kprintf("[%d] - Disp:[%d, %d], ADC:[%d, %d]\n", i, sDispPoints[i].x, sDispPoints[i].y, sADCPoints[i].x, sADCPoints[i].y);
+ }
+ }
+ else
+ {
+ rt_kprintf("Failed to calibrate.\n");
+ }
+
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWEROFF, RT_NULL);
+ rt_device_close(lcd_device);
+
+ return;
}
static void adc_touch_entry(void *parameter)
@@ -190,66 +573,63 @@ static void adc_touch_entry(void *parameter)
struct rt_touch_data touch_point;
rt_err_t result;
- rt_device_t pdev = &s_NuAdcTouch.dev.parent;
+ rt_device_t pdev;
int max_range;
adc_touch_sem = rt_sem_create("adc_touch_sem", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(adc_touch_sem != RT_NULL);
+ pdev = rt_device_find("adc_touch");
+ if (!pdev)
+ {
+ rt_kprintf("Not found\n");
+ return ;
+ }
+
+ nu_adc_touch_readfile();
+
result = rt_device_open(pdev, RT_DEVICE_FLAG_INT_RX);
RT_ASSERT(result == RT_EOK);
result = rt_device_set_rx_indicate(pdev, adc_touch_rx_callback);
RT_ASSERT(result == RT_EOK);
- max_range = LCM_WIDTH;
+ max_range = BSP_LCD_WIDTH;
result = rt_device_control(pdev, RT_TOUCH_CTRL_SET_X_RANGE, (void *)&max_range);
RT_ASSERT(result == RT_EOK);
- max_range = LCM_HEIGHT;
+ max_range = BSP_LCD_HEIGHT;
result = rt_device_control(pdev, RT_TOUCH_CTRL_SET_Y_RANGE, (void *)&max_range);
RT_ASSERT(result == RT_EOK);
- // nu_adc_touch_reset_caldata(int *psi32NewValue);
- // nu_adc_touch_update_caldata(int *psi32NewValue);
-
result = rt_device_control(pdev, RT_TOUCH_CTRL_POWER_ON, RT_NULL);
RT_ASSERT(result == RT_EOK);
while (adc_touch_worker_run)
{
- if ((-RT_ETIMEOUT == rt_sem_take(adc_touch_sem, rt_tick_from_millisecond(100))))
+ if (!g_u32Calibrated)
+ {
+ rt_kprintf("Start ADC touching calibration.\n");
+ nu_touch_do_calibration(pdev);
+ rt_kprintf("Stop ADC touching calibration.\n");
continue;
+ }
- rt_memset(&touch_point, 0, sizeof(struct rt_touch_data));
-
- if (rt_device_read(pdev, 0, &touch_point, s_NuAdcTouch.dev.info.point_num) == s_NuAdcTouch.dev.info.point_num)
+ if (adc_request_point(pdev, &touch_point) == RT_EOK)
{
if (touch_point.event == RT_TOUCH_EVENT_DOWN
|| touch_point.event == RT_TOUCH_EVENT_UP
|| touch_point.event == RT_TOUCH_EVENT_MOVE)
{
-
-#if defined(PKG_USING_LVGL)
- extern void nu_touch_inputevent_cb(rt_int16_t x, rt_int16_t y, rt_uint8_t state);
nu_touch_inputevent_cb(touch_point.x_coordinate, touch_point.y_coordinate, touch_point.event);
-#elif defined(PKG_USING_LITTLEVGL2RTT)
- extern void littlevgl2rtt_send_input_event(rt_int16_t x, rt_int16_t y, rt_uint8_t state);
- littlevgl2rtt_send_input_event(touch_point.x_coordinate, touch_point.y_coordinate, touch_point.event);
-#endif
-#if defined(PKG_USING_NUEMWIN)
- extern void nuemwin_send_input_event(rt_int16_t x, rt_int16_t y, rt_uint8_t state);
- nuemwin_send_input_event(touch_point.x_coordinate, touch_point.y_coordinate, touch_point.event);
-#endif
- rt_kprintf("[%d-%d] id=%d width=%d x=%d y=%d\n",
- touch_point.timestamp,
- touch_point.event,
- touch_point.track_id,
- touch_point.width,
+ rt_kprintf("x=%d y=%d event=%s%s%s\n",
touch_point.x_coordinate,
- touch_point.y_coordinate);
+ touch_point.y_coordinate,
+ (touch_point.event == RT_TOUCH_EVENT_DOWN) ? "DOWN" : "",
+ (touch_point.event == RT_TOUCH_EVENT_UP) ? "UP" : "",
+ (touch_point.event == RT_TOUCH_EVENT_MOVE) ? "MOVE" : "");
}
}
}
@@ -270,7 +650,7 @@ static rt_err_t nu_touch_start(int argc, char **argv)
adc_touch_thread = rt_thread_create("adc_touch_thread",
adc_touch_entry,
RT_NULL,
- 1024,
+ 4096,
25,
5);
adc_touch_worker_run = 1;
@@ -290,4 +670,19 @@ static rt_err_t nu_touch_stop(int argc, char **argv)
}
MSH_CMD_EXPORT(nu_touch_stop, e.g: stop adc touch);
+static int nu_touch_autostart(void)
+{
+ return nu_touch_start(0, RT_NULL);
+}
+INIT_APP_EXPORT(nu_touch_autostart);
+
+static rt_err_t nu_touch_calibration(int argc, char **argv)
+{
+ /* Clean calibration matrix data for getting raw adc value. */
+ nu_adc_touch_reset_calmat();
+
+ return 0;
+}
+MSH_CMD_EXPORT(nu_touch_calibration, for adc touch);
+
#endif //#if defined(BSP_USING_ADC_TOUCH)
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_can.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_can.c
index a4da2879cf..aedd61f018 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_can.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_can.c
@@ -58,6 +58,7 @@ struct nu_can
IRQn_Type irqn;
E_SYS_IPRST rstidx;
E_SYS_IPCLK clkidx;
+ uint32_t int_flag;
};
typedef struct nu_can *nu_can_t;
@@ -106,16 +107,16 @@ static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT;
/* Interrupt Handle Function ----------------------------------------------------*/
static void nu_can_isr(int vector, void *param)
{
- uint32_t u32IIDRstatus;
nu_can_t psNuCAN = (nu_can_t)param;
/* Get base address of CAN register */
CAN_T *base = psNuCAN->base;
/* Get interrupt event */
- u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(base);
+ uint32_t u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(base) & CAN_IIDR_INTID_Msk;
- if (u32IIDRstatus == 0x00008000) /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ if (u32IIDRstatus == 0x00008000)
{
/**************************/
/* Status Change interrupt*/
@@ -123,20 +124,24 @@ static void nu_can_isr(int vector, void *param)
if (base->STATUS & CAN_STATUS_TXOK_Msk)
{
base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
- //rt_kprintf("%s: TX\n", psNuCAN->name) ;
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
+ }
#endif
}
if (base->STATUS & CAN_STATUS_RXOK_Msk)
{
base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
- //rt_kprintf("%s: RX\n", psNuCAN->name) ;
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_RX_IND);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_RX_IND);
+ }
#endif
}
@@ -145,17 +150,16 @@ static void nu_can_isr(int vector, void *param)
/**************************/
if (base->STATUS & CAN_STATUS_EWARN_Msk)
{
- rt_kprintf("%s: EWARN\n", psNuCAN->name) ;
+ rt_kprintf("[%s]EWARN INT\n", psNuCAN->name) ;
}
if (base->STATUS & CAN_STATUS_BOFF_Msk)
{
- rt_kprintf("%s: BUSOFF\n", psNuCAN->name) ;
+ rt_kprintf("[%s]BUSOFF INT\n", psNuCAN->name) ;
- /* Do Init to release busoff pin */
- base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
- base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
- while (base->CON & CAN_CON_INIT_Msk);
+ /* To release busoff pin */
+ CAN_EnterInitMode(base, CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+ CAN_LeaveInitMode(base);
}
if (base->STATUS & CAN_STATUS_LEC_Msk)
@@ -168,66 +172,83 @@ static void nu_can_isr(int vector, void *param)
/*IntId: 0x0001-0x0020, Number of Message Object which caused the interrupt.*/
else if (u32IIDRstatus > 0 && u32IIDRstatus <= 32)
{
- /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
- if (u32IIDRstatus <= RX_MSG_ID_INDEX)
+ if ((psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX) &&
+ (u32IIDRstatus <= RX_MSG_ID_INDEX))
{
- //rt_kprintf("[%s-Tx]IntId = %d\n", psNuCAN->name, u32IIDRstatus);
+ /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
}
- else /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+ else if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
{
- //rt_kprintf("[%s-Rx]IntId = %d\n", psNuCAN->name, u32IIDRstatus);
+ /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
rt_hw_can_isr(&psNuCAN->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
}
CAN_CLR_INT_PENDING_BIT(base, (u32IIDRstatus - 1)); /* Clear Interrupt Pending */
}
#endif
-
}
+static void nu_can_ie(nu_can_t psNuCAN)
+{
+ uint32_t u32CanIE = CAN_CON_IE_Msk;
+
+ if (psNuCAN->int_flag & (RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX))
+ {
+ u32CanIE |= CAN_CON_SIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_SIE_Msk;
+ }
+
+ if (psNuCAN->int_flag & RT_DEVICE_CAN_INT_ERR)
+ {
+ u32CanIE |= CAN_CON_EIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_EIE_Msk;
+ }
+
+ if (u32CanIE & (CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))
+ {
+ CAN_EnableInt(psNuCAN->base, u32CanIE);
+
+ /* Enable interrupt. */
+ rt_hw_interrupt_umask(psNuCAN->irqn);
+ }
+ else
+ {
+ u32CanIE |= (CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+ CAN_DisableInt(psNuCAN->base, u32CanIE);
+
+ /* Disable interrupt. */
+ rt_hw_interrupt_mask(psNuCAN->irqn);
+ }
+}
static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg)
{
nu_can_t psNuCAN = (nu_can_t)can;
+ uint32_t u32CANMode;
- RT_ASSERT(can != RT_NULL);
- RT_ASSERT(cfg != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(cfg);
/* Get base address of CAN register */
CAN_T *base = psNuCAN->base;
- RT_ASSERT(base != RT_NULL);
-
- switch (cfg->mode)
- {
- /* CAN default Normal mode */
- case RT_CAN_MODE_NORMAL:
- can->config.mode = CAN_NORMAL_MODE;
- break;
- case RT_CAN_MODE_LISEN:
- can->config.mode = RT_CAN_MODE_LISEN;
- break;
- case RT_CAN_MODE_LOOPBACK:
- can->config.mode = RT_CAN_MODE_LOOPBACK;
- break;
- case RT_CAN_MODE_LOOPBACKANLISEN:
- can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN;
- break;
- default:
- rt_kprintf("Unsupported Operating mode");
- goto exit_nu_can_configure;
- }
-
+ /* Reset this module */
nu_sys_ip_reset(psNuCAN->rstidx);
- /*Set the CAN Bit Rate and Operating mode*/
- if (CAN_Open(base, can->config.baud_rate, can->config.mode) < 1)
- return -(RT_ERROR);
+ u32CANMode = (cfg->mode == RT_CAN_MODE_NORMAL) ? CAN_NORMAL_MODE : CAN_BASIC_MODE;
+ /*Set the CAN Bit Rate and Operating mode*/
+ if (CAN_Open(base, cfg->baud_rate, u32CANMode) != cfg->baud_rate)
+ goto exit_nu_can_configure;
switch (cfg->mode)
{
- /* CAN default Normal mode */
case RT_CAN_MODE_NORMAL:
#ifdef RT_CAN_USING_HDR
CAN_LeaveTestMode(base);
@@ -249,6 +270,7 @@ static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure
goto exit_nu_can_configure;
}
+ nu_can_ie(psNuCAN);
return RT_EOK;
@@ -261,73 +283,33 @@ exit_nu_can_configure:
static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
- rt_uint32_t argval;
- nu_can_t psNuCAN = (nu_can_t)can;
+ rt_uint32_t argval = (rt_uint32_t)arg;
+ nu_can_t psNuCAN = (nu_can_t)can;
-#ifdef RT_CAN_USING_HDR
- struct rt_can_filter_config *filter_cfg;
-#endif
- /* Get base address of CAN register */
- CAN_T *base = psNuCAN->base;
-
- RT_ASSERT(base != RT_NULL);
- /* Check baud rate */
- RT_ASSERT(can->config.baud_rate != 0);
+ RT_ASSERT(can);
switch (cmd)
{
- case RT_DEVICE_CTRL_CLR_INT:
- argval = (rt_uint32_t) arg;
- if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Disable NVIC interrupt. */
- rt_hw_interrupt_mask(psNuCAN->irqn);
-
- /* Disable Status Change Interrupt */
- CAN_DisableInt(base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
-
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Disable interrupt. */
- rt_hw_interrupt_mask(psNuCAN->irqn);
-
- /* Disable Error Interrupt */
- CAN_DisableInt(base, CAN_CON_EIE_Msk);
- }
- break;
-
case RT_DEVICE_CTRL_SET_INT:
- argval = (rt_uint32_t) arg;
- if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Enable Status Change Interrupt */
- CAN_EnableInt(base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
-
- /* Enable interrupt. */
- rt_hw_interrupt_umask(psNuCAN->irqn);
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Enable Error Status and Status Change Interrupt */
- CAN_EnableInt(base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
-
- /* Enable interrupt. */
- rt_hw_interrupt_umask(psNuCAN->irqn);
- }
+ psNuCAN->int_flag |= argval;
+ nu_can_ie(psNuCAN);
+ break;
+
+ case RT_DEVICE_CTRL_CLR_INT:
+ psNuCAN->int_flag &= ~argval;
+ nu_can_ie(psNuCAN);
break;
-#ifdef RT_CAN_USING_HDR
case RT_CAN_CMD_SET_FILTER:
- filter_cfg = (struct rt_can_filter_config *)arg;
+ {
+ struct rt_can_filter_config *filter_cfg = (struct rt_can_filter_config *)arg;
for (int i = 0; i < filter_cfg->count; i++)
{
-
/*set the filter message object*/
if (filter_cfg->items[i].mode == 1)
{
- if (CAN_SetRxMsgObjAndMsk(base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
+ if (CAN_SetRxMsgObjAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
{
return -(RT_ERROR);
}
@@ -335,46 +317,61 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
else
{
/*set the filter message object*/
- if (CAN_SetRxMsgAndMsk(base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
+ if (CAN_SetRxMsgAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
{
return -(RT_ERROR);
}
}
}
- break;
-#endif
+ }
+ break;
case RT_CAN_CMD_SET_MODE:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN &&
- argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN)
+ if ((argval == RT_CAN_MODE_NORMAL) ||
+ (argval == RT_CAN_MODE_LISEN) ||
+ (argval == RT_CAN_MODE_LOOPBACK) ||
+ (argval == RT_CAN_MODE_LOOPBACKANLISEN))
+ {
+ if (argval != can->config.mode)
+ {
+ can->config.mode = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.mode)
- {
- can->config.mode = argval;
- return nu_can_configure(can, &can->config);
- }
break;
case RT_CAN_CMD_SET_BAUD:
- argval = (rt_uint32_t) arg;
- if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud &&
- argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud && argval != CAN20kBaud && argval != CAN10kBaud)
+ {
+ if ((argval == CAN1MBaud) ||
+ (argval == CAN800kBaud) ||
+ (argval == CAN500kBaud) ||
+ (argval == CAN250kBaud) ||
+ (argval == CAN125kBaud) ||
+ (argval == CAN100kBaud) ||
+ (argval == CAN50kBaud) ||
+ (argval == CAN20kBaud) ||
+ (argval == CAN10kBaud))
+ {
+ if (argval != can->config.baud_rate)
+ {
+ can->config.baud_rate = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.baud_rate)
- {
- can->config.baud_rate = argval;
- return nu_can_configure(can, &can->config);
- }
- break;
+ }
+ break;
case RT_CAN_CMD_SET_PRIV:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV)
+ if (argval != RT_CAN_MODE_PRIV &&
+ argval != RT_CAN_MODE_NOPRIV)
{
return -(RT_ERROR);
}
@@ -387,16 +384,23 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
case RT_CAN_CMD_GET_STATUS:
{
- rt_uint32_t errtype;
- errtype = base->ERR;
- /*Receive Error Counter*/
+ rt_uint32_t errtype = psNuCAN->base->ERR;
+
+ RT_ASSERT(arg);
+
+ /*Receive Error Counter, return value is with Receive Error Passive.*/
can->status.rcverrcnt = (errtype >> 8);
+
/*Transmit Error Counter*/
- can->status.snderrcnt = ((errtype >> 24) & 0xFF);
- can->status.lasterrtype = CAN_GET_INT_STATUS(base) & 0x8000;
- /*status error code*/
- can->status.errcode = CAN_GET_INT_STATUS(base) & 0x07;
- rt_memcpy(arg, &can->status, sizeof(can->status));
+ can->status.snderrcnt = (errtype & 0xFF);
+
+ /*Last Error Type*/
+ can->status.lasterrtype = CAN_GET_INT_STATUS(psNuCAN->base) & 0x8000;
+
+ /*Status error code*/
+ can->status.errcode = CAN_GET_INT_STATUS(psNuCAN->base) & 0x07;
+
+ rt_memcpy(arg, &can->status, sizeof(struct rt_can_status));
}
break;
@@ -411,64 +415,91 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- /* Get base address of CAN register */
- CAN_T *base = ((nu_can_t)can)->base;
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
- RT_ASSERT(base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
+ pmsg = (struct rt_can_msg *) buf;
- /* Check the parameters */
- RT_ASSERT(IS_CAN_DLC(pmsg->len));
-
- /* Standard ID (11 bits)*/
- if (pmsg->ide == RT_CAN_STDID)
+ if (pmsg->ide == RT_CAN_STDID && IS_CAN_STDID(pmsg->id))
{
+ /* Standard ID (11 bits)*/
tMsg.IdType = CAN_STD_ID;
- RT_ASSERT(IS_CAN_STDID(pmsg->id))
tMsg.Id = pmsg->id ;
}
- else
+ else if (pmsg->ide == RT_CAN_EXTID && IS_CAN_EXTID(pmsg->id))
{
/* Extended ID (29 bits)*/
tMsg.IdType = CAN_EXT_ID;
- RT_ASSERT(IS_CAN_EXTID(pmsg->id));
tMsg.Id = pmsg->id ;
}
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
if (pmsg->rtr == RT_CAN_DTR)
{
/* Data frame */
tMsg.FrameType = CAN_DATA_FRAME;
}
- else
+ else if (pmsg->rtr == RT_CAN_RTR)
{
/* Remote frame */
tMsg.FrameType = CAN_REMOTE_FRAME;
}
- tMsg.DLC = pmsg->len;
- rt_memcpy(tMsg.Data, pmsg->data, pmsg->len);
-
- if (CAN_Transmit(base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM
+ else
{
- return -(RT_ERROR);
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Check the parameters */
+ if (IS_CAN_DLC(pmsg->len))
+ {
+ tMsg.DLC = pmsg->len;
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ if (pmsg->data && pmsg->len)
+ {
+ rt_memcpy(&tMsg.Data[0], pmsg->data, pmsg->len);
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Configure Msg RAM and send the Msg in the RAM. */
+ if (CAN_Transmit(psNuCAN->base, MSG(boxno), &tMsg) == FALSE)
+ {
+ goto exit_nu_can_sendmsg;
}
return RT_EOK;
+
+exit_nu_can_sendmsg:
+
+ return -(RT_ERROR);
}
+
static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- /* Get base address of CAN register */
- CAN_T *base = ((nu_can_t)can)->base;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- RT_ASSERT(base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pmsg = (struct rt_can_msg *) buf;
/* get data */
- if (CAN_Receive(base, boxno, &tMsg) == FALSE)
+ if (CAN_Receive(psNuCAN->base, boxno, &tMsg) == FALSE)
{
rt_kprintf("No available RX Msg.\n");
return -(RT_ERROR);
@@ -480,32 +511,13 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn
can->hdr[pmsg->hdr].connected = 1;
#endif
- /* Standard ID (11 bits)*/
- if (tMsg.IdType == CAN_STD_ID)
- {
- pmsg->ide = RT_CAN_STDID;
- pmsg->id = tMsg.Id;
- }
- else /* Extended ID (29 bits)*/
- {
- pmsg->ide = RT_CAN_EXTID;
- pmsg->id = tMsg.Id;
- }
-
- if (tMsg.FrameType == CAN_DATA_FRAME)
- {
- /* Data frame */
- pmsg->rtr = RT_CAN_DTR;
- }
- else
- {
- /* Remote frame */
- pmsg->rtr = RT_CAN_RTR;
- }
-
+ pmsg->ide = (tMsg.IdType == CAN_STD_ID) ? RT_CAN_STDID : RT_CAN_EXTID;
+ pmsg->rtr = (tMsg.FrameType == CAN_DATA_FRAME) ? RT_CAN_DTR : RT_CAN_RTR;
+ pmsg->id = tMsg.Id;
pmsg->len = tMsg.DLC ;
- rt_memcpy(pmsg->data, tMsg.Data, pmsg->len);
+ if (pmsg->data && pmsg->len)
+ rt_memcpy(pmsg->data, &tMsg.Data[0], pmsg->len);
return RT_EOK;
}
@@ -540,5 +552,4 @@ static int rt_hw_can_init(void)
return (int)ret;
}
INIT_DEVICE_EXPORT(rt_hw_can_init);
-
#endif //#if defined(BSP_USING_CAN)
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_i2c.c
index 0b4fbaabf1..987f8b3fd5 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_i2c.c
@@ -34,6 +34,8 @@
#define I2C_ENABLE(dev) I2C_REG_WRITE(dev, I2C_CSR, 0x3) /* Enable i2c core and interrupt */
#define I2C_ISBUSFREE(dev) (((I2C_REG_READ(dev, I2C_SWR) & 0x18) == 0x18 && (I2C_REG_READ(dev, I2C_CSR) & 0x0400) == 0) ? 1 : 0)
+#define I2C_SIGNAL_TIMEOUT 5000
+
enum
{
I2C_START = -1,
@@ -50,7 +52,7 @@ enum
typedef struct
{
int32_t base; /* i2c bus number */
- int32_t state;
+ volatile int32_t state;
int32_t addr;
uint32_t last_error;
int32_t bNackValid;
@@ -58,9 +60,11 @@ typedef struct
uint32_t subaddr;
int32_t subaddr_len;
- uint8_t buffer[I2C_MAX_BUF_LEN];
- uint32_t pos, len;
+ volatile uint32_t pos;
+ volatile uint32_t len;
+ uint8_t *buffer;
+ struct rt_completion signal;
} nu_i2c_dev;
typedef nu_i2c_dev *nu_i2c_dev_t;
@@ -68,7 +72,6 @@ typedef struct
{
struct rt_i2c_bus_device parent;
char *name;
-
IRQn_Type irqn;
E_SYS_IPRST rstidx;
E_SYS_IPCLK clkidx;
@@ -113,13 +116,13 @@ static nu_i2c_bus nu_i2c_arr [ ] =
* @brief Set i2c interface speed
* @param[in] dev i2c device structure pointer
* @param[in] sp i2c speed
- * @return always 0
+ * @return 0 or I2C_ERR_NOTTY
*/
static int32_t nu_i2c_set_speed(nu_i2c_dev_t psNuI2cDev, int32_t sp)
{
uint32_t d;
- if (sp != 100 && sp != 400)
+ if ((sp != 100) && (sp != 400))
return (I2C_ERR_NOTTY);
d = (sysGetClock(SYS_PCLK) * 1000) / (sp * 5) - 1;
@@ -205,6 +208,7 @@ static void nu_i2c_isr(int vector, void *param)
psNuI2CDev->last_error = I2C_ERR_NACK;
nu_i2c_command(psNuI2CDev, I2C_CMD_STOP);
psNuI2CDev->state = I2C_STATE_NOP;
+ rt_completion_done(&psNuI2CDev->signal);
}
/* Arbitration lost */
else if (csr & 0x200)
@@ -212,6 +216,7 @@ static void nu_i2c_isr(int vector, void *param)
rt_kprintf("Arbitration lost\n");
psNuI2CDev->last_error = I2C_ERR_LOSTARBITRATION;
psNuI2CDev->state = I2C_STATE_NOP;
+ rt_completion_done(&psNuI2CDev->signal);
}
/* Transmit complete */
else if (!(csr & 0x100))
@@ -225,6 +230,7 @@ static void nu_i2c_isr(int vector, void *param)
}
else if (psNuI2CDev->state == I2C_STATE_READ)
{
+
/* Sub-address send over, begin restart a read command */
if (psNuI2CDev->pos == psNuI2CDev->subaddr_len + 1)
{
@@ -246,6 +252,7 @@ static void nu_i2c_isr(int vector, void *param)
else
{
psNuI2CDev->state = I2C_STATE_NOP;
+ rt_completion_done(&psNuI2CDev->signal);
}
}
}
@@ -270,13 +277,13 @@ static void nu_i2c_isr(int vector, void *param)
else
{
psNuI2CDev->state = I2C_STATE_NOP;
+ rt_completion_done(&psNuI2CDev->signal);
}
}
}
+
}
-
-
/**
* @brief Read data from I2C slave.
* @param[in] psNuI2cDev is interface structure pointer.
@@ -294,6 +301,9 @@ static int32_t nu_i2c_read(nu_i2c_dev_t psNuI2cDev, struct rt_i2c_msg *pmsg)
uint8_t *buf = pmsg->buf;
uint32_t len = pmsg->len;
+ RT_ASSERT(len);
+ RT_ASSERT(buf);
+
if (len > I2C_MAX_BUF_LEN - 10)
len = I2C_MAX_BUF_LEN - 10;
@@ -317,9 +327,22 @@ static int32_t nu_i2c_read(nu_i2c_dev_t psNuI2cDev, struct rt_i2c_msg *pmsg)
if (!I2C_ISBUSFREE(psNuI2cDev))
return (I2C_ERR_BUSY);
+ rt_completion_init(&psNuI2cDev->signal);
+
nu_i2c_command(psNuI2cDev, I2C_CMD_START | I2C_CMD_WRITE);
- while (psNuI2cDev->state != I2C_STATE_NOP);
+ if ((RT_EOK == rt_completion_wait(&psNuI2cDev->signal, I2C_SIGNAL_TIMEOUT)))
+ {
+ rt_memcpy(buf, psNuI2cDev->buffer + psNuI2cDev->subaddr_len + 3, len);
+
+ psNuI2cDev->subaddr += len;
+ }
+ else
+ {
+ rt_kprintf("[%s]Wait signal timeout.\n", __func__);
+
+ len = 0;
+ }
/* Disable I2C-EN */
I2C_DISABLE(psNuI2cDev);
@@ -327,10 +350,6 @@ static int32_t nu_i2c_read(nu_i2c_dev_t psNuI2cDev, struct rt_i2c_msg *pmsg)
if (psNuI2cDev->last_error)
return (psNuI2cDev->last_error);
- rt_memcpy(buf, psNuI2cDev->buffer + psNuI2cDev->subaddr_len + 3, len);
-
- psNuI2cDev->subaddr += len;
-
return len;
}
@@ -351,6 +370,9 @@ static int32_t nu_i2c_write(nu_i2c_dev_t psNuI2cDev, struct rt_i2c_msg *pmsg)
uint8_t *buf = pmsg->buf;
uint32_t len = pmsg->len;
+ RT_ASSERT(len);
+ RT_ASSERT(buf);
+
if (len > I2C_MAX_BUF_LEN - 10)
len = I2C_MAX_BUF_LEN - 10;
@@ -373,9 +395,20 @@ static int32_t nu_i2c_write(nu_i2c_dev_t psNuI2cDev, struct rt_i2c_msg *pmsg)
if (!I2C_ISBUSFREE(psNuI2cDev))
return (I2C_ERR_BUSY);
+ rt_completion_init(&psNuI2cDev->signal);
+
nu_i2c_command(psNuI2cDev, I2C_CMD_START | I2C_CMD_WRITE);
- while (psNuI2cDev->state != I2C_STATE_NOP);
+ if ((RT_EOK == rt_completion_wait(&psNuI2cDev->signal, I2C_SIGNAL_TIMEOUT)))
+ {
+ psNuI2cDev->subaddr += len;
+ }
+ else
+ {
+ rt_kprintf("[%s]Wait signal timeout.\n", __func__);
+
+ len = 0;
+ }
/* Disable I2C-EN */
I2C_DISABLE(psNuI2cDev);
@@ -383,8 +416,6 @@ static int32_t nu_i2c_write(nu_i2c_dev_t psNuI2cDev, struct rt_i2c_msg *pmsg)
if (psNuI2cDev->last_error)
return (psNuI2cDev->last_error);
- psNuI2cDev->subaddr += len;
-
return len;
}
@@ -405,16 +436,13 @@ static int32_t nu_i2c_ioctl(nu_i2c_dev_t psNuI2cDev, uint32_t cmd, uint32_t arg0
switch (cmd)
{
case I2C_IOC_SET_DEV_ADDRESS:
-
psNuI2cDev->addr = arg0;
break;
case I2C_IOC_SET_SPEED:
-
- return (nu_i2c_set_speed(psNuI2cDev, (int32_t)arg0));
+ return nu_i2c_set_speed(psNuI2cDev, (int32_t)arg0);
case I2C_IOC_SET_SUB_ADDRESS:
-
if (arg1 > 4)
{
return (I2C_ERR_NOTTY);
@@ -441,7 +469,8 @@ static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
rt_err_t ret;
struct rt_i2c_msg *pmsg;
- RT_ASSERT(bus != RT_NULL);
+ RT_ASSERT(bus);
+
psNuI2cBus = (nu_i2c_bus_t) bus;
psNuI2cDev = &psNuI2cBus->dev;
@@ -459,6 +488,7 @@ static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
/* Set device address */
nu_i2c_reset(psNuI2cDev);
+
nu_i2c_ioctl(psNuI2cDev, I2C_IOC_SET_DEV_ADDRESS, pmsg->addr, 0);
if (pmsg->flags & RT_I2C_RD)
@@ -470,18 +500,39 @@ static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
ret = nu_i2c_write(psNuI2cDev, pmsg);
}
-
if (ret != pmsg->len) break;
}
return i;
}
+static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value)
+{
+ nu_i2c_bus_t psNuI2cBus;
+ nu_i2c_dev_t psNuI2cDev;
+
+ RT_ASSERT(bus);
+
+ psNuI2cBus = (nu_i2c_bus_t) bus;
+ psNuI2cDev = &psNuI2cBus->dev;
+
+ switch (u32Cmd)
+ {
+ case RT_I2C_DEV_CTRL_CLK:
+ nu_i2c_set_speed(psNuI2cDev, (int32_t)u32Value);
+ break;
+ default:
+ return -RT_EIO;
+ }
+
+ return RT_EOK;
+}
+
static const struct rt_i2c_bus_device_ops nu_i2c_ops =
{
.master_xfer = nu_i2c_mst_xfer,
.slave_xfer = NULL,
- .i2c_bus_control = NULL,
+ .i2c_bus_control = nu_i2c_bus_control,
};
@@ -489,17 +540,17 @@ static const struct rt_i2c_bus_device_ops nu_i2c_ops =
int rt_hw_i2c_init(void)
{
int i;
- rt_err_t ret = RT_EOK;
+ rt_err_t ret;
for (i = (I2C_START + 1); i < I2C_CNT; i++)
{
nu_i2c_dev_t psNuI2cDev = &nu_i2c_arr[i].dev;
- ret = rt_i2c_bus_device_register(&nu_i2c_arr[i].parent, nu_i2c_arr[i].name);
- RT_ASSERT(RT_EOK == ret);
-
nu_i2c_arr[i].parent.ops = &nu_i2c_ops;
+ psNuI2cDev->buffer = rt_malloc(I2C_MAX_BUF_LEN);
+ RT_ASSERT(psNuI2cDev->buffer);
+
/* Enable I2C engine clock and reset. */
nu_sys_ipclk_enable(nu_i2c_arr[i].clkidx);
nu_sys_ip_reset(nu_i2c_arr[i].rstidx);
@@ -509,6 +560,9 @@ int rt_hw_i2c_init(void)
/* Register ISR and Respond IRQ. */
rt_hw_interrupt_install(nu_i2c_arr[i].irqn, nu_i2c_isr, &nu_i2c_arr[i], nu_i2c_arr[i].name);
rt_hw_interrupt_umask(nu_i2c_arr[i].irqn);
+
+ ret = rt_i2c_bus_device_register(&nu_i2c_arr[i].parent, nu_i2c_arr[i].name);
+ RT_ASSERT(RT_EOK == ret);
}
return 0;
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sdh.c
index 499311c752..2ead28d452 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sdh.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_sdh.c
@@ -19,10 +19,12 @@
#include "NuMicro.h"
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
/* Private define ---------------------------------------------------------------*/
@@ -598,8 +600,6 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
{
rt_bool_t ret = RT_FALSE;
-#if defined(RT_USING_DFS)
-
struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path);
if (psFS == RT_NULL)
{
@@ -616,15 +616,11 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
exit_nu_sdh_hotplug_is_mounted:
-#endif
-
return ret;
}
static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
{
rt_err_t ret = RT_ERROR;
-
-#if defined(RT_USING_DFS)
DIR *t;
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE)
@@ -674,7 +670,6 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
exit_nu_sdh_hotplug_mount:
-#endif
return -(ret);
}
@@ -682,7 +677,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
{
rt_err_t ret = RT_ERROR;
-#if defined(RT_USING_DFS)
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE)
{
ret = RT_EOK;
@@ -702,8 +696,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
exit_nu_sdh_hotplug_unmount:
-#endif
-
return -(ret);
}
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c
index a5660ba328..64e9dbf3ae 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c
@@ -425,7 +425,7 @@ static int nu_bulk_xfer(
UTR_T *psUTR,
int timeouts)
{
- #define TIMEOUT_RETRY 3
+#define TIMEOUT_RETRY 3
int retry = TIMEOUT_RETRY;
int ret = usbh_bulk_xfer(psUTR);
@@ -435,9 +435,9 @@ static int nu_bulk_xfer(
return ret;
}
- while ( retry > 0 )
+ while (retry > 0)
{
- if ( rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0 )
+ if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0)
{
rt_uint32_t level;
@@ -513,7 +513,7 @@ static void int_xfer_done_cb(UTR_T *psUTR)
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
- rt_usbh_event_signal(&msg);
+ rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
@@ -942,7 +942,7 @@ int nu_usbh_register(void)
/*initialize the usb host function */
- res = rt_usb_host_init();
+ res = rt_usb_host_init("usbh");
RT_ASSERT(res == RT_EOK);
#if defined(RT_USING_PM)
diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_vpost.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_vpost.c
index 41fae42ae4..0f5f1e23a3 100644
--- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_vpost.c
+++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_vpost.c
@@ -69,6 +69,9 @@ static struct nu_vpost nu_fbdev[eVpost_Cnt] =
#endif
};
+RT_WEAK void nu_lcd_backlight_on(void) { }
+
+RT_WEAK void nu_lcd_backlight_off(void) { }
static rt_err_t vpost_layer_open(rt_device_t dev, rt_uint16_t oflag)
{
nu_vpost_t psVpost = (nu_vpost_t)dev;
@@ -149,6 +152,18 @@ static rt_err_t vpost_layer_control(rt_device_t dev, int cmd, void *args)
switch (cmd)
{
+ case RTGRAPHIC_CTRL_POWERON:
+ {
+ nu_lcd_backlight_on();
+ }
+ break;
+
+ case RTGRAPHIC_CTRL_POWEROFF:
+ {
+ nu_lcd_backlight_off();
+ }
+ break;
+
case RTGRAPHIC_CTRL_GET_INFO:
{
struct rt_device_graphic_info *info = (struct rt_device_graphic_info *) args;
@@ -324,6 +339,11 @@ int rt_hw_vpost_init(void)
rt_kprintf("Fail to get VRAM buffer.\n");
RT_ASSERT(0);
}
+ else
+ {
+ uint32_t u32FBSize = psVpost->info.pitch * psVpostLcmInst->u32DevHeight;
+ rt_memset(psVpost->info.framebuffer, 0, u32FBSize);
+ }
/* Register member functions of lcd device */
psVpost->dev.type = RT_Device_Class_Graphic;
diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c b/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
index d978fa4ded..6a805b3ba7 100644
--- a/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
+++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
@@ -16,7 +16,11 @@
#include "wavrecorder.h"
#include "wavplayer.h"
-#include "dfs_posix.h"
+#include
+#include
+#include
+#include
+#include
/*
The routine just for test automatically.
diff --git a/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c b/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c
index 31cb6c6d02..90829c3c8f 100644
--- a/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c
+++ b/bsp/nuvoton/libraries/nu_packages/ILI9341/lcd_ili9341.c
@@ -17,16 +17,13 @@
#include
#include
-#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
- #define DEF_VRAM_BUFFER_NUMBER 2
-#endif
-
static struct rt_device_graphic_info g_Ili9341Info =
{
.bits_per_pixel = 16,
.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565,
.framebuffer = RT_NULL,
.width = XSIZE_PHYS,
+ .pitch = XSIZE_PHYS * 2,
.height = YSIZE_PHYS
};
@@ -274,16 +271,9 @@ static rt_err_t ili9341_lcd_control(rt_device_t dev, int cmd, void *args)
case RTGRAPHIC_CTRL_RECT_UPDATE:
{
#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
- struct rt_device_rect_info *psRectInfo = args;
+ struct rt_device_rect_info *psRectInfo = (struct rt_device_rect_info *)args;
rt_uint16_t *pixels = (rt_uint16_t *)g_Ili9341Info.framebuffer;
- RT_ASSERT(args != RT_NULL);
-
- if (psRectInfo->y >= g_Ili9341Info.height)
- {
- int buf_id = psRectInfo->y / g_Ili9341Info.height;
- pixels += g_Ili9341Info.width * g_Ili9341Info.height * buf_id;
- psRectInfo->y %= g_Ili9341Info.height;
- }
+ RT_ASSERT(args);
ili9341_fillrect(pixels, psRectInfo);
#else
@@ -324,7 +314,7 @@ int rt_hw_lcd_ili9341_init(void)
lcd_device.user_data = &ili9341_ops;
#if defined(NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER)
- g_Ili9341Info.framebuffer = rt_malloc_align((DEF_VRAM_BUFFER_NUMBER * g_Ili9341Info.width * g_Ili9341Info.height * (g_Ili9341Info.bits_per_pixel / 8)) + 32, 32);
+ g_Ili9341Info.framebuffer = rt_malloc_align((g_Ili9341Info.pitch * g_Ili9341Info.height) + 32, 32);
RT_ASSERT(g_Ili9341Info.framebuffer != RT_NULL);
#endif
diff --git a/bsp/nuvoton/libraries/nu_packages/Kconfig b/bsp/nuvoton/libraries/nu_packages/Kconfig
index ab3bba4331..b27797f36a 100644
--- a/bsp/nuvoton/libraries/nu_packages/Kconfig
+++ b/bsp/nuvoton/libraries/nu_packages/Kconfig
@@ -38,7 +38,7 @@ menu "Nuvoton Packages Config"
bool "ILI9341 LCD Panel"
select BSP_USING_GPIO
default n
-
+
if NU_PKG_USING_ILI9341
choice
@@ -62,8 +62,20 @@ menu "Nuvoton Packages Config"
default n
config NU_PKG_ILI9341_HORIZONTAL
- bool "Set horizontal view. (320x240)"
- default n
+ bool
+ default y
+
+ config BSP_LCD_BPP
+ int
+ default 16 if NU_PKG_USING_ILI9341
+
+ config BSP_LCD_WIDTH
+ int
+ default 320 if NU_PKG_ILI9341_HORIZONTAL
+
+ config BSP_LCD_HEIGHT
+ int
+ default 240 if NU_PKG_ILI9341_HORIZONTAL
endif
diff --git a/bsp/nuvoton/libraries/nuc980/Driver/Include/nu_adc.h b/bsp/nuvoton/libraries/nuc980/Driver/Include/nu_adc.h
index 341e2606f0..6e814049ff 100644
--- a/bsp/nuvoton/libraries/nuc980/Driver/Include/nu_adc.h
+++ b/bsp/nuvoton/libraries/nuc980/Driver/Include/nu_adc.h
@@ -35,51 +35,142 @@ extern "C"
#define ADC_ERR_CMD 2 /*!< The command is wrong */
/// @cond HIDDEN_SYMBOLS
-typedef INT32(*ADC_CALLBACK)(UINT32 status, UINT32 userData);
+typedef int32_t(*ADC_CALLBACK)(uint32_t status, uint32_t userData);
/// @endcond HIDDEN_SYMBOLS
/*---------------------------------------------------------------------------------------------------------*/
/* ADC_CTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_CTL_ADEN 0x00000001 /*!< ADC Power Control */
-#define ADC_CTL_VBGEN 0x00000002 /*!< ADC Internal Bandgap Power Control */
+#define ADC_CTL_VBGEN 0x00000002 /*!< ADC Internal Bandgap Power Control */
+#define ADC_CTL_PWKPEN 0x00000004 /*!< ADC Keypad Power Enable Control */
#define ADC_CTL_MST 0x00000100 /*!< Menu Start Conversion */
+#define ADC_CTL_PEDEEN 0x00000200 /*!< Pen Down Event Enable */
+#define ADC_CTL_WKPEN 0x00000400 /*!< Keypad Press Wake Up Enable */
+#define ADC_CTL_WKTEN 0x00000800 /*!< Touch Wake Up Enable */
+#define ADC_CTL_WMSWCH 0x00010000 /*!< Wire Mode Switch For 5-Wire/4-Wire Configuration */
/*---------------------------------------------------------------------------------------------------------*/
/* ADC_CONF constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
+#define ADC_CONF_TEN 0x00000001 /*!< Touch Enable */
+#define ADC_CONF_ZEN 0x00000002 /*!< Press Enable */
#define ADC_CONF_NACEN 0x00000004 /*!< Normal AD Conversion Enable */
+#define ADC_CONF_VBATEN 0x00000100 /*!< Voltage Battery Enable */
+#define ADC_CONF_KPCEN 0x00000200 /*!< Keypad Press Conversion Enable */
#define ADC_CONF_SELFTEN 0x00000400 /*!< Selft Test Enable */
+#define ADC_CONF_DISTMAVEN (1<<20) /*!< Display T Mean Average Enable */
+#define ADC_CONF_DISZMAVEN (1<<21) /*!< Display Z Mean Average Enable */
#define ADC_CONF_HSPEED (1<<22) /*!< High Speed Enable */
-#define ADC_CONF_CHSEL_Pos 12 /*!< Channel Selection Position */
-#define ADC_CONF_CHSEL_Msk (0xF<psCurrentRxDesc;
@@ -1151,7 +1151,7 @@ EMAC_DESCRIPTOR_T * EMAC_RecvPktDoneWoRxTrigger(EMAC_MEMMGR_T *psMemMgr)
return ret;
}
-void EMAC_RxTrigger(EMAC_MEMMGR_T *psMemMgr, EMAC_DESCRIPTOR_T * rx_desc)
+void EMAC_RxTrigger(EMAC_MEMMGR_T *psMemMgr, EMAC_DESCRIPTOR_T *rx_desc)
{
EMAC_T *EMAC = psMemMgr->psEmac;
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
index 08ea27c97a..697685116c 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
@@ -70,6 +70,13 @@ config SOC_SERIES_NUC980
bool "Enable Analog-to-Digital Converter(ADC)"
select RT_USING_ADC
+ if BSP_USING_ADC
+ config BSP_USING_ADC_TOUCH
+ bool "Enable ADC Touching function"
+ select RT_USING_TOUCH
+ default n
+ endif
+
menuconfig BSP_USING_TMR
bool "Enable Timer Controller(TIMER)"
@@ -346,6 +353,7 @@ config SOC_SERIES_NUC980
menuconfig BSP_USING_SDH
bool "Enable Secure Digital Host Controller(SDH)"
select RT_USING_DFS
+ select DFS_USING_POSIX
if BSP_USING_SDH
config BSP_USING_SDH0
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c
index 721bd5d6c1..66d93845ab 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c
@@ -15,9 +15,12 @@
#include
#include "NuMicro.h"
-#include
+#include "drv_sys.h"
+#include "nu_bitutil.h"
+#include "drv_adc.h"
/* Private define ---------------------------------------------------------------*/
+#define DEF_ADC_TOUCH_SMPL_TICK 40
/* Private Typedef --------------------------------------------------------------*/
struct nu_adc
@@ -31,12 +34,33 @@ struct nu_adc
int chn_num;
uint32_t chn_mask;
rt_sem_t m_psSem;
+
+#if defined(BSP_USING_ADC_TOUCH)
+ rt_touch_t psRtTouch;
+ rt_timer_t psRtTouchMenuTimer;
+ rt_mq_t m_pmqTouchXYZ;
+#endif
+
+ nu_adc_cb m_isr[eAdc_ISR_CNT];
+ nu_adc_cb m_wkisr[eAdc_WKISR_CNT];
};
typedef struct nu_adc *nu_adc_t;
+#if defined(BSP_USING_ADC_TOUCH)
+struct nu_adc_touch_data
+{
+ uint32_t u32X;
+ uint32_t u32Y;
+ uint32_t u32Z0;
+ uint32_t u32Z1;
+};
+typedef struct nu_adc_touch_data *nu_adc_touch_data_t;
+#endif
+
/* Private functions ------------------------------------------------------------*/
static rt_err_t nu_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled);
static rt_err_t nu_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value);
+static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args);
/* Public functions ------------------------------------------------------------*/
int rt_hw_adc_init(void);
@@ -56,24 +80,41 @@ static struct nu_adc g_sNuADC =
static void nu_adc_isr(int vector, void *param)
{
- uint32_t isr, conf;
+ rt_int32_t isr, wkisr;
nu_adc_t psNuAdc = (nu_adc_t)param;
+ rt_int32_t irqidx;
- conf = inpw(REG_ADC_CONF);
isr = inpw(REG_ADC_ISR);
+ wkisr = inpw(REG_ADC_WKISR);
- if ((isr & ADC_ISR_NACF) && (conf & ADC_CONF_NACEN))
+ while ((irqidx = nu_ctz(isr)) < eAdc_ISR_CNT)
{
- outpw(REG_ADC_ISR, ADC_ISR_NACF);
- }
+ uint32_t u32IsrBitMask = 1 << irqidx ;
- if (isr & ADC_ISR_MF)
+ if (psNuAdc->m_isr[irqidx].cbfunc != RT_NULL)
+ {
+ //rt_kprintf("[%s] %d %x\n", __func__, irqidx, psNuAdc->m_isr[irqidx].cbfunc);
+ psNuAdc->m_isr[irqidx].cbfunc(isr, psNuAdc->m_isr[irqidx].private_data);
+ }
+
+ /* Clear sent bit */
+ outpw(REG_ADC_ISR, u32IsrBitMask);
+ isr &= ~(u32IsrBitMask);
+ } //while
+
+ while ((irqidx = nu_ctz(wkisr)) < eAdc_WKISR_CNT)
{
- rt_err_t result;
- outpw(REG_ADC_ISR, ADC_ISR_MF);
- result = rt_sem_release(psNuAdc->m_psSem);
- RT_ASSERT(result == RT_EOK);
- }
+ uint32_t u32IsrBitMask = 1 << irqidx ;
+
+ if (psNuAdc->m_wkisr[irqidx].cbfunc != RT_NULL)
+ {
+ psNuAdc->m_wkisr[irqidx].cbfunc(wkisr, psNuAdc->m_wkisr[irqidx].private_data);
+ }
+
+ /* Clear sent bit */
+ outpw(REG_ADC_WKISR, u32IsrBitMask);
+ wkisr &= ~(u32IsrBitMask);
+ } //while
}
static rt_err_t _nu_adc_init(rt_device_t dev)
@@ -96,11 +137,171 @@ static rt_err_t _nu_adc_init(rt_device_t dev)
return RT_EOK;
}
+static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)userData;
+
+#if defined(BSP_USING_ADC_TOUCH)
+
+ static struct nu_adc_touch_data point;
+ static rt_bool_t bDrop = RT_FALSE;
+ static uint32_t u32LastZ0 = 0xffffu;
+
+ if (psNuAdc->psRtTouch != RT_NULL)
+ {
+ uint32_t value;
+
+ value = inpw(REG_ADC_XYDATA);
+ point.u32X = (value & 0x0ffful);
+ point.u32Y = ((value >> 16) & 0x0ffful);
+
+ value = inpw(REG_ADC_ZDATA);
+ point.u32Z0 = (value & 0x0ffful);
+ point.u32Z1 = ((value >> 16) & 0x0ffful);
+
+ /* Trigger next or not. */
+ if (point.u32Z0 == 0)
+ {
+ /* Stop sampling procedure. */
+ rt_timer_stop(g_sNuADC.psRtTouchMenuTimer);
+
+ /* Re-start pendown detection */
+ nu_adc_touch_detect(RT_TRUE);
+
+ bDrop = RT_TRUE;
+ }
+ else
+ {
+ bDrop = RT_FALSE;
+ }
+
+ /* Notify upper layer. */
+ if ((!bDrop || (u32LastZ0 != 0)) && rt_mq_send(psNuAdc->m_pmqTouchXYZ, (const void *)&point, sizeof(struct nu_adc_touch_data)) == RT_EOK)
+ {
+ rt_hw_touch_isr(psNuAdc->psRtTouch);
+ }
+
+ u32LastZ0 = point.u32Z0;
+ }
+ else
+#endif
+ {
+ rt_err_t result = rt_sem_release(psNuAdc->m_psSem);
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ return 0;
+}
+
+#if defined(BSP_USING_ADC_TOUCH)
+
+void nu_adc_touch_detect(rt_bool_t bStartDetect)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+
+ if (bStartDetect)
+ {
+ /* Start detect PenDown */
+ _nu_adc_control((rt_device_t)psNuAdc, PEPOWER_ON, RT_NULL);
+ }
+ else
+ {
+ /* Stop detect PenDown */
+ _nu_adc_control((rt_device_t)psNuAdc, PEPOWER_OFF, RT_NULL);
+ }
+}
+
+static int32_t PenDownCallback(uint32_t status, uint32_t userData)
+{
+ nu_adc_touch_detect(RT_FALSE);
+
+ rt_timer_start(g_sNuADC.psRtTouchMenuTimer);
+
+ return 0;
+}
+
+int32_t nu_adc_touch_read_xyz(uint32_t *bufX, uint32_t *bufY, uint32_t *bufZ0, uint32_t *bufZ1, int32_t dataCnt)
+{
+ int i;
+ struct nu_adc_touch_data value;
+
+ for (i = 0 ; i < dataCnt; i++)
+ {
+ if (rt_mq_recv(g_sNuADC.m_pmqTouchXYZ, (void *)&value, sizeof(struct nu_adc_touch_data), 0) == -RT_ETIMEOUT)
+ break;
+
+ bufX[i] = value.u32X;
+ bufY[i] = value.u32Y;
+ bufZ0[i] = value.u32Z0;
+ bufZ1[i] = value.u32Z1;
+ }
+ return i;
+}
+
+void nu_adc_touch_start_conv(void)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+ _nu_adc_control((rt_device_t)psNuAdc, START_MST, RT_NULL);
+}
+
+rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+ nu_adc_cb sNuAdcCb;
+
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 4);
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 5);
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 6);
+ rt_adc_enable((rt_adc_device_t)psNuAdc, 7);
+
+ outpw(REG_ADC_CONF, (inpw(REG_ADC_CONF) & ~(0xfful << 24)) | 0xfful << 24);
+
+ /* Register touch device. */
+ psNuAdc->psRtTouch = psRtTouch;
+
+ /* Enable TouchXY. */
+ _nu_adc_control((rt_device_t)psNuAdc, T_ON, RT_NULL);
+
+ /* Enable TouchZZ. */
+ _nu_adc_control((rt_device_t)psNuAdc, Z_ON, RT_NULL);
+
+ /* Register PenDown callback. */
+ sNuAdcCb.cbfunc = PenDownCallback;
+ sNuAdcCb.private_data = (rt_uint32_t)psRtTouch;
+ _nu_adc_control((rt_device_t)psNuAdc, PEDEF_ON, (void *)&sNuAdcCb);
+
+ nu_adc_touch_detect(RT_TRUE);
+
+ return RT_EOK;
+}
+
+rt_err_t nu_adc_touch_disable(void)
+{
+ nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC;
+
+ nu_adc_touch_detect(RT_FALSE);
+
+ _nu_adc_control((rt_device_t)psNuAdc, T_OFF, RT_NULL);
+ _nu_adc_control((rt_device_t)psNuAdc, Z_OFF, RT_NULL);
+ _nu_adc_control((rt_device_t)psNuAdc, PEDEF_OFF, RT_NULL);
+
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 4);
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 5);
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 6);
+ rt_adc_disable((rt_adc_device_t)psNuAdc, 7);
+
+ return RT_EOK;
+}
+
+#endif
+
static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EINVAL ;
nu_adc_t psNuAdc = (nu_adc_t)dev;
+ nu_adc_cb_t psAdcCb = (nu_adc_cb_t)args;
+
switch (cmd)
{
case START_MST: /* Menu Start Conversion */
@@ -116,29 +317,259 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args)
RT_ASSERT(ret == RT_EOK);
/* Get data: valid data is 12-bit */
- *((uint32_t *)args) = inpw(REG_ADC_DATA) & 0x00000FFF;
+ if (args != RT_NULL)
+ *((uint32_t *)args) = inpw(REG_ADC_DATA) & 0x00000FFF;
}
break;
+
+ /* case START_MST_POLLING: Not supported. */
+
case VBPOWER_ON: /* Enable ADC Internal Bandgap Power */
{
outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_VBGEN);
}
break;
+
case VBPOWER_OFF: /* Disable ADC Internal Bandgap Power */
{
outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) & ~ADC_CTL_VBGEN);
}
break;
+
+ case KPPOWER_ON: /* Enable ADC Keypad Power */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_PWKPEN);
+ }
+ break;
+
+ case KPPOWER_OFF: /* Disable ADC Keypad Power */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) & ~ADC_CTL_PWKPEN);
+ }
+ break;
+
+ case PEPOWER_ON: /* Enable Pen Power */
+ {
+ int retry = 100;
+ uint32_t treg = inpw(REG_ADC_IER);
+ outpw(REG_ADC_IER, treg & ~(ADC_IER_PEDEIEN | ADC_IER_PEUEIEN));
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_PEDEEN);
+ do
+ {
+ outpw(REG_ADC_ISR, ADC_ISR_PEDEF | ADC_ISR_PEUEF);
+ rt_thread_mdelay(1);
+ if (retry-- == 0)
+ break;
+ }
+ while (inpw(REG_ADC_ISR) & (ADC_ISR_PEDEF | ADC_ISR_PEUEF));
+ outpw(REG_ADC_IER, treg);
+ }
+ break;
+
+ case PEPOWER_OFF: /* Disable Pen Power */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) & ~ADC_CTL_PEDEEN);
+ }
+ break;
+
+ case KPPRESS_ON: /* Enable Keypad press event */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_isr[eAdc_KPEF], psAdcCb, sizeof(nu_adc_cb));
+ }
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_KPEIEN);
+ }
+ break;
+
+ case KPPRESS_OFF: /* Disable Keypad press event */
+ {
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER & ~ADC_IER_KPEIEN));
+ }
+ break;
+
+ case KPUP_ON: /* Enable Keypad up event */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_isr[eAdc_KPUEF], psAdcCb, sizeof(nu_adc_cb));
+ }
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_KPUEIEN);
+ }
+ break;
+
+ case KPUP_OFF: /* Disable Keypad up event */
+ {
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) & ~ADC_IER_KPUEIEN);
+ }
+ break;
+
+ case PEDEF_ON: /* Enable Pen Down Event */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_isr[eAdc_PEDEF], psAdcCb, sizeof(nu_adc_cb));
+ }
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_PEDEIEN);
+ }
+ break;
+
+ case PEDEF_OFF: /* Disable Pen Down Event */
+ {
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) & ~ADC_IER_PEDEIEN);
+ }
+ break;
+
+ case WKP_ON: /* Enable Keypad Press Wake Up */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_wkisr[eAdc_WKPEF], psAdcCb, sizeof(nu_adc_cb));
+ }
+
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_WKPEN);
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_WKPIEN);
+ //outpw(REG_SYS_WKUPSER, inpw(REG_SYS_WKUPSER) | (1 << 26));
+ }
+ break;
+
+ case WKP_OFF: /* Disable Keypad Press Wake Up */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) & ~ADC_CTL_WKPEN);
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) & ~ADC_IER_WKPIEN);
+ //outpw(REG_SYS_WKUPSER, inpw(REG_SYS_WKUPSER) & ~(1 << 26));
+ }
+ break;
+
+ case WKT_ON: /* Enable Touch Wake Up */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_wkisr[eAdc_WPEDEF], psAdcCb, sizeof(nu_adc_cb));
+ }
+
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_WKTEN);
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_WKTIEN);
+ //outpw(REG_SYS_WKUPSER, inpw(REG_SYS_WKUPSER) | (1 << 26));
+ }
+ break;
+
+ case WKT_OFF: /* Disable Touch Wake Up */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) & ~ADC_CTL_WKTEN);
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) & ~ADC_IER_WKTIEN);
+ //outpw(REG_SYS_WKUPSER, inpw(REG_SYS_WKUPSER) & ~(1 << 26));
+ }
+ break;
+
+ case SWITCH_5WIRE_ON: /* Wire Mode Switch to 5-Wire */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_WMSWCH);
+ }
+ break;
+
+ case SWITCH_5WIRE_OFF: /* Wire Mode Switch to 4-Wire */
+ {
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) & ~ADC_CTL_WMSWCH);
+ }
+ break;
+
+ case T_ON: /* Enable Touch detection function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_TEN);
+ }
+ break;
+
+ case T_OFF: /* Disable Touch detection function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_TEN);
+ }
+ break;
+
+ case TAVG_ON: /* Enable Touch Mean average for X and Y function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_DISTMAVEN);
+ }
+ break;
+
+ case TAVG_OFF: /* Disable Touch Mean average for X and Y function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_DISTMAVEN);
+ }
+ break;
+
+ case Z_ON: /* Enable Press measure function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_ZEN);
+ }
+ break;
+
+ case Z_OFF: /* Disable Press measure function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_ZEN);
+#if defined(BSP_USING_ADC_TOUCH)
+ rt_mq_control(psNuAdc->m_pmqTouchXYZ, RT_IPC_CMD_RESET, RT_NULL);
+#endif
+ }
+ break;
+
+ case TZAVG_ON: /* Enable Pressure Mean average for Z1 and Z2 function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_DISZMAVEN);
+ }
+ break;
+
+ case TZAVG_OFF: /* Disable Pressure Mean average for Z1 and Z2 function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_DISZMAVEN);
+ }
+ break;
+
case NAC_ON: /* Enable Normal AD Conversion */
{
outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_NACEN | ADC_CONF_REFSEL_AVDD33);
}
break;
+
case NAC_OFF: /* Disable Normal AD Conversion */
{
outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_NACEN);
}
break;
+
+ case VBAT_ON: /* Enable Voltage Battery Conversion */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_isr[eAdc_VBF], psAdcCb, sizeof(nu_adc_cb));
+ }
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_VBATEN);
+ }
+ break;
+
+ case VBAT_OFF: /* Disable Voltage Battery */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_VBATEN);
+ }
+ break;
+
+ case KPCONV_ON: /* Enable Keypad conversion function */
+ {
+ if (psAdcCb)
+ {
+ rt_memcpy(&psNuAdc->m_isr[eAdc_KPCF], psAdcCb, sizeof(nu_adc_cb));
+ }
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) | ADC_CONF_KPCEN);
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_KPEIEN);
+ }
+ break;
+
+ case KPCONV_OFF: /* Disable Keypad conversion function */
+ {
+ outpw(REG_ADC_CONF, inpw(REG_ADC_CONF) & ~ADC_CONF_KPCEN);
+ }
+ break;
+
case SWITCH_CH:
{
int chn = (int)args;
@@ -265,6 +696,16 @@ exit_nu_adc_convert:
return (-ret) ;
}
+static void nu_adc_touch_smpl(void *p)
+{
+ /* Enable interrupt */
+ outpw(REG_ADC_IER, inpw(REG_ADC_IER) | ADC_IER_MIEN);
+
+ /* Start conversion */
+ outpw(REG_ADC_CTL, inpw(REG_ADC_CTL) | ADC_CTL_MST);
+}
+
+
int rt_hw_adc_init(void)
{
rt_err_t result = RT_ERROR;
@@ -279,8 +720,22 @@ int rt_hw_adc_init(void)
g_sNuADC.m_psSem = rt_sem_create("adc_mst_sem", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(g_sNuADC.m_psSem != RT_NULL);
+#if defined(BSP_USING_ADC_TOUCH)
+ g_sNuADC.m_pmqTouchXYZ = rt_mq_create("ADC_TOUCH_XYZ", sizeof(struct nu_adc_touch_data), TOUCH_MQ_LENGTH, RT_IPC_FLAG_FIFO);
+ RT_ASSERT(g_sNuADC.m_pmqTouchXYZ != RT_NULL);
+
+ g_sNuADC.psRtTouchMenuTimer = rt_timer_create("TOUCH_SMPL_TIMER", nu_adc_touch_smpl, (void *)&g_sNuADC, DEF_ADC_TOUCH_SMPL_TICK, RT_TIMER_FLAG_PERIODIC);
+ RT_ASSERT(g_sNuADC.psRtTouchMenuTimer != RT_NULL);
+#endif
+
+ rt_memset(&g_sNuADC.m_isr, 0, sizeof(g_sNuADC.m_isr));
+ rt_memset(&g_sNuADC.m_wkisr, 0, sizeof(g_sNuADC.m_wkisr));
+
+ g_sNuADC.m_isr[eAdc_MF].cbfunc = AdcMenuStartCallback;
+ g_sNuADC.m_isr[eAdc_MF].private_data = (UINT32)&g_sNuADC;
+
return (int)result;
}
INIT_BOARD_EXPORT(rt_hw_adc_init);
-#endif //#if defined(BSP_USING_EADC)
+#endif //#if defined(BSP_USING_ADC)
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.h b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.h
new file mode 100644
index 0000000000..ead185e0c1
--- /dev/null
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.h
@@ -0,0 +1,84 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2021-4-7 Wayne First version
+*
+******************************************************************************/
+
+#ifndef __DRV_ADC_H__
+#define __DRV_ADC_H__
+
+#include
+#include "nu_adc.h"
+#if defined(BSP_USING_ADC_TOUCH)
+ #include "touch.h"
+#endif
+
+#define TOUCH_MQ_LENGTH 64
+
+#define DEF_CAL_POINT_NUM 5
+
+typedef enum
+{
+ eAdc_MF, //0
+ eAdc_KPEF, //1
+ eAdc_PEDEF, //2
+ eAdc_KPUEF, //3
+ eAdc_PEUEF, //4
+ eAdc_TF = 8, //8
+ eAdc_ZF, //9
+ eAdc_NACF, //10
+ eAdc_VBF, //11
+ eAdc_KPCF, //12
+ eAdc_SELFTF, //13
+ eAdc_INTKP = 16, //16
+ eAdc_INTTC, //17
+ eAdc_ISR_CNT //18
+} E_ADC_ISR_EVENT;
+
+typedef enum
+{
+ eAdc_WKPEF,
+ eAdc_WPEDEF,
+ eAdc_WKISR_CNT
+} E_ADC_WKISR_EVENT;
+
+typedef struct
+{
+ ADC_CALLBACK cbfunc;
+ uint32_t private_data;
+} nu_adc_cb;
+
+typedef nu_adc_cb *nu_adc_cb_t;
+
+#if defined(BSP_USING_ADC_TOUCH)
+typedef struct
+{
+ int32_t x;
+ int32_t y;
+} S_COORDINATE_POINT;
+
+typedef struct
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ int32_t d;
+ int32_t e;
+ int32_t f;
+ int32_t div;
+} S_CALIBRATION_MATRIX;
+
+int32_t nu_adc_touch_read_xyz(uint32_t *bufX, uint32_t *bufY, uint32_t *bufZ0, uint32_t *bufZ1, int32_t dataCnt);
+rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch);
+rt_err_t nu_adc_touch_disable(void);
+void nu_adc_touch_detect(rt_bool_t bStartDetect);
+void nu_adc_touch_start_conv(void);
+#endif
+
+#endif /* __DRV_ADC_H__ */
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc_touch.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc_touch.c
new file mode 100644
index 0000000000..aa6cf1be8d
--- /dev/null
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc_touch.c
@@ -0,0 +1,685 @@
+/**************************************************************************//**
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date Author Notes
+* 2021-04-20 Wayne First version
+*
+******************************************************************************/
+
+#include
+
+#if defined(BSP_USING_ADC_TOUCH)
+
+#include "NuMicro.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drv_adc.h"
+#include "touch.h"
+
+#if !defined(PATH_CALIBRATION_FILE)
+ #define PATH_CALIBRATION_FILE "/mnt/filesystem/ts_calibration"
+#endif
+
+
+typedef struct
+{
+ struct rt_touch_device dev;
+ rt_uint32_t x_range;
+ rt_uint32_t y_range;
+} nu_adc_touch;
+typedef nu_adc_touch *nu_adc_touch_t;
+
+static nu_adc_touch s_NuAdcTouch = {0};
+
+#if (BSP_LCD_WIDTH==320) && (BSP_LCD_HEIGHT==240)
+static S_CALIBRATION_MATRIX g_sCalMat = { 43, -5839, 21672848, 4193, -11, -747882, 65536 };
+static volatile uint32_t g_u32Calibrated = 1;
+#else
+static S_CALIBRATION_MATRIX g_sCalMat = { 1, 0, 0, 0, 1, 0, 1 };
+static volatile uint32_t g_u32Calibrated = 0;
+#endif
+
+static int nu_adc_touch_readfile(void);
+
+static const S_CALIBRATION_MATRIX g_sCalZero = { 1, 0, 0, 0, 1, 0, 1 };
+
+static int nu_adc_cal_mat_get(const S_COORDINATE_POINT *psDispCP, S_COORDINATE_POINT *psADCCP, S_CALIBRATION_MATRIX *psCM)
+{
+#if (DEF_CAL_POINT_NUM==3)
+
+ psCM->div = ((psADCCP[0].x - psADCCP[2].x) * (psADCCP[1].y - psADCCP[2].y)) -
+ ((psADCCP[1].x - psADCCP[2].x) * (psADCCP[0].y - psADCCP[2].y)) ;
+
+ if (psCM->div == 0)
+ {
+ return -1;
+ }
+ else
+ {
+ psCM->a = ((psDispCP[0].x - psDispCP[2].x) * (psADCCP[1].y - psADCCP[2].y)) -
+ ((psDispCP[1].x - psDispCP[2].x) * (psADCCP[0].y - psADCCP[2].y)) ;
+
+ psCM->b = ((psADCCP[0].x - psADCCP[2].x) * (psDispCP[1].x - psDispCP[2].x)) -
+ ((psDispCP[0].x - psDispCP[2].x) * (psADCCP[1].x - psADCCP[2].x)) ;
+
+ psCM->c = (psADCCP[2].x * psDispCP[1].x - psADCCP[1].x * psDispCP[2].x) * psADCCP[0].y +
+ (psADCCP[0].x * psDispCP[2].x - psADCCP[2].x * psDispCP[0].x) * psADCCP[1].y +
+ (psADCCP[1].x * psDispCP[0].x - psADCCP[0].x * psDispCP[1].x) * psADCCP[2].y ;
+
+ psCM->d = ((psDispCP[0].y - psDispCP[2].y) * (psADCCP[1].y - psADCCP[2].y)) -
+ ((psDispCP[1].y - psDispCP[2].y) * (psADCCP[0].y - psADCCP[2].y)) ;
+
+ psCM->e = ((psADCCP[0].x - psADCCP[2].x) * (psDispCP[1].y - psDispCP[2].y)) -
+ ((psDispCP[0].y - psDispCP[2].y) * (psADCCP[1].x - psADCCP[2].x)) ;
+
+ psCM->f = (psADCCP[2].x * psDispCP[1].y - psADCCP[1].x * psDispCP[2].y) * psADCCP[0].y +
+ (psADCCP[0].x * psDispCP[2].y - psADCCP[2].x * psDispCP[0].y) * psADCCP[1].y +
+ (psADCCP[1].x * psDispCP[0].y - psADCCP[0].x * psDispCP[1].y) * psADCCP[2].y ;
+ }
+
+#elif (DEF_CAL_POINT_NUM==5)
+
+ int i;
+ float n, x, y, xx, yy, xy, z, zx, zy;
+ float a, b, c, d, e, f, g;
+ float scaling = 65536.0f;
+
+ n = x = y = xx = yy = xy = 0;
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ n += 1.0;
+ x += (float)psADCCP[i].x;
+ y += (float)psADCCP[i].y;
+ xx += (float)psADCCP[i].x * psADCCP[i].x;
+ yy += (float)psADCCP[i].y * psADCCP[i].y;
+ xy += (float)psADCCP[i].x * psADCCP[i].y;
+ }
+
+ d = n * (xx * yy - xy * xy) + x * (xy * y - x * yy) + y * (x * xy - y * xx);
+ if (d < 0.1 && d > -0.1)
+ {
+ return -1;
+ }
+
+ a = (xx * yy - xy * xy) / d;
+ b = (xy * y - x * yy) / d;
+ c = (x * xy - y * xx) / d;
+ e = (n * yy - y * y) / d;
+ f = (x * y - n * xy) / d;
+ g = (n * xx - x * x) / d;
+
+ z = zx = zy = 0;
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ z += (float)psDispCP[i].x;
+ zx += (float)psDispCP[i].x * psADCCP[i].x;
+ zy += (float)psDispCP[i].x * psADCCP[i].y;
+ }
+
+ psCM->c = (int32_t)((a * z + b * zx + c * zy) * scaling);
+ psCM->a = (int32_t)((b * z + e * zx + f * zy) * scaling);
+ psCM->b = (int32_t)((c * z + f * zx + g * zy) * scaling);
+
+ z = zx = zy = 0;
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ z += (float)psDispCP[i].y;
+ zx += (float)psDispCP[i].y * psADCCP[i].x;
+ zy += (float)psDispCP[i].y * psADCCP[i].y;
+ }
+
+ psCM->f = (int32_t)((a * z + b * zx + c * zy) * scaling);
+ psCM->d = (int32_t)((b * z + e * zx + f * zy) * scaling);
+ psCM->e = (int32_t)((c * z + f * zx + g * zy) * scaling);
+
+ psCM->div = (int32_t)scaling;
+
+#else
+#error "Not supported calibration method"
+#endif
+ return 0;
+}
+
+static void nu_adc_touch_cal(int32_t *sumx, int32_t *sumy)
+{
+ int32_t xtemp, ytemp;
+
+ xtemp = *sumx;
+ ytemp = *sumy;
+ *sumx = (g_sCalMat.c +
+ g_sCalMat.a * xtemp +
+ g_sCalMat.b * ytemp) / g_sCalMat.div;
+ *sumy = (g_sCalMat.f +
+ g_sCalMat.d * xtemp +
+ g_sCalMat.e * ytemp) / g_sCalMat.div;
+}
+
+static rt_size_t nu_adc_touch_readpoint(struct rt_touch_device *device, void *buf, rt_size_t read_num)
+{
+ static uint32_t last_report_x = 0, last_report_y = 0;
+ struct rt_touch_data *pPoint = (struct rt_touch_data *)buf;
+ nu_adc_touch_t psNuAdcTouch = (nu_adc_touch_t)device;
+
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+
+ int i;
+
+ for (i = 0; i < read_num; i++)
+ {
+ uint32_t bufZ0 = 0, bufZ1 = 0;
+ int32_t sumx = 0, sumy = 0;
+ pPoint[i].timestamp = rt_touch_get_ts();
+ pPoint[i].track_id = 0;
+
+ if (nu_adc_touch_read_xyz((uint32_t *)&sumx, (uint32_t *)&sumy, &bufZ0, &bufZ1, 1) != 1)
+ break;
+
+ if (bufZ0 == 0)
+ {
+ /* Workaround: In this case, x, y values are unstable. so, report last point's coordinate.*/
+ pPoint[i].event = RT_TOUCH_EVENT_UP;
+ pPoint[i].x_coordinate = (uint16_t)last_report_x;
+ pPoint[i].y_coordinate = (uint16_t)last_report_y;
+ }
+ else
+ {
+ if (g_u32Calibrated)
+ {
+ nu_adc_touch_cal(&sumx, &sumy);
+ }
+ last_report_x = sumx;
+ last_report_y = sumy;
+
+ pPoint[i].event = RT_TOUCH_EVENT_DOWN;
+ pPoint[i].x_coordinate = (uint16_t)sumx;
+ pPoint[i].y_coordinate = (uint16_t)sumy;
+ }
+
+ if (g_u32Calibrated)
+ {
+ bufZ0 = bufZ0 >> 3;
+ pPoint[i].width = (bufZ0 > 255) ? 255 : bufZ0;
+
+ //Limit max x, y coordinate if value is over its range.
+ pPoint[i].x_coordinate = (pPoint[i].x_coordinate > psNuAdcTouch->x_range) ? psNuAdcTouch->x_range : pPoint[i].x_coordinate;
+ pPoint[i].y_coordinate = (pPoint[i].y_coordinate > psNuAdcTouch->y_range) ? psNuAdcTouch->y_range : pPoint[i].y_coordinate;
+ }
+ }
+ return (rt_size_t)i;
+}
+
+static rt_err_t nu_adc_touch_control(struct rt_touch_device *device, int cmd, void *data)
+{
+ nu_adc_touch_t psNuAdcTouch = (nu_adc_touch_t)device;
+ RT_ASSERT(psNuAdcTouch != RT_NULL);
+
+ switch (cmd)
+ {
+ case RT_TOUCH_CTRL_SET_X_RANGE: /* set x range */
+ psNuAdcTouch->x_range = *((rt_int32_t *)data);
+ break;
+
+ case RT_TOUCH_CTRL_SET_Y_RANGE: /* set y range */
+ psNuAdcTouch->y_range = *((rt_int32_t *)data);
+ break;
+
+ case RT_TOUCH_CTRL_ENABLE_INT: /* enable pen_down interrupt */
+ nu_adc_touch_detect(RT_TRUE);
+ break;
+
+ case RT_TOUCH_CTRL_DISABLE_INT: /* disable pen_down interrupt */
+ nu_adc_touch_detect(RT_FALSE);
+ break;
+
+ case RT_TOUCH_CTRL_POWER_ON: /* Touch Power On */
+ return nu_adc_touch_enable(device);
+
+ case RT_TOUCH_CTRL_POWER_OFF: /* Touch Power Off */
+ return nu_adc_touch_disable();
+
+ default:
+ return -RT_ERROR;
+ }
+ return RT_EOK;
+}
+
+static struct rt_touch_ops touch_ops =
+{
+ .touch_readpoint = nu_adc_touch_readpoint,
+ .touch_control = nu_adc_touch_control,
+};
+
+static void nu_adc_touch_update_calmat(S_CALIBRATION_MATRIX *psNewCalMat)
+{
+ if (psNewCalMat &&
+ psNewCalMat->div != 0)
+ {
+ rt_memcpy(&g_sCalMat, psNewCalMat, sizeof(S_CALIBRATION_MATRIX));
+ g_u32Calibrated = 1;
+ rt_kprintf("Applied calibration data: %d, %d, %d, %d, %d, %d, %d\n",
+ g_sCalMat.a,
+ g_sCalMat.b,
+ g_sCalMat.c,
+ g_sCalMat.d,
+ g_sCalMat.e,
+ g_sCalMat.f,
+ g_sCalMat.div);
+
+ }
+}
+
+static void nu_adc_touch_reset_calmat(void)
+{
+ rt_memcpy(&g_sCalMat, &g_sCalZero, sizeof(S_CALIBRATION_MATRIX));
+ g_u32Calibrated = 0;
+}
+
+int rt_hw_adc_touch_init(void)
+{
+ /* Register touch device */
+ s_NuAdcTouch.dev.info.type = RT_TOUCH_TYPE_RESISTANCE;
+ s_NuAdcTouch.dev.info.vendor = RT_TOUCH_VENDOR_UNKNOWN;
+ s_NuAdcTouch.dev.info.point_num = 1;
+ s_NuAdcTouch.dev.info.range_x = BSP_LCD_WIDTH;
+ s_NuAdcTouch.dev.info.range_y = BSP_LCD_HEIGHT;
+
+ s_NuAdcTouch.dev.ops = &touch_ops;
+
+ return (int)rt_hw_touch_register(&s_NuAdcTouch.dev, "adc_touch", RT_DEVICE_FLAG_INT_RX, RT_NULL);
+}
+INIT_DEVICE_EXPORT(rt_hw_adc_touch_init);
+
+
+static rt_thread_t adc_touch_thread = RT_NULL;
+static rt_sem_t adc_touch_sem = RT_NULL;
+static int adc_touch_worker_run = 0;
+
+static rt_err_t adc_touch_rx_callback(rt_device_t dev, rt_size_t size)
+{
+ //rt_kprintf("[%s %d] %d\n", __func__, __LINE__, size);
+ return rt_sem_release(adc_touch_sem);
+}
+
+static rt_err_t adc_request_point(rt_device_t pdev, struct rt_touch_data *psTouchPoint)
+{
+ rt_err_t ret = -RT_ERROR;
+
+ if ((ret = rt_sem_take(adc_touch_sem, rt_tick_from_millisecond(500))) == RT_EOK)
+ {
+ rt_memset(psTouchPoint, 0, sizeof(struct rt_touch_data));
+
+ if (rt_device_read(pdev, 0, psTouchPoint, s_NuAdcTouch.dev.info.point_num) == s_NuAdcTouch.dev.info.point_num)
+ {
+ ret = RT_EOK;
+ }
+
+ }
+
+ return ret;
+}
+
+RT_WEAK void nu_touch_inputevent_cb(rt_int16_t x, rt_int16_t y, rt_uint8_t event)
+{
+}
+
+static rt_device_t lcd_device = 0;
+static struct rt_device_graphic_info info;
+
+static void lcd_cleanscreen(void)
+{
+ if (info.framebuffer != RT_NULL)
+ {
+ /* Rendering */
+ struct rt_device_rect_info rect;
+
+ rt_memset(info.framebuffer, 0, (info.pitch * info.height));
+ rect.x = 0;
+ rect.y = 0;
+ rect.width = info.width;
+ rect.height = info.height;
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
+ }
+ else
+ {
+ // TODO
+ }
+}
+
+#define DEF_DOT_NUMBER 9
+#define DOTS_NUMBER (DEF_DOT_NUMBER*DEF_DOT_NUMBER)
+static void nu_draw_bots(int x, int y)
+{
+ if (info.framebuffer != RT_NULL)
+ {
+ /* Rendering */
+ struct rt_device_rect_info rect;
+ int i, j;
+ int start_x = x - (DEF_DOT_NUMBER / 2);
+ int start_y = y - (DEF_DOT_NUMBER / 2);
+
+ if (info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565)
+ {
+ uint16_t *pu16Start = (uint16_t *)((uint32_t)info.framebuffer + (start_y) * info.pitch + (start_x * 2));
+ for (j = 0; j < DEF_DOT_NUMBER; j++)
+ {
+ for (i = 0; i < DEF_DOT_NUMBER; i++)
+ pu16Start[i] = 0x07E0; //Green, RGB
+ pu16Start += info.width;
+ }
+ }
+ else if (info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888)
+ {
+ uint32_t *pu32Start = (uint32_t *)((uint32_t)info.framebuffer + (start_y) * info.pitch + (start_x * 4));
+ for (j = 0; j < DEF_DOT_NUMBER; j++)
+ {
+ for (i = 0; i < DEF_DOT_NUMBER; i++)
+ pu32Start[i] = 0xff00ff00; //Green, ARGB
+ pu32Start += info.width;
+ }
+ }
+ else
+ {
+ //Not supported
+ }
+
+ rect.x = 0;
+ rect.y = 0;
+ rect.width = info.width;
+ rect.height = info.height;
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
+ }
+ else
+ {
+ // TODO
+ }
+}
+
+#if (DEF_CAL_POINT_NUM==3)
+const S_COORDINATE_POINT sDispPoints[DEF_CAL_POINT_NUM] =
+{
+ {BSP_LCD_WIDTH / 4, BSP_LCD_HEIGHT / 2},
+ {BSP_LCD_WIDTH - BSP_LCD_WIDTH / 4, BSP_LCD_HEIGHT / 4},
+ {BSP_LCD_WIDTH / 2, BSP_LCD_HEIGHT - BSP_LCD_HEIGHT / 4}
+};
+#elif (DEF_CAL_POINT_NUM==5)
+const static S_COORDINATE_POINT sDispPoints[DEF_CAL_POINT_NUM] =
+{
+#define DEF_CUT_PIECES 8
+ {BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+ {BSP_LCD_WIDTH - BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+ {BSP_LCD_WIDTH - BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT - BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+ {BSP_LCD_WIDTH / DEF_CUT_PIECES, BSP_LCD_HEIGHT - BSP_LCD_HEIGHT / DEF_CUT_PIECES},
+
+ {BSP_LCD_WIDTH / 2, BSP_LCD_HEIGHT / 2}
+};
+#endif
+
+static int nu_adc_touch_readfile(void)
+{
+ int fd;
+
+ S_CALIBRATION_MATRIX sCalMat;
+
+ if ((fd = open(PATH_CALIBRATION_FILE, O_RDONLY, 0)) < 0)
+ {
+ goto exit_nu_adc_touch_readfile;
+ }
+ else if (read(fd, &sCalMat, sizeof(S_CALIBRATION_MATRIX)) == sizeof(S_CALIBRATION_MATRIX))
+ {
+ rt_kprintf("[%s] %s\n", __func__, PATH_CALIBRATION_FILE);
+ }
+
+ close(fd);
+
+ nu_adc_touch_update_calmat(&sCalMat);
+
+ return 0;
+
+exit_nu_adc_touch_readfile:
+
+ return -1;
+}
+
+static int nu_adc_touch_writefile(void *buf, int buf_len)
+{
+ int fd;
+
+ if ((fd = open(PATH_CALIBRATION_FILE, O_WRONLY | O_CREAT, 0)) < 0)
+ {
+ goto exit_nu_adc_touch_writefile;
+ }
+ else if (write(fd, buf, buf_len) == buf_len)
+ {
+ rt_kprintf("[%s] %s\n", __func__, PATH_CALIBRATION_FILE);
+ }
+
+ close(fd);
+
+ return 0;
+
+exit_nu_adc_touch_writefile:
+
+ return -1;
+}
+
+static void nu_touch_do_calibration(rt_device_t pdev)
+{
+ int i;
+ rt_err_t result;
+
+ S_CALIBRATION_MATRIX sCalMat;
+ S_COORDINATE_POINT sADCPoints[DEF_CAL_POINT_NUM];
+
+ lcd_device = rt_device_find("lcd");
+ if (!lcd_device)
+ {
+ rt_kprintf("Not supported graphics ops\n");
+ return;
+ }
+
+ result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info);
+ if (result != RT_EOK)
+ {
+ rt_kprintf("error!");
+ return;
+ }
+
+ result = rt_device_open(lcd_device, 0);
+ if (result != RT_EOK)
+ {
+ rt_kprintf("opened?");
+ }
+
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, info.framebuffer);
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL);
+
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ struct rt_touch_data sTouchPoint;
+ int count = 0;
+
+ lcd_cleanscreen();
+
+ /* Drain RX queue before doing calibrate. */
+ while (adc_request_point(pdev, &sTouchPoint) == RT_EOK);
+
+ rt_thread_mdelay(100);
+
+ /* Ready to calibrate */
+ nu_draw_bots(sDispPoints[i].x, sDispPoints[i].y);
+
+#define DEF_MAX_GET_POINT_NUM 5
+
+ sADCPoints[i].x = 0;
+ sADCPoints[i].y = 0;
+
+ while (count < DEF_MAX_GET_POINT_NUM)
+ {
+ if (adc_request_point(pdev, &sTouchPoint) == RT_EOK)
+ {
+ sADCPoints[i].x += (int32_t)sTouchPoint.x_coordinate;
+ sADCPoints[i].y += (int32_t)sTouchPoint.y_coordinate;
+ rt_kprintf("[%d %d] - Disp:[%d, %d] -> ADC:[%d, %d]\n", i, count, sDispPoints[i].x, sDispPoints[i].y, sADCPoints[i].x, sADCPoints[i].y);
+ count++;
+ }
+ }
+
+ sADCPoints[i].x = (int32_t)((float)sADCPoints[i].x / DEF_MAX_GET_POINT_NUM);
+ sADCPoints[i].y = (int32_t)((float)sADCPoints[i].y / DEF_MAX_GET_POINT_NUM);
+ rt_kprintf("[%d] - Disp:[%d, %d], ADC:[%d, %d]\n", i, sDispPoints[i].x, sDispPoints[i].y, sADCPoints[i].x, sADCPoints[i].y);
+
+ rt_thread_mdelay(300);
+ }
+
+ lcd_cleanscreen();
+
+ /* Get calibration matrix. */
+ if (nu_adc_cal_mat_get(&sDispPoints[0], &sADCPoints[0], &sCalMat) == 0)
+ {
+ /* Finally, update calibration matrix to drivers. */
+ nu_adc_touch_update_calmat(&sCalMat);
+
+ nu_adc_touch_writefile(&sCalMat, sizeof(sCalMat));
+
+ for (i = 0; i < DEF_CAL_POINT_NUM; i++)
+ {
+ rt_kprintf("[%d] - Disp:[%d, %d], ADC:[%d, %d]\n", i, sDispPoints[i].x, sDispPoints[i].y, sADCPoints[i].x, sADCPoints[i].y);
+ }
+ }
+ else
+ {
+ rt_kprintf("Failed to calibrate.\n");
+ }
+
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWEROFF, RT_NULL);
+ rt_device_close(lcd_device);
+
+ return;
+}
+
+static void adc_touch_entry(void *parameter)
+{
+ struct rt_touch_data touch_point;
+
+ rt_err_t result;
+ rt_device_t pdev;
+
+ int max_range;
+
+ adc_touch_sem = rt_sem_create("adc_touch_sem", 0, RT_IPC_FLAG_FIFO);
+ RT_ASSERT(adc_touch_sem != RT_NULL);
+
+ pdev = rt_device_find("adc_touch");
+ if (!pdev)
+ {
+ rt_kprintf("Not found\n");
+ return ;
+ }
+
+ nu_adc_touch_readfile();
+
+ result = rt_device_open(pdev, RT_DEVICE_FLAG_INT_RX);
+ RT_ASSERT(result == RT_EOK);
+
+ result = rt_device_set_rx_indicate(pdev, adc_touch_rx_callback);
+ RT_ASSERT(result == RT_EOK);
+
+ max_range = BSP_LCD_WIDTH;
+ result = rt_device_control(pdev, RT_TOUCH_CTRL_SET_X_RANGE, (void *)&max_range);
+ RT_ASSERT(result == RT_EOK);
+
+ max_range = BSP_LCD_HEIGHT;
+ result = rt_device_control(pdev, RT_TOUCH_CTRL_SET_Y_RANGE, (void *)&max_range);
+ RT_ASSERT(result == RT_EOK);
+
+ result = rt_device_control(pdev, RT_TOUCH_CTRL_POWER_ON, RT_NULL);
+ RT_ASSERT(result == RT_EOK);
+
+ while (adc_touch_worker_run)
+ {
+ if (!g_u32Calibrated)
+ {
+ rt_kprintf("Start ADC touching calibration.\n");
+ nu_touch_do_calibration(pdev);
+ rt_kprintf("Stop ADC touching calibration.\n");
+ continue;
+ }
+
+ if (adc_request_point(pdev, &touch_point) == RT_EOK)
+ {
+ if (touch_point.event == RT_TOUCH_EVENT_DOWN
+ || touch_point.event == RT_TOUCH_EVENT_UP
+ || touch_point.event == RT_TOUCH_EVENT_MOVE)
+ {
+ nu_touch_inputevent_cb(touch_point.x_coordinate, touch_point.y_coordinate, touch_point.event);
+
+ rt_kprintf("x=%d y=%d event=%s%s%s\n",
+ touch_point.x_coordinate,
+ touch_point.y_coordinate,
+ (touch_point.event == RT_TOUCH_EVENT_DOWN) ? "DOWN" : "",
+ (touch_point.event == RT_TOUCH_EVENT_UP) ? "UP" : "",
+ (touch_point.event == RT_TOUCH_EVENT_MOVE) ? "MOVE" : "");
+ }
+ }
+ }
+
+ result = rt_device_control(pdev, RT_TOUCH_CTRL_POWER_OFF, RT_NULL);
+ RT_ASSERT(result == RT_EOK);
+
+ result = rt_device_close(pdev);
+ RT_ASSERT(result == RT_EOK);
+}
+
+
+/* Support "nu_touch_start" command line in msh mode */
+static rt_err_t nu_touch_start(int argc, char **argv)
+{
+ if (adc_touch_thread == RT_NULL)
+ {
+ adc_touch_thread = rt_thread_create("adc_touch_thread",
+ adc_touch_entry,
+ RT_NULL,
+ 4096,
+ 25,
+ 5);
+ adc_touch_worker_run = 1;
+ if (adc_touch_thread != RT_NULL)
+ rt_thread_startup(adc_touch_thread);
+ }
+ return 0;
+}
+MSH_CMD_EXPORT(nu_touch_start, e.g: start adc touch);
+
+/* Support "nu_touch_stop" command line in msh mode */
+static rt_err_t nu_touch_stop(int argc, char **argv)
+{
+ adc_touch_worker_run = 0;
+ adc_touch_thread = RT_NULL;
+ return 0;
+}
+MSH_CMD_EXPORT(nu_touch_stop, e.g: stop adc touch);
+
+static int nu_touch_autostart(void)
+{
+ return nu_touch_start(0, RT_NULL);
+}
+INIT_APP_EXPORT(nu_touch_autostart);
+
+static rt_err_t nu_touch_calibration(int argc, char **argv)
+{
+ /* Clean calibration matrix data for getting raw adc value. */
+ nu_adc_touch_reset_calmat();
+
+ return 0;
+}
+MSH_CMD_EXPORT(nu_touch_calibration, for adc touch);
+
+#endif //#if defined(BSP_USING_ADC_TOUCH)
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c
index 3b48867bb2..fcdbbe8d74 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c
@@ -64,6 +64,7 @@ struct nu_can
IRQn_Type irqn;
E_SYS_IPRST rstidx;
E_SYS_IPCLK clkidx;
+ uint32_t int_flag;
};
typedef struct nu_can *nu_can_t;
@@ -130,16 +131,16 @@ static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT;
/* Interrupt Handle Function ----------------------------------------------------*/
static void nu_can_isr(int vector, void *param)
{
- uint32_t u32IIDRstatus;
nu_can_t psNuCAN = (nu_can_t)param;
/* Get base address of CAN register */
CAN_T *base = psNuCAN->base;
/* Get interrupt event */
- u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(base);
+ uint32_t u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(base) & CAN_IIDR_INTID_Msk;
- if (u32IIDRstatus == 0x00008000) /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+ if (u32IIDRstatus == 0x00008000)
{
/**************************/
/* Status Change interrupt*/
@@ -147,20 +148,24 @@ static void nu_can_isr(int vector, void *param)
if (base->STATUS & CAN_STATUS_TXOK_Msk)
{
base->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
- //rt_kprintf("%s: TX\n", psNuCAN->name) ;
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
+ }
#endif
}
if (base->STATUS & CAN_STATUS_RXOK_Msk)
{
base->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
- //rt_kprintf("%s: RX\n", psNuCAN->name) ;
#ifndef RT_CAN_USING_HDR
- /* Using as Lisen,Loopback,Loopback+Lisen mode*/
- rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_RX_IND);
+ if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /*Using as Lisen,Loopback,Loopback+Lisen mode*/
+ rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_RX_IND);
+ }
#endif
}
@@ -169,17 +174,16 @@ static void nu_can_isr(int vector, void *param)
/**************************/
if (base->STATUS & CAN_STATUS_EWARN_Msk)
{
- rt_kprintf("%s: EWARN\n", psNuCAN->name) ;
+ rt_kprintf("[%s]EWARN INT\n", psNuCAN->name) ;
}
if (base->STATUS & CAN_STATUS_BOFF_Msk)
{
- rt_kprintf("%s: BUSOFF\n", psNuCAN->name) ;
+ rt_kprintf("[%s]BUSOFF INT\n", psNuCAN->name) ;
- /* Do Init to release busoff pin */
- base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
- base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
- while (base->CON & CAN_CON_INIT_Msk);
+ /* To release busoff pin */
+ CAN_EnterInitMode(base, CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+ CAN_LeaveInitMode(base);
}
if (base->STATUS & CAN_STATUS_LEC_Msk)
@@ -192,66 +196,83 @@ static void nu_can_isr(int vector, void *param)
/*IntId: 0x0001-0x0020, Number of Message Object which caused the interrupt.*/
else if (u32IIDRstatus > 0 && u32IIDRstatus <= 32)
{
- /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
- if (u32IIDRstatus <= RX_MSG_ID_INDEX)
+ if ((psNuCAN->int_flag & RT_DEVICE_FLAG_INT_TX) &&
+ (u32IIDRstatus <= RX_MSG_ID_INDEX))
{
- //rt_kprintf("[%s-Tx]IntId = %d\n", psNuCAN->name, u32IIDRstatus);
+ /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
rt_hw_can_isr(&psNuCAN->dev, RT_CAN_EVENT_TX_DONE);
}
- else /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+ else if (psNuCAN->int_flag & RT_DEVICE_FLAG_INT_RX)
{
- //rt_kprintf("[%s-Rx]IntId = %d\n", psNuCAN->name, u32IIDRstatus);
+ /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
rt_hw_can_isr(&psNuCAN->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
}
CAN_CLR_INT_PENDING_BIT(base, (u32IIDRstatus - 1)); /* Clear Interrupt Pending */
}
#endif
-
}
+static void nu_can_ie(nu_can_t psNuCAN)
+{
+ uint32_t u32CanIE = CAN_CON_IE_Msk;
+
+ if (psNuCAN->int_flag & (RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX))
+ {
+ u32CanIE |= CAN_CON_SIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_SIE_Msk;
+ }
+
+ if (psNuCAN->int_flag & RT_DEVICE_CAN_INT_ERR)
+ {
+ u32CanIE |= CAN_CON_EIE_Msk;
+ }
+ else
+ {
+ u32CanIE &= ~CAN_CON_EIE_Msk;
+ }
+
+ if (u32CanIE & (CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))
+ {
+ CAN_EnableInt(psNuCAN->base, u32CanIE);
+
+ /* Enable interrupt. */
+ rt_hw_interrupt_umask(psNuCAN->irqn);
+ }
+ else
+ {
+ u32CanIE |= (CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+ CAN_DisableInt(psNuCAN->base, u32CanIE);
+
+ /* Disable interrupt. */
+ rt_hw_interrupt_mask(psNuCAN->irqn);
+ }
+}
static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg)
{
nu_can_t psNuCAN = (nu_can_t)can;
+ uint32_t u32CANMode;
- RT_ASSERT(can != RT_NULL);
- RT_ASSERT(cfg != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(cfg);
/* Get base address of CAN register */
CAN_T *base = psNuCAN->base;
- RT_ASSERT(base != RT_NULL);
-
- switch (cfg->mode)
- {
- /* CAN default Normal mode */
- case RT_CAN_MODE_NORMAL:
- can->config.mode = CAN_NORMAL_MODE;
- break;
- case RT_CAN_MODE_LISEN:
- can->config.mode = RT_CAN_MODE_LISEN;
- break;
- case RT_CAN_MODE_LOOPBACK:
- can->config.mode = RT_CAN_MODE_LOOPBACK;
- break;
- case RT_CAN_MODE_LOOPBACKANLISEN:
- can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN;
- break;
- default:
- rt_kprintf("Unsupported Operating mode");
- goto exit_nu_can_configure;
- }
-
+ /* Reset this module */
nu_sys_ip_reset(psNuCAN->rstidx);
- /*Set the CAN Bit Rate and Operating mode*/
- if (CAN_Open(base, can->config.baud_rate, can->config.mode) < 1)
- return -(RT_ERROR);
+ u32CANMode = (cfg->mode == RT_CAN_MODE_NORMAL) ? CAN_NORMAL_MODE : CAN_BASIC_MODE;
+ /*Set the CAN Bit Rate and Operating mode*/
+ if (CAN_Open(base, cfg->baud_rate, u32CANMode) != cfg->baud_rate)
+ goto exit_nu_can_configure;
switch (cfg->mode)
{
- /* CAN default Normal mode */
case RT_CAN_MODE_NORMAL:
#ifdef RT_CAN_USING_HDR
CAN_LeaveTestMode(base);
@@ -273,6 +294,7 @@ static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure
goto exit_nu_can_configure;
}
+ nu_can_ie(psNuCAN);
return RT_EOK;
@@ -285,73 +307,33 @@ exit_nu_can_configure:
static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
{
- rt_uint32_t argval;
- nu_can_t psNuCAN = (nu_can_t)can;
+ rt_uint32_t argval = (rt_uint32_t)arg;
+ nu_can_t psNuCAN = (nu_can_t)can;
-#ifdef RT_CAN_USING_HDR
- struct rt_can_filter_config *filter_cfg;
-#endif
- /* Get base address of CAN register */
- CAN_T *base = psNuCAN->base;
-
- RT_ASSERT(base != RT_NULL);
- /* Check baud rate */
- RT_ASSERT(can->config.baud_rate != 0);
+ RT_ASSERT(can);
switch (cmd)
{
- case RT_DEVICE_CTRL_CLR_INT:
- argval = (rt_uint32_t) arg;
- if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Disable NVIC interrupt. */
- rt_hw_interrupt_mask(psNuCAN->irqn);
-
- /* Disable Status Change Interrupt */
- CAN_DisableInt(base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
-
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Disable interrupt. */
- rt_hw_interrupt_mask(psNuCAN->irqn);
-
- /* Disable Error Interrupt */
- CAN_DisableInt(base, CAN_CON_EIE_Msk);
- }
- break;
-
case RT_DEVICE_CTRL_SET_INT:
- argval = (rt_uint32_t) arg;
- if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX))
- {
- /* Enable Status Change Interrupt */
- CAN_EnableInt(base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
-
- /* Enable interrupt. */
- rt_hw_interrupt_umask(psNuCAN->irqn);
- }
- else if (argval == RT_DEVICE_CAN_INT_ERR)
- {
- /* Enable Error Status and Status Change Interrupt */
- CAN_EnableInt(base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
-
- /* Enable interrupt. */
- rt_hw_interrupt_umask(psNuCAN->irqn);
- }
+ psNuCAN->int_flag |= argval;
+ nu_can_ie(psNuCAN);
+ break;
+
+ case RT_DEVICE_CTRL_CLR_INT:
+ psNuCAN->int_flag &= ~argval;
+ nu_can_ie(psNuCAN);
break;
-#ifdef RT_CAN_USING_HDR
case RT_CAN_CMD_SET_FILTER:
- filter_cfg = (struct rt_can_filter_config *)arg;
+ {
+ struct rt_can_filter_config *filter_cfg = (struct rt_can_filter_config *)arg;
for (int i = 0; i < filter_cfg->count; i++)
{
-
/*set the filter message object*/
if (filter_cfg->items[i].mode == 1)
{
- if (CAN_SetRxMsgObjAndMsk(base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
+ if (CAN_SetRxMsgObjAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
{
return -(RT_ERROR);
}
@@ -359,46 +341,61 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
else
{
/*set the filter message object*/
- if (CAN_SetRxMsgAndMsk(base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
+ if (CAN_SetRxMsgAndMsk(psNuCAN->base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
{
return -(RT_ERROR);
}
}
}
- break;
-#endif
+ }
+ break;
case RT_CAN_CMD_SET_MODE:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN &&
- argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN)
+ if ((argval == RT_CAN_MODE_NORMAL) ||
+ (argval == RT_CAN_MODE_LISEN) ||
+ (argval == RT_CAN_MODE_LOOPBACK) ||
+ (argval == RT_CAN_MODE_LOOPBACKANLISEN))
+ {
+ if (argval != can->config.mode)
+ {
+ can->config.mode = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.mode)
- {
- can->config.mode = argval;
- return nu_can_configure(can, &can->config);
- }
break;
case RT_CAN_CMD_SET_BAUD:
- argval = (rt_uint32_t) arg;
- if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud &&
- argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud && argval != CAN20kBaud && argval != CAN10kBaud)
+ {
+ if ((argval == CAN1MBaud) ||
+ (argval == CAN800kBaud) ||
+ (argval == CAN500kBaud) ||
+ (argval == CAN250kBaud) ||
+ (argval == CAN125kBaud) ||
+ (argval == CAN100kBaud) ||
+ (argval == CAN50kBaud) ||
+ (argval == CAN20kBaud) ||
+ (argval == CAN10kBaud))
+ {
+ if (argval != can->config.baud_rate)
+ {
+ can->config.baud_rate = argval;
+ return nu_can_configure(can, &can->config);
+ }
+ }
+ else
{
return -(RT_ERROR);
}
- if (argval != can->config.baud_rate)
- {
- can->config.baud_rate = argval;
- return nu_can_configure(can, &can->config);
- }
- break;
+ }
+ break;
case RT_CAN_CMD_SET_PRIV:
- argval = (rt_uint32_t) arg;
- if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV)
+ if (argval != RT_CAN_MODE_PRIV &&
+ argval != RT_CAN_MODE_NOPRIV)
{
return -(RT_ERROR);
}
@@ -411,16 +408,23 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
case RT_CAN_CMD_GET_STATUS:
{
- rt_uint32_t errtype;
- errtype = base->ERR;
- /*Receive Error Counter*/
+ rt_uint32_t errtype = psNuCAN->base->ERR;
+
+ RT_ASSERT(arg);
+
+ /*Receive Error Counter, return value is with Receive Error Passive.*/
can->status.rcverrcnt = (errtype >> 8);
+
/*Transmit Error Counter*/
- can->status.snderrcnt = ((errtype >> 24) & 0xFF);
- can->status.lasterrtype = CAN_GET_INT_STATUS(base) & 0x8000;
- /*status error code*/
- can->status.errcode = CAN_GET_INT_STATUS(base) & 0x07;
- rt_memcpy(arg, &can->status, sizeof(can->status));
+ can->status.snderrcnt = (errtype & 0xFF);
+
+ /*Last Error Type*/
+ can->status.lasterrtype = CAN_GET_INT_STATUS(psNuCAN->base) & 0x8000;
+
+ /*Status error code*/
+ can->status.errcode = CAN_GET_INT_STATUS(psNuCAN->base) & 0x07;
+
+ rt_memcpy(arg, &can->status, sizeof(struct rt_can_status));
}
break;
@@ -435,64 +439,91 @@ static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- /* Get base address of CAN register */
- CAN_T *base = ((nu_can_t)can)->base;
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
- RT_ASSERT(base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
+ pmsg = (struct rt_can_msg *) buf;
- /* Check the parameters */
- RT_ASSERT(IS_CAN_DLC(pmsg->len));
-
- /* Standard ID (11 bits)*/
- if (pmsg->ide == RT_CAN_STDID)
+ if (pmsg->ide == RT_CAN_STDID && IS_CAN_STDID(pmsg->id))
{
+ /* Standard ID (11 bits)*/
tMsg.IdType = CAN_STD_ID;
- RT_ASSERT(IS_CAN_STDID(pmsg->id))
tMsg.Id = pmsg->id ;
}
- else
+ else if (pmsg->ide == RT_CAN_EXTID && IS_CAN_EXTID(pmsg->id))
{
/* Extended ID (29 bits)*/
tMsg.IdType = CAN_EXT_ID;
- RT_ASSERT(IS_CAN_EXTID(pmsg->id));
tMsg.Id = pmsg->id ;
}
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
if (pmsg->rtr == RT_CAN_DTR)
{
/* Data frame */
tMsg.FrameType = CAN_DATA_FRAME;
}
- else
+ else if (pmsg->rtr == RT_CAN_RTR)
{
/* Remote frame */
tMsg.FrameType = CAN_REMOTE_FRAME;
}
- tMsg.DLC = pmsg->len;
- rt_memcpy(tMsg.Data, pmsg->data, pmsg->len);
-
- if (CAN_Transmit(base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM
+ else
{
- return -(RT_ERROR);
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Check the parameters */
+ if (IS_CAN_DLC(pmsg->len))
+ {
+ tMsg.DLC = pmsg->len;
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ if (pmsg->data && pmsg->len)
+ {
+ rt_memcpy(&tMsg.Data[0], pmsg->data, pmsg->len);
+ }
+ else
+ {
+ goto exit_nu_can_sendmsg;
+ }
+
+ /* Configure Msg RAM and send the Msg in the RAM. */
+ if (CAN_Transmit(psNuCAN->base, MSG(boxno), &tMsg) == FALSE)
+ {
+ goto exit_nu_can_sendmsg;
}
return RT_EOK;
+
+exit_nu_can_sendmsg:
+
+ return -(RT_ERROR);
}
+
static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{
STR_CANMSG_T tMsg;
- struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
- /* Get base address of CAN register */
- CAN_T *base = ((nu_can_t)can)->base;
+ struct rt_can_msg *pmsg;
+ nu_can_t psNuCAN = (nu_can_t)can;
- RT_ASSERT(base != RT_NULL);
- RT_ASSERT(buf != RT_NULL);
+ RT_ASSERT(can);
+ RT_ASSERT(buf);
+
+ pmsg = (struct rt_can_msg *) buf;
/* get data */
- if (CAN_Receive(base, boxno, &tMsg) == FALSE)
+ if (CAN_Receive(psNuCAN->base, boxno, &tMsg) == FALSE)
{
rt_kprintf("No available RX Msg.\n");
return -(RT_ERROR);
@@ -504,32 +535,13 @@ static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxn
can->hdr[pmsg->hdr].connected = 1;
#endif
- /* Standard ID (11 bits)*/
- if (tMsg.IdType == CAN_STD_ID)
- {
- pmsg->ide = RT_CAN_STDID;
- pmsg->id = tMsg.Id;
- }
- else /* Extended ID (29 bits)*/
- {
- pmsg->ide = RT_CAN_EXTID;
- pmsg->id = tMsg.Id;
- }
-
- if (tMsg.FrameType == CAN_DATA_FRAME)
- {
- /* Data frame */
- pmsg->rtr = RT_CAN_DTR;
- }
- else
- {
- /* Remote frame */
- pmsg->rtr = RT_CAN_RTR;
- }
-
+ pmsg->ide = (tMsg.IdType == CAN_STD_ID) ? RT_CAN_STDID : RT_CAN_EXTID;
+ pmsg->rtr = (tMsg.FrameType == CAN_DATA_FRAME) ? RT_CAN_DTR : RT_CAN_RTR;
+ pmsg->id = tMsg.Id;
pmsg->len = tMsg.DLC ;
- rt_memcpy(pmsg->data, tMsg.Data, pmsg->len);
+ if (pmsg->data && pmsg->len)
+ rt_memcpy(pmsg->data, &tMsg.Data[0], pmsg->len);
return RT_EOK;
}
@@ -564,5 +576,4 @@ static int rt_hw_can_init(void)
return (int)ret;
}
INIT_DEVICE_EXPORT(rt_hw_can_init);
-
#endif //#if defined(BSP_USING_CAN)
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_crypto.c
index 4a31151c29..f26440524d 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_crypto.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_crypto.c
@@ -57,11 +57,6 @@ static struct rt_mutex s_AES_mutex;
static struct rt_mutex s_SHA_mutex;
static struct rt_mutex s_PRNG_mutex;
-static void nu_crypto_isr(int vector, void *param)
-{
- /* Nothing */
-}
-
static rt_err_t nu_aes_crypt_run(
rt_bool_t bEncrypt,
uint32_t u32OpMode,
@@ -153,7 +148,7 @@ static void nu_prng_open(uint32_t u32Seed)
result = rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
- //Open PRNG 64 bits. But always return 32 bits
+ //Open PRNG 64 bits
PRNG_Open(CRPT, PRNG_KEY_SIZE_64, PRNG_SEED_RELOAD, u32Seed);
result = rt_mutex_release(&s_PRNG_mutex);
@@ -179,7 +174,7 @@ static rt_uint32_t nu_prng_run(void)
result = rt_mutex_release(&s_PRNG_mutex);
RT_ASSERT(result == RT_EOK);
- return au32RNGValue[0];
+ return au32RNGValue[0] ^ au32RNGValue[1];
}
static rt_err_t nu_aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
@@ -665,6 +660,8 @@ static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
break;
}
+ nu_hwcrypto_reset(ctx);
+
return res;
}
@@ -770,9 +767,6 @@ int nu_hwcrypto_device_init(void)
result = rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME);
RT_ASSERT(result == RT_EOK);
- /* Enable Crypto engine interrupt */
- rt_hw_interrupt_install(IRQ_CRYPTO, nu_crypto_isr, RT_NULL, "crypto");
-
return 0;
}
INIT_DEVICE_EXPORT(nu_hwcrypto_device_init);
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
index 252ca1e1ae..9e94e347ca 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
@@ -682,7 +682,7 @@ lwiperf_report(void *arg, enum lwiperf_report_type report_type,
(int)report_type, ipaddr_ntoa(remote_addr), (int)remote_port, bytes_transferred, ms_duration, bandwidth_kbitpsec);
}
-void lwiperf_example_init(void)
+void lwiperf_example_init(int argc, char **argv)
{
lwiperf_start_tcp_server_default(lwiperf_report, NULL);
}
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
index 423740dfc0..89e80b662f 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
@@ -118,7 +118,7 @@ static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u3
RT_ASSERT(bus != RT_NULL);
nu_i2c = (nu_i2c_bus_t *) bus;
- switch (RT_I2C_DEV_CTRL_CLK)
+ switch (u32Cmd)
{
case RT_I2C_DEV_CTRL_CLK:
I2C_SetBusClockFreq(nu_i2c->I2C, u32Value);
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c
index 6990ce215c..bc3b23fd0d 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c
@@ -20,10 +20,12 @@
#include
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
/* Private define ---------------------------------------------------------------*/
@@ -454,8 +456,6 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
{
rt_bool_t ret = RT_FALSE;
-#if defined(RT_USING_DFS)
-
struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path);
if (psFS == RT_NULL)
{
@@ -472,15 +472,11 @@ static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
exit_nu_sdh_hotplug_is_mounted:
-#endif
-
return ret;
}
static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
{
rt_err_t ret = RT_ERROR;
-
-#if defined(RT_USING_DFS)
DIR *t;
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE)
@@ -530,7 +526,6 @@ static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
exit_nu_sdh_hotplug_mount:
-#endif
return -(ret);
}
@@ -538,7 +533,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
{
rt_err_t ret = RT_ERROR;
-#if defined(RT_USING_DFS)
if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE)
{
ret = RT_EOK;
@@ -558,8 +552,6 @@ static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
exit_nu_sdh_hotplug_unmount:
-#endif
-
return -(ret);
}
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
index a5660ba328..64e9dbf3ae 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
@@ -425,7 +425,7 @@ static int nu_bulk_xfer(
UTR_T *psUTR,
int timeouts)
{
- #define TIMEOUT_RETRY 3
+#define TIMEOUT_RETRY 3
int retry = TIMEOUT_RETRY;
int ret = usbh_bulk_xfer(psUTR);
@@ -435,9 +435,9 @@ static int nu_bulk_xfer(
return ret;
}
- while ( retry > 0 )
+ while (retry > 0)
{
- if ( rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0 )
+ if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0)
{
rt_uint32_t level;
@@ -513,7 +513,7 @@ static void int_xfer_done_cb(UTR_T *psUTR)
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
- rt_usbh_event_signal(&msg);
+ rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
@@ -942,7 +942,7 @@ int nu_usbh_register(void)
/*initialize the usb host function */
- res = rt_usb_host_init();
+ res = rt_usb_host_init("usbh");
RT_ASSERT(res == RT_EOK);
#if defined(RT_USING_PM)
diff --git a/bsp/nuvoton/nk-980iot/.config b/bsp/nuvoton/nk-980iot/.config
index fa6f45f046..1339d389e1 100644
--- a/bsp/nuvoton/nk-980iot/.config
+++ b/bsp/nuvoton/nk-980iot/.config
@@ -203,8 +203,7 @@ CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048
# CONFIG_RT_USING_SENSOR is not set
-CONFIG_RT_USING_TOUCH=y
-# CONFIG_RT_TOUCH_PIN_IRQ is not set
+# CONFIG_RT_USING_TOUCH is not set
CONFIG_RT_USING_HWCRYPTO=y
CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto"
CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16
@@ -550,17 +549,11 @@ CONFIG_PKG_NETUTILS_VER_NUM=0x10301
#
# LVGL: powerful and easy-to-use embedded GUI library
#
-CONFIG_PKG_USING_LVGL=y
-CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL"
-# CONFIG_PKG_USING_LVGL_EXAMPLES is not set
-CONFIG_PKG_USING_LVGL_V810=y
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LVGL_V810 is not set
# CONFIG_PKG_USING_LVGL_LATEST_VERSION is not set
-CONFIG_PKG_LVGL_VER="v8.1.0"
-CONFIG_PKG_LVGL_VER_NUM=0x08010
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-CONFIG_PKG_USING_LV_MUSIC_DEMO=y
-CONFIG_PKG_LV_MUSIC_DEMO_PATH="/packages/multimedia/LVGL/lv_music_demo"
-CONFIG_PKG_LV_MUSIC_DEMO_VER="v0.1.1"
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
@@ -597,6 +590,7 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -607,7 +601,6 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -658,6 +651,7 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -783,6 +777,7 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -874,23 +869,8 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
-
-#
-# Nuvoton Packages Config
-#
-CONFIG_NU_PKG_USING_UTILS=y
-CONFIG_NU_PKG_USING_DEMO=y
-# CONFIG_NU_PKG_USING_BMX055 is not set
-# CONFIG_NU_PKG_USING_MAX31875 is not set
-# CONFIG_NU_PKG_USING_NAU88L25 is not set
-CONFIG_NU_PKG_USING_NAU8822=y
-# CONFIG_NU_PKG_USING_DA9062 is not set
-CONFIG_NU_PKG_USING_ILI9341=y
-CONFIG_NU_PKG_USING_ILI9341_SPI=y
-# CONFIG_NU_PKG_USING_ILI9341_EBI is not set
-CONFIG_NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER=y
-CONFIG_NU_PKG_ILI9341_HORIZONTAL=y
-CONFIG_NU_PKG_USING_SPINAND=y
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
@@ -913,6 +893,7 @@ CONFIG_BSP_USING_RTC=y
CONFIG_NU_RTC_SUPPORT_IO_RW=y
CONFIG_NU_RTC_SUPPORT_MSH_CMD=y
CONFIG_BSP_USING_ADC=y
+# CONFIG_BSP_USING_ADC_TOUCH is not set
CONFIG_BSP_USING_TMR=y
CONFIG_BSP_USING_TIMER=y
CONFIG_BSP_USING_TMR0=y
@@ -998,8 +979,20 @@ CONFIG_BOARD_USING_USB1_HOST=y
# Board extended module drivers
#
# CONFIG_BOARD_USING_MAX31875 is not set
-CONFIG_BOARD_USING_LCD_ILI9341=y
-CONFIG_BOARD_USING_ILI9341_PIN_BACKLIGHT=103
-CONFIG_BOARD_USING_ILI9341_PIN_RESET=90
-CONFIG_BOARD_USING_ILI9341_PIN_DC=89
+# CONFIG_BOARD_USING_LCD_ILI9341 is not set
# CONFIG_BOARD_USING_ESP8266 is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+# CONFIG_NU_PKG_USING_NAU88L25 is not set
+CONFIG_NU_PKG_USING_NAU8822=y
+# CONFIG_NU_PKG_USING_DA9062 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+CONFIG_NU_PKG_USING_SPINAND=y
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.nk980-iot.test.utest."
diff --git a/bsp/nuvoton/nk-980iot/Kconfig b/bsp/nuvoton/nk-980iot/Kconfig
index 5c55e87c61..b396340d12 100644
--- a/bsp/nuvoton/nk-980iot/Kconfig
+++ b/bsp/nuvoton/nk-980iot/Kconfig
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_disp.c b/bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_disp.c
index cc72d47337..cee304eb09 100644
--- a/bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_disp.c
+++ b/bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_disp.c
@@ -33,11 +33,6 @@ static void lcd_fb_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_colo
rect.width = area->x2 - area->x1 + 1;
rect.height = area->y2 - area->y1 + 1;
- if ((uint32_t)info.framebuffer != (uint32_t)color_p)
- {
- rect.y += info.height;
- }
-
rt_device_control(lcd_device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
lv_disp_flush_ready(disp_drv);
}
@@ -50,8 +45,7 @@ void lcd_perf_monitor(struct _lv_disp_drv_t *disp_drv, uint32_t time, uint32_t p
void lv_port_disp_init(void)
{
rt_err_t result;
- void *buf_1 = RT_NULL;
- void *buf_2 = RT_NULL;
+ void *buf1 = RT_NULL;
lcd_device = rt_device_find("lcd");
if (lcd_device == 0)
@@ -62,7 +56,7 @@ void lv_port_disp_init(void)
/* get framebuffer address */
result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info);
- if (result != RT_EOK)
+ if (result != RT_EOK && info.framebuffer == RT_NULL)
{
LOG_E("error!");
/* get device information failed */
@@ -72,12 +66,11 @@ void lv_port_disp_init(void)
RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
- buf_1 = (void *)info.framebuffer;
- buf_2 = (void *)((uint32_t)buf_1 + info.height * info.width * info.bits_per_pixel / 8);
- rt_kprintf("LVGL: Use two buffers - buf_1@%08x, buf_2@%08x\n", buf_1, buf_2);
+ buf1 = (void *)info.framebuffer;
+ rt_kprintf("LVGL: Use one buffers - buf1@%08x\n", buf1);
/*Initialize `disp_buf` with the buffer(s).*/
- lv_disp_draw_buf_init(&disp_buf, buf_1, buf_2, info.width * info.height);
+ lv_disp_draw_buf_init(&disp_buf, buf1, RT_NULL, info.width * info.height);
result = rt_device_open(lcd_device, 0);
if (result != RT_EOK)
diff --git a/bsp/nuvoton/nk-980iot/applications/mnt.c b/bsp/nuvoton/nk-980iot/applications/mnt.c
index 4ff5b1f252..07905a6b13 100644
--- a/bsp/nuvoton/nk-980iot/applications/mnt.c
+++ b/bsp/nuvoton/nk-980iot/applications/mnt.c
@@ -21,10 +21,12 @@
#define DBG_COLOR
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
#if defined(PKG_USING_FAL)
#include
diff --git a/bsp/nuvoton/nk-980iot/board/Kconfig b/bsp/nuvoton/nk-980iot/board/Kconfig
index 06547f567b..e623161d9e 100644
--- a/bsp/nuvoton/nk-980iot/board/Kconfig
+++ b/bsp/nuvoton/nk-980iot/board/Kconfig
@@ -72,6 +72,7 @@ menu "Hardware Drivers Config"
config BOARD_USING_LCD_ILI9341
bool "LCD ILI9341 (over spi0)"
select RT_USING_TOUCH
+ select BSP_USING_ADC_TOUCH
select NU_PKG_USING_ILI9341
select NU_PKG_USING_ILI9341_SPI
select NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER
@@ -113,5 +114,6 @@ menu "Hardware Drivers Config"
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
endmenu
diff --git a/bsp/nuvoton/nk-980iot/board/nu_pin_init.c b/bsp/nuvoton/nk-980iot/board/nu_pin_init.c
index 97ab099cfa..0ab0bb1f71 100644
--- a/bsp/nuvoton/nk-980iot/board/nu_pin_init.c
+++ b/bsp/nuvoton/nk-980iot/board/nu_pin_init.c
@@ -57,8 +57,10 @@ static void nu_pin_i2c_init(void)
/* I2C0: PA[0, 1] */
outpw(REG_SYS_GPA_MFPL, (inpw(REG_SYS_GPA_MFPL) & ~0x000000FF) | 0x00000033);
+#if !defined(BSP_USING_ADC_TOUCH)
/* I2C2: PB5, PB7 */
outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & ~0xF0F00000) | 0x20200000);
+#endif
}
diff --git a/bsp/nuvoton/nk-980iot/project.uvproj b/bsp/nuvoton/nk-980iot/project.uvproj
deleted file mode 100644
index edb52cb8a3..0000000000
--- a/bsp/nuvoton/nk-980iot/project.uvproj
+++ /dev/null
@@ -1,1877 +0,0 @@
-
-
- 1.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread
- 0x4
- ARM-ADS
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- --c99
- __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
-
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-
-
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-
-
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-
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-
-
-
-
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-
-
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-
-
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-
-
-
-
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-
-
-
-
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-
-
-
-
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-
-
-
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-
-
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-
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- 1
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-
-
-
-
- Filesystem
-
-
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-
-
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-
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-
-
-
-
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-
-
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-
-
-
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-
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-
-
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-
-
-
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-
-
-
-
- ff.c
- 1
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-
-
-
-
- Finsh
-
-
- shell.c
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-
-
-
-
- msh.c
- 1
- ..\..\..\components\finsh\msh.c
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diff --git a/bsp/nuvoton/nk-980iot/project.uvprojx b/bsp/nuvoton/nk-980iot/project.uvprojx
deleted file mode 100644
index 7d23d354b5..0000000000
--- a/bsp/nuvoton/nk-980iot/project.uvprojx
+++ /dev/null
@@ -1,1869 +0,0 @@
-
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- 2.1
- ### uVision Project, (C) Keil Software
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- --c99
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- mem_alloc.c
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- ..\libraries\nuc980\UsbHostLib\src\mem_alloc.c
-
-
-
-
- usb_core.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\usb_core.c
-
-
-
-
- ehci_iso.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\ehci_iso.c
-
-
-
-
- ehci.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\ehci.c
-
-
-
-
- POSIX
-
-
- select.c
- 1
- ..\..\..\components\libc\posix\io\select.c
-
-
-
-
- poll.c
- 1
- ..\..\..\components\libc\posix\io\poll\poll.c
-
-
-
-
- rt_usbd
-
-
- usbdevice_core.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c
-
-
-
-
- mstorage.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\mstorage.c
-
-
-
-
- usbdevice.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c
-
-
-
-
- cdc_vcom.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c
-
-
-
-
- rt_usbh
-
-
- hub.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\hub.c
-
-
-
-
- usbhost.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost.c
-
-
-
-
- usbhost_core.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c
-
-
-
-
- udisk.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\udisk.c
-
-
-
-
- driver.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\driver.c
-
-
-
-
- mass.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\mass.c
-
-
-
-
- SAL
-
-
- netdev.c
- 1
- ..\..\..\components\net\netdev\src\netdev.c
-
-
-
-
- netdev_ipaddr.c
- 1
- ..\..\..\components\net\netdev\src\netdev_ipaddr.c
-
-
-
-
- net_netdb.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_netdb.c
-
-
-
-
- net_sockets.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_sockets.c
-
-
-
-
- dfs_net.c
- 1
- ..\..\..\components\net\sal_socket\dfs_net\dfs_net.c
-
-
-
-
- sal_socket.c
- 1
- ..\..\..\components\net\sal_socket\src\sal_socket.c
-
-
-
-
- af_inet_lwip.c
- 1
- ..\..\..\components\net\sal_socket\impl\af_inet_lwip.c
-
-
-
-
- UTest
-
-
- utest.c
- 1
- ..\..\..\components\utilities\utest\utest.c
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuvoton/nk-980iot/rtconfig.h b/bsp/nuvoton/nk-980iot/rtconfig.h
deleted file mode 100644
index b77df08b3f..0000000000
--- a/bsp/nuvoton/nk-980iot/rtconfig.h
+++ /dev/null
@@ -1,459 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 16
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 2048
-
-/* kservice optimization */
-
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-#define RT_USING_SIGNALS
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_MEMHEAP
-#define RT_MEMHEAP_FAST_MODE
-#define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_MEMTRACE
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-#define ARCH_ARM
-#define ARCH_ARM_ARM9
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define RT_USING_MSH
-#define FINSH_USING_MSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_CMD_SIZE 80
-#define MSH_USING_BUILT_IN_COMMANDS
-#define FINSH_USING_DESCRIPTION
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 16
-#define DFS_FILESYSTEM_TYPES_MAX 16
-#define DFS_FD_MAX 64
-#define RT_USING_DFS_MNTTABLE
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_3
-#define RT_DFS_ELM_USE_LFN 3
-#define RT_DFS_ELM_LFN_UNICODE_0
-#define RT_DFS_ELM_LFN_UNICODE 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 8
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
-#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
-#define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 2048
-#define RT_USING_CAN
-#define RT_CAN_USING_HDR
-#define RT_USING_HWTIMER
-#define RT_USING_CPUTIME
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_MTD_NAND
-#define RT_MTD_NAND_DEBUG
-#define RT_USING_RTC
-#define RT_USING_ALARM
-#define RT_USING_SPI
-#define RT_USING_QSPI
-#define RT_USING_WDT
-#define RT_USING_AUDIO
-#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
-#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
-#define RT_AUDIO_RECORD_PIPE_SIZE 2048
-#define RT_USING_TOUCH
-#define RT_USING_HWCRYPTO
-#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
-#define RT_HWCRYPTO_IV_MAX_SIZE 16
-#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
-#define RT_HWCRYPTO_USING_AES
-#define RT_HWCRYPTO_USING_AES_ECB
-#define RT_HWCRYPTO_USING_AES_CBC
-#define RT_HWCRYPTO_USING_AES_CFB
-#define RT_HWCRYPTO_USING_AES_CTR
-#define RT_HWCRYPTO_USING_AES_OFB
-#define RT_HWCRYPTO_USING_SHA1
-#define RT_HWCRYPTO_USING_SHA2
-#define RT_HWCRYPTO_USING_SHA2_224
-#define RT_HWCRYPTO_USING_SHA2_256
-#define RT_HWCRYPTO_USING_SHA2_384
-#define RT_HWCRYPTO_USING_SHA2_512
-#define RT_HWCRYPTO_USING_RNG
-
-/* Using USB */
-
-#define RT_USING_USB
-#define RT_USING_USB_HOST
-#define RT_USBH_MSTORAGE
-#define UDISK_MOUNTPOINT "/mnt/udisk"
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define RT_USB_DEVICE_COMPOSITE
-#define RT_USB_DEVICE_CDC
-#define RT_USB_DEVICE_NONE
-#define RT_USB_DEVICE_MSTORAGE
-#define RT_VCOM_TASK_STK_SIZE 2048
-#define RT_CDC_RX_BUFSIZE 128
-#define RT_VCOM_SERNO "32021919830108"
-#define RT_VCOM_SER_LEN 14
-#define RT_VCOM_TX_TIMEOUT 1000
-#define RT_USB_MSTORAGE_DISK_NAME "ramdisk1"
-
-/* POSIX layer and C standard library */
-
-#define RT_LIBC_DEFAULT_TIMEZONE 8
-
-/* POSIX (Portable Operating System Interface) layer */
-
-#define RT_USING_POSIX_FS
-#define RT_USING_POSIX_POLL
-#define RT_USING_POSIX_SELECT
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-#define RT_USING_SAL
-
-/* protocol stack implement */
-
-#define SAL_USING_LWIP
-#define SAL_USING_POSIX
-
-/* Network interface device */
-
-#define RT_USING_NETDEV
-#define NETDEV_USING_IFCONFIG
-#define NETDEV_USING_PING
-#define NETDEV_USING_NETSTAT
-#define NETDEV_USING_AUTO_DEFAULT
-#define NETDEV_IPV4 1
-#define NETDEV_IPV6 0
-
-/* light weight TCP/IP stack */
-
-#define RT_USING_LWIP
-#define RT_USING_LWIP212
-#define RT_LWIP_MEM_ALIGNMENT 4
-#define RT_LWIP_IGMP
-#define RT_LWIP_ICMP
-#define RT_LWIP_DNS
-#define RT_LWIP_DHCP
-#define IP_SOF_BROADCAST 1
-#define IP_SOF_BROADCAST_RECV 1
-
-/* Static IPv4 Address */
-
-#define RT_LWIP_IPADDR "192.168.31.55"
-#define RT_LWIP_GWADDR "192.168.31.1"
-#define RT_LWIP_MSKADDR "255.255.255.0"
-#define RT_LWIP_UDP
-#define RT_LWIP_TCP
-#define RT_LWIP_RAW
-#define RT_MEMP_NUM_NETCONN 16
-#define RT_LWIP_PBUF_NUM 256
-#define RT_LWIP_RAW_PCB_NUM 16
-#define RT_LWIP_UDP_PCB_NUM 16
-#define RT_LWIP_TCP_PCB_NUM 16
-#define RT_LWIP_TCP_SEG_NUM 64
-#define RT_LWIP_TCP_SND_BUF 16384
-#define RT_LWIP_TCP_WND 65535
-#define RT_LWIP_TCPTHREAD_PRIORITY 10
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 256
-#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
-#define RT_LWIP_ETHTHREAD_PRIORITY 12
-#define RT_LWIP_ETHTHREAD_STACKSIZE 4096
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 256
-#define RT_LWIP_REASSEMBLY_FRAG
-#define LWIP_NETIF_STATUS_CALLBACK 1
-#define LWIP_NETIF_LINK_CALLBACK 1
-#define SO_REUSE 1
-#define LWIP_SO_RCVTIMEO 1
-#define LWIP_SO_SNDTIMEO 1
-#define LWIP_SO_RCVBUF 1
-#define LWIP_SO_LINGER 0
-#define RT_LWIP_NETIF_LOOPBACK
-#define LWIP_NETIF_LOOPBACK 1
-#define RT_LWIP_STATS
-#define RT_LWIP_USING_PING
-
-/* AT commands */
-
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
-
-/* RT-Thread Utestcases */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-#define PKG_USING_NETUTILS
-#define PKG_NETUTILS_TFTP
-#define PKG_NETUTILS_IPERF
-#define PKG_NETUTILS_NTP
-#define NTP_USING_AUTO_SYNC
-#define NTP_AUTO_SYNC_FIRST_DELAY 30
-#define NTP_AUTO_SYNC_PERIOD 3600
-#define NETUTILS_NTP_HOSTNAME "0.tw.pool.ntp.org"
-#define NETUTILS_NTP_HOSTNAME2 "1.tw.pool.ntp.org"
-#define NETUTILS_NTP_HOSTNAME3 "2.tw.pool.ntp.org"
-#define PKG_USING_NETUTILS_V131
-#define PKG_NETUTILS_VER_NUM 0x10301
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-/* LVGL: powerful and easy-to-use embedded GUI library */
-
-#define PKG_USING_LVGL
-#define PKG_USING_LVGL_V810
-#define PKG_LVGL_VER_NUM 0x08010
-#define PKG_USING_LV_MUSIC_DEMO
-
-/* u8g2: a monochrome graphic library */
-
-#define PKG_USING_WAVPLAYER
-#define PKG_WP_USING_PLAY
-#define PKG_WP_PLAY_DEVICE "sound0"
-#define PKG_WP_USING_RECORD
-#define PKG_WP_RECORD_DEVICE "sound0"
-#define PKG_USING_WAVPLAYER_LATEST_VERSION
-
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
-/* acceleration: Assembly language or algorithmic acceleration packages */
-
-
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
-/* Micrium: Micrium software products porting for RT-Thread */
-
-#define PKG_USING_DFS_UFFS
-#define RT_USING_DFS_UFFS
-#define RT_UFFS_ECC_MODE_3
-#define RT_UFFS_ECC_MODE 3
-#define PKG_USING_DFS_UFFS_LATEST_VERSION
-#define PKG_USING_RAMDISK
-#define PKG_USING_RAMDISK_LATEST_VERSION
-
-/* peripheral libraries and drivers */
-
-
-/* AI packages */
-
-
-/* miscellaneous packages */
-
-/* samples: kernel and components samples */
-
-
-/* entertainment: terminal games and other interesting software packages */
-
-#define PKG_USING_OPTPARSE
-#define PKG_USING_OPTPARSE_LATEST_VERSION
-
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_DEMO
-#define NU_PKG_USING_NAU8822
-#define NU_PKG_USING_ILI9341
-#define NU_PKG_USING_ILI9341_SPI
-#define NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER
-#define NU_PKG_ILI9341_HORIZONTAL
-#define NU_PKG_USING_SPINAND
-
-/* Hardware Drivers Config */
-
-/* On-chip Peripheral Drivers */
-
-#define SOC_SERIES_NUC980
-#define BSP_USE_STDDRIVER_SOURCE
-#define BSP_USING_MMU
-#define BSP_USING_PDMA
-#define NU_PDMA_MEMFUN_ACTOR_MAX 2
-#define BSP_USING_GPIO
-#define BSP_USING_EMAC
-#define BSP_USING_EMAC0
-#define BSP_USING_RTC
-#define NU_RTC_SUPPORT_IO_RW
-#define NU_RTC_SUPPORT_MSH_CMD
-#define BSP_USING_ADC
-#define BSP_USING_TMR
-#define BSP_USING_TIMER
-#define BSP_USING_TMR0
-#define BSP_USING_TIMER0
-#define BSP_USING_TMR1
-#define BSP_USING_TIMER1
-#define BSP_USING_TMR2
-#define BSP_USING_TIMER2
-#define BSP_USING_TMR3
-#define BSP_USING_TIMER3
-#define BSP_USING_TMR4
-#define BSP_USING_TIMER4
-#define BSP_USING_UART
-#define BSP_USING_UART0
-#define BSP_USING_UART1
-#define BSP_USING_UART1_TX_DMA
-#define BSP_USING_UART1_RX_DMA
-#define BSP_USING_I2C
-#define BSP_USING_I2C0
-#define BSP_USING_I2C2
-#define BSP_USING_SDH
-#define BSP_USING_SDH1
-#define NU_SDH_USING_PDMA
-#define NU_SDH_HOTPLUG
-#define BSP_USING_PWM
-#define BSP_USING_PWM0
-#define BSP_USING_SPI
-#define BSP_USING_SPI_PDMA
-#define BSP_USING_SPI0
-#define BSP_USING_SPI0_PDMA
-#define BSP_USING_SPI1_NONE
-#define BSP_USING_I2S
-#define NU_I2S_DMA_FIFO_SIZE 4096
-#define BSP_USING_QSPI
-#define BSP_USING_QSPI_PDMA
-#define BSP_USING_QSPI0
-#define BSP_USING_QSPI0_PDMA
-#define BSP_USING_CRYPTO
-#define BSP_USING_WDT
-#define BSP_USING_USBD
-#define BSP_USING_USBH
-
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_CONSOLE
-#define BOARD_USING_IP101GR
-#define BOARD_USING_NAU8822
-#define BOARD_USING_STORAGE_SDCARD
-#define BOARD_USING_STORAGE_SPINAND
-#define BOARD_USING_USB0_DEVICE_HOST
-#define BOARD_USING_USB1_HOST
-
-/* Board extended module drivers */
-
-#define BOARD_USING_LCD_ILI9341
-#define BOARD_USING_ILI9341_PIN_BACKLIGHT 103
-#define BOARD_USING_ILI9341_PIN_RESET 90
-#define BOARD_USING_ILI9341_PIN_DC 89
-
-#endif
diff --git a/bsp/nuvoton/nk-980iot/rtconfig.py b/bsp/nuvoton/nk-980iot/rtconfig.py
index 1f8263adae..7412b89abf 100644
--- a/bsp/nuvoton/nk-980iot/rtconfig.py
+++ b/bsp/nuvoton/nk-980iot/rtconfig.py
@@ -85,4 +85,10 @@ elif PLATFORM == 'armcc':
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
- POST_ACTION += 'fromelf -z $TARGET\n'
\ No newline at end of file
+ POST_ACTION += 'fromelf -z $TARGET\n'
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nuvoton/nk-980iot/spinor.config b/bsp/nuvoton/nk-980iot/spinor.config
index d93d276436..689099bb5b 100644
--- a/bsp/nuvoton/nk-980iot/spinor.config
+++ b/bsp/nuvoton/nk-980iot/spinor.config
@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
@@ -17,10 +18,19 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=2048
# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -48,13 +58,18 @@ CONFIG_RT_USING_SIGNALS=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
-CONFIG_RT_USING_MEMHEAP=y
-# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BSET_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_MEMTRACE=y
+# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
@@ -66,7 +81,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-CONFIG_RT_VER_NUM=0x40003
+CONFIG_RT_VER_NUM=0x40100
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_ARM9=y
@@ -79,6 +94,7 @@ CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
#
# C++ features
@@ -89,25 +105,26 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
# Command shell
#
CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=16
CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
@@ -125,27 +142,32 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=8
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=2048
CONFIG_RT_USING_CAN=y
@@ -167,9 +189,6 @@ CONFIG_RT_USING_PWM=y
CONFIG_RT_USING_RTC=y
CONFIG_RT_USING_ALARM=y
# CONFIG_RT_USING_SOFT_RTC is not set
-CONFIG_RTC_SYNC_USING_NTP=y
-CONFIG_RTC_NTP_FIRST_SYNC_DELAY=30
-CONFIG_RTC_NTP_SYNC_PERIOD=3600
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
CONFIG_RT_USING_QSPI=y
@@ -220,9 +239,11 @@ CONFIG_RT_HWCRYPTO_USING_RNG=y
#
# Using USB
#
+CONFIG_RT_USING_USB=y
CONFIG_RT_USING_USB_HOST=y
CONFIG_RT_USBH_MSTORAGE=y
CONFIG_UDISK_MOUNTPOINT="/mnt/udisk"
+# CONFIG_RT_USBH_HID is not set
CONFIG_RT_USING_USB_DEVICE=y
CONFIG_RT_USBD_THREAD_STACK_SZ=4096
CONFIG_USB_VENDOR_ID=0x0FFE
@@ -247,14 +268,34 @@ CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1"
#
# POSIX layer and C standard library
#
-CONFIG_RT_USING_LIBC=y
-# CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_GETLINE is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
#
# Network
@@ -264,7 +305,7 @@ CONFIG_RT_USING_POSIX=y
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
-CONFIG_SAL_INTERNET_CHECK=y
+# CONFIG_SAL_INTERNET_CHECK is not set
#
# protocol stack implement
@@ -290,8 +331,9 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP212 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
CONFIG_RT_LWIP_IGMP=y
@@ -305,30 +347,30 @@ CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
-CONFIG_RT_LWIP_IPADDR="192.168.1.30"
-CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_IPADDR="192.168.31.55"
+CONFIG_RT_LWIP_GWADDR="192.168.31.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
-CONFIG_RT_MEMP_NUM_NETCONN=32
+CONFIG_RT_MEMP_NUM_NETCONN=16
CONFIG_RT_LWIP_PBUF_NUM=256
-CONFIG_RT_LWIP_RAW_PCB_NUM=32
-CONFIG_RT_LWIP_UDP_PCB_NUM=32
-CONFIG_RT_LWIP_TCP_PCB_NUM=32
-CONFIG_RT_LWIP_TCP_SEG_NUM=256
-CONFIG_RT_LWIP_TCP_SND_BUF=32768
-CONFIG_RT_LWIP_TCP_WND=10240
+CONFIG_RT_LWIP_RAW_PCB_NUM=16
+CONFIG_RT_LWIP_UDP_PCB_NUM=16
+CONFIG_RT_LWIP_TCP_PCB_NUM=16
+CONFIG_RT_LWIP_TCP_SEG_NUM=64
+CONFIG_RT_LWIP_TCP_SND_BUF=16384
+CONFIG_RT_LWIP_TCP_WND=65535
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
-CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=256
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
-CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
-CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32
-# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=4096
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=256
+CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
@@ -362,8 +404,15 @@ CONFIG_RT_LWIP_USING_PING=y
CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
#
# RT-Thread online packages
#
@@ -411,22 +460,25 @@ CONFIG_PKG_NETUTILS_TFTP=y
CONFIG_PKG_NETUTILS_IPERF=y
# CONFIG_PKG_NETUTILS_NETIO is not set
CONFIG_PKG_NETUTILS_NTP=y
-CONFIG_NETUTILS_NTP_TIMEZONE=8
+CONFIG_NTP_USING_AUTO_SYNC=y
+CONFIG_NTP_AUTO_SYNC_FIRST_DELAY=30
+CONFIG_NTP_AUTO_SYNC_PERIOD=3600
CONFIG_NETUTILS_NTP_HOSTNAME="0.tw.pool.ntp.org"
CONFIG_NETUTILS_NTP_HOSTNAME2="1.tw.pool.ntp.org"
CONFIG_NETUTILS_NTP_HOSTNAME3="2.tw.pool.ntp.org"
# CONFIG_PKG_NETUTILS_TELNET is not set
# CONFIG_PKG_NETUTILS_TCPDUMP is not set
-CONFIG_PKG_USING_NETUTILS_V120=y
-# CONFIG_PKG_USING_NETUTILS_V110 is not set
-# CONFIG_PKG_USING_NETUTILS_V100 is not set
# CONFIG_PKG_USING_NETUTILS_LATEST_VERSION is not set
-CONFIG_PKG_NETUTILS_VER="v1.2.0"
+CONFIG_PKG_USING_NETUTILS_V131=y
+# CONFIG_PKG_USING_NETUTILS_V130 is not set
+CONFIG_PKG_NETUTILS_VER="v1.3.1"
+CONFIG_PKG_NETUTILS_VER_NUM=0x10301
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
@@ -439,6 +491,7 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@@ -447,8 +500,6 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
@@ -462,12 +513,26 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
@@ -475,21 +540,51 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
#
# language packages
#
+# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -498,9 +593,11 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
@@ -514,15 +611,72 @@ CONFIG_PKG_NETUTILS_VER="v1.2.0"
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+CONFIG_PKG_USING_MEM_SANDBOX=y
+CONFIG_PKG_MEM_SANDBOX_PATH="/packages/tools/mem_sandbox"
+CONFIG_PKG_USING_MEM_SANDBOX_LATEST_VERSION=y
+CONFIG_PKG_MEM_SANDBOX_VER="latest"
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
#
# system packages
#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# POSIX extension functions
+#
+# CONFIG_PKG_USING_POSIX_GETLINE is not set
+# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
+# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_RT_USING_ARDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
CONFIG_PKG_USING_FAL=y
CONFIG_PKG_FAL_PATH="/packages/system/fal"
@@ -542,10 +696,11 @@ CONFIG_PKG_FAL_VER_NUM=0x99999
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
@@ -559,17 +714,15 @@ CONFIG_PKG_USING_RAMDISK_LATEST_VERSION=y
CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
-
-#
-# Micrium: Micrium software products porting for RT-Thread
-#
-# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
-# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
-# CONFIG_PKG_USING_UC_CRC is not set
-# CONFIG_PKG_USING_UC_CLK is not set
-# CONFIG_PKG_USING_UC_COMMON is not set
-# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_USB_STACK is not set
#
# peripheral libraries and drivers
@@ -578,9 +731,9 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
-# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@@ -593,7 +746,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
@@ -627,16 +779,73 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
CONFIG_PKG_USING_OPTPARSE=y
CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse"
-CONFIG_PKG_USING_OPTPARSE_V100=y
-# CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION is not set
-CONFIG_PKG_OPTPARSE_VER="v1.0.0"
+CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION=y
+CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_OPTPARSE_USING_DEMO is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
@@ -646,69 +855,44 @@ CONFIG_PKG_OPTPARSE_VER="v1.0.0"
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
CONFIG_PKG_USING_VI=y
CONFIG_PKG_VI_PATH="/packages/misc/vi"
+CONFIG_VI_SANDBOX_SIZE_KB=20
CONFIG_VI_MAX_LEN=4096
# CONFIG_VI_ENABLE_8BIT is not set
CONFIG_VI_ENABLE_COLON=y
+CONFIG_VI_ENABLE_COLON_EXPAND=y
CONFIG_VI_ENABLE_YANKMARK=y
CONFIG_VI_ENABLE_SEARCH=y
CONFIG_VI_ENABLE_DOT_CMD=y
CONFIG_VI_ENABLE_READONLY=y
CONFIG_VI_ENABLE_SETOPTS=y
CONFIG_VI_ENABLE_SET=y
+# CONFIG_VI_ENABLE_WIN_RESIZE is not set
CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y
CONFIG_VI_ENABLE_UNDO=y
CONFIG_VI_ENABLE_UNDO_QUEUE=y
CONFIG_VI_UNDO_QUEUE_MAX=256
+CONFIG_VI_ENABLE_VERBOSE_STATUS=y
CONFIG_PKG_USING_VI_LATEST_VERSION=y
CONFIG_PKG_VI_VER="latest"
# CONFIG_PKG_USING_KI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
-# CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
-
-#
-# games: games run on RT-Thread console
-#
-# CONFIG_PKG_USING_THREES is not set
-# CONFIG_PKG_USING_2048 is not set
-# CONFIG_PKG_USING_SNAKE is not set
-# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
-# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
-
-#
-# Nuvoton Packages Config
-#
-CONFIG_NU_PKG_USING_UTILS=y
-CONFIG_NU_PKG_USING_DEMO=y
-# CONFIG_NU_PKG_USING_BMX055 is not set
-# CONFIG_NU_PKG_USING_MAX31875 is not set
-# CONFIG_NU_PKG_USING_NAU88L25 is not set
-CONFIG_NU_PKG_USING_NAU8822=y
-# CONFIG_NU_PKG_USING_ILI9341 is not set
-# CONFIG_NU_PKG_USING_SPINAND is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
@@ -718,12 +902,11 @@ CONFIG_NU_PKG_USING_NAU8822=y
# On-chip Peripheral Drivers
#
CONFIG_SOC_SERIES_NUC980=y
-# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set
+CONFIG_BSP_USE_STDDRIVER_SOURCE=y
CONFIG_BSP_USING_MMU=y
CONFIG_BSP_USING_PDMA=y
CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2
CONFIG_BSP_USING_GPIO=y
-# CONFIG_BSP_USING_CLK is not set
CONFIG_BSP_USING_EMAC=y
CONFIG_BSP_USING_EMAC0=y
# CONFIG_BSP_USING_EMAC1 is not set
@@ -732,27 +915,23 @@ CONFIG_BSP_USING_RTC=y
CONFIG_NU_RTC_SUPPORT_IO_RW=y
CONFIG_NU_RTC_SUPPORT_MSH_CMD=y
CONFIG_BSP_USING_ADC=y
+# CONFIG_BSP_USING_ADC_TOUCH is not set
CONFIG_BSP_USING_TMR=y
CONFIG_BSP_USING_TIMER=y
CONFIG_BSP_USING_TMR0=y
CONFIG_BSP_USING_TIMER0=y
-# CONFIG_BSP_USING_TPWM0 is not set
# CONFIG_BSP_USING_TIMER0_CAPTURE is not set
CONFIG_BSP_USING_TMR1=y
CONFIG_BSP_USING_TIMER1=y
-# CONFIG_BSP_USING_TPWM1 is not set
# CONFIG_BSP_USING_TIMER1_CAPTURE is not set
CONFIG_BSP_USING_TMR2=y
CONFIG_BSP_USING_TIMER2=y
-# CONFIG_BSP_USING_TPWM2 is not set
# CONFIG_BSP_USING_TIMER2_CAPTURE is not set
CONFIG_BSP_USING_TMR3=y
CONFIG_BSP_USING_TIMER3=y
-# CONFIG_BSP_USING_TPWM3 is not set
# CONFIG_BSP_USING_TIMER3_CAPTURE is not set
CONFIG_BSP_USING_TMR4=y
CONFIG_BSP_USING_TIMER4=y
-# CONFIG_BSP_USING_TPWM4 is not set
# CONFIG_BSP_USING_TIMER4_CAPTURE is not set
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
@@ -794,8 +973,9 @@ CONFIG_BSP_USING_SPI1_NONE=y
CONFIG_BSP_USING_I2S=y
CONFIG_NU_I2S_DMA_FIFO_SIZE=4096
CONFIG_BSP_USING_QSPI=y
+# CONFIG_BSP_USING_QSPI_PDMA is not set
CONFIG_BSP_USING_QSPI0=y
-CONFIG_BSP_USING_QSPI0_PDMA=y
+# CONFIG_BSP_USING_QSPI0_PDMA is not set
# CONFIG_BSP_USING_SCUART is not set
CONFIG_BSP_USING_CRYPTO=y
# CONFIG_NU_PRNG_USE_SEED is not set
@@ -823,5 +1003,18 @@ CONFIG_BOARD_USING_USB1_HOST=y
# CONFIG_BOARD_USING_MAX31875 is not set
# CONFIG_BOARD_USING_LCD_ILI9341 is not set
# CONFIG_BOARD_USING_ESP8266 is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+# CONFIG_NU_PKG_USING_NAU88L25 is not set
+CONFIG_NU_PKG_USING_NAU8822=y
+# CONFIG_NU_PKG_USING_DA9062 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
CONFIG_BOARD_USE_UTEST=y
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.nk980-iot.test.utest."
diff --git a/bsp/nuvoton/nk-n9h30/.config b/bsp/nuvoton/nk-n9h30/.config
index d235edc087..d561d34221 100644
--- a/bsp/nuvoton/nk-n9h30/.config
+++ b/bsp/nuvoton/nk-n9h30/.config
@@ -310,8 +310,8 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP203 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@@ -744,6 +744,7 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -832,19 +833,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
-#
-# Nuvoton Packages Config
-#
-CONFIG_NU_PKG_USING_UTILS=y
-# CONFIG_NU_PKG_USING_DEMO is not set
-# CONFIG_NU_PKG_USING_BMX055 is not set
-# CONFIG_NU_PKG_USING_MAX31875 is not set
-# CONFIG_NU_PKG_USING_NAU88L25 is not set
-CONFIG_NU_PKG_USING_NAU8822=y
-# CONFIG_NU_PKG_USING_DA9062 is not set
-# CONFIG_NU_PKG_USING_ILI9341 is not set
-# CONFIG_NU_PKG_USING_SPINAND is not set
-
#
# Hardware Drivers Config
#
@@ -929,6 +917,7 @@ CONFIG_BSP_USING_VPOST=y
# CONFIG_LCM_USING_LSA40AT9001 is not set
CONFIG_LCM_USING_FW070TFT=y
# CONFIG_LCM_USING_FW043TFT is not set
+# CONFIG_LCM_USING_FW070TFT_WSVGA is not set
CONFIG_VPOST_USING_LCD_IDX=3
CONFIG_BSP_LCD_BPP=32
CONFIG_BSP_LCD_WIDTH=800
@@ -946,10 +935,30 @@ CONFIG_BOARD_USING_NAU8822=y
CONFIG_BOARD_USING_STORAGE_SDCARD=y
CONFIG_BOARD_USING_STORAGE_SPIFLASH=y
CONFIG_BOARD_USING_BUZZER=y
-CONFIG_BOARD_USING_LCM=y
CONFIG_BOARD_USING_USB0_DEVICE_HOST=y
CONFIG_BOARD_USING_USB1_HOST=y
#
# Board extended module drivers
#
+CONFIG_BOARD_USING_LCM=y
+CONFIG_BOARD_USING_LCM_FW070TFT_WVGA=y
+# CONFIG_BOARD_USING_LCM_FW043TFT_HVGA is not set
+# CONFIG_BOARD_USING_LCM_FW070TFT_WSVGA is not set
+CONFIG_BOARD_USING_ADCTOUCH=y
+# CONFIG_BOARD_USING_GT911 is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+# CONFIG_NU_PKG_USING_DEMO is not set
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+# CONFIG_NU_PKG_USING_NAU88L25 is not set
+CONFIG_NU_PKG_USING_NAU8822=y
+# CONFIG_NU_PKG_USING_DA9062 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.nk-n9h30.test.utest."
diff --git a/bsp/nuvoton/nk-n9h30/Kconfig b/bsp/nuvoton/nk-n9h30/Kconfig
index 5c55e87c61..b396340d12 100644
--- a/bsp/nuvoton/nk-n9h30/Kconfig
+++ b/bsp/nuvoton/nk-n9h30/Kconfig
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_disp.c b/bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_disp.c
index 266be12a31..3162bf8d2b 100644
--- a/bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_disp.c
+++ b/bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_disp.c
@@ -26,9 +26,30 @@ static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/
static void *buf3_next = RT_NULL;
+static uint32_t u32FirstFlush = 0;
+
+static void nu_antitearing(lv_disp_draw_buf_t *draw_buf, lv_color_t *color_p)
+{
+ if (buf3_next)
+ {
+ /* vsync-none: Use triple screen-sized buffers. */
+ if (draw_buf->buf1 == color_p)
+ draw_buf->buf1 = buf3_next;
+ else
+ draw_buf->buf2 = buf3_next;
+
+ draw_buf->buf_act = buf3_next;
+ buf3_next = color_p;
+ }
+ else
+ {
+ /* vsync-after: Use ping-pong screen-sized buffers only.*/
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_WAIT_VSYNC, RT_NULL);
+ }
+}
+
static void nu_flush_direct(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
{
- lv_disp_t *psDisp = _lv_refr_get_disp_refreshing();
void *pvDstReDraw;
#if (LV_USE_GPU_N9H30_GE2D==0)
@@ -55,8 +76,14 @@ static void nu_flush_direct(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_c
mmu_invalidate_dcache((uint32_t)pvDstReDraw, disp_drv->draw_buf->size * sizeof(lv_color_t));
#endif
- /* WAIT_VSYNC */
- rt_device_control(lcd_device, RTGRAPHIC_CTRL_WAIT_VSYNC, RT_NULL);
+ nu_antitearing(disp_drv->draw_buf, color_p);
+
+ if (!u32FirstFlush)
+ {
+ /* Enable backlight at first flushing. */
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL);
+ u32FirstFlush = 1;
+ }
lv_disp_flush_ready(disp_drv);
}
@@ -70,21 +97,13 @@ static void nu_flush_full_refresh(lv_disp_drv_t *disp_drv, const lv_area_t *area
/* Use PANDISPLAY without H/W copying */
rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, color_p);
- if (buf3_next)
- {
- /* vsync-none: Use triple screen-sized buffers. */
- if (disp_drv->draw_buf->buf1 == color_p)
- disp_drv->draw_buf->buf1 = buf3_next;
- else
- disp_drv->draw_buf->buf2 = buf3_next;
+ nu_antitearing(disp_drv->draw_buf, color_p);
- disp_drv->draw_buf->buf_act = buf3_next;
- buf3_next = color_p;
- }
- else
+ if (!u32FirstFlush)
{
- /* vsync-after: Use ping-pong screen-sized buffers only.*/
- rt_device_control(lcd_device, RTGRAPHIC_CTRL_WAIT_VSYNC, RT_NULL);
+ /* Enable backlight at first flushing. */
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL);
+ u32FirstFlush = 1;
}
lv_disp_flush_ready(disp_drv);
@@ -106,6 +125,13 @@ static void nu_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t
ge2dSpriteBlt_Screen(area->x1, area->y1, flush_area_w, flush_area_h, (void *)color_p);
// -> Leave GE2D
+ if (!u32FirstFlush)
+ {
+ /* Enable backlight at first flushing. */
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL);
+ u32FirstFlush = 1;
+ }
+
lv_disp_flush_ready(disp_drv);
}
@@ -188,6 +214,9 @@ void lv_port_disp_init(void)
return;
}
+ /* Disable backlight at startup. */
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWEROFF, RT_NULL);
+
RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
diff --git a/bsp/nuvoton/nk-n9h30/applications/mnt.c b/bsp/nuvoton/nk-n9h30/applications/mnt.c
index 03e7481242..9fdf7ec3a1 100644
--- a/bsp/nuvoton/nk-n9h30/applications/mnt.c
+++ b/bsp/nuvoton/nk-n9h30/applications/mnt.c
@@ -21,10 +21,12 @@
#define DBG_COLOR
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
#if defined(PKG_USING_FAL)
#include
diff --git a/bsp/nuvoton/nk-n9h30/board/Kconfig b/bsp/nuvoton/nk-n9h30/board/Kconfig
index c26e25fb65..379add6d0b 100644
--- a/bsp/nuvoton/nk-n9h30/board/Kconfig
+++ b/bsp/nuvoton/nk-n9h30/board/Kconfig
@@ -45,12 +45,6 @@ menu "Hardware Drivers Config"
select BSP_USING_PWM0
default n
- config BOARD_USING_LCM
- bool "NuDesign TFT-LCD7(over vpost)"
- select BSP_USING_VPOST
- select LCM_USING_FW070TFT
- default y
-
config BOARD_USING_USB0_DEVICE_HOST
select BSP_USING_USBH
select BSP_USING_USBD
@@ -69,7 +63,61 @@ menu "Hardware Drivers Config"
menu "Board extended module drivers"
+ config BOARD_USING_LCM
+ bool "Use LCD panel."
+ default y
+
+ if BOARD_USING_LCM
+
+ choice
+ prompt "Select LCD panel devices.(Over VPOST)"
+ default BOARD_USING_LCM_FW070TFT_WVGA
+
+ config BOARD_USING_LCM_FW070TFT_WVGA
+ bool "NuDesign TFT-LCD7-WVGA"
+ select BSP_USING_VPOST
+ select LCM_USING_FW070TFT
+ help
+ Choose this option if you use 7" 800x480x32b LCD panel.
+
+ config BOARD_USING_LCM_FW043TFT_HVGA
+ bool "NuDesign TFT-LCD43-HVGA"
+ select BSP_USING_VPOST
+ select LCM_USING_FW043TFT
+ help
+ Choose this option if you use 4.3" 480x272x32b LCD panel.
+
+ config BOARD_USING_LCM_FW070TFT_WSVGA
+ bool "NuDesign TFT-LCD7-WSVGA"
+ select BSP_USING_VPOST
+ select LCM_USING_FW070TFT_WSVGA
+ help
+ Choose this option if you use 7" 1024x600x32b LCD panel.
+ endchoice
+
+ choice
+ prompt "Select Touch devices."
+ default BOARD_USING_ADCTOUCH
+
+ config BOARD_USING_ADCTOUCH
+ bool "ADC touching"
+ select BSP_USING_ADC_TOUCH
+ help
+ Choose this option if you use internal ADC touching function.
+
+ config BOARD_USING_GT911
+ bool "GT911 TSC"
+ select BSP_USING_I2C
+ select BSP_USING_I2C0
+ select PKG_USING_GT911
+ help
+ Choose this option if you use GT911 external TSC touching function.
+ endchoice
+
+ endif
+
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
endmenu
diff --git a/bsp/nuvoton/nk-n9h30/board/board_dev.c b/bsp/nuvoton/nk-n9h30/board/board_dev.c
index 42d1bdac94..ba21df17dd 100644
--- a/bsp/nuvoton/nk-n9h30/board/board_dev.c
+++ b/bsp/nuvoton/nk-n9h30/board/board_dev.c
@@ -173,6 +173,34 @@ int rt_hw_nau8822_port(void)
INIT_COMPONENT_EXPORT(rt_hw_nau8822_port);
#endif /* BOARD_USING_NAU8822 */
+//#if defined(BOARD_USING_GT911) && defined(PKG_USING_GT911)
+#if defined(PKG_USING_GT911)
+#include "drv_gpio.h"
+#include "gt911.h"
+
+#define GT911_RST_PIN NU_GET_PININDEX(NU_PG, 4)
+#define GT911_IRQ_PIN NU_GET_PININDEX(NU_PG, 5)
+
+extern int gt911_sample(const char *name, rt_uint16_t x, rt_uint16_t y);
+int rt_hw_gt911_port(void)
+{
+ struct rt_touch_config cfg;
+ rt_uint8_t rst_pin;
+
+ rst_pin = GT911_RST_PIN;
+ cfg.dev_name = "i2c0";
+ cfg.irq_pin.pin = GT911_IRQ_PIN;
+ cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN;
+ cfg.user_data = &rst_pin;
+
+ rt_hw_gt911_init("gt911", &cfg);
+ gt911_sample("gt911", BSP_LCD_WIDTH, BSP_LCD_HEIGHT);
+
+ return 0;
+}
+INIT_ENV_EXPORT(rt_hw_gt911_port);
+#endif /* if defined(BOARD_USING_GT911) && defined(PKG_USING_GT911) */
+
#if defined(BOARD_USING_BUZZER)
#define PWM_DEV_NAME "pwm0"
@@ -224,13 +252,13 @@ static void PlayRingTone(void)
#include
/* defined the LCM_BLEN pin: PH3 */
- #define LCM_BLEN NU_GET_PININDEX(NU_PH, 3)
+ #define LCM_BACKLIGHT_CTRL NU_GET_PININDEX(NU_PH, 3)
#endif
-#define PWM_DEV_NAME "pwm0"
-#define LCM_PWM_CHANNEL (0)
+#define PWM_DEV_NAME "pwm0"
+#define LCM_PWM_CHANNEL (0)
-static void LCMLightOn(void)
+void nu_lcd_backlight_on(void)
{
struct rt_device_pwm *pwm_dev;
@@ -243,10 +271,27 @@ static void LCMLightOn(void)
{
rt_kprintf("Can't find %s\n", PWM_DEV_NAME);
}
+
+ rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT);
+ rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_HIGH);
+}
+
+void nu_lcd_backlight_off(void)
+{
+ struct rt_device_pwm *pwm_dev;
+
+ if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME)) != RT_NULL)
+ {
+ rt_pwm_disable(pwm_dev, LCM_PWM_CHANNEL);
+ }
+ else
+ {
+ rt_kprintf("Can't find %s\n", PWM_DEV_NAME);
+ }
+
+ rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT);
+ rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_LOW);
}
-#ifdef FINSH_USING_MSH
- MSH_CMD_EXPORT(LCMLightOn, LCM - light on panel);
-#endif
int rt_hw_lcm_port(void)
{
@@ -259,9 +304,6 @@ int rt_hw_lcm_port(void)
}
#endif
- /* Use PWM to control backlight. */
- LCMLightOn();
-
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_lcm_port);
diff --git a/bsp/nuvoton/nk-n9h30/project.uvproj b/bsp/nuvoton/nk-n9h30/project.uvproj
deleted file mode 100644
index f3ff2ed8d7..0000000000
--- a/bsp/nuvoton/nk-n9h30/project.uvproj
+++ /dev/null
@@ -1,1791 +0,0 @@
-
-
- 1.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread
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- --c99
- __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
-
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-
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diff --git a/bsp/nuvoton/nk-n9h30/project.uvprojx b/bsp/nuvoton/nk-n9h30/project.uvprojx
deleted file mode 100644
index 6dc5488c5c..0000000000
--- a/bsp/nuvoton/nk-n9h30/project.uvprojx
+++ /dev/null
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- ..\libraries\n9h30\rtt_port\drv_usbhost.c
-
-
-
-
- drv_crypto.c
- 1
- ..\libraries\n9h30\rtt_port\drv_crypto.c
-
-
-
-
- drv_systick.c
- 1
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-
-
-
-
- drv_gpio.c
- 1
- ..\libraries\n9h30\rtt_port\drv_gpio.c
-
-
-
-
- drv_scuart.c
- 1
- ..\libraries\n9h30\rtt_port\drv_scuart.c
-
-
-
-
- drv_etimer.c
- 1
- ..\libraries\n9h30\rtt_port\drv_etimer.c
-
-
-
-
- drv_wdt.c
- 1
- ..\libraries\n9h30\rtt_port\drv_wdt.c
-
-
-
-
- drv_adc.c
- 1
- ..\libraries\n9h30\rtt_port\drv_adc.c
-
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-
-
- drv_qspi.c
- 1
- ..\libraries\n9h30\rtt_port\drv_qspi.c
-
-
-
-
- drv_i2s.c
- 1
- ..\libraries\n9h30\rtt_port\drv_i2s.c
-
-
-
-
- drv_sdh.c
- 1
- ..\libraries\n9h30\rtt_port\drv_sdh.c
-
-
-
-
- drv_i2c.c
- 1
- ..\libraries\n9h30\rtt_port\drv_i2c.c
-
-
-
-
- drv_softi2c.c
- 1
- ..\libraries\n9h30\rtt_port\drv_softi2c.c
-
-
-
-
- drv_uart.c
- 1
- ..\libraries\n9h30\rtt_port\drv_uart.c
-
-
-
-
- drv_etimer_capture.c
- 1
- ..\libraries\n9h30\rtt_port\drv_etimer_capture.c
-
-
-
-
- drv_vpost.c
- 1
- ..\libraries\n9h30\rtt_port\drv_vpost.c
-
-
-
-
- drv_adc_touch.c
- 1
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-
-
-
-
- drv_rtc.c
- 1
- ..\libraries\n9h30\rtt_port\drv_rtc.c
-
-
-
-
- drv_sys.c
- 1
- ..\libraries\n9h30\rtt_port\drv_sys.c
-
-
-
-
- drv_jpegcodec.c
- 1
- ..\libraries\n9h30\rtt_port\drv_jpegcodec.c
-
-
-
-
- drv_ge2d.c
- 1
- ..\libraries\n9h30\rtt_port\drv_ge2d.c
-
-
-
-
- Filesystem
-
-
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- 1
- ..\..\..\components\dfs\src\dfs_posix.c
-
-
-
-
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-
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- 1
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-
-
-
-
- dfs_file.c
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-
-
-
-
- devfs.c
- 1
- ..\..\..\components\dfs\filesystems\devfs\devfs.c
-
-
-
-
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-
-
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- 1
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-
-
-
-
- ffunicode.c
- 1
- ..\..\..\components\dfs\filesystems\elmfat\ffunicode.c
-
-
-
-
- Finsh
-
-
- shell.c
- 1
- ..\..\..\components\finsh\shell.c
-
-
-
-
- msh.c
- 1
- ..\..\..\components\finsh\msh.c
-
-
-
-
- msh_file.c
- 1
- ..\..\..\components\finsh\msh_file.c
-
-
-
-
- cmd.c
- 1
- ..\..\..\components\finsh\cmd.c
-
-
-
-
- Kernel
-
-
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- 1
- ..\..\..\src\timer.c
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-
-
-
- device.c
- 1
- ..\..\..\src\device.c
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- 1
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- ..\..\..\src\irq.c
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-
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- 1
- ..\..\..\src\signal.c
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- mempool.c
- 1
- ..\..\..\src\mempool.c
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-
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- idle.c
- 1
- ..\..\..\src\idle.c
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-
-
- kservice.c
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- ..\..\..\src\kservice.c
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-
-
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- components.c
- 1
- ..\..\..\src\components.c
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-
-
-
- Libraries
-
-
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-
-
-
- nu_lcd.c
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-
-
-
- nu_usbd.c
- 1
- ..\libraries\n9h30\Driver\Source\nu_usbd.c
-
-
-
-
- nu_i2s.c
- 1
- ..\libraries\n9h30\Driver\Source\nu_i2s.c
-
-
-
-
- nu_rtc.c
- 1
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-
-
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- nu_pwm.c
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-
-
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-
- nu_sys.c
- 1
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-
-
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- nu_spi.c
- 1
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-
-
-
- nu_etimer.c
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-
-
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- nu_timer.c
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-
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- 1
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-
-
-
-
- nu_fmi.c
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-
-
-
-
- nu_gpio.c
- 1
- ..\libraries\n9h30\Driver\Source\nu_gpio.c
-
-
-
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- nu_wdt.c
- 1
- ..\libraries\n9h30\Driver\Source\nu_wdt.c
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-
-
-
- nu_scuart.c
- 1
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-
-
-
-
- nu_crypto.c
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-
-
-
-
- nu_uart.c
- 1
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-
-
-
-
- nu_sdh.c
- 1
- ..\libraries\n9h30\Driver\Source\nu_sdh.c
-
-
-
-
- nu_cap.c
- 1
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-
-
-
-
- LVGL-port
-
-
- lv_port_disp.c
- 1
- applications\lvgl\lv_port_disp.c
-
-
-
-
- lv_port_indev.c
- 1
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-
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- 1
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- 1
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- igmp.c
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-
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- tcp.c
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- ..\..\..\components\net\lwip-2.0.2\src\core\tcp.c
-
-
-
-
- n9h30_usbhostlib
-
-
- ohci.c
- 1
- ..\libraries\n9h30\UsbHostLib\src\ohci.c
-
-
-
-
- usb_core.c
- 1
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-
-
-
-
- mem_alloc.c
- 1
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-
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- support.c
- 1
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-
-
- ehci.c
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-
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-
- ehci_iso.c
- 1
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-
-
-
-
- nu_pkgs_nau8822
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- 1
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- POSIX
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- poll.c
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-
- rt_usbd
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- mstorage.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\mstorage.c
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-
-
-
- usbdevice_core.c
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-
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- cdc_vcom.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c
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-
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- usbdevice.c
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-
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- rt_usbh
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-
-
-
- usbhost_core.c
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-
-
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- SAL
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-
- netdev.c
- 1
- ..\..\..\components\net\netdev\src\netdev.c
-
-
-
-
- netdev_ipaddr.c
- 1
- ..\..\..\components\net\netdev\src\netdev_ipaddr.c
-
-
-
-
- sal_socket.c
- 1
- ..\..\..\components\net\sal_socket\src\sal_socket.c
-
-
-
-
- net_netdb.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_netdb.c
-
-
-
-
- net_sockets.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_sockets.c
-
-
-
-
- af_inet_lwip.c
- 1
- ..\..\..\components\net\sal_socket\impl\af_inet_lwip.c
-
-
-
-
- dfs_net.c
- 1
- ..\..\..\components\net\sal_socket\dfs_net\dfs_net.c
-
-
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-
- UTest
-
-
- utest.c
- 1
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-
-
-
-
-
-
-
-
-
-
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-
diff --git a/bsp/nuvoton/nk-n9h30/rtconfig.h b/bsp/nuvoton/nk-n9h30/rtconfig.h
deleted file mode 100644
index 1138f94322..0000000000
--- a/bsp/nuvoton/nk-n9h30/rtconfig.h
+++ /dev/null
@@ -1,422 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 16
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 2048
-
-/* kservice optimization */
-
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-#define RT_USING_SIGNALS
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_MEMHEAP
-#define RT_MEMHEAP_FAST_MODE
-#define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_MEMTRACE
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_INTERRUPT_INFO
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-#define ARCH_ARM
-#define ARCH_ARM_ARM9
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define RT_USING_MSH
-#define FINSH_USING_MSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_CMD_SIZE 80
-#define MSH_USING_BUILT_IN_COMMANDS
-#define FINSH_USING_DESCRIPTION
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 16
-#define DFS_FILESYSTEM_TYPES_MAX 16
-#define DFS_FD_MAX 64
-#define RT_USING_DFS_MNTTABLE
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_3
-#define RT_DFS_ELM_USE_LFN 3
-#define RT_DFS_ELM_LFN_UNICODE_0
-#define RT_DFS_ELM_LFN_UNICODE 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 8
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
-#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
-#define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_RB_BUFSZ 2048
-#define RT_USING_CAN
-#define RT_USING_HWTIMER
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_RTC
-#define RT_USING_ALARM
-#define RT_USING_SPI
-#define RT_USING_QSPI
-#define RT_USING_SFUD
-#define RT_SFUD_USING_SFDP
-#define RT_SFUD_USING_FLASH_INFO_TABLE
-#define RT_SFUD_USING_QSPI
-#define RT_SFUD_SPI_MAX_HZ 50000000
-#define RT_USING_WDT
-#define RT_USING_AUDIO
-#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
-#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
-#define RT_AUDIO_RECORD_PIPE_SIZE 2048
-#define RT_USING_TOUCH
-#define RT_USING_INPUT_CAPTURE
-#define RT_INPUT_CAPTURE_RB_SIZE 100
-
-/* Using USB */
-
-#define RT_USING_USB
-#define RT_USING_USB_HOST
-#define RT_USBH_MSTORAGE
-#define UDISK_MOUNTPOINT "/mnt/udisk"
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define RT_USB_DEVICE_COMPOSITE
-#define RT_USB_DEVICE_CDC
-#define RT_USB_DEVICE_NONE
-#define RT_USB_DEVICE_MSTORAGE
-#define RT_VCOM_TASK_STK_SIZE 512
-#define RT_CDC_RX_BUFSIZE 128
-#define RT_VCOM_SERNO "32021919830108"
-#define RT_VCOM_SER_LEN 14
-#define RT_VCOM_TX_TIMEOUT 1000
-#define RT_USB_MSTORAGE_DISK_NAME "ramdisk1"
-
-/* POSIX layer and C standard library */
-
-#define RT_LIBC_DEFAULT_TIMEZONE 8
-
-/* POSIX (Portable Operating System Interface) layer */
-
-#define RT_USING_POSIX_FS
-#define RT_USING_POSIX_DEVIO
-#define RT_USING_POSIX_POLL
-#define RT_USING_POSIX_SELECT
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-#define RT_USING_SAL
-#define SAL_INTERNET_CHECK
-
-/* protocol stack implement */
-
-#define SAL_USING_LWIP
-#define SAL_USING_POSIX
-
-/* Network interface device */
-
-#define RT_USING_NETDEV
-#define NETDEV_USING_IFCONFIG
-#define NETDEV_USING_PING
-#define NETDEV_USING_NETSTAT
-#define NETDEV_USING_AUTO_DEFAULT
-#define NETDEV_IPV4 1
-#define NETDEV_IPV6 0
-
-/* light weight TCP/IP stack */
-
-#define RT_USING_LWIP
-#define RT_USING_LWIP202
-#define RT_LWIP_MEM_ALIGNMENT 4
-#define RT_LWIP_IGMP
-#define RT_LWIP_ICMP
-#define RT_LWIP_DNS
-#define RT_LWIP_DHCP
-#define IP_SOF_BROADCAST 1
-#define IP_SOF_BROADCAST_RECV 1
-
-/* Static IPv4 Address */
-
-#define RT_LWIP_IPADDR "192.168.1.30"
-#define RT_LWIP_GWADDR "192.168.1.1"
-#define RT_LWIP_MSKADDR "255.255.255.0"
-#define RT_LWIP_UDP
-#define RT_LWIP_TCP
-#define RT_LWIP_RAW
-#define RT_MEMP_NUM_NETCONN 32
-#define RT_LWIP_PBUF_NUM 256
-#define RT_LWIP_RAW_PCB_NUM 32
-#define RT_LWIP_UDP_PCB_NUM 32
-#define RT_LWIP_TCP_PCB_NUM 32
-#define RT_LWIP_TCP_SEG_NUM 256
-#define RT_LWIP_TCP_SND_BUF 32768
-#define RT_LWIP_TCP_WND 10240
-#define RT_LWIP_TCPTHREAD_PRIORITY 10
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
-#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
-#define RT_LWIP_ETHTHREAD_PRIORITY 12
-#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32
-#define LWIP_NETIF_STATUS_CALLBACK 1
-#define LWIP_NETIF_LINK_CALLBACK 1
-#define SO_REUSE 1
-#define LWIP_SO_RCVTIMEO 1
-#define LWIP_SO_SNDTIMEO 1
-#define LWIP_SO_RCVBUF 1
-#define LWIP_SO_LINGER 0
-#define RT_LWIP_NETIF_LOOPBACK
-#define LWIP_NETIF_LOOPBACK 1
-#define RT_LWIP_STATS
-#define RT_LWIP_USING_PING
-
-/* AT commands */
-
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
-
-/* RT-Thread Utestcases */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-/* LVGL: powerful and easy-to-use embedded GUI library */
-
-#define PKG_USING_LVGL
-#define PKG_USING_LVGL_V810
-#define PKG_LVGL_VER_NUM 0x08010
-#define PKG_USING_LV_MUSIC_DEMO
-
-/* u8g2: a monochrome graphic library */
-
-
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
-/* acceleration: Assembly language or algorithmic acceleration packages */
-
-
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
-/* Micrium: Micrium software products porting for RT-Thread */
-
-#define PKG_USING_FAL
-#define FAL_DEBUG_CONFIG
-#define FAL_DEBUG 1
-#define FAL_PART_HAS_TABLE_CFG
-#define FAL_USING_SFUD_PORT
-#define FAL_USING_NOR_FLASH_DEV_NAME "norflash0"
-#define PKG_USING_FAL_LATEST_VERSION
-#define PKG_FAL_VER_NUM 0x99999
-#define PKG_USING_RAMDISK
-#define PKG_USING_RAMDISK_LATEST_VERSION
-
-/* peripheral libraries and drivers */
-
-
-/* AI packages */
-
-
-/* miscellaneous packages */
-
-/* samples: kernel and components samples */
-
-
-/* entertainment: terminal games and other interesting software packages */
-
-
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_NAU8822
-
-/* Hardware Drivers Config */
-
-/* On-chip Peripheral Drivers */
-
-#define SOC_SERIES_N9H30
-#define BSP_USING_MMU
-#define BSP_USING_GPIO
-#define BSP_USING_EMAC
-#define BSP_USING_EMAC0
-#define BSP_USING_EMAC1
-#define BSP_USING_RTC
-#define BSP_USING_ADC
-#define BSP_USING_ADC_TOUCH
-#define BSP_USING_ETMR
-#define BSP_USING_ETIMER
-#define BSP_USING_ETIMER_CAPTURE
-#define BSP_USING_ETMR0
-#define BSP_USING_ETIMER0
-#define BSP_USING_ETMR1
-#define BSP_USING_ETIMER1
-#define BSP_USING_ETMR2
-#define BSP_USING_ETIMER2_CAPTURE
-#define BSP_USING_ETMR3
-#define BSP_USING_ETIMER3_CAPTURE
-#define BSP_USING_TMR
-#define BSP_USING_TIMER
-#define BSP_USING_TIMER0
-#define BSP_USING_TIMER1
-#define BSP_USING_TIMER2
-#define BSP_USING_TIMER3
-#define BSP_USING_UART
-#define BSP_USING_UART0
-#define BSP_USING_I2C
-#define BSP_USING_I2C0
-#define BSP_USING_SDH
-#define BSP_USING_SDH0
-#define BSP_USING_SDH1
-#define NU_SDH_HOTPLUG
-#define BSP_USING_CAN
-#define BSP_USING_CAN0
-#define BSP_USING_PWM
-#define BSP_USING_PWM0
-#define BSP_USING_QSPI
-#define BSP_USING_QSPI0
-#define BSP_USING_QSPI1_NONE
-#define BSP_USING_I2S
-#define NU_I2S_DMA_FIFO_SIZE 2048
-#define BSP_USING_WDT
-#define BSP_USING_EBI
-#define BSP_USING_VPOST
-#define LCM_USING_FW070TFT
-#define VPOST_USING_LCD_IDX 3
-#define BSP_LCD_BPP 32
-#define BSP_LCD_WIDTH 800
-#define BSP_LCD_HEIGHT 480
-#define BSP_USING_VPOST_OSD
-#define BSP_USING_USBD
-#define BSP_USING_USBH
-
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_CONSOLE
-#define BOARD_USING_IP101GR
-#define BOARD_USING_NAU8822
-#define BOARD_USING_STORAGE_SDCARD
-#define BOARD_USING_STORAGE_SPIFLASH
-#define BOARD_USING_BUZZER
-#define BOARD_USING_LCM
-#define BOARD_USING_USB0_DEVICE_HOST
-#define BOARD_USING_USB1_HOST
-
-/* Board extended module drivers */
-
-
-#endif
diff --git a/bsp/nuvoton/nk-n9h30/rtconfig.py b/bsp/nuvoton/nk-n9h30/rtconfig.py
index 79a4da1d49..cdca30ea1a 100644
--- a/bsp/nuvoton/nk-n9h30/rtconfig.py
+++ b/bsp/nuvoton/nk-n9h30/rtconfig.py
@@ -85,4 +85,10 @@ elif PLATFORM == 'armcc':
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
- POST_ACTION += 'fromelf -z $TARGET\n'
\ No newline at end of file
+ POST_ACTION += 'fromelf -z $TARGET\n'
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nuvoton/nk-rtu980/.config b/bsp/nuvoton/nk-rtu980/.config
index 853e905aed..566468f589 100644
--- a/bsp/nuvoton/nk-rtu980/.config
+++ b/bsp/nuvoton/nk-rtu980/.config
@@ -974,3 +974,5 @@ CONFIG_BOARD_USING_USB0_DEVICE_HOST=y
# Board extended module drivers
#
CONFIG_BOARD_USING_IP101GR=y
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.nk-rtu980.test.utest."
diff --git a/bsp/nuvoton/nk-rtu980/Kconfig b/bsp/nuvoton/nk-rtu980/Kconfig
index 5c55e87c61..b396340d12 100644
--- a/bsp/nuvoton/nk-rtu980/Kconfig
+++ b/bsp/nuvoton/nk-rtu980/Kconfig
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/nk-rtu980/applications/mnt.c b/bsp/nuvoton/nk-rtu980/applications/mnt.c
index ecfc390243..1c834fcb3e 100644
--- a/bsp/nuvoton/nk-rtu980/applications/mnt.c
+++ b/bsp/nuvoton/nk-rtu980/applications/mnt.c
@@ -21,10 +21,12 @@
#define DBG_COLOR
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
#if defined(PKG_USING_FAL)
#include
diff --git a/bsp/nuvoton/nk-rtu980/board/Kconfig b/bsp/nuvoton/nk-rtu980/board/Kconfig
index 2682f8b89f..04cc595e7a 100644
--- a/bsp/nuvoton/nk-rtu980/board/Kconfig
+++ b/bsp/nuvoton/nk-rtu980/board/Kconfig
@@ -44,5 +44,6 @@ menu "Hardware Drivers Config"
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
endmenu
diff --git a/bsp/nuvoton/nk-rtu980/project.uvproj b/bsp/nuvoton/nk-rtu980/project.uvproj
deleted file mode 100644
index 9c0d498aed..0000000000
--- a/bsp/nuvoton/nk-rtu980/project.uvproj
+++ /dev/null
@@ -1,1774 +0,0 @@
-
-
- 1.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread
- 0x4
- ARM-ADS
-
-
- Nuvoton_ARM9_Series
- Nuvoton
-
-
-
-
- 0
-
-
-
-
-
-
-
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-
-
-
- 0
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-
- Atmel\SAM9260\
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- TARMATS9.DLL
- -p91SAM9260
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-
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- 0
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-
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-
-
-
-
-
-
-
-
- ..\libraries\nuc980\Script\NUC980xx61.ini
- Segger\JLTAgdi.dll
-
-
-
-
- 1
- 0
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- 1
- 4098
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- 0
- Segger\JLTAgdi.dll
- "" ()
-
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-
- --c99
- __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
-
- applications;.;board;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\arm926;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\hwcrypto;.;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\spi\sfud\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\nuc980\rtt_port;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\finsh;.;..\..\..\include;..\libraries\nuc980\Driver\Include;..\..\..\components\net\lwip-2.1.2\src;..\..\..\components\net\lwip-2.1.2\src\include;..\..\..\components\net\lwip-2.1.2\src\arch\include;..\..\..\components\net\lwip-2.1.2\src\include\netif;..\libraries\nu_packages\Demo;..\libraries\nuc980\UsbHostLib\inc;..\libraries\nu_packages\NuUtils\inc;..\..\..\components\libc\posix\io;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\usb\usbdevice;..\..\..\components\drivers\usb\usbhost;..\..\..\components\drivers\usb\usbhost\class;..\..\..\components\drivers\usb\usbhost\core;..\..\..\components\drivers\usb\usbhost\include;..\..\..\components\drivers\include;..\..\..\components\net\netdev\include;..\..\..\components\net\sal_socket\include;..\..\..\components\net\sal_socket\include\socket;..\..\..\components\net\sal_socket\impl;..\..\..\components\net\sal_socket\include\dfs_net;..\..\..\components\net\sal_socket\include\socket\sys_socket;..\..\..\components\utilities\utest;..\..\..\examples\utest\testcases\kernel
-
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-
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-
- Applications
-
-
- mnt.c
- 1
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-
-
-
-
- main.c
- 1
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-
-
-
-
- board
-
-
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-
-
-
-
- nu_pin_init.c
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-
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- Compiler
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-
-
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-
-
-
-
- stdlib.c
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-
-
-
-
- time.c
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-
-
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-
-
-
-
- showmem.c
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-
-
-
-
- backtrace.c
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-
-
-
-
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-
-
-
-
- context_rvds.S
- 2
- ..\..\..\libcpu\arm\arm926\context_rvds.S
-
-
-
-
- start_rvds.S
- 2
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-
-
-
-
- stack.c
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-
-
-
-
- machine.c
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-
-
-
-
- trap.c
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- ..\..\..\libcpu\arm\arm926\trap.c
-
-
-
-
- mmu.c
- 1
- ..\..\..\libcpu\arm\arm926\mmu.c
-
-
-
-
- DeviceDrivers
-
-
- can.c
- 1
- ..\..\..\components\drivers\can\can.c
-
-
-
-
- cputime.c
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- ..\..\..\components\drivers\cputime\cputime.c
-
-
-
-
- hw_symmetric.c
- 1
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-
-
-
-
- hwcrypto.c
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- ..\..\..\components\drivers\hwcrypto\hwcrypto.c
-
-
-
-
- hw_rng.c
- 1
- ..\..\..\components\drivers\hwcrypto\hw_rng.c
-
-
-
-
- hw_hash.c
- 1
- ..\..\..\components\drivers\hwcrypto\hw_hash.c
-
-
-
-
- hwtimer.c
- 1
- ..\..\..\components\drivers\hwtimer\hwtimer.c
-
-
-
-
- i2c_core.c
- 1
- ..\..\..\components\drivers\i2c\i2c_core.c
-
-
-
-
- i2c_dev.c
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- ..\..\..\components\drivers\i2c\i2c_dev.c
-
-
-
-
- i2c-bit-ops.c
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- ..\..\..\components\drivers\i2c\i2c-bit-ops.c
-
-
-
-
- adc.c
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-
-
-
-
- pin.c
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-
-
-
-
- serial.c
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-
-
-
-
- sfud.c
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-
-
-
-
- spi_core.c
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- ..\..\..\components\drivers\spi\spi_core.c
-
-
-
-
- sfud_sfdp.c
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-
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-
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-
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-
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-
-
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-
- --c99
- __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
-
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-
-
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-
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-
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-
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-
- Compiler
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-
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-
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- CPU
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
-
-
- DeviceDrivers
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-
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-
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-
-
-
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-
-
-
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-
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-
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-
-
-
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-
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-
-
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-
-
-
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-
-
-
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-
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-
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-
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-
-
-
- spi_core.c
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-
-
-
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-
-
-
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-
-
-
- qspi_core.c
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-
-
-
- spi_flash_sfud.c
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-
-
-
- pipe.c
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-
-
-
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-
-
-
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-
-
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-
-
-
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-
-
-
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-
-
-
-
- watchdog.c
- 1
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-
-
-
-
-
-
- --c99
-
-
-
-
-
-
-
-
-
- Drivers
-
-
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- 1
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-
-
-
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-
-
-
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-
-
-
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-
-
-
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-
-
-
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-
-
-
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-
-
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-
-
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-
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-
-
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-
-
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-
-
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-
-
-
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-
-
-
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-
-
-
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-
-
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-
-
-
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-
-
-
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-
-
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-
-
-
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-
-
-
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-
-
-
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-
-
-
-
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-
-
-
- Filesystem
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-
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-
-
-
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-
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-
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-
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-
-
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-
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-
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-
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- Kernel
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-
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-
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-
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-
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-
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-
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-
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-
-
-
- memheap.c
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-
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-
-
-
- Libraries
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-
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-
-
-
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-
-
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-
-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
-
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-
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- icmp.c
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-
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-
-
-
- err.c
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-
-
-
- altcp.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\altcp.c
-
-
-
-
- tcp_in.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\tcp_in.c
-
-
-
-
- dns.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\dns.c
-
-
-
-
- sys_arch.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\arch\sys_arch.c
-
-
-
-
- timeouts.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\timeouts.c
-
-
-
-
- igmp.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\ipv4\igmp.c
-
-
-
-
- udp.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\udp.c
-
-
-
-
- altcp_tcp.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\altcp_tcp.c
-
-
-
-
- pbuf.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\pbuf.c
-
-
-
-
- def.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\def.c
-
-
-
-
- api_msg.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\api\api_msg.c
-
-
-
-
- ping.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\apps\ping\ping.c
-
-
-
-
- if_api.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\api\if_api.c
-
-
-
-
- tcp.c
- 1
- ..\..\..\components\net\lwip-2.1.2\src\core\tcp.c
-
-
-
-
- nu_pkgs_demo
-
-
- usbd_cdc_vcom_echo.c
- 1
- ..\libraries\nu_packages\Demo\usbd_cdc_vcom_echo.c
-
-
-
-
- slcd_show_tick.c
- 1
- ..\libraries\nu_packages\Demo\slcd_show_tick.c
-
-
-
-
- usbd_hid_dance_mouse.c
- 1
- ..\libraries\nu_packages\Demo\usbd_hid_dance_mouse.c
-
-
-
-
- nuc980_usbhostlib
-
-
- ehci.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\ehci.c
-
-
-
-
- ehci_iso.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\ehci_iso.c
-
-
-
-
- mem_alloc.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\mem_alloc.c
-
-
-
-
- ohci.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\ohci.c
-
-
-
-
- support.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\support.c
-
-
-
-
- usb_core.c
- 1
- ..\libraries\nuc980\UsbHostLib\src\usb_core.c
-
-
-
-
- POSIX
-
-
- select.c
- 1
- ..\..\..\components\libc\posix\io\select.c
-
-
-
-
- poll.c
- 1
- ..\..\..\components\libc\posix\io\poll\poll.c
-
-
-
-
- rt_usbd
-
-
- usbdevice_core.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c
-
-
-
-
- mstorage.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\mstorage.c
-
-
-
-
- usbdevice.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c
-
-
-
-
- cdc_vcom.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c
-
-
-
-
- rt_usbh
-
-
- hub.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\hub.c
-
-
-
-
- usbhost.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost.c
-
-
-
-
- usbhost_core.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c
-
-
-
-
- udisk.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\udisk.c
-
-
-
-
- mass.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\mass.c
-
-
-
-
- driver.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\driver.c
-
-
-
-
- SAL
-
-
- netdev.c
- 1
- ..\..\..\components\net\netdev\src\netdev.c
-
-
-
-
- netdev_ipaddr.c
- 1
- ..\..\..\components\net\netdev\src\netdev_ipaddr.c
-
-
-
-
- net_netdb.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_netdb.c
-
-
-
-
- af_inet_lwip.c
- 1
- ..\..\..\components\net\sal_socket\impl\af_inet_lwip.c
-
-
-
-
- sal_socket.c
- 1
- ..\..\..\components\net\sal_socket\src\sal_socket.c
-
-
-
-
- net_sockets.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_sockets.c
-
-
-
-
- dfs_net.c
- 1
- ..\..\..\components\net\sal_socket\dfs_net\dfs_net.c
-
-
-
-
- UTest
-
-
- utest.c
- 1
- ..\..\..\components\utilities\utest\utest.c
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuvoton/nk-rtu980/rtconfig.h b/bsp/nuvoton/nk-rtu980/rtconfig.h
deleted file mode 100644
index 6da5ab3233..0000000000
--- a/bsp/nuvoton/nk-rtu980/rtconfig.h
+++ /dev/null
@@ -1,431 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 16
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 2048
-
-/* kservice optimization */
-
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-#define RT_USING_SIGNALS
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_MEMHEAP
-#define RT_MEMHEAP_FAST_MODE
-#define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_MEMTRACE
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-#define ARCH_ARM
-#define ARCH_ARM_ARM9
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define RT_USING_MSH
-#define FINSH_USING_MSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_CMD_SIZE 80
-#define MSH_USING_BUILT_IN_COMMANDS
-#define FINSH_USING_DESCRIPTION
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 16
-#define DFS_FILESYSTEM_TYPES_MAX 16
-#define DFS_FD_MAX 64
-#define RT_USING_DFS_MNTTABLE
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_3
-#define RT_DFS_ELM_USE_LFN 3
-#define RT_DFS_ELM_LFN_UNICODE_0
-#define RT_DFS_ELM_LFN_UNICODE 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 8
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
-#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
-#define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 2048
-#define RT_USING_CAN
-#define RT_CAN_USING_HDR
-#define RT_USING_HWTIMER
-#define RT_USING_CPUTIME
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_SPI
-#define RT_USING_QSPI
-#define RT_USING_SFUD
-#define RT_SFUD_USING_SFDP
-#define RT_SFUD_USING_FLASH_INFO_TABLE
-#define RT_SFUD_USING_QSPI
-#define RT_SFUD_SPI_MAX_HZ 50000000
-#define RT_USING_WDT
-#define RT_USING_HWCRYPTO
-#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
-#define RT_HWCRYPTO_IV_MAX_SIZE 16
-#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
-#define RT_HWCRYPTO_USING_AES
-#define RT_HWCRYPTO_USING_AES_ECB
-#define RT_HWCRYPTO_USING_AES_CBC
-#define RT_HWCRYPTO_USING_AES_CFB
-#define RT_HWCRYPTO_USING_AES_CTR
-#define RT_HWCRYPTO_USING_AES_OFB
-#define RT_HWCRYPTO_USING_SHA1
-#define RT_HWCRYPTO_USING_SHA2
-#define RT_HWCRYPTO_USING_SHA2_224
-#define RT_HWCRYPTO_USING_SHA2_256
-#define RT_HWCRYPTO_USING_SHA2_384
-#define RT_HWCRYPTO_USING_SHA2_512
-#define RT_HWCRYPTO_USING_RNG
-
-/* Using USB */
-
-#define RT_USING_USB
-#define RT_USING_USB_HOST
-#define RT_USBH_MSTORAGE
-#define UDISK_MOUNTPOINT "/mnt/udisk"
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define RT_USB_DEVICE_COMPOSITE
-#define RT_USB_DEVICE_CDC
-#define RT_USB_DEVICE_NONE
-#define RT_USB_DEVICE_MSTORAGE
-#define RT_VCOM_TASK_STK_SIZE 2048
-#define RT_CDC_RX_BUFSIZE 128
-#define RT_VCOM_SERNO "32021919830108"
-#define RT_VCOM_SER_LEN 14
-#define RT_VCOM_TX_TIMEOUT 1000
-#define RT_USB_MSTORAGE_DISK_NAME "ramdisk1"
-
-/* POSIX layer and C standard library */
-
-#define RT_LIBC_DEFAULT_TIMEZONE 8
-
-/* POSIX (Portable Operating System Interface) layer */
-
-#define RT_USING_POSIX_FS
-#define RT_USING_POSIX_DEVIO
-#define RT_USING_POSIX_POLL
-#define RT_USING_POSIX_SELECT
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-#define RT_USING_SAL
-
-/* protocol stack implement */
-
-#define SAL_USING_LWIP
-#define SAL_USING_POSIX
-
-/* Network interface device */
-
-#define RT_USING_NETDEV
-#define NETDEV_USING_IFCONFIG
-#define NETDEV_USING_PING
-#define NETDEV_USING_NETSTAT
-#define NETDEV_USING_AUTO_DEFAULT
-#define NETDEV_IPV4 1
-#define NETDEV_IPV6 0
-
-/* light weight TCP/IP stack */
-
-#define RT_USING_LWIP
-#define RT_USING_LWIP212
-#define RT_LWIP_MEM_ALIGNMENT 4
-#define RT_LWIP_IGMP
-#define RT_LWIP_ICMP
-#define RT_LWIP_DNS
-#define RT_LWIP_DHCP
-#define IP_SOF_BROADCAST 1
-#define IP_SOF_BROADCAST_RECV 1
-
-/* Static IPv4 Address */
-
-#define RT_LWIP_IPADDR "192.168.31.55"
-#define RT_LWIP_GWADDR "192.168.31.1"
-#define RT_LWIP_MSKADDR "255.255.255.0"
-#define RT_LWIP_UDP
-#define RT_LWIP_TCP
-#define RT_LWIP_RAW
-#define RT_MEMP_NUM_NETCONN 16
-#define RT_LWIP_PBUF_NUM 256
-#define RT_LWIP_RAW_PCB_NUM 16
-#define RT_LWIP_UDP_PCB_NUM 16
-#define RT_LWIP_TCP_PCB_NUM 16
-#define RT_LWIP_TCP_SEG_NUM 64
-#define RT_LWIP_TCP_SND_BUF 16384
-#define RT_LWIP_TCP_WND 65535
-#define RT_LWIP_TCPTHREAD_PRIORITY 10
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 256
-#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
-#define RT_LWIP_ETHTHREAD_PRIORITY 12
-#define RT_LWIP_ETHTHREAD_STACKSIZE 4096
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 256
-#define RT_LWIP_REASSEMBLY_FRAG
-#define LWIP_NETIF_STATUS_CALLBACK 1
-#define LWIP_NETIF_LINK_CALLBACK 1
-#define SO_REUSE 1
-#define LWIP_SO_RCVTIMEO 1
-#define LWIP_SO_SNDTIMEO 1
-#define LWIP_SO_RCVBUF 1
-#define LWIP_SO_LINGER 0
-#define RT_LWIP_NETIF_LOOPBACK
-#define LWIP_NETIF_LOOPBACK 1
-#define RT_LWIP_STATS
-#define RT_LWIP_USING_PING
-
-/* AT commands */
-
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
-
-/* RT-Thread Utestcases */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-#define PKG_USING_NETUTILS
-#define PKG_NETUTILS_TFTP
-#define PKG_NETUTILS_IPERF
-#define PKG_NETUTILS_NTP
-#define NTP_USING_AUTO_SYNC
-#define NTP_AUTO_SYNC_FIRST_DELAY 30
-#define NTP_AUTO_SYNC_PERIOD 3600
-#define NETUTILS_NTP_HOSTNAME "0.tw.pool.ntp.org"
-#define NETUTILS_NTP_HOSTNAME2 "1.tw.pool.ntp.org"
-#define NETUTILS_NTP_HOSTNAME3 "2.tw.pool.ntp.org"
-#define PKG_USING_NETUTILS_V131
-#define PKG_NETUTILS_VER_NUM 0x10301
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-/* LVGL: powerful and easy-to-use embedded GUI library */
-
-
-/* u8g2: a monochrome graphic library */
-
-
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
-/* acceleration: Assembly language or algorithmic acceleration packages */
-
-
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
-/* Micrium: Micrium software products porting for RT-Thread */
-
-#define PKG_USING_FAL
-#define FAL_DEBUG_CONFIG
-#define FAL_DEBUG 1
-#define FAL_PART_HAS_TABLE_CFG
-#define FAL_USING_SFUD_PORT
-#define FAL_USING_NOR_FLASH_DEV_NAME "norflash0"
-#define PKG_USING_FAL_LATEST_VERSION
-#define PKG_FAL_VER_NUM 0x99999
-#define PKG_USING_RAMDISK
-#define PKG_USING_RAMDISK_LATEST_VERSION
-
-/* peripheral libraries and drivers */
-
-
-/* AI packages */
-
-
-/* miscellaneous packages */
-
-/* samples: kernel and components samples */
-
-
-/* entertainment: terminal games and other interesting software packages */
-
-#define PKG_USING_OPTPARSE
-#define PKG_USING_OPTPARSE_LATEST_VERSION
-
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_DEMO
-
-/* Hardware Drivers Config */
-
-/* On-chip Peripheral Drivers */
-
-#define SOC_SERIES_NUC980
-#define BSP_USE_STDDRIVER_SOURCE
-#define BSP_USING_MMU
-#define BSP_USING_PDMA
-#define NU_PDMA_MEMFUN_ACTOR_MAX 2
-#define BSP_USING_GPIO
-#define BSP_USING_EMAC
-#define BSP_USING_EMAC1
-#define NU_EMAC_PDMA_MEMCOPY
-#define NU_EMAC_PDMA_MEMCOPY_THRESHOLD 128
-#define BSP_USING_ADC
-#define BSP_USING_TMR
-#define BSP_USING_TIMER
-#define BSP_USING_TMR0
-#define BSP_USING_TIMER0
-#define BSP_USING_TMR1
-#define BSP_USING_TIMER1
-#define BSP_USING_TMR2
-#define BSP_USING_TIMER2
-#define BSP_USING_TMR3
-#define BSP_USING_TIMER3
-#define BSP_USING_TMR4
-#define BSP_USING_TIMER4
-#define BSP_USING_UART
-#define BSP_USING_UART0
-#define BSP_USING_UART4
-#define BSP_USING_UART4_TX_DMA
-#define BSP_USING_UART4_RX_DMA
-#define BSP_USING_UART8
-#define BSP_USING_UART8_TX_DMA
-#define BSP_USING_UART8_RX_DMA
-#define BSP_USING_I2C
-#define BSP_USING_I2C1
-#define BSP_USING_CAN
-#define BSP_USING_CAN3
-#define BSP_USING_SPI
-#define BSP_USING_SPI_PDMA
-#define BSP_USING_SPI0
-#define BSP_USING_SPI0_PDMA
-#define BSP_USING_SPI1_NONE
-#define BSP_USING_QSPI
-#define BSP_USING_QSPI_PDMA
-#define BSP_USING_QSPI0
-#define BSP_USING_QSPI0_PDMA
-#define BSP_USING_CRYPTO
-#define BSP_USING_WDT
-#define BSP_USING_USBD
-#define BSP_USING_USBH
-
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_CONSOLE
-#define BOARD_USING_UART8_RS485
-#define BOARD_USING_STORAGE_SPIFLASH
-#define BOARD_USING_USB0_DEVICE_HOST
-
-/* Board extended module drivers */
-
-#define BOARD_USING_IP101GR
-
-#endif
diff --git a/bsp/nuvoton/nk-rtu980/rtconfig.py b/bsp/nuvoton/nk-rtu980/rtconfig.py
index c246b656ad..07f75ed3e0 100644
--- a/bsp/nuvoton/nk-rtu980/rtconfig.py
+++ b/bsp/nuvoton/nk-rtu980/rtconfig.py
@@ -85,4 +85,10 @@ elif PLATFORM == 'armcc':
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
- POST_ACTION += 'fromelf -z $TARGET\n'
\ No newline at end of file
+ POST_ACTION += 'fromelf -z $TARGET\n'
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nuvoton/numaker-iot-m487/.config b/bsp/nuvoton/numaker-iot-m487/.config
index c10d9235f9..35a86cd719 100644
--- a/bsp/nuvoton/numaker-iot-m487/.config
+++ b/bsp/nuvoton/numaker-iot-m487/.config
@@ -277,7 +277,6 @@ CONFIG_RT_USB_DEVICE_HID_MOUSE=y
#
# POSIX layer and C standard library
#
-# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
@@ -293,7 +292,9 @@ CONFIG_RT_USING_POSIX_SELECT=y
# CONFIG_RT_USING_POSIX_MMAN is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
@@ -427,7 +428,9 @@ CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device"
# CONFIG_AT_DEVICE_USING_ESP32 is not set
CONFIG_AT_DEVICE_USING_ESP8266=y
CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y
+CONFIG_AT_DEVICE_ESP8266_SOCKET=y
# CONFIG_AT_DEVICE_ESP8266_SAMPLE is not set
+# CONFIG_AT_DEVICE_ESP8266_SAMPLE_BSP_TAKEOVER is not set
# CONFIG_AT_DEVICE_USING_RW007 is not set
# CONFIG_AT_DEVICE_USING_SIM800C is not set
# CONFIG_AT_DEVICE_USING_SIM76XX is not set
@@ -561,6 +564,7 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -571,7 +575,6 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -622,6 +625,7 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -747,6 +751,7 @@ CONFIG_PKG_FAL_VER_NUM=0x99999
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -834,19 +839,8 @@ CONFIG_PKG_FAL_VER_NUM=0x99999
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
-
-#
-# Nuvoton Packages Config
-#
-CONFIG_NU_PKG_USING_UTILS=y
-CONFIG_NU_PKG_USING_DEMO=y
-CONFIG_NU_PKG_USING_BMX055=y
-# CONFIG_NU_PKG_USING_MAX31875 is not set
-CONFIG_NU_PKG_USING_NAU88L25=y
-# CONFIG_NU_PKG_USING_NAU8822 is not set
-# CONFIG_NU_PKG_USING_DA9062 is not set
-# CONFIG_NU_PKG_USING_ILI9341 is not set
-# CONFIG_NU_PKG_USING_SPINAND is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
@@ -962,6 +956,7 @@ CONFIG_BOARD_USING_BMX055=y
CONFIG_BOARD_USING_NAU88L25=y
CONFIG_BOARD_USING_STORAGE_SDCARD=y
CONFIG_BOARD_USING_STORAGE_SPIFLASH=y
+CONFIG_BOARD_USING_USB_D_H=y
# CONFIG_BOARD_USING_HSUSBD is not set
# CONFIG_BOARD_USING_HSUSBD_USBH is not set
# CONFIG_BOARD_USING_HSUSBH is not set
@@ -973,3 +968,18 @@ CONFIG_BOARD_USING_HSUSBH_USBD=y
#
# CONFIG_BOARD_USING_MAX31875 is not set
# CONFIG_BOARD_USING_LCD_ILI9341 is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+CONFIG_NU_PKG_USING_BMX055=y
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+CONFIG_NU_PKG_USING_NAU88L25=y
+# CONFIG_NU_PKG_USING_NAU8822 is not set
+# CONFIG_NU_PKG_USING_DA9062 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-iot-m487.test.utest."
diff --git a/bsp/nuvoton/numaker-iot-m487/Kconfig b/bsp/nuvoton/numaker-iot-m487/Kconfig
index 5c55e87c61..b396340d12 100644
--- a/bsp/nuvoton/numaker-iot-m487/Kconfig
+++ b/bsp/nuvoton/numaker-iot-m487/Kconfig
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/numaker-iot-m487/applications/mnt.c b/bsp/nuvoton/numaker-iot-m487/applications/mnt.c
index d7e657d852..9abcd5de26 100644
--- a/bsp/nuvoton/numaker-iot-m487/applications/mnt.c
+++ b/bsp/nuvoton/numaker-iot-m487/applications/mnt.c
@@ -12,10 +12,12 @@
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
#if defined(PKG_USING_FAL)
#include
diff --git a/bsp/nuvoton/numaker-iot-m487/board/Kconfig b/bsp/nuvoton/numaker-iot-m487/board/Kconfig
index 7b2fb2683a..3e3d614599 100644
--- a/bsp/nuvoton/numaker-iot-m487/board/Kconfig
+++ b/bsp/nuvoton/numaker-iot-m487/board/Kconfig
@@ -54,42 +54,48 @@ menu "Hardware Drivers Config"
select BSP_USING_QSPI0
default y
- choice
- prompt "Select FS/HS USB Ports"
-
- config BOARD_USING_HSUSBD
- select BSP_USING_HSUSBD
- bool "Enable HSUSBD(over USB2.0)"
- help
- Choose this option if you need HSUSBD function mode.
+ config BOARD_USING_USB_D_H
+ bool "Enable USB Device or Host function"
+ help
+ Choose this option if you need USB function.
- config BOARD_USING_HSUSBD_USBH
- select BSP_USING_USBH
- select BSP_USING_HSUSBD
- bool "Enable HSUSBD(over USB2.0) and USBH(over USB1.1)"
- help
- Choose this option if you need HSUSBD and USBH function mode at the same time.
+ if BOARD_USING_USB_D_H
+ choice
+ prompt "Select FS/HS USB Ports"
- config BOARD_USING_HSUSBH
- select BSP_USING_HSUSBH
- bool "Enable HSUSBH(over USB2.0)"
- help
- Choose this option if you need HSUSBH function mode.
+ config BOARD_USING_HSUSBD
+ select BSP_USING_HSUSBD
+ bool "Enable HSUSBD(over USB2.0)"
+ help
+ Choose this option if you need HSUSBD function mode.
- config BOARD_USING_HSUSBH_USBD
- select BSP_USING_HSUSBH
- select BSP_USING_USBD
- bool "Enable HSUSBH(over USB2.0) and USBD(over USB1.1)"
- help
- Choose this option if you need HSUSBH and USBD function mode at the same time.
+ config BOARD_USING_HSUSBD_USBH
+ select BSP_USING_USBH
+ select BSP_USING_HSUSBD
+ bool "Enable HSUSBD(over USB2.0) and USBH(over USB1.1)"
+ help
+ Choose this option if you need HSUSBD and USBH function mode at the same time.
- config BOARD_USING_HSOTG
- select BSP_USING_HSOTG
- bool "Enable HSOTG(over USB2.0)"
- help
- Choose this option if you need HSOTG function mode.
+ config BOARD_USING_HSUSBH
+ select BSP_USING_HSUSBH
+ bool "Enable HSUSBH(over USB2.0)"
+ help
+ Choose this option if you need HSUSBH function mode.
- endchoice
+ config BOARD_USING_HSUSBH_USBD
+ select BSP_USING_HSUSBH
+ select BSP_USING_USBD
+ bool "Enable HSUSBH(over USB2.0) and USBD(over USB1.1)"
+ help
+ Choose this option if you need HSUSBH and USBD function mode at the same time.
+
+ config BOARD_USING_HSOTG
+ select BSP_USING_HSOTG
+ bool "Enable HSOTG(over USB2.0)"
+ help
+ Choose this option if you need HSOTG function mode.
+ endchoice
+ endif
endmenu
@@ -129,5 +135,6 @@ menu "Hardware Drivers Config"
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
endmenu
diff --git a/bsp/nuvoton/numaker-iot-m487/project.uvproj b/bsp/nuvoton/numaker-iot-m487/project.uvproj
deleted file mode 100644
index b26994de86..0000000000
--- a/bsp/nuvoton/numaker-iot-m487/project.uvproj
+++ /dev/null
@@ -1,1814 +0,0 @@
-
-
- 1.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread-m480
- 0x4
- ARM-ADS
-
-
- M487JIDAE
- Nuvoton
- IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2
-
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-
- --c99
- __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
-
- applications;.;..\..\..\components\net\at\include;..\..\..\components\net\at\at_socket;..\libraries\m480\CMSIS\Include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\audio;..\..\..\components\drivers\include;..\..\..\components\drivers\hwcrypto;.;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\spi\sfud\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\NuClockConfig;board\NuPinConfig;..\libraries\m480\Device\Nuvoton\M480\Include;..\libraries\m480\rtt_port;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\finsh;.;..\..\..\include;..\libraries\m480\StdDriver\inc;..\libraries\m480\USBHostLib\inc;..\libraries\nu_packages\BMX055;..\libraries\nu_packages\BMX055\libraries\BMA2x2_driver;..\libraries\nu_packages\BMX055\libraries\BMG160_driver;..\libraries\nu_packages\BMX055\libraries\BMM050_driver;..\libraries\nu_packages\Demo;..\libraries\nu_packages\AudioCodec;..\libraries\nu_packages\NuUtils\inc;..\..\..\components\libc\posix\io;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\usb\usbdevice;..\..\..\components\drivers\usb\usbhost;..\..\..\components\drivers\usb\usbhost\class;..\..\..\components\drivers\usb\usbhost\core;..\..\..\components\drivers\usb\usbhost\include;..\..\..\components\drivers\include;..\..\..\components\net\netdev\include;..\..\..\components\net\sal_socket\include;..\..\..\components\net\sal_socket\include\socket;..\..\..\components\net\sal_socket\impl;..\..\..\components\net\sal_socket\include\dfs_net;..\..\..\components\net\sal_socket\include\socket\sys_socket;..\..\..\components\drivers\sensors;..\..\..\components\drivers\include;..\..\..\components\utilities\utest;..\..\..\examples\utest\testcases\kernel
-
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- 1
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- --c99
-
-
-
-
-
-
-
-
-
- Drivers
-
-
- nutool_pincfg.c
- 1
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-
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-
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- 1
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-
-
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-
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-
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-
-
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-
-
-
-
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- 1
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-
-
-
-
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- 1
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-
-
-
-
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- 1
- ..\libraries\m480\rtt_port\drv_qspi.c
-
-
-
-
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- 1
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-
-
-
-
- drv_epwm.c
- 1
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-
-
-
-
- drv_wdt.c
- 1
- ..\libraries\m480\rtt_port\drv_wdt.c
-
-
-
-
- drv_clk.c
- 1
- ..\libraries\m480\rtt_port\drv_clk.c
-
-
-
-
- drv_timer.c
- 1
- ..\libraries\m480\rtt_port\drv_timer.c
-
-
-
-
- drv_uspi.c
- 1
- ..\libraries\m480\rtt_port\drv_uspi.c
-
-
-
-
- drv_emac.c
- 1
- ..\libraries\m480\rtt_port\drv_emac.c
-
-
-
-
- drv_uart.c
- 1
- ..\libraries\m480\rtt_port\drv_uart.c
-
-
-
-
- drv_timer_capture.c
- 1
- ..\libraries\m480\rtt_port\drv_timer_capture.c
-
-
-
-
- drv_crypto.c
- 1
- ..\libraries\m480\rtt_port\drv_crypto.c
-
-
-
-
- drv_qei.c
- 1
- ..\libraries\m480\rtt_port\drv_qei.c
-
-
-
-
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- 1
- ..\libraries\m480\rtt_port\drv_usbhost.c
-
-
-
-
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- 1
- ..\libraries\m480\rtt_port\drv_hsusbd.c
-
-
-
-
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- 1
- ..\libraries\m480\rtt_port\drv_gpio.c
-
-
-
-
- drv_ecap.c
- 1
- ..\libraries\m480\rtt_port\drv_ecap.c
-
-
-
-
- drv_crc.c
- 1
- ..\libraries\m480\rtt_port\drv_crc.c
-
-
-
-
- drv_bpwm.c
- 1
- ..\libraries\m480\rtt_port\drv_bpwm.c
-
-
-
-
- drv_ui2c.c
- 1
- ..\libraries\m480\rtt_port\drv_ui2c.c
-
-
-
-
- drv_scuart.c
- 1
- ..\libraries\m480\rtt_port\drv_scuart.c
-
-
-
-
- drv_spi.c
- 1
- ..\libraries\m480\rtt_port\drv_spi.c
-
-
-
-
- drv_spii2s.c
- 1
- ..\libraries\m480\rtt_port\drv_spii2s.c
-
-
-
-
- drv_i2c.c
- 1
- ..\libraries\m480\rtt_port\drv_i2c.c
-
-
-
-
- drv_i2s.c
- 1
- ..\libraries\m480\rtt_port\drv_i2s.c
-
-
-
-
- drv_sdh.c
- 1
- ..\libraries\m480\rtt_port\drv_sdh.c
-
-
-
-
- drv_hsotg.c
- 1
- ..\libraries\m480\rtt_port\drv_hsotg.c
-
-
-
-
- drv_tpwm.c
- 1
- ..\libraries\m480\rtt_port\drv_tpwm.c
-
-
-
-
- drv_epwm_capture.c
- 1
- ..\libraries\m480\rtt_port\drv_epwm_capture.c
-
-
-
-
- drv_common.c
- 1
- ..\libraries\m480\rtt_port\drv_common.c
-
-
-
-
- drv_fmc.c
- 1
- ..\libraries\m480\rtt_port\drv_fmc.c
-
-
-
-
- drv_softi2c.c
- 1
- ..\libraries\m480\rtt_port\drv_softi2c.c
-
-
-
-
- drv_eadc.c
- 1
- ..\libraries\m480\rtt_port\drv_eadc.c
-
-
-
-
- drv_can.c
- 1
- ..\libraries\m480\rtt_port\drv_can.c
-
-
-
-
- Filesystem
-
-
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- 1
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-
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-
-
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-
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-
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- 1
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- Libraries
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-
-
- nu_sys.c
- 1
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-
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-
-
- nu_crc.c
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-
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-
-
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-
-
-
-
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-
-
-
-
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- 1
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-
-
-
-
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- 1
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-
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-
-
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-
-
-
-
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-
-
-
-
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-
-
-
-
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-
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-
-
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-
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-
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-
-
-
-
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- 1
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-
-
-
-
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- 1
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-
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-
-
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-
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-
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-
-
-
-
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-
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-
-
- net_netdb.c
- 1
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-
-
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- Sensors
-
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-
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diff --git a/bsp/nuvoton/numaker-iot-m487/project.uvprojx b/bsp/nuvoton/numaker-iot-m487/project.uvprojx
deleted file mode 100644
index bf9144d3c4..0000000000
--- a/bsp/nuvoton/numaker-iot-m487/project.uvprojx
+++ /dev/null
@@ -1,1809 +0,0 @@
-
-
- 2.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread-m480
- 0x4
- ARM-ADS
- 0
-
-
- M487JIDAE
- Nuvoton
- Nuvoton.NuMicro_DFP.1.3.5
- http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
- IRAM(0x20000000,0x28000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)
-
-
- UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M481_AP_512 -FS00 -FL080000 -FP0($$Device:M487JIDAE$Flash\M481_AP_512.FLM))
- 0
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-
- SARMCM3.DLL
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-
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-
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-
-
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- 1
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- 16
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-
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-
- 1
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- 4103
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- 1
- NULink\Nu_Link.dll
- "" ()
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- "Cortex-M4"
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-
- --c99
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-
- usb_core.c
- 1
- ..\libraries\m480\USBHostLib\src\usb_core.c
-
-
-
-
- nu_pkgs_bmx055
-
-
- bmg160.c
- 1
- ..\libraries\nu_packages\BMX055\libraries\BMG160_driver\bmg160.c
-
-
-
-
- bma2x2.c
- 1
- ..\libraries\nu_packages\BMX055\libraries\BMA2x2_driver\bma2x2.c
-
-
-
-
- sensor_bmx055.c
- 1
- ..\libraries\nu_packages\BMX055\sensor_bmx055.c
-
-
-
-
- bmm050.c
- 1
- ..\libraries\nu_packages\BMX055\libraries\BMM050_driver\bmm050.c
-
-
-
-
- nu_pkgs_demo
-
-
- usbd_cdc_vcom_echo.c
- 1
- ..\libraries\nu_packages\Demo\usbd_cdc_vcom_echo.c
-
-
-
-
- slcd_show_tick.c
- 1
- ..\libraries\nu_packages\Demo\slcd_show_tick.c
-
-
-
-
- usbd_hid_dance_mouse.c
- 1
- ..\libraries\nu_packages\Demo\usbd_hid_dance_mouse.c
-
-
-
-
- nu_pkgs_nau88l25
-
-
- audio_test.c
- 1
- ..\libraries\nu_packages\AudioCodec\audio_test.c
-
-
-
-
- acodec_nau88l25.c
- 1
- ..\libraries\nu_packages\AudioCodec\acodec_nau88l25.c
-
-
-
-
- POSIX
-
-
- select.c
- 1
- ..\..\..\components\libc\posix\io\select.c
-
-
-
-
- poll.c
- 1
- ..\..\..\components\libc\posix\io\poll\poll.c
-
-
-
-
- rt_usbd
-
-
- usbdevice_core.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c
-
-
-
-
- usbdevice.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c
-
-
-
-
- hid.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\hid.c
-
-
-
-
- rt_usbh
-
-
- mass.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\mass.c
-
-
-
-
- hub.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\hub.c
-
-
-
-
- usbhost.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost.c
-
-
-
-
- usbhost_core.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c
-
-
-
-
- udisk.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\udisk.c
-
-
-
-
- driver.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\driver.c
-
-
-
-
- SAL
-
-
- netdev.c
- 1
- ..\..\..\components\net\netdev\src\netdev.c
-
-
-
-
- netdev_ipaddr.c
- 1
- ..\..\..\components\net\netdev\src\netdev_ipaddr.c
-
-
-
-
- dfs_net.c
- 1
- ..\..\..\components\net\sal_socket\dfs_net\dfs_net.c
-
-
-
-
- net_sockets.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_sockets.c
-
-
-
-
- sal_socket.c
- 1
- ..\..\..\components\net\sal_socket\src\sal_socket.c
-
-
-
-
- af_inet_at.c
- 1
- ..\..\..\components\net\sal_socket\impl\af_inet_at.c
-
-
-
-
- net_netdb.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_netdb.c
-
-
-
-
- Sensors
-
-
- sensor_cmd.c
- 1
- ..\..\..\components\drivers\sensors\sensor_cmd.c
-
-
-
-
- sensor.c
- 1
- ..\..\..\components\drivers\sensors\sensor.c
-
-
-
-
- UTest
-
-
- utest.c
- 1
- ..\..\..\components\utilities\utest\utest.c
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuvoton/numaker-iot-m487/rtconfig.h b/bsp/nuvoton/numaker-iot-m487/rtconfig.h
deleted file mode 100644
index 670d11e494..0000000000
--- a/bsp/nuvoton/numaker-iot-m487/rtconfig.h
+++ /dev/null
@@ -1,400 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 8
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 1024
-
-/* kservice optimization */
-
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-#define RT_USING_SIGNALS
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-#define ARCH_ARM
-#define RT_USING_CPU_FFS
-#define ARCH_ARM_CORTEX_M
-#define ARCH_ARM_CORTEX_M4
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define RT_USING_MSH
-#define FINSH_USING_MSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 2048
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_CMD_SIZE 80
-#define MSH_USING_BUILT_IN_COMMANDS
-#define FINSH_USING_DESCRIPTION
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 8
-#define DFS_FILESYSTEM_TYPES_MAX 4
-#define DFS_FD_MAX 32
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_3
-#define RT_DFS_ELM_USE_LFN 3
-#define RT_DFS_ELM_LFN_UNICODE_0
-#define RT_DFS_ELM_LFN_UNICODE 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 8
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
-#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
-#define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 2048
-#define RT_USING_CAN
-#define RT_USING_HWTIMER
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_PM
-#define PM_TICKLESS_THRESHOLD_TIME 2
-#define RT_USING_RTC
-#define RT_USING_SPI
-#define RT_USING_QSPI
-#define RT_USING_SFUD
-#define RT_SFUD_USING_SFDP
-#define RT_SFUD_USING_FLASH_INFO_TABLE
-#define RT_SFUD_SPI_MAX_HZ 50000000
-#define RT_USING_WDT
-#define RT_USING_AUDIO
-#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
-#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
-#define RT_AUDIO_RECORD_PIPE_SIZE 2048
-#define RT_USING_SENSOR
-#define RT_USING_SENSOR_CMD
-#define RT_USING_HWCRYPTO
-#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
-#define RT_HWCRYPTO_IV_MAX_SIZE 16
-#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
-#define RT_HWCRYPTO_USING_AES
-#define RT_HWCRYPTO_USING_AES_ECB
-#define RT_HWCRYPTO_USING_AES_CBC
-#define RT_HWCRYPTO_USING_AES_CFB
-#define RT_HWCRYPTO_USING_AES_CTR
-#define RT_HWCRYPTO_USING_AES_OFB
-#define RT_HWCRYPTO_USING_DES
-#define RT_HWCRYPTO_USING_DES_ECB
-#define RT_HWCRYPTO_USING_DES_CBC
-#define RT_HWCRYPTO_USING_3DES
-#define RT_HWCRYPTO_USING_3DES_ECB
-#define RT_HWCRYPTO_USING_3DES_CBC
-#define RT_HWCRYPTO_USING_SHA1
-#define RT_HWCRYPTO_USING_SHA2
-#define RT_HWCRYPTO_USING_SHA2_224
-#define RT_HWCRYPTO_USING_SHA2_256
-#define RT_HWCRYPTO_USING_SHA2_384
-#define RT_HWCRYPTO_USING_SHA2_512
-#define RT_HWCRYPTO_USING_RNG
-#define RT_HWCRYPTO_USING_CRC
-#define RT_HWCRYPTO_USING_CRC_07
-#define RT_HWCRYPTO_USING_CRC_8005
-#define RT_HWCRYPTO_USING_CRC_1021
-#define RT_HWCRYPTO_USING_CRC_04C11DB7
-
-/* Using USB */
-
-#define RT_USING_USB
-#define RT_USING_USB_HOST
-#define RT_USBH_MSTORAGE
-#define UDISK_MOUNTPOINT "/mnt/udisk/"
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define _RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID_MOUSE
-
-/* POSIX layer and C standard library */
-
-#define RT_LIBC_DEFAULT_TIMEZONE 8
-
-/* POSIX (Portable Operating System Interface) layer */
-
-#define RT_USING_POSIX_FS
-#define RT_USING_POSIX_DEVIO
-#define RT_USING_POSIX_POLL
-#define RT_USING_POSIX_SELECT
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-#define RT_USING_SAL
-#define SAL_INTERNET_CHECK
-
-/* protocol stack implement */
-
-#define SAL_USING_AT
-#define SAL_USING_POSIX
-
-/* Network interface device */
-
-#define RT_USING_NETDEV
-#define NETDEV_USING_IFCONFIG
-#define NETDEV_USING_PING
-#define NETDEV_USING_NETSTAT
-#define NETDEV_USING_AUTO_DEFAULT
-#define NETDEV_IPV4 1
-#define NETDEV_IPV6 0
-
-/* light weight TCP/IP stack */
-
-
-/* AT commands */
-
-#define RT_USING_AT
-#define AT_USING_CLIENT
-#define AT_CLIENT_NUM_MAX 1
-#define AT_USING_SOCKET
-#define AT_USING_CLI
-#define AT_CMD_MAX_LEN 512
-#define AT_SW_VERSION_NUM 0x10301
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
-
-/* RT-Thread Utestcases */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-#define PKG_USING_AT_DEVICE
-#define AT_DEVICE_USING_ESP8266
-#define AT_DEVICE_ESP8266_INIT_ASYN
-#define PKG_USING_AT_DEVICE_LATEST_VERSION
-#define PKG_AT_DEVICE_VER_NUM 0x99999
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-/* LVGL: powerful and easy-to-use embedded GUI library */
-
-
-/* u8g2: a monochrome graphic library */
-
-
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
-/* acceleration: Assembly language or algorithmic acceleration packages */
-
-
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
-/* Micrium: Micrium software products porting for RT-Thread */
-
-#define PKG_USING_FAL
-#define FAL_DEBUG_CONFIG
-#define FAL_DEBUG 1
-#define FAL_PART_HAS_TABLE_CFG
-#define PKG_USING_FAL_LATEST_VERSION
-#define PKG_FAL_VER_NUM 0x99999
-
-/* peripheral libraries and drivers */
-
-
-/* AI packages */
-
-
-/* miscellaneous packages */
-
-/* samples: kernel and components samples */
-
-
-/* entertainment: terminal games and other interesting software packages */
-
-
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_DEMO
-#define NU_PKG_USING_BMX055
-#define NU_PKG_USING_NAU88L25
-
-/* Hardware Drivers Config */
-
-/* On-chip Peripheral Drivers */
-
-#define SOC_SERIES_M480
-#define BSP_USE_STDDRIVER_SOURCE
-#define BSP_USING_PDMA
-#define NU_PDMA_MEMFUN_ACTOR_MAX 2
-#define NU_PDMA_SGTBL_POOL_SIZE 16
-#define BSP_USING_FMC
-#define BSP_USING_GPIO
-#define BSP_USING_CLK
-#define NU_CLK_INVOKE_WKTMR
-#define BSP_USING_RTC
-#define NU_RTC_SUPPORT_MSH_CMD
-#define BSP_USING_TMR
-#define BSP_USING_UART
-#define BSP_USING_UART0
-#define BSP_USING_UART1
-#define BSP_USING_UART1_TX_DMA
-#define BSP_USING_UART1_RX_DMA
-#define BSP_USING_UART2
-#define BSP_USING_UART2_TX_DMA
-#define BSP_USING_UART2_RX_DMA
-#define BSP_USING_I2C
-#define BSP_USING_I2C0
-#define BSP_USING_I2C1
-#define BSP_USING_I2C2
-#define BSP_USING_USCI
-#define BSP_USING_UUART
-#define BSP_USING_USCI0
-#define BSP_USING_UUART0
-#define BSP_USING_UUART0_TX_DMA
-#define BSP_USING_UUART0_RX_DMA
-#define BSP_USING_SDH
-#define BSP_USING_SDH0
-#define NU_SDH_USING_PDMA
-#define NU_SDH_HOTPLUG
-#define BSP_USING_SPI
-#define BSP_USING_SPI_PDMA
-#define BSP_USING_SPI0_NONE
-#define BSP_USING_SPI1
-#define BSP_USING_SPI1_PDMA
-#define BSP_USING_SPI2
-#define BSP_USING_SPI3_NONE
-#define BSP_USING_I2S
-#define NU_I2S_DMA_FIFO_SIZE 2048
-#define BSP_USING_QSPI
-#define BSP_USING_QSPI0
-#define BSP_USING_CRYPTO
-#define BSP_USING_TRNG
-#define BSP_USING_CRC
-#define NU_CRC_USE_PDMA
-#define BSP_USING_WDT
-#define BSP_USING_USBD
-#define BSP_USING_HSUSBH
-#define NU_USBHOST_HUB_POLLING_INTERVAL 100
-
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_NULINKME
-#define BOARD_USING_ESP8266
-#define BOARD_USING_BMX055
-#define BOARD_USING_NAU88L25
-#define BOARD_USING_STORAGE_SDCARD
-#define BOARD_USING_STORAGE_SPIFLASH
-#define BOARD_USING_HSUSBH_USBD
-
-/* Board extended module drivers */
-
-
-#endif
diff --git a/bsp/nuvoton/numaker-iot-m487/rtconfig.py b/bsp/nuvoton/numaker-iot-m487/rtconfig.py
index 902a2bdce9..7beeafe88a 100644
--- a/bsp/nuvoton/numaker-iot-m487/rtconfig.py
+++ b/bsp/nuvoton/numaker-iot-m487/rtconfig.py
@@ -130,3 +130,11 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = ''
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
+
diff --git a/bsp/nuvoton/numaker-m032ki/.config b/bsp/nuvoton/numaker-m032ki/.config
index acdfc2eb88..13bed80dd6 100644
--- a/bsp/nuvoton/numaker-m032ki/.config
+++ b/bsp/nuvoton/numaker-m032ki/.config
@@ -797,3 +797,5 @@ CONFIG_BSP_USING_NULINKME=y
# Board extended module drivers
#
# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-m032ki.test.utest."
diff --git a/bsp/nuvoton/numaker-m032ki/Kconfig b/bsp/nuvoton/numaker-m032ki/Kconfig
index 5c55e87c61..b396340d12 100644
--- a/bsp/nuvoton/numaker-m032ki/Kconfig
+++ b/bsp/nuvoton/numaker-m032ki/Kconfig
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/numaker-m032ki/applications/mnt.c b/bsp/nuvoton/numaker-m032ki/applications/mnt.c
index 914fa657f6..7ac94f7f0f 100644
--- a/bsp/nuvoton/numaker-m032ki/applications/mnt.c
+++ b/bsp/nuvoton/numaker-m032ki/applications/mnt.c
@@ -12,10 +12,12 @@
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
#if defined(PKG_USING_FAL)
#include
diff --git a/bsp/nuvoton/numaker-m032ki/board/Kconfig b/bsp/nuvoton/numaker-m032ki/board/Kconfig
index a3f0437b7b..bc112e0583 100644
--- a/bsp/nuvoton/numaker-m032ki/board/Kconfig
+++ b/bsp/nuvoton/numaker-m032ki/board/Kconfig
@@ -24,4 +24,5 @@ menu "Hardware Drivers Config"
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
endmenu
diff --git a/bsp/nuvoton/numaker-m032ki/project.uvprojx b/bsp/nuvoton/numaker-m032ki/project.uvprojx
deleted file mode 100644
index dbefa40af7..0000000000
--- a/bsp/nuvoton/numaker-m032ki/project.uvprojx
+++ /dev/null
@@ -1,1228 +0,0 @@
-
-
- 2.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread-m031
- 0x4
- ARM-ADS
- 5060750::V5.06 update 6 (build 750)::ARMCC
- 5060750::V5.06 update 6 (build 750)::ARMCC
- 0
-
-
- M032KIAAE
- Nuvoton
- Nuvoton.NuMicro_DFP.1.3.10
- http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
- IRAM(0x20000000,0x18000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(12000000)
-
-
- UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M031_AP_512 -FS00 -FL080000 -FP0($$Device:M032KIAAE$Flash\M031_AP_512.FLM))
- 0
- $$Device:M032KIAAE$Device\M031\Include\M031Series.h
-
-
-
-
-
-
-
-
-
- $$Device:M032KIAAE$SVD\Nuvoton\M031AE_v1.svd
- 0
- 0
-
-
-
-
-
-
- 0
- 0
- 0
- 0
- 1
-
- .\build\keil5\
- rtthread
- 1
- 0
- 1
- 1
- 1
- .\build\keil5\
- 1
- 0
- 0
-
- 0
- 0
-
-
- 0
- 0
- 0
- 0
-
-
- 0
- 0
-
-
- 0
- 0
- 0
- 0
-
-
- 1
- 1
- fromelf --bin ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.bin"
- fromelf --text -c ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.txt"
- 0
- 0
- 0
- 0
-
- 1
-
-
-
- 0
- 0
- 0
- 0
- 0
- 1
- 0
- 0
- 0
- 0
- 3
-
-
- 1
-
-
- SARMCM3.DLL
-
- DARMCM1.DLL
- -pCM0
- SARMCM3.DLL
-
- TARMCM1.DLL
- -pCM0
-
-
-
- 1
- 0
- 0
- 0
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- startup_M031Series.s
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-
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-
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-
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- drv_crypto.c
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-
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-
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- Filesystem
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-
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-
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-
-
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-
-
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-
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-
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-
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-
-
-
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- 1
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-
-
-
-
- hid.c
- 1
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-
-
-
-
- UTest
-
-
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- 1
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-
-
-
-
- utestcases
-
-
- mem_tc.c
- 1
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-
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diff --git a/bsp/nuvoton/numaker-m032ki/rtconfig.py b/bsp/nuvoton/numaker-m032ki/rtconfig.py
index bc7ec5b5c1..1061a7f5fd 100644
--- a/bsp/nuvoton/numaker-m032ki/rtconfig.py
+++ b/bsp/nuvoton/numaker-m032ki/rtconfig.py
@@ -122,3 +122,11 @@ elif PLATFORM == 'iar':
EXEC_PATH += '/arm/bin/'
POST_ACTION = ''
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
+
diff --git a/bsp/nuvoton/numaker-m2354/.config b/bsp/nuvoton/numaker-m2354/.config
index 0ff7f7a969..12f8e22bcc 100644
--- a/bsp/nuvoton/numaker-m2354/.config
+++ b/bsp/nuvoton/numaker-m2354/.config
@@ -557,6 +557,7 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -567,7 +568,6 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -618,6 +618,7 @@ CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -652,14 +653,14 @@ CONFIG_FAL_DEBUG_CONFIG=y
CONFIG_FAL_DEBUG=1
CONFIG_FAL_PART_HAS_TABLE_CFG=y
# CONFIG_FAL_USING_SFUD_PORT is not set
-CONFIG_PKG_USING_FAL_V00500=y
+# CONFIG_PKG_USING_FAL_V00500 is not set
# CONFIG_PKG_USING_FAL_V00400 is not set
# CONFIG_PKG_USING_FAL_V00300 is not set
# CONFIG_PKG_USING_FAL_V00200 is not set
# CONFIG_PKG_USING_FAL_V00100 is not set
-# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set
-CONFIG_PKG_FAL_VER="v0.5.0"
-CONFIG_PKG_FAL_VER_NUM=0x00500
+CONFIG_PKG_USING_FAL_LATEST_VERSION=y
+CONFIG_PKG_FAL_VER="latest"
+CONFIG_PKG_FAL_VER_NUM=0x99999
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@@ -742,6 +743,7 @@ CONFIG_PKG_FAL_VER_NUM=0x00500
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -829,19 +831,8 @@ CONFIG_PKG_FAL_VER_NUM=0x00500
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
-
-#
-# Nuvoton Packages Config
-#
-CONFIG_NU_PKG_USING_UTILS=y
-CONFIG_NU_PKG_USING_DEMO=y
-# CONFIG_NU_PKG_USING_BMX055 is not set
-# CONFIG_NU_PKG_USING_MAX31875 is not set
-# CONFIG_NU_PKG_USING_NAU88L25 is not set
-# CONFIG_NU_PKG_USING_NAU8822 is not set
-# CONFIG_NU_PKG_USING_DA9062 is not set
-# CONFIG_NU_PKG_USING_ILI9341 is not set
-# CONFIG_NU_PKG_USING_SPINAND is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
@@ -947,3 +938,18 @@ CONFIG_BOARD_USING_OTG=y
# Board extended module drivers
#
CONFIG_BOARD_USING_SEGMENT_LCD=y
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+# CONFIG_NU_PKG_USING_NAU88L25 is not set
+# CONFIG_NU_PKG_USING_NAU8822 is not set
+# CONFIG_NU_PKG_USING_DA9062 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-m2354.test.utest."
diff --git a/bsp/nuvoton/numaker-m2354/Kconfig b/bsp/nuvoton/numaker-m2354/Kconfig
index 90354447b3..b396340d12 100644
--- a/bsp/nuvoton/numaker-m2354/Kconfig
+++ b/bsp/nuvoton/numaker-m2354/Kconfig
@@ -9,7 +9,7 @@ config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
-
+
# you can change the RTT_ROOT default "../../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/numaker-m2354/applications/SConscript b/bsp/nuvoton/numaker-m2354/applications/SConscript
index 9ffdbcd0f9..3769d125df 100644
--- a/bsp/nuvoton/numaker-m2354/applications/SConscript
+++ b/bsp/nuvoton/numaker-m2354/applications/SConscript
@@ -3,9 +3,19 @@
from building import *
cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-Return('group')
+objs = objs + group
+
+Return('objs')
+
diff --git a/bsp/nuvoton/numaker-m2354/applications/lvgl/SConscript b/bsp/nuvoton/numaker-m2354/applications/lvgl/SConscript
new file mode 100644
index 0000000000..18f793dbe0
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/SConscript
@@ -0,0 +1,10 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('LVGL-port', src, depend = ['PKG_USING_LVGL'], CPPPATH = CPPPATH)
+
+Return('group')
+
diff --git a/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_conf.h b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_conf.h
new file mode 100644
index 0000000000..9c2479dc5c
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_conf.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-10-18 Meco Man First version
+ */
+
+#ifndef LV_CONF_H
+#define LV_CONF_H
+
+#define LV_USE_PERF_MONITOR 1
+#define LV_COLOR_DEPTH 16
+
+#define LV_HOR_RES_MAX (320)
+#define LV_VER_RES_MAX (240)
+
+#define LV_FONT_MONTSERRAT_12 1
+#define LV_FONT_MONTSERRAT_16 1
+#define LV_USE_DEMO_RTT_MUSIC 1
+#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
+
+#define LV_DISP_DEF_REFR_PERIOD 16
+
+//#define CONFIG_LV_LOG_LEVEL LV_LOG_LEVEL_TRACE
+#endif
diff --git a/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_demo.c b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_demo.c
new file mode 100644
index 0000000000..7ac1eab9e5
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_demo.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-10-17 Meco Man First version
+ */
+#include
+#include
+#define DBG_TAG "LVGL"
+#define DBG_LVL DBG_INFO
+#include
+
+#ifndef LV_THREAD_STACK_SIZE
+ #define LV_THREAD_STACK_SIZE 4096
+#endif
+
+#ifndef LV_THREAD_PRIO
+ #define LV_THREAD_PRIO (RT_THREAD_PRIORITY_MAX*2/3)
+#endif
+
+static void lvgl_thread(void *parameter)
+{
+ extern void lv_demo_music(void);
+ lv_demo_music();
+
+ while (1)
+ {
+ lv_task_handler();
+ rt_thread_mdelay(1);
+ }
+}
+
+static int lvgl_demo_init(void)
+{
+ rt_thread_t tid;
+
+ tid = rt_thread_create("LVGL", lvgl_thread, RT_NULL, LV_THREAD_STACK_SIZE, LV_THREAD_PRIO, 10);
+ if (tid == RT_NULL)
+ {
+ LOG_E("Fail to create 'LVGL' thread");
+ }
+ rt_thread_startup(tid);
+
+ return 0;
+}
+INIT_APP_EXPORT(lvgl_demo_init);
diff --git a/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_disp.c b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_disp.c
new file mode 100644
index 0000000000..cee304eb09
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_disp.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-17 Wayne The first version
+ */
+#include
+
+#define LOG_TAG "lvgl.disp"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME LOG_TAG
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include
+
+/*A static or global variable to store the buffers*/
+static lv_disp_draw_buf_t disp_buf;
+static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/
+
+static rt_device_t lcd_device = 0;
+static struct rt_device_graphic_info info;
+
+static void lcd_fb_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
+{
+ /* Rendering */
+ struct rt_device_rect_info rect;
+
+ rect.x = area->x1;
+ rect.y = area->y1;
+ rect.width = area->x2 - area->x1 + 1;
+ rect.height = area->y2 - area->y1 + 1;
+
+ rt_device_control(lcd_device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
+ lv_disp_flush_ready(disp_drv);
+}
+
+void lcd_perf_monitor(struct _lv_disp_drv_t *disp_drv, uint32_t time, uint32_t px)
+{
+ rt_kprintf("Elapsed: %dms, Pixel: %d, Bytes:%d\n", time, px, px * sizeof(lv_color_t));
+}
+
+void lv_port_disp_init(void)
+{
+ rt_err_t result;
+ void *buf1 = RT_NULL;
+
+ lcd_device = rt_device_find("lcd");
+ if (lcd_device == 0)
+ {
+ LOG_E("error!");
+ return;
+ }
+
+ /* get framebuffer address */
+ result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info);
+ if (result != RT_EOK && info.framebuffer == RT_NULL)
+ {
+ LOG_E("error!");
+ /* get device information failed */
+ return;
+ }
+
+ RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
+ info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
+
+ buf1 = (void *)info.framebuffer;
+ rt_kprintf("LVGL: Use one buffers - buf1@%08x\n", buf1);
+
+ /*Initialize `disp_buf` with the buffer(s).*/
+ lv_disp_draw_buf_init(&disp_buf, buf1, RT_NULL, info.width * info.height);
+
+ result = rt_device_open(lcd_device, 0);
+ if (result != RT_EOK)
+ {
+ LOG_E("error!");
+ return;
+ }
+
+ lv_disp_drv_init(&disp_drv); /*Basic initialization*/
+
+ /*Set the resolution of the display*/
+ disp_drv.hor_res = info.width;
+ disp_drv.ver_res = info.height;
+
+ /*Set a display buffer*/
+ disp_drv.draw_buf = &disp_buf;
+
+ /*Write the internal buffer (draw_buf) to the display*/
+ disp_drv.flush_cb = lcd_fb_flush;
+
+ /* Called after every refresh cycle to tell the rendering and flushing time + the number of flushed pixels */
+ //disp_drv.monitor_cb = lcd_perf_monitor;
+
+ /*Finally register the driver*/
+ lv_disp_drv_register(&disp_drv);
+}
diff --git a/bsp/gd32103c-eval/drivers/drv_adc.h b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_disp.h
similarity index 50%
rename from bsp/gd32103c-eval/drivers/drv_adc.h
rename to bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_disp.h
index 4fba7c093d..ef39eb03cd 100644
--- a/bsp/gd32103c-eval/drivers/drv_adc.h
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_disp.h
@@ -4,20 +4,20 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
- * Date Author Notes
- * 2021-01-03 iysheng first release
+ * Date Author Notes
+ * 2021-10-18 Meco Man The first version
*/
-
-#ifndef __DRV_ADC_H__
-#define __DRV_ADC_H__
+#ifndef LV_PORT_DISP_H
+#define LV_PORT_DISP_H
#ifdef __cplusplus
extern "C" {
#endif
+void lv_port_disp_init(void);
+
#ifdef __cplusplus
-}
+} /*extern "C"*/
#endif
-#endif /* __DRV_ADC_H__ */
-
+#endif
diff --git a/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_indev.c b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_indev.c
new file mode 100644
index 0000000000..4451ad4f84
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_indev.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-10-18 Meco Man The first version
+ * 2021-12-17 Wayne Add input event
+ */
+#include
+#include
+#include
+#include "touch.h"
+
+static lv_indev_state_t last_state = LV_INDEV_STATE_REL;
+static rt_int16_t last_x = 0;
+static rt_int16_t last_y = 0;
+
+static void input_read(lv_indev_drv_t *indev_drv, lv_indev_data_t *data)
+{
+ data->point.x = last_x;
+ data->point.y = last_y;
+ data->state = last_state;
+}
+
+void nu_touch_inputevent_cb(rt_int16_t x, rt_int16_t y, rt_uint8_t state)
+{
+ switch (state)
+ {
+ case RT_TOUCH_EVENT_UP:
+ last_state = LV_INDEV_STATE_RELEASED;
+ break;
+ case RT_TOUCH_EVENT_DOWN:
+ last_x = x;
+ last_y = y;
+ last_state = LV_INDEV_STATE_PRESSED;
+ break;
+ case RT_TOUCH_EVENT_MOVE:
+ last_x = x;
+ last_y = y;
+ break;
+ }
+}
+
+void lv_port_indev_init(void)
+{
+ static lv_indev_drv_t indev_drv;
+
+ /* Basic initialization */
+ lv_indev_drv_init(&indev_drv);
+ indev_drv.type = LV_INDEV_TYPE_POINTER;
+ indev_drv.read_cb = input_read;
+
+ /* Register the driver in LVGL and save the created input device object */
+ lv_indev_drv_register(&indev_drv);
+}
diff --git a/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_indev.h b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_indev.h
new file mode 100644
index 0000000000..dec92bccbc
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/lvgl/lv_port_indev.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-10-18 Meco Man The first version
+ */
+#ifndef LV_PORT_INDEV_H
+#define LV_PORT_INDEV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+extern lv_indev_t *button_indev;
+
+void lv_port_indev_init(void);
+void lv_port_indev_input(rt_int16_t x, rt_int16_t y, lv_indev_state_t state);
+
+#ifdef __cplusplus
+} /*extern "C"*/
+#endif
+
+#endif
diff --git a/bsp/nuvoton/numaker-m2354/board/Kconfig b/bsp/nuvoton/numaker-m2354/board/Kconfig
index a3e751aa42..8af0a080ea 100644
--- a/bsp/nuvoton/numaker-m2354/board/Kconfig
+++ b/bsp/nuvoton/numaker-m2354/board/Kconfig
@@ -61,6 +61,37 @@ menu "Hardware Drivers Config"
endmenu
menu "Board extended module drivers"
+ config BOARD_USING_LCD_ILI9341
+ bool "LCD ILI9341 (over spi1)"
+ select RT_USING_TOUCH
+ select NU_PKG_USING_ILI9341
+ select NU_PKG_USING_ILI9341_SPI
+ select NU_PKG_ILI9341_WITH_OFFSCREEN_FRAMEBUFFER
+ select NU_PKG_ILI9341_HORIZONTAL
+ select BSP_USING_SPI1
+ select PKG_USING_LVGL
+ select PKG_USING_LV_MUSIC_DEMO
+ default n
+
+ if BOARD_USING_LCD_ILI9341
+
+ config BOARD_USING_ILI9341_PIN_BACKLIGHT
+ int "Specify the pin index of backlight pin index"
+ range 0 127
+ default 43
+
+ config BOARD_USING_ILI9341_PIN_RESET
+ int "Specify the pin index of reset pin index"
+ range 0 127
+ default 9
+
+ config BOARD_USING_ILI9341_PIN_DC
+ int "Specify the pin index of data&command switching"
+ range 0 127
+ default 8
+
+ endif
+
config BOARD_USING_SEGMENT_LCD
bool "Segment LCD supporting.(over lcd)"
select BSP_USING_SLCD
@@ -68,4 +99,6 @@ menu "Hardware Drivers Config"
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
+
endmenu
diff --git a/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c
index f64be93443..f4e2a1ffd0 100644
--- a/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c
+++ b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c
@@ -108,7 +108,12 @@ void nutool_pincfg_deinit_epwm0(void)
void nutool_pincfg_init_epwm1(void)
{
SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk);
+#if !defined(BOARD_USING_LCD_ILI9341)
SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 | SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 | SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 | SYS_GPC_MFPH_PC9MFP_EPWM1_CH3);
+#else
+ SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 | SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 | SYS_GPC_MFPH_PC9MFP_EPWM1_CH3);
+#endif
+
SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk);
SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 | SYS_GPC_MFPL_PC0MFP_EPWM1_CH5);
@@ -396,7 +401,9 @@ void nutool_pincfg_init(void)
nutool_pincfg_init_spi0();
nutool_pincfg_init_spi1();
nutool_pincfg_init_uart0();
+#if !defined(BOARD_USING_LCD_ILI9341)
nutool_pincfg_init_uart1();
+#endif
nutool_pincfg_init_uart4();
nutool_pincfg_init_usb();
diff --git a/bsp/nuvoton/numaker-m2354/board/board_dev.c b/bsp/nuvoton/numaker-m2354/board/board_dev.c
index 3cf1d862b7..0b2453be39 100644
--- a/bsp/nuvoton/numaker-m2354/board/board_dev.c
+++ b/bsp/nuvoton/numaker-m2354/board/board_dev.c
@@ -13,6 +13,32 @@
#include
#include
+
+
+#if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_SPI)
+#include
+#if defined(PKG_USING_GUIENGINE)
+ #include
+#endif
+int rt_hw_ili9341_port(void)
+{
+ if (rt_hw_lcd_ili9341_spi_init("spi1") != RT_EOK)
+ return -1;
+
+ rt_hw_lcd_ili9341_init();
+
+#if defined(PKG_USING_GUIENGINE)
+ rt_device_t lcd_ili9341;
+ lcd_ili9341 = rt_device_find("lcd");
+ if (lcd_ili9341)
+ {
+ rtgui_graphic_set_device(lcd_ili9341);
+ }
+#endif
+ return 0;
+}
+INIT_COMPONENT_EXPORT(rt_hw_ili9341_port);
+#endif /* BOARD_USING_LCD_ILI9341 */
#if defined(BOARD_USING_ESP8266)
#include
diff --git a/bsp/nuvoton/numaker-m2354/project.uvprojx b/bsp/nuvoton/numaker-m2354/project.uvprojx
deleted file mode 100644
index c15ccbb19a..0000000000
--- a/bsp/nuvoton/numaker-m2354/project.uvprojx
+++ /dev/null
@@ -1,1768 +0,0 @@
-
-
- 2.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread-m2354
- 0x4
- ARM-ADS
- 6100001::V6.10.1::.\ARMCLANG
- 1
-
-
- M2354KJFAE
- Nuvoton
- Nuvoton.NuMicro_DFP.1.3.10
- http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
- IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE
-
-
- UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M2354_AP_1M -FS00 -FL0100000 -FP0($$Device:M2354KJFAE$Flash\M2354_AP_1M.FLM))
- 0
- $$Device:M2354KJFAE$Device\M2354\Include\M2354.h
-
-
-
-
-
-
-
-
-
- $$Device:M2354KJFAE$SVD\Nuvoton\M2354.svd
- 0
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- fromelf --bin ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.bin"
- fromelf --text -c ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.txt"
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- SARMV8M.DLL
- -MPU
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- -pCM23
-
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- "" ()
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-
-
- nu_i2s.c
- 1
- ..\libraries\m2354\StdDriver\src\nu_i2s.c
-
-
-
-
- nu_rng.c
- 1
- ..\libraries\m2354\StdDriver\src\nu_rng.c
-
-
-
-
- nu_gpio.c
- 1
- ..\libraries\m2354\StdDriver\src\nu_gpio.c
-
-
-
-
- nu_keystore.c
- 1
- ..\libraries\m2354\StdDriver\src\nu_keystore.c
-
-
-
-
- nu_tamper.c
- 1
- ..\libraries\m2354\StdDriver\src\nu_tamper.c
-
-
-
-
- m2354_usbhostlib
-
-
- mem_alloc.c
- 1
- ..\libraries\m2354\USBHostLib\src\mem_alloc.c
-
-
-
-
- ohci.c
- 1
- ..\libraries\m2354\USBHostLib\src\ohci.c
-
-
-
-
- usb_core.c
- 1
- ..\libraries\m2354\USBHostLib\src\usb_core.c
-
-
-
-
- nu_pkgs_demo
-
-
- usbd_cdc_vcom_echo.c
- 1
- ..\libraries\nu_packages\Demo\usbd_cdc_vcom_echo.c
-
-
-
-
- slcd_show_tick.c
- 1
- ..\libraries\nu_packages\Demo\slcd_show_tick.c
-
-
-
-
- usbd_hid_dance_mouse.c
- 1
- ..\libraries\nu_packages\Demo\usbd_hid_dance_mouse.c
-
-
-
-
- nu_pkgs_slcd
-
-
- slcd_rhe6616tp01.c
- 1
- ..\libraries\nu_packages\SLCD\slcd_rhe6616tp01.c
-
-
-
-
- POSIX
-
-
- select.c
- 1
- ..\..\..\components\libc\posix\io\select.c
-
-
-
-
- poll.c
- 1
- ..\..\..\components\libc\posix\io\poll\poll.c
-
-
-
-
- rt_usbd
-
-
- hid.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\hid.c
-
-
-
-
- usbdevice_core.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c
-
-
-
-
- usbdevice.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c
-
-
-
-
- rt_usbh
-
-
- udisk.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\udisk.c
-
-
-
-
- usbhost.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost.c
-
-
-
-
- mass.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\mass.c
-
-
-
-
- usbhost_core.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c
-
-
-
-
- hub.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\hub.c
-
-
-
-
- driver.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\driver.c
-
-
-
-
- SAL
-
-
- netdev_ipaddr.c
- 1
- ..\..\..\components\net\netdev\src\netdev_ipaddr.c
-
-
-
-
- netdev.c
- 1
- ..\..\..\components\net\netdev\src\netdev.c
-
-
-
-
- dfs_net.c
- 1
- ..\..\..\components\net\sal_socket\dfs_net\dfs_net.c
-
-
-
-
- sal_socket.c
- 1
- ..\..\..\components\net\sal_socket\src\sal_socket.c
-
-
-
-
- net_sockets.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_sockets.c
-
-
-
-
- net_netdb.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_netdb.c
-
-
-
-
- af_inet_at.c
- 1
- ..\..\..\components\net\sal_socket\impl\af_inet_at.c
-
-
-
-
- Sensors
-
-
- sensor_cmd.c
- 1
- ..\..\..\components\drivers\sensors\sensor_cmd.c
-
-
-
-
- sensor.c
- 1
- ..\..\..\components\drivers\sensors\sensor.c
-
-
-
-
- UTest
-
-
- utest.c
- 1
- ..\..\..\components\utilities\utest\utest.c
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuvoton/numaker-m2354/rtconfig.h b/bsp/nuvoton/numaker-m2354/rtconfig.h
deleted file mode 100644
index 81c3909d82..0000000000
--- a/bsp/nuvoton/numaker-m2354/rtconfig.h
+++ /dev/null
@@ -1,383 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 8
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 2048
-
-/* kservice optimization */
-
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-#define RT_USING_SIGNALS
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define RT_USING_MSH
-#define FINSH_USING_MSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_CMD_SIZE 80
-#define MSH_USING_BUILT_IN_COMMANDS
-#define FINSH_USING_DESCRIPTION
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 4
-#define DFS_FILESYSTEM_TYPES_MAX 4
-#define DFS_FD_MAX 32
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_3
-#define RT_DFS_ELM_USE_LFN 3
-#define RT_DFS_ELM_LFN_UNICODE_0
-#define RT_DFS_ELM_LFN_UNICODE 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 2
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
-#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
-#define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 2048
-#define RT_USING_CAN
-#define RT_USING_HWTIMER
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_PM
-#define PM_TICKLESS_THRESHOLD_TIME 2
-#define RT_USING_RTC
-#define RT_USING_SPI
-#define RT_USING_QSPI
-#define RT_USING_SFUD
-#define RT_SFUD_USING_SFDP
-#define RT_SFUD_USING_FLASH_INFO_TABLE
-#define RT_SFUD_USING_QSPI
-#define RT_SFUD_SPI_MAX_HZ 50000000
-#define RT_DEBUG_SFUD
-#define RT_USING_WDT
-#define RT_USING_AUDIO
-#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
-#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
-#define RT_AUDIO_RECORD_PIPE_SIZE 2048
-#define RT_USING_SENSOR
-#define RT_USING_SENSOR_CMD
-#define RT_USING_HWCRYPTO
-#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
-#define RT_HWCRYPTO_IV_MAX_SIZE 16
-#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
-#define RT_HWCRYPTO_USING_AES
-#define RT_HWCRYPTO_USING_AES_ECB
-#define RT_HWCRYPTO_USING_AES_CBC
-#define RT_HWCRYPTO_USING_AES_CFB
-#define RT_HWCRYPTO_USING_AES_CTR
-#define RT_HWCRYPTO_USING_AES_OFB
-#define RT_HWCRYPTO_USING_DES
-#define RT_HWCRYPTO_USING_DES_ECB
-#define RT_HWCRYPTO_USING_DES_CBC
-#define RT_HWCRYPTO_USING_3DES
-#define RT_HWCRYPTO_USING_3DES_ECB
-#define RT_HWCRYPTO_USING_3DES_CBC
-#define RT_HWCRYPTO_USING_SHA1
-#define RT_HWCRYPTO_USING_SHA2
-#define RT_HWCRYPTO_USING_SHA2_224
-#define RT_HWCRYPTO_USING_SHA2_256
-#define RT_HWCRYPTO_USING_SHA2_384
-#define RT_HWCRYPTO_USING_SHA2_512
-#define RT_HWCRYPTO_USING_RNG
-#define RT_HWCRYPTO_USING_CRC
-#define RT_HWCRYPTO_USING_CRC_07
-#define RT_HWCRYPTO_USING_CRC_8005
-#define RT_HWCRYPTO_USING_CRC_1021
-#define RT_HWCRYPTO_USING_CRC_04C11DB7
-
-/* Using USB */
-
-#define RT_USING_USB
-#define RT_USING_USB_HOST
-#define RT_USBH_MSTORAGE
-#define UDISK_MOUNTPOINT "/"
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define _RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID_MOUSE
-
-/* POSIX layer and C standard library */
-
-#define RT_LIBC_DEFAULT_TIMEZONE 8
-
-/* POSIX (Portable Operating System Interface) layer */
-
-#define RT_USING_POSIX_FS
-#define RT_USING_POSIX_DEVIO
-#define RT_USING_POSIX_POLL
-#define RT_USING_POSIX_SELECT
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-#define RT_USING_SAL
-#define SAL_INTERNET_CHECK
-
-/* protocol stack implement */
-
-#define SAL_USING_AT
-#define SAL_USING_POSIX
-
-/* Network interface device */
-
-#define RT_USING_NETDEV
-#define NETDEV_USING_IFCONFIG
-#define NETDEV_USING_PING
-#define NETDEV_USING_NETSTAT
-#define NETDEV_USING_AUTO_DEFAULT
-#define NETDEV_IPV4 1
-#define NETDEV_IPV6 0
-
-/* light weight TCP/IP stack */
-
-
-/* AT commands */
-
-#define RT_USING_AT
-#define AT_USING_CLIENT
-#define AT_CLIENT_NUM_MAX 1
-#define AT_USING_SOCKET
-#define AT_USING_CLI
-#define AT_CMD_MAX_LEN 2048
-#define AT_SW_VERSION_NUM 0x10301
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
-
-/* RT-Thread Utestcases */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-#define PKG_USING_AT_DEVICE
-#define AT_DEVICE_USING_ESP8266
-#define AT_DEVICE_ESP8266_INIT_ASYN
-#define PKG_USING_AT_DEVICE_LATEST_VERSION
-#define PKG_AT_DEVICE_VER_NUM 0x99999
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-/* LVGL: powerful and easy-to-use embedded GUI library */
-
-
-/* u8g2: a monochrome graphic library */
-
-
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
-/* acceleration: Assembly language or algorithmic acceleration packages */
-
-
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
-/* Micrium: Micrium software products porting for RT-Thread */
-
-#define PKG_USING_FAL
-#define FAL_DEBUG_CONFIG
-#define FAL_DEBUG 1
-#define FAL_PART_HAS_TABLE_CFG
-#define PKG_USING_FAL_V00500
-#define PKG_FAL_VER_NUM 0x00500
-
-/* peripheral libraries and drivers */
-
-
-/* AI packages */
-
-
-/* miscellaneous packages */
-
-/* samples: kernel and components samples */
-
-
-/* entertainment: terminal games and other interesting software packages */
-
-
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_DEMO
-
-/* Hardware Drivers Config */
-
-/* On-chip Peripheral Drivers */
-
-#define SOC_SERIES_M2354
-#define BSP_USE_STDDRIVER_SOURCE
-#define BSP_USING_PDMA
-#define NU_PDMA_MEMFUN_ACTOR_MAX 2
-#define NU_PDMA_SGTBL_POOL_SIZE 16
-#define BSP_USING_FMC
-#define BSP_USING_GPIO
-#define BSP_USING_CLK
-#define NU_CLK_INVOKE_WKTMR
-#define BSP_USING_RTC
-#define NU_RTC_SUPPORT_MSH_CMD
-#define BSP_USING_EADC
-#define BSP_USING_EADC0
-#define BSP_USING_TMR
-#define BSP_USING_UART
-#define BSP_USING_UART0
-#define BSP_USING_UART1
-#define BSP_USING_UART4
-#define BSP_USING_UART4_TX_DMA
-#define BSP_USING_UART4_RX_DMA
-#define BSP_USING_I2C
-#define BSP_USING_I2C1
-#define BSP_USING_SDH
-#define BSP_USING_SDH0
-#define NU_SDH_USING_PDMA
-#define NU_SDH_HOTPLUG
-#define NU_SDH_MOUNT_ON_ROOT
-#define BSP_USING_SPI
-#define BSP_USING_SPI0
-#define BSP_USING_SPI1
-#define BSP_USING_SPI2_NONE
-#define BSP_USING_SPI3_NONE
-#define BSP_USING_CRYPTO
-#define BSP_USING_TRNG
-#define BSP_USING_CRC
-#define NU_CRC_USE_PDMA
-#define BSP_USING_WDT
-#define BSP_USING_SLCD
-#define BSP_USING_USBD
-#define BSP_USING_USBH
-#define NU_USBHOST_HUB_POLLING_INTERVAL 100
-#define BSP_USING_OTG
-
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_NULINKME
-#define BOARD_USING_ESP8266
-#define BOARD_USING_STORAGE_SDCARD
-#define BOARD_USING_OTG
-
-/* Board extended module drivers */
-
-#define BOARD_USING_SEGMENT_LCD
-
-#endif
diff --git a/bsp/nuvoton/numaker-m2354/rtconfig.py b/bsp/nuvoton/numaker-m2354/rtconfig.py
index 2a59f1a4f0..2b2d5c86f7 100644
--- a/bsp/nuvoton/numaker-m2354/rtconfig.py
+++ b/bsp/nuvoton/numaker-m2354/rtconfig.py
@@ -122,3 +122,11 @@ elif PLATFORM == 'iar':
EXEC_PATH += '/arm/bin/'
POST_ACTION = ''
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
+
diff --git a/bsp/nuvoton/numaker-pfm-m487/.config b/bsp/nuvoton/numaker-pfm-m487/.config
index d0bd4b04bf..8bc0959025 100644
--- a/bsp/nuvoton/numaker-pfm-m487/.config
+++ b/bsp/nuvoton/numaker-pfm-m487/.config
@@ -279,7 +279,6 @@ CONFIG_RT_USB_DEVICE_HID_MOUSE=y
#
# POSIX layer and C standard library
#
-# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
@@ -295,7 +294,9 @@ CONFIG_RT_USING_POSIX_DEVIO=y
# CONFIG_RT_USING_POSIX_MMAN is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
@@ -343,8 +344,7 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@@ -578,6 +578,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -588,7 +589,6 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -639,6 +639,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -675,13 +676,13 @@ CONFIG_FAL_DEBUG=1
CONFIG_FAL_PART_HAS_TABLE_CFG=y
# CONFIG_FAL_USING_SFUD_PORT is not set
# CONFIG_PKG_USING_FAL_V00500 is not set
-CONFIG_PKG_USING_FAL_V00400=y
+# CONFIG_PKG_USING_FAL_V00400 is not set
# CONFIG_PKG_USING_FAL_V00300 is not set
# CONFIG_PKG_USING_FAL_V00200 is not set
# CONFIG_PKG_USING_FAL_V00100 is not set
-# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set
-CONFIG_PKG_FAL_VER="v0.4.0"
-CONFIG_PKG_FAL_VER_NUM=0x00400
+CONFIG_PKG_USING_FAL_LATEST_VERSION=y
+CONFIG_PKG_FAL_VER="latest"
+CONFIG_PKG_FAL_VER_NUM=0x99999
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@@ -764,6 +765,7 @@ CONFIG_PKG_FAL_VER_NUM=0x00400
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -851,19 +853,8 @@ CONFIG_PKG_FAL_VER_NUM=0x00400
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
-
-#
-# Nuvoton Packages Config
-#
-CONFIG_NU_PKG_USING_UTILS=y
-CONFIG_NU_PKG_USING_DEMO=y
-# CONFIG_NU_PKG_USING_BMX055 is not set
-# CONFIG_NU_PKG_USING_MAX31875 is not set
-CONFIG_NU_PKG_USING_NAU88L25=y
-# CONFIG_NU_PKG_USING_NAU8822 is not set
-# CONFIG_NU_PKG_USING_DA9062 is not set
-# CONFIG_NU_PKG_USING_ILI9341 is not set
-# CONFIG_NU_PKG_USING_SPINAND is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
@@ -965,6 +956,7 @@ CONFIG_BOARD_USING_IP101GR=y
CONFIG_BOARD_USING_NAU88L25=y
CONFIG_BOARD_USING_STORAGE_SDCARD=y
CONFIG_BOARD_USING_STORAGE_SPIFLASH=y
+CONFIG_BOARD_USING_USB_D_H=y
# CONFIG_BOARD_USING_HSUSBD is not set
# CONFIG_BOARD_USING_HSUSBD_USBH is not set
# CONFIG_BOARD_USING_HSUSBH is not set
@@ -975,3 +967,18 @@ CONFIG_BOARD_USING_HSUSBH_USBD=y
# Board extended module drivers
#
# CONFIG_BOARD_USING_ADVANCE_V4 is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+CONFIG_NU_PKG_USING_NAU88L25=y
+# CONFIG_NU_PKG_USING_NAU8822 is not set
+# CONFIG_NU_PKG_USING_DA9062 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-pfm-m487.test.utest."
diff --git a/bsp/nuvoton/numaker-pfm-m487/Kconfig b/bsp/nuvoton/numaker-pfm-m487/Kconfig
index 5c55e87c61..b396340d12 100644
--- a/bsp/nuvoton/numaker-pfm-m487/Kconfig
+++ b/bsp/nuvoton/numaker-pfm-m487/Kconfig
@@ -18,12 +18,6 @@ config PKGS_DIR
option env="PKGS_ROOT"
default "packages"
-config NU_PKGS_DIR
- string
- option env="NU_PKGS_ROOT"
- default "../libraries/nu_packages"
-
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
-source "$NU_PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c b/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c
index 6e7a9ff5de..0b4ed458b1 100644
--- a/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c
+++ b/bsp/nuvoton/numaker-pfm-m487/applications/mnt.c
@@ -12,10 +12,12 @@
#include
-#if defined(RT_USING_DFS)
- #include
- #include
-#endif
+#include
+#include
+#include
+#include
+#include
+#include
#if defined(PKG_USING_FAL)
#include
diff --git a/bsp/nuvoton/numaker-pfm-m487/board/Kconfig b/bsp/nuvoton/numaker-pfm-m487/board/Kconfig
index fc56305c9d..dd7ef72a68 100644
--- a/bsp/nuvoton/numaker-pfm-m487/board/Kconfig
+++ b/bsp/nuvoton/numaker-pfm-m487/board/Kconfig
@@ -37,42 +37,48 @@ menu "Hardware Drivers Config"
select BSP_USING_QSPI0
default y
- choice
- prompt "Select FS/HS USB Ports"
+ config BOARD_USING_USB_D_H
+ bool "Enable USB Device or Host function"
+ help
+ Choose this option if you need USB function.
- config BOARD_USING_HSUSBD
- select BSP_USING_HSUSBD
- bool "Enable HSUSBD(over USB2.0)"
- help
- Choose this option if you need HSUSBD function mode.
+ if BOARD_USING_USB_D_H
+ choice
+ prompt "Select FS/HS USB Ports"
- config BOARD_USING_HSUSBD_USBH
- select BSP_USING_USBH
- select BSP_USING_HSUSBD
- bool "Enable HSUSBD(over USB2.0) and USBH(over USB1.1)"
- help
- Choose this option if you need HSUSBD and USBH function mode at the same time.
+ config BOARD_USING_HSUSBD
+ select BSP_USING_HSUSBD
+ bool "Enable HSUSBD(over USB2.0)"
+ help
+ Choose this option if you need HSUSBD function mode.
- config BOARD_USING_HSUSBH
- select BSP_USING_HSUSBH
- bool "Enable HSUSBH(over USB2.0)"
- help
- Choose this option if you need HSUSBH function mode.
+ config BOARD_USING_HSUSBD_USBH
+ select BSP_USING_USBH
+ select BSP_USING_HSUSBD
+ bool "Enable HSUSBD(over USB2.0) and USBH(over USB1.1)"
+ help
+ Choose this option if you need HSUSBD and USBH function mode at the same time.
- config BOARD_USING_HSUSBH_USBD
- select BSP_USING_HSUSBH
- select BSP_USING_USBD
- bool "Enable HSUSBH(over USB2.0) and USBD(over USB1.1)"
- help
- Choose this option if you need HSUSBH and USBD function mode at the same time.
+ config BOARD_USING_HSUSBH
+ select BSP_USING_HSUSBH
+ bool "Enable HSUSBH(over USB2.0)"
+ help
+ Choose this option if you need HSUSBH function mode.
- config BOARD_USING_HSOTG
- select BSP_USING_HSOTG
- bool "Enable HSOTG(over USB2.0)"
- help
- Choose this option if you need HSOTG function mode.
+ config BOARD_USING_HSUSBH_USBD
+ select BSP_USING_HSUSBH
+ select BSP_USING_USBD
+ bool "Enable HSUSBH(over USB2.0) and USBD(over USB1.1)"
+ help
+ Choose this option if you need HSUSBH and USBD function mode at the same time.
- endchoice
+ config BOARD_USING_HSOTG
+ select BSP_USING_HSOTG
+ bool "Enable HSOTG(over USB2.0)"
+ help
+ Choose this option if you need HSOTG function mode.
+ endchoice
+ endif
endmenu
@@ -162,4 +168,6 @@ menu "Hardware Drivers Config"
endmenu
+ source "$BSP_DIR/../libraries/nu_packages/Kconfig"
+
endmenu
diff --git a/bsp/nuvoton/numaker-pfm-m487/project.uvproj b/bsp/nuvoton/numaker-pfm-m487/project.uvproj
deleted file mode 100644
index 9e8d850de2..0000000000
--- a/bsp/nuvoton/numaker-pfm-m487/project.uvproj
+++ /dev/null
@@ -1,1966 +0,0 @@
-
-
- 1.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread-m480
- 0x4
- ARM-ADS
-
-
- M487JIDAE
- Nuvoton
- IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2
-
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- NULink\Nu_Link.dll
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-
- --c99
- __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND
-
- applications;.;..\libraries\m480\CMSIS\Include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\audio;..\..\..\components\drivers\include;..\..\..\components\drivers\hwcrypto;.;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\spi\sfud\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\NuClockConfig;board\NuPinConfig;..\libraries\m480\Device\Nuvoton\M480\Include;..\libraries\m480\rtt_port;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\finsh;.;..\..\..\include;..\libraries\m480\StdDriver\inc;..\..\..\components\net\lwip-2.0.2\src;..\..\..\components\net\lwip-2.0.2\src\include;..\..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\..\components\net\lwip-2.0.2\src\arch\include;..\..\..\components\net\lwip-2.0.2\src\include\netif;..\libraries\m480\USBHostLib\inc;..\libraries\nu_packages\Demo;..\libraries\nu_packages\AudioCodec;..\libraries\nu_packages\NuUtils\inc;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\usb\usbdevice;..\..\..\components\drivers\usb\usbhost;..\..\..\components\drivers\usb\usbhost\class;..\..\..\components\drivers\usb\usbhost\core;..\..\..\components\drivers\usb\usbhost\include;..\..\..\components\drivers\include;..\..\..\components\net\netdev\include;..\..\..\components\net\sal_socket\include;..\..\..\components\net\sal_socket\include\socket;..\..\..\components\net\sal_socket\impl;..\..\..\components\net\sal_socket\include\socket\sys_socket;..\..\..\components\utilities\utest;..\..\..\examples\utest\testcases\kernel
-
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-
-
-
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-
- Applications
-
-
- mnt.c
- 1
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-
-
-
-
- main.c
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-
-
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-
- Compiler
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-
-
-
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-
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- CPU
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-
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-
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- 1
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-
-
-
-
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-
-
-
-
- cpuport.c
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-
-
-
-
- context_rvds.S
- 2
- ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
-
-
-
-
- DeviceDrivers
-
-
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- 1
- ..\..\..\components\drivers\audio\audio.c
-
-
-
-
- audio_pipe.c
- 1
- ..\..\..\components\drivers\audio\audio_pipe.c
-
-
-
-
- can.c
- 1
- ..\..\..\components\drivers\can\can.c
-
-
-
-
- hw_symmetric.c
- 1
- ..\..\..\components\drivers\hwcrypto\hw_symmetric.c
-
-
-
-
- hwcrypto.c
- 1
- ..\..\..\components\drivers\hwcrypto\hwcrypto.c
-
-
-
-
- hw_rng.c
- 1
- ..\..\..\components\drivers\hwcrypto\hw_rng.c
-
-
-
-
- hw_crc.c
- 1
- ..\..\..\components\drivers\hwcrypto\hw_crc.c
-
-
-
-
- hw_hash.c
- 1
- ..\..\..\components\drivers\hwcrypto\hw_hash.c
-
-
-
-
- hwtimer.c
- 1
- ..\..\..\components\drivers\hwtimer\hwtimer.c
-
-
-
-
- i2c_core.c
- 1
- ..\..\..\components\drivers\i2c\i2c_core.c
-
-
-
-
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- 1
- ..\..\..\components\drivers\i2c\i2c_dev.c
-
-
-
-
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- 1
- ..\..\..\components\drivers\i2c\i2c-bit-ops.c
-
-
-
-
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- 1
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-
-
-
-
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-
-
-
-
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-
-
-
-
- lptimer.c
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-
-
-
-
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-
-
-
-
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-
-
-
-
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-
-
-
-
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-
-
-
-
- spi_core.c
- 1
- ..\..\..\components\drivers\spi\spi_core.c
-
-
-
-
- sfud_sfdp.c
- 1
- ..\..\..\components\drivers\spi\sfud\src\sfud_sfdp.c
-
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-
-
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-
-
-
-
- qspi_core.c
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-
-
-
-
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- 1
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-
-
-
-
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-
-
-
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-
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-
-
-
-
- watchdog.c
- 1
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-
-
-
-
-
-
- --c99
-
-
-
-
-
-
-
-
-
- Drivers
-
-
- nutool_pincfg.c
- 1
- board\NuPinConfig\nutool_pincfg.c
-
-
-
-
- board_dev.c
- 1
- board\board_dev.c
-
-
-
-
- nutool_modclkcfg.c
- 1
- board\NuClockConfig\nutool_modclkcfg.c
-
-
-
-
- system_M480.c
- 1
- ..\libraries\m480\Device\Nuvoton\M480\Source\system_M480.c
-
-
-
-
- startup_M480.s
- 2
- ..\libraries\m480\Device\Nuvoton\M480\Source\ARM\startup_M480.s
-
-
-
-
- drv_fmc.c
- 1
- ..\libraries\m480\rtt_port\drv_fmc.c
-
-
-
-
- drv_sdh.c
- 1
- ..\libraries\m480\rtt_port\drv_sdh.c
-
-
-
-
- drv_clk.c
- 1
- ..\libraries\m480\rtt_port\drv_clk.c
-
-
-
-
- drv_crc.c
- 1
- ..\libraries\m480\rtt_port\drv_crc.c
-
-
-
-
- drv_bpwm_capture.c
- 1
- ..\libraries\m480\rtt_port\drv_bpwm_capture.c
-
-
-
-
- drv_usbd.c
- 1
- ..\libraries\m480\rtt_port\drv_usbd.c
-
-
-
-
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- 1
- ..\libraries\m480\rtt_port\drv_epwm.c
-
-
-
-
- drv_ui2c.c
- 1
- ..\libraries\m480\rtt_port\drv_ui2c.c
-
-
-
-
- drv_trng.c
- 1
- ..\libraries\m480\rtt_port\drv_trng.c
-
-
-
-
- drv_rtc.c
- 1
- ..\libraries\m480\rtt_port\drv_rtc.c
-
-
-
-
- drv_ecap.c
- 1
- ..\libraries\m480\rtt_port\drv_ecap.c
-
-
-
-
- drv_uuart.c
- 1
- ..\libraries\m480\rtt_port\drv_uuart.c
-
-
-
-
- drv_gpio.c
- 1
- ..\libraries\m480\rtt_port\drv_gpio.c
-
-
-
-
- drv_pdma.c
- 1
- ..\libraries\m480\rtt_port\drv_pdma.c
-
-
-
-
- drv_timer_capture.c
- 1
- ..\libraries\m480\rtt_port\drv_timer_capture.c
-
-
-
-
- drv_tpwm.c
- 1
- ..\libraries\m480\rtt_port\drv_tpwm.c
-
-
-
-
- drv_spi.c
- 1
- ..\libraries\m480\rtt_port\drv_spi.c
-
-
-
-
- drv_crypto.c
- 1
- ..\libraries\m480\rtt_port\drv_crypto.c
-
-
-
-
- drv_ebi.c
- 1
- ..\libraries\m480\rtt_port\drv_ebi.c
-
-
-
-
- drv_i2c.c
- 1
- ..\libraries\m480\rtt_port\drv_i2c.c
-
-
-
-
- drv_uart.c
- 1
- ..\libraries\m480\rtt_port\drv_uart.c
-
-
-
-
- drv_common.c
- 1
- ..\libraries\m480\rtt_port\drv_common.c
-
-
-
-
- drv_hsusbd.c
- 1
- ..\libraries\m480\rtt_port\drv_hsusbd.c
-
-
-
-
- drv_eadc.c
- 1
- ..\libraries\m480\rtt_port\drv_eadc.c
-
-
-
-
- drv_qei.c
- 1
- ..\libraries\m480\rtt_port\drv_qei.c
-
-
-
-
- drv_spii2s.c
- 1
- ..\libraries\m480\rtt_port\drv_spii2s.c
-
-
-
-
- drv_bpwm.c
- 1
- ..\libraries\m480\rtt_port\drv_bpwm.c
-
-
-
-
- drv_usbhost.c
- 1
- ..\libraries\m480\rtt_port\drv_usbhost.c
-
-
-
-
- drv_hsotg.c
- 1
- ..\libraries\m480\rtt_port\drv_hsotg.c
-
-
-
-
- drv_softi2c.c
- 1
- ..\libraries\m480\rtt_port\drv_softi2c.c
-
-
-
-
- drv_can.c
- 1
- ..\libraries\m480\rtt_port\drv_can.c
-
-
-
-
- drv_timer.c
- 1
- ..\libraries\m480\rtt_port\drv_timer.c
-
-
-
-
- drv_i2s.c
- 1
- ..\libraries\m480\rtt_port\drv_i2s.c
-
-
-
-
- drv_scuart.c
- 1
- ..\libraries\m480\rtt_port\drv_scuart.c
-
-
-
-
- drv_qspi.c
- 1
- ..\libraries\m480\rtt_port\drv_qspi.c
-
-
-
-
- drv_wdt.c
- 1
- ..\libraries\m480\rtt_port\drv_wdt.c
-
-
-
-
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- 1
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diff --git a/bsp/nuvoton/numaker-pfm-m487/project.uvprojx b/bsp/nuvoton/numaker-pfm-m487/project.uvprojx
deleted file mode 100644
index 0050c2f13a..0000000000
--- a/bsp/nuvoton/numaker-pfm-m487/project.uvprojx
+++ /dev/null
@@ -1,1961 +0,0 @@
-
-
- 2.1
- ### uVision Project, (C) Keil Software
-
-
- rtthread-m480
- 0x4
- ARM-ADS
- 0
-
-
- M487JIDAE
- Nuvoton
- Nuvoton.NuMicro_DFP.1.3.5
- http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
- IRAM(0x20000000,0x28000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)
-
-
- UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M481_AP_512 -FS00 -FL080000 -FP0($$Device:M487JIDAE$Flash\M481_AP_512.FLM))
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- SARMCM3.DLL
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- 16
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- "" ()
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- --c99
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- tcpip.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\api\tcpip.c
-
-
-
-
- ip4_addr.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c
-
-
-
-
- dhcp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c
-
-
-
-
- init.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\init.c
-
-
-
-
- ethernetif.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c
-
-
-
-
- etharp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c
-
-
-
-
- memp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\memp.c
-
-
-
-
- ip4.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c
-
-
-
-
- netbuf.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\api\netbuf.c
-
-
-
-
- raw.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\raw.c
-
-
-
-
- ping.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\apps\ping\ping.c
-
-
-
-
- ip4_frag.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c
-
-
-
-
- tcp_out.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\tcp_out.c
-
-
-
-
- lowpan6.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c
-
-
-
-
- icmp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c
-
-
-
-
- api_lib.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\api\api_lib.c
-
-
-
-
- inet_chksum.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c
-
-
-
-
- stats.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\stats.c
-
-
-
-
- err.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\api\err.c
-
-
-
-
- tcp_in.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\tcp_in.c
-
-
-
-
- dns.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\dns.c
-
-
-
-
- sys_arch.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c
-
-
-
-
- timeouts.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\timeouts.c
-
-
-
-
- igmp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c
-
-
-
-
- udp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\udp.c
-
-
-
-
- pbuf.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\pbuf.c
-
-
-
-
- def.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\def.c
-
-
-
-
- api_msg.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\api\api_msg.c
-
-
-
-
- tcp.c
- 1
- ..\..\..\components\net\lwip-2.0.2\src\core\tcp.c
-
-
-
-
- m480_usbhostlib
-
-
- mem_alloc.c
- 1
- ..\libraries\m480\USBHostLib\src\mem_alloc.c
-
-
-
-
- ehci.c
- 1
- ..\libraries\m480\USBHostLib\src\ehci.c
-
-
-
-
- usb_core.c
- 1
- ..\libraries\m480\USBHostLib\src\usb_core.c
-
-
-
-
- ohci.c
- 1
- ..\libraries\m480\USBHostLib\src\ohci.c
-
-
-
-
- ehci_iso.c
- 1
- ..\libraries\m480\USBHostLib\src\ehci_iso.c
-
-
-
-
- nu_pkgs_demo
-
-
- usbd_cdc_vcom_echo.c
- 1
- ..\libraries\nu_packages\Demo\usbd_cdc_vcom_echo.c
-
-
-
-
- slcd_show_tick.c
- 1
- ..\libraries\nu_packages\Demo\slcd_show_tick.c
-
-
-
-
- usbd_hid_dance_mouse.c
- 1
- ..\libraries\nu_packages\Demo\usbd_hid_dance_mouse.c
-
-
-
-
- nu_pkgs_nau88l25
-
-
- audio_test.c
- 1
- ..\libraries\nu_packages\AudioCodec\audio_test.c
-
-
-
-
- acodec_nau88l25.c
- 1
- ..\libraries\nu_packages\AudioCodec\acodec_nau88l25.c
-
-
-
-
- rt_usbd
-
-
- usbdevice_core.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c
-
-
-
-
- usbdevice.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c
-
-
-
-
- hid.c
- 1
- ..\..\..\components\drivers\usb\usbdevice\class\hid.c
-
-
-
-
- rt_usbh
-
-
- mass.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\mass.c
-
-
-
-
- hub.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\hub.c
-
-
-
-
- usbhost.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost.c
-
-
-
-
- udisk.c
- 1
- ..\..\..\components\drivers\usb\usbhost\class\udisk.c
-
-
-
-
- usbhost_core.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c
-
-
-
-
- driver.c
- 1
- ..\..\..\components\drivers\usb\usbhost\core\driver.c
-
-
-
-
- SAL
-
-
- netdev_ipaddr.c
- 1
- ..\..\..\components\net\netdev\src\netdev_ipaddr.c
-
-
-
-
- netdev.c
- 1
- ..\..\..\components\net\netdev\src\netdev.c
-
-
-
-
- net_netdb.c
- 1
- ..\..\..\components\net\sal_socket\socket\net_netdb.c
-
-
-
-
- sal_socket.c
- 1
- ..\..\..\components\net\sal_socket\src\sal_socket.c
-
-
-
-
- af_inet_lwip.c
- 1
- ..\..\..\components\net\sal_socket\impl\af_inet_lwip.c
-
-
-
-
- UTest
-
-
- utest.c
- 1
- ..\..\..\components\utilities\utest\utest.c
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/nuvoton/numaker-pfm-m487/rtconfig.h b/bsp/nuvoton/numaker-pfm-m487/rtconfig.h
deleted file mode 100644
index 4f9e169ee4..0000000000
--- a/bsp/nuvoton/numaker-pfm-m487/rtconfig.h
+++ /dev/null
@@ -1,413 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 8
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_HOOK_USING_FUNC_PTR
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 1024
-
-/* kservice optimization */
-
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-#define RT_USING_SIGNALS
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 256
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40100
-#define ARCH_ARM
-#define RT_USING_CPU_FFS
-#define ARCH_ARM_CORTEX_M
-#define ARCH_ARM_CORTEX_M4
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define RT_USING_MSH
-#define FINSH_USING_MSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 2048
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_CMD_SIZE 80
-#define MSH_USING_BUILT_IN_COMMANDS
-#define FINSH_USING_DESCRIPTION
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 8
-#define DFS_FILESYSTEM_TYPES_MAX 4
-#define DFS_FD_MAX 32
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_3
-#define RT_DFS_ELM_USE_LFN 3
-#define RT_DFS_ELM_LFN_UNICODE_0
-#define RT_DFS_ELM_LFN_UNICODE 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 8
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SYSTEM_WORKQUEUE
-#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
-#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
-#define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
-#define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 128
-#define RT_USING_CAN
-#define RT_USING_HWTIMER
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_PM
-#define PM_TICKLESS_THRESHOLD_TIME 2
-#define RT_USING_RTC
-#define RT_USING_SPI
-#define RT_USING_QSPI
-#define RT_USING_SFUD
-#define RT_SFUD_USING_SFDP
-#define RT_SFUD_USING_FLASH_INFO_TABLE
-#define RT_SFUD_SPI_MAX_HZ 50000000
-#define RT_USING_WDT
-#define RT_USING_AUDIO
-#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
-#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
-#define RT_AUDIO_RECORD_PIPE_SIZE 2048
-#define RT_USING_HWCRYPTO
-#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
-#define RT_HWCRYPTO_IV_MAX_SIZE 16
-#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
-#define RT_HWCRYPTO_USING_AES
-#define RT_HWCRYPTO_USING_AES_ECB
-#define RT_HWCRYPTO_USING_AES_CBC
-#define RT_HWCRYPTO_USING_AES_CFB
-#define RT_HWCRYPTO_USING_AES_CTR
-#define RT_HWCRYPTO_USING_AES_OFB
-#define RT_HWCRYPTO_USING_DES
-#define RT_HWCRYPTO_USING_DES_ECB
-#define RT_HWCRYPTO_USING_DES_CBC
-#define RT_HWCRYPTO_USING_3DES
-#define RT_HWCRYPTO_USING_3DES_ECB
-#define RT_HWCRYPTO_USING_3DES_CBC
-#define RT_HWCRYPTO_USING_SHA1
-#define RT_HWCRYPTO_USING_SHA2
-#define RT_HWCRYPTO_USING_SHA2_224
-#define RT_HWCRYPTO_USING_SHA2_256
-#define RT_HWCRYPTO_USING_SHA2_384
-#define RT_HWCRYPTO_USING_SHA2_512
-#define RT_HWCRYPTO_USING_RNG
-#define RT_HWCRYPTO_USING_CRC
-#define RT_HWCRYPTO_USING_CRC_07
-#define RT_HWCRYPTO_USING_CRC_8005
-#define RT_HWCRYPTO_USING_CRC_1021
-#define RT_HWCRYPTO_USING_CRC_04C11DB7
-
-/* Using USB */
-
-#define RT_USING_USB
-#define RT_USING_USB_HOST
-#define RT_USBH_MSTORAGE
-#define UDISK_MOUNTPOINT "/mnt/udisk/"
-#define RT_USING_USB_DEVICE
-#define RT_USBD_THREAD_STACK_SZ 4096
-#define USB_VENDOR_ID 0x0FFE
-#define USB_PRODUCT_ID 0x0001
-#define _RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID
-#define RT_USB_DEVICE_HID_MOUSE
-
-/* POSIX layer and C standard library */
-
-#define RT_LIBC_DEFAULT_TIMEZONE 8
-
-/* POSIX (Portable Operating System Interface) layer */
-
-#define RT_USING_POSIX_FS
-#define RT_USING_POSIX_DEVIO
-
-/* Interprocess Communication (IPC) */
-
-
-/* Socket is in the 'Network' category */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-#define RT_USING_SAL
-#define SAL_INTERNET_CHECK
-
-/* protocol stack implement */
-
-#define SAL_USING_LWIP
-#define SAL_SOCKETS_NUM 16
-
-/* Network interface device */
-
-#define RT_USING_NETDEV
-#define NETDEV_USING_IFCONFIG
-#define NETDEV_USING_PING
-#define NETDEV_USING_NETSTAT
-#define NETDEV_USING_AUTO_DEFAULT
-#define NETDEV_IPV4 1
-#define NETDEV_IPV6 0
-
-/* light weight TCP/IP stack */
-
-#define RT_USING_LWIP
-#define RT_USING_LWIP202
-#define RT_LWIP_MEM_ALIGNMENT 4
-#define RT_LWIP_IGMP
-#define RT_LWIP_ICMP
-#define RT_LWIP_DNS
-#define RT_LWIP_DHCP
-#define IP_SOF_BROADCAST 1
-#define IP_SOF_BROADCAST_RECV 1
-
-/* Static IPv4 Address */
-
-#define RT_LWIP_IPADDR "192.168.1.30"
-#define RT_LWIP_GWADDR "192.168.1.1"
-#define RT_LWIP_MSKADDR "255.255.255.0"
-#define RT_LWIP_UDP
-#define RT_LWIP_TCP
-#define RT_LWIP_RAW
-#define RT_MEMP_NUM_NETCONN 8
-#define RT_LWIP_PBUF_NUM 16
-#define RT_LWIP_RAW_PCB_NUM 4
-#define RT_LWIP_UDP_PCB_NUM 4
-#define RT_LWIP_TCP_PCB_NUM 4
-#define RT_LWIP_TCP_SEG_NUM 40
-#define RT_LWIP_TCP_SND_BUF 8196
-#define RT_LWIP_TCP_WND 8196
-#define RT_LWIP_TCPTHREAD_PRIORITY 10
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
-#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
-#define RT_LWIP_ETHTHREAD_PRIORITY 12
-#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
-#define LWIP_NETIF_STATUS_CALLBACK 1
-#define LWIP_NETIF_LINK_CALLBACK 1
-#define SO_REUSE 1
-#define LWIP_SO_RCVTIMEO 1
-#define LWIP_SO_SNDTIMEO 1
-#define LWIP_SO_RCVBUF 1
-#define LWIP_SO_LINGER 0
-#define LWIP_NETIF_LOOPBACK 0
-#define RT_LWIP_USING_PING
-
-/* AT commands */
-
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-#define RT_USING_UTEST
-#define UTEST_THR_STACK_SIZE 4096
-#define UTEST_THR_PRIORITY 20
-
-/* RT-Thread Utestcases */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-/* LVGL: powerful and easy-to-use embedded GUI library */
-
-
-/* u8g2: a monochrome graphic library */
-
-
-/* PainterEngine: A cross-platform graphics application framework written in C language */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-/* enhanced kernel services */
-
-
-/* POSIX extension functions */
-
-
-/* acceleration: Assembly language or algorithmic acceleration packages */
-
-
-/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
-
-
-/* Micrium: Micrium software products porting for RT-Thread */
-
-#define PKG_USING_FAL
-#define FAL_DEBUG_CONFIG
-#define FAL_DEBUG 1
-#define FAL_PART_HAS_TABLE_CFG
-#define PKG_USING_FAL_V00400
-#define PKG_FAL_VER_NUM 0x00400
-
-/* peripheral libraries and drivers */
-
-
-/* AI packages */
-
-
-/* miscellaneous packages */
-
-/* samples: kernel and components samples */
-
-
-/* entertainment: terminal games and other interesting software packages */
-
-
-/* Nuvoton Packages Config */
-
-#define NU_PKG_USING_UTILS
-#define NU_PKG_USING_DEMO
-#define NU_PKG_USING_NAU88L25
-
-/* Hardware Drivers Config */
-
-/* On-chip Peripheral Drivers */
-
-#define SOC_SERIES_M480
-#define BSP_USE_STDDRIVER_SOURCE
-#define BSP_USING_PDMA
-#define NU_PDMA_MEMFUN_ACTOR_MAX 2
-#define NU_PDMA_SGTBL_POOL_SIZE 16
-#define BSP_USING_FMC
-#define BSP_USING_GPIO
-#define BSP_USING_CLK
-#define NU_CLK_INVOKE_WKTMR
-#define BSP_USING_EMAC
-#define NU_EMAC_PDMA_MEMCOPY
-#define NU_EMAC_PDMA_MEMCOPY_THRESHOLD 128
-#define BSP_USING_RTC
-#define NU_RTC_SUPPORT_MSH_CMD
-#define BSP_USING_TMR
-#define BSP_USING_UART
-#define BSP_USING_UART0
-#define BSP_USING_I2C
-#define BSP_USING_I2C1
-#define BSP_USING_I2C2
-#define BSP_USING_SDH
-#define BSP_USING_SDH0
-#define NU_SDH_USING_PDMA
-#define NU_SDH_HOTPLUG
-#define BSP_USING_SPI
-#define BSP_USING_SPI_PDMA
-#define BSP_USING_SPI0_NONE
-#define BSP_USING_SPI1_NONE
-#define BSP_USING_SPI2_NONE
-#define BSP_USING_SPI3
-#define BSP_USING_I2S
-#define NU_I2S_DMA_FIFO_SIZE 2048
-#define BSP_USING_QSPI
-#define BSP_USING_QSPI0
-#define BSP_USING_QSPI0_PDMA
-#define BSP_USING_CRYPTO
-#define BSP_USING_TRNG
-#define BSP_USING_CRC
-#define NU_CRC_USE_PDMA
-#define BSP_USING_WDT
-#define BSP_USING_USBD
-#define BSP_USING_HSUSBH
-#define NU_USBHOST_HUB_POLLING_INTERVAL 100
-
-/* On-board Peripheral Drivers */
-
-#define BSP_USING_NULINKME
-#define BOARD_USING_IP101GR
-#define BOARD_USING_NAU88L25
-#define BOARD_USING_STORAGE_SDCARD
-#define BOARD_USING_STORAGE_SPIFLASH
-#define BOARD_USING_HSUSBH_USBD
-
-/* Board extended module drivers */
-
-
-#endif
diff --git a/bsp/nuvoton/numaker-pfm-m487/rtconfig.py b/bsp/nuvoton/numaker-pfm-m487/rtconfig.py
index 902a2bdce9..7beeafe88a 100644
--- a/bsp/nuvoton/numaker-pfm-m487/rtconfig.py
+++ b/bsp/nuvoton/numaker-pfm-m487/rtconfig.py
@@ -130,3 +130,11 @@ elif PLATFORM == 'iar':
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = ''
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
+
diff --git a/bsp/nuvoton/tools/sdk_dist.py b/bsp/nuvoton/tools/sdk_dist.py
new file mode 100644
index 0000000000..d76f7fcfc8
--- /dev/null
+++ b/bsp/nuvoton/tools/sdk_dist.py
@@ -0,0 +1,39 @@
+import os
+import sys
+import shutil
+cwd_path = os.getcwd()
+sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
+
+def dist_modify_relative_path(board_kconfig_path):
+ # Read in the file
+ with open(board_kconfig_path, 'r') as file :
+ filedata = file.read()
+
+ # Replace the target string
+ filedata = filedata.replace('$BSP_DIR/../libraries', './libraries')
+
+ # Write the file out again
+ with open(board_kconfig_path, 'w') as file:
+ file.write(filedata)
+
+# BSP dist function
+def dist_do_building(BSP_ROOT, dist_dir):
+ from mkdist import bsp_copy_files
+ import rtconfig
+
+ library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
+ library_dir = os.path.join(dist_dir, 'libraries')
+
+ print('=> copy nuvoton bsp drivers')
+ bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE),
+ os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
+
+ print('=> copy nu_packages')
+ bsp_copy_files(os.path.join(library_path, 'nu_packages'),
+ os.path.join(library_dir, 'nu_packages'))
+
+ print('=> copy Kconfig')
+ shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
+
+ print('=> Modify libraries relative path in board/Kconfig ')
+ dist_modify_relative_path(os.path.join(dist_dir, 'board', 'Kconfig'))
\ No newline at end of file
diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config
index 1823424c79..f20d37057e 100644
--- a/bsp/qemu-vexpress-a9/.config
+++ b/bsp/qemu-vexpress-a9/.config
@@ -299,9 +299,8 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-# CONFIG_RT_USING_LWIP202 is not set
-# CONFIG_RT_USING_LWIP203 is not set
-CONFIG_RT_USING_LWIP212=y
+CONFIG_RT_USING_LWIP203=y
+# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
# CONFIG_RT_LWIP_IGMP is not set
@@ -532,6 +531,7 @@ CONFIG_RT_USING_LWP=y
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -542,7 +542,6 @@ CONFIG_RT_USING_LWP=y
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -593,6 +592,7 @@ CONFIG_RT_USING_LWP=y
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -705,6 +705,7 @@ CONFIG_RT_USING_LWP=y
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -792,6 +793,8 @@ CONFIG_RT_USING_LWP=y
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
diff --git a/bsp/qemu-vexpress-a9/applications/main.c b/bsp/qemu-vexpress-a9/applications/main.c
index e8ef51657e..b9364eee2f 100644
--- a/bsp/qemu-vexpress-a9/applications/main.c
+++ b/bsp/qemu-vexpress-a9/applications/main.c
@@ -14,7 +14,7 @@
int main(void)
{
- printf("hello rt-thread\n");
+ printf("Hello RT-Thread!\n");
return 0;
}
diff --git a/bsp/qemu-vexpress-a9/drivers/drv_clcd.c b/bsp/qemu-vexpress-a9/drivers/drv_clcd.c
index 2d012dca84..3fe2bd58d3 100644
--- a/bsp/qemu-vexpress-a9/drivers/drv_clcd.c
+++ b/bsp/qemu-vexpress-a9/drivers/drv_clcd.c
@@ -75,13 +75,15 @@ static rt_err_t drv_clcd_control(struct rt_device *device, int cmd, void *args)
RT_ASSERT(info != RT_NULL);
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
- // info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888;
info->bits_per_pixel= 16;
info->width = lcd->width;
info->height = lcd->height;
info->framebuffer = lcd->fb;
}
break;
+
+ default:
+ return -RT_EINVAL;
}
return RT_EOK;
@@ -109,7 +111,7 @@ int drv_clcd_hw_init(void)
_lcd.width = CLCD_WIDTH;
_lcd.height = CLCD_HEIGHT;
- _lcd.fb = rt_malloc(_lcd.width * _lcd.height * 2);
+ _lcd.fb = rt_malloc(_lcd.width * _lcd.height * 2 /*RGB565 2 Bytes*/);
if (_lcd.fb == NULL)
{
rt_kprintf("initialize frame buffer failed!\n");
diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h
index 5957f7c565..35238f926c 100644
--- a/bsp/qemu-vexpress-a9/rtconfig.h
+++ b/bsp/qemu-vexpress-a9/rtconfig.h
@@ -203,7 +203,7 @@
/* light weight TCP/IP stack */
#define RT_USING_LWIP
-#define RT_USING_LWIP212
+#define RT_USING_LWIP203
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config
index 82e6d9493e..133327fe51 100644
--- a/bsp/raspberry-pi/raspi4-32/.config
+++ b/bsp/raspberry-pi/raspi4-32/.config
@@ -282,8 +282,7 @@ CONFIG_NETDEV_IPV6=0
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
@@ -514,6 +513,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
@@ -524,7 +524,6 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
@@ -575,6 +574,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
@@ -686,6 +686,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
@@ -773,6 +774,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
CONFIG_BCM2711_SOC=y
# CONFIG_BSP_SUPPORT_FPU is not set
diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h
index aeeb1f12f8..ed2adcbb38 100644
--- a/bsp/raspberry-pi/raspi4-32/rtconfig.h
+++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h
@@ -168,7 +168,7 @@
/* light weight TCP/IP stack */
#define RT_USING_LWIP
-#define RT_USING_LWIP202
+#define RT_USING_LWIP203
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
diff --git a/bsp/rx/applications/application.c b/bsp/rx/applications/application.c
index 77bbbfd301..0d8043de91 100644
--- a/bsp/rx/applications/application.c
+++ b/bsp/rx/applications/application.c
@@ -119,7 +119,7 @@ void rt_init_thread_entry(void* parameter)
#endif
#ifdef RT_USING_USB_HOST
- rt_usb_host_init();
+ rt_usb_host_init("usbh");
#endif
#ifdef RT_USING_FINSH
diff --git a/bsp/simulator/drivers/module_win32.c b/bsp/simulator/drivers/module_win32.c
index 81a98eca87..0f07576964 100644
--- a/bsp/simulator/drivers/module_win32.c
+++ b/bsp/simulator/drivers/module_win32.c
@@ -193,7 +193,11 @@ RTM_EXPORT(rt_module_find);
#ifdef RT_USING_DFS
#include
-#include
+#include
+#include
+#include
+#include
+#include
extern char * dfs_win32_dirdup(char * path);
static char* _module_name(const char *path)
{
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
index 96c61835e6..a0db14fc1a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
@@ -90,6 +90,9 @@ static rt_err_t drv_lcd_control(struct rt_device *device, int cmd, void *args)
info->framebuffer = lcd->lcd_info.framebuffer;
}
break;
+
+ default:
+ return -RT_EINVAL;
}
return RT_EOK;
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
index 275a18e925..e3bb847c5c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
@@ -23,7 +23,7 @@ struct stm32_lcd
struct rt_device parent;
struct rt_device_graphic_info info;
};
-static struct stm32_lcd lcd;
+struct stm32_lcd lcd;
extern void stm32_mipi_lcd_init(void);
extern void stm32_mipi_lcd_config(rt_uint32_t pixel_format);
@@ -76,7 +76,7 @@ rt_err_t ltdc_init(void)
HAL_DSI_Init(&hdsi, &dsi_pll);
hdsi_video.VirtualChannelID = 0;
- hdsi_video.ColorCoding = DSI_RGB888;
+ hdsi_video.ColorCoding = DSI_RGB565;
hdsi_video.VSPolarity = DSI_VSYNC_ACTIVE_HIGH;
hdsi_video.HSPolarity = DSI_HSYNC_ACTIVE_HIGH;
hdsi_video.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH;
@@ -130,7 +130,7 @@ rt_err_t ltdc_init(void)
HAL_DSI_Start(&(hdsi));
- stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_ARGB888);
+ stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_RGB565);
return RT_EOK;
}
@@ -143,7 +143,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
layer_cfg.WindowX1 = LCD_WIDTH;
layer_cfg.WindowY0 = 0;
layer_cfg.WindowY1 = LCD_HEIGHT;
- layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
+ layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
layer_cfg.Alpha = 255;
@@ -169,9 +169,9 @@ static rt_err_t stm32_lcd_init(rt_device_t device)
{
lcd.info.width = LCD_WIDTH;
lcd.info.height = LCD_HEIGHT;
- lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888;
- lcd.info.bits_per_pixel = 32;
- lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);
+ lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
+ lcd.info.bits_per_pixel = 16;
+ lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);;
memset(lcd.info.framebuffer, 0, LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8));
ltdc_init();
ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer);
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
index 7807e0c010..6211676056 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
@@ -918,6 +918,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (RT_DEVICE_FLAG_DMA_RX == flag)
@@ -925,7 +926,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
DMA_Handle = &uart->dma_rx.handle;
dma_config = uart->config->dma_rx;
}
- else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ else /* RT_DEVICE_FLAG_DMA_TX == flag */
{
DMA_Handle = &uart->dma_tx.handle;
dma_config = uart->config->dma_tx;
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c
index 038129beef..95635fe37b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c
@@ -959,6 +959,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (RT_DEVICE_FLAG_DMA_RX == flag)
@@ -966,7 +967,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
DMA_Handle = &uart->dma_rx.handle;
dma_config = uart->config->dma_rx;
}
- else if (RT_DEVICE_FLAG_DMA_TX == flag)
+ else /* RT_DEVICE_FLAG_DMA_TX == flag */
{
DMA_Handle = &uart->dma_tx.handle;
dma_config = uart->config->dma_tx;
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
index 9486e1a56d..1f169d2e6b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
@@ -247,7 +247,7 @@ int stm_usbh_register(void)
return -RT_ERROR;
}
- rt_usb_host_init();
+ rt_usb_host_init("usbh");
return RT_EOK;
}
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
index d56fb039d4..df2614c080 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
@@ -14,7 +14,11 @@
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
index 13d235b694..d717da27dd 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
@@ -14,7 +14,11 @@
#if defined BSP_USING_SDIO_SDCARD || defined BSP_USING_SPI_SDCARD
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#include "drv_gpio.h"
#define DBG_TAG "app.card"
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
index 55baa2c263..c0575f01b2 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
@@ -14,7 +14,11 @@
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c
index f5427ef265..2b6e48ba3f 100644
--- a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c
@@ -14,7 +14,11 @@
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
index 2684672d54..7fcdba54c8 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
+++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
@@ -438,6 +438,7 @@ menu "Board extended module Drivers"
select PKG_USING_AT_DEVICE
select AT_DEVICE_USING_ESP8266
select AT_DEVICE_ESP8266_SAMPLE
+ select AT_DEVICE_ESP8266_SAMPLE_BSP_TAKEOVER
if BSP_USING_AT_ESP8266
@@ -457,6 +458,8 @@ menu "Board extended module Drivers"
int "The maximum length of receive line buffer"
default 512
+ comment "May adjust RT_SERIAL_RB_BUFSZ up to 512 if using the Serial V1 device driver"
+
endif
endmenu
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c
index 6635c43128..cafb45b107 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_filesystem.c
@@ -15,7 +15,11 @@
#ifdef BSP_USING_FS
#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
#if DFS_FILESYSTEMS_MAX < 4
#error "Please define DFS_FILESYSTEMS_MAX more than 4"
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
index 6a79c83523..376089ef9e 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
@@ -14,7 +14,11 @@
#include
#include
-#include