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bsp/stm32:Separate STM32H7 HAL drivers (#10204)
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@@ -68,6 +68,7 @@ config SOC_SERIES_STM32H7
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bool
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bool
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select ARCH_ARM_CORTEX_M7
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select ARCH_ARM_CORTEX_M7
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select SOC_FAMILY_STM32
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select SOC_FAMILY_STM32
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select PKG_USING_STM32H7_HAL_DRIVER
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config SOC_SERIES_STM32U5
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config SOC_SERIES_STM32U5
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bool
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bool
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@@ -1,301 +0,0 @@
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/**
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******************************************************************************
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* @file stm32h7xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32H7xx device used in the target application
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* - To use or not the peripheral's drivers in application code(i.e.
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* code will be based on direct access to peripheral's registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32h7xx
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* @{
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*/
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#ifndef STM32H7xx_H
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#define STM32H7xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32H7)
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#define STM32H7
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#endif /* STM32H7 */
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/* Uncomment the line below according to the target STM32H7 device used in your
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application
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*/
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#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
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!defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
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!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
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!defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
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/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
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/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
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/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
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/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
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/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
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/* #define STM32H747xG */ /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */
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/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
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/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
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/* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */
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/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
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/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
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/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
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/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
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/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
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/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
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/* #define STM32H735xx */ /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */
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/* #define STM32H733xx */ /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */
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/* #define STM32H730xx */ /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */
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/* #define STM32H730xxQ */ /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */
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/* #define STM32H725xx */ /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices */
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/* #define STM32H723xx */ /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
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#error "Dual core device, please select CORE_CM4 or CORE_CM7"
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#endif
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V1.10.4
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*/
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
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|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
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|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
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|(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32H743xx)
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#include "stm32h743xx.h"
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#elif defined(STM32H753xx)
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#include "stm32h753xx.h"
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#elif defined(STM32H750xx)
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#include "stm32h750xx.h"
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#elif defined(STM32H742xx)
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#include "stm32h742xx.h"
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#elif defined(STM32H745xx)
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#include "stm32h745xx.h"
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#elif defined(STM32H745xG)
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#include "stm32h745xg.h"
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#elif defined(STM32H755xx)
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#include "stm32h755xx.h"
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#elif defined(STM32H747xx)
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#include "stm32h747xx.h"
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#elif defined(STM32H747xG)
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#include "stm32h747xg.h"
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#elif defined(STM32H757xx)
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#include "stm32h757xx.h"
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#elif defined(STM32H7B0xx)
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#include "stm32h7b0xx.h"
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#elif defined(STM32H7B0xxQ)
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#include "stm32h7b0xxq.h"
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#elif defined(STM32H7A3xx)
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#include "stm32h7a3xx.h"
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#elif defined(STM32H7B3xx)
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#include "stm32h7b3xx.h"
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#elif defined(STM32H7A3xxQ)
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#include "stm32h7a3xxq.h"
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#elif defined(STM32H7B3xxQ)
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#include "stm32h7b3xxq.h"
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#elif defined(STM32H735xx)
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#include "stm32h735xx.h"
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#elif defined(STM32H733xx)
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#include "stm32h733xx.h"
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#elif defined(STM32H730xx)
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#include "stm32h730xx.h"
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#elif defined(STM32H730xxQ)
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#include "stm32h730xxq.h"
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#elif defined(STM32H725xx)
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#include "stm32h725xx.h"
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#elif defined(STM32H723xx)
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#include "stm32h723xx.h"
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#else
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#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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SUCCESS = 0,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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/* Use of CMSIS compiler intrinsics for register exclusive access */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t val; \
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do { \
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val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint16_t val; \
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do { \
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val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/**
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* @}
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*/
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#if defined (USE_HAL_DRIVER)
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#include "stm32h7xx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* STM32H7xx_H */
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/**
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* @}
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*/
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|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -1,103 +0,0 @@
|
|||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file system_stm32h7xx.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2017 STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CMSIS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup stm32h7xx_system
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Define to prevent recursive inclusion
|
|
||||||
*/
|
|
||||||
#ifndef SYSTEM_STM32H7XX_H
|
|
||||||
#define SYSTEM_STM32H7XX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @addtogroup STM32H7xx_System_Includes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup STM32H7xx_System_Exported_types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* This variable is updated in three ways:
|
|
||||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
|
||||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
|
||||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
|
||||||
Note: If you use this function to configure the system clock; then there
|
|
||||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
|
||||||
variable is updated automatically.
|
|
||||||
*/
|
|
||||||
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
|
|
||||||
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
|
|
||||||
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32H7xx_System_Exported_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32H7xx_System_Exported_Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32H7xx_System_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
extern void SystemInit(void);
|
|
||||||
extern void SystemCoreClockUpdate(void);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* SYSTEM_STM32H7XX_H */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
@@ -1,411 +0,0 @@
|
|||||||
<!DOCTYPE html>
|
|
||||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
|
||||||
<head>
|
|
||||||
<meta charset="utf-8" />
|
|
||||||
<meta name="generator" content="pandoc" />
|
|
||||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
|
||||||
<title>Release Notes for STM32H7xx CMSIS</title>
|
|
||||||
<style type="text/css">
|
|
||||||
code{white-space: pre-wrap;}
|
|
||||||
span.smallcaps{font-variant: small-caps;}
|
|
||||||
span.underline{text-decoration: underline;}
|
|
||||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
|
||||||
</style>
|
|
||||||
<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
|
|
||||||
<!--[if lt IE 9]>
|
|
||||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
|
||||||
<![endif]-->
|
|
||||||
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
|
||||||
</head>
|
|
||||||
<body>
|
|
||||||
<div class="row">
|
|
||||||
<div class="col-sm-12 col-lg-4">
|
|
||||||
<center>
|
|
||||||
<h1 id="release-notes-for-stm32h7xx-cmsis">Release Notes for <mark> STM32H7xx CMSIS </mark></h1>
|
|
||||||
<p>Copyright © 2017 STMicroelectronics<br />
|
|
||||||
</p>
|
|
||||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
|
||||||
</center>
|
|
||||||
</div>
|
|
||||||
<div class="col-sm-12 col-lg-8">
|
|
||||||
<h1 id="update-history"><strong>Update History</strong></h1>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section16" checked aria-hidden="true"> <label for="collapse-section16" aria-hidden="true"><strong>V1.10.4 / 15-March-2024</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Update the values of the sensor calibration temperatures for H742, H743, and H753 part numbers.</li>
|
|
||||||
<li>Remove the unsupported MDMA BASE channel.</li>
|
|
||||||
<li>Align CMSIS with IP spec and product reference manual by adding missing bit fields definition.</li>
|
|
||||||
<li>Update STM32CubeIDE projects to fix the location of .size directive in startup code to allow proper size information of vector table.</li>
|
|
||||||
<li>Update the Cortex-M7 core revision.</li>
|
|
||||||
<li>Set FMC_SDCMR_MODE_2 bit field definition to 0x4.</li>
|
|
||||||
<li>Update to support I2S feature on SPI6 instance available on STM32H723xx, STM32H725xx, STM32H730xx, STM32H730xxQ, STM32H733xx and STM32H735xx devices.</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.10.3 / 23-September-2022</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-1">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>General updates to fix known defects and implementation enhancements</li>
|
|
||||||
<li>Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.</li>
|
|
||||||
<li>Adjust QUADSPI FIFO level threshold bits mask definition on 5 bits instead of 4bits.</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-2">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>General updates to fix known defects and implementation enhancements</li>
|
|
||||||
<li>Add support for ADC LDO output voltage ready bit.</li>
|
|
||||||
<li>Remove useless OCTOSPI_DCR1_CKCSHT definition: alignment with the reference manual</li>
|
|
||||||
<li>All system_stm32h7xx.c template files
|
|
||||||
<ul>
|
|
||||||
<li>Update VTOR configuration to be modified by user</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-3">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>General updates to fix known defects and implementation enhancements</li>
|
|
||||||
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
|
|
||||||
<li>New CMSIS header files added for STM32H747xG and STM32H7575xG.</li>
|
|
||||||
<li>Added new atomic register access macros in stm32h7xx.h file.</li>
|
|
||||||
<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
|
|
||||||
<li>FLASH_SIZE incorrectly defined for CM4 for STM32H747xG and STM32H757xG.</li>
|
|
||||||
<li>Add missing bit definition for HRTIM TimerB/C/D/E Reset Register.</li>
|
|
||||||
<li>Fix wrong TIM_CR2_OIS6_Pos bit position.</li>
|
|
||||||
<li>Add check on TIM15 within IS_TIM_SLAVE_INSTANCE() macro.</li>
|
|
||||||
<li>Add check on TIM12 within IS_TIM_CLOCKSOURCE_TIX_INSTANCE() and IS_TIM_CLOCKSOURCE_ITRX_INSTANCE() macros as it supports external clock mode 1 for TIX inputs and internal trigger inputs.</li>
|
|
||||||
<li>Fix TIM_CCMR2_OC3M_Msk, TIM_CCMR2_OC4M_Msk, TIM_CCMR3_OC5M_Msk and TIM_CCMR3_OC6M_Msk incorrect definitions.
|
|
||||||
<ul>
|
|
||||||
<li>FLASH_ACR_LATENCY_Msk corrected to be 3 bits instead of 4 bits.</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>system_stm32h7xx.c
|
|
||||||
<ul>
|
|
||||||
<li>Update VTOR configuration to be modified by user</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-4">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Fix minor issues related to English typo in comments of registers and fields description</li>
|
|
||||||
<li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li>
|
|
||||||
<li>Update “FLASH_SIZE” define in STM32H7 devices header files to retrieve the flash size from the dedicated FLASH_SIZE_DATA_REGISTER register</li>
|
|
||||||
<li>Update “IS_TIM_MASTER_INSTANCE” define in STM32H7 devices header files to consider TIM12 that can be a master timer</li>
|
|
||||||
<li>Remove extra fields defines related to Domain D3 in DBGMCU_CR_DBG register</li>
|
|
||||||
<li>Remove “FLASH_OPTCR_SWAP_BANK” and “FLASH_OPTSR_SWAP_BANK_OPT” field definitions from STM32H750xx device header file (that is a value line single bank device)</li>
|
|
||||||
<li>Fix "__STM32H7xx_CMSIS_DEVICE_VERSION" definition in stm32h7xx.h file by referring to the right “STM32H7xx_CMSIS_DEVICE” defines</li>
|
|
||||||
<li>Update “SystemCoreClockUpdate” function implementation in system_stm32h7xx.c files with default system_clock and PLL source set to HIS instead of CSI (as per the product specification)</li>
|
|
||||||
<li>Update and improve GCC startup files to reduce the number of loads inside of the .data copy</li>
|
|
||||||
<li>Update MDK-ARM template scatter files for dual core devices to fix a typo within the IRAM1 section</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-5">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
|
|
||||||
<ul>
|
|
||||||
<li>Add “stm32h723xx.h” , “stm32h725xx.h”, “stm32h733xx.h”, “stm32h735xx.h”, “stm32h730xx.h” and “stm32h730xxq.h” files</li>
|
|
||||||
<li>Add startup files “startup_stm32h723xx.s”, “startup_stm32h725xx.s”, “startup_stm32h733xx.s”, “startup_stm32h735xx.s”, “startup_stm32h730xx.s” and “startup_stm32h730xxq.s” for EWARM , MDK-ARM and GCC toolchains</li>
|
|
||||||
<li>Add part numbers list to stm32h7xx.h header file:
|
|
||||||
<ul>
|
|
||||||
<li>STM32H723xx: STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices</li>
|
|
||||||
<li>STM32H725xx: STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices</li>
|
|
||||||
<li>STM32H733xx: STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices</li>
|
|
||||||
<li>STM32H735xx: STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices</li>
|
|
||||||
<li>STM32H730xx: STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices</li>
|
|
||||||
<li><p>STM32H730xxQ: STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices</p></li>
|
|
||||||
<li>Add EWARM STM32H723xx, STM32H725xx, STM32H733xx, STM32H735xx, STM32H730xx and STM32H730xxQ devices linker files (1MB flash) for EWARM toolchain</li>
|
|
||||||
<li><p>Add EWARM STM32H723xE and STM32H725xE devices linker files (<strong>Subset 512KB flash</strong>) for EWARM toolchain</p></li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Note : <strong>stm32h730xx</strong> and <strong>stm32h730xxQ</strong> are <strong>Value line</strong> devices with 128KB flash:</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update STM32H7 devices header files:
|
|
||||||
<ul>
|
|
||||||
<li>Fix FDCAN_ECR_TEC_Msk definition (8 bits bit field instead of 4)</li>
|
|
||||||
<li>Fix IS_SMBUS_INSTANCE macro definition with the right instances list for each STM32H7 line</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c, system_stm32h7xx_dualcore_bootcm7_cm4gated.c and system_stm32h7xx_singlecore.c files to:
|
|
||||||
<ul>
|
|
||||||
<li>Add Flash latency settings depending of the previous CPU frequency (Increasing or decreasing the CPU frequency)<br />
|
|
||||||
</li>
|
|
||||||
<li>Fix RCC registers reset values settings</li>
|
|
||||||
<li>Disable the FMC bank1 (enabled after reset)
|
|
||||||
<ul>
|
|
||||||
<li>This prevents CPU speculation access on this bank which blocks the use of FMC during 24us. During this time the others FMC master (such as LTDC) cannot use it<br />
|
|
||||||
</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c and system_stm32h7xx_dualcore_bootcm7_cm4gated.c to:
|
|
||||||
<ul>
|
|
||||||
<li>Use D2_AXISRAM_BASE for Coretx-M4 VTOR when executing from RAM instead of D2_AHBSRAM_BASE
|
|
||||||
<ul>
|
|
||||||
<li>Note: both addresses are aliases to the same D2 domain physical RAM. D2_AXISRAM_BASE (<span class="citation" data-cites="0x10000000">@0x10000000</span>) gives access to the RAM with access using Instruction bus (I), where D2_AHBSRAM_BASE(<span class="citation" data-cites="0x30000000">@0x30000000</span>) gives access to the RAM with access using Data bus. thus when executing from this D2 RAM it is recommended to use D2_AXISRAM_BASE alias so the execution scheme respects the Harvard architecture (One bus for data and one bus for instructions).</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update system_stm32h7xx.c and system_stm32h7xx_dualcore_boot_cm4_cm7.c to:
|
|
||||||
<ul>
|
|
||||||
<li>Fix usage of SCB->SCR register: SEVONPEND enabled so that an interrupt generated by the other CPU triggers an event and wakes up the current CPU after a WFI/WFE instruction even if the interrupt is disabled</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Add EWARM, linker files for STM32H742xG and STM32H743xG devices coming with 1MB flash: 512KB for each bank</li>
|
|
||||||
<li><p>Add EWARM, MDK-ARM and GCC linker files for STM32H745xG and STM32H747xG devices coming with 1MB flash: 512KB for each bank</p></li>
|
|
||||||
<li>Update GCC startup files for all devices to align sequence to EWARM/MDK-ARM by calling “SystemInit” prior to any memory access
|
|
||||||
<ul>
|
|
||||||
<li>Allowing to avoid issues when using external memories</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-6">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li>
|
|
||||||
<li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li>
|
|
||||||
<li>Add definition of DMA_SxCR_TRBUFF bit field of DMA SxCR register allowing to enabled/disable bufferable transfers</li>
|
|
||||||
<li>Remove RCC_AHB2ENR_CRYPEN/RCC_AHB2RSTR_CRYPRST/RCC_AHB2LPENR_CRYPLPEN and RCC_AHB2ENR_HASHEN/RCC_AHB2RSTR_HASHRST/RCC_AHB2LPENR_HASHLPEN from H7 devices that doesn’t support CRYP/HASH (STM32H742/43/45/47/A3)</li>
|
|
||||||
<li>Add STM32H7_DEV_ID define allowing to identify the H7 Device ID</li>
|
|
||||||
<li>Update OCTOSPIM_TypeDef structure definition with 3 PCR registers instead of 8 (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
|
|
||||||
<li>Add definition for OCTOSPIM_CR_MUXEN and OCTOSPIM_CR_REQ2ACK_TIME in order to support OctoSPI IO Manager multiplexed mode feature (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
|
|
||||||
<li>Update system_stm32h7xx.c to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
|
|
||||||
<li>Add EWARM linker files for STM32H7A3 devices with reduced Flash size to 1MB:
|
|
||||||
<ul>
|
|
||||||
<li>stm32h7a3xg_flash.icf, stm32h7a3xg_flash_rw_sram1.icf, stm32h7a3xg_flash_rw_sram2.icf.</li>
|
|
||||||
<li>stm32h7a3xgq_flash.icf, stm32h7a3xgq_flash_rw_sram1.icf, stm32h7a3xgq_flash_rw_sram2.icf.</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-7">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li>
|
|
||||||
<li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
|
|
||||||
<ul>
|
|
||||||
<li>Add “stm32h7a3xx.h”, “stm32h7a3xxq.h”, “stm32h7b3xx.h”, “stm32h7b3xxq.h”, “stm32h7b0xx.h” and “stm32h7b0xxq.h” files</li>
|
|
||||||
<li>Add startup files “startup_stm32h7a3xx.s”, “startup_stm32h7a3xxq.s”, “startup_stm32h7b3xx.s”, “startup_stm32h7b3xxq.s”, “startup_stm32h7b0xx.s” and “startup_stm32h7b0xxq.s” for EWARM , MDK-ARM and STM32CubeIDE toolchains</li>
|
|
||||||
<li>Add part numbers list to stm32h7xx.h header file:
|
|
||||||
<ul>
|
|
||||||
<li>STM32H7A3xx : STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6</li>
|
|
||||||
<li>STM32H7A3xxQ : STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q</li>
|
|
||||||
<li>STM32H7B3xx : STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6</li>
|
|
||||||
<li>STM32H7B3xxQ : STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q</li>
|
|
||||||
<li>STM32H7B0xx : STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features
|
|
||||||
<ul>
|
|
||||||
<li>Add CR_LOM (Line Ofset Mode) bit definition, Add OPFCCR_SB (Swap Bytes) bit definition</li>
|
|
||||||
<li>Update CR_MODE, FGOR_LO, BGOR_LO and OOR_LO bit definition</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</li>
|
|
||||||
<li><p>Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions</p></li>
|
|
||||||
<li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implementation</p></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-8">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
|
|
||||||
<li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
|
|
||||||
<li>Add definition of “ART” bit fields: ART_CTR_EN and ART_CTR_PCACHEADDR<br />
|
|
||||||
</li>
|
|
||||||
<li>Update definitions of “HRTIM1_TIMA” to “HRTIM1_TIME” : pointer to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef</li>
|
|
||||||
<li>Fix Typo in “ETH_TypeDef” definition: use uint32_t for “RESERVED16” registers instead of int32_t</li>
|
|
||||||
<li>Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-9">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
|
|
||||||
<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
|
|
||||||
<li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):
|
|
||||||
<ul>
|
|
||||||
<li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>
|
|
||||||
<li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
|
|
||||||
<li>Add part numbers list to stm32h7xx.h header file:
|
|
||||||
<ul>
|
|
||||||
<li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
|
|
||||||
<li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
|
|
||||||
<li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
|
|
||||||
<li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
|
|
||||||
<li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
|
|
||||||
<li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
|
|
||||||
<li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
|
|
||||||
<li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
|
|
||||||
<li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
|
|
||||||
<li>Add system initialization template source file for dual core lines:
|
|
||||||
<ul>
|
|
||||||
<li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
|
|
||||||
<li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
|
|
||||||
<li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
|
|
||||||
<li><p>Add EWARM STM32H742xx devices linker files</p></li>
|
|
||||||
</ul></li>
|
|
||||||
</ul></li>
|
|
||||||
<li><strong>Registers and bit field definitions updates</strong>:
|
|
||||||
<ul>
|
|
||||||
<li>Update SYSCFG_TypeDef structure to add
|
|
||||||
<ul>
|
|
||||||
<li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>
|
|
||||||
<li>Add definitions of SYSCFG_CFGR register bit fields</li>
|
|
||||||
<li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>
|
|
||||||
<li>Add SYSCFG_PWRCR register bit fields</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:
|
|
||||||
<ul>
|
|
||||||
<li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>
|
|
||||||
<li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>
|
|
||||||
<li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>
|
|
||||||
<li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
|
|
||||||
<ul>
|
|
||||||
<li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>
|
|
||||||
<li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>
|
|
||||||
<li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>
|
|
||||||
<li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>
|
|
||||||
<li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>
|
|
||||||
<li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>
|
|
||||||
<li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>
|
|
||||||
<li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-10">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li><strong>Patch Release on top of V1.3.0</strong></li>
|
|
||||||
<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
|
|
||||||
<ul>
|
|
||||||
<li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-11">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>STM32H7xx include files:
|
|
||||||
<ul>
|
|
||||||
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
|
|
||||||
<li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>
|
|
||||||
<li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>
|
|
||||||
<li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>
|
|
||||||
<li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>
|
|
||||||
<li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>
|
|
||||||
<li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>
|
|
||||||
<li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>
|
|
||||||
<li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>
|
|
||||||
<li>Update <strong>FLASH</strong> user option bytes bit definition</li>
|
|
||||||
<li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>
|
|
||||||
<li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>
|
|
||||||
<li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>
|
|
||||||
<li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>
|
|
||||||
<li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>
|
|
||||||
<li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>
|
|
||||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>
|
|
||||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>
|
|
||||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>
|
|
||||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>
|
|
||||||
<li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>
|
|
||||||
<li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>
|
|
||||||
<li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>
|
|
||||||
<li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>
|
|
||||||
<li>Add IS_GPIO_AF_INSTANCE macro</li>
|
|
||||||
<li>Update <strong>DAC</strong> bits definition</li>
|
|
||||||
<li>Update <strong>FDCAN</strong> bits definition</li>
|
|
||||||
<li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>
|
|
||||||
<li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>
|
|
||||||
<li>Update <strong>TIM</strong> registers and bits definition naming</li>
|
|
||||||
<li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>
|
|
||||||
<li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>
|
|
||||||
<li>Update <strong>BDMA</strong> bits definition</li>
|
|
||||||
<li>Update <strong>FMC</strong> bits definition</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-12">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Add support for stm32h750xx value line devices:
|
|
||||||
<ul>
|
|
||||||
<li>Add “stm32h750xx.h” file</li>
|
|
||||||
<li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>
|
|
||||||
</ul></li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-13">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Update FDCAN bit definition</li>
|
|
||||||
<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-14">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Update USB OTG bit definition</li>
|
|
||||||
<li>Adjust PLL fractional computation</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-15">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<footer class="sticky">
|
|
||||||
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
|
|
||||||
</footer>
|
|
||||||
</body>
|
|
||||||
</html>
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08100000 0x00080000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08100000 0x00080000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10000000 0x00048000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x20000000 0x00020000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10000000 0x00048000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x20000000 0x00020000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
|
||||||
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x24040000 0x00040000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
|
||||||
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10020000 0x00028000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08100000 0x00080000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08100000 0x00080000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10000000 0x00048000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x20000000 0x00020000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10000000 0x00048000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x20000000 0x00020000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
|
||||||
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x24040000 0x00040000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
|
||||||
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10020000 0x00028000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10000000 0x00048000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x20000000 0x00020000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
|
||||||
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x24040000 0x00040000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
|
||||||
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10020000 0x00028000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08100000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08100000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10000000 0x00048000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
|
||||||
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x20000000 0x00020000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x24000000 0x00040000 { ; load region size_region
|
|
||||||
ER_IROM1 0x24000000 0x00040000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x24040000 0x00040000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,14 +0,0 @@
|
|||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
|
|
||||||
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
RW_IRAM1 0x10020000 0x00028000{ ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user