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i# This is a combination of 3 commits.

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【修改】format
This commit is contained in:
YJIE_1998
2021-08-10 10:30:52 +08:00
parent 19d4c6809c
commit 53a4074f0b
107 changed files with 47438 additions and 47438 deletions
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bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2020, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.h
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h
+2 -2
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@@ -8,8 +8,8 @@
* is using in the C source code, usually in main.c. This file contains: * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select: * - Configuration section that allows to select:
* - The STM32F3xx device used in the target application * - The STM32F3xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e. * - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers * code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by * rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER" * "#define USE_HAL_DRIVER"
* *
bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/RTOS/Template/cmsis_os.h
+1 -1
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@@ -49,7 +49,7 @@
#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) #define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. /// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) #define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. /// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string #define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h
+1 -1
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@@ -98,7 +98,7 @@ typedef enum
{ \ { \
(__HANDLE__)->Lock = HAL_LOCKED; \ (__HANDLE__)->Lock = HAL_LOCKED; \
} \ } \
}while (0U) }while (0U)
#define __HAL_UNLOCK(__HANDLE__) \ #define __HAL_UNLOCK(__HANDLE__) \
do{ \ do{ \
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h
+3 -3
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@@ -1246,7 +1246,7 @@
* @brief AF 0 selection * @brief AF 0 selection
*/ */
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
@@ -1351,7 +1351,7 @@
* @brief AF 0 selection * @brief AF 0 selection
*/ */
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
@@ -1415,7 +1415,7 @@
/** /**
* @brief AF 8 selection * @brief AF 8 selection
*/ */
#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ #define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ #define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ #define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ #define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
+1 -1
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@@ -311,7 +311,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
} }
/** /**
* @brief Initializes and configures the Region and the memory to be protected. * @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information. * the initialization and configuration information.
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
+3 -3
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@@ -81,7 +81,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
*/ */
/** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions /** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
* @brief Peripheral Control functions * @brief Peripheral Control functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
@@ -90,7 +90,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Set the specified data holding register value for DAC channel. (+) Set the specified data holding register value for DAC channel.
(+) Set the specified data holding register value for dual DAC channel (+) Set the specified data holding register value for dual DAC channel
(when DAC channel 2 is present in DAC 1U) (when DAC channel 2 is present in DAC 1U)
@endverbatim @endverbatim
* @{ * @{
@@ -218,7 +218,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
(+) Handle DAC IRQ's. (+) Handle DAC IRQ's.
(+) Generate triangular-wave (+) Generate triangular-wave
(+) Generate noise-wave (+) Generate noise-wave
(+) Callback functions for DAC1 Channel2 (when supported) (+) Callback functions for DAC1 Channel2 (when supported)
@endverbatim @endverbatim
* @{ * @{
*/ */
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
+69 -69
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@@ -280,7 +280,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/ */
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); assert_param(IS_DMA_BUFFER_SIZE(DataLength));
@@ -290,27 +290,27 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
if(HAL_DMA_STATE_READY == hdma->State) if(HAL_DMA_STATE_READY == hdma->State)
{ {
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */ /* Disable the peripheral */
hdma->Instance->CCR &= ~DMA_CCR_EN; hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Configure the source, destination address and the data length */ /* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */ /* Enable the Peripheral */
hdma->Instance->CCR |= DMA_CCR_EN; hdma->Instance->CCR |= DMA_CCR_EN;
} }
else else
{ {
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
/* Remain BUSY */ /* Remain BUSY */
status = HAL_BUSY; status = HAL_BUSY;
} }
return status; return status;
@@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
*/ */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); assert_param(IS_DMA_BUFFER_SIZE(DataLength));
@@ -337,35 +337,35 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
if(HAL_DMA_STATE_READY == hdma->State) if(HAL_DMA_STATE_READY == hdma->State)
{ {
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */ /* Disable the peripheral */
hdma->Instance->CCR &= ~DMA_CCR_EN; hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Configure the source, destination address and the data length */ /* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete, & transfer error interrupts */ /* Enable the transfer complete, & transfer error interrupts */
/* Half transfer interrupt is optional: enable it only if associated callback is available */ /* Half transfer interrupt is optional: enable it only if associated callback is available */
if(NULL != hdma->XferHalfCpltCallback ) if(NULL != hdma->XferHalfCpltCallback )
{ {
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
} }
else else
{ {
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
hdma->Instance->CCR &= ~DMA_IT_HT; hdma->Instance->CCR &= ~DMA_IT_HT;
} }
/* Enable the Peripheral */ /* Enable the Peripheral */
hdma->Instance->CCR |= DMA_CCR_EN; hdma->Instance->CCR |= DMA_CCR_EN;
} }
else else
{ {
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
/* Remain BUSY */ /* Remain BUSY */
@@ -568,62 +568,62 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
*/ */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{ {
uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR; uint32_t source_it = hdma->Instance->CCR;
/* Half Transfer Complete Interrupt management ******************************/ /* Half Transfer Complete Interrupt management ******************************/
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
{ {
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
/* Disable the half transfer interrupt */ /* Disable the half transfer interrupt */
hdma->Instance->CCR &= ~DMA_IT_HT; hdma->Instance->CCR &= ~DMA_IT_HT;
} }
/* Clear the half transfer complete flag */ /* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
/* DMA peripheral state is not updated in Half Transfer */ /* DMA peripheral state is not updated in Half Transfer */
/* State is updated only in Transfer Complete case */ /* State is updated only in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL) if(hdma->XferHalfCpltCallback != NULL)
{ {
/* Half transfer callback */ /* Half transfer callback */
hdma->XferHalfCpltCallback(hdma); hdma->XferHalfCpltCallback(hdma);
} }
} }
/* Transfer Complete Interrupt management ***********************************/ /* Transfer Complete Interrupt management ***********************************/
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
{ {
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
/* Disable the transfer complete & transfer error interrupts */ /* Disable the transfer complete & transfer error interrupts */
/* if the DMA mode is not CIRCULAR */ /* if the DMA mode is not CIRCULAR */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
} }
/* Clear the transfer complete flag */ /* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL) if(hdma->XferCpltCallback != NULL)
{ {
/* Transfer complete callback */ /* Transfer complete callback */
hdma->XferCpltCallback(hdma); hdma->XferCpltCallback(hdma);
} }
} }
/* Transfer Error Interrupt management ***************************************/ /* Transfer Error Interrupt management ***************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
{ {
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
/* Then, disable all DMA interrupts */ /* Then, disable all DMA interrupts */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
@@ -642,8 +642,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
if(hdma->XferErrorCallback != NULL) if(hdma->XferErrorCallback != NULL)
{ {
/* Transfer error callback */ /* Transfer error callback */
hdma->XferErrorCallback(hdma); hdma->XferErrorCallback(hdma);
} }
} }
} }
@@ -824,7 +824,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
*/ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{ {
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
/* Configure DMA Channel data length */ /* Configure DMA Channel data length */
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp_ex.c
+1 -1
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@@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA
return status; return status;
} }
#endif /* STM32F302xE || */ #endif /* STM32F302xE || */
/* STM32F302xC */ /* STM32F302xC */
#if defined(STM32F303xE) || defined(STM32F398xx) || \ #if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx) defined(STM32F303xC) || defined(STM32F358xx)
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
+1 -1
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@@ -20,7 +20,7 @@
HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
[..] [..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes: (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources. configuration requiring different wake up sources.
Application/Example behavior is no more guaranteed Application/Example behavior is no more guaranteed
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
+1 -1
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@@ -21,7 +21,7 @@
HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
[..] [..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes: (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources. configuration requiring different wake up sources.
Application/Example behavior is no more guaranteed Application/Example behavior is no more guaranteed
bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
+1 -1
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@@ -40,7 +40,7 @@
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values: (+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler: (++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 113.78µs max timeout before reset: approximately 113.78µs
(++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler (++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler
dividing by 8: dividing by 8:
max timeout before reset: approximately 58.25ms max timeout before reset: approximately 58.25ms
bsp/stm32/libraries/templates/stm32f3xx/applications/main.c
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/libraries/templates/stm32f3xx/board/board.c
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/libraries/templates/stm32f3xx/board/board.h
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/stm32f302-st-nucleo/applications/main.c
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/stm32f302-st-nucleo/board/board.c
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
bsp/stm32/stm32f302-st-nucleo/board/board.h
+1 -1
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *