mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-22 19:44:24 +08:00
add qemu-riscv-virt64 bsp
add qemu-riscv-virt64 bsp
This commit is contained in:
lizhirui
@@ -14,6 +14,8 @@ if rtconfig.CPU == "e906" :
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group = group
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elif rtconfig.CPU == "nuclei" :
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group = group
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elif rtconfig.CPU == "virt64" :
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group = group
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else :
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group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
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@@ -0,0 +1,14 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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ASFLAGS = ''
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group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
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Return('group')
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@@ -0,0 +1,52 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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* 2021/02/02 lizhirui Add userspace support
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*/
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#include "cpuport.h"
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#include "stackframe.h"
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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la s0, rt_current_thread
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LOAD s1, (s0)
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RESTORE_ALL
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sret
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/*
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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*
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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mv t2, sp
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li t0, 0x120//set SPIE and SPP = 1
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csrs sstatus, t0//if enter here,caller must be in system thread
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csrw sepc, ra//return address
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//saved from thread context
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SAVE_ALL
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STORE t2, 32 * REGBYTES(sp)//save user_sp
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STORE sp, (a0)
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//restore to thread context
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LOAD sp, (a1)
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la s0, rt_current_thread
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LOAD s1, (s0)
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RESTORE_ALL
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sret
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@@ -0,0 +1,120 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting code.
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* 2021-02-11 lizhirui add gp support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "cpuport.h"
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#include "stack.h"
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/**
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* @brief from thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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/**
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* @brief to thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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/**
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* @brief flag to indicate context switch in interrupt or not
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*
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*/
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volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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extern int __global_pointer$;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->gp = (rt_ubase_t)&__global_pointer$;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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frame->user_sp_exc_stack = (rt_ubase_t)(((rt_ubase_t)stk) + sizeof(struct rt_hw_stack_frame));
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/* force to supervisor mode(SPP=1) and set SPIE and SUM to 1 */
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frame->sstatus = 0x00040120;
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return stk;
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}
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*/
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#ifndef RT_USING_SMP
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void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
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{
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if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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rt_interrupt_to_thread = to;
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rt_thread_switch_interrupt_flag = 1;
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return ;
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}
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#endif /* end of RT_USING_SMP */
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/** shutdown CPU */
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void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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rt_thread_t rt_thread_sp_to_thread(void *spmember_addr)
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{
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return (rt_thread_t)(((rt_ubase_t)spmember_addr) - (offsetof(struct rt_thread,sp)));
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}
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void *get_thread_kernel_stack_top(rt_thread_t thread)
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{
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return (void *)(((rt_size_t)thread -> stack_addr) + ((rt_size_t)thread -> stack_size));
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}
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@@ -0,0 +1,28 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-03 Bernard The first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <rtconfig.h>
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/* bytes of register width */
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#else
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// error here, not portable
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#endif
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#endif
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#ifdef RISCV_U_MODE
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#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL
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#endif
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@@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/02 Bernard The first version
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* 2018/12/27 Jesven Add SMP schedule
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* 2021/02/02 lizhirui Add userspace support
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*/
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#include "cpuport.h"
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#include "encoding.h"
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#include "stackframe.h"
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.section .text.entry
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.align 2
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.global trap_entry
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.extern __stack_cpu0
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.extern get_current_thread_kernel_stack_top
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trap_entry:
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//backup sp
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csrrw sp, sscratch, sp
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//load interrupt stack
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la sp, __stack_cpu0
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//backup context
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SAVE_ALL
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RESTORE_SYS_GP
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csrr a0, scause
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csrrc a1, stval, zero
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csrr a2, sepc
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mv a3, sp
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/* scause, stval, sepc, sp */
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call handle_trap
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/* need to switch new thread */
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la s0, rt_thread_switch_interrupt_flag
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lw s2, 0(s0)
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beqz s2, spurious_interrupt
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sw zero, 0(s0)
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.global rt_hw_context_switch_interrupt_do
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rt_hw_context_switch_interrupt_do:
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//switch to thread kernel stack
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csrr t0, sstatus
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andi t0, t0, 0x100
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beqz t0, __restore_sp_from_tcb_interrupt
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__restore_sp_from_sscratch_interrupt:
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csrr t0, sscratch
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j __move_stack_context_interrupt
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__restore_sp_from_tcb_interrupt:
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la s0, rt_interrupt_from_thread
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LOAD a0, 0(s0)
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jal rt_thread_sp_to_thread
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jal get_thread_kernel_stack_top
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mv t0, a0
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__move_stack_context_interrupt:
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mv t1, sp//src
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mv sp, t0//switch stack
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addi sp, sp, -33 * REGBYTES
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//copy context
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li s0, 33//cnt
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mv t2, sp//dst
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copy_context_loop_interrupt:
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LOAD t0, 0(t1)
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STORE t0, 0(t2)
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addi s0, s0, -1
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addi t1, t1, 8
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addi t2, t2, 8
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bnez s0, copy_context_loop_interrupt
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la s0, rt_interrupt_from_thread
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LOAD s1, 0(s0)
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STORE sp, 0(s1)
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la s0, rt_interrupt_to_thread
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LOAD s1, 0(s0)
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LOAD sp, 0(s1)
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spurious_interrupt:
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RESTORE_ALL
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sret
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.global rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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csrs sstatus, a0
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jr ra
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.global rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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csrrci a0, sstatus, 2
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jr ra
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@@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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||||
* SPDX-License-Identifier: Apache-2.0
|
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*
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* Change Logs:
|
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* Date Author Notes
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* 2021-01-30 lizhirui first version
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*/
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#ifndef __RISCV_H__
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#define __RISCV_H__
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#include <encoding.h>
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#define __SIZE(bit) (1UL << (bit))
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#define __MASK(bit) (__SIZE(bit) - 1UL)
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#define __UMASK(bit) (~(__MASK(bit)))
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#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
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#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))
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#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)value) & (~__MASK(bit_count))))
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#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)value) & (__MASK(start_bit))))
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#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length))
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#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
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#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
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#endif
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@@ -0,0 +1,109 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_IO_H__
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#define __RISCV_IO_H__
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static inline void __raw_writeb(rt_uint8_t val, volatile void *addr)
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{
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asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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static inline void __raw_writew(rt_uint16_t val, volatile void *addr)
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{
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asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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static inline void __raw_writel(rt_uint32_t val, volatile void *addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#if __riscv_xlen != 32
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static inline void __raw_writeq(rt_uint64_t val, volatile void *addr)
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{
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asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#endif
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static inline rt_uint8_t __raw_readb(const volatile void *addr)
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{
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rt_uint8_t val;
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asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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static inline rt_uint16_t __raw_readw(const volatile void *addr)
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{
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rt_uint16_t val;
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asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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static inline rt_uint32_t __raw_readl(const volatile void *addr)
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{
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rt_uint32_t val;
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asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#if __riscv_xlen != 32
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static inline rt_uint64_t __raw_readq(const volatile void *addr)
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{
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rt_uint64_t val;
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asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#endif
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/* FIXME: These are now the same as asm-generic */
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|
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/* clang-format off */
|
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|
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#define __io_rbr() do {} while (0)
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#define __io_rar() do {} while (0)
|
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#define __io_rbw() do {} while (0)
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#define __io_raw() do {} while (0)
|
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|
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#define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
|
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#define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
|
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#define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
|
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|
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#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
|
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#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
|
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#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
|
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|
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#if __riscv_xlen != 32
|
||||
#define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
|
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#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
|
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#endif
|
||||
|
||||
#define __io_br() do {} while (0)
|
||||
#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
|
||||
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
|
||||
#define __io_aw() do {} while (0)
|
||||
|
||||
#define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
|
||||
#define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
|
||||
#define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
|
||||
|
||||
#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
|
||||
#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
|
||||
#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
#define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
|
||||
#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
*/
|
||||
|
||||
#ifndef __STACK_H__
|
||||
#define __STACK_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
struct rt_hw_stack_frame
|
||||
{
|
||||
rt_ubase_t epc; /* epc - epc - program counter */
|
||||
rt_ubase_t ra; /* x1 - ra - return address for jumps */
|
||||
rt_ubase_t sstatus; /* - supervisor status register */
|
||||
rt_ubase_t gp; /* x3 - gp - global pointer */
|
||||
rt_ubase_t tp; /* x4 - tp - thread pointer */
|
||||
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
|
||||
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
|
||||
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
|
||||
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
|
||||
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
|
||||
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
|
||||
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
|
||||
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
|
||||
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
|
||||
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
|
||||
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
|
||||
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
|
||||
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
|
||||
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
|
||||
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
|
||||
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
|
||||
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
|
||||
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
|
||||
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
|
||||
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
|
||||
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
|
||||
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
|
||||
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
|
||||
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
|
||||
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
|
||||
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
|
||||
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
|
||||
rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-02-02 lizhirui first version
|
||||
* 2021-02-11 lizhirui fixed gp save/store bug
|
||||
*/
|
||||
|
||||
#ifndef __STACKFRAME_H__
|
||||
#define __STACKFRAME_H__
|
||||
|
||||
#include "cpuport.h"
|
||||
|
||||
.macro SAVE_ALL
|
||||
addi sp, sp, -33 * REGBYTES
|
||||
|
||||
STORE x1, 1 * REGBYTES(sp)
|
||||
|
||||
csrr x1, sstatus
|
||||
STORE x1, 2 * REGBYTES(sp)
|
||||
|
||||
csrr x1, sepc
|
||||
STORE x1, 0 * REGBYTES(sp)
|
||||
|
||||
STORE x3, 3 * REGBYTES(sp)
|
||||
STORE x4, 4 * REGBYTES(sp)
|
||||
STORE x5, 5 * REGBYTES(sp)
|
||||
STORE x6, 6 * REGBYTES(sp)
|
||||
STORE x7, 7 * REGBYTES(sp)
|
||||
STORE x8, 8 * REGBYTES(sp)
|
||||
STORE x9, 9 * REGBYTES(sp)
|
||||
STORE x10, 10 * REGBYTES(sp)
|
||||
STORE x11, 11 * REGBYTES(sp)
|
||||
STORE x12, 12 * REGBYTES(sp)
|
||||
STORE x13, 13 * REGBYTES(sp)
|
||||
STORE x14, 14 * REGBYTES(sp)
|
||||
STORE x15, 15 * REGBYTES(sp)
|
||||
STORE x16, 16 * REGBYTES(sp)
|
||||
STORE x17, 17 * REGBYTES(sp)
|
||||
STORE x18, 18 * REGBYTES(sp)
|
||||
STORE x19, 19 * REGBYTES(sp)
|
||||
STORE x20, 20 * REGBYTES(sp)
|
||||
STORE x21, 21 * REGBYTES(sp)
|
||||
STORE x22, 22 * REGBYTES(sp)
|
||||
STORE x23, 23 * REGBYTES(sp)
|
||||
STORE x24, 24 * REGBYTES(sp)
|
||||
STORE x25, 25 * REGBYTES(sp)
|
||||
STORE x26, 26 * REGBYTES(sp)
|
||||
STORE x27, 27 * REGBYTES(sp)
|
||||
STORE x28, 28 * REGBYTES(sp)
|
||||
STORE x29, 29 * REGBYTES(sp)
|
||||
STORE x30, 30 * REGBYTES(sp)
|
||||
STORE x31, 31 * REGBYTES(sp)
|
||||
csrr t0, sscratch
|
||||
STORE t0, 32 * REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_ALL_ONLY
|
||||
/* resw ra to sepc */
|
||||
LOAD x1, 0 * REGBYTES(sp)
|
||||
csrw sepc, x1
|
||||
|
||||
LOAD x1, 2 * REGBYTES(sp)
|
||||
csrw sstatus, x1
|
||||
|
||||
LOAD x1, 1 * REGBYTES(sp)
|
||||
|
||||
LOAD x3, 3 * REGBYTES(sp)
|
||||
LOAD x4, 4 * REGBYTES(sp)
|
||||
LOAD x5, 5 * REGBYTES(sp)
|
||||
LOAD x6, 6 * REGBYTES(sp)
|
||||
LOAD x7, 7 * REGBYTES(sp)
|
||||
LOAD x8, 8 * REGBYTES(sp)
|
||||
LOAD x9, 9 * REGBYTES(sp)
|
||||
LOAD x10, 10 * REGBYTES(sp)
|
||||
LOAD x11, 11 * REGBYTES(sp)
|
||||
LOAD x12, 12 * REGBYTES(sp)
|
||||
LOAD x13, 13 * REGBYTES(sp)
|
||||
LOAD x14, 14 * REGBYTES(sp)
|
||||
LOAD x15, 15 * REGBYTES(sp)
|
||||
LOAD x16, 16 * REGBYTES(sp)
|
||||
LOAD x17, 17 * REGBYTES(sp)
|
||||
LOAD x18, 18 * REGBYTES(sp)
|
||||
LOAD x19, 19 * REGBYTES(sp)
|
||||
LOAD x20, 20 * REGBYTES(sp)
|
||||
LOAD x21, 21 * REGBYTES(sp)
|
||||
LOAD x22, 22 * REGBYTES(sp)
|
||||
LOAD x23, 23 * REGBYTES(sp)
|
||||
LOAD x24, 24 * REGBYTES(sp)
|
||||
LOAD x25, 25 * REGBYTES(sp)
|
||||
LOAD x26, 26 * REGBYTES(sp)
|
||||
LOAD x27, 27 * REGBYTES(sp)
|
||||
LOAD x28, 28 * REGBYTES(sp)
|
||||
LOAD x29, 29 * REGBYTES(sp)
|
||||
LOAD x30, 30 * REGBYTES(sp)
|
||||
LOAD x31, 31 * REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 33 * REGBYTES
|
||||
.endm
|
||||
|
||||
.macro RESTORE_ALL
|
||||
/* resw ra to sepc */
|
||||
LOAD x1, 0 * REGBYTES(sp)
|
||||
csrw sepc, x1
|
||||
|
||||
LOAD x1, 2 * REGBYTES(sp)
|
||||
csrw sstatus, x1
|
||||
|
||||
LOAD x1, 1 * REGBYTES(sp)
|
||||
|
||||
LOAD x3, 3 * REGBYTES(sp)
|
||||
LOAD x4, 4 * REGBYTES(sp)
|
||||
LOAD x5, 5 * REGBYTES(sp)
|
||||
LOAD x6, 6 * REGBYTES(sp)
|
||||
LOAD x7, 7 * REGBYTES(sp)
|
||||
LOAD x8, 8 * REGBYTES(sp)
|
||||
LOAD x9, 9 * REGBYTES(sp)
|
||||
LOAD x10, 10 * REGBYTES(sp)
|
||||
LOAD x11, 11 * REGBYTES(sp)
|
||||
LOAD x12, 12 * REGBYTES(sp)
|
||||
LOAD x13, 13 * REGBYTES(sp)
|
||||
LOAD x14, 14 * REGBYTES(sp)
|
||||
LOAD x15, 15 * REGBYTES(sp)
|
||||
LOAD x16, 16 * REGBYTES(sp)
|
||||
LOAD x17, 17 * REGBYTES(sp)
|
||||
LOAD x18, 18 * REGBYTES(sp)
|
||||
LOAD x19, 19 * REGBYTES(sp)
|
||||
LOAD x20, 20 * REGBYTES(sp)
|
||||
LOAD x21, 21 * REGBYTES(sp)
|
||||
LOAD x22, 22 * REGBYTES(sp)
|
||||
LOAD x23, 23 * REGBYTES(sp)
|
||||
LOAD x24, 24 * REGBYTES(sp)
|
||||
LOAD x25, 25 * REGBYTES(sp)
|
||||
LOAD x26, 26 * REGBYTES(sp)
|
||||
LOAD x27, 27 * REGBYTES(sp)
|
||||
LOAD x28, 28 * REGBYTES(sp)
|
||||
LOAD x29, 29 * REGBYTES(sp)
|
||||
LOAD x30, 30 * REGBYTES(sp)
|
||||
LOAD x31, 31 * REGBYTES(sp)
|
||||
|
||||
//restore user sp
|
||||
LOAD sp, 32 * REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_SYS_GP
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
.endm
|
||||
|
||||
.macro OPEN_INTERRUPT
|
||||
csrsi sstatus, 2
|
||||
.endm
|
||||
|
||||
.macro CLOSE_INTERRUPT
|
||||
csrci sstatus, 2
|
||||
.endm
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/01 Bernard The first version
|
||||
* 2018/12/27 Jesven Add SMP support
|
||||
* 2020/6/12 Xim Port to QEMU and remove SMP support
|
||||
*/
|
||||
|
||||
#define SSTATUS_FS 0x00006000U /* initial state of FPU, clear to disable */
|
||||
#include <cpuport.h>
|
||||
|
||||
.global _start
|
||||
.section ".start", "ax"
|
||||
_start:
|
||||
j 1f
|
||||
.word 0xdeadbeef
|
||||
.align 3
|
||||
.global g_wake_up
|
||||
g_wake_up:
|
||||
.dword 1
|
||||
.dword 0
|
||||
1:
|
||||
csrw sie, 0
|
||||
csrw sip, 0
|
||||
la t0, trap_entry
|
||||
csrw stvec, t0
|
||||
|
||||
li x1, 0
|
||||
li x2, 0
|
||||
li x3, 0
|
||||
li x4, 0
|
||||
li x5, 0
|
||||
li x6, 0
|
||||
li x7, 0
|
||||
li x8, 0
|
||||
li x9, 0
|
||||
li x10,0
|
||||
li x11,0
|
||||
li x12,0
|
||||
li x13,0
|
||||
li x14,0
|
||||
li x15,0
|
||||
li x16,0
|
||||
li x17,0
|
||||
li x18,0
|
||||
li x19,0
|
||||
li x20,0
|
||||
li x21,0
|
||||
li x22,0
|
||||
li x23,0
|
||||
li x24,0
|
||||
li x25,0
|
||||
li x26,0
|
||||
li x27,0
|
||||
li x28,0
|
||||
li x29,0
|
||||
li x30,0
|
||||
li x31,0
|
||||
|
||||
/* set to disable FPU */
|
||||
li t0, SSTATUS_FS
|
||||
csrc sstatus, t0
|
||||
li t0, 0x40000 // SUM in sstatus
|
||||
csrs sstatus, t0
|
||||
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
|
||||
// removed SMP support here
|
||||
la sp, __stack_start__
|
||||
li t0, __STACKSIZE__
|
||||
add sp, sp, t0
|
||||
csrw sscratch, sp
|
||||
j primary_cpu_entry
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <encoding.h>
|
||||
#include "sbi.h"
|
||||
|
||||
static volatile uint64_t time_elapsed = 0;
|
||||
static volatile unsigned long tick_cycles = 0;
|
||||
|
||||
static uint64_t get_ticks()
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"rdtime %0"
|
||||
: "=r"(time_elapsed));
|
||||
return time_elapsed;
|
||||
}
|
||||
|
||||
int tick_isr(void)
|
||||
{
|
||||
// uint64_t core_id = current_coreid();
|
||||
int tick_cycles = 40000;
|
||||
// clint->mtimecmp[core_id] += tick_cycles;
|
||||
rt_tick_increase();
|
||||
sbi_set_timer(get_ticks() + tick_cycles);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sets and enable the timer interrupt */
|
||||
int rt_hw_tick_init(void)
|
||||
{
|
||||
/* Read core id */
|
||||
// unsigned long core_id = current_coreid();
|
||||
unsigned long interval = 1000/RT_TICK_PER_SECOND;
|
||||
|
||||
/* Clear the Supervisor-Timer bit in SIE */
|
||||
clear_csr(sie, SIP_STIP);
|
||||
|
||||
/* calculate the tick cycles */
|
||||
// tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1;
|
||||
tick_cycles = 40000;
|
||||
/* Set timer */
|
||||
sbi_set_timer(get_ticks() + tick_cycles);
|
||||
|
||||
/* Enable the Supervisor-Timer bit in SIE */
|
||||
set_csr(sie, SIP_STIP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#ifndef TICK_H__
|
||||
#define TICK_H__
|
||||
|
||||
int tick_isr(void);
|
||||
int rt_hw_tick_init(void);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user