add nrf5340 bsp,add uarte and gpio drv for 5340

bsp/nrf5x/nrf5340/Kconfig

@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+    
+source "board/Kconfig"
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+

bsp/nrf5x/nrf5340/README.md

@@ -0,0 +1,70 @@
+# nRF5340-PCA10095 BSP说明
+
+## 简介
+
+该文件夹主要存放所有主芯片为nRF5340的板级支持包。
+
+目前支持的开发板如下
+
+| 支持开发板型号                                               | 开发板上外设                | 备注                                |
+| ------------------------------------------------------------ | --------------------------- | ----------------------------------- |
+| [PCA10095](https://www.nordicsemi.com/Products/Development-hardware/nRF5340-DK) | QSPI FLASH, 4 button，4 LED | UART0                               |
+
+|                                                              |                             |                                     |
+
+
+选择开发板请使用`menuconfig` -> `Hardware Driver Config` -> `Select Bsp board`
+
+选择对应的开发板
+
+本文主要内容如下：
+
+- 开发板资源介绍
+- 进阶使用方法
+
+## 开发板介绍
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** |        **备注**        |
+| :----------- | :----------: | :--------------------: |
+| GPIO         |     支持     |         GPION          |
+| UART         |     支持     |         UART0          |
+| PWM          |     支持     |          支持          |
+| SPI          |     支持     |          支持          |
+| QSPI         |     支持     | 支持开发板上QSPI FLASH |
+| RTC          |     支持     |                        |
+| ADC          |     支持     |                        |
+|              |              |                        |
+|              |              |                        |
+|              |              |                        |
+
+
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 0 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5` 命令重新生成工程。
+
+
+
+## 支持其他开发板
+
+客户可以将自己的开发板的.config文件和board/Kconfig文件到board/$(board_name)下面添加README.md即可，使用的时候替换.config文件
+
+## 注意事项
+
+## 联系人信息
+
+维护人:
+
+-  [Andrew], 邮箱：<andrew.li@nordicsemi.no>

bsp/nrf5x/nrf5340/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/nrf5x/nrf5340/SConstruct

@@ -0,0 +1,57 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+print(SDK_LIB)
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
+
+# include cmsis
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/nrf5x/nrf5340/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nrf5x/nrf5340/applications/application.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ * 2021-06-26     supperthomas fix led
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+int main(void)
+{
+    int count = 1;
+    rt_pin_mode(RT_BSP_LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(RT_BSP_LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+
+        rt_pin_write(RT_BSP_LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}
+
+

bsp/nrf5x/nrf5340/board/SConscript

@@ -0,0 +1,10 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')

bsp/nrf5x/nrf5340/board/board.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-09     Andrew       first version
+ *
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#include <nrfx_systick.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include <nrfx_clock.h>
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+static void clk_event_handler(nrfx_clock_evt_type_t event){}
+
+void SysTick_Configuration(void)
+{
+    nrfx_clock_init(clk_event_handler);
+    nrfx_clock_enable();
+    nrfx_clock_lfclk_start();
+    /* Set interrupt priority */
+    NVIC_SetPriority(SysTick_IRQn, 0xf);
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
+    nrf_systick_val_clear();
+    nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
+                        | NRF_SYSTICK_CSR_ENABLE);
+
+}
+
+
+void rt_hw_board_init(void)
+{
+    rt_hw_interrupt_enable(0);
+
+    SysTick_Configuration();
+
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+
+#ifdef BSP_USING_SOFTDEVICE
+    extern uint32_t  Image$$RW_IRAM1$$Base;
+    uint32_t const *const m_ram_start  = &Image$$RW_IRAM1$$Base;
+    if ((uint32_t)m_ram_start == 0x20000000)
+    {
+        rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
+        while (1);
+    }
+    else
+    {
+        rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
+    }
+#endif
+
+}
+

bsp/nrf5x/nrf5340/board/board.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-09     Andrew       first version
+ *
+ */
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "nrf.h"
+
+#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
+#define MCU_FLASH_END_ADDRESS        ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
+#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024
+#define MCU_SRAM_END_ADDRESS        (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE)
+
+#if defined(__ARMCC_VERSION)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end__;
+#define HEAP_BEGIN      ((void *)&__bss_end__)
+#endif
+
+
+#define HEAP_END       (MCU_SRAM_END_ADDRESS)
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/nrf5x/nrf5340/board/fal_cfg.h

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-05-05     supperthomas this is sample you can change by yourself
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#if (defined(BSP_USING_QSPI_FLASH)&&defined(BSP_USING_ON_CHIP_FLASH))
+
+#define ON_CHIP_FLASH_DEV_NAME             "mcu_onchip"
+#define NOR_FLASH_DEV_NAME             "norflash0"
+
+extern const struct fal_flash_dev mcu_onchip_flash;
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+    {                                                                    \
+        &mcu_onchip_flash,                                           \
+        &nor_flash0,                                                     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+    {                                                                                    \
+        {FAL_PART_MAGIC_WORD, "bl",            ON_CHIP_FLASH_DEV_NAME,         0,   64*1024, 0}, \
+        {FAL_PART_MAGIC_WORD, "app_flash",     ON_CHIP_FLASH_DEV_NAME,   64*1024,  960*1024, 0}, \
+        {FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME,         0, 1024*1024, 0}, \
+        {FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \
+    }
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#elif defined(BSP_USING_QSPI_FLASH)
+
+#define NOR_FLASH_DEV_NAME             "norflash0"
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+    {                                                                    \
+        &nor_flash0,                                                     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+    {                                                                                    \
+        {FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME,         0, 1024*1024, 0}, \
+        {FAL_PART_MAGIC_WORD,  "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \
+    }
+#endif
+#elif defined(BSP_USING_ON_CHIP_FLASH)
+extern const struct fal_flash_dev mcu_onchip_flash;
+#define ON_CHIP_FLASH_DEV_NAME             "mcu_onchip"
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+    {                                                                    \
+        &mcu_onchip_flash,                                               \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+    {                                                                                    \
+        {FAL_PART_MAGIC_WORD,        "bl",           ON_CHIP_FLASH_DEV_NAME,         0,   64*1024, 0}, \
+        {FAL_PART_MAGIC_WORD,       "app_flash",     ON_CHIP_FLASH_DEV_NAME,   64*1024,  960*1024, 0}, \
+    }
+#endif
+#endif
+
+#endif /* _FAL_CFG_H_ */

bsp/nrf5x/nrf5340/board/linker_scripts/link.lds

@@ -0,0 +1,166 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000
+  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x80000
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+	        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+    } > FLASH
+	
+	 .nrf_queue :
+	{
+		PROVIDE(__start_nrf_queue = .);
+		KEEP(*(.nrf_balloc))
+		PROVIDE(__stop_nrf_queue = .);
+	} > FLASH
+	
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap (COPY):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        PROVIDE(end = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        KEEP(*(.stack*))
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+    
+    /* Check if text sections + data exceeds FLASH limit */
+    DataInitFlashUsed = __bss_start__ - __data_start__;
+    CodeFlashUsed = __etext - ORIGIN(FLASH);
+    TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
+    ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
+    
+}
+
+

bsp/nrf5x/nrf5340/board/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x80000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/nrf5x/nrf5340/board/nrfx_config.h

@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+// TODO - temporary redirection
+#include <sdk_config.h>
+/*
+ * These are mappings of Kconfig options enabling nrfx drivers and particular
+ * peripheral instances to the corresponding symbols used inside of nrfx.
+ * Please note that only subsets of these entries are used for particular SoCs
+ * supported by nrfx (see the corresponding nrfx_config_*.h files).
+ */
+
+#ifdef CONFIG_NRFX_ADC
+#define NRFX_ADC_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_CLOCK
+#define NRFX_CLOCK_ENABLED 1
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC
+#if defined(CONFIG_SOC_SERIES_NRF91X) || defined(CONFIG_SOC_SERIES_NRF53X)
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#else
+#define NRFX_CLOCK_CONFIG_LF_SRC 0
+#endif
+#endif // CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC
+
+#ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL
+#if defined(CONFIG_SOC_SERIES_NRF91X) || defined(CONFIG_SOC_SERIES_NRF53X)
+#define NRFX_CLOCK_CONFIG_LF_SRC 2
+#else
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#endif
+#endif // CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL
+
+#ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH
+#ifdef CONFIG_SOC_SERIES_NRF53X
+#define NRFX_CLOCK_CONFIG_LF_SRC 3
+#else
+#define NRFX_CLOCK_CONFIG_LF_SRC 2
+#endif
+#endif // CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH
+
+#ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_LOW_SWING
+#define NRFX_CLOCK_CONFIG_LF_SRC 131073
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_FULL_SWING
+#define NRFX_CLOCK_CONFIG_LF_SRC 196609
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION
+#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED
+#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_COMP
+#define NRFX_COMP_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_DPPI
+#define NRFX_DPPI_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_EGU
+#define NRFX_EGU_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_EGU0
+#define NRFX_EGU0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_EGU1
+#define NRFX_EGU1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_EGU2
+#define NRFX_EGU2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_EGU3
+#define NRFX_EGU3_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_EGU4
+#define NRFX_EGU4_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_EGU5
+#define NRFX_EGU5_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_GPIOTE
+#define NRFX_GPIOTE_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_I2S
+#define NRFX_I2S_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_IPC
+#define NRFX_IPC_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_LPCOMP
+#define NRFX_LPCOMP_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_NFCT
+#define NRFX_NFCT_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_NVMC
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_PDM
+#define NRFX_PDM_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_POWER
+#define NRFX_POWER_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_PPI
+#define NRFX_PPI_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_PRS
+#define NRFX_PRS_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PRS_BOX_0
+#define NRFX_PRS_BOX_0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PRS_BOX_1
+#define NRFX_PRS_BOX_1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PRS_BOX_2
+#define NRFX_PRS_BOX_2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PRS_BOX_3
+#define NRFX_PRS_BOX_3_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PRS_BOX_4
+#define NRFX_PRS_BOX_4_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_PWM
+#define NRFX_PWM_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PWM0
+#define NRFX_PWM0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PWM1
+#define NRFX_PWM1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PWM2
+#define NRFX_PWM2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_PWM3
+#define NRFX_PWM3_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_QDEC
+#define NRFX_QDEC_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_QSPI
+#define NRFX_QSPI_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_RNG
+#define NRFX_RNG_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_RTC
+#define NRFX_RTC_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_RTC0
+#define NRFX_RTC0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_RTC1
+#define NRFX_RTC1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_RTC2
+#define NRFX_RTC2_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_SAADC
+#define NRFX_SAADC_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_SPI
+#define NRFX_SPI_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPI0
+#define NRFX_SPI0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPI1
+#define NRFX_SPI1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPI2
+#define NRFX_SPI2_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_SPIM
+#define NRFX_SPIM_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIM0
+#define NRFX_SPIM0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIM1
+#define NRFX_SPIM1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIM2
+#define NRFX_SPIM2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIM3
+#define NRFX_SPIM3_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIM4
+#define NRFX_SPIM4_ENABLED 1
+#endif
+#if defined(CONFIG_SPI_3_NRF_RX_DELAY) || defined(CONFIG_SPI_4_NRF_RX_DELAY)
+#define NRFX_SPIM_EXTENDED_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_SPIS
+#define NRFX_SPIS_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIS0
+#define NRFX_SPIS0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIS1
+#define NRFX_SPIS1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIS2
+#define NRFX_SPIS2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_SPIS3
+#define NRFX_SPIS3_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_SYSTICK
+#define NRFX_SYSTICK_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_TEMP
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_TIMER
+#define NRFX_TIMER_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TIMER0
+#define NRFX_TIMER0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TIMER1
+#define NRFX_TIMER1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TIMER2
+#define NRFX_TIMER2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TIMER3
+#define NRFX_TIMER3_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TIMER4
+#define NRFX_TIMER4_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_TWI
+#define NRFX_TWI_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWI0
+#define NRFX_TWI0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWI1
+#define NRFX_TWI1_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_TWIM
+#define NRFX_TWIM_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIM0
+#define NRFX_TWIM0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIM1
+#define NRFX_TWIM1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIM2
+#define NRFX_TWIM2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIM3
+#define NRFX_TWIM3_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_TWIS
+#define NRFX_TWIS_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIS0
+#define NRFX_TWIS0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIS1
+#define NRFX_TWIS1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIS2
+#define NRFX_TWIS2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_TWIS3
+#define NRFX_TWIS3_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_UART
+#define NRFX_UART_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_UART0
+#define NRFX_UART0_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_UARTE
+#define NRFX_UARTE_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_UARTE0
+#define NRFX_UARTE0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_UARTE1
+#define NRFX_UARTE1_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_UARTE2
+#define NRFX_UARTE2_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_UARTE3
+#define NRFX_UARTE3_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_USBD
+#define NRFX_USBD_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_USBREG
+#define NRFX_USBREG_ENABLED 1
+#endif
+
+#ifdef CONFIG_NRFX_WDT
+#define NRFX_WDT_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_WDT0
+#define NRFX_WDT0_ENABLED 1
+#endif
+#ifdef CONFIG_NRFX_WDT1
+#define NRFX_WDT1_ENABLED 1
+#endif
+
+#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX)
+#include "nrfx_config_bsim.h"
+#endif
+
+/*
+ * For chips with TrustZone support, MDK provides CMSIS-Core peripheral
+ * accessing symbols in two flavors, with secure and non-secure base address
+ * mappings. Their names contain the suffix _S or _NS, respectively.
+ * Because nrfx HALs and drivers require these peripheral accessing symbols
+ * without any suffixes, the following macro is provided that will translate
+ * their names according to the kind of the target that is built.
+ */
+#if defined(NRF_TRUSTZONE_NONSECURE)
+#define NRF_PERIPH(P) P##_NS
+#else
+#define NRF_PERIPH(P) P##_S
+#endif
+
+
+#if defined(NRF51)
+    #include <nrfx_config_nrf51.h>
+#elif defined(NRF5340_XXAA_APPLICATION)
+    #include <nrfx_config_nrf5340_application.h>
+#elif defined(NRF5340_XXAA_NETWORK)
+    #include <nrfx_config_nrf5340_network.h>
+#elif defined(NRF9160_XXAA)
+    #include <nrfx_config_nrf9160.h>
+#endif
+
+
+#endif // NRFX_CONFIG_H__

bsp/nrf5x/nrf5340/board/nrfx_glue.h

@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_GLUE_H__
+#define NRFX_GLUE_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <stdbool.h>
+#include "nrf.h"
+/**
+ * @defgroup nrfx_glue nrfx_glue.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+// Uncomment this line to use the standard MDK way of binding IRQ handlers
+// at linking time.
+#include <soc/nrfx_irqs.h>
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for placing a runtime assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_ASSERT(expression)
+
+/**
+ * @brief Macro for placing a compile time assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_STATIC_ASSERT(expression)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for setting the priority of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ * @param priority   Priority to be set.
+ */
+#define NRFX_IRQ_PRIORITY_SET(irq_number, priority)     NVIC_SetPriority(irq_number, priority)
+
+/**
+ * @brief Macro for enabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_ENABLE(irq_number)     NVIC_EnableIRQ(irq_number)
+
+/**
+ * @brief Macro for checking if a specific IRQ is enabled.
+ *
+ * @param irq_number IRQ number.
+ *
+ * @retval true  If the IRQ is enabled.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_ENABLED(irq_number)  _NRFX_IRQ_IS_ENABLED(irq_number)
+static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
+{
+    return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
+}
+
+
+/**
+ * @brief Macro for disabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_DISABLE(irq_number)  _NRFX_IRQ_DISABLE(irq_number)
+static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
+{
+    NVIC_DisableIRQ(irq_number);
+}
+
+
+/**
+ * @brief Macro for setting a specific IRQ as pending.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_SET(irq_number)
+
+/**
+ * @brief Macro for clearing the pending status of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_CLEAR(irq_number)
+
+/**
+ * @brief Macro for checking the pending status of a specific IRQ.
+ *
+ * @retval true  If the IRQ is pending.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_PENDING(irq_number)
+
+/** @brief Macro for entering into a critical section. */
+#define NRFX_CRITICAL_SECTION_ENTER()
+
+/** @brief Macro for exiting from a critical section. */
+#define NRFX_CRITICAL_SECTION_EXIT()
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that
+ *        @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
+ *        A compilation error is generated if the DWT unit is not present
+ *        in the SoC used.
+ */
+#define NRFX_DELAY_DWT_BASED    0
+
+/**
+ * @brief Macro for delaying the code execution for at least the specified time.
+ *
+ * @param us_time Number of microseconds to wait.
+ */
+#define NRFX_DELAY_US(us_time)
+
+//------------------------------------------------------------------------------
+
+/** @brief Atomic 32-bit unsigned type. */
+#include <soc/nrfx_atomic.h>
+#define nrfx_atomic_t               nrfx_atomic_u32_t
+
+/**
+ * @brief Macro for storing a value to an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value to store.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the OR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)   nrfx_atomic_u32_fetch_or(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise AND operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the AND operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)   nrfx_atomic_u32_fetch_and(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise XOR operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the XOR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)   nrfx_atomic_u32_fetch_xor(p_data, value)
+
+/**
+ * @brief Macro for running an addition operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the ADD operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)   nrfx_atomic_u32_fetch_add(p_data, value)
+
+/**
+ * @brief Macro for running a subtraction operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the SUB operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)   nrfx_atomic_u32_fetch_sub(p_data, value)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that the
+ *        @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
+ *        in a customized way and the default definitions from @c <nrfx_error.h>
+ *        should not be used.
+ */
+#define NRFX_CUSTOM_ERROR_CODES 0
+
+//------------------------------------------------------------------------------
+
+/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
+#define NRFX_EGUS_USED          0
+
+/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
+#define NRFX_TIMERS_USED        0
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_GLUE_H__

bsp/nrf5x/nrf5340/board/nrfx_log.h

@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_LOG_H__
+#define NRFX_LOG_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_log nrfx_log.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+/**
+ * @brief Macro for logging a message with the severity level ERROR.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_ERROR(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level WARNING.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_WARNING(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level INFO.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_INFO(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level DEBUG.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_DEBUG(format, ...)
+
+
+/**
+ * @brief Macro for logging a memory dump with the severity level ERROR.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level WARNING.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level INFO.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level DEBUG.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
+
+
+/**
+ * @brief Macro for getting the textual representation of a given error code.
+ *
+ * @param[in] error_code Error code.
+ *
+ * @return String containing the textual representation of the error code.
+ */
+#define NRFX_LOG_ERROR_STRING_GET(error_code)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_LOG_H__

bsp/nrf5x/nrf5340/rtconfig.h

@@ -0,0 +1,227 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* Hardware Drivers Config */
+
+#define SOC_NRF5340
+#define SOC_NORDIC
+#define BSP_BOARD_PCA_10095
+
+/* Onboard Peripheral Drivers */
+
+#define RT_BSP_LED_PIN 28
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define NRFX_USING_UARTE
+#define BSP_USING_UART0
+#define BSP_UART0_RX_PIN 22
+#define BSP_UART0_TX_PIN 20
+#define NRFX_UARTE_ENABLED 1
+#define NRFX_UARTE0_ENABLED 1
+#define BSP_USING_UART1
+#define NRFX_UARTE1_ENABLED 1
+#define BSP_UART1_RX_PIN 32
+#define BSP_UART1_TX_PIN 33
+
+/* MCU flash config */
+
+#define MCU_FLASH_START_ADDRESS 0x00000000
+#define MCU_FLASH_SIZE_KB 1024
+#define MCU_SRAM_START_ADDRESS 0x20000000
+#define MCU_SRAM_SIZE_KB 512
+#define MCU_FLASH_PAGE_SIZE 0x1000
+#define BLE_STACK_USING_NULL
+#define NRFX_CLOCK_ENABLED 1
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#define NRFX_UART_ENABLED 1
+#define NRFX_UART0_ENABLED 1
+#define NRFX_GPIOTE_ENABLED 1
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_HWTIMER
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
+#define RT_USING_PIN
+#define RT_USING_ADC
+#define RT_USING_PWM
+#define RT_USING_RTC
+#define RT_USING_SPI
+#define RT_USING_WDT
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* POSIX extension functions */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_NRFX
+#define PKG_USING_NRFX_LATEST_VERSION
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+#endif

bsp/nrf5x/nrf5340/rtconfig.py

@@ -0,0 +1,92 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = 'D:/SourceryGCC/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    print('================ERROR============================')
+    print('Not support iar yet!')
+    print('=================================================')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu='+CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
+
+    CFLAGS += ' --c99'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/nrf5x/nrf5340/template.uvoptx

@@ -0,0 +1,187 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp; *.cc; *.cxx</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>0</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>13</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC4000 -FN1 -FF0nrf53xx_application -FS00 -FL0200000 -FP0($$Device:nRF5340_xxAA$Flash\nrf53xx_application.flm))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>