Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-09-21 10:36:04 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

[libcpu][arm926] Optimize code

Browse Source 
1. Combine code for IAR and GCC in file mmu.c and cpuport.c
2. Remove remap code in start_xxx.S. User should config MMU to map vector table to visual address 0x0
This commit is contained in:
ardafu
2015-04-22 11:19:50 +08:00
parent 66ac2fb9d7
commit 49fa5c44d7
6 changed files with 192 additions and 477 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libcpu/arm/arm926/context_gcc.S
+13 -13
View File
@@ -49,15 +49,15 @@ rt_hw_interrupt_enable:
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
stmfd sp!, {lr} @; push pc (lr should be pushed in place of pc)
stmfd sp!, {r0-r12, lr} @; push lr & register file
mrs r4, cpsr
stmfd sp!, {r4} @; push cpsr
str sp, [r0] @; store sp in preempted tasks tcb
ldr sp, [r1] @; get new task stack pointer
ldmfd sp!, {r4} @; pop new task spsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc}^ @; pop new task r0-r12, lr & pc
STMFD SP!, {LR} @; push pc (lr should be pushed in place of pc)
STMFD SP!, {R0-R12, LR} @; push lr & register file
MRS R4, CPSR
STMFD SP!, {R4} @; push cpsr
STR SP, [R0] @; store sp in preempted tasks tcb
LDR SP, [R1] @; get new task stack pointer
LDMFD SP!, {R4} @; pop new task spsr
MSR SPSR_cxsf, R4
LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc
/*
* void rt_hw_context_switch_to(rt_uint32 to);
@@ -65,10 +65,10 @@ rt_hw_context_switch:
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
ldr sp, [r0] @; get new task stack pointer
ldmfd sp!, {r4} @; pop new task cpsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc}^ @; pop new task r0-r12, lr & pc
LDR SP, [R0] @; get new task stack pointer
LDMFD SP!, {R4} @; pop new task cpsr
MSR SPSR_cxsf, R4
LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
libcpu/arm/arm926/cpuport.c
+21 -56
View File
@@ -32,18 +32,18 @@
extern void machine_reset(void);
extern void machine_shutdown(void);
#ifdef __GNUC__
#if defined(__GNUC__) || defined(__ICCARM__)
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__(\
__asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
@@ -54,7 +54,7 @@ rt_inline void cache_enable(rt_uint32_t bit)
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__(\
__asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
@@ -64,12 +64,12 @@ rt_inline void cache_disable(rt_uint32_t bit)
}
#endif
#ifdef __CC_ARM
#if defined(__CC_ARM)
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
__asm volatile
{
mrc p15, 0, i, c1, c0, 0
}
@@ -81,7 +81,7 @@ rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
@@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
@@ -102,38 +102,6 @@ rt_inline void cache_disable(rt_uint32_t bit)
}
#endif
#ifdef __ICCARM__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
/**
* enable I-Cache
*
@@ -249,27 +217,24 @@ int __rt_ffs(int value)
return x;
}
#elif defined(__ICCARM__)
#elif defined(__GNUC__) || defined(__ICCARM__)
int __rt_ffs(int value)
{
register rt_uint32_t x;
if (value == 0)
return value;
__ASM("RSB r4, r0, #0");
__ASM("AND r4, r4, r0");
__ASM("CLZ r4, r4");
__ASM("RSB r0, r4, #32");
}
#elif defined(__GNUC__)
int __rt_ffs(int value)
{
if (value == 0)
return value;
value &= (-value);
asm ("clz %0, %1": "=r"(value) :"r"(value));
return (32 - value);
__asm
(
"rsb %[temp], %[val], #0\n"
"and %[temp], %[temp], %[val]\n"
"clz %[temp], %[temp]\n"
"rsb %[temp], %[temp], #32\n"
:[temp] "=r"(x)
:[val] "r"(value)
);
return x;
}
#endif
libcpu/arm/arm926/mmu.c
+100 -316
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/arm926/start_gcc.S
+20 -23
View File
@@ -21,6 +21,7 @@
* Date Author Notes
* 2011-01-13 weety first version
* 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
* 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
*/
#define S_FRAME_SIZE (18*4) //72
@@ -63,31 +64,30 @@
.global UND_STACK_START
UND_STACK_START:
.space SVC_STK_SIZE
.align 2
.global SVC_STACK_START
SVC_STACK_START:
.space ABT_STK_SIZE
.align 2
.global ABT_STACK_START
ABT_STACK_START:
.space IRQ_STK_SIZE
.align 2
.global IRQ_STACK_START
IRQ_STACK_START:
.space FIQ_STK_SIZE
.align 2
.global FIQ_STACK_START
FIQ_STACK_START:
.space IRQ_STK_SIZE
.align 2
.global IRQ_STACK_START
IRQ_STACK_START:
.skip SYS_STK_SIZE
.align 2
.global SYS_STACK_START
SYS_STACK_START:
.space SVC_STK_SIZE
.align 2
.global SVC_STACK_START
SVC_STACK_START:
@;--------------Jump vector table-----------------------------------------------
.section .init, "ax"
@@ -132,24 +132,21 @@ Reset_Handler:
MRS R0, CPSR
BIC R0, R0, #MODEMASK
ORR R0, R0, #MODE_SVC|NOINT
MSR CPSR, R0
LDR SP, =SVC_STACK_START
MSR CPSR_cxsf, R0
@; Set CO-Processor
@; little-end，disbale I/D Cache MMU, vector table is 0x00000000
MRC P15, 0, R0, C1, C0, 0 @; Read CP15
LDR R1, =0x00003085 @; set clear bits
BIC R0, R0, R1
MCR P15, 0, R0, C1, C0, 0 @; Write CP15
@; Call low level init function,
@; disable and clear all IRQs and remap internal ram to 0x00000000.
@; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
LDR SP, =SVC_STACK_START
LDR R0, =rt_low_level_init
BLX R0
@; Copy Exception Vectors to Internal RAM
LDR R8, =entry @; Source
LDR R9, =VECTOR_TABLE_START @; Destination
CMP R8, R9
BEQ Setup_Stack
LDMIA R8!, {R0-R7} @; Load Vectors
STMIA R9!, {R0-R7} @; Store Vectors
LDMIA R8!, {R0-R7} @; Load Handler Addresses
STMIA R9!, {R0-R7} @; Store Handler Addresses
Setup_Stack:
@; Setup Stack for each mode
MRS R0, CPSR
libcpu/arm/arm926/start_iar.S
+15 -17
View File
@@ -21,6 +21,7 @@
; * Date Author Notes
; * 2011-01-13 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
; */
#define S_FRAME_SIZE (18*4) ;72
@@ -80,16 +81,16 @@ FIQ_STACK_START:
PUBLIC IRQ_STACK_START
IRQ_STACK_START:
ALIGNRAM 2
DS8 SVC_STK_SIZE
PUBLIC SVC_STACK_START
SVC_STACK_START:
ALIGNRAM 2
DS8 SYS_STK_SIZE
PUBLIC SYS_STACK_START
SYS_STACK_START:
ALIGNRAM 2
DS8 SVC_STK_SIZE
PUBLIC SVC_STACK_START
SVC_STACK_START:
;--------------Jump vector table------------------------------------------------
SECTION .intvec:CODE:ROOT(2)
ARM
@@ -134,22 +135,19 @@ Reset_Handler:
BIC R0, R0, #MODEMASK
ORR R0, R0, #MODE_SVC|NOINT
MSR CPSR_cxsf, R0
LDR SP, =SVC_STACK_START
; Set CO-Processor
; little-end，disbale I/D Cache MMU, vector table is 0x00000000
MRC P15, 0, R0, C1, C0, 0 ; Read CP15
LDR R1, =0x00003085 ; set clear bits
BIC R0, R0, R1
MCR P15, 0, R0, C1, C0, 0 ; Write CP15
; Call low level init function,
; disable and clear all IRQs and remap internal ram to 0x00000000.
; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
LDR SP, =SVC_STACK_START
LDR R0, =rt_low_level_init
BLX R0
; Copy Exception Vectors to Internal RAM
LDR R8, =Entry_Point ; Source
LDR R9, =VECTOR_TABLE_START ; Destination
CMP R8, R9
BEQ Setup_Stack
LDMIA R8!, {R0-R7} ; Load Vectors
STMIA R9!, {R0-R7} ; Store Vectors
LDMIA R8!, {R0-R7} ; Load Handler Addresses
STMIA R9!, {R0-R7} ; Store Handler Addresses
Setup_Stack:
; Setup Stack for each mode
libcpu/arm/arm926/start_rvds.S
+23 -52
View File
@@ -20,7 +20,8 @@
; * Change Logs:
; * Date Author Notes
; * 2011-08-14 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
; */
S_FRAME_SIZE EQU (18*4) ;72
@@ -59,46 +60,38 @@ NOINT EQU 0xC0
GET rt_low_level_keil.inc
;----------------------- Stack and Heap Definitions ----------------------------
AREA STACK, NOINIT, READWRITE, ALIGN=3
AREA STACK, NOINIT, READWRITE, ALIGN=2
Stack_Mem
SPACE UND_STK_SIZE
EXPORT UND_STACK_START
UND_STACK_START
ALIGN 8
ALIGN 4
SPACE ABT_STK_SIZE
EXPORT ABT_STACK_START
ABT_STACK_START
ALIGN 8
ALIGN 4
SPACE FIQ_STK_SIZE
EXPORT FIQ_STACK_START
FIQ_STACK_START
ALIGN 8
ALIGN 4
SPACE IRQ_STK_SIZE
EXPORT IRQ_STACK_START
IRQ_STACK_START
ALIGN 8
SPACE SVC_STK_SIZE
EXPORT SVC_STACK_START
SVC_STACK_START
ALIGN 8
ALIGN 4
SPACE SYS_STK_SIZE
EXPORT SYS_STACK_START
SYS_STACK_START
ALIGN 4
SPACE SVC_STK_SIZE
EXPORT SVC_STACK_START
SVC_STACK_START
Stack_Top
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem
SPACE Heap_Size
__heap_limit
PRESERVE8
;--------------Jump vector table------------------------------------------------
EXPORT Entry_Point
@@ -139,25 +132,22 @@ Reset_Handler
; set the cpu to SVC32 mode
MRS R0,CPSR
BIC R0,R0,#MODEMASK
ORR R0,R0,#MODE_SVC
MSR CPSR_CXSF,R0
LDR SP, =SVC_STACK_START
ORR R0,R0,#MODE_SVC:OR:NOINT
MSR CPSR_cxsf,R0
; Set CO-Processor
; little-end，disbale I/D Cache MMU, vector table is 0x00000000
MRC p15, 0, R0, c1, c0, 0 ; Read CP15
LDR R1, =0x00003085 ; set clear bits
BIC R0, R0, R1
MCR p15, 0, R0, c1, c0, 0 ; Write CP15
; Call low level init function,
; disable and clear all IRQs and remap internal ram to 0x00000000.
; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
LDR SP, =SVC_STACK_START
LDR R0, =rt_low_level_init
BLX R0
; Copy Exception Vectors to Internal RAM
LDR R8, =Entry_Point ; Source
LDR R9, =VECTOR_TABLE_START ; Destination
CMP R8, R9
BEQ Setup_Stack
LDMIA R8!, {R0-R7} ; Load Vectors
STMIA R9!, {R0-R7} ; Store Vectors
LDMIA R8!, {R0-R7} ; Load Handler Addresses
STMIA R9!, {R0-R7} ; Store Handler Addresses
Setup_Stack
; Setup Stack for each mode
MRS R0, CPSR
@@ -301,23 +291,4 @@ rt_hw_context_switch_interrupt_do PROC
LDMFD SP!, {R0-R12,LR,PC}^ ; pop new task's R0-R12,LR & PC SPSR to CPSR
ENDP
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + SYS_STK_SIZE)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END