From 40a474fefa27f7bdb56946812b764faa44e25d77 Mon Sep 17 00:00:00 2001
From: SummerGift <SummerGift@qq.com>
Date: Tue, 8 Jan 2019 14:01:02 +0800
Subject: [PATCH] [bsp][stm32] optimize eth driver

---
 bsp/stm32/libraries/HAL_Drivers/drv_eth.c | 56 +++++++++++++++++++++--
 bsp/stm32/libraries/HAL_Drivers/drv_eth.h |  7 +++
 2 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
index 21c2e90cf2..315c1b9890 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
@@ -260,6 +260,9 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
     /* TODO Optimize data send speed*/
     LOG_D("transmit frame lenth :%d", framelength);
 
+    /* wait for unlocked */
+    while (EthHandle.Lock == HAL_LOCKED);
+
     state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
     if (state != HAL_OK)
     {
@@ -410,6 +413,40 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
     LOG_E("eth err");
 }
 
+#ifdef PHY_USING_INTERRUPT_MODE
+static void eth_phy_isr(void *args)
+{
+    rt_uint32_t status = 0;
+    static rt_uint8_t link_status = 1;
+
+    HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
+    LOG_D("phy interrupt status reg is 0x%X", status);
+    HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
+    LOG_D("phy basic status reg is 0x%X", status);
+
+    if (status & PHY_LINKED_STATUS_MASK)
+    {
+        if (link_status == 0)
+        {
+            link_status = 1;
+            LOG_D("link up");
+            /* send link up. */
+            eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
+        }
+    }
+    else
+    {
+        if (link_status == 1)
+        {
+            link_status = 0;
+            LOG_I("link down");
+            /* send link down. */
+            eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
+        }
+    }
+}
+#endif /* PHY_USING_INTERRUPT_MODE */
+
 static uint8_t phy_speed = 0;
 #define PHY_LINK_MASK       (1<<0)
 static void phy_monitor_thread_entry(void *parameter)
@@ -435,12 +472,12 @@ static void phy_monitor_thread_entry(void *parameter)
 
     if (phy_addr == 0xFF)
     {
-        LOG_E("phy not probe!\r\n");
+        LOG_E("phy not probe!");
         return;
     }
     else
     {
-        LOG_D("found a phy, address:0x%02X\r\n", phy_addr);
+        LOG_D("found a phy, address:0x%02X", phy_addr);
     }
 
     /* RESET PHY */
@@ -452,7 +489,7 @@ static void phy_monitor_thread_entry(void *parameter)
     while (1)
     {
         HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
-        LOG_D("PHY BASIC STATUS REG:0x%04X\r\n", status);
+        LOG_D("PHY BASIC STATUS REG:0x%04X", status);
 
         phy_speed_new = 0;
 
@@ -512,10 +549,21 @@ static void phy_monitor_thread_entry(void *parameter)
                 /* send link up. */
                 eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
 
+#ifdef PHY_USING_INTERRUPT_MODE
+                /* configuration intterrupt pin */
+                rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
+                rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
+                rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
+
+                /* enable phy interrupt */
+                HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MSAK_REG, PHY_INT_MASK);
+
+                break;
+#endif
             } /* link up. */
             else
             {
-                LOG_I("link down\r\n");
+                LOG_I("link down");
                 /* send link down. */
                 eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
             }
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
index fbfe08d484..378aca5838 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
@@ -55,6 +55,13 @@
 #define PHY_10M_MASK                ((1<<12) || (1<<13))
 #define PHY_100M_MASK               ((1<<14) || (1<<15))
 #define PHY_FULL_DUPLEX_MASK        ((1<<15) || (1<<13))
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x15U
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MSAK_REG      0x15U
+#define PHY_LINK_CHANGE_FLAG        (1<<2)
+#define PHY_LINK_CHANGE_MASK        (1<<9)
+#define PHY_INT_MASK                0
 
 #endif /* PHY_USING_DM9161CEP */