mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 20:57:20 +08:00
update at91sam9260 project directory structure.
This commit is contained in:
weety
+10
-20
@@ -1,24 +1,14 @@
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import rtconfig
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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src_bsp = ['application.c', 'startup.c', 'board.c']
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src_drv = ['usart.c']
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cwd = str(Dir('#'))
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objs = []
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list = os.listdir(cwd)
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if GetDepend('RT_USING_LED'):
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src_drv += ['led.c']
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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if GetDepend('RT_USING_SDIO'):
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src_drv += ['at91_mci.c']
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if GetDepend('RT_USING_LWIP'):
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src_drv += ['macb.c']
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if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
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src_drv += ['at91_i2c_gpio.c']
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src = File(src_bsp + src_drv)
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CPPPATH = [RTT_ROOT + '/bsp/at91sam9260']
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group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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Return('objs')
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@@ -0,0 +1,11 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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Executable → Regular
Executable → Regular
@@ -0,0 +1,31 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'drivers')
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# add the general drvers.
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src = Split("""
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board.c
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usart.c
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""")
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# add Ethernet drvers.
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if GetDepend('RT_USING_LED'):
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src += ['led.c']
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if GetDepend('RT_USING_SDIO'):
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src += ['at91_mci.c']
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if GetDepend('RT_USING_LWIP'):
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src += ['macb.c']
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if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
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src += ['at91_i2c_gpio.c']
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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Executable → Regular
Executable → Regular
+11
-2
@@ -16,6 +16,7 @@
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#include <rthw.h>
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#include "board.h"
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#include <mmu.h>
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/**
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* @addtogroup at91sam9260
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@@ -24,13 +25,21 @@
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extern void rt_hw_clock_init(void);
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extern void rt_hw_mmu_init(void);
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extern void rt_hw_get_clock(void);
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extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
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extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
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extern void rt_dbgu_isr(void);
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static struct mem_desc at91_mem_desc[] = {
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{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
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{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */
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{ 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */
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{ 0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB }, /* 4K SRAM0 + 4k SRAM1 */
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{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */
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};
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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@@ -132,7 +141,7 @@ void rt_hw_board_init()
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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/* initialize mmu */
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rt_hw_mmu_init();
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rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
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/* initialize timer0 */
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rt_hw_timer_init();
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Executable → Regular
Executable → Regular
Executable → Regular
Executable → Regular
Executable → Regular
@@ -0,0 +1,26 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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CPPPATH = [cwd]
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# The set of source files associated with this SConscript file.
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if rtconfig.PLATFORM == 'armcc':
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src = Glob('*.c') + Glob('*_rvds.S')
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if rtconfig.PLATFORM == 'gcc':
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src = Glob('*.c') + Glob('*_gcc.S') + Glob('*_init.S')
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if rtconfig.PLATFORM == 'iar':
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src = Glob('*.c') + Glob('*_iar.S')
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if rtconfig.PLATFORM == 'cl':
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src = Glob('*.c')
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if rtconfig.PLATFORM == 'mingw':
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src = Glob('*.c')
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group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,63 @@
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/*
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* File : at91_aic.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#ifndef AT91_AIC_H
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#define AT91_AIC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AIC_IRQS 32
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#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
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#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
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#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
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#define AT91_AIC_SRCTYPE_LOW (0 << 5)
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#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
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#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
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#define AT91_AIC_SRCTYPE_RISING (3 << 5)
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#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
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#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
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#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
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#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
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#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
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#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
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#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
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#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
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#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
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#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
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#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
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#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
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#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
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#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
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#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
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#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
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#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
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#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
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#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
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#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
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#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
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#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -0,0 +1,21 @@
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#ifndef __AT91_PDC_H__
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#define __AT91_PDC_H__
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#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
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#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
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#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
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#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
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#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
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#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
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#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
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#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
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#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
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#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
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#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
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#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
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#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
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#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
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#endif
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@@ -0,0 +1,57 @@
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/*
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* File : at91_pio.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#ifndef AT91_PIO_H
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#define AT91_PIO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PIO_PER 0x00 /* Enable Register */
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#define PIO_PDR 0x04 /* Disable Register */
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#define PIO_PSR 0x08 /* Status Register */
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#define PIO_OER 0x10 /* Output Enable Register */
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#define PIO_ODR 0x14 /* Output Disable Register */
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#define PIO_OSR 0x18 /* Output Status Register */
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#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
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#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
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#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
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#define PIO_SODR 0x30 /* Set Output Data Register */
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#define PIO_CODR 0x34 /* Clear Output Data Register */
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#define PIO_ODSR 0x38 /* Output Data Status Register */
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#define PIO_PDSR 0x3c /* Pin Data Status Register */
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#define PIO_IER 0x40 /* Interrupt Enable Register */
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#define PIO_IDR 0x44 /* Interrupt Disable Register */
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#define PIO_IMR 0x48 /* Interrupt Mask Register */
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#define PIO_ISR 0x4c /* Interrupt Status Register */
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#define PIO_MDER 0x50 /* Multi-driver Enable Register */
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#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
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#define PIO_MDSR 0x58 /* Multi-driver Status Register */
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#define PIO_PUDR 0x60 /* Pull-up Disable Register */
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#define PIO_PUER 0x64 /* Pull-up Enable Register */
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#define PIO_PUSR 0x68 /* Pull-up Status Register */
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#define PIO_ASR 0x70 /* Peripheral A Select Register */
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#define PIO_BSR 0x74 /* Peripheral B Select Register */
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#define PIO_ABSR 0x78 /* AB Status Register */
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#define PIO_OWER 0xa0 /* Output Write Enable Register */
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#define PIO_OWDR 0xa4 /* Output Write Disable Register */
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#define PIO_OWSR 0xa8 /* Output Write Status Register */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -0,0 +1,40 @@
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/*
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* File : at91_pit.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
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*
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* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
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*/
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#ifndef AT91_PIT_H
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#define AT91_PIT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
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#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
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#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
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#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
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#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
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#define AT91_PIT_PITS (1 << 0) /* Timer Status */
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#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
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#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
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#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
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#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -0,0 +1,141 @@
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/*
|
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* File : at91_pmc.h
|
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* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
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#ifndef AT91_PMC_H
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#define AT91_PMC_H
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||||
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#ifdef __cplusplus
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extern "C" {
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||||
#endif
|
||||
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||||
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
|
||||
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
|
||||
|
||||
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
|
||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */
|
||||
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
||||
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
||||
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
|
||||
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
||||
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
|
||||
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
||||
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
||||
|
||||
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
|
||||
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
||||
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
||||
|
||||
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
|
||||
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
||||
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
||||
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
||||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
||||
|
||||
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
|
||||
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
|
||||
#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
||||
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
||||
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
|
||||
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
|
||||
#define AT91_PMC_USBDIV_1 (0 << 28)
|
||||
#define AT91_PMC_USBDIV_2 (1 << 28)
|
||||
#define AT91_PMC_USBDIV_4 (2 << 28)
|
||||
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
|
||||
|
||||
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
|
||||
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
|
||||
#define AT91_PMC_CSS_SLOW (0 << 0)
|
||||
#define AT91_PMC_CSS_MAIN (1 << 0)
|
||||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << 2)
|
||||
#define AT91_PMC_PRES_2 (1 << 2)
|
||||
#define AT91_PMC_PRES_4 (2 << 2)
|
||||
#define AT91_PMC_PRES_8 (3 << 2)
|
||||
#define AT91_PMC_PRES_16 (4 << 2)
|
||||
#define AT91_PMC_PRES_32 (5 << 2)
|
||||
#define AT91_PMC_PRES_64 (6 << 2)
|
||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
||||
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
|
||||
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
|
||||
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
|
||||
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
|
||||
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
|
||||
#define AT91_PMC_PDIV_1 (0 << 12)
|
||||
#define AT91_PMC_PDIV_2 (1 << 12)
|
||||
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
|
||||
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
|
||||
#define AT91_PMC_PLLADIV2_ON (1 << 12)
|
||||
|
||||
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
|
||||
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
|
||||
#define AT91_PMC_USBS_PLLA (0 << 0)
|
||||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||
|
||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
|
||||
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
|
||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
|
||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* File : at91_rstc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_RSTC_H
|
||||
#define AT91_RSTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
|
||||
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
|
||||
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
|
||||
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
|
||||
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
|
||||
|
||||
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
|
||||
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
|
||||
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
|
||||
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
|
||||
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
|
||||
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
|
||||
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
|
||||
#define AT91_RSTC_RSTTYP_USER (4 << 8)
|
||||
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
|
||||
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
|
||||
|
||||
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
|
||||
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
|
||||
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* File : at91_serial.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_SERIAL_H
|
||||
#define AT91_SERIAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_US_CR 0x00 /* Control Register */
|
||||
#define AT91_US_RSTRX (1 << 2) /* Reset Receiver */
|
||||
#define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */
|
||||
#define AT91_US_RXEN (1 << 4) /* Receiver Enable */
|
||||
#define AT91_US_RXDIS (1 << 5) /* Receiver Disable */
|
||||
#define AT91_US_TXEN (1 << 6) /* Transmitter Enable */
|
||||
#define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */
|
||||
#define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */
|
||||
#define AT91_US_STTBRK (1 << 9) /* Start Break */
|
||||
#define AT91_US_STPBRK (1 << 10) /* Stop Break */
|
||||
#define AT91_US_STTTO (1 << 11) /* Start Time-out */
|
||||
#define AT91_US_SENDA (1 << 12) /* Send Address */
|
||||
#define AT91_US_RSTIT (1 << 13) /* Reset Iterations */
|
||||
#define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
|
||||
#define AT91_US_RETTO (1 << 15) /* Rearm Time-out */
|
||||
#define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
|
||||
#define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
|
||||
#define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */
|
||||
#define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */
|
||||
|
||||
#define AT91_US_MR 0x04 /* Mode Register */
|
||||
#define AT91_US_USMODE (0xf << 0) /* Mode of the USART */
|
||||
#define AT91_US_USMODE_NORMAL 0
|
||||
#define AT91_US_USMODE_RS485 1
|
||||
#define AT91_US_USMODE_HWHS 2
|
||||
#define AT91_US_USMODE_MODEM 3
|
||||
#define AT91_US_USMODE_ISO7816_T0 4
|
||||
#define AT91_US_USMODE_ISO7816_T1 6
|
||||
#define AT91_US_USMODE_IRDA 8
|
||||
#define AT91_US_USCLKS (3 << 4) /* Clock Selection */
|
||||
#define AT91_US_USCLKS_MCK (0 << 4)
|
||||
#define AT91_US_USCLKS_MCK_DIV8 (1 << 4)
|
||||
#define AT91_US_USCLKS_SCK (3 << 4)
|
||||
#define AT91_US_CHRL (3 << 6) /* Character Length */
|
||||
#define AT91_US_CHRL_5 (0 << 6)
|
||||
#define AT91_US_CHRL_6 (1 << 6)
|
||||
#define AT91_US_CHRL_7 (2 << 6)
|
||||
#define AT91_US_CHRL_8 (3 << 6)
|
||||
#define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */
|
||||
#define AT91_US_PAR (7 << 9) /* Parity Type */
|
||||
#define AT91_US_PAR_EVEN (0 << 9)
|
||||
#define AT91_US_PAR_ODD (1 << 9)
|
||||
#define AT91_US_PAR_SPACE (2 << 9)
|
||||
#define AT91_US_PAR_MARK (3 << 9)
|
||||
#define AT91_US_PAR_NONE (4 << 9)
|
||||
#define AT91_US_PAR_MULTI_DROP (6 << 9)
|
||||
#define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */
|
||||
#define AT91_US_NBSTOP_1 (0 << 12)
|
||||
#define AT91_US_NBSTOP_1_5 (1 << 12)
|
||||
#define AT91_US_NBSTOP_2 (2 << 12)
|
||||
#define AT91_US_CHMODE (3 << 14) /* Channel Mode */
|
||||
#define AT91_US_CHMODE_NORMAL (0 << 14)
|
||||
#define AT91_US_CHMODE_ECHO (1 << 14)
|
||||
#define AT91_US_CHMODE_LOC_LOOP (2 << 14)
|
||||
#define AT91_US_CHMODE_REM_LOOP (3 << 14)
|
||||
#define AT91_US_MSBF (1 << 16) /* Bit Order */
|
||||
#define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */
|
||||
#define AT91_US_CLKO (1 << 18) /* Clock Output Select */
|
||||
#define AT91_US_OVER (1 << 19) /* Oversampling Mode */
|
||||
#define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
|
||||
#define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */
|
||||
#define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */
|
||||
#define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
|
||||
|
||||
#define AT91_US_IER 0x08 /* Interrupt Enable Register */
|
||||
#define AT91_US_RXRDY (1 << 0) /* Receiver Ready */
|
||||
#define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */
|
||||
#define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */
|
||||
#define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */
|
||||
#define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
|
||||
#define AT91_US_OVRE (1 << 5) /* Overrun Error */
|
||||
#define AT91_US_FRAME (1 << 6) /* Framing Error */
|
||||
#define AT91_US_PARE (1 << 7) /* Parity Error */
|
||||
#define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */
|
||||
#define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */
|
||||
#define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
|
||||
#define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
|
||||
#define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */
|
||||
#define AT91_US_NACK (1 << 13) /* Non Acknowledge */
|
||||
#define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
|
||||
#define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
|
||||
#define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
|
||||
#define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */
|
||||
#define AT91_US_RI (1 << 20) /* RI */
|
||||
#define AT91_US_DSR (1 << 21) /* DSR */
|
||||
#define AT91_US_DCD (1 << 22) /* DCD */
|
||||
#define AT91_US_CTS (1 << 23) /* CTS */
|
||||
|
||||
#define AT91_US_IDR 0x0c /* Interrupt Disable Register */
|
||||
#define AT91_US_IMR 0x10 /* Interrupt Mask Register */
|
||||
#define AT91_US_CSR 0x14 /* Channel Status Register */
|
||||
#define AT91_US_RHR 0x18 /* Receiver Holding Register */
|
||||
#define AT91_US_THR 0x1c /* Transmitter Holding Register */
|
||||
#define AT91_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
|
||||
|
||||
#define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */
|
||||
#define AT91_US_CD (0xffff << 0) /* Clock Divider */
|
||||
|
||||
#define AT91_US_RTOR 0x24 /* Receiver Time-out Register */
|
||||
#define AT91_US_TO (0xffff << 0) /* Time-out Value */
|
||||
|
||||
#define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */
|
||||
#define AT91_US_TG (0xff << 0) /* Timeguard Value */
|
||||
|
||||
#define AT91_US_FIDI 0x40 /* FI DI Ratio Register */
|
||||
#define AT91_US_NER 0x44 /* Number of Errors Register */
|
||||
#define AT91_US_IF 0x4c /* IrDA Filter Register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* File : at91_shdwc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_SHDWC_H
|
||||
#define AT91_SHDWC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
|
||||
#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
|
||||
#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
|
||||
|
||||
#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
|
||||
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
|
||||
#define AT91_SHDW_WKMODE0_NONE 0
|
||||
#define AT91_SHDW_WKMODE0_HIGH 1
|
||||
#define AT91_SHDW_WKMODE0_LOW 2
|
||||
#define AT91_SHDW_WKMODE0_ANYLEVEL 3
|
||||
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
|
||||
#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
|
||||
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
|
||||
|
||||
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
|
||||
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
|
||||
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
|
||||
#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
* File : at91_tc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_TC_H
|
||||
#define AT91_TC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
|
||||
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
|
||||
|
||||
#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
|
||||
#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
|
||||
#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
|
||||
#define AT91_TC_TC0XC0S_NONE (1 << 0)
|
||||
#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
|
||||
#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
|
||||
#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
|
||||
#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
|
||||
#define AT91_TC_TC1XC1S_NONE (1 << 2)
|
||||
#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
|
||||
#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
|
||||
#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
|
||||
#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
|
||||
#define AT91_TC_TC2XC2S_NONE (1 << 4)
|
||||
#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
|
||||
#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
|
||||
|
||||
|
||||
#define AT91_TC_CCR 0x00 /* Channel Control Register */
|
||||
#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
|
||||
#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
|
||||
#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
|
||||
|
||||
#define AT91_TC_CMR 0x04 /* Channel Mode Register */
|
||||
#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
|
||||
#define AT91_TC_TIMER_CLOCK1 (0 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK2 (1 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK3 (2 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK4 (3 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK5 (4 << 0)
|
||||
#define AT91_TC_XC0 (5 << 0)
|
||||
#define AT91_TC_XC1 (6 << 0)
|
||||
#define AT91_TC_XC2 (7 << 0)
|
||||
#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
|
||||
#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
|
||||
#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
|
||||
#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
|
||||
#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
|
||||
#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
|
||||
#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
|
||||
#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
|
||||
#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
|
||||
#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
|
||||
|
||||
#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
|
||||
#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
|
||||
#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
|
||||
#define AT91_TC_EEVTEDG_NONE (0 << 8)
|
||||
#define AT91_TC_EEVTEDG_RISING (1 << 8)
|
||||
#define AT91_TC_EEVTEDG_FALLING (2 << 8)
|
||||
#define AT91_TC_EEVTEDG_BOTH (3 << 8)
|
||||
#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
|
||||
#define AT91_TC_EEVT_TIOB (0 << 10)
|
||||
#define AT91_TC_EEVT_XC0 (1 << 10)
|
||||
#define AT91_TC_EEVT_XC1 (2 << 10)
|
||||
#define AT91_TC_EEVT_XC2 (3 << 10)
|
||||
#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
|
||||
#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
|
||||
#define AT91_TC_WAVESEL_UP (0 << 13)
|
||||
#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
|
||||
#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
|
||||
#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
|
||||
#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
|
||||
#define AT91_TC_ACPA_NONE (0 << 16)
|
||||
#define AT91_TC_ACPA_SET (1 << 16)
|
||||
#define AT91_TC_ACPA_CLEAR (2 << 16)
|
||||
#define AT91_TC_ACPA_TOGGLE (3 << 16)
|
||||
#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
|
||||
#define AT91_TC_ACPC_NONE (0 << 18)
|
||||
#define AT91_TC_ACPC_SET (1 << 18)
|
||||
#define AT91_TC_ACPC_CLEAR (2 << 18)
|
||||
#define AT91_TC_ACPC_TOGGLE (3 << 18)
|
||||
#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
|
||||
#define AT91_TC_AEEVT_NONE (0 << 20)
|
||||
#define AT91_TC_AEEVT_SET (1 << 20)
|
||||
#define AT91_TC_AEEVT_CLEAR (2 << 20)
|
||||
#define AT91_TC_AEEVT_TOGGLE (3 << 20)
|
||||
#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
|
||||
#define AT91_TC_ASWTRG_NONE (0 << 22)
|
||||
#define AT91_TC_ASWTRG_SET (1 << 22)
|
||||
#define AT91_TC_ASWTRG_CLEAR (2 << 22)
|
||||
#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
|
||||
#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
|
||||
#define AT91_TC_BCPB_NONE (0 << 24)
|
||||
#define AT91_TC_BCPB_SET (1 << 24)
|
||||
#define AT91_TC_BCPB_CLEAR (2 << 24)
|
||||
#define AT91_TC_BCPB_TOGGLE (3 << 24)
|
||||
#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
|
||||
#define AT91_TC_BCPC_NONE (0 << 26)
|
||||
#define AT91_TC_BCPC_SET (1 << 26)
|
||||
#define AT91_TC_BCPC_CLEAR (2 << 26)
|
||||
#define AT91_TC_BCPC_TOGGLE (3 << 26)
|
||||
#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
|
||||
#define AT91_TC_BEEVT_NONE (0 << 28)
|
||||
#define AT91_TC_BEEVT_SET (1 << 28)
|
||||
#define AT91_TC_BEEVT_CLEAR (2 << 28)
|
||||
#define AT91_TC_BEEVT_TOGGLE (3 << 28)
|
||||
#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
|
||||
#define AT91_TC_BSWTRG_NONE (0 << 30)
|
||||
#define AT91_TC_BSWTRG_SET (1 << 30)
|
||||
#define AT91_TC_BSWTRG_CLEAR (2 << 30)
|
||||
#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
|
||||
|
||||
#define AT91_TC_CV 0x10 /* Counter Value */
|
||||
#define AT91_TC_RA 0x14 /* Register A */
|
||||
#define AT91_TC_RB 0x18 /* Register B */
|
||||
#define AT91_TC_RC 0x1c /* Register C */
|
||||
|
||||
#define AT91_TC_SR 0x20 /* Status Register */
|
||||
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
|
||||
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
|
||||
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
|
||||
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
|
||||
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
|
||||
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
|
||||
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
|
||||
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
|
||||
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
|
||||
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
|
||||
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
|
||||
|
||||
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
|
||||
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
|
||||
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* File : at91sam9260_matrix.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_MATRIX_H
|
||||
#define AT91SAM9260_MATRIX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
* File : at91sam926x.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_H
|
||||
#define AT91SAM9260_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "at91_aic.h"
|
||||
#include "at91_pit.h"
|
||||
#include "at91_pmc.h"
|
||||
#include "at91_rstc.h"
|
||||
#include "at91_shdwc.h"
|
||||
#include "at91sam9260_matrix.h"
|
||||
#include "at91_pio.h"
|
||||
#include "at91_serial.h"
|
||||
#include "at91_tc.h"
|
||||
#include "at91_pdc.h"
|
||||
#include "io.h"
|
||||
#include "irq.h"
|
||||
#include "gpio.h"
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
|
||||
#define AT91SAM9260_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9260_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9260_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
|
||||
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
|
||||
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
|
||||
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
|
||||
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
|
||||
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
|
||||
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
|
||||
#define AT91SAM9260_ID_US3 23 /* USART 3 */
|
||||
#define AT91SAM9260_ID_US4 24 /* USART 4 */
|
||||
#define AT91SAM9260_ID_US5 25 /* USART 5 */
|
||||
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
|
||||
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
|
||||
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
|
||||
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
|
||||
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9260_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9260_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9260_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9260_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9260_BASE_UDP 0xfffa4000
|
||||
#define AT91SAM9260_BASE_MCI 0xfffa8000
|
||||
#define AT91SAM9260_BASE_TWI 0xfffac000
|
||||
#define AT91SAM9260_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9260_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9260_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9260_BASE_SSC 0xfffbc000
|
||||
#define AT91SAM9260_BASE_ISI 0xfffc0000
|
||||
#define AT91SAM9260_BASE_EMAC 0xfffc4000
|
||||
#define AT91SAM9260_BASE_SPI0 0xfffc8000
|
||||
#define AT91SAM9260_BASE_SPI1 0xfffcc000
|
||||
#define AT91SAM9260_BASE_US3 0xfffd0000
|
||||
#define AT91SAM9260_BASE_US4 0xfffd4000
|
||||
#define AT91SAM9260_BASE_US5 0xfffd8000
|
||||
#define AT91SAM9260_BASE_TCB1 0xfffdc000
|
||||
#define AT91SAM9260_BASE_TC3 0xfffdc000
|
||||
#define AT91SAM9260_BASE_TC4 0xfffdc040
|
||||
#define AT91SAM9260_BASE_TC5 0xfffdc080
|
||||
#define AT91SAM9260_BASE_ADC 0xfffe0000
|
||||
#define AT91_BASE_SYS 0xffffe800
|
||||
#define AT91SAM9260_BASE_DBGU 0xfffff200
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
|
||||
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
|
||||
|
||||
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
|
||||
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
|
||||
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
|
||||
#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
|
||||
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
|
||||
|
||||
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
|
||||
|
||||
|
||||
/* Serial ports */
|
||||
#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
|
||||
|
||||
/* External Memory Map */
|
||||
#define AT91_CHIPSELECT_0 0x10000000
|
||||
#define AT91_CHIPSELECT_1 0x20000000
|
||||
#define AT91_CHIPSELECT_2 0x30000000
|
||||
#define AT91_CHIPSELECT_3 0x40000000
|
||||
#define AT91_CHIPSELECT_4 0x50000000
|
||||
#define AT91_CHIPSELECT_5 0x60000000
|
||||
#define AT91_CHIPSELECT_6 0x70000000
|
||||
#define AT91_CHIPSELECT_7 0x80000000
|
||||
|
||||
/* SDRAM */
|
||||
#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
|
||||
|
||||
/* Clocks */
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
|
||||
/*****************************/
|
||||
/* CPU Mode */
|
||||
/*****************************/
|
||||
#define USERMODE 0x10
|
||||
#define FIQMODE 0x11
|
||||
#define IRQMODE 0x12
|
||||
#define SVCMODE 0x13
|
||||
#define ABORTMODE 0x17
|
||||
#define UNDEFMODE 0x1b
|
||||
#define MODEMASK 0x1f
|
||||
#define NOINT 0xc0
|
||||
|
||||
struct rt_hw_register
|
||||
{
|
||||
rt_uint32_t r0;
|
||||
rt_uint32_t r1;
|
||||
rt_uint32_t r2;
|
||||
rt_uint32_t r3;
|
||||
rt_uint32_t r4;
|
||||
rt_uint32_t r5;
|
||||
rt_uint32_t r6;
|
||||
rt_uint32_t r7;
|
||||
rt_uint32_t r8;
|
||||
rt_uint32_t r9;
|
||||
rt_uint32_t r10;
|
||||
rt_uint32_t fp;
|
||||
rt_uint32_t ip;
|
||||
rt_uint32_t sp;
|
||||
rt_uint32_t lr;
|
||||
rt_uint32_t pc;
|
||||
rt_uint32_t cpsr;
|
||||
rt_uint32_t ORIG_r0;
|
||||
};
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
extern struct clk *clk_get(const char *id);
|
||||
extern rt_uint32_t clk_get_rate(struct clk *clk);
|
||||
extern void rt_hw_clock_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <at91_aic.h>
|
||||
|
||||
#define PIN_BASE AIC_IRQS
|
||||
|
||||
#define MAX_GPIO_BANKS 3
|
||||
|
||||
#define PIN_IRQS (MAX_GPIO_BANKS*32)
|
||||
|
||||
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
|
||||
|
||||
#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
|
||||
#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
|
||||
#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
|
||||
#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
|
||||
#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
|
||||
#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
|
||||
#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
|
||||
#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
|
||||
#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
|
||||
#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
|
||||
#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
|
||||
#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
|
||||
#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
|
||||
#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
|
||||
#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
|
||||
#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
|
||||
#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
|
||||
#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
|
||||
#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
|
||||
#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
|
||||
#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
|
||||
#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
|
||||
#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
|
||||
#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
|
||||
#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
|
||||
#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
|
||||
#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
|
||||
#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
|
||||
#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
|
||||
#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
|
||||
#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
|
||||
#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
|
||||
|
||||
#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
|
||||
#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
|
||||
#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
|
||||
#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
|
||||
#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
|
||||
#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
|
||||
#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
|
||||
#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
|
||||
#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
|
||||
#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
|
||||
#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
|
||||
#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
|
||||
#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
|
||||
#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
|
||||
#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
|
||||
#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
|
||||
#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
|
||||
#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
|
||||
#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
|
||||
#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
|
||||
#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
|
||||
#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
|
||||
#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
|
||||
#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
|
||||
#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
|
||||
#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
|
||||
#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
|
||||
#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
|
||||
#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
|
||||
#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
|
||||
#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
|
||||
#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
|
||||
|
||||
#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
|
||||
#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
|
||||
#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
|
||||
#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
|
||||
#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
|
||||
#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
|
||||
#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
|
||||
#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
|
||||
#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
|
||||
#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
|
||||
#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
|
||||
#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
|
||||
#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
|
||||
#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
|
||||
#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
|
||||
#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
|
||||
#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
|
||||
#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
|
||||
#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
|
||||
#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
|
||||
#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
|
||||
#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
|
||||
#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
|
||||
#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
|
||||
#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
|
||||
#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
|
||||
#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
|
||||
#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
|
||||
#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
|
||||
#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
|
||||
#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
|
||||
#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
|
||||
|
||||
|
||||
rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
|
||||
{
|
||||
return gpio;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,387 @@
|
||||
/*
|
||||
* File : interrupt.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include "at91sam926x.h"
|
||||
|
||||
#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
|
||||
|
||||
extern rt_uint32_t rt_interrupt_nest;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
struct rt_irq_desc irq_desc[MAX_HANDLERS];
|
||||
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
rt_uint32_t at91_extern_irq;
|
||||
|
||||
#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
|
||||
|
||||
/*
|
||||
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
||||
*/
|
||||
static rt_uint32_t at91sam9260_default_irq_priority[MAX_HANDLERS] = {
|
||||
7, /* Advanced Interrupt Controller */
|
||||
7, /* System Peripherals */
|
||||
1, /* Parallel IO Controller A */
|
||||
1, /* Parallel IO Controller B */
|
||||
1, /* Parallel IO Controller C */
|
||||
0, /* Analog-to-Digital Converter */
|
||||
5, /* USART 0 */
|
||||
5, /* USART 1 */
|
||||
5, /* USART 2 */
|
||||
0, /* Multimedia Card Interface */
|
||||
2, /* USB Device Port */
|
||||
6, /* Two-Wire Interface */
|
||||
5, /* Serial Peripheral Interface 0 */
|
||||
5, /* Serial Peripheral Interface 1 */
|
||||
5, /* Serial Synchronous Controller */
|
||||
0,
|
||||
0,
|
||||
0, /* Timer Counter 0 */
|
||||
0, /* Timer Counter 1 */
|
||||
0, /* Timer Counter 2 */
|
||||
2, /* USB Host port */
|
||||
3, /* Ethernet */
|
||||
0, /* Image Sensor Interface */
|
||||
5, /* USART 3 */
|
||||
5, /* USART 4 */
|
||||
5, /* USART 5 */
|
||||
0, /* Timer Counter 3 */
|
||||
0, /* Timer Counter 4 */
|
||||
0, /* Timer Counter 5 */
|
||||
0, /* Advanced Interrupt Controller */
|
||||
0, /* Advanced Interrupt Controller */
|
||||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
/**
|
||||
* @addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
void rt_hw_interrupt_mask(int irq);
|
||||
void rt_hw_interrupt_umask(int irq);
|
||||
|
||||
rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param)
|
||||
{
|
||||
rt_uint32_t isr, pio, irq_n;
|
||||
void *parameter;
|
||||
|
||||
if (vector == AT91SAM9260_ID_PIOA)
|
||||
{
|
||||
pio = AT91_PIOA;
|
||||
irq_n = AIC_IRQS;
|
||||
}
|
||||
else if (vector == AT91SAM9260_ID_PIOB)
|
||||
{
|
||||
pio = AT91_PIOB;
|
||||
irq_n = AIC_IRQS + 32;
|
||||
}
|
||||
else if (vector == AT91SAM9260_ID_PIOC)
|
||||
{
|
||||
pio = AT91_PIOC;
|
||||
irq_n = AIC_IRQS + 32*2;
|
||||
}
|
||||
else
|
||||
return RT_NULL;
|
||||
isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR);
|
||||
while (isr)
|
||||
{
|
||||
if (isr & 1)
|
||||
{
|
||||
parameter = irq_desc[irq_n].param;
|
||||
irq_desc[irq_n].handler(irq_n, parameter);
|
||||
}
|
||||
isr >>= 1;
|
||||
irq_n++;
|
||||
}
|
||||
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the AIC interrupt controller.
|
||||
*/
|
||||
void at91_aic_init(rt_uint32_t *priority)
|
||||
{
|
||||
rt_uint32_t i;
|
||||
|
||||
/*
|
||||
* The IVR is used by macro get_irqnr_and_base to read and verify.
|
||||
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
|
||||
*/
|
||||
for (i = 0; i < AIC_IRQS; i++) {
|
||||
/* Put irq number in Source Vector Register: */
|
||||
at91_sys_write(AT91_AIC_SVR(i), i);
|
||||
/* Active Low interrupt, with the specified priority */
|
||||
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
|
||||
//AT91_AIC_SRCTYPE_FALLING
|
||||
|
||||
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
|
||||
if (i < 8)
|
||||
at91_sys_write(AT91_AIC_EOICR, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
|
||||
* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
|
||||
*/
|
||||
at91_sys_write(AT91_AIC_SPU, AIC_IRQS);
|
||||
|
||||
/* No debugging in AIC: Debug (Protect) Control Register */
|
||||
at91_sys_write(AT91_AIC_DCR, 0);
|
||||
|
||||
/* Disable and clear all interrupts initially */
|
||||
at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
|
||||
at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
|
||||
static void at91_gpio_irq_init()
|
||||
{
|
||||
int i, idx;
|
||||
char *name[] = {"PIOA", "PIOB", "PIOC"};
|
||||
|
||||
at91_sys_write(AT91_PIOA+PIO_IDR, 0xffffffff);
|
||||
at91_sys_write(AT91_PIOB+PIO_IDR, 0xffffffff);
|
||||
at91_sys_write(AT91_PIOC+PIO_IDR, 0xffffffff);
|
||||
|
||||
idx = AT91SAM9260_ID_PIOA;
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
|
||||
irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
|
||||
irq_desc[idx].param = RT_NULL;
|
||||
irq_desc[idx].counter = 0;
|
||||
idx++;
|
||||
}
|
||||
|
||||
rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
|
||||
rt_hw_interrupt_umask(AT91SAM9260_ID_PIOB);
|
||||
rt_hw_interrupt_umask(AT91SAM9260_ID_PIOC);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_int32_t i;
|
||||
register rt_uint32_t idx;
|
||||
rt_uint32_t *priority = at91sam9260_default_irq_priority;
|
||||
|
||||
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
|
||||
| (1 << AT91SAM9260_ID_IRQ2);
|
||||
|
||||
/* Initialize the AIC interrupt controller */
|
||||
at91_aic_init(priority);
|
||||
|
||||
/* init exceptions table */
|
||||
for(idx=0; idx < MAX_HANDLERS; idx++)
|
||||
{
|
||||
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
|
||||
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
|
||||
irq_desc[idx].param = RT_NULL;
|
||||
irq_desc[idx].counter = 0;
|
||||
}
|
||||
|
||||
at91_gpio_irq_init();
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
}
|
||||
|
||||
static void at91_gpio_irq_mask(int irq)
|
||||
{
|
||||
rt_uint32_t pin, pio, bank;
|
||||
|
||||
bank = (irq - AIC_IRQS)>>5;
|
||||
|
||||
if (bank == 0)
|
||||
{
|
||||
pio = AT91_PIOA;
|
||||
}
|
||||
else if (bank == 1)
|
||||
{
|
||||
pio = AT91_PIOB;
|
||||
}
|
||||
else if (bank == 2)
|
||||
{
|
||||
pio = AT91_PIOC;
|
||||
}
|
||||
else
|
||||
return;
|
||||
pin = 1 << ((irq - AIC_IRQS) & 31);
|
||||
at91_sys_write(pio+PIO_IDR, pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int irq)
|
||||
{
|
||||
if (irq >= AIC_IRQS)
|
||||
{
|
||||
at91_gpio_irq_mask(irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable interrupt on AIC */
|
||||
at91_sys_write(AT91_AIC_IDCR, 1 << irq);
|
||||
}
|
||||
}
|
||||
|
||||
static void at91_gpio_irq_umask(int irq)
|
||||
{
|
||||
rt_uint32_t pin, pio, bank;
|
||||
|
||||
bank = (irq - AIC_IRQS)>>5;
|
||||
|
||||
if (bank == 0)
|
||||
{
|
||||
pio = AT91_PIOA;
|
||||
}
|
||||
else if (bank == 1)
|
||||
{
|
||||
pio = AT91_PIOB;
|
||||
}
|
||||
else if (bank == 2)
|
||||
{
|
||||
pio = AT91_PIOC;
|
||||
}
|
||||
else
|
||||
return;
|
||||
pin = 1 << ((irq - AIC_IRQS) & 31);
|
||||
at91_sys_write(pio+PIO_IER, pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int irq)
|
||||
{
|
||||
if (irq >= AIC_IRQS)
|
||||
{
|
||||
at91_gpio_irq_umask(irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable interrupt on AIC */
|
||||
at91_sys_write(AT91_AIC_IECR, 1 << irq);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param handler the interrupt service routine to be installed
|
||||
* @param param the interrupt service function parameter
|
||||
* @param name the interrupt name
|
||||
* @return old handler
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if(vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = irq_desc[vector].handler;
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
|
||||
irq_desc[vector].handler = (rt_isr_handler_t)handler;
|
||||
irq_desc[vector].param = param;
|
||||
irq_desc[vector].counter = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
static int at91_aic_set_type(unsigned irq, unsigned type)
|
||||
{
|
||||
unsigned int smr, srctype;
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
srctype = AT91_AIC_SRCTYPE_HIGH;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
srctype = AT91_AIC_SRCTYPE_RISING;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
|
||||
srctype = AT91_AIC_SRCTYPE_LOW;
|
||||
else
|
||||
return -1;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
|
||||
srctype = AT91_AIC_SRCTYPE_FALLING;
|
||||
else
|
||||
return -1;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
|
||||
at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
void list_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
rt_kprintf("number\tcount\tname\n");
|
||||
for (irq = 0; irq < MAX_HANDLERS; irq++)
|
||||
{
|
||||
if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
|
||||
{
|
||||
rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT(list_irq, list system irq);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* File : io.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#define AT91_BASE_SYS 0xffffe800
|
||||
|
||||
#define IO_SPACE_LIMIT 0xFFFFFFFF
|
||||
|
||||
#define readb(a) (*(volatile unsigned char *)(a))
|
||||
#define readw(a) (*(volatile unsigned short *)(a))
|
||||
#define readl(a) (*(volatile unsigned int *)(a))
|
||||
|
||||
#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
|
||||
|
||||
rt_inline unsigned int at91_sys_read(unsigned int reg_offset)
|
||||
{
|
||||
unsigned int addr = AT91_BASE_SYS;
|
||||
|
||||
return readl(addr + reg_offset);
|
||||
}
|
||||
|
||||
rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
|
||||
{
|
||||
unsigned int addr = AT91_BASE_SYS;
|
||||
|
||||
writel(value, addr + reg_offset);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* File : irq.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_H__
|
||||
#define __IRQ_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IRQ line status.
|
||||
*
|
||||
* Bits 0-7 are reserved
|
||||
*
|
||||
* IRQ types
|
||||
*/
|
||||
#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
|
||||
#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
|
||||
#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
|
||||
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
|
||||
#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
|
||||
#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
|
||||
#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
|
||||
#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* File : reset.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety modified from mini2440
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "at91sam926x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
void machine_reset(void)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
}
|
||||
|
||||
void machine_shutdown(void)
|
||||
{
|
||||
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,382 @@
|
||||
/*
|
||||
* File : start.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http:/*openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#define CONFIG_STACKSIZE 512
|
||||
#define S_FRAME_SIZE 72
|
||||
|
||||
#define S_OLD_R0 68
|
||||
#define S_PSR 64
|
||||
#define S_PC 60
|
||||
#define S_LR 56
|
||||
#define S_SP 52
|
||||
|
||||
#define S_IP 48
|
||||
#define S_FP 44
|
||||
#define S_R10 40
|
||||
#define S_R9 36
|
||||
#define S_R8 32
|
||||
#define S_R7 28
|
||||
#define S_R6 24
|
||||
#define S_R5 20
|
||||
#define S_R4 16
|
||||
#define S_R3 12
|
||||
#define S_R2 8
|
||||
#define S_R1 4
|
||||
#define S_R0 0
|
||||
|
||||
.equ USERMODE, 0x10
|
||||
.equ FIQMODE, 0x11
|
||||
.equ IRQMODE, 0x12
|
||||
.equ SVCMODE, 0x13
|
||||
.equ ABORTMODE, 0x17
|
||||
.equ UNDEFMODE, 0x1b
|
||||
.equ MODEMASK, 0x1f
|
||||
.equ NOINT, 0xc0
|
||||
|
||||
.equ RAM_BASE, 0x00000000 /*Start address of RAM */
|
||||
.equ ROM_BASE, 0x20000000 /*Start address of Flash */
|
||||
|
||||
|
||||
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
|
||||
#define AT91_RSTC_PERRST (1 << 2)
|
||||
#define AT91_RSTC_KEY (0xa5 << 24)
|
||||
#define AT91_MATRIX_BASE 0xffffee00
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX_BASE + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_AIC_BASE 0xfffff000
|
||||
#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
|
||||
#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Jump vector table
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
.section .init, "ax"
|
||||
.code 32
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
b reset
|
||||
ldr pc, _vector_undef
|
||||
ldr pc, _vector_swi
|
||||
ldr pc, _vector_pabt
|
||||
ldr pc, _vector_dabt
|
||||
ldr pc, _vector_resv
|
||||
ldr pc, _vector_irq
|
||||
ldr pc, _vector_fiq
|
||||
|
||||
_vector_undef: .word vector_undef
|
||||
_vector_swi: .word vector_swi
|
||||
_vector_pabt: .word vector_pabt
|
||||
_vector_dabt: .word vector_dabt
|
||||
_vector_resv: .word vector_resv
|
||||
_vector_irq: .word vector_irq
|
||||
_vector_fiq: .word vector_fiq
|
||||
|
||||
.balignl 16,0xdeadbeef
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Startup Code (reset vector)
|
||||
* relocate armboot to ram
|
||||
* setup stack
|
||||
* jump to second stage
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
/*
|
||||
* rtthread kernel start and end
|
||||
* which are defined in linker script
|
||||
*/
|
||||
.globl _rtthread_start
|
||||
_rtthread_start:
|
||||
.word _start
|
||||
|
||||
.globl _rtthread_end
|
||||
_rtthread_end:
|
||||
.word _end
|
||||
|
||||
/*
|
||||
* rtthread bss start and end which are defined in linker script
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word __bss_end
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START:
|
||||
.word _irq_stack_start + 1024
|
||||
|
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START:
|
||||
.word _fiq_stack_start + 1024
|
||||
|
||||
.globl UNDEFINED_STACK_START
|
||||
UNDEFINED_STACK_START:
|
||||
.word _undefined_stack_start + CONFIG_STACKSIZE
|
||||
|
||||
.globl ABORT_STACK_START
|
||||
ABORT_STACK_START:
|
||||
.word _abort_stack_start + CONFIG_STACKSIZE
|
||||
|
||||
.globl _STACK_START
|
||||
_STACK_START:
|
||||
.word _svc_stack_start + 4096
|
||||
|
||||
/* ----------------------------------entry------------------------------*/
|
||||
reset:
|
||||
|
||||
/* set the cpu to SVC32 mode */
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#MODEMASK
|
||||
orr r0,r0,#SVCMODE
|
||||
msr cpsr,r0
|
||||
|
||||
/* mask all IRQs by clearing all bits in the INTMRs */
|
||||
ldr r1, =AT91_AIC_BASE
|
||||
ldr r0, =0xffffffff
|
||||
str r0, [r1, #AT91_AIC_IDCR]
|
||||
str r0, [r1, #AT91_AIC_ICCR]
|
||||
|
||||
|
||||
/*remap internal ram to 0x00000000 address*/
|
||||
ldr r0, =AT91_MATRIX_MRCR
|
||||
ldr r1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1)
|
||||
str r1, [r0]
|
||||
|
||||
/* set interrupt vector */
|
||||
ldr r0, _TEXT_BASE
|
||||
mov r1, #0x00
|
||||
add r2, r0, #0x40 /* size, 32bytes */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end addreee [r2] */
|
||||
ble copy_loop
|
||||
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
|
||||
/* clear .bss */
|
||||
mov r0,#0 /* get a zero */
|
||||
ldr r1,=__bss_start /* bss start */
|
||||
ldr r2,=__bss_end /* bss end */
|
||||
|
||||
bss_loop:
|
||||
cmp r1,r2 /* check if data to clear */
|
||||
strlo r0,[r1],#4 /* clear 4 bytes */
|
||||
blo bss_loop /* loop until done */
|
||||
|
||||
/* call C++ constructors of global objects */
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
|
||||
ctor_loop:
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0], #4
|
||||
stmfd sp!, {r0-r1}
|
||||
mov lr, pc
|
||||
bx r2
|
||||
ldmfd sp!, {r0-r1}
|
||||
b ctor_loop
|
||||
|
||||
ctor_end:
|
||||
|
||||
/* start RT-Thread Kernel */
|
||||
ldr pc, _rtthread_startup
|
||||
|
||||
_rtthread_startup:
|
||||
.word rtthread_startup
|
||||
#if defined (__FLASH_BUILD__)
|
||||
_load_address:
|
||||
.word ROM_BASE + _TEXT_BASE
|
||||
#else
|
||||
_load_address:
|
||||
.word RAM_BASE + _TEXT_BASE
|
||||
#endif
|
||||
|
||||
.global cpu_reset
|
||||
cpu_reset:
|
||||
ldr r0, =0xfffffd00
|
||||
ldr r1, =(AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST)
|
||||
str r1, [r0]
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Interrupt handling
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
/* exception handlers */
|
||||
.align 5
|
||||
vector_undef:
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
||||
add r8, sp, #S_PC
|
||||
stmdb r8, {sp, lr}^ /* Calling SP, LR */
|
||||
str lr, [r8, #0] /* Save calling PC */
|
||||
mrs r6, spsr
|
||||
str r6, [r8, #4] /* Save CPSR */
|
||||
str r0, [r8, #8] /* Save OLD_R0 */
|
||||
mov r0, sp
|
||||
|
||||
bl rt_hw_trap_udef
|
||||
|
||||
.align 5
|
||||
vector_swi:
|
||||
bl rt_hw_trap_swi
|
||||
|
||||
.align 5
|
||||
vector_pabt:
|
||||
bl rt_hw_trap_pabt
|
||||
|
||||
.align 5
|
||||
vector_dabt:
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
||||
add r8, sp, #S_PC
|
||||
stmdb r8, {sp, lr}^ /* Calling SP, LR */
|
||||
str lr, [r8, #0] /* Save calling PC */
|
||||
mrs r6, spsr
|
||||
str r6, [r8, #4] /* Save CPSR */
|
||||
str r0, [r8, #8] /* Save OLD_R0 */
|
||||
mov r0, sp
|
||||
|
||||
bl rt_hw_trap_dabt
|
||||
|
||||
.align 5
|
||||
vector_resv:
|
||||
bl rt_hw_trap_resv
|
||||
|
||||
.globl rt_interrupt_enter
|
||||
.globl rt_interrupt_leave
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
vector_irq:
|
||||
stmfd sp!, {r0-r12,lr}
|
||||
bl rt_interrupt_enter
|
||||
bl rt_hw_trap_irq
|
||||
bl rt_interrupt_leave
|
||||
|
||||
/* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
|
||||
ldr r0, =rt_thread_switch_interrupt_flag
|
||||
ldr r1, [r0]
|
||||
cmp r1, #1
|
||||
beq _interrupt_thread_switch
|
||||
|
||||
ldmfd sp!, {r0-r12,lr}
|
||||
subs pc, lr, #4
|
||||
|
||||
.align 5
|
||||
vector_fiq:
|
||||
stmfd sp!,{r0-r7,lr}
|
||||
bl rt_hw_trap_fiq
|
||||
ldmfd sp!,{r0-r7,lr}
|
||||
subs pc,lr,#4
|
||||
|
||||
_interrupt_thread_switch:
|
||||
mov r1, #0 /* clear rt_thread_switch_interrupt_flag*/
|
||||
str r1, [r0]
|
||||
|
||||
ldmfd sp!, {r0-r12,lr} /* reload saved registers */
|
||||
stmfd sp!, {r0-r3} /* save r0-r3 */
|
||||
mov r1, sp
|
||||
add sp, sp, #16 /* restore sp */
|
||||
sub r2, lr, #4 /* save old task's pc to r2 */
|
||||
|
||||
mrs r3, spsr /* disable interrupt */
|
||||
orr r0, r3, #NOINT
|
||||
msr spsr_c, r0
|
||||
|
||||
ldr r0, =.+8 /* switch to interrupted task's stack*/
|
||||
movs pc, r0
|
||||
|
||||
stmfd sp!, {r2} /* push old task's pc */
|
||||
stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
|
||||
mov r4, r1 /* Special optimised code below */
|
||||
mov r5, r3
|
||||
ldmfd r4!, {r0-r3}
|
||||
stmfd sp!, {r0-r3} /* push old task's r3-r0 */
|
||||
stmfd sp!, {r5} /* push old task's psr */
|
||||
mrs r4, spsr
|
||||
stmfd sp!, {r4} /* push old task's spsr */
|
||||
|
||||
ldr r4, =rt_interrupt_from_thread
|
||||
ldr r5, [r4]
|
||||
str sp, [r5] /* store sp in preempted tasks's TCB*/
|
||||
|
||||
ldr r6, =rt_interrupt_to_thread
|
||||
ldr r6, [r6]
|
||||
ldr sp, [r6] /* get new task's stack pointer */
|
||||
|
||||
ldmfd sp!, {r4} /* pop new task's spsr */
|
||||
msr SPSR_cxsf, r4
|
||||
ldmfd sp!, {r4} /* pop new task's psr */
|
||||
msr CPSR_cxsf, r4
|
||||
|
||||
ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
|
||||
|
||||
stack_setup:
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1, r0, #UNDEFMODE|NOINT
|
||||
msr cpsr_cxsf, r1 /* undef mode */
|
||||
ldr sp, UNDEFINED_STACK_START
|
||||
|
||||
orr r1,r0,#ABORTMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* abort mode */
|
||||
ldr sp, ABORT_STACK_START
|
||||
|
||||
orr r1,r0,#IRQMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* IRQ mode */
|
||||
ldr sp, IRQ_STACK_START
|
||||
|
||||
orr r1,r0,#FIQMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* FIQ mode */
|
||||
ldr sp, FIQ_STACK_START
|
||||
|
||||
bic r0,r0,#MODEMASK
|
||||
orr r1,r0,#SVCMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* SVC mode */
|
||||
|
||||
ldr sp, _STACK_START
|
||||
|
||||
/* USER mode is not initialized. */
|
||||
mov pc,lr /* The LR register may be not valid for the mode changes.*/
|
||||
|
||||
/*/*}*/
|
||||
|
||||
|
||||
@@ -0,0 +1,315 @@
|
||||
;/*
|
||||
; * File : start_rvds.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
; *
|
||||
; * The license and distribution terms for this file may be
|
||||
; * found in the file LICENSE in this distribution or at
|
||||
; * http://www.rt-thread.org/license/LICENSE
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2011-08-14 weety first version
|
||||
; */
|
||||
|
||||
|
||||
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
|
||||
|
||||
Mode_USR EQU 0x10
|
||||
Mode_FIQ EQU 0x11
|
||||
Mode_IRQ EQU 0x12
|
||||
Mode_SVC EQU 0x13
|
||||
Mode_ABT EQU 0x17
|
||||
Mode_UND EQU 0x1B
|
||||
Mode_SYS EQU 0x1F
|
||||
|
||||
SVCMODE EQU 0x13
|
||||
MODEMASK EQU 0x1f
|
||||
|
||||
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
|
||||
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
|
||||
|
||||
|
||||
;----------------------- Stack and Heap Definitions ----------------------------
|
||||
|
||||
;// <h> Stack Configuration (Stack Sizes in Bytes)
|
||||
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
|
||||
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
|
||||
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
|
||||
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
|
||||
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
|
||||
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
|
||||
;// </h>
|
||||
|
||||
UND_Stack_Size EQU 512
|
||||
SVC_Stack_Size EQU 4096
|
||||
ABT_Stack_Size EQU 512
|
||||
FIQ_Stack_Size EQU 1024
|
||||
IRQ_Stack_Size EQU 1024
|
||||
USR_Stack_Size EQU 512
|
||||
|
||||
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
|
||||
FIQ_Stack_Size + IRQ_Stack_Size)
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
|
||||
Stack_Mem SPACE USR_Stack_Size
|
||||
__initial_sp SPACE ISR_Stack_Size
|
||||
Stack_Top
|
||||
|
||||
|
||||
;// <h> Heap Configuration
|
||||
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
|
||||
;// </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
;----------------------- Memory Definitions ------------------------------------
|
||||
|
||||
AT91_MATRIX_BASE EQU 0xffffee00
|
||||
AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100)
|
||||
AT91_MATRIX_RCB0 EQU 0x00000001
|
||||
AT91_MATRIX_RCB1 EQU 0x00000002
|
||||
AT91_AIC_BASE EQU 0xfffff000
|
||||
AT91_AIC_IDCR EQU 0x124
|
||||
AT91_AIC_ICCR EQU 0x128
|
||||
|
||||
;----------------------- CODE --------------------------------------------------
|
||||
|
||||
PRESERVE8
|
||||
|
||||
|
||||
; Area Definition and Entry Point
|
||||
; Startup Code must be linked first at Address at which it expects to run.
|
||||
|
||||
AREA RESET, CODE, READONLY
|
||||
ARM
|
||||
|
||||
; Exception Vectors
|
||||
; Mapped to Address 0.
|
||||
; Absolute addressing mode must be used.
|
||||
; Dummy Handlers are implemented as infinite loops which can be modified.
|
||||
|
||||
EXPORT Entry_Point
|
||||
Entry_Point
|
||||
Vectors LDR PC, Reset_Addr
|
||||
LDR PC, Undef_Addr
|
||||
LDR PC, SWI_Addr
|
||||
LDR PC, PAbt_Addr
|
||||
LDR PC, DAbt_Addr
|
||||
NOP
|
||||
LDR PC, IRQ_Addr
|
||||
LDR PC, FIQ_Addr
|
||||
|
||||
Reset_Addr DCD Reset_Handler
|
||||
Undef_Addr DCD Undef_Handler
|
||||
SWI_Addr DCD SWI_Handler
|
||||
PAbt_Addr DCD PAbt_Handler
|
||||
DAbt_Addr DCD DAbt_Handler
|
||||
DCD 0 ; Reserved Address
|
||||
IRQ_Addr DCD IRQ_Handler
|
||||
FIQ_Addr DCD FIQ_Handler
|
||||
|
||||
Undef_Handler B Undef_Handler
|
||||
SWI_Handler B SWI_Handler
|
||||
PAbt_Handler B PAbt_Handler
|
||||
;DAbt_Handler B DAbt_Handler
|
||||
FIQ_Handler B FIQ_Handler
|
||||
|
||||
;*
|
||||
;*************************************************************************
|
||||
;*
|
||||
;* Interrupt handling
|
||||
;*
|
||||
;*************************************************************************
|
||||
;*
|
||||
; DAbt Handler
|
||||
DAbt_Handler
|
||||
IMPORT rt_hw_trap_dabt
|
||||
|
||||
sub sp, sp, #72
|
||||
stmia sp, {r0 - r12} ;/* Calling r0-r12 */
|
||||
add r8, sp, #60
|
||||
stmdb r8, {sp, lr} ;/* Calling SP, LR */
|
||||
str lr, [r8, #0] ;/* Save calling PC */
|
||||
mrs r6, spsr
|
||||
str r6, [r8, #4] ;/* Save CPSR */
|
||||
str r0, [r8, #8] ;/* Save OLD_R0 */
|
||||
mov r0, sp
|
||||
|
||||
bl rt_hw_trap_dabt
|
||||
|
||||
|
||||
;##########################################
|
||||
; Reset Handler
|
||||
|
||||
EXPORT Reset_Handler
|
||||
Reset_Handler
|
||||
|
||||
|
||||
; set the cpu to SVC32 mode-----------------------------------------------------
|
||||
|
||||
MRS R0,CPSR
|
||||
BIC R0,R0,#MODEMASK
|
||||
ORR R0,R0,#SVCMODE
|
||||
MSR CPSR_cxsf,R0
|
||||
LDR R1, =AT91_AIC_BASE
|
||||
LDR R0, =0xffffffff
|
||||
STR R0, [R1, #AT91_AIC_IDCR]
|
||||
STR R0, [R1, #AT91_AIC_ICCR]
|
||||
|
||||
; remap internal ram to 0x00000000 address
|
||||
LDR R0, =AT91_MATRIX_MRCR
|
||||
LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1)
|
||||
STR R1, [R0]
|
||||
|
||||
|
||||
; Copy Exception Vectors to Internal RAM ---------------------------------------
|
||||
|
||||
ADR R8, Vectors ; Source
|
||||
LDR R9, =0x00 ; Destination
|
||||
LDMIA R8!, {R0-R7} ; Load Vectors
|
||||
STMIA R9!, {R0-R7} ; Store Vectors
|
||||
LDMIA R8!, {R0-R7} ; Load Handler Addresses
|
||||
STMIA R9!, {R0-R7} ; Store Handler Addresses
|
||||
|
||||
|
||||
; Setup Stack for each mode ----------------------------------------------------
|
||||
|
||||
LDR R0, =Stack_Top
|
||||
|
||||
; Enter Undefined Instruction Mode and set its Stack Pointer
|
||||
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
|
||||
MOV SP, R0
|
||||
SUB R0, R0, #UND_Stack_Size
|
||||
|
||||
; Enter Abort Mode and set its Stack Pointer
|
||||
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
|
||||
MOV SP, R0
|
||||
SUB R0, R0, #ABT_Stack_Size
|
||||
|
||||
; Enter FIQ Mode and set its Stack Pointer
|
||||
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
|
||||
MOV SP, R0
|
||||
SUB R0, R0, #FIQ_Stack_Size
|
||||
|
||||
; Enter IRQ Mode and set its Stack Pointer
|
||||
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
|
||||
MOV SP, R0
|
||||
SUB R0, R0, #IRQ_Stack_Size
|
||||
|
||||
; Enter Supervisor Mode and set its Stack Pointer
|
||||
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
|
||||
MOV SP, R0
|
||||
SUB R0, R0, #SVC_Stack_Size
|
||||
|
||||
; Enter User Mode and set its Stack Pointer
|
||||
; MSR CPSR_c, #Mode_USR
|
||||
MOV SP, R0
|
||||
SUB SL, SP, #USR_Stack_Size
|
||||
|
||||
; Enter the C code -------------------------------------------------------------
|
||||
|
||||
IMPORT __main
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
|
||||
IMPORT rt_interrupt_enter
|
||||
IMPORT rt_interrupt_leave
|
||||
IMPORT rt_thread_switch_interrupt_flag
|
||||
IMPORT rt_interrupt_from_thread
|
||||
IMPORT rt_interrupt_to_thread
|
||||
IMPORT rt_hw_trap_irq
|
||||
|
||||
IRQ_Handler PROC
|
||||
EXPORT IRQ_Handler
|
||||
STMFD sp!, {r0-r12,lr}
|
||||
BL rt_interrupt_enter
|
||||
BL rt_hw_trap_irq
|
||||
BL rt_interrupt_leave
|
||||
|
||||
; if rt_thread_switch_interrupt_flag set, jump to
|
||||
; rt_hw_context_switch_interrupt_do and don't return
|
||||
LDR r0, =rt_thread_switch_interrupt_flag
|
||||
LDR r1, [r0]
|
||||
CMP r1, #1
|
||||
BEQ rt_hw_context_switch_interrupt_do
|
||||
|
||||
LDMFD sp!, {r0-r12,lr}
|
||||
SUBS pc, lr, #4
|
||||
ENDP
|
||||
|
||||
; /*
|
||||
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
||||
; */
|
||||
rt_hw_context_switch_interrupt_do PROC
|
||||
EXPORT rt_hw_context_switch_interrupt_do
|
||||
MOV r1, #0 ; clear flag
|
||||
STR r1, [r0]
|
||||
|
||||
LDMFD sp!, {r0-r12,lr}; reload saved registers
|
||||
STMFD sp!, {r0-r3} ; save r0-r3
|
||||
MOV r1, sp
|
||||
ADD sp, sp, #16 ; restore sp
|
||||
SUB r2, lr, #4 ; save old task's pc to r2
|
||||
|
||||
MRS r3, spsr ; get cpsr of interrupt thread
|
||||
|
||||
; switch to SVC mode and no interrupt
|
||||
MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
|
||||
|
||||
STMFD sp!, {r2} ; push old task's pc
|
||||
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
|
||||
MOV r4, r1 ; Special optimised code below
|
||||
MOV r5, r3
|
||||
LDMFD r4!, {r0-r3}
|
||||
STMFD sp!, {r0-r3} ; push old task's r3-r0
|
||||
STMFD sp!, {r5} ; push old task's cpsr
|
||||
MRS r4, spsr
|
||||
STMFD sp!, {r4} ; push old task's spsr
|
||||
|
||||
LDR r4, =rt_interrupt_from_thread
|
||||
LDR r5, [r4]
|
||||
STR sp, [r5] ; store sp in preempted tasks's TCB
|
||||
|
||||
LDR r6, =rt_interrupt_to_thread
|
||||
LDR r6, [r6]
|
||||
LDR sp, [r6] ; get new task's stack pointer
|
||||
|
||||
LDMFD sp!, {r4} ; pop new task's spsr
|
||||
MSR spsr_cxsf, r4
|
||||
LDMFD sp!, {r4} ; pop new task's psr
|
||||
MSR cpsr_cxsf, r4
|
||||
|
||||
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
|
||||
ENDP
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
; User Initial Stack & Heap
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + USR_Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
||||
@@ -0,0 +1,294 @@
|
||||
/*
|
||||
* File : clock.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "at91sam926x.h"
|
||||
|
||||
static rt_list_t clocks;
|
||||
|
||||
struct clk {
|
||||
char name[32];
|
||||
rt_uint32_t rate_hz;
|
||||
struct clk *parent;
|
||||
rt_list_t node;
|
||||
};
|
||||
|
||||
static struct clk clk32k = {
|
||||
"clk32k",
|
||||
AT91_SLOW_CLOCK,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk main_clk = {
|
||||
"main",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk plla = {
|
||||
"plla",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk mck = {
|
||||
"mck",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk uhpck = {
|
||||
"uhpck",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk pllb = {
|
||||
"pllb",
|
||||
0,
|
||||
&main_clk,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk udpck = {
|
||||
"udpck",
|
||||
0,
|
||||
&pllb,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk *const standard_pmc_clocks[] = {
|
||||
/* four primary clocks */
|
||||
&clk32k,
|
||||
&main_clk,
|
||||
&plla,
|
||||
|
||||
/* MCK */
|
||||
&mck
|
||||
};
|
||||
|
||||
/* clocks cannot be de-registered no refcounting necessary */
|
||||
struct clk *clk_get(const char *id)
|
||||
{
|
||||
struct clk *clk;
|
||||
rt_list_t *list;
|
||||
|
||||
for (list = (&clocks)->next; list != &clocks; list = list->next)
|
||||
{
|
||||
clk = (struct clk *)rt_list_entry(list, struct clk, node);
|
||||
if (rt_strcmp(id, clk->name) == 0)
|
||||
return clk;
|
||||
}
|
||||
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
rt_uint32_t clk_get_rate(struct clk *clk)
|
||||
{
|
||||
rt_uint32_t flags;
|
||||
rt_uint32_t rate;
|
||||
|
||||
for (;;) {
|
||||
rate = clk->rate_hz;
|
||||
if (rate || !clk->parent)
|
||||
break;
|
||||
clk = clk->parent;
|
||||
}
|
||||
return rate;
|
||||
}
|
||||
|
||||
static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
|
||||
{
|
||||
unsigned mul, div;
|
||||
|
||||
div = reg & 0xff;
|
||||
mul = (reg >> 16) & 0x7ff;
|
||||
if (div && mul) {
|
||||
freq /= div;
|
||||
freq *= mul + 1;
|
||||
} else
|
||||
freq = 0;
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
|
||||
{
|
||||
unsigned i, div = 0, mul = 0, diff = 1 << 30;
|
||||
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
|
||||
|
||||
/* PLL output max 240 MHz (or 180 MHz per errata) */
|
||||
if (out_freq > 240000000)
|
||||
goto fail;
|
||||
|
||||
for (i = 1; i < 256; i++) {
|
||||
int diff1;
|
||||
unsigned input, mul1;
|
||||
|
||||
/*
|
||||
* PLL input between 1MHz and 32MHz per spec, but lower
|
||||
* frequences seem necessary in some cases so allow 100K.
|
||||
* Warning: some newer products need 2MHz min.
|
||||
*/
|
||||
input = main_freq / i;
|
||||
if (input < 100000)
|
||||
continue;
|
||||
if (input > 32000000)
|
||||
continue;
|
||||
|
||||
mul1 = out_freq / input;
|
||||
if (mul1 > 2048)
|
||||
continue;
|
||||
if (mul1 < 2)
|
||||
goto fail;
|
||||
|
||||
diff1 = out_freq - input * mul1;
|
||||
if (diff1 < 0)
|
||||
diff1 = -diff1;
|
||||
if (diff > diff1) {
|
||||
diff = diff1;
|
||||
div = i;
|
||||
mul = mul1;
|
||||
if (diff == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i == 256 && diff > (out_freq >> 5))
|
||||
goto fail;
|
||||
return ret | ((mul - 1) << 16) | div;
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
|
||||
{
|
||||
if (pll == &pllb && (reg & AT91_PMC_USB96M))
|
||||
return freq / 2;
|
||||
else
|
||||
return freq;
|
||||
}
|
||||
|
||||
|
||||
/* PLLB generated USB full speed clock init */
|
||||
static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
|
||||
{
|
||||
rt_uint32_t at91_pllb_usb_init;
|
||||
/*
|
||||
* USB clock init: choose 48 MHz PLLB value,
|
||||
* disable 48MHz clock during usb peripheral suspend.
|
||||
*
|
||||
* REVISIT: assumes MCK doesn't derive from PLLB!
|
||||
*/
|
||||
uhpck.parent = &pllb;
|
||||
|
||||
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
|
||||
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
|
||||
|
||||
at91_sys_write(AT91_CKGR_PLLBR, 0);
|
||||
|
||||
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
||||
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
||||
}
|
||||
|
||||
static struct clk *at91_css_to_clk(unsigned long css)
|
||||
{
|
||||
switch (css) {
|
||||
case AT91_PMC_CSS_SLOW:
|
||||
return &clk32k;
|
||||
case AT91_PMC_CSS_MAIN:
|
||||
return &main_clk;
|
||||
case AT91_PMC_CSS_PLLA:
|
||||
return &plla;
|
||||
case AT91_PMC_CSS_PLLB:
|
||||
return &pllb;
|
||||
}
|
||||
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
#define false 0
|
||||
#define true 1
|
||||
int at91_clock_init(rt_uint32_t main_clock)
|
||||
{
|
||||
unsigned tmp, freq, mckr;
|
||||
int i;
|
||||
int pll_overclock = false;
|
||||
|
||||
/*
|
||||
* When the bootloader initialized the main oscillator correctly,
|
||||
* there's no problem using the cycle counter. But if it didn't,
|
||||
* or when using oscillator bypass mode, we must be told the speed
|
||||
* of the main clock.
|
||||
*/
|
||||
if (!main_clock) {
|
||||
do {
|
||||
tmp = at91_sys_read(AT91_CKGR_MCFR);
|
||||
} while (!(tmp & AT91_PMC_MAINRDY));
|
||||
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
|
||||
}
|
||||
main_clk.rate_hz = main_clock;
|
||||
|
||||
/* report if PLLA is more than mildly overclocked */
|
||||
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
|
||||
if (plla.rate_hz > 209000000)
|
||||
pll_overclock = true;
|
||||
if (pll_overclock)
|
||||
;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
||||
|
||||
at91_pllb_usbfs_clock_init(main_clock);
|
||||
|
||||
/*
|
||||
* MCK and CPU derive from one of those primary clocks.
|
||||
* For now, assume this parentage won't change.
|
||||
*/
|
||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
||||
freq = mck.parent->rate_hz;
|
||||
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
|
||||
|
||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||
|
||||
/* Register the PMC's standard clocks */
|
||||
rt_list_init(&clocks);
|
||||
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
||||
rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
|
||||
|
||||
rt_list_insert_after(&clocks, &pllb.node);
|
||||
rt_list_insert_after(&clocks, &uhpck.node);
|
||||
rt_list_insert_after(&clocks, &udpck.node);
|
||||
|
||||
/* MCK and CPU clock are "always on" */
|
||||
//clk_enable(&mck);
|
||||
|
||||
/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
|
||||
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
|
||||
(unsigned) main_clock / 1000000,
|
||||
((unsigned) main_clock % 1000000) / 1000);*///cause blocked
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
*/
|
||||
void rt_hw_clock_init(void)
|
||||
{
|
||||
at91_clock_init(18432000);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* File : trap.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety modified from mini2440
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include "at91sam926x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
extern struct rt_thread *rt_current_thread;
|
||||
#ifdef RT_USING_FINSH
|
||||
extern long list_thread(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* this function will show registers of CPU
|
||||
*
|
||||
* @param regs the registers point
|
||||
*/
|
||||
|
||||
void rt_hw_show_register (struct rt_hw_register *regs)
|
||||
{
|
||||
rt_kprintf("Execption:\n");
|
||||
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
|
||||
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
|
||||
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
|
||||
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
|
||||
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
|
||||
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
|
||||
}
|
||||
|
||||
/**
|
||||
* When ARM7TDMI comes across an instruction which it cannot handle,
|
||||
* it takes the undefined instruction trap.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_udef(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("undefined instruction\n");
|
||||
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* The software interrupt instruction (SWI) is used for entering
|
||||
* Supervisor mode, usually to request a particular supervisor
|
||||
* function.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_swi(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("software interrupt\n");
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* An abort indicates that the current memory access cannot be completed,
|
||||
* which occurs during an instruction prefetch.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_pabt(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("prefetch abort\n");
|
||||
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* An abort indicates that the current memory access cannot be completed,
|
||||
* which occurs during a data access.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_dabt(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("data abort\n");
|
||||
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* Normally, system will never reach here
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_resv(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_kprintf("not used\n");
|
||||
rt_hw_show_register(regs);
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
extern struct rt_irq_desc irq_desc[];
|
||||
|
||||
void rt_hw_trap_irq()
|
||||
{
|
||||
rt_isr_handler_t isr_func;
|
||||
rt_uint32_t irqstat, irq, mask;
|
||||
void *param;
|
||||
//rt_kprintf("irq interrupt request\n");
|
||||
/* get irq number */
|
||||
irq = at91_sys_read(AT91_AIC_IVR);
|
||||
/* clear pending register */
|
||||
irqstat = at91_sys_read(AT91_AIC_ISR);
|
||||
if (irqstat == 0)
|
||||
{
|
||||
rt_kprintf("No interrupt occur\n");
|
||||
at91_sys_write(AT91_AIC_EOICR, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = irq_desc[irq].handler;
|
||||
param = irq_desc[irq].param;
|
||||
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(irq, param);
|
||||
at91_sys_write(AT91_AIC_EOICR, 0x55555555); //EIOCR must be write any value after interrupt, or else can't response next interrupt
|
||||
irq_desc[irq].counter ++;
|
||||
}
|
||||
|
||||
void rt_hw_trap_fiq()
|
||||
{
|
||||
rt_kprintf("fast interrupt request\n");
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -2,7 +2,7 @@ import os
|
||||
|
||||
# toolchains options
|
||||
ARCH = 'arm'
|
||||
CPU = 'at91sam926x'
|
||||
CPU = 'arm926'
|
||||
TextBase = '0x20000000'
|
||||
|
||||
CROSS_TOOL = 'gcc'
|
||||
|
||||
Reference in New Issue
Block a user