From 33f5de4411b087c542ebbb61194122e5a77844c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=A8=8B=E8=92=99=E8=92=99?= <37764731+meng-plus@users.noreply.github.com> Date: Thu, 29 Jun 2023 00:04:06 +0800 Subject: [PATCH] =?UTF-8?q?[atomic][IAR]=E4=BF=AE=E5=A4=8DIAR=E7=BC=96?= =?UTF-8?q?=E8=AF=91=E6=8A=A5=E8=AD=A6=20=E5=87=BD=E6=95=B0=E2=80=9C=5F=5F?= =?UTF-8?q?LDREX=E2=80=9D=E9=9A=90=E5=BC=8F=E5=A3=B0=E6=98=8E=20(#7733)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/arm/common/atomic_arm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/libcpu/arm/common/atomic_arm.c b/libcpu/arm/common/atomic_arm.c index 18d186233f..290d72e717 100644 --- a/libcpu/arm/common/atomic_arm.c +++ b/libcpu/arm/common/atomic_arm.c @@ -10,6 +10,9 @@ #include +#if defined (__IAR_SYSTEMS_ICC__) /* for IAR Compiler */ +#include +#endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. @@ -27,7 +30,7 @@ #elif defined (__IAR_SYSTEMS_ICC__) /* for IAR Compiler */ _Pragma("inline=forced") __intrinsic rt_atomic_t __LDREXW(volatile rt_atomic_t *ptr) { - return __LDREX((unsigned long *)ptr); + return __LDREX((unsigned int *)ptr); } #elif defined (__GNUC__) /* GNU GCC Compiler */ __attribute__((always_inline)) static inline rt_atomic_t __LDREXW(volatile rt_atomic_t *addr) @@ -58,7 +61,7 @@ __attribute__((always_inline)) static inline rt_atomic_t __LDREXW(volatile r #elif defined (__IAR_SYSTEMS_ICC__) /* for IAR Compiler */ _Pragma("inline=forced") __intrinsic rt_atomic_t __STREXW(rt_atomic_t value, volatile rt_atomic_t *ptr) { - return __STREX(value, (unsigned long *)ptr); + return __STREX(value, (unsigned int *)ptr); } #elif defined (__GNUC__) /* GNU GCC Compiler */ __attribute__((always_inline)) static inline rt_atomic_t __STREXW(volatile rt_atomic_t value, volatile rt_atomic_t *addr)