[dm][clk] refactoring the CLK framework

The old CLK is can't link all hardware clock cell in system that the
API of layout such as 'set_parent' can't work as expected.

Some hareware clock cell need some flags to prevent some dangerous behaviors, eg:
When a clock cell is link to the PMU, the SoC will power-down if the cell is
disable.

The new CLK can do it, and make the CLK drivers implemented easier from
TRM/DataSheet.

Signed-off-by: GuEe-GUI <2991707448@qq.com>

components/drivers/clk/SConscript

@@ -1,7 +1,6 @@
 from building import *
 
 group = []
-objs = []
 
 if not GetDepend(['RT_USING_CLK']):
     Return('group')
@@ -15,12 +14,7 @@ src = ['clk.c']
 if GetDepend(['RT_USING_OFW']):
     src += ['clk-fixed-rate.c']
 
+
 group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
 
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-objs = objs + group
-
-Return('objs')
+Return('group')