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https://github.com/RT-Thread/rt-thread.git
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🎈 perf: perf rt_hw_interrupt_disable/enable (#8042)
Signed-off-by: Shell <smokewood@qq.com> Co-authored-by: Shell <smokewood@qq.com>
This commit is contained in:
xqyjlj
Shell
@@ -9,10 +9,14 @@
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* 2023-06-24 WangXiaoyao Support backtrace for user thread
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include "rtconfig.h"
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#include "asm-generic.h"
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#include "asm-fpu.h"
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#include "armv8.h"
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.text
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.weak rt_hw_cpu_id_set
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@@ -279,12 +283,30 @@ START_POINT_END(_thread_start)
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1:
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.endm
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.macro RESTORE_USER_CTX, ctx
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LDR X1, [\ctx, #CONTEXT_OFFSET_SPSR_EL1]
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AND X1, X1, 0x1f
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CMP X1, XZR
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BNE 1f
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BL lwp_uthread_ctx_restore
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1:
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.endm
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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.text
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.global rt_hw_interrupt_is_disabled
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rt_hw_interrupt_is_disabled:
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MRS X0, DAIF
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TST X0, #0xc0
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CSET X0, NE
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RET
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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@@ -387,8 +409,7 @@ rt_hw_context_switch_interrupt:
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vector_fiq:
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B .
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.globl vector_irq
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vector_irq:
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START_POINT(vector_irq)
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SAVE_CONTEXT
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STP X0, X1, [SP, #-0x10]! /* X0 is thread sp */
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@@ -399,13 +420,15 @@ vector_irq:
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#endif
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BL rt_hw_trap_irq
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#ifdef RT_USING_LWP
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BL lwp_uthread_ctx_restore
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LDP X0, X1, [SP]
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RESTORE_USER_CTX X0
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#endif
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BL rt_interrupt_leave
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LDP X0, X1, [SP], #0x10
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BL rt_scheduler_do_irq_switch
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B rt_hw_context_switch_exit
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START_POINT_END(vector_irq)
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.global rt_hw_context_switch_exit
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rt_hw_context_switch_exit:
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@@ -540,7 +563,8 @@ START_POINT(vector_exception)
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BL rt_hw_trap_exception
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#ifdef RT_USING_LWP
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BL lwp_uthread_ctx_restore
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LDP X0, X1, [SP]
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RESTORE_USER_CTX X0
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#endif
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LDP X0, X1, [SP], #0x10
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+50
-37
@@ -59,52 +59,65 @@ rt_weak rt_uint64_t rt_cpu_mpidr_early[] =
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};
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#endif /* RT_USING_SMART */
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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lock->slock = 0;
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}
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typedef rt_hw_spinlock_t arch_spinlock_t;
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#define TICKET_SHIFT 16
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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struct __arch_tickets lockval, newval;
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asm volatile(
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/* Atomically increment the next ticket. */
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" prfm pstl1strm, %3\n"
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"1: ldaxr %w0, %3\n"
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" add %w1, %w0, %w5\n"
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" stxr %w2, %w1, %3\n"
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" cbnz %w2, 1b\n"
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/* Did we get the lock? */
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" eor %w1, %w0, %w0, ror #16\n"
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" cbz %w1, 3f\n"
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/*
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* No: spin on the owner. Send a local event to avoid missing an
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* unlock before the exclusive load.
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*/
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" sevl\n"
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"2: wfe\n"
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" ldaxrh %w2, %4\n"
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" eor %w1, %w2, %w0, lsr #16\n"
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" cbnz %w1, 2b\n"
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/* We got the lock. Critical section starts here. */
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"3:"
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: "=&r"(lockval), "=&r"(newval), "=&r"(tmp), "+Q"(*lock)
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: "Q"(lock->tickets.owner), "I"(1 << TICKET_SHIFT)
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: "memory");
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rt_hw_dmb();
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %1\n"
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" cbnz %w0, 1b\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 2b\n"
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: "=&r" (tmp), "+Q" (lock->lock)
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: "r" (1)
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: "cc", "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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asm volatile(
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" ldaxr %w0, %1\n"
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" cbnz %w0, 1f\n"
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" stxr %w0, %w2, %1\n"
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"1:\n"
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: "=&r" (tmp), "+Q" (lock->lock)
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: "r" (1)
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: "cc", "memory");
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return !tmp;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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asm volatile(
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" stlr %w1, %0\n"
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: "=Q" (lock->lock) : "r" (0) : "memory");
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}
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void rt_hw_spin_lock_init(arch_spinlock_t *lock)
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{
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lock->lock = 0;
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}
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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arch_spin_lock(lock);
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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rt_hw_dmb();
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asm volatile(
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" stlrh %w1, %0\n"
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: "=Q"(lock->tickets.owner)
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: "r"(lock->tickets.owner + 1)
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: "memory");
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arch_spin_unlock(lock);
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}
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rt_bool_t rt_hw_spin_trylock(rt_hw_spinlock_t *lock)
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{
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return arch_spin_trylock(lock);
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}
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static int _cpus_init_data_hardcoded(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[])
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@@ -14,12 +14,8 @@
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#include <rtdef.h>
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#ifdef RT_USING_SMP
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typedef union {
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unsigned long slock;
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struct __arch_tickets {
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unsigned short owner;
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unsigned short next;
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} tickets;
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typedef struct {
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volatile unsigned int lock;
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} rt_hw_spinlock_t;
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#endif
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@@ -38,7 +38,7 @@ extern void *system_vectors;
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#ifdef RT_USING_SMP
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#define rt_interrupt_nest rt_cpu_self()->irq_nest
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#else
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extern volatile rt_uint8_t rt_interrupt_nest;
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extern volatile rt_atomic_t rt_interrupt_nest;
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#endif
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#ifdef SOC_BCM283x
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@@ -85,7 +85,7 @@ void rt_hw_interrupt_init(void)
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}
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_atomic_store(&rt_interrupt_nest, 0);
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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@@ -415,3 +415,48 @@ void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
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}
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#endif
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#if defined(FINSH_USING_MSH) && defined(RT_USING_INTERRUPT_INFO)
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int list_isr()
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{
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int idx;
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rt_kprintf("%-*.*s nr handler param counter ", RT_NAME_MAX, RT_NAME_MAX, "irq");
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#ifdef RT_USING_SMP
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for (int i = 0; i < RT_CPUS_NR; i++)
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{
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rt_kprintf(" cpu%2d ", i);
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}
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#endif
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rt_kprintf("\n");
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for (int i = 0; i < RT_NAME_MAX; i++)
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{
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rt_kprintf("-");
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}
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rt_kprintf(" ---- ------------------ ------------------ ----------------");
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#ifdef RT_USING_SMP
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for (int i = 0; i < RT_CPUS_NR; i++)
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{
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rt_kprintf(" -------");
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}
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#endif
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rt_kprintf("\n");
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for (idx = 0; idx < MAX_HANDLERS; idx++)
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{
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if (isr_table[idx].handler != RT_NULL)
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{
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rt_kprintf("%*.s %4d %p %p %16d", RT_NAME_MAX, isr_table[idx].name, idx, isr_table[idx].handler,
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isr_table[idx].param, isr_table[idx].counter);
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#ifdef RT_USING_SMP
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for (int i = 0; i < RT_CPUS_NR; i++)
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rt_kprintf(" %7d", isr_table[idx].cpu_counter[i]);
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#endif
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rt_kprintf("\n");
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}
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}
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return 0;
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}
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#include "finsh.h"
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MSH_CMD_EXPORT(list_isr, list isr)
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#endif
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@@ -274,6 +274,9 @@ void rt_hw_trap_irq(void)
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isr_func = isr_table[ir_self].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[ir_self].counter++;
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#ifdef RT_USING_SMP
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isr_table[ir_self].cpu_counter[rt_hw_cpu_id()]++;
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#endif
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#endif
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if (isr_func)
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{
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