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[HC32] support HC32F472 & remove residual files

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This commit is contained in:
chengy2
2024-04-30 05:48:47 +08:00
committed by GitHub
parent 7890e2cb14
commit 2aa66b1b4e
453 changed files with 295736 additions and 47893 deletions
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1
bsp/hc32/libraries/.ignore_format.yml
View File

@@ -6,3 +6,4 @@ dir_path:
- hc32f4a0_ddl
- hc32f460_ddl
- hc32f448_ddl
- hc32f472_ddl

8
bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c
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@@ -111,8 +111,10 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
/* calculate sector information */
FirstSector = addr / SECTOR_SIZE,
NbOfSectors = GetSectorNum(addr, size);
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
/* Sectors disable write protection */
EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, ENABLE);
#endif
/* Word align */
if (0U != (addr % 4))
{
@@ -149,8 +151,10 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
}
__exit:
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
/* Sectors enable write protection */
EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, DISABLE);
#endif
EFM_FWMC_Cmd(DISABLE);
if (result != RT_EOK)
@@ -189,8 +193,10 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
/* calculate sector information */
FirstSector = addr / SECTOR_SIZE,
NbOfSectors = GetSectorNum(addr, size);
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
/* Sectors disable write protection */
EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, ENABLE);
#endif
/* Erase sector */
for (SectorVal = FirstSector; SectorVal < NbOfSectors; SectorVal++)
{
@@ -201,8 +207,10 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
break;
}
}
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
/* Sectors enable write protection */
EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, DISABLE);
#endif
EFM_FWMC_Cmd(DISABLE);
if (result != RT_EOK)

5
bsp/hc32/libraries/hc32_drivers/drv_gpio.c
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@@ -29,6 +29,8 @@
#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
#elif defined (HC32F448)
#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
#elif defined (HC32F472)
#define PIN_MAX_NUM ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_08))) + 1)
#endif
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
@@ -252,6 +254,9 @@ static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mo
case PIN_MODE_INPUT_PULLDOWN:
stcGpioInit.u16PinDir = PIN_DIR_IN;
stcGpioInit.u16PullUp = PIN_PU_OFF;
#if defined (HC32F448) || defined (HC32F472)
stcGpioInit.u16PullDown = PIN_PD_ON;
#endif
break;
case PIN_MODE_OUTPUT_OD:
stcGpioInit.u16PinDir = PIN_DIR_OUT;

2
bsp/hc32/libraries/hc32_drivers/drv_irq.c
View File

@@ -68,7 +68,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
return result;
}
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
rt_bool_t irq_enable)
{

2
bsp/hc32/libraries/hc32_drivers/drv_irq.h
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@@ -47,7 +47,7 @@ struct hc32_irq_config
rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
void (*irq_hdr)(void),
rt_bool_t irq_enable);
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
rt_bool_t irq_enable);
#endif

4
bsp/hc32/libraries/hc32_drivers/drv_pm.c
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@@ -66,7 +66,7 @@ static void _uart_console_reconfig(void)
* @retval None
*/
__WEAKDEF void pwc_seep_enter(uint8_t u8SleepType)
__WEAKDEF void pwc_sleep_enter(uint8_t u8SleepType)
{
DDL_ASSERT(IS_PWC_UNLOCKED());
@@ -96,7 +96,7 @@ __WEAKDEF void pwc_seep_enter(uint8_t u8SleepType)
static void _sleep_enter_idle(void)
{
struct pm_sleep_mode_idle_config sleep_idle_cfg = PM_SLEEP_IDLE_CFG;
pwc_seep_enter(sleep_idle_cfg.pwc_sleep_type);
pwc_sleep_enter(sleep_idle_cfg.pwc_sleep_type);
}
static void _sleep_enter_deep(void)

361
bsp/hc32/libraries/hc32_drivers/drv_qspi.c
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File diff suppressed because it is too large Load Diff

4
bsp/hc32/libraries/hc32_drivers/drv_qspi.h
View File

@@ -39,6 +39,10 @@ struct hc32_qspi_config
struct hc32_qspi_irq_config err_irq;
#ifdef BSP_QSPI_USING_DMA
struct dma_config *dma_qspi;
#if defined (HC32F448)
rt_uint16_t *dma_tx_buf;
rt_uint16_t dma_tx_buf_size; /* unit: half-word, DMA data width of QSPI transmitting is 16bit */
#endif
#endif
};

23
bsp/hc32/libraries/hc32_drivers/drv_spi.c
View File

@@ -8,6 +8,7 @@
* 2022-04-28 CDT first version
* 2023-09-30 CDT Delete dma transmit interrupt
* 2024-02-20 CDT support HC32F448
* 2024-04-16 CDT support HC32F472
*/
/*******************************************************************************
@@ -293,7 +294,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
#endif
/* Enable error interrupt */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(spi_drv->config->err_irq.irq_config.int_src, ENABLE);
#endif
NVIC_EnableIRQ(spi_drv->config->err_irq.irq_config.irq_num);
@@ -311,7 +312,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
{
SPI_Cmd(SPIx, ENABLE);
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE)
{
SPI_Cmd(SPIx, ENABLE);
@@ -332,7 +333,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
{
CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
if (SPI_SEND_ONLY == u32Mode)
{
SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
@@ -351,7 +352,7 @@ static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx)
{
#if defined (HC32F460) || defined (HC32F4A0)
return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
#else
#error "Please select first the target HC32xxxx device used in your application."
@@ -679,7 +680,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
static void hc32_spi_err_irq_handle(struct hc32_spi *spi)
{
#if defined (HC32F448)
#if defined (HC32F448) ||defined (HC32F472)
#define SPI_FLAG_OVERLOAD SPI_FLAG_OVERRUN
#define SPI_FLAG_UNDERLOAD SPI_FLAG_UNDERRUN
#endif
@@ -715,12 +716,12 @@ static void hc32_spi1_err_irq_handler(void)
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) ||defined (HC32F472)
void SPI1_Handler(void)
{
hc32_spi1_err_irq_handler();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_SPI1 */
@@ -733,12 +734,12 @@ static void hc32_spi2_err_irq_handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) ||defined (HC32F472)
void SPI2_Handler(void)
{
hc32_spi2_err_irq_handler();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_SPI2 */
@@ -751,12 +752,12 @@ static void hc32_spi3_err_irq_handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) ||defined (HC32F472)
void SPI3_Handler(void)
{
hc32_spi3_err_irq_handler();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_SPI3 */

76
bsp/hc32/libraries/hc32_drivers/drv_usart.c
View File

@@ -7,6 +7,7 @@
* Date Author Notes
* 2022-04-28 CDT first version
* 2023-10-09 CDT support HC32F448
* 2024-04-15 CDT support HC32F472
*/
/*******************************************************************************
@@ -46,10 +47,8 @@
#if defined (HC32F460)
#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd
#elif defined (HC32F4A0) || defined (HC32F448)
#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd
#endif
#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd
@@ -162,7 +161,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
#elif defined (HC32F460)
if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
(CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
(CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
#endif
@@ -220,7 +219,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
{
uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
}
#if defined (HC32F4A0) || defined (HC32F448)
#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
switch (cfg->flowcontrol)
{
case RT_SERIAL_FLOWCONTROL_NONE:
@@ -271,7 +270,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
/* Enable error interrupt */
#if defined (HC32F460) || defined (HC32F4A0)
NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE);
@@ -300,7 +299,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
#if defined (HC32F460) || defined (HC32F4A0)
NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
#endif
}
@@ -310,7 +309,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num);
USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
#endif
}
@@ -334,14 +333,14 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
}
else
else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
{
INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE);
USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
/* NVIC config */
if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
{
@@ -349,7 +348,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE);
USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
}
else
else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
{
USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
}
@@ -504,7 +503,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
{
RT_ASSERT(TMR0_CH_B == ch);
}
#elif defined(HC32F4A0)
#elif defined (HC32F4A0)
if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance))
{
RT_ASSERT(TMR0_CH_A == ch);
@@ -513,7 +512,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
{
RT_ASSERT(TMR0_CH_B == ch);
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
{
RT_ASSERT(TMR0_CH_A == ch);
@@ -588,7 +587,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
RT_ASSERT(RT_NULL != rx_fifo);
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
#endif
@@ -748,7 +747,7 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
#endif
#endif
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
static void hc32_usart_handler(struct hc32_uart *uart)
{
RT_ASSERT(RT_NULL != uart);
@@ -758,7 +757,10 @@ static void hc32_usart_handler(struct hc32_uart *uart)
(ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \
(ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src)))
{
#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || \
defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA)
hc32_uart_rxto_irq_handler(uart);
#endif
}
#endif
@@ -835,7 +837,7 @@ static void hc32_uart1_tc_irq_handler(void)
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART1_TxComplete_Handler(void)
{
hc32_uart1_tc_irq_handler();
@@ -870,7 +872,7 @@ static void hc32_uart1_dma_rx_irq_handler(void)
#endif /* BSP_UART1_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART1_Handler(void)
{
/* enter interrupt */
@@ -881,7 +883,7 @@ void USART1_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART1 */
#if defined (BSP_USING_UART2)
@@ -933,7 +935,7 @@ static void hc32_uart2_tc_irq_handler(void)
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART2_TxComplete_Handler(void)
{
hc32_uart2_tc_irq_handler();
@@ -968,7 +970,7 @@ static void hc32_uart2_dma_rx_irq_handler(void)
#endif /* BSP_UART2_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART2_Handler(void)
{
/* enter interrupt */
@@ -979,7 +981,7 @@ void USART2_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART2 */
#if defined (BSP_USING_UART3)
@@ -1058,7 +1060,7 @@ static void hc32_uart3_dma_rx_irq_handler(void)
#endif /* RT_SERIAL_USING_DMA */
#endif /* HC32F460, HC32F4A0 */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART3_Handler(void)
{
/* enter interrupt */
@@ -1069,7 +1071,7 @@ void USART3_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART3 */
#if defined (BSP_USING_UART4)
@@ -1121,12 +1123,12 @@ static void hc32_uart4_tc_irq_handler(void)
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART4_TxComplete_Handler(void)
{
hc32_uart4_tc_irq_handler();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined (BSP_UART4_RX_USING_DMA)
@@ -1156,7 +1158,7 @@ static void hc32_uart4_dma_rx_irq_handler(void)
#endif /* BSP_UART4_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART4_Handler(void)
{
/* enter interrupt */
@@ -1167,7 +1169,7 @@ void USART4_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART4 */
#if defined (BSP_USING_UART5)
@@ -1206,7 +1208,7 @@ static void hc32_uart5_rxerr_irq_handler(void)
}
#endif /* HC32F460, HC32F4A0 */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
#if defined (RT_SERIAL_USING_DMA)
#if defined (BSP_UART5_TX_USING_DMA)
static void hc32_uart5_tc_irq_handler(void)
@@ -1250,7 +1252,7 @@ void USART5_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART5 */
#if defined (BSP_USING_UART6)
@@ -1302,7 +1304,7 @@ static void hc32_uart6_tc_irq_handler(void)
}
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined (BSP_UART6_RX_USING_DMA)
static void hc32_uart6_rxto_irq_handler(void)
{
/* enter interrupt */
@@ -1328,7 +1330,7 @@ static void hc32_uart6_dma_rx_irq_handler(void)
#endif /* RT_SERIAL_USING_DMA */
#endif /* HC32F460, HC32F4A0 */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART6_Handler(void)
{
/* enter interrupt */
@@ -1339,7 +1341,7 @@ void USART6_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART6 */
#if defined (BSP_USING_UART7)
@@ -1577,7 +1579,7 @@ static void hc32_uart_get_dma_info(void)
#ifdef BSP_USING_UART3
uart_obj[UART3_INDEX].uart_dma_flag = 0;
#if defined (HC32F460) || defined (HC32F4A0)
#if defined (HC32F460)
#ifdef BSP_UART3_RX_USING_DMA
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
@@ -1605,7 +1607,7 @@ static void hc32_uart_get_dma_info(void)
static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
#if defined (HC32F460) || defined (HC32F4A0)
#if defined (HC32F460)
uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
#endif
uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
@@ -1623,7 +1625,7 @@ static void hc32_uart_get_dma_info(void)
#ifdef BSP_USING_UART5
uart_obj[UART5_INDEX].uart_dma_flag = 0;
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
#ifdef BSP_UART5_RX_USING_DMA
uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
@@ -1645,7 +1647,7 @@ static void hc32_uart_get_dma_info(void)
#ifdef BSP_USING_UART6
uart_obj[UART6_INDEX].uart_dma_flag = 0;
#if defined (HC32F460) || defined (HC32F4A0)
#if defined (HC32F4A0)
#ifdef BSP_UART6_RX_USING_DMA
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
@@ -1668,6 +1670,7 @@ static void hc32_uart_get_dma_info(void)
#ifdef BSP_USING_UART7
uart_obj[UART7_INDEX].uart_dma_flag = 0;
#if defined (HC32F4A0)
#ifdef BSP_UART7_RX_USING_DMA
uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
@@ -1686,6 +1689,7 @@ static void hc32_uart_get_dma_info(void)
uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq;
#endif
#endif
#endif
#ifdef BSP_USING_UART8
uart_obj[UART8_INDEX].uart_dma_flag = 0;

2
bsp/hc32/libraries/hc32_drivers/drv_usart.h
View File

@@ -57,7 +57,7 @@ struct hc32_uart_config
struct hc32_uart_irq_config rxerr_irq;
struct hc32_uart_irq_config rx_irq;
struct hc32_uart_irq_config tx_irq;
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
IRQn_Type irq_num;
en_int_src_t rxerr_int_src;
en_int_src_t tx_int_src;

72
bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c
View File

@@ -7,6 +7,7 @@
* Date Author Notes
* 2022-04-28 CDT first version
* 2024-02-06 CDT support HC32F448
* 2024-04-15 CDT support HC32F472
*/
/*******************************************************************************
@@ -47,7 +48,7 @@
#if defined (HC32F460)
#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd
#elif defined(HC32F4A0) || defined (HC32F448)
#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd
#endif
@@ -156,13 +157,13 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT;
uart_init.u32Baudrate = cfg->baud_rate;
uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK;
#if defined(HC32F4A0)
#if defined (HC32F4A0)
if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
(CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance))
#elif defined (HC32F460)
if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
(CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
(CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
#endif
@@ -220,7 +221,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
{
uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
}
#if defined (HC32F4A0) || defined (HC32F448)
#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
switch (cfg->flowcontrol)
{
case RT_SERIAL_FLOWCONTROL_NONE:
@@ -268,7 +269,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
/* Enable error interrupt */
#if defined (HC32F460) || defined (HC32F4A0)
NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE);
@@ -321,7 +322,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
#if defined (HC32F460) || defined (HC32F4A0)
NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
#endif
}
@@ -333,7 +334,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num);
INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
@@ -359,7 +360,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
}
else
else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
{
INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
@@ -368,7 +369,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
/* NVIC config */
if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
{
@@ -376,7 +377,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE);
USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
}
else
else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
{
NVIC_ClearPendingIRQ(uart->config->tc_irq.irq_config.irq_num);
NVIC_EnableIRQ(uart->config->tc_irq.irq_config.irq_num);
@@ -573,7 +574,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
{
RT_ASSERT(TMR0_CH_B == ch);
}
#elif defined(HC32F4A0)
#elif defined (HC32F4A0)
if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance))
{
RT_ASSERT(TMR0_CH_A == ch);
@@ -582,7 +583,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
{
RT_ASSERT(TMR0_CH_B == ch);
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
{
RT_ASSERT(TMR0_CH_A == ch);
@@ -657,7 +658,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
RT_ASSERT(RT_NULL != rx_fifo);
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
#endif
@@ -801,7 +802,7 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
#endif
#endif
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
static void hc32_usart_handler(struct hc32_uart *uart)
{
RT_ASSERT(RT_NULL != uart);
@@ -811,7 +812,10 @@ static void hc32_usart_handler(struct hc32_uart *uart)
(ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \
(ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src)))
{
#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || \
defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA)
hc32_uart_rxto_irq_handler(uart);
#endif
}
#endif
@@ -914,7 +918,7 @@ static void hc32_uart1_dma_rx_irq_handler(void)
#endif /* BSP_UART1_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART1_Handler(void)
{
/* enter interrupt */
@@ -936,7 +940,7 @@ void USART1_TxComplete_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART1 */
#if defined (BSP_USING_UART2)
@@ -1014,7 +1018,7 @@ static void hc32_uart2_dma_rx_irq_handler(void)
#endif /* BSP_UART2_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART2_Handler(void)
{
/* enter interrupt */
@@ -1036,7 +1040,7 @@ void USART2_TxComplete_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART2 */
#if defined (BSP_USING_UART3)
@@ -1115,7 +1119,7 @@ static void hc32_uart3_dma_rx_irq_handler(void)
#endif /* BSP_UART3_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART3_Handler(void)
{
/* enter interrupt */
@@ -1137,7 +1141,7 @@ void USART3_TxComplete_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART3 */
#if defined (BSP_USING_UART4)
@@ -1215,7 +1219,7 @@ static void hc32_uart4_dma_rx_irq_handler(void)
#endif /* BSP_UART4_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART4_Handler(void)
{
/* enter interrupt */
@@ -1237,7 +1241,7 @@ void USART4_TxComplete_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART4 */
#if defined (BSP_USING_UART5)
@@ -1287,7 +1291,7 @@ static void hc32_uart5_tc_irq_handler(void)
rt_interrupt_leave();
}
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
#if defined (RT_SERIAL_USING_DMA)
#if defined (BSP_UART5_RX_USING_DMA)
static void hc32_uart5_dma_rx_irq_handler(void)
@@ -1324,7 +1328,7 @@ void USART5_TxComplete_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART5 */
#if defined (BSP_USING_UART6)
@@ -1402,7 +1406,7 @@ static void hc32_uart6_dma_rx_irq_handler(void)
#endif /* BSP_UART6_RX_USING_DMA */
#endif /* RT_SERIAL_USING_DMA */
#if defined (HC32F448)
#if defined (HC32F448) || defined (HC32F472)
void USART6_Handler(void)
{
/* enter interrupt */
@@ -1424,7 +1428,7 @@ void USART6_TxComplete_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
#endif /* BSP_USING_UART6 */
#if defined (BSP_USING_UART7)
@@ -1698,7 +1702,7 @@ static void hc32_uart_get_info(void)
uart_obj[UART3_INDEX].serial.config = config;
uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
#if defined (HC32F460) || defined (HC32F4A0)
#if defined (HC32F460)
#ifdef BSP_UART3_RX_USING_DMA
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
@@ -1721,12 +1725,13 @@ static void hc32_uart_get_info(void)
uart_obj[UART4_INDEX].serial.config = config;
uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
#if defined (HC32F460) || defined (HC32F448) || defined (HC32F472)
#ifdef BSP_UART4_RX_USING_DMA
uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
#if defined (HC32F460) || defined (HC32F4A0)
#if defined (HC32F460)
uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
#endif
uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
@@ -1738,13 +1743,14 @@ static void hc32_uart_get_info(void)
uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
#endif
#endif
#endif
#ifdef BSP_USING_UART5
uart_obj[UART5_INDEX].uart_dma_flag = 0;
uart_obj[UART5_INDEX].serial.config = config;
uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
#if defined (HC32F460)
#if defined (HC32F448) || defined (HC32F472)
#ifdef BSP_UART5_RX_USING_DMA
uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
@@ -1766,7 +1772,7 @@ static void hc32_uart_get_info(void)
uart_obj[UART6_INDEX].serial.config = config;
uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
#if defined (HC32F460) || defined (HC32F4A0)
#if defined (HC32F4A0)
#ifdef BSP_UART6_RX_USING_DMA
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
@@ -1789,6 +1795,7 @@ static void hc32_uart_get_info(void)
uart_obj[UART7_INDEX].serial.config = config;
uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
#if defined (HC32F4A0)
#ifdef BSP_UART7_RX_USING_DMA
uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
@@ -1804,6 +1811,7 @@ static void hc32_uart_get_info(void)
uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
#endif
#endif
#endif
#ifdef BSP_USING_UART8
uart_obj[UART8_INDEX].uart_dma_flag = 0;
@@ -1916,7 +1924,7 @@ static void hc32_get_uart_callback(void)
uart_config[UART10_INDEX].tc_irq.irq_callback = hc32_uart10_tc_irq_handler;
#endif
}
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
/**
* @brief This function gets uart irq handle.
* @param None
@@ -1955,7 +1963,7 @@ static void hc32_get_uart_callback(void)
uart_config[UART6_INDEX].tc_irq.irq_callback = hc32_uart6_tc_irq_handler;
#endif
}
#endif /* HC32F448 */
#endif /* HC32F448, HC32F472 */
static const struct rt_uart_ops hc32_uart_ops =
{

2
bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h
View File

@@ -57,7 +57,7 @@ struct hc32_uart_config
struct hc32_uart_irq_config rxerr_irq;
struct hc32_uart_irq_config rx_irq;
struct hc32_uart_irq_config tx_irq;
#elif defined (HC32F448)
#elif defined (HC32F448) || defined (HC32F472)
IRQn_Type irq_num;
en_int_src_t rxerr_int_src;
en_int_src_t tx_int_src;

145
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h
View File

@@ -1,145 +0,0 @@
/**
*******************************************************************************
* @file stl_common.h
* @brief This file contains STL common definitions: enumeration, macros and
* structures definitions.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_COMMON_H__
#define __STL_COMMON_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup IEC60730_STL
* @{
*/
/**
* @addtogroup IEC60730_STL_Common
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup STL_Common_Global_Macros STL Common Global Macros
* @{
*/
/**
* @defgroup STL_Generic_Error_Codes STL Generic Error Codes
* @{
*/
#define STL_OK (0UL) /*!< No error occurs */
#define STL_ERR (1UL) /*!< Error occurs */
/**
* @}
*/
/**
* @defgroup STL_Module_Switch STL Module Switch
* @{
*/
#define STL_ON (1U)
#define STL_OFF (0U)
/**
* @}
*/
/**
* @defgroup Compiler_Macros Compiler Macros
* @{
*/
#ifdef __CC_ARM /*!< ARM Compiler */
/* CPU will start executing at the program entry label __main when the CPU is reset */
extern void __main(void);
/* CC */
#define STL_SECTION(x) __attribute__((section(x)))
#define STL_UNUSED __attribute__((unused))
#define STL_USED __attribute__((used))
#define STL_ALIGN(n) __attribute__((aligned(n)))
#define STL_WEAK __WEAKDEF
#define STL_INLINE static __inline
#define CallApplicationStartUp( ) __main()
#elif defined (__ICCARM__) /*!< IAR Compiler */
/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */
extern void __iar_program_start(void);
/* CC */
#define STL_SECTION(x) @ x
#define STL_UNUSED
#define STL_USED __root
#define STL_PRAGMA(x) _Pragma(#x)
#define STL_ALIGN(n) STL_PRAGMA(data_alignment=n)
#define STL_WEAK __WEAKDEF
#define STL_INLINE static inline
#define CallApplicationStartUp( ) __iar_program_start()
#else
#error Unsupported tool chain
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_COMMON_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

106
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h
View File

@@ -1,106 +0,0 @@
/**
*******************************************************************************
* @file stl_conf.h
* @brief This file contains STL resource configure.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2022-06-30 CDT Optimize macros definitions
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_CONF_H__
#define __STL_CONF_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_bsp_conf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup IEC60730_STL
* @{
*/
/**
* @addtogroup IEC60730_STL_Configure
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters
* @{
*/
#define STL_ROM_CRC32_START (STL_ROM_START)
#define STL_ROM_CRC32_END ((uint32_t)(&__checksum))
#define STL_ROM_CRC32_BLOCK_SIZE (128UL)
#define STL_ROM_CRC32_CC_CHECKSUM (__checksum)
/**
* @}
*/
/**
* @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters
* @{
*/
#define STL_MARCH_RAM_SIZE (32UL)
#define STL_MARCH_RAM_WORDS (STL_MARCH_RAM_SIZE >> 2)
#define STL_MARCH_RAM_BUF_SIZE (16UL)
#define STL_MARCH_RAM_BUF_WORDS (STL_MARCH_RAM_BUF_SIZE >> 2)
#define STL_MARCH_RAM_BCKGRND (0x00000000UL)
#define STL_MARCH_RAM_INVBCKGRND (0xFFFFFFFFUL)
#define STL_STACK_BOUNDARY_WORDS (4UL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_CONF_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

93
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h
View File

@@ -1,93 +0,0 @@
/**
*******************************************************************************
* @file stl_test_flash.h
* @brief This file contains all the functions prototypes of the flash test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_SW_CRC32_H__
#define __STL_SW_CRC32_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_CRC32
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros
* @{
*/
#define STL_CRC32_INIT_VALUE (0xFFFFFFFFUL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_CRC32_Global_Functions
* @{
*/
uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_SW_CRC32_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

85
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h
View File

@@ -1,85 +0,0 @@
/**
*******************************************************************************
* @file stl_test_cpu.h
* @brief This file contains all the functions prototypes of the CPU test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_CPU_H__
#define __STL_TEST_CPU_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_CPU
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_CPU_Global_Functions
* @{
*/
uint32_t STL_CpuTestStartup(void);
uint32_t STL_CpuTestRuntime(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_CPU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

85
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h
View File

@@ -1,85 +0,0 @@
/**
*******************************************************************************
* @file stl_test_flash.h
* @brief This file contains all the functions prototypes of the flash test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_FLASH_H__
#define __STL_TEST_FLASH_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_Flash
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_Flash_Global_Functions
* @{
*/
uint32_t STL_FlashStartupTest(void);
uint32_t STL_FlashRuntimeTest(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_FLASH_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

99
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h
View File

@@ -1,99 +0,0 @@
/**
*******************************************************************************
* @file stl_test_interrupt.h
* @brief This file contains all the functions prototypes of the interrupt test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_INTERRUPT_H__
#define __STL_TEST_INTERRUPT_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_Interrupt
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/**
* @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type
* @{
*/
typedef struct stc_stl_int_params {
uint32_t u32FreqInitVal;
uint32_t u32FreqLowerVal;
uint32_t u32FreqUpperVal;
uint32_t u32PrivateParam;
} stc_stl_int_params_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_Interrupt_Global_Functions
* @{
*/
uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize);
uint32_t STL_IntRuntimeTest(void);
void STL_IntUpdateCount(uint8_t u8ParamIndex);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_INTERRUPT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

84
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h
View File

@@ -1,84 +0,0 @@
/**
*******************************************************************************
* @file stl_test_pc.h
* @brief This file contains all the functions prototypes of the PC test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_PC_H__
#define __STL_TEST_PC_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_PC
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_PC_Global_Functions
* @{
*/
uint32_t STL_PcTest(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_PC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

88
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h
View File

@@ -1,88 +0,0 @@
/**
*******************************************************************************
* @file stl_test_ram.h
* @brief This file contains all the functions prototypes of the RAM test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_RAM_H__
#define __STL_TEST_RAM_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_RAM
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_RAM_Global_Functions
* @{
*/
uint32_t STL_StackRuntimeInit(void);
uint32_t STL_StackRuntimeTest(void);
uint32_t STL_RamRuntimeInit(void);
uint32_t STL_RamRuntimeTest(void);
uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_RAM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

372
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s
View File

@@ -1,372 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Version V1.0 */
;/* Date 2022-09-14 */
;/****************************************************************************/
SECTION constdata:CONST(2)
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
data0x80000000 DCD 0x80000000
data0xAAAAAAA8 DCD 0xAAAAAAA8
data0x55555554 DCD 0x55555554
data0x00000000 DCD 0x00000000
data0x00000001 DCD 0x00000001
data0x50000000 DCD 0x50000000
data0xA0000000 DCD 0xA0000000
; Exported function
EXPORT STL_CpuTestStartup
;*******************************************************************************
; Function Name : STL_CpuTestStartup
; Description : Test CPU at start-up
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
THUMB
SECTION .text:CODE(2)
STL_CpuTestStartup:
PUSH {R4-R7} ; Save registers
_test_cpu_reg0_reg8
MOVS R0, #0x00
UXTB R0, R0
ADDS R0, #0 ; Set Z(ero) Flag
BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
SUBS R0, #1 ; Set N(egative) Flag
BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
ADDS R0, #2 ; Set C(arry) Flag and do not set Z
BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
LDR R0, =data0x80000000 ; Prepares Overflow test
LDR R0, [R0]
ADDS R0, R0, R0 ; Set V(overflow) Flag
BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_reg0_reg13_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_reg0_reg13_fail
CMP R2, #0x02
BNE _test_cpu_reg0_reg13_fail
CMP R3, #0x03
BNE _test_cpu_reg0_reg13_fail
CMP R4, #0x04
BNE _test_cpu_reg0_reg13_fail
CMP R5, #0x05
BNE _test_cpu_reg0_reg13_fail
CMP R6, #0x06
BNE _test_cpu_reg0_reg13_fail
CMP R7, #0x07
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
; Process Stack pointer (banked Register R13)
MRS R0, PSP ; Save process stack value
LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
MSR PSP, R0 ; Restore process stack value
; Stack pointer (Register R13)
MRS R0, MSP ; Save stack pointer value
LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR MSP, R1 ; load SP value
MRS R2, MSP ; Get back SP value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554
LDR R1, [R1] ; load SP value
MSR MSP, R1 ; Get back SP value
MRS R2, MSP ; Verify value
CMP R2, R1
BNE _test_cpu_reg0_reg13_fail
MSR MSP, R0 ; Restore stack pointer value
_test_cpu_r14_sfr
; Link register R14
MOV R1, LR
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
MOV LR, R1
; APSR
MRS R0, APSR
LDR R1, =data0x50000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0xA0000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR APSR,R0
; PRIMASK register
MRS R0, PRIMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR PRIMASK, R0
B _test_cpu_pass
_test_cpu_r14_sfr_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_pass
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _test_exit
_test_exit
POP {R4-R7} ; Restore registers
BX LR
END

420
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s
View File

@@ -1,420 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Date Author Notes */
;/* 2022-09-14 CDT First version */
;/* 2022-12-20 CDT Load data to R0 before USAT */
;/* 2023-05-31 CDT Typo: Veriry -> Verify */
;/****************************************************************************/
SECTION constdata:CONST(2)
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
data0x80000000 DCD 0x80000000
data0xAAAAAAA8 DCD 0xAAAAAAA8
data0x55555554 DCD 0x55555554
data0x00000000 DCD 0x00000000
data0x00000001 DCD 0x00000001
data0x50000000 DCD 0x50000000
data0xA8000000 DCD 0xA8000000
data0x00000050 DCD 0x00000050
data0x000000A0 DCD 0x000000A0
data0xFFFFFFFF DCD 0xFFFFFFFF
; Exported function
EXPORT STL_CpuTestStartup
;*******************************************************************************
; Function Name : STL_CpuTestStartup
; Description : Test CPU at start-up
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
THUMB
SECTION .text:CODE(2)
STL_CpuTestStartup:
PUSH {R4-R7} ; Save registers
_test_cpu_reg0_reg8
MOVS R0, #0x00
UXTB R0, R0
ADDS R0, #0 ; Set Z(ero) Flag
BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
SUBS R0, #1 ; Set N(egative) Flag
BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
ADDS R0, #2 ; Set C(arry) Flag and do not set Z
BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
LDR R0, =data0x80000000 ; Prepares Overflow test
LDR R0, [R0]
ADDS R0, R0, R0 ; Set V(overflow) Flag
BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
MOV R0, #0
MSR APSR, R0
LDR R0, =data0xFFFFFFFF ; Prepares Saturation test
LDR R0, [R0]
USAT R1, #10, R0 ; Set Q(saturation) flag
MRS R0, APSR ; Get APSR status register
CMP R0, #0x08000000 ; Verify Q=1
BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_reg0_reg13_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_reg0_reg13_fail
CMP R2, #0x02
BNE _test_cpu_reg0_reg13_fail
CMP R3, #0x03
BNE _test_cpu_reg0_reg13_fail
CMP R4, #0x04
BNE _test_cpu_reg0_reg13_fail
CMP R5, #0x05
BNE _test_cpu_reg0_reg13_fail
CMP R6, #0x06
BNE _test_cpu_reg0_reg13_fail
CMP R7, #0x07
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
; Process Stack pointer (banked Register R13)
MRS R0, PSP ; Save process stack value
LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
MSR PSP, R0 ; Restore process stack value
; Stack pointer (Register R13)
MRS R0, MSP ; Save stack pointer value
LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR MSP, R1 ; load SP value
MRS R2, MSP ; Get back SP value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554
LDR R1, [R1] ; load SP value
MSR MSP, R1 ; Get back SP value
MRS R2, MSP ; Verify value
CMP R2, R1
BNE _test_cpu_reg0_reg13_fail
MSR MSP, R0 ; Restore stack pointer value
_test_cpu_r14_sfr
; Link register R14
MOV R1, LR
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
MOV LR, R1
; APSR
MRS R0, APSR
LDR R1, =data0x50000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0xA8000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR APSR,R0
; PRIMASK register
MRS R0, PRIMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR PRIMASK, R0
; FAULTMASK register
MRS R0, FAULTMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR FAULTMASK, R1
MRS R2, FAULTMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR FAULTMASK, R1
MRS R2, FAULTMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR FAULTMASK, R0
; BASEPRI register
MRS R0, BASEPRI
LDR R1, =data0x000000A0
LDR R1, [R1]
MSR BASEPRI, R1
MRS R2, BASEPRI
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000050
LDR R1, [R1]
MSR BASEPRI, R1
MRS R2, BASEPRI
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR BASEPRI, R0
B _test_cpu_pass
_test_cpu_r14_sfr_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_pass
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _test_exit
_test_exit
POP {R4-R7} ; Restore registers
BX LR
END

245
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s
View File

@@ -1,245 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Version V1.0 */
;/* Date 2022-03-31 */
;/****************************************************************************/
SECTION constdata:CONST(2)
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
; Exported function
EXPORT STL_CpuTestRuntime
;*******************************************************************************
; Function Name : STL_CpuTestRuntime
; Description : Test CPU at run-time
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
THUMB
SECTION .text:CODE(2)
STL_CpuTestRuntime:
PUSH {R4-R7} ; Save registers
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_fail
CMP R2, #0x02
BNE _test_cpu_fail
CMP R3, #0x03
BNE _test_cpu_fail
CMP R4, #0x04
BNE _test_cpu_fail
CMP R5, #0x05
BNE _test_cpu_fail
CMP R6, #0x06
BNE _test_cpu_fail
CMP R7, #0x07
BNE _test_cpu_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_fail
; Link register R14
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
_test_exit
POP {R4-R7} ; Restore registers
BX LR ; return
END

186
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s
View File

@@ -1,186 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Version V1.0 */
;/* Date 2022-03-31 */
;/****************************************************************************/
SECTION constdata:CONST(2)
data0x00000000 DCD 0x00000000
data0xFFFFFFFF DCD 0xFFFFFFFF
; Exported function
EXPORT STL_FullRamTestStartup
;*******************************************************************************
; Function Name : STL_FullRamTestStartup
; Description : Full RAM test at start-up
; Input : R0 .. RAM begin address
; R1 .. RAM end address
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
THUMB
SECTION .text:CODE(2)
STL_FullRamTestStartup:
MOVS R4, #0x0 ; STL_OK:Test success status by default
LDR R2, =data0x00000000 ; Prepares background pattern
LDR R2, [R2]
LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern
LDR R3, [R3]
; *** Step 1 ***
; Write background pattern with addresses increasing
MOVS R5, R0
_step1_loop:
CMP R5, R1
BHI _step_2
STR R2, [R5, #+0]
ADDS R5, R5, #+4
B _step1_loop
; *** Step 2 ***
; Verify background and write inverted background with addresses increasing
_step_2:
MOVS R5, R0
_step_2_loop:
CMP R5, R1
BHI _step_3
LDR R6, [R5, #+0]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+0]
LDR R6, [R5, #+4]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+4]
LDR R6, [R5, #+8]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+8]
LDR R6, [R5, #+12]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+12]
ADDS R5, R5, #+16
B _step_2_loop
; *** Step 3 ***
; Verify inverted background and write background with addresses increasing
_step_3:
MOVS R5, R0
_step_3_loop:
CMP R5, R1
BHI _step_4
LDR R6, [R5, #+0]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+0]
LDR R6, [R5, #+4]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+4]
LDR R6, [R5, #+8]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+8]
LDR R6, [R5, #+12]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+12]
ADDS R5, R5, #+16
B _step_3_loop
; *** Step 4 ***
; Verify background and write inverted background with addresses decreasing
_step_4:
MOVS R5, R1
SUBS R5, R5, #+15
_step_4_loop:
CMP R5, R0
BLO _step_5
LDR R6, [R5, #+12]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+12]
LDR R6, [R5, #+8]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+8]
LDR R6, [R5, #+4]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+4]
LDR R6, [R5, #+0]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+0]
SUBS R5, R5, #+16
B _step_4_loop
; *** Step 5 ***
; Verify inverted background and write background with addresses decreasing
_step_5:
MOVS R5, R1
SUBS R5, R5, #+15
_step_5_loop:
CMP R5, R0
BLO _step_6
LDR R6, [R5, #+12]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+12]
LDR R6, [R5, #+8]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+8]
LDR R6, [R5, #+4]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+4]
LDR R6, [R5, #+0]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+0]
SUBS R5, R5, #+16
B _step_5_loop
; *** Step 6 ***
; Verify background with addresses increasing
_step_6:
MOVS R5, R0
_step_6_loop:
CMP R5, R1
BHI _full_ram1_test_pass
LDR R6, [R5, #+0]
CMP R6, R2
BNE _full_ram1_test_fail
ADDS R5, R5, #+4
B _step_6_loop
_full_ram1_test_fail:
MOVS R4, #1 ; STL_ERR
_full_ram1_test_pass:
MOVS R0, R4
BX LR ; return to the caller
END

148
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s
View File

@@ -1,148 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Date Author Notes */
;/* 2022-03-31 CDT First version */
;/* 2023-05-31 CDT Typo: subrouitne -> subroutine */
;/****************************************************************************/
; Exported function
EXPORT STL_PcTest
;*******************************************************************************
; Function Name : STL_PcTest
; Description : Test PC
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
SECTION .text:CODE(2)
THUMB
STL_PcTest
PUSH {R4-R7} ; Save registers
MOVS R0, #0
MOVS R1, #0 ; clr R0,R1
MOV R3, LR
_subroutine_1
LDR R0, =_return_pc_test_addr_1
BL _return_pc_test_addr_1
CMP R0, R1 ; verify return address?
BEQ _subroutine_2
B _pc_test_fail
_subroutine_2
LDR R0, =_return_pc_test_addr_2
BL _return_pc_test_addr_2
CMP R0, R1 ; verify return address?
BEQ _subroutine_3
B _pc_test_fail
_subroutine_3
LDR R0, =_return_pc_test_addr_3
BL _return_pc_test_addr_3
CMP R0, R1 ; verify return address?
BEQ _subroutine_4
B _pc_test_fail
_subroutine_4
LDR R0, =_return_pc_test_addr_4
BL _return_pc_test_addr_4
CMP R0, R1 ; verify return address?
BEQ _subroutine_5
B _pc_test_fail
_subroutine_5
LDR R0, =_return_pc_test_addr_5
BL _return_pc_test_addr_5
CMP R0, R1 ; verify return address?
BEQ _subroutine_6
B _pc_test_fail
_subroutine_6
LDR R0, =_return_pc_test_addr_6
BL _return_pc_test_addr_6
CMP R0, R1 ; verify return address?
BEQ _subroutine_7
B _pc_test_fail
_subroutine_7
LDR R0, =_return_pc_test_addr_7
BL _return_pc_test_addr_7
CMP R0, R1 ; verify return address?
BEQ _subroutine_8
B _pc_test_fail
_subroutine_8
LDR R0, =_return_pc_test_addr_8
BL _return_pc_test_addr_8
CMP R0, R1 ; verify return address?
BEQ _pc_test_pass
B _pc_test_fail
_pc_test_fail
; when test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _pc_test_exit
_pc_test_pass
; when test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _pc_test_exit
_pc_test_exit:
POP {R4-R7} ; Restore registers
BX R3 ; return
SECTION .pctestaddr1:CODE(2)
_return_pc_test_addr_1
LDR R1, =_return_pc_test_addr_1 ; store subroutine address in R1
BX LR
SECTION .pctestaddr2:CODE(2)
_return_pc_test_addr_2
LDR R1, =_return_pc_test_addr_2 ; store subroutine address in R1
BX LR
SECTION .pctestaddr3:CODE(2)
_return_pc_test_addr_3
LDR R1, =_return_pc_test_addr_3 ; store subroutine address in R1
BX LR
SECTION .pctestaddr4:CODE(2)
_return_pc_test_addr_4
LDR R1, =_return_pc_test_addr_4 ; store subroutine address in R1
BX LR
SECTION .pctestaddr5:CODE(2)
_return_pc_test_addr_5
LDR R1, =_return_pc_test_addr_5 ; store subroutine address in R1
BX LR
SECTION .pctestaddr6:CODE(2)
_return_pc_test_addr_6
LDR R1, =_return_pc_test_addr_6 ; store subroutine address in R1
BX LR
SECTION .pctestaddr7:CODE(2)
_return_pc_test_addr_7
LDR R1, =_return_pc_test_addr_7 ; store subroutine address in R1
BX LR
SECTION .pctestaddr8:CODE(2)
_return_pc_test_addr_8
LDR R1, =_return_pc_test_addr_8 ; store subroutine address in R1
BX LR
END

378
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s
View File

@@ -1,378 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for MDK */
;/* Version V1.0 */
;/* Date 2022-09-14 */
;/****************************************************************************/
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
data0x80000000 DCD 0x80000000
data0xAAAAAAA8 DCD 0xAAAAAAA8
data0x55555554 DCD 0x55555554
data0x00000000 DCD 0x00000000
data0x00000001 DCD 0x00000001
data0x50000000 DCD 0x50000000
data0xA0000000 DCD 0xA0000000
;*******************************************************************************
; Function Name : STL_CpuTestStartup
; Description : Test CPU at start-up
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
STL_CpuTestStartup PROC
EXPORT STL_CpuTestStartup
PUSH {R4-R7} ; Save registers
_test_cpu_reg0_reg8
MOVS R0, #0x00
UXTB R0, R0
ADDS R0, #0 ; Set Z(ero) Flag
BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
SUBS R0, #1 ; Set N(egative) Flag
BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
ADDS R0, #2 ; Set C(arry) Flag and do not set Z
BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
LDR R0, =data0x80000000 ; Prepares Overflow test
LDR R0, [R0]
ADDS R0, R0, R0 ; Set V(overflow) Flag
BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_reg0_reg13_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_reg0_reg13_fail
CMP R2, #0x02
BNE _test_cpu_reg0_reg13_fail
CMP R3, #0x03
BNE _test_cpu_reg0_reg13_fail
CMP R4, #0x04
BNE _test_cpu_reg0_reg13_fail
CMP R5, #0x05
BNE _test_cpu_reg0_reg13_fail
CMP R6, #0x06
BNE _test_cpu_reg0_reg13_fail
CMP R7, #0x07
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
; Process Stack pointer (banked Register R13)
MRS R0, PSP ; Save process stack value
LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
MSR PSP, R0 ; Restore process stack value
; Stack pointer (Register R13)
MRS R0, MSP ; Save stack pointer value
LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR MSP, R1 ; load SP value
MRS R2, MSP ; Get back SP value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554
LDR R1, [R1] ; load SP value
MSR MSP, R1 ; Get back SP value
MRS R2, MSP ; Verify value
CMP R2, R1
BNE _test_cpu_reg0_reg13_fail
MSR MSP, R0 ; Restore stack pointer value
_test_cpu_r14_sfr
; Link register R14
MOV R1, LR
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
MOV LR, R1
; APSR
MRS R0, APSR
LDR R1, =data0x50000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0xA0000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR APSR,R0
; PRIMASK register
MRS R0, PRIMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR PRIMASK, R0
B _test_cpu_pass
_test_cpu_r14_sfr_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_pass
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _test_exit
_test_exit
POP {R4-R7} ; Restore registers
BX LR
ENDP
ALIGN
END

426
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s
View File

@@ -1,426 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for MDK */
;/* Date Author Notes */
;/* 2022-09-14 CDT First version */
;/* 2022-12-20 CDT Load data to R0 before USAT */
;/* 2023-05-31 CDT Typo: Veriry -> Verify */
;/****************************************************************************/
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
data0x80000000 DCD 0x80000000
data0xAAAAAAA8 DCD 0xAAAAAAA8
data0x55555554 DCD 0x55555554
data0x00000000 DCD 0x00000000
data0x00000001 DCD 0x00000001
data0x50000000 DCD 0x50000000
data0xA8000000 DCD 0xA8000000
data0x00000050 DCD 0x00000050
data0x000000A0 DCD 0x000000A0
data0xFFFFFFFF DCD 0xFFFFFFFF
;*******************************************************************************
; Function Name : STL_CpuTestStartup
; Description : Test CPU at start-up
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
STL_CpuTestStartup PROC
EXPORT STL_CpuTestStartup
PUSH {R4-R7} ; Save registers
_test_cpu_reg0_reg8
MOVS R0, #0x00
UXTB R0, R0
ADDS R0, #0 ; Set Z(ero) Flag
BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
SUBS R0, #1 ; Set N(egative) Flag
BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
ADDS R0, #2 ; Set C(arry) Flag and do not set Z
BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
LDR R0, =data0x80000000 ; Prepares Overflow test
LDR R0, [R0]
ADDS R0, R0, R0 ; Set V(overflow) Flag
BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
MOV R0, #0
MSR APSR, R0
LDR R0, =data0xFFFFFFFF ; Prepares Saturation test
LDR R0, [R0]
USAT R1, #10, R0 ; Set Q(saturation) flag
MRS R0, APSR ; Get APSR status register
CMP R0, #0x08000000 ; Verify Q=1
BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_reg0_reg13_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_reg0_reg13_fail
CMP R2, #0x02
BNE _test_cpu_reg0_reg13_fail
CMP R3, #0x03
BNE _test_cpu_reg0_reg13_fail
CMP R4, #0x04
BNE _test_cpu_reg0_reg13_fail
CMP R5, #0x05
BNE _test_cpu_reg0_reg13_fail
CMP R6, #0x06
BNE _test_cpu_reg0_reg13_fail
CMP R7, #0x07
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
; Process Stack pointer (banked Register R13)
MRS R0, PSP ; Save process stack value
LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
MSR PSP, R0 ; Restore process stack value
; Stack pointer (Register R13)
MRS R0, MSP ; Save stack pointer value
LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR MSP, R1 ; load SP value
MRS R2, MSP ; Get back SP value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554
LDR R1, [R1] ; load SP value
MSR MSP, R1 ; Get back SP value
MRS R2, MSP ; Verify value
CMP R2, R1
BNE _test_cpu_reg0_reg13_fail
MSR MSP, R0 ; Restore stack pointer value
_test_cpu_r14_sfr
; Link register R14
MOV R1, LR
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
MOV LR, R1
; APSR
MRS R0, APSR
LDR R1, =data0x50000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0xA8000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR APSR,R0
; PRIMASK register
MRS R0, PRIMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR PRIMASK, R0
; FAULTMASK register
MRS R0, FAULTMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR FAULTMASK, R1
MRS R2, FAULTMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR FAULTMASK, R1
MRS R2, FAULTMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR FAULTMASK, R0
; BASEPRI register
MRS R0, BASEPRI
LDR R1, =data0x000000A0
LDR R1, [R1]
MSR BASEPRI, R1
MRS R2, BASEPRI
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000050
LDR R1, [R1]
MSR BASEPRI, R1
MRS R2, BASEPRI
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR BASEPRI, R0
B _test_cpu_pass
_test_cpu_r14_sfr_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_pass
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _test_exit
_test_exit
POP {R4-R7} ; Restore registers
BX LR
ENDP
ALIGN
END

251
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s
View File

@@ -1,251 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for MDK */
;/* Version V1.0 */
;/* Date 2022-03-31 */
;/****************************************************************************/
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
;*******************************************************************************
; Function Name : STL_CpuTestRuntime
; Description : Test CPU at run-time
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
STL_CpuTestRuntime PROC
EXPORT STL_CpuTestRuntime
PUSH {R4-R7} ; Save registers
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_fail
CMP R2, #0x02
BNE _test_cpu_fail
CMP R3, #0x03
BNE _test_cpu_fail
CMP R4, #0x04
BNE _test_cpu_fail
CMP R5, #0x05
BNE _test_cpu_fail
CMP R6, #0x06
BNE _test_cpu_fail
CMP R7, #0x07
BNE _test_cpu_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_fail
; Link register R14
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
_test_exit
POP {R4-R7} ; Restore registers
BX LR ; return
ENDP
ALIGN
END

191
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s
View File

@@ -1,191 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for MDK */
;/* Version V1.0 */
;/* Date 2022-03-31 */
;/****************************************************************************/
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
data0x00000000 DCD 0x00000000
data0xFFFFFFFF DCD 0xFFFFFFFF
;*******************************************************************************
; Function Name : STL_FullRamTestStartup
; Description : Full RAM test at start-up
; Input : R0 .. RAM begin address
; R1 .. RAM end address
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
STL_FullRamTestStartup PROC
EXPORT STL_FullRamTestStartup
MOVS R4, #0x0 ; STL_OK:Test success status by default
LDR R2, =data0x00000000 ; Prepares background pattern
LDR R2, [R2]
LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern
LDR R3, [R3]
; *** Step 1 ***
; Write background pattern with addresses increasing
MOVS R5, R0
_step1_loop
CMP R5, R1
BHI _step_2
STR R2, [R5, #+0]
ADDS R5, R5, #+4
B _step1_loop
; *** Step 2 ***
; Verify background and write inverted background with addresses increasing
_step_2
MOVS R5, R0
_step_2_loop
CMP R5, R1
BHI _step_3
LDR R6, [R5, #+0]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+0]
LDR R6, [R5, #+4]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+4]
LDR R6, [R5, #+8]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+8]
LDR R6, [R5, #+12]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+12]
ADDS R5, R5, #+16
B _step_2_loop
; *** Step 3 ***
; Verify inverted background and write background with addresses increasing
_step_3
MOVS R5, R0
_step_3_loop
CMP R5, R1
BHI _step_4
LDR R6, [R5, #+0]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+0]
LDR R6, [R5, #+4]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+4]
LDR R6, [R5, #+8]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+8]
LDR R6, [R5, #+12]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+12]
ADDS R5, R5, #+16
B _step_3_loop
; *** Step 4 ***
; Verify background and write inverted background with addresses decreasing
_step_4
MOVS R5, R1
SUBS R5, R5, #+15
_step_4_loop
CMP R5, R0
BLO _step_5
LDR R6, [R5, #+12]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+12]
LDR R6, [R5, #+8]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+8]
LDR R6, [R5, #+4]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+4]
LDR R6, [R5, #+0]
CMP R6, R2
BNE _full_ram1_test_fail
STR R3, [R5, #+0]
SUBS R5, R5, #+16
B _step_4_loop
; *** Step 5 ***
; Verify inverted background and write background with addresses decreasing
_step_5
MOVS R5, R1
SUBS R5, R5, #+15
_step_5_loop
CMP R5, R0
BLO _step_6
LDR R6, [R5, #+12]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+12]
LDR R6, [R5, #+8]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+8]
LDR R6, [R5, #+4]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+4]
LDR R6, [R5, #+0]
CMP R6, R3
BNE _full_ram1_test_fail
STR R2, [R5, #+0]
SUBS R5, R5, #+16
B _step_5_loop
; *** Step 6 ***
; Verify background with addresses increasing
_step_6
MOVS R5, R0
_step_6_loop
CMP R5, R1
BHI _full_ram1_test_pass
LDR R6, [R5, #+0]
CMP R6, R2
BNE _full_ram1_test_fail
ADDS R5, R5, #+4
B _step_6_loop
_full_ram1_test_fail
MOVS R4, #1 ; STL_ERR
_full_ram1_test_pass
MOVS R0, R4
BX LR ; return to the caller
ENDP
ALIGN
END

147
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s
View File

@@ -1,147 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for MDK */
;/* Date Author Notes */
;/* 2022-03-31 CDT First version */
;/* 2023-05-31 CDT Typo: subrouitne -> subroutine */
;/****************************************************************************/
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
;*******************************************************************************
; Function Name : STL_PcTest
; Description : Test PC
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
STL_PcTest PROC
EXPORT STL_PcTest
PUSH {R4-R7} ; Save registers
MOVS R0, #0
MOVS R1, #0 ; clr R0,R1
MOV R3, LR
_subroutine_1
LDR R0, =_return_pc_test_addr_1
BL _return_pc_test_addr_1
CMP R0, R1 ; verify return address?
BEQ _subroutine_2
B _pc_test_fail
_subroutine_2
LDR R0, =_return_pc_test_addr_2
BL _return_pc_test_addr_2
CMP R0, R1 ; verify return address?
BEQ _subroutine_3
B _pc_test_fail
_subroutine_3
LDR R0, =_return_pc_test_addr_3
BL _return_pc_test_addr_3
CMP R0, R1 ; verify return address?
BEQ _subroutine_4
B _pc_test_fail
_subroutine_4
LDR R0, =_return_pc_test_addr_4
BL _return_pc_test_addr_4
CMP R0, R1 ; verify return address?
BEQ _subroutine_5
B _pc_test_fail
_subroutine_5
LDR R0, =_return_pc_test_addr_5
BL _return_pc_test_addr_5
CMP R0, R1 ; verify return address?
BEQ _subroutine_6
B _pc_test_fail
_subroutine_6
LDR R0, =_return_pc_test_addr_6
BL _return_pc_test_addr_6
CMP R0, R1 ; verify return address?
BEQ _subroutine_7
B _pc_test_fail
_subroutine_7
LDR R0, =_return_pc_test_addr_7
BL _return_pc_test_addr_7
CMP R0, R1 ; verify return address?
BEQ _subroutine_8
B _pc_test_fail
_subroutine_8
LDR R0, =_return_pc_test_addr_8
BL _return_pc_test_addr_8
CMP R0, R1 ; verify return address?
BEQ _pc_test_pass
B _pc_test_fail
_pc_test_fail
; when test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _pc_test_exit
_pc_test_pass
; when test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _pc_test_exit
_pc_test_exit
POP {R4-R7} ; Restore registers
BX R3 ; return
_return_pc_test_addr_1
LDR R1, =_return_pc_test_addr_1 ; store subroutine address in R1
BX LR
_return_pc_test_addr_2
LDR R1, =_return_pc_test_addr_2 ; store subroutine address in R1
BX LR
_return_pc_test_addr_3
LDR R1, =_return_pc_test_addr_3 ; store subroutine address in R1
BX LR
_return_pc_test_addr_4
LDR R1, =_return_pc_test_addr_4 ; store subroutine address in R1
BX LR
_return_pc_test_addr_5
LDR R1, =_return_pc_test_addr_5 ; store subroutine address in R1
BX LR
_return_pc_test_addr_6
LDR R1, =_return_pc_test_addr_6 ; store subroutine address in R1
BX LR
_return_pc_test_addr_7
LDR R1, =_return_pc_test_addr_7 ; store subroutine address in R1
BX LR
_return_pc_test_addr_8
LDR R1, =_return_pc_test_addr_8 ; store subroutine address in R1
BX LR
ENDP
ALIGN
END

154
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c
View File

@@ -1,154 +0,0 @@
/**
*******************************************************************************
* @file stl_sw_crc32.c
* @brief This file provides firmware functions to manage the software CRC32.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_sw_crc32.h"
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @defgroup STL_IEC60730_CRC32 STL IEC60730 CRC32
* @brief IEC60730 software CRC32
* @{
*/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_CRC32_Local_Variables STL IEC60730 CRC32 Local Variables
* @{
*/
static const uint32_t m_au32Crc32Table[256] = {
0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F,
0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2,
0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9,
0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C,
0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423,
0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106,
0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D,
0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950,
0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7,
0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA,
0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81,
0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84,
0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB,
0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E,
0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55,
0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28,
0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F,
0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242,
0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69,
0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC,
0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693,
0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
};
/**
* @}
*/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_CRC32_Global_Functions STL IEC60730 CRC32 Global Functions
* @{
*/
/**
* @brief Calculate CRC32 value.
* @param [in] u32Crc32Value CRC32 value
* @param [in] pu8Data Pointer to data buffer
* @param [in] u32Len Data length
* @retval CRC32 value
* @note Poly=0x04C11DB7, Init=0xFFFFFFFF, RefIn=true, RefOut=true, XorOut=0x00000000
*/
uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len)
{
uint32_t i;
uint32_t u32CurrCrc32Value = u32Crc32Value;
for (i = 0UL; i < u32Len; i++) {
u32CurrCrc32Value = (u32CurrCrc32Value >> 8) ^ m_au32Crc32Table[(u32CurrCrc32Value & 0xFFUL) ^ pu8Data[i]];
}
return u32CurrCrc32Value;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
*****************************************************************************/

179
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c
View File

@@ -1,179 +0,0 @@
/**
*******************************************************************************
* @file stl_test_flash.c
* @brief This file provides firmware functions to manage the flash test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4
2023-01-15 CDT Fix bug: Reading CC Build CRC32 value is error in release project
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_conf.h"
#include "stl_utility.h"
#include "stl_sw_crc32.h"
#include "stl_test_flash.h"
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @defgroup STL_IEC60730_Flash STL IEC60730 Flash
* @brief IEC60730 flash test
* @{
*/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
#if defined (__CC_ARM) /* keil Compiler */
#define STL_CRC32_XOR_VALUE (0xFFFFFFFFUL)
#elif defined (__IAR_SYSTEMS_ICC__) /* IAR Compiler */
#define STL_CRC32_XOR_VALUE (0x00000000UL)
#endif
#define SW_CRC32_VALUE_XOR(x) ((x) ^ STL_CRC32_XOR_VALUE)
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/**
* @defgroup STL_IEC60730_Flash_Local_Variables STL IEC60730 Flash Local Variables
* @{
*/
STL_USED const uint32_t __checksum STL_SECTION(".checksum") = 0UL;
/**
* @}
*/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_Flash_Global_Functions STL IEC60730 Flash Global Functions
* @{
*/
/**
* @brief Flash test in startup.
* @param None
* @retval uint32_t:
* - STL_OK: Test pass.
* - STL_ERR: Flash CRC value error.
*/
uint32_t STL_FlashStartupTest(void)
{
uint32_t u32RomStart = STL_ROM_CRC32_START;
uint32_t u32RomEnd = STL_ROM_CRC32_END;
uint32_t u32RomSize = (u32RomEnd - u32RomStart);
uint8_t *pu8CrcData = (uint8_t *)u32RomStart;
uint32_t u32CalcCrc32Value;
volatile uint32_t u32CcBulidCrc32Addr;
volatile uint32_t u32CcBulidCrc32Value;
uint32_t u32Ret = STL_ERR;
u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM);
u32CcBulidCrc32Value = *(uint32_t *)(u32CcBulidCrc32Addr);
u32CalcCrc32Value = STL_CalculateCRC32Value(STL_CRC32_INIT_VALUE, pu8CrcData, u32RomSize);
u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value);
if (u32CcBulidCrc32Value == u32CalcCrc32Value) {
u32Ret = STL_OK;
}
return u32Ret;
}
/**
* @brief Flash test in runtime.
* @param None
* @retval uint32_t:
* - STL_OK: Test pass.
* - STL_ERR: Flash CRC value error.
*/
uint32_t STL_FlashRuntimeTest(void)
{
uint32_t u32Ret = STL_OK;
uint32_t u32RomStart = STL_ROM_CRC32_START;
uint32_t u32RomEnd = STL_ROM_CRC32_END;
uint32_t u32RomSize = (u32RomEnd - u32RomStart);
volatile uint32_t u32CcBulidCrc32Addr;
volatile uint32_t u32CcBulidCrc32Value;
const uint32_t u32CheckEndAddr = u32RomSize + 3UL - STL_ROM_CRC32_BLOCK_SIZE;
static uint32_t u32CalcLen;
static uint32_t u32CheckAddr = STL_ROM_CRC32_START;
static uint32_t u32CalcCrc32Value = STL_CRC32_INIT_VALUE;
if (u32CheckAddr < STL_ROM_CRC32_END) {
if (u32CheckAddr == STL_ROM_CRC32_START) {
u32CalcCrc32Value = STL_CRC32_INIT_VALUE; /* Update CRC32 init value */
}
if (u32CheckAddr < u32CheckEndAddr) {
u32CalcLen = STL_ROM_CRC32_BLOCK_SIZE;
} else {
u32CalcLen = u32RomEnd - u32CheckAddr;
}
u32CalcCrc32Value = STL_CalculateCRC32Value(u32CalcCrc32Value, (uint8_t *)u32CheckAddr, u32CalcLen);
u32CheckAddr += u32CalcLen; /* Update address */
} else {
u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM);
u32CcBulidCrc32Value = *(uint32_t *)(u32CcBulidCrc32Addr);
u32CheckAddr = STL_ROM_CRC32_START; /* Update address */
u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value);
if (u32CcBulidCrc32Value == u32CalcCrc32Value) {
STL_Printf("******** CRC32 verify ok in runtime ********\r\n");
} else {
STL_Printf("******** CRC32 verify error in runtime ********\r\n");
STL_Printf("* Calc_CRC32= 0x%x:CC Build_CRC32= 0x%x *\r\n", u32CalcCrc32Value, u32CcBulidCrc32Value);
u32Ret = STL_ERR;
}
}
return u32Ret;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
*****************************************************************************/

165
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c
View File

@@ -1,165 +0,0 @@
/**
*******************************************************************************
* @file stl_test_interrupt.c
* @brief This file provides firmware functions to manage the interrupt test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_conf.h"
#include "stl_test_interrupt.h"
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @defgroup STL_IEC60730_Interrupt_Runtime STL IEC60730 Interrupt Runtime
* @brief IEC60730 interrupt runtime test
* @{
*/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables
* @{
*/
static uint32_t m_u32TestParamTableSize;
static stc_stl_int_params_t *m_pstcTestParamTable;
/**
* @}
*/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_Interrupt_Global_Functions STL IEC60730 Interrupt Global Functions
* @{
*/
/**
* @brief Interrupt test table initialize in runtime.
* @param [in] pstcParamsTable Test case table
* @param [in] u32TableSize Test case size
* @retval uint32_t:
* - STL_OK: Initialize successfully.
* - STL_ERR: Initialize unsuccessfully.
*/
uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize)
{
uint32_t i;
uint32_t u32Ret = STL_ERR;
if ((pstcParamsTable != NULL) && (u32TableSize != 0UL)) {
for (i = 0UL; i < u32TableSize; i++) {
pstcParamsTable[i].u32PrivateParam = 0UL;
}
m_pstcTestParamTable = pstcParamsTable;
m_u32TestParamTableSize = u32TableSize;
u32Ret = STL_OK;
}
return u32Ret;
}
/**
* @brief Interrupt test in runtime.
* @param None
* @retval uint32_t:
* - STL_OK: Test pass.
* - STL_ERR: Test error.
*/
uint32_t STL_IntRuntimeTest(void)
{
uint32_t i;
uint32_t u32Ret = STL_OK;
stc_stl_int_params_t *pstcTestParam;
static uint32_t u32SystickCount;
if (++u32SystickCount == STL_SYSTICK_TICK_FREQ) {
for (i = 0UL; i < m_u32TestParamTableSize; i++) {
pstcTestParam = &m_pstcTestParamTable[i];
if ((pstcTestParam->u32PrivateParam < pstcTestParam->u32FreqLowerVal) || \
(pstcTestParam->u32PrivateParam > pstcTestParam->u32FreqUpperVal)) {
u32Ret = STL_ERR;
}
pstcTestParam->u32PrivateParam = 0UL;
}
u32SystickCount = 0UL;
}
return u32Ret;
}
/**
* @brief Update interrupt count in runtime.
* @param [in] u8ParamIndex Params index
* @retval None
*/
void STL_IntUpdateCount(uint8_t u8ParamIndex)
{
stc_stl_int_params_t *pstcTestParam;
if (u8ParamIndex < m_u32TestParamTableSize) {
pstcTestParam = &m_pstcTestParamTable[u8ParamIndex];
pstcTestParam->u32PrivateParam++;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

269
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c
View File

@@ -1,269 +0,0 @@
/**
*******************************************************************************
* @file stl_test_ram_runtime.c
* @brief This file provides firmware functions to manage the RAM test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_conf.h"
#include "stl_test_ram.h"
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @defgroup STL_IEC60730_RAM_Runtime STL IEC60730 RAM Runtime
* @brief IEC60730 RAM runtime test
* @{
*/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables
* @{
*/
STL_USED uint32_t m_au32MarchRAM[STL_MARCH_RAM_WORDS] STL_SECTION(".march_ram");
STL_USED uint32_t m_au32MarchRAMBuf[STL_MARCH_RAM_BUF_WORDS] STL_SECTION(".march_ram_buf");
STL_USED uint32_t *m_pu32MarchRAM STL_SECTION(".march_ram_pointer");
STL_USED uint32_t m_au32StackBoundary[STL_STACK_BOUNDARY_WORDS] STL_SECTION(".stack_boundary");
/**
* @}
*/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_RAM_Global_Functions STL IEC60730 RAM Global Functions
* @{
*/
/**
* @brief Stack test initialize in runtime.
* @param None
* @retval uint32_t:
* - STL_OK: Initialization pass.
*/
uint32_t STL_StackRuntimeInit(void)
{
m_au32StackBoundary[0] = 0x5A5A5A5AUL;
m_au32StackBoundary[1] = 0xA5A5A5A5UL;
m_au32StackBoundary[2] = 0xAAAAAAAAUL;
m_au32StackBoundary[3] = 0x55555555UL;
return STL_OK;
}
/**
* @brief Stack test in runtime.
* @param None
* @retval uint32_t:
* - STL_OK: Test pass.
* - STL_ERR: Stack boundary value error.
*/
uint32_t STL_StackRuntimeTest(void)
{
if ((m_au32StackBoundary[0] != 0x5A5A5A5AUL) || \
(m_au32StackBoundary[1] != 0xA5A5A5A5UL) || \
(m_au32StackBoundary[2] != 0xAAAAAAAAUL) || \
(m_au32StackBoundary[3] != 0x55555555UL)) {
return STL_ERR;
}
return STL_OK;
}
/**
* @brief RAM test initialize in runtime.
* @param None
* @retval uint32_t:
* - STL_OK: Initialization pass.
*/
uint32_t STL_RamRuntimeInit(void)
{
m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START;
return STL_OK;
}
/**
* @brief RAM test in runtime.
* @param None
* @retval uint32_t:
* - STL_OK: Test pass.
* - STL_ERR: Test fail.
*/
uint32_t STL_RamRuntimeTest(void)
{
uint32_t i; /* Index for RAM physical addressing */
uint32_t u32Ret = STL_OK;
if (m_pu32MarchRAM >= (uint32_t *)STL_MARCH_RAM_END) {
/*------------- March C- to the RAM Buffer itself --------------- */
m_pu32MarchRAM = &m_au32MarchRAMBuf[0];
/*---------------------------- STEP 1 --------------------------------- */
/* Write background with addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
}
/*---------------------------- STEP 2 --------------------------------- */
/* Verify background and write inverted background addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND;
}
/*---------------------------- STEP 3 --------------------------------- */
/* Verify inverted background and write background addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
}
/*---------------------------- STEP 4 --------------------------------- */
/* Verify background and write inverted background addresses decreasing */
for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) {
if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND;
}
/*---------------------------- STEP 5 --------------------------------- */
/* Verify inverted background and write background addresses decreasing */
for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) {
if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND;
}
/*---------------------------- STEP 6 --------------------------------- */
/* Verify background with addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
u32Ret = STL_ERR;
}
}
/* Prepare next Tranparent RAM test from the beginning of Class A area */
m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START;
} else {
/*---------------------------- STEP 1 --------------------------------- */
/* Save the content of the 6 words to be tested and start MarchC -
Write background with addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
m_au32MarchRAMBuf[i] = m_pu32MarchRAM[i];
m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
}
/*---------------------------- STEP 2 --------------------------------- */
/* Verify background and write inverted background addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND;
}
/*---------------------------- STEP 3 --------------------------------- */
/* Verify inverted background and write background addresses increasing */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
}
/*---------------------------- STEP 4 --------------------------------- */
/* Verify background and write inverted background addresses decreasing */
for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) {
if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND;
}
/*---------------------------- STEP 5 --------------------------------- */
/* Verify inverted background and write background addresses decreasing */
for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) {
if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND;
}
/*---------------------------- STEP 6 --------------------------------- */
/* Verify background with addresses increasing */
/* and restore the content of the 6 tested words */
for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
u32Ret = STL_ERR;
}
m_pu32MarchRAM[i] = m_au32MarchRAMBuf[i];
}
/* Prepare next Row Tranparent RAM test */
m_pu32MarchRAM = &m_pu32MarchRAM[STL_MARCH_RAM_BUF_WORDS];
}
return u32Ret;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
*****************************************************************************/

145
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c
View File

@@ -1,145 +0,0 @@
/**
*******************************************************************************
* @file stl_test_runtime.c
* @brief This file provides firmware functions to manage the runtime self-test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_test_runtime.h"
#include "stl_conf.h"
#include "stl_utility.h"
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @defgroup STL_IEC60730_Runtime STL IEC60730 Runtime
* @brief IEC60730 runtime test
* @{
*/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_Runtime_Global_Macros STL IEC60730 Runtime Global Macros
* @{
*/
/**
* @brief Self-test initialization in runtime.
* @param [in] pstcCaseTable Test case table
* @param [in] u32TableSize Test case size
* @retval None
*/
void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize)
{
uint32_t i;
#if (STL_PRINT_ENABLE == STL_ON)
static en_flag_status_t enPrintInitActived = RESET;
#endif
#if (STL_PRINT_ENABLE == STL_ON)
/* startup debug print */
if (enPrintInitActived == RESET) {
(void)STL_PrintfInit();
enPrintInitActived = SET;
}
#endif
STL_Printf("******** Self-test runtime initialize ********\r\n");
if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
for (i = 0UL; i < u32TableSize; i++) {
if (pstcCaseTable[i].pfnInit != NULL) {
if (pstcCaseTable[i].pfnInit() != STL_OK) {
STL_Printf("******** Init fail in runtime: %-20s ********\r\n", pstcCaseTable[i].pcCaseName);
}
}
}
}
}
/**
* @brief Self-test on runtime.
* @param [in] pstcCaseTable Test case table
* @param [in] u32TableSize Test case size
* @retval None
*/
void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize)
{
uint32_t i;
if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
for (i = 0UL; i < u32TableSize; i++) {
if (pstcCaseTable[i].pfnTest != NULL) {
if (pstcCaseTable[i].pfnTest() != STL_OK) {
STL_Printf("******** Test fail in runtime: %-20s ********\r\n", pstcCaseTable[i].pcCaseName);
if (pstcCaseTable[i].pfnFailHandler != NULL) {
pstcCaseTable[i].pfnFailHandler();
}
}
}
if (pstcCaseTable[i].pfnFeedDog != NULL) {
pstcCaseTable[i].pfnFeedDog();
}
}
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
*****************************************************************************/

236
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c
View File

@@ -1,236 +0,0 @@
/**
*******************************************************************************
* @file stl_utility.c
* @brief This file provides utility functions for STL.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2023-01-15 CDT Modify USART_SR_TXE to USART_SR_TC in STL_ConsoleOutputChar()
2023-05-31 CDT Modify register USART DR to USART TDR
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_utility.h"
#include "hc32_ll_fcg.h"
#include "hc32_ll_gpio.h"
#include "hc32_ll_usart.h"
#include "hc32_ll_utility.h"
/**
* @addtogroup IEC60730_STL
* @{
*/
/**
* @defgroup IEC60730_STL_Utility IEC60730 STL Utility
* @{
*/
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup STL_IEC60730_Utility_Global_Functions STL IEC60730 Utility Global Functions
* @{
*/
/**
* @brief Delay function, delay us approximately
* @param [in] u32Count us
* @retval None
*/
void STL_DelayUS(uint32_t u32Count)
{
DDL_DelayUS(u32Count);
}
/**
* @brief Delay function, delay ms approximately
* @param [in] u32Count ms
* @retval None
*/
void STL_DelayMS(uint32_t u32Count)
{
DDL_DelayMS(u32Count);
}
/**
* @brief STL test safety failure handle
* @param None
* @retval None
*/
void STL_SafetyFailure(void)
{
#if (STL_RESET_AT_FAILURE == STL_ON)
NVIC_SystemReset(); /* Generate system reset */
#endif
}
#if (STL_PRINT_ENABLE == STL_ON)
/**
* @brief Transmit character.
* @param [in] cData The character for transmitting
* @retval uint32_t:
* - STL_OK: Transmit successfully.
* - STL_ERR: Transmit timeout.
*/
__WEAKDEF uint32_t STL_ConsoleOutputChar(char cData)
{
uint32_t u32Ret = STL_ERR;
uint32_t u32TxEmpty = 0UL;
__IO uint32_t u32TmpCount = 0UL;
uint32_t u32Timeout = 10000UL;
/* Wait TX data register empty */
while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) {
u32TxEmpty = READ_REG32_BIT(STL_PRINTF_DEVICE->SR, USART_SR_TC);
u32TmpCount++;
}
if (0UL != u32TxEmpty) {
WRITE_REG16(STL_PRINTF_DEVICE->TDR, (uint16_t)cData);
u32Ret = STL_OK;
}
return u32Ret;
}
#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
(defined (__ICCARM__)) || (defined (__CC_ARM))
/**
* @brief Re-target fputc function.
* @param [in] ch
* @param [in] f
* @retval int32_t
*/
int32_t fputc(int32_t ch, FILE *f)
{
(void)f; /* Prevent unused argument compilation warning */
return (STL_OK == STL_ConsoleOutputChar((char)ch)) ? ch : -1;
}
#elif defined (__GNUC__) && !defined (__CC_ARM)
/**
* @brief Re-target _write function.
* @param [in] fd
* @param [in] data
* @param [in] size
* @retval int32_t
*/
int32_t _write(int fd, char data[], int32_t size)
{
int32_t i = -1;
if (NULL != data) {
(void)fd; /* Prevent unused argument compilation warning */
for (i = 0; i < size; i++) {
if (STL_OK != STL_ConsoleOutputChar(data[i])) {
break;
}
}
}
return i ? i : -1;
}
#endif
/**
* @brief Initialize printf function
* @param None
* @retval None
*/
uint32_t STL_PrintfInit(void)
{
uint32_t u32Div;
float32_t f32Error;
uint32_t u32Ret = STL_ERR;
stc_usart_uart_init_t stcUartInit;
/* Set TX port function */
GPIO_SetFunc(STL_PRINTF_PORT, STL_PRINTF_PIN, STL_PRINTF_PORT_FUNC);
/* Enable clock */
STL_PRINTF_DEVICE_FCG_ENALBE();
/***************************************************************************
* Configure UART
***************************************************************************
* Baud rate: STL_PRINTF_BAUDRATE
* Bit direction: LSB
* Data bits: 8
* Stop bits: 1
* Parity: None
* Sampling bits: 8
**************************************************************************/
/* Configure UART */
(void)USART_UART_StructInit(&stcUartInit);
stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT;
(void)USART_UART_Init(STL_PRINTF_DEVICE, &stcUartInit, NULL);
for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) {
USART_SetClockDiv(STL_PRINTF_DEVICE, u32Div);
if ((LL_OK == USART_SetBaudrate(STL_PRINTF_DEVICE, STL_PRINTF_BAUDRATE, &f32Error)) && \
((-STL_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= STL_PRINTF_BAUDRATE_ERR_MAX))) {
USART_FuncCmd(STL_PRINTF_DEVICE, USART_TX, ENABLE);
u32Ret = STL_OK;
break;
}
}
return u32Ret;
}
#endif /* STL_PRINT_ENABLE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

107
bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h
View File

@@ -1,107 +0,0 @@
/**
*******************************************************************************
* @file stl_utility.h
* @brief This file contains all the functions prototypes of utility.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_UTILITY_H__
#define __STL_UTILITY_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#include "stl_conf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup IEC60730_STL
* @{
*/
/**
* @addtogroup IEC60730_STL_Utility
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @addtogroup STL_UTILITY_Global_Functions
* @{
*/
#if (STL_PRINT_ENABLE == STL_ON)
#include <stdio.h>
uint32_t STL_ConsoleOutputChar(char cData);
#define STL_Printf (void)printf
#else
#define STL_Printf(...)
#endif
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addgroup STL_Utility_Global_Functions
* @{
*/
void STL_DelayUS(uint32_t u32Count);
void STL_DelayMS(uint32_t u32Count);
void STL_SafetyFailure(void);
uint32_t STL_PrintfInit(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_UTILITY_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

58
bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf
View File

@@ -1,58 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFCFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFFD000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x2000FFFF;
define symbol __ICFEDIT_region_IRAM3_start__ = 0x20010000;
define symbol __ICFEDIT_region_IRAM3_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM4_start__ = 0x20020000;
define symbol __ICFEDIT_region_IRAM4_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM5_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM5_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x100;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x100;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
| mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]
| mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__]
| mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

50
bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf
View File

@@ -1,50 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0xC00;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

50
bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf
View File

@@ -1,50 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0xC00;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

145
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h
View File

@@ -1,145 +0,0 @@
/**
*******************************************************************************
* @file stl_common.h
* @brief This file contains STL common definitions: enumeration, macros and
* structures definitions.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_COMMON_H__
#define __STL_COMMON_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ll_def.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup IEC60730_STL
* @{
*/
/**
* @addtogroup IEC60730_STL_Common
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup STL_Common_Global_Macros STL Common Global Macros
* @{
*/
/**
* @defgroup STL_Generic_Error_Codes STL Generic Error Codes
* @{
*/
#define STL_OK (0UL) /*!< No error occurs */
#define STL_ERR (1UL) /*!< Error occurs */
/**
* @}
*/
/**
* @defgroup STL_Module_Switch STL Module Switch
* @{
*/
#define STL_ON (1U)
#define STL_OFF (0U)
/**
* @}
*/
/**
* @defgroup Compiler_Macros Compiler Macros
* @{
*/
#ifdef __CC_ARM /*!< ARM Compiler */
/* CPU will start executing at the program entry label __main when the CPU is reset */
extern void __main(void);
/* CC */
#define STL_SECTION(x) __attribute__((section(x)))
#define STL_UNUSED __attribute__((unused))
#define STL_USED __attribute__((used))
#define STL_ALIGN(n) __attribute__((aligned(n)))
#define STL_WEAK __WEAKDEF
#define STL_INLINE static __inline
#define CallApplicationStartUp( ) __main()
#elif defined (__ICCARM__) /*!< IAR Compiler */
/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */
extern void __iar_program_start(void);
/* CC */
#define STL_SECTION(x) @ x
#define STL_UNUSED
#define STL_USED __root
#define STL_PRAGMA(x) _Pragma(#x)
#define STL_ALIGN(n) STL_PRAGMA(data_alignment=n)
#define STL_WEAK __WEAKDEF
#define STL_INLINE static inline
#define CallApplicationStartUp( ) __iar_program_start()
#else
#error Unsupported tool chain
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_COMMON_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

106
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h
View File

@@ -1,106 +0,0 @@
/**
*******************************************************************************
* @file stl_conf.h
* @brief This file contains STL resource configure.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
2022-06-30 CDT Optimize macros definitions
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_CONF_H__
#define __STL_CONF_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_bsp_conf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup IEC60730_STL
* @{
*/
/**
* @addtogroup IEC60730_STL_Configure
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters
* @{
*/
#define STL_ROM_CRC32_START (STL_ROM_START)
#define STL_ROM_CRC32_END ((uint32_t)(&__checksum))
#define STL_ROM_CRC32_BLOCK_SIZE (128UL)
#define STL_ROM_CRC32_CC_CHECKSUM (__checksum)
/**
* @}
*/
/**
* @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters
* @{
*/
#define STL_MARCH_RAM_SIZE (32UL)
#define STL_MARCH_RAM_WORDS (STL_MARCH_RAM_SIZE >> 2)
#define STL_MARCH_RAM_BUF_SIZE (16UL)
#define STL_MARCH_RAM_BUF_WORDS (STL_MARCH_RAM_BUF_SIZE >> 2)
#define STL_MARCH_RAM_BCKGRND (0x00000000UL)
#define STL_MARCH_RAM_INVBCKGRND (0xFFFFFFFFUL)
#define STL_STACK_BOUNDARY_WORDS (4UL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_CONF_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

93
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h
View File

@@ -1,93 +0,0 @@
/**
*******************************************************************************
* @file stl_test_flash.h
* @brief This file contains all the functions prototypes of the flash test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_SW_CRC32_H__
#define __STL_SW_CRC32_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_CRC32
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros
* @{
*/
#define STL_CRC32_INIT_VALUE (0xFFFFFFFFUL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_CRC32_Global_Functions
* @{
*/
uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_SW_CRC32_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

85
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h
View File

@@ -1,85 +0,0 @@
/**
*******************************************************************************
* @file stl_test_cpu.h
* @brief This file contains all the functions prototypes of the CPU test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_CPU_H__
#define __STL_TEST_CPU_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_CPU
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_CPU_Global_Functions
* @{
*/
uint32_t STL_CpuTestStartup(void);
uint32_t STL_CpuTestRuntime(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_CPU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

85
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h
View File

@@ -1,85 +0,0 @@
/**
*******************************************************************************
* @file stl_test_flash.h
* @brief This file contains all the functions prototypes of the flash test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_FLASH_H__
#define __STL_TEST_FLASH_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_Flash
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_Flash_Global_Functions
* @{
*/
uint32_t STL_FlashStartupTest(void);
uint32_t STL_FlashRuntimeTest(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_FLASH_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

99
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h
View File

@@ -1,99 +0,0 @@
/**
*******************************************************************************
* @file stl_test_interrupt.h
* @brief This file contains all the functions prototypes of the interrupt test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_INTERRUPT_H__
#define __STL_TEST_INTERRUPT_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_Interrupt
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/**
* @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type
* @{
*/
typedef struct stc_stl_int_params {
uint32_t u32FreqInitVal;
uint32_t u32FreqLowerVal;
uint32_t u32FreqUpperVal;
uint32_t u32PrivateParam;
} stc_stl_int_params_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_Interrupt_Global_Functions
* @{
*/
uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize);
uint32_t STL_IntRuntimeTest(void);
void STL_IntUpdateCount(uint8_t u8ParamIndex);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_INTERRUPT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

88
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h
View File

@@ -1,88 +0,0 @@
/**
*******************************************************************************
* @file stl_test_ram.h
* @brief This file contains all the functions prototypes of the RAM test.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __STL_TEST_RAM_H__
#define __STL_TEST_RAM_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include "stl_common.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @addtogroup STL_IEC60730
* @{
*/
/**
* @addtogroup STL_IEC60730_RAM
* @{
*/
/*******************************************************************************
* Global type definitions ('typedef')
*******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup STL_IEC60730_RAM_Global_Functions
* @{
*/
uint32_t STL_StackRuntimeInit(void);
uint32_t STL_StackRuntimeTest(void);
uint32_t STL_RamRuntimeInit(void);
uint32_t STL_RamRuntimeTest(void);
uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STL_TEST_RAM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

372
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s
View File

@@ -1,372 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Version V1.0 */
;/* Date 2022-09-14 */
;/****************************************************************************/
SECTION constdata:CONST(2)
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
data0x80000000 DCD 0x80000000
data0xAAAAAAA8 DCD 0xAAAAAAA8
data0x55555554 DCD 0x55555554
data0x00000000 DCD 0x00000000
data0x00000001 DCD 0x00000001
data0x50000000 DCD 0x50000000
data0xA0000000 DCD 0xA0000000
; Exported function
EXPORT STL_CpuTestStartup
;*******************************************************************************
; Function Name : STL_CpuTestStartup
; Description : Test CPU at start-up
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
THUMB
SECTION .text:CODE(2)
STL_CpuTestStartup:
PUSH {R4-R7} ; Save registers
_test_cpu_reg0_reg8
MOVS R0, #0x00
UXTB R0, R0
ADDS R0, #0 ; Set Z(ero) Flag
BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
SUBS R0, #1 ; Set N(egative) Flag
BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
ADDS R0, #2 ; Set C(arry) Flag and do not set Z
BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
LDR R0, =data0x80000000 ; Prepares Overflow test
LDR R0, [R0]
ADDS R0, R0, R0 ; Set V(overflow) Flag
BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_reg0_reg13_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_reg0_reg13_fail
CMP R2, #0x02
BNE _test_cpu_reg0_reg13_fail
CMP R3, #0x03
BNE _test_cpu_reg0_reg13_fail
CMP R4, #0x04
BNE _test_cpu_reg0_reg13_fail
CMP R5, #0x05
BNE _test_cpu_reg0_reg13_fail
CMP R6, #0x06
BNE _test_cpu_reg0_reg13_fail
CMP R7, #0x07
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
; Process Stack pointer (banked Register R13)
MRS R0, PSP ; Save process stack value
LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
MSR PSP, R0 ; Restore process stack value
; Stack pointer (Register R13)
MRS R0, MSP ; Save stack pointer value
LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR MSP, R1 ; load SP value
MRS R2, MSP ; Get back SP value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554
LDR R1, [R1] ; load SP value
MSR MSP, R1 ; Get back SP value
MRS R2, MSP ; Verify value
CMP R2, R1
BNE _test_cpu_reg0_reg13_fail
MSR MSP, R0 ; Restore stack pointer value
_test_cpu_r14_sfr
; Link register R14
MOV R1, LR
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
MOV LR, R1
; APSR
MRS R0, APSR
LDR R1, =data0x50000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0xA0000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR APSR,R0
; PRIMASK register
MRS R0, PRIMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR PRIMASK, R0
B _test_cpu_pass
_test_cpu_r14_sfr_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_pass
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _test_exit
_test_exit
POP {R4-R7} ; Restore registers
BX LR
END

420
bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s
View File

@@ -1,420 +0,0 @@
;/*****************************************************************************
; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Test for IAR */
;/* Date Author Notes */
;/* 2022-09-14 CDT First version */
;/* 2022-12-20 CDT Load data to R0 before USAT */
;/* 2023-05-31 CDT Typo: Veriry -> Verify */
;/****************************************************************************/
SECTION constdata:CONST(2)
data0xAAAAAAAA DCD 0xAAAAAAAA
data0x55555555 DCD 0x55555555
data0x80000000 DCD 0x80000000
data0xAAAAAAA8 DCD 0xAAAAAAA8
data0x55555554 DCD 0x55555554
data0x00000000 DCD 0x00000000
data0x00000001 DCD 0x00000001
data0x50000000 DCD 0x50000000
data0xA8000000 DCD 0xA8000000
data0x00000050 DCD 0x00000050
data0x000000A0 DCD 0x000000A0
data0xFFFFFFFF DCD 0xFFFFFFFF
; Exported function
EXPORT STL_CpuTestStartup
;*******************************************************************************
; Function Name : STL_CpuTestStartup
; Description : Test CPU at start-up
; Input : None.
; Output : Perform routine when detect failure at set of self test cases
; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
; WARNING : all registers destroyed when exiting this function (including
; preserved registers R4 to R11) and excluding stack point R13)
;*******************************************************************************/
THUMB
SECTION .text:CODE(2)
STL_CpuTestStartup:
PUSH {R4-R7} ; Save registers
_test_cpu_reg0_reg8
MOVS R0, #0x00
UXTB R0, R0
ADDS R0, #0 ; Set Z(ero) Flag
BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
SUBS R0, #1 ; Set N(egative) Flag
BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
ADDS R0, #2 ; Set C(arry) Flag and do not set Z
BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
LDR R0, =data0x80000000 ; Prepares Overflow test
LDR R0, [R0]
ADDS R0, R0, R0 ; Set V(overflow) Flag
BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
MOV R0, #0
MSR APSR, R0
LDR R0, =data0xFFFFFFFF ; Prepares Saturation test
LDR R0, [R0]
USAT R1, #10, R0 ; Set Q(saturation) flag
MRS R0, APSR ; Get APSR status register
CMP R0, #0x08000000 ; Verify Q=1
BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set
; Register R1
LDR R0, =data0xAAAAAAAA
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R1, [R0]
LDR R0, [R0]
CMP R0, R1
BNE _test_cpu_reg0_reg13_fail
MOVS R1, #0x1
; Register R2
LDR R0, =data0xAAAAAAAA
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R2, [R0]
LDR R0, [R0]
CMP R0, R2
BNE _test_cpu_reg0_reg13_fail
MOVS R2, #0x2
; Register R3
LDR R0, =data0xAAAAAAAA
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R3, [R0]
LDR R0, [R0]
CMP R0, R3
BNE _test_cpu_reg0_reg13_fail
MOVS R3, #0x3
; Register R4
LDR R0, =data0xAAAAAAAA
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R4, [R0]
LDR R0, [R0]
CMP R0, R4
BNE _test_cpu_reg0_reg13_fail
MOVS R4, #0x4
; Register R5
LDR R0, =data0xAAAAAAAA
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R5, [R0]
LDR R0, [R0]
CMP R0, R5
BNE _test_cpu_reg0_reg13_fail
MOVS R5, #0x5
; Register R6
LDR R0, =data0xAAAAAAAA
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R6, [R0]
LDR R0, [R0]
CMP R0, R6
BNE _test_cpu_reg0_reg13_fail
MOVS R6, #0x6
; Register R7
LDR R0, =data0xAAAAAAAA
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R7, [R0]
LDR R0, [R0]
CMP R0, R7
BNE _test_cpu_reg0_reg13_fail
MOVS R7, #0x7
; Register R8
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R8, R0
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
MOV R8, R0
BAL _test_cpu_continue
_test_cpu_reg0_reg13_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_continue
; Register R9
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R9, R0
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
MOV R9, R0
; Register R10
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R10, R0
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
MOV R10, R0
; Register R11
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R11, R0
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
MOV R11, R0
; Register R12
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R12, R0
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
MOV R12, R0
LDR R0, =_test_cpu_continue
; pattern verification (R0 is not tested)
CMP R1, #0x01
BNE _test_cpu_reg0_reg13_fail
CMP R2, #0x02
BNE _test_cpu_reg0_reg13_fail
CMP R3, #0x03
BNE _test_cpu_reg0_reg13_fail
CMP R4, #0x04
BNE _test_cpu_reg0_reg13_fail
CMP R5, #0x05
BNE _test_cpu_reg0_reg13_fail
CMP R6, #0x06
BNE _test_cpu_reg0_reg13_fail
CMP R7, #0x07
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x08
CMP R0, R8
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x09
CMP R0, R9
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0A
CMP R0, R10
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0B
CMP R0, R11
BNE _test_cpu_reg0_reg13_fail
MOVS R0, #0x0C
CMP R0, R12
BNE _test_cpu_reg0_reg13_fail
; Process Stack pointer (banked Register R13)
MRS R0, PSP ; Save process stack value
LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR PSP, R1 ; load process stack value
MRS R2, PSP ; Get back process stack value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
MSR PSP, R0 ; Restore process stack value
; Stack pointer (Register R13)
MRS R0, MSP ; Save stack pointer value
LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
LDR R1, [R1]
MSR MSP, R1 ; load SP value
MRS R2, MSP ; Get back SP value
CMP R2, R1 ; Verify value
BNE _test_cpu_reg0_reg13_fail
LDR R1, =data0x55555554
LDR R1, [R1] ; load SP value
MSR MSP, R1 ; Get back SP value
MRS R2, MSP ; Verify value
CMP R2, R1
BNE _test_cpu_reg0_reg13_fail
MSR MSP, R0 ; Restore stack pointer value
_test_cpu_r14_sfr
; Link register R14
MOV R1, LR
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0x55555555
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
LDR R0, =data0xAAAAAAAA
LDR R0, [R0]
MOV R14, R0
CMP R0, R14
BNE _test_cpu_r14_sfr_fail
MOV LR, R1
; APSR
MRS R0, APSR
LDR R1, =data0x50000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0xA8000000
LDR R1,[R1]
MSR APSR,R1
MRS R2, APSR
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR APSR,R0
; PRIMASK register
MRS R0, PRIMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR PRIMASK, R1
MRS R2, PRIMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR PRIMASK, R0
; FAULTMASK register
MRS R0, FAULTMASK
LDR R1, =data0x00000000
LDR R1, [R1]
MSR FAULTMASK, R1
MRS R2, FAULTMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000001
LDR R1, [R1]
MSR FAULTMASK, R1
MRS R2, FAULTMASK
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR FAULTMASK, R0
; BASEPRI register
MRS R0, BASEPRI
LDR R1, =data0x000000A0
LDR R1, [R1]
MSR BASEPRI, R1
MRS R2, BASEPRI
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
LDR R1, =data0x00000050
LDR R1, [R1]
MSR BASEPRI, R1
MRS R2, BASEPRI
CMP R1, R2
BNE _test_cpu_r14_sfr_fail
MSR BASEPRI, R0
B _test_cpu_pass
_test_cpu_r14_sfr_fail
; test fail, R0 will hold value 1
MOVS R0, #0x1 ; STL_ERR
B _test_exit
_test_cpu_pass
; test pass, R0 will hold value 0
MOVS R0, #0x0 ; STL_OK
B _test_exit
_test_exit
POP {R4-R7} ; Restore registers
BX LR
END

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