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[libcpu] Add unified RISC-V libcpu porting.

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This commit is contained in:
Bernard Xiong
2018-12-08 10:41:38 +08:00
parent 94e6c349a6
commit 2a7d814f77
8 changed files with 562 additions and 9 deletions
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21
libcpu/SConscript
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@@ -2,30 +2,37 @@ Import('RTT_ROOT')
Import('rtconfig')
from building import *
arch = rtconfig.ARCH
comm = rtconfig.ARCH + '/common'
path = rtconfig.ARCH + '/' + rtconfig.CPU
src = []
ASFLAGS = ''
# The set of source files associated with this SConscript file.
if rtconfig.PLATFORM == 'armcc':
src = Glob(path + '/*.c') + Glob(path + '/*_rvds.S') + Glob(comm + '/*.c')
src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S')
src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S')
if rtconfig.PLATFORM == 'gcc':
src = Glob(path + '/*.c') + Glob(path + '/*_gcc.S') + Glob(comm + '/*.c') + Glob(path + '/*_init.S')
src += Glob(path + '/*_init.S')
src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S')
src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S')
if rtconfig.PLATFORM == 'iar':
src = Glob(path + '/*.c') + Glob(path + '/*_iar.S') + Glob(comm + '/*.c')
src += Glob(path + '/*.c') + Glob(path + '/*_iar.S')
src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S')
if rtconfig.PLATFORM == 'cl':
src = Glob(path + '/*.c')
src = Glob(path + '/*.c')
if rtconfig.PLATFORM == 'mingw':
src = Glob(path + '/*.c')
src = Glob(path + '/*.c')
if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926':
ASFLAGS = ' --cpreproc'
CPPPATH = [RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/common']
CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common']
group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
Return('group')