diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index e2b6d159d8..056ca614a2 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -37,6 +37,8 @@ jobs: - {RTT_BSP: "acm32/acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "apm32/apm32f407ig-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "apm32/apm32f072vb-miniboard", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"} # - {RTT_BSP: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm"} diff --git a/bsp/apm32/apm32f072vb-miniboard/.config b/bsp/apm32/apm32f072vb-miniboard/.config new file mode 100644 index 0000000000..d187c9346e --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/.config @@ -0,0 +1,985 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_APM32=y +CONFIG_SOC_SERIES_APM32F0=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_APM32F072VB=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_TMR is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_WDT is not set + +# +# Board extended module Drivers +# diff --git a/bsp/apm32/apm32f072vb-miniboard/.gitignore b/bsp/apm32/apm32f072vb-miniboard/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/apm32/apm32f072vb-miniboard/Kconfig b/bsp/apm32/apm32f072vb-miniboard/Kconfig new file mode 100644 index 0000000000..7a400db91f --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/apm32/apm32f072vb-miniboard/README.md b/bsp/apm32/apm32f072vb-miniboard/README.md new file mode 100644 index 0000000000..05c9bbfd5a --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/README.md @@ -0,0 +1,116 @@ +# APM32F072VB MINI BOARD BSP 说明 + +## 简介 + +本文档为 APM32F072VB MINI 开发板（MINI BOARD）的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +APM32F072VB MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示： + +image-20221227141551541 + +- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192) + + +该开发板常用 **板载资源** 如下： + +- MCU：APM32F072VBT6，主频 48MHz，128KB FLASH ，16KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - LED：2个，（黄色，PE5/PE6） + - 按键：2个，K1（PA1），K2（PA0） +- 常用接口：RS232转串口、USB SLAVE +- 调试接口：标准 JTAG/SWD + + + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------------------------------------ | +| RS232转串口 | 支持 | 使用 UART1/ UART2(通过跳线选择) | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PF10 ---> PIN: 0, 1...89 | +| UART | 支持 | UART1/2 | +| ADC | 支持 | ADC1 | +| DAC | 支持 | DAC1 | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| TMR | 支持 | TMR1/2/3/6/7/14/15/16/17 | +| PWM | 支持 | TMR3 ->CH1/2/3/4 | +| I2C | 支持 | 软件I2C | +| SPI | 支持 | SPI1/2 | +| WDT | 支持 | IWDT | + +## 使用说明 + +本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + + +### 快速上手 + +本 BSP 为开发者提供MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 +- 方式一：MDK + + 双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +- 方式二：J-Flash下载 + + 通过ENV工具的scons指令或MDK编译出bin文件后，再使用J-Flash工具将bin文件下载至开发板即可，大致步骤如下： + +##### 1、建立J-Flash工程 + +![board](figures/JFlash_Leader_01.png) + +**注意**：步骤4选择芯片型号时，要根据自己的开发板所用的芯片型号进行选择。比如本开发板，则选择对应的 **APM32F072VBT6** 。 + +##### 2、连接开发板 + +![board](figures/JFlash_Leader_02.png) +##### 3、将bin文件拖至工程，起始地址设为0x8000000 +![board](figures/JFlash_Leader_03.png) +##### 4、点击下载 +![board](figures/JFlash_Leader_04.png) + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Aug 20 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +## 注意事项 + +- 可在极海官方网站进行所需资料下载，如pack安装包和MINI开发板原理图等（www.geehy.com）; + +## 联系人信息 + +-[abbbcc ](https://gitee.com/abbbcc) + +-[stevetong459 ](https://github.com/stevetong459) + +-[luobeihai](https://github.com/luobeihai) \ No newline at end of file diff --git a/bsp/apm32/apm32f072vb-miniboard/SConscript b/bsp/apm32/apm32f072vb-miniboard/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/apm32/apm32f072vb-miniboard/SConstruct b/bsp/apm32/apm32f072vb-miniboard/SConstruct new file mode 100644 index 0000000000..5660242653 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +apm32_library = 'APM32F0xx_Library' +rtconfig.BSP_LIBRARY_TYPE = apm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/apm32/apm32f072vb-miniboard/applications/SConscript b/bsp/apm32/apm32f072vb-miniboard/applications/SConscript new file mode 100644 index 0000000000..9bb9abae89 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/apm32/apm32f072vb-miniboard/applications/main.c b/bsp/apm32/apm32f072vb-miniboard/applications/main.c new file mode 100644 index 0000000000..de1309f793 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 zylx first version + */ + +#include +#include +#include + +/* defined the LED2 pin: PE6 */ +#define LED2_PIN GET_PIN(E, 6) + +int main(void) +{ + int count = 1; + /* set LED2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/apm32/apm32f072vb-miniboard/board/Kconfig b/bsp/apm32/apm32f072vb-miniboard/board/Kconfig new file mode 100644 index 0000000000..42cbfabb9d --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/Kconfig @@ -0,0 +1,213 @@ +menu "Hardware Drivers Config" + +config SOC_APM32F072VB + bool + select SOC_SERIES_APM32F0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + config BSP_USING_UART2 + bool "Enable UART2" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "Enable DAC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1 BUS" + if BSP_USING_I2C1 + comment "Notice: PB10 --> 26; PB11 --> 27" + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 63 + default 26 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 63 + default 27 + endif + config BSP_USING_I2C2 + bool "Enable I2C2 BUS" + if BSP_USING_I2C2 + comment "Notice: PA0 --> 0; PA1 --> 1" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 0 63 + default 22 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 0 63 + default 23 + endif + config BSP_USING_I2C3 + bool "Enable I2C3 BUS" + if BSP_USING_I2C3 + comment "Notice: PB0 --> 16; PB1 --> 17" + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 0 63 + default 8 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 0 63 + default 41 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + endif + + menuconfig BSP_USING_TMR + bool "Enable Timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TMR + config BSP_USING_TMR1 + bool "Enable TMR1" + default n + + config BSP_USING_TMR2 + bool "Enable TMR2" + default n + + config BSP_USING_TMR3 + bool "Enable TMR3" + default n + + config BSP_USING_TMR6 + bool "Enable TMR6" + default n + + config BSP_USING_TMR7 + bool "Enable TMR7" + default n + + config BSP_USING_TMR14 + bool "Enable TMR14" + default n + + config BSP_USING_TMR15 + bool "Enable TMR15" + default n + + config BSP_USING_TMR16 + bool "Enable TMR16" + default n + + config BSP_USING_TMR17 + bool "Enable TMR17" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output PWM" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH1 + bool "Enable PWM3 channel1" + default n + + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + + config BSP_USING_PWM3_CH3 + bool "Enable PWM3 channel3" + default n + + config BSP_USING_PWM3_CH4 + bool "Enable PWM3 channel4" + default n + endif + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/apm32/apm32f072vb-miniboard/board/SConscript b/bsp/apm32/apm32f072vb-miniboard/board/SConscript new file mode 100644 index 0000000000..5dabcec176 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/SConscript @@ -0,0 +1,36 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f072.s'] + +if rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f072.s'] + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f072.S'] + +# APM32F030x6 || APM32F030x8 || APM32F030xC +# APM32F051x6 || APM32F051x8 +# APM32F070xB +# APM32F071x8 || APM32F071xB +# APM32F072x8 || APM32F072xB +# APM32F091xB || APM32F091xC +# You can select chips from the list above +CPPDEFINES = ['APM32F072xB'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/apm32/apm32f072vb-miniboard/board/board.c b/bsp/apm32/apm32f072vb-miniboard/board/board.c new file mode 100644 index 0000000000..16ffd4f2b5 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/board.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-21 zylx first version + */ + +#include "board.h" + +void apm32_usart_init(void) +{ + GPIO_Config_T GPIO_ConfigStruct; + +#ifdef BSP_USING_UART1 + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA); + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_USART1); + + /* Connect PXx to USARTx_Tx */ + GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_9, GPIO_AF_PIN1); + + /* Connect PXx to USARRX_Rx */ + GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_10, GPIO_AF_PIN1); + + /* Configure USART Tx/Rx as alternate function push-pull */ + GPIO_ConfigStruct.mode = GPIO_MODE_AF; + GPIO_ConfigStruct.pin = GPIO_PIN_9; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_ConfigStruct.outtype = GPIO_OUT_TYPE_PP; + GPIO_ConfigStruct.pupd = GPIO_PUPD_PU; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.pin = GPIO_PIN_10; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif + +#ifdef BSP_USING_UART2 + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA); + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2); + + /* Connect PXx to USARTx_Tx */ + GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_2, GPIO_AF_PIN1); + + /* Connect PXx to USARRX_Rx */ + GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_3, GPIO_AF_PIN1); + + /* Configure USART Tx/Rx as alternate function push-pull */ + GPIO_ConfigStruct.mode = GPIO_MODE_AF; + GPIO_ConfigStruct.pin = GPIO_PIN_2; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_ConfigStruct.outtype = GPIO_OUT_TYPE_PP; + GPIO_ConfigStruct.pupd = GPIO_PUPD_PU; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.pin = GPIO_PIN_3; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif +} + +void apm32_msp_spi_init(void *Instance) +{ +#ifdef BSP_USING_SPI + GPIO_Config_T GPIO_InitStructure; + SPI_T *spi_x = (SPI_T *)Instance; + + if(spi_x == SPI1) + { + /* Enable related Clock */ + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOE); + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SPI1); + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG); + + /* Config SPI PinAF */ + GPIO_ConfigPinAF(GPIOE, GPIO_PIN_SOURCE_15, GPIO_AF_PIN1); + GPIO_ConfigPinAF(GPIOE, GPIO_PIN_SOURCE_14, GPIO_AF_PIN1); + GPIO_ConfigPinAF(GPIOE, GPIO_PIN_SOURCE_13, GPIO_AF_PIN1); + + /* Config SPI GPIO*/ + GPIO_ConfigStructInit(&GPIO_InitStructure); + GPIO_InitStructure.pin = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + GPIO_InitStructure.speed = GPIO_SPEED_50MHz; + GPIO_InitStructure.mode = GPIO_MODE_AF; + GPIO_InitStructure.outtype = GPIO_OUT_TYPE_PP; + GPIO_InitStructure.pupd = GPIO_PUPD_NO; + GPIO_Config(GPIOE, &GPIO_InitStructure); + } +#endif +} + +void apm32_msp_timer_init(void *Instance) +{ +#ifdef BSP_USING_PWM + GPIO_Config_T gpio_config; + TMR_T *tmr_x = (TMR_T *)Instance; + + if (tmr_x == TMR3) + { + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3); + + /* TMR3 channel 1 gpio init */ + GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_6, GPIO_AF_PIN0); + gpio_config.pin = GPIO_PIN_6; + gpio_config.mode = GPIO_MODE_AF; + gpio_config.outtype = GPIO_OUT_TYPE_PP; + gpio_config.pupd = GPIO_PUPD_NO; + gpio_config.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOC, &gpio_config); + + /* TMR3 channel 2 gpio init */ + GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_7, GPIO_AF_PIN0); + gpio_config.pin = GPIO_PIN_7; + GPIO_Config(GPIOC, &gpio_config); + + /* TMR3 channel 3 gpio init */ + GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_8, GPIO_AF_PIN0); + gpio_config.pin = GPIO_PIN_8; + GPIO_Config(GPIOC, &gpio_config); + + /* TMR3 channel 4 gpio init */ + GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_9, GPIO_AF_PIN0); + gpio_config.pin = GPIO_PIN_9; + GPIO_Config(GPIOC, &gpio_config); + } +#endif +} diff --git a/bsp/apm32/apm32f072vb-miniboard/board/board.h b/bsp/apm32/apm32f072vb-miniboard/board/board.h new file mode 100644 index 0000000000..8091e17298 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/board.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +#include "apm32f0xx_gpio.h" +#include "apm32f0xx_syscfg.h" +#include "apm32f0xx_rcm.h" +#include "apm32f0xx_misc.h" +#include "apm32f0xx_eint.h" +#include "apm32f0xx_usart.h" + +#if defined(RT_USING_ADC) + #include "apm32f0xx_adc.h" +#endif +#if defined(RT_USING_DAC) + #include "apm32f0xx_dac.h" +#endif +#if defined(RT_USING_RTC) + #include "apm32f0xx_rtc.h" + #include "apm32f0xx_pmu.h" +#endif +#if defined(RT_USING_SPI) + #include "apm32f0xx_spi.h" +#endif +#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) + #include "apm32f0xx_tmr.h" +#endif +#if defined(RT_USING_WDT) + #include "apm32f0xx_iwdt.h" + #include "apm32f0xx_wwdt.h" +#endif + +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define APM32_FLASH_SIZE (128 * 1024) +#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64 */ +#define APM32_SRAM_SIZE 16 +#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END APM32_SRAM_END + +void SystemClock_Config(void); + +void apm32_usart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.icf b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.icf new file mode 100644 index 0000000000..7f352fc72a --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds new file mode 100644 index 0000000000..8f9c4fa1a8 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds @@ -0,0 +1,163 @@ +/* + * linker script for APM32F0xx with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* 128KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 16K /* 16K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + _start_address_init_data = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + _start_address_data = .; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + _end_address_data = .; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + _end_stack = .; + } >RAM + + __bss_start = .; + _start_address_bss = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + _end_address_bss = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.sct b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.sct new file mode 100644 index 0000000000..adff0c5912 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/apm32/apm32f072vb-miniboard/figures/APM32F072VB.png b/bsp/apm32/apm32f072vb-miniboard/figures/APM32F072VB.png new file mode 100644 index 0000000000..77aacffaee Binary files /dev/null and b/bsp/apm32/apm32f072vb-miniboard/figures/APM32F072VB.png differ diff --git a/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_01.png b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_01.png new file mode 100644 index 0000000000..5640216ae5 Binary files /dev/null and b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_01.png differ diff --git a/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_02.png b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_02.png new file mode 100644 index 0000000000..93984c1a90 Binary files /dev/null and b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_02.png differ diff --git a/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_03.png b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_03.png new file mode 100644 index 0000000000..6280b5d664 Binary files /dev/null and b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_03.png differ diff --git a/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_04.png b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_04.png new file mode 100644 index 0000000000..b133313482 Binary files /dev/null and b/bsp/apm32/apm32f072vb-miniboard/figures/JFlash_Leader_04.png differ diff --git a/bsp/apm32/apm32f072vb-miniboard/project.ewp b/bsp/apm32/apm32f072vb-miniboard/project.ewp new file mode 100644 index 0000000000..805a2cb828 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/project.ewp @@ -0,0 +1,2399 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\context_iar.S + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Source\iar\startup_apm32f072.s + + + $PROJ_DIR$\..\libraries\Drivers\drv_common.c + + + $PROJ_DIR$\..\libraries\Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\Drivers\drv_usart.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + Libraries + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_eint.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_misc.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_gpio.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Source\system_apm32f0xx.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_usart.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_syscfg.c + + + $PROJ_DIR$\..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_rcm.c + + + + POSIX + + diff --git a/bsp/apm32/apm32f072vb-miniboard/project.eww b/bsp/apm32/apm32f072vb-miniboard/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/apm32/apm32f072vb-miniboard/project.uvoptx b/bsp/apm32/apm32f072vb-miniboard/project.uvoptx new file mode 100644 index 0000000000..e551477e4b --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/project.uvoptx @@ -0,0 +1,853 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_syscfg.c + apm32f0xx_syscfg.c + 0 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_rcm.c + apm32f0xx_rcm.c + 0 + 0 + + + + diff --git a/bsp/apm32/apm32f072vb-miniboard/project.uvprojx b/bsp/apm32/apm32f072vb-miniboard/project.uvprojx new file mode 100644 index 0000000000..14307eafbd --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/project.uvprojx @@ -0,0 +1,697 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + APM32F072VB + Geehy + Geehy.APM32F0xx_DFP.1.0.7 + https://www.geehy.com/uploads/tool/ + IRAM(0x20000000,0x4000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM)) + 0 + $$Device:APM32F072VB$Device\Device\Geehy\APM32F0xx\Include\apm32f0xx.h + + + + + + + + + + $$Device:APM32F072VB$SVD\APM32F072.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F072xB + + ..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\inc;..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Include;..\libraries\Drivers\config;..\..\..\components\libc\compilers\common\extension;.;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F0xx_Library\CMSIS\Include;..\..\..\components\libc\posix\ipc;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdio.c + 1 + ..\..\..\components\libc\compilers\common\cstdio.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + DeviceDrivers + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + startup_apm32f072.s + 2 + ..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Source\arm\startup_apm32f072.s + + + drv_common.c + 1 + ..\libraries\Drivers\drv_common.c + + + drv_gpio.c + 1 + ..\libraries\Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\Drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + apm32f0xx_eint.c + 1 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_eint.c + + + apm32f0xx_misc.c + 1 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_misc.c + + + apm32f0xx_gpio.c + 1 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_gpio.c + + + system_apm32f0xx.c + 1 + ..\libraries\APM32F0xx_Library\Device\Geehy\APM32F0xx\Source\system_apm32f0xx.c + + + apm32f0xx_usart.c + 1 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_usart.c + + + apm32f0xx_syscfg.c + 1 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_syscfg.c + + + apm32f0xx_rcm.c + 1 + ..\libraries\APM32F0xx_Library\APM32F0xx_StdPeriphDriver\src\apm32f0xx_rcm.c + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/apm32/apm32f072vb-miniboard/rtconfig.h b/bsp/apm32/apm32f072vb-miniboard/rtconfig.h new file mode 100644 index 0000000000..2bfb0b486a --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/rtconfig.h @@ -0,0 +1,241 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50000 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_APM32 +#define SOC_SERIES_APM32F0 + +/* Hardware Drivers Config */ + +#define SOC_APM32F072VB + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/apm32/apm32f072vb-miniboard/rtconfig.py b/bsp/apm32/apm32f072vb-miniboard/rtconfig.py new file mode 100644 index 0000000000..2fd6753c9b --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'D:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m0 ' + CFLAGS += ' -mcpu=cortex-m0 ' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/apm32/apm32f072vb-miniboard/template.ewp b/bsp/apm32/apm32f072vb-miniboard/template.ewp new file mode 100644 index 0000000000..5f559e1751 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/template.ewp @@ -0,0 +1,2144 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + + Release + + ARM + + 0 + + General + 3 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + diff --git a/bsp/apm32/apm32f072vb-miniboard/template.eww b/bsp/apm32/apm32f072vb-miniboard/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/apm32/apm32f072vb-miniboard/template.uvoptx b/bsp/apm32/apm32f072vb-miniboard/template.uvoptx new file mode 100644 index 0000000000..5a29a67e0a --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/template.uvoptx @@ -0,0 +1,185 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/apm32/apm32f072vb-miniboard/template.uvprojx b/bsp/apm32/apm32f072vb-miniboard/template.uvprojx new file mode 100644 index 0000000000..09efb9ffc4 --- /dev/null +++ b/bsp/apm32/apm32f072vb-miniboard/template.uvprojx @@ -0,0 +1,405 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + APM32F072VB + Geehy + Geehy.APM32F0xx_DFP.1.0.7 + https://www.geehy.com/uploads/tool/ + IRAM(0x20000000,0x4000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:APM32F072VB$Flash\APM32F0xx_128.FLM)) + 0 + $$Device:APM32F072VB$Device\Device\Geehy\APM32F0xx\Include\apm32f0xx.h + + + + + + + + + + $$Device:APM32F072VB$SVD\APM32F072.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/.config b/bsp/apm32/apm32f103xe-minibroard/.config index 49c1edd185..1d85696fbc 100644 --- a/bsp/apm32/apm32f103xe-minibroard/.config +++ b/bsp/apm32/apm32f103xe-minibroard/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -77,16 +78,19 @@ CONFIG_RT_USING_HEAP=y # CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,14 +125,16 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set # CONFIG_RT_USING_DFS_DEVFS is not set # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y @@ -143,10 +149,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set @@ -154,10 +164,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set # # Using USB @@ -302,6 +315,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_AGILE_FTP is not set # CONFIG_PKG_USING_EMBEDDEDPROTO is not set # CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set # CONFIG_PKG_USING_LORA_PKT_FWD is not set # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set @@ -309,6 +323,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SMALL_MODBUS is not set # CONFIG_PKG_USING_NET_SERVER is not set # CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set # # security packages @@ -399,7 +414,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set # CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set @@ -433,8 +447,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CBOX is not set # CONFIG_PKG_USING_SNOWFLAKE is not set # CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set # # system packages @@ -470,7 +484,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set @@ -505,19 +518,93 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KMULTI_RTIMER is not set # CONFIG_PKG_USING_TFDB is not set # CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set @@ -540,12 +627,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set @@ -560,7 +644,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CAN_YMODEM is not set # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set # CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set @@ -591,10 +674,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set # # AI packages @@ -609,6 +693,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + # # miscellaneous packages # @@ -660,7 +750,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_STATE_MACHINE is not set @@ -671,63 +760,212 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SLCAN2RTT is not set # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set # -# Privated Packages of RealThread +# Arduino libraries # -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set +# CONFIG_PKG_USING_RTDUINO is not set # -# Network Utilities +# Projects # -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set # -# RT-Thread Smart +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized # -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set CONFIG_SOC_FAMILY_APM32=y CONFIG_SOC_SERIES_APM32F1=y @@ -746,6 +984,8 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_RTC_USING_LSE is not set +# CONFIG_BSP_RTC_USING_LSI is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_TMR is not set diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds index 592dad353f..5d1d12bbfb 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds @@ -57,6 +57,7 @@ SECTIONS /* This is used by the startup in order to initialize the .data secion */ _sidata = .; + _start_address_init_data = .; } > CODE __exidx_end = .; @@ -67,6 +68,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _sdata = . ; + _start_address_data = .; *(.data) *(.data.*) @@ -75,6 +77,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; + _end_address_data = .; } >DATA .stack : @@ -85,6 +88,7 @@ SECTIONS } >DATA __bss_start = .; + _start_address_bss = .; .bss : { . = ALIGN(4); @@ -102,6 +106,7 @@ SECTIONS *(.bss.init) } > DATA __bss_end = .; + _end_address_bss = .; _end = .; diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvoptx b/bsp/apm32/apm32f103xe-minibroard/project.uvoptx index 2b7d33fccd..a6526b52bd 100644 --- a/bsp/apm32/apm32f103xe-minibroard/project.uvoptx +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvoptx @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 @@ -73,11 +73,11 @@ 0 - 0 + 1 0 1 - 0 + 255 0 1 @@ -171,15 +171,746 @@ + + 1 + 1 + 0 + 2 + 10000000 + - Source Group 1 + Applications 0 0 0 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + context_rvds.S + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 1 + 0 + 0 + 0 + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + + + Drivers + 1 + 0 + 0 + 0 + + 5 + 23 + 1 + 1 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 5 + 24 + 2 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s + startup_apm32f10x_hd.s + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\libraries\Drivers\drv_common.c + drv_common.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\libraries\Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\libraries\Drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs.c + dfs.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_file.c + dfs_file.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 8 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 9 + 50 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c + system_apm32f10x.c + 0 + 0 + + + 9 + 51 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c + apm32f10x_rcm.c + 0 + 0 + + + 9 + 52 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c + apm32f10x_misc.c + 0 + 0 + + + 9 + 53 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c + apm32f10x_usart.c + 0 + 0 + + + 9 + 54 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c + apm32f10x_eint.c + 0 + 0 + + + 9 + 55 + 1 + 0 + 0 + 0 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c + apm32f10x_gpio.c + 0 + 0 + diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx index 0fee2a3843..2136f3fc49 100644 --- a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx @@ -1,43 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 APM32F103ZE Geehy - Geehy.APM32F1xx_DFP.1.0.8 + Geehy.APM32F1xx_DFP.1.0.9 https://www.geehy.com/uploads/tool/ IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) 0 $$Device:APM32F103ZE$Device\Include\apm32f10x.h - - - - - - - - - + + + + + + + + + $$Device:APM32F103ZE$SVD\APM32F103xx.svd 0 0 - - - - - + + + + + 0 0 @@ -49,9 +52,9 @@ rtthread 1 0 - 0 + 1 1 - 0 + 1 .\build\keil\List\ 1 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -111,7 +114,7 @@ DCM.DLL -pCM3 SARMCM3.DLL - + TCM.DLL -pCM3 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -182,6 +185,7 @@ 0 0 0 + 0 0 0 8 @@ -305,7 +309,7 @@ 0x0 - + 1 @@ -332,10 +336,10 @@ 0 0 - - __STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC, APM32F10X_HD - - applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, APM32F10X_HD + + ..\..\..\components\finsh;..\..\..\components\libc\posix\io\poll;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\stdio;applications;..\..\..\components\dfs\include;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\libraries\APM32F10x_Library\APM32F10x_ETH_Driver\inc;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;. @@ -348,12 +352,12 @@ 0 0 0 - 0 + 4 - - - - + + + + @@ -365,13 +369,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -394,50 +398,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -447,35 +437,22 @@ CPU - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - - cpuport.c 1 @@ -491,57 +468,41 @@ 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial.c 1 @@ -557,29 +518,21 @@ 1 board\board.c - - startup_apm32f10x_hd.s 2 ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s - - drv_common.c 1 ..\libraries\Drivers\drv_common.c - - drv_gpio.c 1 ..\libraries\Drivers\drv_gpio.c - - drv_usart.c 1 @@ -595,22 +548,16 @@ 1 ..\..\..\components\dfs\src\dfs_posix.c - - dfs_fs.c 1 ..\..\..\components\dfs\src\dfs_fs.c - - dfs.c 1 ..\..\..\components\dfs\src\dfs.c - - dfs_file.c 1 @@ -626,29 +573,21 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c - - msh_file.c 1 @@ -664,85 +603,61 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -758,36 +673,26 @@ 1 ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c - - apm32f10x_rcm.c 1 ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c - - apm32f10x_misc.c 1 ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c - - apm32f10x_usart.c 1 ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c - - apm32f10x_eint.c 1 ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c - - apm32f10x_gpio.c 1 @@ -798,9 +703,11 @@ + - - - + + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/rtconfig.h b/bsp/apm32/apm32f103xe-minibroard/rtconfig.h index 621d91fdfd..51d71acfff 100644 --- a/bsp/apm32/apm32f103xe-minibroard/rtconfig.h +++ b/bsp/apm32/apm32f103xe-minibroard/rtconfig.h @@ -47,9 +47,9 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40101 -#define ARCH_ARM +#define RT_VER_NUM 0x50000 #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 @@ -82,6 +82,7 @@ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA @@ -170,6 +171,11 @@ /* peripheral libraries and drivers */ +/* sensors drivers */ + + +/* touch drivers */ + /* Kendryte SDK */ @@ -177,6 +183,9 @@ /* AI packages */ +/* Signal Processing and Control Algorithm Packages */ + + /* miscellaneous packages */ /* project laboratory */ @@ -187,13 +196,38 @@ /* entertainment: terminal games and other interesting software packages */ -/* Privated Packages of RealThread */ +/* Arduino libraries */ -/* Network Utilities */ +/* Projects */ -/* RT-Thread Smart */ +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + +/* Signal IO */ + + +/* Uncategorized */ #define SOC_FAMILY_APM32 #define SOC_SERIES_APM32F1 diff --git a/bsp/apm32/apm32f407ig-minibroard/.config b/bsp/apm32/apm32f407ig-minibroard/.config index 158e36b2ff..b1bed341aa 100644 --- a/bsp/apm32/apm32f407ig-minibroard/.config +++ b/bsp/apm32/apm32f407ig-minibroard/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -77,16 +78,19 @@ CONFIG_RT_USING_HEAP=y # CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M4=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -121,14 +125,16 @@ CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_ELMFAT is not set # CONFIG_RT_USING_DFS_DEVFS is not set # CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y @@ -143,10 +149,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set @@ -154,10 +164,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set # # Using USB @@ -302,6 +315,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_AGILE_FTP is not set # CONFIG_PKG_USING_EMBEDDEDPROTO is not set # CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set # CONFIG_PKG_USING_LORA_PKT_FWD is not set # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set @@ -309,6 +323,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SMALL_MODBUS is not set # CONFIG_PKG_USING_NET_SERVER is not set # CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set # # security packages @@ -400,7 +415,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set # CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set @@ -434,8 +448,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CBOX is not set # CONFIG_PKG_USING_SNOWFLAKE is not set # CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set # # system packages @@ -471,7 +485,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set @@ -506,19 +519,93 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KMULTI_RTIMER is not set # CONFIG_PKG_USING_TFDB is not set # CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set @@ -541,12 +628,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set @@ -561,7 +645,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CAN_YMODEM is not set # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set # CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set @@ -592,10 +675,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set # # AI packages @@ -610,6 +694,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + # # miscellaneous packages # @@ -661,7 +751,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_STATE_MACHINE is not set @@ -672,63 +761,212 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SLCAN2RTT is not set # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set # -# Privated Packages of RealThread +# Arduino libraries # -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set +# CONFIG_PKG_USING_RTDUINO is not set # -# Network Utilities +# Projects # -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set # -# RT-Thread Smart +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized # -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set CONFIG_SOC_FAMILY_APM32=y CONFIG_SOC_SERIES_APM32F4=y diff --git a/bsp/apm32/apm32f407ig-minibroard/board/board.h b/bsp/apm32/apm32f407ig-minibroard/board/board.h index 94b48d16e6..6aa61cdc92 100644 --- a/bsp/apm32/apm32f407ig-minibroard/board/board.h +++ b/bsp/apm32/apm32f407ig-minibroard/board/board.h @@ -15,6 +15,7 @@ #include #include "apm32f4xx_gpio.h" +#include "apm32f4xx_syscfg.h" #include "apm32f4xx_rcm.h" #include "apm32f4xx_misc.h" #include "apm32f4xx_rcm.h" diff --git a/bsp/apm32/apm32f407ig-minibroard/project.uvoptx b/bsp/apm32/apm32f407ig-minibroard/project.uvoptx index 287920c063..dc86c0ab26 100644 --- a/bsp/apm32/apm32f407ig-minibroard/project.uvoptx +++ b/bsp/apm32/apm32f407ig-minibroard/project.uvoptx @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 @@ -175,11 +175,747 @@ - Source Group 1 + Applications 0 0 0 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + + + Drivers + 1 + 0 + 0 + 0 + + 5 + 23 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 5 + 24 + 2 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\arm\startup_apm32f40x.s + startup_apm32f40x.s + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\libraries\Drivers\drv_common.c + drv_common.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\libraries\Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\libraries\Drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs.c + dfs.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_file.c + dfs_file.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 7 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 7 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 7 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 7 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 8 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 8 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libraries + 1 + 0 + 0 + 0 + + 9 + 50 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_usart.c + apm32f4xx_usart.c + 0 + 0 + + + 9 + 51 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_syscfg.c + apm32f4xx_syscfg.c + 0 + 0 + + + 9 + 52 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c + apm32f4xx_rcm.c + 0 + 0 + + + 9 + 53 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c + apm32f4xx_eint.c + 0 + 0 + + + 9 + 54 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_misc.c + apm32f4xx_misc.c + 0 + 0 + + + 9 + 55 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_gpio.c + apm32f4xx_gpio.c + 0 + 0 + + + 9 + 56 + 1 + 0 + 0 + 0 + ..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\system_apm32f4xx.c + system_apm32f4xx.c + 0 + 0 + diff --git a/bsp/apm32/apm32f407ig-minibroard/project.uvprojx b/bsp/apm32/apm32f407ig-minibroard/project.uvprojx index 2b721ff537..3c06617113 100644 --- a/bsp/apm32/apm32f407ig-minibroard/project.uvprojx +++ b/bsp/apm32/apm32f407ig-minibroard/project.uvprojx @@ -1,43 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 APM32F407IG Geehy - Geehy.APM32F4xx_DFP.1.0.1 + Geehy.APM32F4xx_DFP.1.0.2 https://www.geehy.com/uploads/tool/ IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL080000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM)) 0 - - - - - - - - - - + + + + + + + + + + $$Device:APM32F407IG$SVD\APM32F40x.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -182,6 +185,7 @@ 0 2 0 + 0 1 0 8 @@ -305,7 +309,7 @@ 0x10000 - + 1 @@ -332,10 +336,10 @@ 0 0 - - __STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC - - applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc;..\libraries\APM32F4xx_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ + + ..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;.;..\libraries\Drivers;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\libraries\APM32F4xx_Library\CMSIS\Include;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\..\..\components\drivers\include;board;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\stdio;..\..\..\components\dfs\include;applications;..\libraries\Drivers\config;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\libraries\APM32F4xx_Library\APM32F4xx_ETH_Driver\inc;..\..\..\components\libc\compilers\common\extension;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc @@ -348,12 +352,12 @@ 0 0 0 - 0 + 4 - - - - + + + + @@ -365,13 +369,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -394,50 +398,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -447,35 +437,22 @@ CPU - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -491,57 +468,41 @@ 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial.c 1 @@ -557,29 +518,21 @@ 1 board\board.c - - startup_apm32f40x.s 2 ..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\arm\startup_apm32f40x.s - - drv_common.c 1 ..\libraries\Drivers\drv_common.c - - drv_gpio.c 1 ..\libraries\Drivers\drv_gpio.c - - drv_usart.c 1 @@ -595,22 +548,16 @@ 1 ..\..\..\components\dfs\src\dfs_posix.c - - dfs_fs.c 1 ..\..\..\components\dfs\src\dfs_fs.c - - dfs.c 1 ..\..\..\components\dfs\src\dfs.c - - dfs_file.c 1 @@ -626,29 +573,21 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c - - msh_file.c 1 @@ -664,85 +603,61 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -758,36 +673,31 @@ 1 ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_usart.c - - + + apm32f4xx_syscfg.c + 1 + ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_syscfg.c + apm32f4xx_rcm.c 1 ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c - - apm32f4xx_eint.c 1 ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c - - apm32f4xx_misc.c 1 ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_misc.c - - apm32f4xx_gpio.c 1 ..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_gpio.c - - system_apm32f4xx.c 1 @@ -798,9 +708,11 @@ + - - - + + + + diff --git a/bsp/apm32/apm32f407ig-minibroard/rtconfig.h b/bsp/apm32/apm32f407ig-minibroard/rtconfig.h index 1cd86165d6..2ad4c524dd 100644 --- a/bsp/apm32/apm32f407ig-minibroard/rtconfig.h +++ b/bsp/apm32/apm32f407ig-minibroard/rtconfig.h @@ -47,9 +47,9 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40101 -#define ARCH_ARM +#define RT_VER_NUM 0x50000 #define RT_USING_CPU_FFS +#define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M4 @@ -82,6 +82,7 @@ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA @@ -170,6 +171,11 @@ /* peripheral libraries and drivers */ +/* sensors drivers */ + + +/* touch drivers */ + /* Kendryte SDK */ @@ -177,6 +183,9 @@ /* AI packages */ +/* Signal Processing and Control Algorithm Packages */ + + /* miscellaneous packages */ /* project laboratory */ @@ -187,13 +196,38 @@ /* entertainment: terminal games and other interesting software packages */ -/* Privated Packages of RealThread */ +/* Arduino libraries */ -/* Network Utilities */ +/* Projects */ -/* RT-Thread Smart */ +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + +/* Signal IO */ + + +/* Uncategorized */ #define SOC_FAMILY_APM32 #define SOC_SERIES_APM32F4 diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_adc.h b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_adc.h new file mode 100644 index 0000000000..7f4612556a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_adc.h @@ -0,0 +1,364 @@ +/*! + * @file apm32f0xx_adc.h + * + * @brief This file contains all the functions prototypes for the ADC firmware library + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_ADC_H +#define __APM32F0XX_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup ADC_Driver + @{ +*/ + +/** @defgroup ADC_Macros Macros + @{ +*/ + +/* ADC_channels */ +#define ADC_Channel_TempSensor ((uint32_t)ADC_CHANNEL_16) /*!< ADC TempSensor Channel definition */ +#define ADC_Channel_Vrefint ((uint32_t)ADC_CHANNEL_17) /*!< ADC Vrefint Channel definition */ +#define ADC_Channel_Vbat ((uint32_t)ADC_CHANNEL_18) /*!< ADC Vbat Channel definition */ + +/* ADC CFG mask */ +#define CFG1_CLEAR_MASK ((uint32_t)0xFFFFD203) + +/* Calibration time out */ +#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000) + +/**@} end of group ADC_Macros */ + +/** @defgroup ADC_Enumerations Enumerations + @{ +*/ + +/** + * @brief ADC conversion mode + */ +typedef enum +{ + ADC_CONVERSION_SINGLE = ((uint8_t)0), /*!< Single conversion mode */ + ADC_CONVERSION_CONTINUOUS = ((uint8_t)1), /*!< Continuous conversion mode */ +} ADC_CONVERSION_T; + +/** + * @brief ADC Jitter + */ +typedef enum +{ + ADC_JITTER_PCLKDIV2 = ((uint8_t)0x01), /*!< ADC clocked by PCLK div2 */ + ADC_JITTER_PCLKDIV4 = ((uint8_t)0x02), /*!< ADC clocked by PCLK div4 */ +} ADC_JITTER_T; + +/** + * @brief ADC clock mode + */ +typedef enum +{ + ADC_CLOCK_MODE_ASYNCLK = ((uint8_t)0x00), /*!< ADC Asynchronous clock mode */ + ADC_CLOCK_MODE_SYNCLKDIV2 = ((uint8_t)0x01), /*!< Synchronous clock mode divided by 2 */ + ADC_CLOCK_MODE_SYNCLKDIV4 = ((uint8_t)0x02), /*!< Synchronous clock mode divided by 4 */ +} ADC_CLOCK_MODE_T; + +/** + * @brief ADC data resolution + */ +typedef enum +{ + ADC_RESOLUTION_12B = ((uint8_t)0x00), /*!< ADC Resolution is 12 bits */ + ADC_RESOLUTION_10B = ((uint8_t)0x01), /*!< ADC Resolution is 10 bits */ + ADC_RESOLUTION_8B = ((uint8_t)0x02), /*!< ADC Resolution is 8 bits */ + ADC_RESOLUTION_6B = ((uint8_t)0x03), /*!< ADC Resolution is 6 bits */ +} ADC_RESOLUTION_T; + +/** + * @brief ADC data alignment + */ +typedef enum +{ + ADC_DATA_ALIGN_RIGHT = ((uint8_t)0), /*!< Data alignment right */ + ADC_DATA_ALIGN_LEFT = ((uint8_t)1), /*!< Data alignment left */ +} ADC_DATA_ALIGN_T; + +/** + * @brief ADC scan sequence direction + */ +typedef enum +{ + ADC_SCAN_DIR_UPWARD = ((uint8_t)0), /*!< from CHSEL0 to CHSEL17 */ + ADC_SCAN_DIR_BACKWARD = ((uint8_t)1), /*!< from CHSEL17 to CHSEL0 */ +} ADC_SCAN_DIR_T; + +/** + * @brief ADC DMA Mode + */ +typedef enum +{ + ADC_DMA_MODE_ONESHOUT = ((uint8_t)0), /*!< ADC DMA Mode Select one shot */ + ADC_DMA_MODE_CIRCULAR = ((uint8_t)1), /*!< ADC DMA Mode Select circular */ +} ADC_DMA_MODE_T; + +/** + * @brief ADC external conversion trigger edge selectio + */ +typedef enum +{ + ADC_EXT_TRIG_EDGE_NONE = ((uint8_t)0x00), /*!< ADC External Trigger Conversion mode disabled */ + ADC_EXT_TRIG_EDGE_RISING = ((uint8_t)0x01), /*!< ADC External Trigger Conversion mode rising edge */ + ADC_EXT_TRIG_EDGE_FALLING = ((uint8_t)0x02), /*!< ADC External Trigger Conversion mode falling edge */ + ADC_EXT_TRIG_EDGE_ALL = ((uint8_t)0x03), /*!< ADC External Trigger Conversion mode rising and falling edges */ +} ADC_EXT_TRIG_EDGE_T; + +/** + * @brief ADC external trigger sources selection + */ +typedef enum +{ + ADC_EXT_TRIG_CONV_TRG0 = ((uint8_t)0x00), /*!< ADC External Trigger Conversion timer1 TRG0 */ + ADC_EXT_TRIG_CONV_TRG1 = ((uint8_t)0x01), /*!< ADC External Trigger Conversion timer1 CC4 */ + ADC_EXT_TRIG_CONV_TRG2 = ((uint8_t)0x02), /*!< ADC External Trigger Conversion timer2 TRGO */ + ADC_EXT_TRIG_CONV_TRG3 = ((uint8_t)0x03), /*!< ADC External Trigger Conversion timer3 TRG0 */ + ADC_EXT_TRIG_CONV_TRG4 = ((uint8_t)0x04), /*!< ADC External Trigger Conversion timer15 TRG0 */ +} ADC_EXT_TRIG_CONV_T; + +/** + * @brief ADC analog watchdog channel selection + */ +typedef enum +{ + ADC_ANALG_WDT_CHANNEL_0 = ((uint8_t)0x00), /*!< AWD Channel 0 */ + ADC_ANALG_WDT_CHANNEL_1 = ((uint8_t)0x01), /*!< AWD Channel 1 */ + ADC_ANALG_WDT_CHANNEL_2 = ((uint8_t)0x02), /*!< AWD Channel 2 */ + ADC_ANALG_WDT_CHANNEL_3 = ((uint8_t)0x03), /*!< AWD Channel 3 */ + ADC_ANALG_WDT_CHANNEL_4 = ((uint8_t)0x04), /*!< AWD Channel 4 */ + ADC_ANALG_WDT_CHANNEL_5 = ((uint8_t)0x05), /*!< AWD Channel 5 */ + ADC_ANALG_WDT_CHANNEL_6 = ((uint8_t)0x06), /*!< AWD Channel 6 */ + ADC_ANALG_WDT_CHANNEL_7 = ((uint8_t)0x07), /*!< AWD Channel 7 */ + ADC_ANALG_WDT_CHANNEL_8 = ((uint8_t)0x08), /*!< AWD Channel 8 */ + ADC_ANALG_WDT_CHANNEL_9 = ((uint8_t)0x09), /*!< AWD Channel 9 */ + ADC_ANALG_WDT_CHANNEL_10 = ((uint8_t)0x0A), /*!< AWD Channel 10 */ + ADC_ANALG_WDT_CHANNEL_11 = ((uint8_t)0x0B), /*!< AWD Channel 11 */ + ADC_ANALG_WDT_CHANNEL_12 = ((uint8_t)0x0C), /*!< AWD Channel 12 */ + ADC_ANALG_WDT_CHANNEL_13 = ((uint8_t)0x0D), /*!< AWD Channel 13 */ + ADC_ANALG_WDT_CHANNEL_14 = ((uint8_t)0x0E), /*!< AWD Channel 14 */ + ADC_ANALG_WDT_CHANNEL_15 = ((uint8_t)0x0F), /*!< AWD Channel 15 */ + ADC_ANALG_WDT_CHANNEL_16 = ((uint8_t)0x10), /*!< AWD Channel 16 */ + ADC_ANALG_WDT_CHANNEL_17 = ((uint8_t)0x11), /*!< AWD Channel 17 */ + ADC_ANALG_WDT_CHANNEL_18 = ((uint8_t)0x12), /*!< AWD Channel 18 */ +} ADC_ANALG_WDT_CHANNEL_T; + +/** + * @brief ADC sampling times + */ +typedef enum +{ + ADC_SAMPLE_TIME_1_5 = ((uint8_t)0x00), /*!< 1.5 ADC clock cycles */ + ADC_SAMPLE_TIME_7_5 = ((uint8_t)0x01), /*!< 7.5 ADC clock cycles */ + ADC_SAMPLE_TIME_13_5 = ((uint8_t)0x02), /*!< 13.5 ADC clock cycles */ + ADC_SAMPLE_TIME_28_5 = ((uint8_t)0x03), /*!< 28.5 ADC clock cycles */ + ADC_SAMPLE_TIME_41_5 = ((uint8_t)0x04), /*!< 41.5 ADC clock cycles */ + ADC_SAMPLE_TIME_55_5 = ((uint8_t)0x05), /*!< 55.5 ADC clock cycles */ + ADC_SAMPLE_TIME_71_5 = ((uint8_t)0x06), /*!< 71.5 ADC clock cycles */ + ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07), /*!< 239.5 ADC clock cycles */ +} ADC_SAMPLE_TIME_T; + +/** + * @brief ADC channel selection + */ +typedef enum +{ + ADC_CHANNEL_0 = ((uint32_t)0x00000001), /*!< ADC Channel 0 */ + ADC_CHANNEL_1 = ((uint32_t)0x00000002), /*!< ADC Channel 1 */ + ADC_CHANNEL_2 = ((uint32_t)0x00000004), /*!< ADC Channel 2 */ + ADC_CHANNEL_3 = ((uint32_t)0x00000008), /*!< ADC Channel 3 */ + ADC_CHANNEL_4 = ((uint32_t)0x00000010), /*!< ADC Channel 4 */ + ADC_CHANNEL_5 = ((uint32_t)0x00000020), /*!< ADC Channel 5 */ + ADC_CHANNEL_6 = ((uint32_t)0x00000040), /*!< ADC Channel 6 */ + ADC_CHANNEL_7 = ((uint32_t)0x00000080), /*!< ADC Channel 7 */ + ADC_CHANNEL_8 = ((uint32_t)0x00000100), /*!< ADC Channel 8 */ + ADC_CHANNEL_9 = ((uint32_t)0x00000200), /*!< ADC Channel 9 */ + ADC_CHANNEL_10 = ((uint32_t)0x00000400), /*!< ADC Channel 10 */ + ADC_CHANNEL_11 = ((uint32_t)0x00000800), /*!< ADC Channel 11 */ + ADC_CHANNEL_12 = ((uint32_t)0x00001000), /*!< ADC Channel 12 */ + ADC_CHANNEL_13 = ((uint32_t)0x00002000), /*!< ADC Channel 13 */ + ADC_CHANNEL_14 = ((uint32_t)0x00004000), /*!< ADC Channel 14 */ + ADC_CHANNEL_15 = ((uint32_t)0x00008000), /*!< ADC Channel 15 */ + ADC_CHANNEL_16 = ((uint32_t)0x00010000), /*!< ADC Channel 16 */ + ADC_CHANNEL_17 = ((uint32_t)0x00020000), /*!< ADC Channel 17 */ + ADC_CHANNEL_18 = ((uint32_t)0x00040000), /*!< ADC Channel 18 (Not for APM32F030 devices) */ +} ADC_CHANNEL_T; + +/** + * @brief ADC interrupts definition + */ +typedef enum +{ + ADC_INT_ADRDY = ((uint8_t)0x01), /*!< ADC ready interrupt */ + ADC_INT_CSMP = ((uint8_t)0x02), /*!< End of sampling interrupt */ + ADC_INT_CC = ((uint8_t)0x04), /*!< End of conversion interrupt */ + ADC_INT_CS = ((uint8_t)0x08), /*!< End of sequence interrupt */ + ADC_INT_OVR = ((uint8_t)0x10), /*!< ADC overrun interrupt */ + ADC_INT_AWD = ((uint8_t)0x80), /*!< Analog watchdog interrupt */ +} ADC_INT_T; + +/** + * @brief ADC Interrupt flag + */ +typedef enum +{ + ADC_INT_FLAG_ADRDY = ((uint8_t)0x01), /*!< ADC ready interrupt flag */ + ADC_INT_FLAG_CSMP = ((uint8_t)0x02), /*!< End of sampling interrupt flag */ + ADC_INT_FLAG_CC = ((uint8_t)0x04), /*!< End of conversion interrupt flag */ + ADC_INT_FLAG_CS = ((uint8_t)0x08), /*!< End of sequence interrupt flag */ + ADC_INT_FLAG_OVR = ((uint8_t)0x10), /*!< ADC overrun interrupt flag */ + ADC_INT_FLAG_AWD = ((uint8_t)0x80), /*!< Analog watchdog interrupt flag */ +} ADC_INT_FLAG_T; + +/** + * @brief ADC flag + */ +typedef enum +{ + ADC_FLAG_ADCON = ((uint32_t)0x01000001), /*!< ADC enable flag */ + ADC_FLAG_ADCOFF = ((uint32_t)0x01000002), /*!< ADC disable flag */ + ADC_FLAG_ADCSTA = ((uint32_t)0x01000004), /*!< ADC start conversion flag */ + ADC_FLAG_ADCSTOP = ((uint32_t)0x01000010), /*!< ADC stop conversion flag */ + ADC_FLAG_ADCCAL = ((int) 0x81000000), /*!< ADC calibration flag */ + ADC_FLAG_ADRDY = ((uint8_t)0x01), /*!< ADC ready flag */ + ADC_FLAG_CSMP = ((uint8_t)0x02), /*!< End of sampling flag */ + ADC_FLAG_CC = ((uint8_t)0x04), /*!< End of conversion flag */ + ADC_FLAG_CS = ((uint8_t)0x08), /*!< End of sequence flag */ + ADC_FLAG_OVR = ((uint8_t)0x10), /*!< ADC overrun flag */ + ADC_FLAG_AWD = ((uint8_t)0x80), /*!< Analog watchdog flag */ +} ADC_FLAG_T; + +/**@} end of group ADC_Enumerations */ + +/** @defgroup ADC_Structures Structures + @{ +*/ + +/** + * @brief ADC Config struct definition + */ +typedef struct +{ + ADC_RESOLUTION_T resolution; /*!< Specifies the ADC data resolution */ + ADC_DATA_ALIGN_T dataAlign; /*!< Specifies the data alignment mode */ + ADC_SCAN_DIR_T scanDir; /*!< Specifies the scan mode */ + ADC_CONVERSION_T convMode; /*!< Specifies the conversion mode */ + ADC_EXT_TRIG_CONV_T extTrigConv; /*!< Specifies the external trigger sources */ + ADC_EXT_TRIG_EDGE_T extTrigEdge; /*!< Specifies the external conversion trigger edge */ +} ADC_Config_T; + +/**@} end of group ADC_Structures */ + +/** @defgroup ADC_Variables Variables + @{ + */ + +/**@} end of group ADC_Variables */ + +/** @defgroup ADC_Functions Functions + @{ +*/ + +/* ADC reset and configuration */ +void ADC_Reset(void); +void ADC_Config(ADC_Config_T* adcConfig); +void ADC_ConfigStructInit(ADC_Config_T* adcConfig); +void ADC_Enable(void); +void ADC_Disable(void); +void ADC_EnableAutoPowerOff(void); +void ADC_DisableAutoPowerOff(void); +void ADC_EnableWaitMode(void); +void ADC_DisableWaitMode(void); +void ADC_ConfigChannel(uint32_t channel, uint8_t sampleTime); +void ADC_EnableContinuousMode(void); +void ADC_DisableContinuousMode(void); +void ADC_EnableDiscMode(void); +void ADC_DisableDiscMode(void); +void ADC_EnableOverrunMode(void); +void ADC_DisableOverrunMode(void); +void ADC_StopConversion(void); +void ADC_StartConversion(void); +void ADC_DMARequestMode(ADC_DMA_MODE_T DMARequestMode); + +/* ADC clock and jitter */ +void ADC_ClockMode(ADC_CLOCK_MODE_T clockMode); +void ADC_EnableJitter(ADC_JITTER_T jitter); +void ADC_DisableJitter(ADC_JITTER_T jitter); + +/* ADC analog watchdog */ +void ADC_EnableAnalogWatchdog(void); +void ADC_DisableAnalogWatchdog(void); +void ADC_AnalogWatchdogLowThreshold(uint16_t lowThreshold); +void ADC_AnalogWatchdogHighThreshold(uint16_t highThreshold); +void ADC_AnalogWatchdogSingleChannel(uint32_t channel); +void ADC_EnableAnalogWatchdogSingleChannel(void); +void ADC_DisableAnalogWatchdogSingleChannel(void); + +/* ADC common configuration */ +void ADC_EnableTempSensor(void); +void ADC_DisableTempSensor(void); +void ADC_EnableVrefint(void); +void ADC_DisableVrefint(void); +void ADC_EnableVbat(void); /*!< Not for APM32F030 devices */ +void ADC_DisableVbat(void); /*!< Not for APM32F030 devices */ + +/* Read data */ +uint32_t ADC_ReadCalibrationFactor(void); +uint16_t ADC_ReadConversionValue(void); + +/* DMA */ +void ADC_EnableDMA(void); +void ADC_DisableDMA(void); + +/* Interrupt and flag */ +void ADC_EnableInterrupt(uint8_t interrupt); +void ADC_DisableInterrupt(uint8_t interrupt); +uint8_t ADC_ReadStatusFlag(ADC_FLAG_T flag); +void ADC_ClearStatusFlag(uint32_t flag); +uint8_t ADC_ReadIntFlag(ADC_INT_FLAG_T flag); +void ADC_ClearIntFlag(uint32_t flag); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F0XX_ADC_H */ + +/**@} end of group ADC_Functions */ +/**@} end of group ADC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_can.h b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_can.h new file mode 100644 index 0000000000..60f1057c8f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_can.h @@ -0,0 +1,413 @@ +/*! + * @file apm32f0xx_can.h + * + * @brief This file contains all the functions prototypes for the CAN firmware library + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_CAN_H +#define __APM32F0XX_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CAN_Driver + @{ +*/ + +/** @defgroup CAN_Macros Macros + @{ +*/ + +/**@} end of group CAN_Macros */ + +/** @defgroup CAN_Enumerations Enumerations + @{ +*/ + +/** + * @brief CAN operating mode + */ +typedef enum +{ + CAN_OPERATING_MODE_INIT = ((uint8_t)00), /*!< Initialization mode */ + CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), /*!< Normal mode */ + CAN_OPERATING_MODE_SLEEP = ((uint8_t)02), /*!< sleep mode */ +} CAN_OPERATING_MODE_T; + +/** + * @brief CAN test mode + */ +typedef enum +{ + CAN_MODE_NORMAL = ((uint8_t)00), /*!< normal mode */ + CAN_MODE_LOOPBACK = ((uint8_t)01), /*!< loopback mode */ + CAN_MODE_SILENT = ((uint8_t)02), /*!< silent mode */ + CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03), /*!< loopback combined with silent mode */ +} CAN_MODE_T; + +/** + * @brief CAN filter mode + */ +typedef enum +{ + CAN_FILTER_MODE_IDMASK = ((uint8_t)00), /*!< identifier/mask mode */ + CAN_FILTER_MODE_IDLIST = ((uint8_t)01), /*!< identifier list mode */ +} CAN_FILTER_MODE_T; + +/** + * @brief CAN synchronisation jump width + */ +typedef enum +{ + CAN_SJW_1 = ((uint8_t)00), /*!< 1 time quantum */ + CAN_SJW_2 = ((uint8_t)01), /*!< 2 time quantum */ + CAN_SJW_3 = ((uint8_t)02), /*!< 3 time quantum */ + CAN_SJW_4 = ((uint8_t)03), /*!< 4 time quantum */ +} CAN_SJW_T; + +/** + * @brief CAN_time quantum in bit_segment_1 + */ +typedef enum +{ + CAN_TIME_SEGMENT1_1 = (uint8_t)0x00, /*!< 1 time quanta */ + CAN_TIME_SEGMENT1_2 = (uint8_t)0x01, /*!< 2 time quanta */ + CAN_TIME_SEGMENT1_3 = (uint8_t)0x02, /*!< 3 time quanta */ + CAN_TIME_SEGMENT1_4 = (uint8_t)0x03, /*!< 4 time quanta */ + CAN_TIME_SEGMENT1_5 = (uint8_t)0x04, /*!< 5 time quanta */ + CAN_TIME_SEGMENT1_6 = (uint8_t)0x05, /*!< 6 time quanta */ + CAN_TIME_SEGMENT1_7 = (uint8_t)0x06, /*!< 7 time quanta */ + CAN_TIME_SEGMENT1_8 = (uint8_t)0x07, /*!< 8 time quanta */ + CAN_TIME_SEGMENT1_9 = (uint8_t)0x08, /*!< 9 time quanta */ + CAN_TIME_SEGMENT1_10 = (uint8_t)0x09, /*!< 10 time quanta */ + CAN_TIME_SEGMENT1_11 = (uint8_t)0x0A, /*!< 11 time quanta */ + CAN_TIME_SEGMENT1_12 = (uint8_t)0x0B, /*!< 12 time quanta */ + CAN_TIME_SEGMENT1_13 = (uint8_t)0x0C, /*!< 13 time quanta */ + CAN_TIME_SEGMENT1_14 = (uint8_t)0x0D, /*!< 14 time quanta */ + CAN_TIME_SEGMENT1_15 = (uint8_t)0x0E, /*!< 15 time quanta */ + CAN_TIME_SEGMENT1_16 = (uint8_t)0x0F, /*!< 16 time quanta */ +} CAN_TIME_SEGMENT1_T; + +/** + * @brief CAN_time_quantum_in_bit_segment_2 + */ +typedef enum +{ + CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, /*!< 1 time quanta */ + CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, /*!< 2 time quanta */ + CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, /*!< 3 time quanta */ + CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, /*!< 4 time quanta */ + CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, /*!< 5 time quanta */ + CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, /*!< 6 time quanta */ + CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, /*!< 7 time quanta */ + CAN_TIME_SEGMENT2_8 = (uint8_t)0x07, /*!< 8 time quanta */ +} CAN_TIME_SEGMENT2_T; + +/** + * @brief CAN_filter_scale + */ +typedef enum +{ + CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), /*!< Two 16-bit filters */ + CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), /*!< One 32-bit filter */ +} CAN_FILTER_SCALE_T; + +/** + * @brief CAN identifier type + */ +typedef enum +{ + CAN_TYPEID_STD = ((uint32_t)0x00000000), /*!< Standard Id */ + CAN_TYPEID_EXT = ((uint32_t)0x00000004), /*!< Extended Id */ +} CAN_TYPEID_T; + +/** + * @brief CAN_remote_transmission_request + */ +typedef enum +{ + CAN_RTXR_DATA = ((uint32_t)0x00000000), /*!< Data frame */ + CAN_RTXR_REMOTE = ((uint32_t)0x00000002), /*!< Remote frame */ +} CAN_RTXR_T; + +/** + * @brief CAN_transmit_constants + */ +typedef enum +{ + CAN_TX_FAILED = ((uint8_t)0x00), /*!< CAN transmission failed */ + CAN_TX_OK = ((uint8_t)0x01), /*!< CAN transmission succeeded */ + CAN_TX_WAITING = ((uint8_t)0x02), /*!< CAN waiting for transmission */ + CAN_TX_MAILBOX_FULL = ((uint8_t)0x04), /*!< CAN cell did not provide */ +} CAN_TX_T; + +/** + * @brief CAN sleep constants + */ +typedef enum +{ + CAN_SLEEP_FAILED = ((uint8_t)0x00), /*!< CAN did not enter the sleep mode */ + CAN_SLEEP_OK = ((uint8_t)0x01), /*!< CAN entered the sleep mode */ +} CAN_SLEEP_T; + +/** + * @brief CAN wake up constants + */ +typedef enum +{ + CAN_WAKEUP_FAILED = ((uint8_t)0x00), /*!< CAN did not leave the sleep mode */ + CAN_WAKEUP_OK = ((uint8_t)0x01), /*!< CAN leaved the sleep mode */ +} CAN_WUP_T; + +/** + * @brief CAN receive FIFO + */ +typedef enum +{ + CAN_FIFO_0 = ((uint8_t)0x00), /*!< CAN FIFO 0 used to receive */ + CAN_FIFO_1 = ((uint8_t)0x01), /*!< CAN FIFO 1 used to receive */ +} CAN_FIFO_T; + +/** + * @brief CAN_error_Code_constants + */ +typedef enum +{ + CAN_ERROR_CODE_NOERR = ((uint8_t)0x00), /*!< No Error */ + CAN_ERROR_CODE_STUFFERR = ((uint8_t)0x10), /*!< Stuff Error */ + CAN_ERROR_CODE_FORMERR = ((uint8_t)0x20), /*!< Form Error */ + CAN_ERROR_CODE_ACKERR = ((uint8_t)0x30), /*!< Acknowledgment Error */ + CAN_ERROR_CODE_BITRECESSIVEERR = ((uint8_t)0x40), /*!< Bit Recessive Error */ + CAN_ERROR_CODE_BITDOMINANTERR = ((uint8_t)0x50), /*!< Bit Dominant Error */ + CAN_ERROR_CODE_CRCERR = ((uint8_t)0x60), /*!< CRC Error */ + CAN_ERROR_CODE_SOFTWARESETERR = ((uint8_t)0x70), /*!< Software Set Error */ +} CAN_ERROR_CODE_T; + +/** + * @brief Flags + */ +typedef enum +{ + /* Error Flags */ + CAN_FLAG_EWF = ((uint32_t)0x10F00001), /*!< Error Warning Flag */ + CAN_FLAG_EPF = ((uint32_t)0x10F00002), /*!< Error Passive Flag */ + CAN_FLAG_BOF = ((uint32_t)0x10F00004), /*!< Bus-Off Flag */ + CAN_FLAG_LEC = ((uint32_t)0x30F00070), /*!< Last error code Flag */ + /* Operating Mode Flags */ + CAN_FLAG_WUP = ((uint32_t)0x31000008), /*!< Wake up Flag */ + CAN_FLAG_SLAK = ((uint32_t)0x31000012), /*!< Sleep acknowledge Flag */ + /* Transmit Flags */ + CAN_FLAG_RQCP0 = ((uint32_t)0x32000001), /*!< Request MailBox0 Flag */ + CAN_FLAG_RQCP1 = ((uint32_t)0x32000100), /*!< Request MailBox1 Flag */ + CAN_FLAG_RQCP2 = ((uint32_t)0x32010000), /*!< Request MailBox2 Flag */ + /* Receive Flags */ + CAN_FLAG_FMP0 = ((uint32_t)0x14000003), /*!< FIFO 0 Message Pending Flag */ + CAN_FLAG_FF0 = ((uint32_t)0x34000008), /*!< FIFO 0 Full Flag */ + CAN_FLAG_FOV0 = ((uint32_t)0x34000010), /*!< FIFO 0 Overrun Flag */ + CAN_FLAG_FMP1 = ((uint32_t)0x18000003), /*!< FIFO 1 Message Pending Flag */ + CAN_FLAG_FF1 = ((uint32_t)0x38000008), /*!< FIFO 1 Full Flag */ + CAN_FLAG_FOV1 = ((uint32_t)0x38000010), /*!< FIFO 1 Overrun Flag */ +} CAN_FLAG_T; + +/** + * @brief CAN interrupts + */ +typedef enum +{ + CAN_INT_TXME = BIT0, /*!< Transmit mailbox empty Interrupt */ + CAN_INT_F0MP = BIT1, /*!< FIFO 0 message pending Interrupt */ + CAN_INT_F0FUL = BIT2, /*!< FIFO 0 full Interrupt */ + CAN_INT_F0OVR = BIT3, /*!< FIFO 0 overrun Interrupt */ + CAN_INT_F1MP = BIT4, /*!< FIFO 1 message pending Interrupt */ + CAN_INT_F1FUL = BIT5, /*!< FIFO 1 full Interrupt */ + CAN_INT_F1OVR = BIT6, /*!< FIFO 1 overrun Interrupt */ + CAN_INT_EWIE = BIT8, /*!< Error warning Interrupt */ + CAN_INT_EPIE = BIT9, /*!< Error passive Interrupt */ + CAN_INT_BOIE = BIT10, /*!< Bus-off Interrupt */ + CAN_INT_LEC = BIT11, /*!< Last error code Interrupt */ + CAN_INT_ERR = BIT15, /*!< Error Interrupt */ + CAN_INT_WUP = BIT16, /*!< Wake-up Interrupt */ + CAN_INT_SLE = BIT17, /*!< Sleep acknowledge Interrupt */ +} CAN_INT_T; + +typedef enum +{ + CAN_FILTER_NUMBER_0 = 0, /*!< Number 0 of filters */ + CAN_FILTER_NUMBER_1, /*!< Number 1 of filters */ + CAN_FILTER_NUMBER_2, /*!< Number 2 of filters */ + CAN_FILTER_NUMBER_3, /*!< Number 3 of filters */ + CAN_FILTER_NUMBER_4, /*!< Number 4 of filters */ + CAN_FILTER_NUMBER_5, /*!< Number 5 of filters */ + CAN_FILTER_NUMBER_6, /*!< Number 6 of filters */ + CAN_FILTER_NUMBER_7, /*!< Number 7 of filters */ + CAN_FILTER_NUMBER_8, /*!< Number 8 of filters */ + CAN_FILTER_NUMBER_9, /*!< Number 9 of filters */ + CAN_FILTER_NUMBER_10, /*!< Number 10 of filters */ + CAN_FILTER_NUMBER_11, /*!< Number 11 of filters */ + CAN_FILTER_NUMBER_12, /*!< Number 12 of filters */ + CAN_FILTER_NUMBER_13, /*!< Number 13 of filters */ +} CAN_FILTER_NUMBER_T; + +typedef enum +{ + CAN_MAILBOX_0 = ((uint8_t)0x00), /*!< Tx mailbox0 */ + CAN_MAILBOX_1 = ((uint8_t)0x01), /*!< Tx mailbox1 */ + CAN_MAILBOX_2 = ((uint8_t)0x02), /*!< Tx mailbox2 */ +} CAN_MAILBOX_T; + +/**@} end of group CAN_Enumerations */ + +/** @defgroup CAN_Structures Structures + @{ +*/ + +/** + * @brief CAN config structure definition + */ +typedef struct +{ + uint8_t timeTrigComMode; /*!< Enable or disable the time triggered communication mode */ + uint8_t autoBusOffManage; /*!< Enable or disable the automatic bus-off management */ + uint8_t autoWakeUpMode; /*!< Enable or disable the automatic wake-up mode */ + uint8_t nonAutoRetran; /*!< Enable or disable the non-automatic retransmission mode */ + uint8_t rxFIFOLockMode; /*!< Enable or disable the Receive FIFO Locked mode */ + uint32_t txFIFOPriority; /*!< Enable or disable the transmit FIFO priority */ + CAN_MODE_T mode; /*!< Specifies the CAN operating mode */ + CAN_SJW_T syncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. */ + CAN_TIME_SEGMENT1_T timeSegment1; /*!< Specifies the number of time quanta in Bit Segment 1 */ + CAN_TIME_SEGMENT2_T timeSegment2; /*!< Specifies the number of time quanta in Bit Segment 2 */ + uint16_t prescaler; /*!< Specifies the length of a time quantum. It can be 1 to 1024 */ +} CAN_Config_T; + +/** + * @brief CAN filter config structure definition + */ +typedef struct +{ + uint16_t filterIdHigh; /*!< Specifies the filter identification number. */ + uint16_t filterIdLow; /*!< Specifies the filter identification number. */ + uint16_t filterMaskIdHigh; /*!< Specifies the filter mask number or identification number. */ + uint16_t filterMaskIdLow; /*!< Specifies the filter mask number or identification number. */ + CAN_FIFO_T filterFIFO; /*!< Specifies the FIFO which will be assigned to the filter. */ + CAN_FILTER_NUMBER_T filterNumber; /*!< Specifies the filter which will be configured. It ranges from 0 to 13. */ + CAN_FILTER_MODE_T filterMode; /*!< Specifies the filter mode to be configured. */ + CAN_FILTER_SCALE_T filterScale; /*!< Specifies the filter scale. */ + uint8_t filterActivation; /*!< Enable or disable the filter. */ +} CAN_FilterConfig_T; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t stanID; /*!< Specifies the standard identifier. */ + uint32_t extenID; /*!< Specifies the extended identifier. */ + CAN_TYPEID_T typeID; /*!< Specifies the type of identifier for the message. */ + CAN_RTXR_T remoteTxReq; /*!< Specifies the type of frame for the message. */ + uint8_t dataLengthCode; /*!< Specifies the length of the frame. It can be a value between 0 to 8. */ + uint8_t data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CAN_Tx_Message; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t stanID; /*!< Specifies the standard identifier. */ + uint32_t extenID; /*!< Specifies the extended identifier. */ + CAN_TYPEID_T typeID; /*!< Specifies the type of identifier for the message. */ + CAN_RTXR_T remoteTxReq; /*!< Specifies the type of frame for the message. */ + uint8_t dataLengthCode; /*!< Specifies the length of the frame. It can be a value between 0 to 8. */ + uint8_t data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ + uint8_t filterMatchIndex; /*!< Specifies the index of the filter the message stored in the mailbox passes through. */ +} CAN_Rx_Message; + +/**@} end of group CAN_Structures */ + +/** @defgroup CAN_Variables Variables + @{ +*/ + +/**@} end of group CAN_Variables */ + +/** @defgroup CAN_Functions Functions + @{ +*/ + +/* CAN reset and configuration */ +void CAN_Reset(void); +uint8_t CAN_Config(CAN_Config_T* canConfig); +void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig); +void CAN_ConfigStructInit(CAN_Config_T* canConfig); +void CAN_StartBankSlave(uint8_t bankNumber); +void CAN_EnableDebugFreeze(void); +void CAN_DisableDebugFreeze(void); +void CAN_EnableTTComMode(void); +void CAN_DisableTTComMode(void); + +/* CAN frames transmission */ +uint8_t CAN_TxMessage(CAN_Tx_Message* TxMessage); +uint8_t CAN_TxMessageStatus(CAN_MAILBOX_T TxMailbox); +void CAN_CancelTx(CAN_MAILBOX_T TxMailbox); + +/* CAN frames reception */ +void CAN_RxMessage(uint8_t FIFONumber, CAN_Rx_Message* RxMessage); +void CAN_ReleaseFIFO(uint8_t FIFONumber); +uint8_t CAN_PendingMessage(uint8_t FIFONumber); + +/* CAN operation modes */ +uint8_t CAN_OperatingMode(CAN_OPERATING_MODE_T operatingMode); +uint8_t CAN_SleepMode(void); +uint8_t CAN_WakeUpMode(void); + +/* CAN bus error management */ +uint8_t CAN_ReadLastErrorCode(void); +uint8_t CAN_ReadRxErrorCounter(void); +uint8_t CAN_ReadLSBTxErrorCounter(void); + +/* CAN interrupt and flag */ +void CAN_EnableInterrupt(uint32_t interrupt); +void CAN_DisableInterrupt(uint32_t interrupt); +uint8_t CAN_ReadStatusFlag(CAN_FLAG_T CAN_FLAG); +void CAN_ClearStatusFlag(CAN_FLAG_T flag); +uint8_t CAN_ReadIntFlag(CAN_INT_T interrupt); +void CAN_ClearIntFlag(uint32_t interrupt); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F0XX_CAN_H */ + +/**@} end of group CAN_Functions */ +/**@} end of group CAN_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_cec.h b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_cec.h new file mode 100644 index 0000000000..3bf007d3f5 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_cec.h @@ -0,0 +1,231 @@ +/*! + * @file apm32f0xx_cec.h + * + * @brief This file contains all the functions prototypes for the CEC firmware library + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_CEC_H +#define __APM32F0XX_CEC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CEC_Driver + @{ +*/ + +/** @defgroup CEC_Macros Macros + @{ +*/ + +/**@} end of group CEC_Macros */ + +/** @defgroup CEC_Enumerations Enumerations + @{ +*/ + +/** + * @brief CEC_Signal_Free_Time + */ +typedef enum +{ + CEC_SINGANL_FREETIME_STANDARD = 0x00, /*!< none nominal data bit periods */ + CEC_SINGANL_FREETIME_1T = 0x01, /*!< 0.5 nominal data bit periods */ + CEC_SINGANL_FREETIME_2T = 0x02, /*!< 1.5 nominal data bit periods */ + CEC_SINGANL_FREETIME_3T = 0x03, /*!< 2.5 nominal data bit periods */ + CEC_SINGANL_FREETIME_4T = 0x04, /*!< 3.5 nominal data bit periods */ + CEC_SINGANL_FREETIME_5T = 0x05, /*!< 4.5 nominal data bit periods */ + CEC_SINGANL_FREETIME_6T = 0x06, /*!< 5.5 nominal data bit periods */ + CEC_SINGANL_FREETIME_7T = 0x07, /*!< 6.5 nominal data bit periods */ +} CEC_SIGNAL_FREETIME_T; + +/** + * @brief CEC_RxTolerance + */ +typedef enum +{ + CEC_RX_TOLERANCE_STANDARD = 0x00, /*!< Standard tolerance margin */ + CEC_RX_TOLERANCE_EXTENDED = 0x01 /*!< Extended Tolerance */ +} CEC_RX_TOLERANCE_T; + +/** + * @brief CEC_Stop_Reception + */ +typedef enum +{ + CEC_STOP_RECEPTION_OFF, /*!< CEC Stop Reception Off */ + CEC_STOP_RECEPTION_ON /*!< CEC Stop Reception On */ +} CEC_STOP_RECEPTION_T; + +/** + * @brief CEC_Bit_Rising_Error_Generation + */ +typedef enum +{ + CEC_BIT_RISING_ERR_OFF, /*!< BRE detection does not generate an Error-Bit on the CEC line */ + CEC_BIT_RISING_ERR_ON /*!< BRE detection generates an Error-Bit on the CEC line (if BRESTP is set) */ +} CEC_BIT_RISING_ERR_T; + +/** + * @brief CEC_Long_Bit_Error_Generation + */ +typedef enum +{ + CEC_LONG_PERIOD_ERR_OFF, /*!< LBPE detection does not generate an Error-Bit on the CEC line */ + CEC_LONG_PERIOD_ERR_ON /*!< LBPE detection generates an Error-Bit on the CEC line */ +} CEC_LONG_PERIOD_ERR_T; + +/** + * @brief CEC_BDR_No_Gen + */ +typedef enum +{ + CEC_BROADCAST_NO_ERR_OFF, /*!< Broadcast Bit Rising Error generation turned Off */ + CEC_BROADCAST_NO_ERR_ON /*!< Broadcast Bit Rising Error generation turned On */ +} CEC_BROADCAST_NO_ERR_T; + +/** + * @brief CEC_SFT_Option + */ +typedef enum +{ + CEC_SIGNAL_FREETIME_OPTION_OFF, /*!< SFTCFG timer starts when TXSOM is set by software */ + CEC_SIGNAL_FREETIME_OPTION_ON /*!< SFTCFG timer starts automatically at the end of message transmission/reception */ +} CEC_SIGNAL_FREETIME_OPTION_T; + +/** + * @brief CEC_Interrupt_Configuration_definition + */ +typedef enum +{ + CEC_INT_RXBR = ((uint32_t)0x00000001), /*!< Rx-Byte Received Interrupt */ + CEC_INT_RXEND = ((uint32_t)0x00000002), /*!< End Of Reception Interrupt */ + CEC_INT_RXOVR = ((uint32_t)0x00000004), /*!< Rx-Buffer Overrun Interrupt */ + CEC_INT_BRE = ((uint32_t)0x00000008), /*!< Bit Rising Error Interrupt */ + CEC_INT_SBPE = ((uint32_t)0x00000010), /*!< Short Bit Period Error Interrupt */ + CEC_INT_LBPE = ((uint32_t)0x00000020), /*!< Long Bit Period Error Interrupt */ + CEC_INT_RXACKE = ((uint32_t)0x00000040), /*!< Rx-Missing Acknowledge Error Interrupt */ + CEC_INT_ARBLST = ((uint32_t)0x00000080), /*!< Arbitration Lost Interrupt */ + CEC_INT_TXBR = ((uint32_t)0x00000100), /*!< Tx-Byte Request Interrupt */ + CEC_INT_TXEND = ((uint32_t)0x00000200), /*!< Tx-End Of Message Interrupt */ + CEC_INT_TXUDR = ((uint32_t)0x00000400), /*!< Tx-Underrun Interrupt */ + CEC_INT_TXERR = ((uint32_t)0x00000800), /*!< Tx-Error Interrupt */ + CEC_INT_TXACKE = ((uint32_t)0x00001000), /*!< Tx-Missing Acknowledge Error Interrupt */ +} CEC_INT_T; + +/** + * @brief CEC_STS_register_flags_definition + */ +typedef enum +{ + CEC_FLAG_RXBR = ((uint32_t)0x00000001), /*!< Rx-Byte Received Flag */ + CEC_FLAG_RXEND = ((uint32_t)0x00000002), /*!< End Of Reception Flag */ + CEC_FLAG_RXOVR = ((uint32_t)0x00000004), /*!< Rx-Buffer Overrun Flag */ + CEC_FLAG_BRE = ((uint32_t)0x00000008), /*!< Bit Rising Error Flag */ + CEC_FLAG_SBPE = ((uint32_t)0x00000010), /*!< Short Bit Period Error Flag */ + CEC_FLAG_LBPE = ((uint32_t)0x00000020), /*!< Long Bit Period Error Flag */ + CEC_FLAG_RXACKE = ((uint32_t)0x00000040), /*!< Rx-Missing Acknowledge Error Flag */ + CEC_FLAG_ARBLST = ((uint32_t)0x00000080), /*!< Arbitration Lost Flag */ + CEC_FLAG_TXBR = ((uint32_t)0x00000100), /*!< Tx-Byte Request Flag */ + CEC_FLAG_TXEND = ((uint32_t)0x00000200), /*!< Tx-End Of Message Flag */ + CEC_FLAG_TXUDR = ((uint32_t)0x00000400), /*!< Tx-Underrun Flag */ + CEC_FLAG_TXERR = ((uint32_t)0x00000800), /*!< Tx-Error Flag */ + CEC_FLAG_TXACKE = ((uint32_t)0x00001000), /*!< Tx-Missing Acknowledge Error Flag */ +} CEC_FLAG_T; + +/**@} end of group CEC_Enumerations */ + +/** @defgroup CEC_Structures Structures + @{ +*/ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + CEC_SIGNAL_FREETIME_T signalFreeTime; /*!< Signal Free Time */ + CEC_RX_TOLERANCE_T RxTolerance; /*!< Rx-Tolerance */ + CEC_STOP_RECEPTION_T stopReception; /*!< Rx-Stop on Bit Rising Error */ + CEC_BIT_RISING_ERR_T bitRisingError; /*!< Generate Error-Bit on Bit Rising Error */ + CEC_LONG_PERIOD_ERR_T longPeriodError; /*!< Generate Error-Bit on Long Bit Period Error */ + CEC_BROADCAST_NO_ERR_T broadcastrNoGen; /*!< Avoid Error-Bit Generation in Broadcast */ + CEC_SIGNAL_FREETIME_OPTION_T signalFreeTimeOption;/*!< Signal Free Time optional */ +} CEC_Config_T; + +/**@} end of group CEC_Structures */ + +/** @defgroup CEC_Variables Variables + @{ +*/ + +/**@} end of group CEC_Variables */ + +/** @defgroup CEC_Functions Functions + @{ +*/ + +/* CEC reset and configuration */ +void CEC_Reset(void); +void CEC_Config(CEC_Config_T* cecConfig); +void CEC_ConfigStructInit(CEC_Config_T* cecConfig); +void CEC_Enable(void); +void CEC_Disable(void); +void CEC_EnableListenMode(void); +void CEC_DisableListenMode(void); +void CEC_ConfigOwnAddress(uint8_t ownAddress); +void CEC_ClearQwnAddress(void); + +/* Transmit and receive */ +void CEC_TxData(uint8_t Data); +uint8_t CEC_RxData(void); + +/* Config Message */ +void CEC_StartNewMessage(void); +void CEC_CompleteMessage(void); + +/* Interrupt and Flag*/ +void CEC_EnableInterrupt(uint32_t interrupt); +void CEC_DisableInterrupt(uint32_t interrupt); +uint8_t CEC_ReadStatusFlag(uint32_t flag); +void CEC_ClearStatusFlag(uint32_t flag); +uint8_t CEC_ReadIntFlag(uint16_t flag); +void CEC_ClearIntFlag(uint16_t flag); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F0XX_CEC_H */ + +/**@} end of group CEC_Functions */ +/**@} end of group CEC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_comp.h b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_comp.h new file mode 100644 index 0000000000..e4aeff7b8b --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_comp.h @@ -0,0 +1,185 @@ +/*! + * @file apm32f0xx_comp.h + * + * @brief This file contains all the functions prototypes for the COMP firmware library + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_COMP_H +#define __APM32F0XX_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup COMP_Driver + @{ +*/ + +/** @defgroup COMP_Macros Macros + @{ +*/ + +/* Macros description */ +#define COMP_CSTS_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output state */ +#define COMP_CSTS_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output state */ +#define COMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00004000) /*!< COMP output level vaild high */ +#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< COMP output level vaild low */ + +/**@} end of group COMP_Macros */ + +/** @defgroup COMP_Enumerations Enumerations + @{ +*/ + +/** + * @brief COMP_Selection + */ +typedef enum +{ + COMP_SELECT_COMP1 = ((uint32_t)0x00000000), /*!< COMP1 */ + COMP_SELECT_COMP2 = ((uint32_t)0x00000010) /*!< COMP2 */ +} COMP_SELECT_T; + +/** + * @brief COMP_InvertingInput + */ +typedef enum +{ + COMP_INVERTING_INPUT_1_4VREFINT = 0x00, /*!< 1/4 of VREFINT */ + COMP_INVERTING_INPUT_1_2VREFINT = 0x01, /*!< 1/2 of VREFINT */ + COMP_INVERTING_INPUT_3_4VREFINT = 0x02, /*!< 3/4 of VREFINT */ + COMP_INVERTING_INPUT_VREFINT = 0x03, /*!< VREFINT */ + COMP_INVERTING_INPUT_DAC1 = 0x04, /*!< COMP1_INM4 (PA4 with DAC_OUT1 if enabled) */ + COMP_INVERTING_INPUT_DAC2 = 0x05, /*!< COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled, only for APM32F072 and APM32F091 devices) */ + COMP_INVERTING_INPUT_IO = 0x06, /*!< COMP1_INM6 (PA0) */ +} COMP_INVERTING_INPUT_T; + +/** + * @brief COMP_Output + */ +typedef enum +{ + COMP_OUTPUT_NONE = 0x00, /*!< no selection */ + COMP_OUTPUT_TIM1BKIN = 0x01, /*!< Timer 1 break input */ + COMP_OUTPUT_TIM1IC1 = 0x02, /*!< Timer 1 Input capture 1 */ + COMP_OUTPUT_TIM1OCREFCLR = 0x03, /*!< Timer 1 OCrefclear input */ + COMP_OUTPUT_TIM2IC4 = 0x04, /*!< Timer 2 input capture 4 */ + COMP_OUTPUT_TIM2OCREFCLR = 0x05, /*!< Timer 2 OCrefclear input */ + COMP_OUTPUT_TIM3IC1 = 0x06, /*!< Timer 3 input capture 1 */ + COMP_OUTPUT_TIM3OCREFCLR = 0x07, /*!< Timer 3 OCrefclear input */ +} COMP_OUTPUT_T; + +/** + * @brief COMP_OutputPolarity + */ +typedef enum +{ + COMP_OUTPUTPOL_NONINVERTED, /*!< output is not inverted */ + COMP_OUTPUTPOL_INVERTED /*!< output is inverted */ +} COMP_OUTPUTPOL_T; + +/** + * @brief COMP_Hysteresis + */ +typedef enum +{ + COMP_HYSTERRSIS_NO = 0x00, /*!< No hysteresis */ + COMP_HYSTERRSIS_LOW = 0x01, /*!< Low hysteresis */ + COMP_HYSTERRSIS_MEDIUM = 0x02, /*!< Medium hysteresis */ + COMP_HYSTERRSIS_HIGH = 0x03, /*!< High hysteresis */ +} COMP_HYSTERRSIS_T; + +/** + * @brief COMP_Mode + */ +typedef enum +{ + COMP_MODE_HIGHSPEED = 0x00, /*!< High speed / full power */ + COMP_MODE_MEDIUMSPEED = 0x01, /*!< Medium speed / medium power */ + COMP_MODE_LOWPOWER = 0x02, /*!< Low speed / low-power */ + COMP_MODE_VERYLOW = 0x03 /*!< Very-low speed / ultra-low power */ +} COMP_MODE_T; + +/**@} end of group COMP_Enumerations*/ + +/** @defgroup COMP_Structures Structures + @{ +*/ + +/** + * @brief OMP Config structure definition + */ +typedef struct +{ + COMP_INVERTING_INPUT_T invertingInput; /*!< Comparator inverting input selection */ + COMP_OUTPUT_T output; /*!< Comparator output selection */ + COMP_OUTPUTPOL_T outputPol; /*!< Comparator output polarity */ + COMP_HYSTERRSIS_T hysterrsis; /*!< Comparator hysteresis */ + COMP_MODE_T mode; /*!< Comparator mode */ +} COMP_Config_T; + +/**@} end of group COMP_Structures */ + +/** @defgroup COMP_Variables Variables + @{ + */ + +/**@} end of group COMP_Variables */ + +/** @defgroup COMP_Functions Functions + @{ +*/ + +/* COMP configuration */ +void COMP_Reset(void); +void COMP_Config(COMP_SELECT_T compSelect, COMP_Config_T* compConfig); +void COMP_ConfigStructInit(COMP_Config_T* compConfig); +void COMP_Enable(COMP_SELECT_T compSelect); +void COMP_Disable(COMP_SELECT_T compSelect); +void COMP_EnableSwitch(void); +void COMP_DisableSwitch(void); +uint32_t COMP_ReadOutPutLevel(COMP_SELECT_T compSelect); + +/* Window mode control */ +void COMP_EnableWindow(void); +void COMP_DisnableWindow(void); + +/* COMP configuration locking */ +void COMP_ConfigLOCK(COMP_SELECT_T compSelect); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F0XX_COMP_H */ + +/**@} end of group COMP_Functions */ +/**@} end of group COMP_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_crc.h b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_crc.h new file mode 100644 index 0000000000..deaa594a76 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_crc.h @@ -0,0 +1,136 @@ +/*! + * @file apm32f0xx_crc.h + * + * @brief This file contains all the functions prototypes for the CRC firmware library + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_CRC_H +#define __APM32F0XX_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CRC_Driver + @{ +*/ + +/** @defgroup CRC_Macros Macros + @{ +*/ + +/**@} end of group CRC_Macros */ + +/** @defgroup CRC_Enumerations Enumerations + @{ +*/ + +/** + * @brief CRC Reverse Input Data + */ +typedef enum +{ + CRC_REVERSE_INPUT_DATA_NO = ((uint8_t)0x00), /*!< Bit order not affected */ + CRC_REVERSE_INPUT_DATA_8B = ((uint8_t)0x01), /*!< Bit reversal done by byte */ + CRC_REVERSE_INPUT_DATA_16B = ((uint8_t)0x02), /*!< Bit reversal done by half-word */ + CRC_REVERSE_INPUT_DATA_32B = ((uint8_t)0x03), /*!< Bit reversal done by word */ +} CRC_REVERSE_INPUT_DATA_T; + +/** + * @brief CRC Polynomial Size + */ +typedef enum +{ + CRC_POLYNOMIAL_SIZE_7 = ((uint8_t)0x03), /*!< 7-bit polynomial for CRC calculation */ + CRC_POLYNOMIAL_SIZE_8 = ((uint8_t)0x02), /*!< 8-bit polynomial for CRC calculation */ + CRC_POLYNOMIAL_SIZE_16 = ((uint8_t)0x01), /*!< 16-bit polynomial for CRC calculation */ + CRC_POLYNOMIAL_SIZE_32 = ((uint8_t)0x00), /*!< 32-bit polynomial for CRC calculation */ +} CRC_POLYNOMIAL_SIZE_T; + +/**@} end of group CRC_Enumerations*/ + +/** @defgroup CRC_Structures Structures + @{ +*/ + +/**@} end of group CRC_Structures */ + +/** @defgroup CRC_Variables Variables + @{ +*/ + +/**@} end of group CRC_Variables */ + +/** @defgroup CRC_Functions Functions + @{ +*/ + +/* Reset CRC */ +void CRC_Reset(void); + +/* Reset DATA */ +void CRC_ResetDATA(void); + +/* CRC Polynomial Size */ +void CRC_SetPolynomialSize(CRC_POLYNOMIAL_SIZE_T polynomialSize); /*!< Only for APM32F072 and APM32F091 devices */ +void CRC_SetPolynomialValue(uint32_t polynomialValue); /*!< Only for APM32F072 and APM32F091 devices */ + +/* Performed on input data */ +void CRC_SelectReverseInputData(CRC_REVERSE_INPUT_DATA_T revInData); + +/* Enable and Disable Reverse Output Data */ +void CRC_EnableReverseOutputData(void); +void CRC_DisableReverseOutputData(void); + +/* Write INITVAL register */ +void CRC_WriteInitRegister(uint32_t initValue); + +/* Calculate CRC */ +uint32_t CRC_CalculateCRC(uint32_t data); +uint32_t CRC_CalculateCRC8bits(uint8_t data); /*!< Only for APM32F072 and APM32F091 devices */ +uint32_t CRC_CalculateCRC16bits(uint16_t data); /*!< Only for APM32F072 and APM32F091 devices */ +uint32_t CRC_CalculateBlockCRC(uint32_t pBuffer[], uint32_t bufferLength); + +/* Read CRC */ +uint32_t CRC_ReadCRC(void); + +/* Independent Data(ID) */ +void CRC_WriteIDRegister(uint8_t IDValue); +uint8_t CRC_ReadIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F0XX_CRC_H */ + +/**@} end of group CRC_Functions */ +/**@} end of group CRC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_crs.h b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_crs.h new file mode 100644 index 0000000000..4ec5f2804a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/inc/apm32f0xx_crs.h @@ -0,0 +1,171 @@ +/*! + * @file apm32f0xx_crs.h + * + * @brief This file contains all the functions prototypes for the CRS firmware library + * + * @note It's only for APM32F072 and APM32F091 devices + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_CRS_H +#define __APM32F0XX_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CRS_Driver + @{ +*/ + +/** @defgroup CRS_Macros Macros + @{ +*/ + +/**@} end of group CRS_Macros */ + +/** @defgroup CRS_Enumerations Enumerations + @{ +*/ + +/** + * @brief CRS_Interrupt_Sources + */ +typedef enum +{ + CRS_INT_SYNCOK = ((uint32_t)0x00000001), /*!CFG1_B.DATARESCFG = adcConfig->resolution; + ADC->CFG1_B.DALIGCFG = adcConfig->dataAlign; + ADC->CFG1_B.SCANSEQDIR = adcConfig->scanDir; + ADC->CFG1_B.CMODESEL = adcConfig->convMode; + ADC->CFG1_B.EXTPOLSEL = adcConfig->extTrigEdge; + ADC->CFG1_B.EXTTRGSEL = adcConfig->extTrigConv; +} + +/*! + * @brief Fills each adcConfig member with its default value + * + * @param adcConfig: Pointer to a ADC_Config_T structure which will be initialized + * + * @retval None + */ +void ADC_ConfigStructInit(ADC_Config_T* adcConfig) +{ + adcConfig->resolution = ADC_RESOLUTION_12B; + adcConfig->dataAlign = ADC_DATA_ALIGN_RIGHT; + adcConfig->scanDir = ADC_SCAN_DIR_UPWARD; + adcConfig->convMode = ADC_CONVERSION_SINGLE; + adcConfig->extTrigConv = ADC_EXT_TRIG_CONV_TRG0; + adcConfig->extTrigEdge = ADC_EXT_TRIG_EDGE_NONE; +} + +/*! + * @brief Enable the ADC peripheral + * + * @param None + * + * @retval None + */ +void ADC_Enable(void) +{ + ADC->CTRL_B.ADCEN = BIT_SET; +} + +/*! + * @brief Disable the ADC peripheral + * + * @param None + * + * @retval None + */ +void ADC_Disable(void) +{ + ADC->CTRL_B.ADCD = BIT_SET; +} + +/*! + * @brief Configure the ADC to either be clocked by the asynchronous clock + * + * @param clockmode: selects the ADC clock mode. + * The parameter can be one of following values: + * @arg ADC_CLOCK_MODE_ASYNCLK: ADC Asynchronous clock mode + * @arg ADC_CLOCK_MODE_SYNCLKDIV2: Synchronous clock mode divided by 2 + * @arg ADC_CLOCK_MODE_SYNCLKDIV4: Synchronous clock mode divided by 4 + * + * @retval None + */ +void ADC_ClockMode(ADC_CLOCK_MODE_T clockMode) +{ + ADC->CFG2_B.CLKCFG = (uint32_t)clockMode; +} + +/*! + * @brief Enables the jitter when the ADC is clocked by PCLK div2 or div4 + * + * @param jitter: They are replaced by PCLK div2 or div4 + * The parameter can be one of following values: + * @arg ADC_JITTER_PCLKDIV2: ADC clocked by PCLK div2 + * @arg ADC_JITTER_PCLKDIV4: ADC clocked by PCLK div4 + * + * @retval None + */ +void ADC_EnableJitter(ADC_JITTER_T jitter) +{ + ADC->CFG2_B.CLKCFG |= (uint32_t)jitter; +} + +/*! + * @brief Disables the jitter when the ADC is clocked by PCLK div2 or div4 + * + * @param jitter: They are replaced by PCLK div2 or div4 + * The parameter can be one of following values: + * @arg ADC_JITTER_PCLKDIV2: ADC clocked by PCLK div2 + * @arg ADC_JITTER_PCLKDIV4: ADC clocked by PCLK div4 + * @retval None + */ +void ADC_DisableJitter(ADC_JITTER_T jitter) +{ + ADC->CFG2_B.CLKCFG &= (uint32_t)~jitter; +} + +/*! + * @brief Enables the Auto Power Off mode + * + * @param None + * + * @retval None + */ +void ADC_EnableAutoPowerOff(void) +{ + ADC->CFG1_B.AOEN = BIT_SET; +} + +/*! + * @brief Disables the Auto Power Off mode + * + * @param None + * + * @retval None + */ +void ADC_DisableAutoPowerOff(void) +{ + ADC->CFG1_B.AOEN = BIT_RESET; +} + +/*! + * @brief Enables the Auto-delayed conversion mode + * + * @param None + * + * @retval None + */ +void ADC_EnableWaitMode(void) +{ + ADC->CFG1_B.WAITCEN = BIT_SET; +} + +/*! + * @brief Disables the Auto-delayed conversion mode + * + * @param None + * + * @retval None + */ +void ADC_DisableWaitMode(void) +{ + ADC->CFG1_B.WAITCEN = BIT_RESET; +} + +/*! + * @brief Enables the analog watchdog + * + * @param None + * + * @retval None + */ +void ADC_EnableAnalogWatchdog(void) +{ + ADC->CFG1_B.AWDEN = BIT_SET; +} + +/*! + * @brief Disables the analog watchdog + * + * @param None + * + * @retval None + */ +void ADC_DisableAnalogWatchdog(void) +{ + ADC->CFG1_B.AWDEN = BIT_RESET; +} + +/*! + * @brief The analog watchdog low threshold + * + * @param None + * + * @retval None + */ +void ADC_AnalogWatchdogLowThreshold(uint16_t lowThreshold) +{ + ADC->AWDT_B.AWDLT = (uint16_t)lowThreshold; +} + +/*! + * @brief The analog watchdog High threshold + * + * @param None + * + * @retval None + */ +void ADC_AnalogWatchdogHighThreshold(uint16_t highThreshold) +{ + ADC->AWDT_B.AWDHT = (uint16_t)highThreshold; +} + +/*! + * @brief Configures the analog watchdog guarded single channel + * + * @param channel: ADC analog watchdog channel selection + * The parameter can be one of following values: + * @arg ADC_ANALG_WDT_CHANNEL_0: AWD Channel 0 + * @arg ADC_ANALG_WDT_CHANNEL_1: AWD Channel 1 + * @arg ADC_ANALG_WDT_CHANNEL_2: AWD Channel 2 + * @arg ADC_ANALG_WDT_CHANNEL_3: AWD Channel 3 + * @arg ADC_ANALG_WDT_CHANNEL_4: AWD Channel 4 + * @arg ADC_ANALG_WDT_CHANNEL_5: AWD Channel 5 + * @arg ADC_ANALG_WDT_CHANNEL_6: AWD Channel 6 + * @arg ADC_ANALG_WDT_CHANNEL_7: AWD Channel 7 + * @arg ADC_ANALG_WDT_CHANNEL_8: AWD Channel 8 + * @arg ADC_ANALG_WDT_CHANNEL_9: AWD Channel 9 + * @arg ADC_ANALG_WDT_CHANNEL_10: AWD Channel 10 + * @arg ADC_ANALG_WDT_CHANNEL_11: AWD Channel 11 + * @arg ADC_ANALG_WDT_CHANNEL_12: AWD Channel 12 + * @arg ADC_ANALG_WDT_CHANNEL_13: AWD Channel 13 + * @arg ADC_ANALG_WDT_CHANNEL_14: AWD Channel 14 + * @arg ADC_ANALG_WDT_CHANNEL_15: AWD Channel 15 + * @arg ADC_ANALG_WDT_CHANNEL_16: AWD Channel 16 is TempSensor + * @arg ADC_ANALG_WDT_CHANNEL_17: AWD Channel 17 is Vrefint + * @arg ADC_ANALG_WDT_CHANNEL_18: AWD Channel 18 is Vbat, not available for APM32F030 devices + * + * @retval None + */ +void ADC_AnalogWatchdogSingleChannel(uint32_t channel) +{ + ADC->CFG1_B.AWDCHSEL = channel; +} + +/*! + * @brief Enables the Analog Watchdog Single Channel + * + * @param None + * + * @retval None + */ +void ADC_EnableAnalogWatchdogSingleChannel(void) +{ + ADC->CFG1_B.AWDCHEN = BIT_SET; +} + +/*! + * @brief Disables the Analog Watchdog Single Channel + * + * @param None + * + * @retval None + */ +void ADC_DisableAnalogWatchdogSingleChannel(void) +{ + ADC->CFG1_B.AWDCHEN = BIT_RESET; +} + +/*! + * @brief Enables the temperature sensor channel + * + * @param None + * + * @retval None + */ +void ADC_EnableTempSensor(void) +{ + ADC->CCFG_B.TSEN = BIT_SET; +} + +/*! + * @brief Disables the temperature sensor channel + * + * @param None + * + * @retval None + */ +void ADC_DisableTempSensor(void) +{ + ADC->CCFG_B.TSEN = BIT_RESET; +} + +/*! + * @brief Enables the vrefint channel + * + * @param None + * + * @retval None + */ +void ADC_EnableVrefint(void) +{ + ADC->CCFG_B.VREFEN = BIT_SET; +} + +/*! + * @brief Disables the vrefint channel + * + * @param None + * + * @retval None + */ +void ADC_DisableVrefint(void) +{ + ADC->CCFG_B.VREFEN = BIT_RESET; +} + +/*! + * @brief Enables the Vbat channel + * + * @param None + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void ADC_EnableVbat(void) +{ + ADC->CCFG_B.VBATEN = BIT_SET; +} + +/*! + * @brief Disables the Vbat channel + * + * @param None + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void ADC_DisableVbat(void) +{ + ADC->CCFG_B.VBATEN = BIT_RESET; +} + +/*! + * @brief Configures for the selected ADC channel and its sampling time + * + * @param channel: the ADC channel + * The parameter can be combination of following values: + * @arg ADC_CHANNEL_0: channel 0 + * @arg ADC_CHANNEL_1: channel 1 + * @arg ADC_CHANNEL_2: channel 2 + * @arg ADC_CHANNEL_3: channel 3 + * @arg ADC_CHANNEL_4: channel 4 + * @arg ADC_CHANNEL_5: channel 5 + * @arg ADC_CHANNEL_6: channel 6 + * @arg ADC_CHANNEL_7: channel 7 + * @arg ADC_CHANNEL_8: channel 8 + * @arg ADC_CHANNEL_9: channel 9 + * @arg ADC_CHANNEL_10: channel 10 + * @arg ADC_CHANNEL_11: channel 11 + * @arg ADC_CHANNEL_12: channel 12 + * @arg ADC_CHANNEL_13: channel 13 + * @arg ADC_CHANNEL_14: channel 14 + * @arg ADC_CHANNEL_15: channel 15 + * @arg ADC_CHANNEL_16: channel 16 is TempSensor + * @arg ADC_CHANNEL_17: channel 17 is Vrefint + * @arg ADC_CHANNEL_18: channel 18 is Vbat, not available for APM32F030 devices + * @param sampleTime: the ADC sampling time + * The parameter can be one of following values: + * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles + * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles + * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles + * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles + * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles + * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles + * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles + * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * + * @retval None + */ +void ADC_ConfigChannel(uint32_t channel, uint8_t sampleTime) +{ + ADC->CHSEL |= (uint32_t)channel; + + ADC->SMPTIM |= (uint8_t)sampleTime; +} + +/*! + * @brief Enables the continuous mode + * + * @param None + * + * @retval None + */ +void ADC_EnableContinuousMode(void) +{ + ADC->CFG1_B.CMODESEL = BIT_SET; +} + +/*! + * @brief Disables the continuous mode + * + * @param None + * + * @retval None + */ +void ADC_DisableContinuousMode(void) +{ + ADC->CFG1_B.CMODESEL = BIT_RESET; +} + +/*! + * @brief Enables the discontinuous mode + * + * @param None + * + * @retval None + */ +void ADC_EnableDiscMode(void) +{ + ADC->CFG1_B.DISCEN = BIT_SET; +} + +/*! + * @brief Disables the discontinuous mode + * + * @param None + * + * @retval None + */ +void ADC_DisableDiscMode(void) +{ + ADC->CFG1_B.DISCEN = BIT_RESET; +} + +/*! + * @brief Enables the Overrun mode + * + * @param None + * + * @retval None + */ +void ADC_EnableOverrunMode(void) +{ + ADC->CFG1_B.OVRMAG = BIT_SET; +} + +/*! + * @brief Disables the Overrun mode + * + * @param None + * + * @retval None + */ +void ADC_DisableOverrunMode(void) +{ + ADC->CFG1_B.OVRMAG = BIT_RESET; +} + +/*! + * @brief ADC Read Calibration Factor + * + * @param None + * + * @retval ADC Calibration factor + */ +uint32_t ADC_ReadCalibrationFactor(void) +{ + uint32_t temp = 0, counter = 0, status = 0; + + ADC->CTRL_B.CAL = BIT_SET; + + do + { + status = ADC->CTRL_B.CAL; + counter++; + } + while ((counter != CALIBRATION_TIMEOUT) && (status != 0x00)); + + if ((uint32_t)(ADC->CTRL_B.CAL) == RESET) + { + temp = ADC->DATA; + } + else + { + temp = 0x00000000; + } + + return temp; +} + +/*! + * @brief ADC stop conversion command + * + * @param None + * + * @retval None + */ +void ADC_StopConversion(void) +{ + ADC->CTRL_B.STOPCEN = BIT_SET; +} + +/*! + * @brief ADC start conversion command + * + * @param None + * + * @retval None + */ +void ADC_StartConversion(void) +{ + ADC->CTRL_B.STARTCEN = BIT_SET; +} + +/*! + * @brief Returns the last ADC conversion result data + * + * @param None + * + * @retval The Data conversion value + */ +uint16_t ADC_ReadConversionValue(void) +{ + return ((uint16_t)ADC->DATA); +} + +/*! + * @brief Enables the ADC DMA request + * + * @param None + * + * @retval None + */ +void ADC_EnableDMA(void) +{ + ADC->CFG1_B.DMAEN = BIT_SET; +} + +/*! + * @brief Disables the ADC DMA request + * + * @param None + * + * @retval None + */ +void ADC_DisableDMA(void) +{ + ADC->CFG1_B.DMAEN = BIT_RESET; +} + +/*! + * @brief ADC DMA Request Mode + * + * @param DMARequestMode: Direct memery access configuration . + * The parameter can be one of following values: + * @arg ADC_DMA_MODE_ONESHOUT: ADC DMA Mode Select one shot + * @arg ADC_DMA_MODE_CIRCULAR: ADC DMA Mode Select circular + * + * @retval None + */ +void ADC_DMARequestMode(ADC_DMA_MODE_T DMARequestMode) +{ + ADC->CFG1_B.DMACFG = (uint8_t)DMARequestMode; +} + +/*! + * @brief Enables the specified interrupts + * + * @param interrupt: Specifies the ADC interrupts sources + * The parameter can be combination of following values: + * @arg ADC_INT_ADRDY: ADC ready interrupt + * @arg ADC_INT_CSMP: End of sampling interrupt + * @arg ADC_INT_CC: End of conversion interrupt + * @arg ADC_INT_CS: End of sequence interrupt + * @arg ADC_INT_OVR: ADC overrun interrupt + * @arg ADC_INT_AWD: Analog watchdog interrupt + * + * @retval None + */ +void ADC_EnableInterrupt(uint8_t interrupt) +{ + ADC->INT |= (uint32_t)interrupt; +} + +/*! + * @brief Disable the specified interrupts + * + * @param interrupt: Specifies the ADC interrupts sources + * The parameter can be combination of following values: + * @arg ADC_INT_ADRDY: ADC ready interrupt + * @arg ADC_INT_CSMP: End of sampling interrupt + * @arg ADC_INT_CC: End of conversion interrupt + * @arg ADC_INT_CS: End of sequence interrupt + * @arg ADC_INT_OVR: ADC overrun interrupt + * @arg ADC_INT_AWD: Analog watchdog interrupt + * + * @retval None + */ +void ADC_DisableInterrupt(uint8_t interrupt) +{ + ADC->INT &= (uint32_t)~interrupt; +} + +/*! + * @brief Checks whether the specified ADC flag is set or not + * + * @param flag: Specifies the flag to check + * This parameter can be one of the following values: + * @arg ADC_FLAG_ADCON: ADC enable flag + * @arg ADC_FLAG_ADCOFF: ADC disable flag + * @arg ADC_FLAG_ADCSTA: ADC start conversion flag + * @arg ADC_FLAG_ADCSTOP: ADC stop conversion flag + * @arg ADC_FLAG_ADCCAL: ADC calibration flag + * @arg ADC_FLAG_ADRDY: ADC ready flag + * @arg ADC_FLAG_CSMP: End of sampling flag + * @arg ADC_FLAG_CC: End of conversion flag + * @arg ADC_FLAG_CS: End of sequence flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_AWD: Analog watchdog flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t ADC_ReadStatusFlag(ADC_FLAG_T flag) +{ + uint32_t status; + + if ((uint32_t)(flag & 0x01000000)) + { + status = ADC->CTRL & 0xFEFFFFFF; + } + else + { + status = ADC->STS; + } + + if ((status & flag) != (uint32_t)RESET) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear the specified ADC flag + * + * @param flag: Specifies the flag to check + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_ADRDY: ADC ready flag + * @arg ADC_FLAG_CSMP: End of sampling flag + * @arg ADC_FLAG_CC: End of conversion flag + * @arg ADC_FLAG_CS: End of sequence flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_AWD: Analog watchdog flag + * + * @retval None + */ +void ADC_ClearStatusFlag(uint32_t flag) +{ + ADC->STS = (uint32_t)flag; +} + +/*! + * @brief Checks whether the specified interrupt has occurred or not + * + * @param flag: Specifies the ADC interrupt pending bit to check + * The parameter can be one of following values: + * @arg ADC_INT_FLAG_ADRDY: ADC ready interrupt + * @arg ADC_INT_FLAG_CSMP: End of sampling interrupt + * @arg ADC_INT_FLAG_CC: End of conversion interrupt + * @arg ADC_INT_FLAG_CS: End of sequence interrupt + * @arg ADC_INT_FLAG_OVR: ADC overrun interrupt + * @arg ADC_INT_FLAG_AWD: Analog watchdog interrupt + * + * @retval None + */ +uint8_t ADC_ReadIntFlag(ADC_INT_FLAG_T flag) +{ + uint8_t intEnable; + uint8_t intStatus; + + intEnable = (uint8_t)(ADC->INT& (uint32_t)flag); + + intStatus = (uint8_t)(ADC->STS & (uint32_t)(flag & 0xff)); + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the specified interrupt pending bits + * + * @param flag: Specifies the ADC interrupt pending bit to check + * The parameter can be combination of following values: + * @arg ADC_INT_FLAG_ADRDY: ADC ready interrupt + * @arg ADC_INT_FLAG_CSMP: End of sampling interrupt + * @arg ADC_INT_FLAG_CC: End of conversion interrupt + * @arg ADC_INT_FLAG_CS: End of sequence interrupt + * @arg ADC_INT_FLAG_OVR: ADC overrun interrupt + * @arg ADC_INT_FLAG_AWD: Analog watchdog interrupt + * + * @retval None + */ + +void ADC_ClearIntFlag(uint32_t flag) +{ + ADC->STS = flag; +} + +/**@} end of group ADC_Functions */ +/**@} end of group ADC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_can.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_can.c new file mode 100644 index 0000000000..f108be7c7e --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_can.c @@ -0,0 +1,1170 @@ +/*! + * @file apm32f0xx_can.c + * + * @brief This file contains all the functions for the CAN peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* include */ +#include "apm32f0xx_can.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CAN_Driver + @{ +*/ + +/** @defgroup CAN_Macros Macros + @{ +*/ + +/**@} end of group CAN_Macros */ + +/** @defgroup CAN_Enumerations Enumerations + @{ +*/ + +/**@} end of group CAN_Enumerations */ + +/** @defgroup CAN_Structures Structures + @{ +*/ + +/**@} end of group CAN_Structures */ + +/** @defgroup CAN_Variables Variables + @{ +*/ + +/**@} end of group CAN_Variables */ + +/** @defgroup CAN_Functions Functions + @{ +*/ + +/*! + * @brief Reset CAN peripheral registers to their default values. + * + * @param None + * + * @retval None + * + */ +void CAN_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN); +} + +/*! + * @brief Congfig the CAN peripheral using the specified parameters in the canConfig. + * + * @param canConfig : pointer to a CAN_Config_T structure that contains + * the configuration information for the CAN peripheral. + * + * @retval Configuration status (SET or RESET) + */ +uint8_t CAN_Config(CAN_Config_T* canConfig) +{ + uint8_t InitStatus = RESET; + uint32_t ackWait = 0x00000000; + + CAN->MCTRL_B.SLEEPREQ = BIT_RESET; + + CAN->MCTRL_B.INITREQ = BIT_SET; + + while ((CAN->MSTS_B.INITFLG != BIT_SET) && (ackWait != (uint32_t)0x00FFFFFF)) + { + ackWait++; + } + + if (CAN->MSTS_B.INITFLG != BIT_SET) + { + InitStatus = RESET; + } + else + { + if (canConfig->timeTrigComMode == ENABLE) + { + CAN->MCTRL_B.TTCM = BIT_SET; + } + else + { + CAN->MCTRL_B.TTCM = BIT_RESET; + } + + if (canConfig->autoBusOffManage == ENABLE) + { + CAN->MCTRL_B.ALBOFFM = BIT_SET; + } + else + { + CAN->MCTRL_B.ALBOFFM = BIT_RESET; + } + + if (canConfig->autoWakeUpMode == ENABLE) + { + CAN->MCTRL_B.AWUPCFG = BIT_SET; + } + else + { + CAN->MCTRL_B.AWUPCFG = BIT_RESET; + } + + if (canConfig->nonAutoRetran == ENABLE) + { + CAN->MCTRL_B.ARTXMD = BIT_SET; + } + else + { + CAN->MCTRL_B.ARTXMD = BIT_RESET; + } + + if (canConfig->rxFIFOLockMode == ENABLE) + { + CAN->MCTRL_B.RXFLOCK = BIT_SET; + } + else + { + CAN->MCTRL_B.RXFLOCK = BIT_RESET; + } + + if (canConfig->txFIFOPriority == ENABLE) + { + CAN->MCTRL_B.TXFPCFG = BIT_SET; + } + else + { + CAN->MCTRL_B.TXFPCFG = BIT_RESET; + } + + CAN->BITTIM = (uint32_t)canConfig->mode << 30; + CAN->BITTIM_B.RSYNJW = canConfig->syncJumpWidth; + CAN->BITTIM_B.TIMSEG1 = canConfig->timeSegment1; + CAN->BITTIM_B.TIMSEG2 = canConfig->timeSegment2; + CAN->BITTIM_B.BRPSC = canConfig->prescaler - 1; + + CAN->MCTRL_B.INITREQ = BIT_RESET; + + ackWait = 0x00000000; + + while ((CAN->MSTS_B.INITFLG == BIT_SET) && (ackWait != (uint32_t)0x00FFFFFF)) + { + ackWait++; + } + + if (CAN->MSTS_B.INITFLG == BIT_RESET) + { + InitStatus = SET; + } + else + { + InitStatus = RESET; + } + } + return InitStatus; +} + +/*! + * @brief Congfig the CAN filter according to the specified parameters in the filterConfig. + * + * @param filterConfig: pointer to a CAN_Filter_Config_T structure that + * contains the configuration information. + * + * @retval None + */ +void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig) +{ + uint16_t filterNumber = 0; + + filterNumber = BIT0 << filterConfig->filterNumber; + + CAN->FCTRL_B.FIM = BIT_SET; + + CAN->FACT &= ~filterNumber; + + if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) + { + CAN->FSCFG &= ~filterNumber; + + CAN->sFilterRegister[filterConfig->filterNumber].R1 = + ((0x0000FFFF & filterConfig->filterMaskIdLow) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + CAN->sFilterRegister[filterConfig->filterNumber].R2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdHigh); + } + + if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT) + { + CAN->FSCFG |= filterNumber; + + CAN->sFilterRegister[filterConfig->filterNumber].R1 = + ((0x0000FFFF & filterConfig->filterIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + CAN->sFilterRegister[filterConfig->filterNumber].R2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterMaskIdLow); + } + + if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) + { + CAN->FMCFG &= ~filterNumber; + } + else + { + CAN->FMCFG |= filterNumber; + } + + if (filterConfig->filterFIFO == CAN_FIFO_0) + { + CAN->FFASS &= ~filterNumber; + } + else + { + CAN->FFASS |= filterNumber; + } + + if (filterConfig->filterActivation == ENABLE) + { + CAN->FACT |= filterNumber; + } + + CAN->FCTRL_B.FIM = BIT_RESET; +} + +/*! + * @brief Fills each canConfig member with its default value. + * + * @param canConfig : Pointer to a CAN_Config_T structure which is used for configuration. + * + * @retval None + */ +void CAN_ConfigStructInit(CAN_Config_T* canConfig) +{ + canConfig->timeTrigComMode = DISABLE; + + canConfig->autoBusOffManage = DISABLE; + + canConfig->autoWakeUpMode = DISABLE; + + canConfig->nonAutoRetran = DISABLE; + + canConfig->rxFIFOLockMode = DISABLE; + + canConfig->txFIFOPriority = DISABLE; + + canConfig->mode = CAN_MODE_NORMAL; + + canConfig->syncJumpWidth = CAN_SJW_1; + + canConfig->timeSegment1 = CAN_TIME_SEGMENT1_4; + + canConfig->timeSegment2 = CAN_TIME_SEGMENT2_3; + + canConfig->prescaler = 1; +} + +/*! + * @brief Select the start bank filter for slave CAN. + * + * @param bankNumber:Select the start slave bank filter from 1 to 27. + * + * @retval None + * + * @note This function applies only to APM32 Connectivity line devices. + */ +void CAN_StartBankSlave(uint8_t bankNumber) +{ + CAN->FCTRL_B.FIM = BIT_SET; + + CAN->FCTRL &= 0xFFFFC0F1; + CAN->FCTRL |= (uint32_t)(bankNumber) << 8; + + CAN->FCTRL_B.FIM = BIT_RESET; +} + +/*! + * @brief Enable the Debug Freeze mdoe for CAN. + * + * @param None + * + * @retval None + */ +void CAN_EnableDebugFreeze(void) +{ + CAN->MCTRL_B.DBGFRZE = BIT_SET; +} + +/*! + * @brief Disable the Debug Freeze mode for CAN. + * + * @param None + * + * @retval None + */ +void CAN_DisableDebugFreeze(void) +{ + CAN->MCTRL_B.DBGFRZE = BIT_RESET; +} + +/*! + * @brief Enables the Time Triggered Communication mode for CAN. + * + * @param None + * + * @retval None + */ +void CAN_EnableTTComMode(void) +{ + CAN->MCTRL_B.TTCM = BIT_SET; + + CAN->sTxMailBox[0].TXDLEN_B.TXGT = BIT_SET; + CAN->sTxMailBox[1].TXDLEN_B.TXGT = BIT_SET; + CAN->sTxMailBox[2].TXDLEN_B.TXGT = BIT_SET; +} + +/*! + * @brief Disables the Time Triggered Communication mode for CAN. + * + * @param None + * + * @retval None + */ +void CAN_DisableTTComMode(void) +{ + CAN->MCTRL_B.TTCM = BIT_RESET; + + CAN->sTxMailBox[0].TXDLEN_B.TXGT = BIT_RESET; + CAN->sTxMailBox[1].TXDLEN_B.TXGT = BIT_RESET; + CAN->sTxMailBox[2].TXDLEN_B.TXGT = BIT_RESET; +} + +/*! + * @brief Transmit a message from TxMessage of CAN_Tx_Message structure. + * + * @param TxMessage : Pointer to a structure which contains CAN Id, CAN DLCODE and CAN data. + * + * @retval Returns the number of the transmit mailbox state.It can be one of value: + * @arg 0: Transmit mailbox 0 + * @arg 1: Transmit mailbox 1 + * @arg 2: Transmit mailbox 2 + * @arg 4: There is no empty mailbox + */ +uint8_t CAN_TxMessage(CAN_Tx_Message* TxMessage) +{ + uint8_t TxMailbox = 0; + + if ((CAN->TXSTS_B.TXMEFLG0 == BIT_SET)) + { + TxMailbox = 0; + } + else if ((CAN->TXSTS_B.TXMEFLG1 == BIT_SET)) + { + TxMailbox = 1; + } + else if ((CAN->TXSTS_B.TXMEFLG2 == BIT_SET)) + { + TxMailbox = 2; + } + else + { + TxMailbox = CAN_TX_MAILBOX_FULL; + } + + if (TxMailbox != CAN_TX_MAILBOX_FULL) + { + /* Set up the Id */ + CAN->sTxMailBox[TxMailbox].TXMID &= BIT0; + if (TxMessage->typeID == CAN_TYPEID_STD) + { + CAN->sTxMailBox[TxMailbox].TXMID |= (((uint32_t)TxMessage->stanID << 21) | \ + TxMessage->typeID | \ + TxMessage->remoteTxReq); + } + else + { + CAN->sTxMailBox[TxMailbox].TXMID |= (((uint32_t)TxMessage->extenID << 3) | \ + TxMessage->typeID | \ + TxMessage->remoteTxReq); + } + + /* Set up the DLCODE */ + CAN->sTxMailBox[TxMailbox].TXDLEN_B.DLCODE = (TxMessage->dataLengthCode & 0x0F); + + /* Set up the data field */ + CAN->sTxMailBox[TxMailbox].TXMDH_B.DATABYTE7 = TxMessage->data[7]; + CAN->sTxMailBox[TxMailbox].TXMDH_B.DATABYTE6 = TxMessage->data[6]; + CAN->sTxMailBox[TxMailbox].TXMDH_B.DATABYTE5 = TxMessage->data[5]; + CAN->sTxMailBox[TxMailbox].TXMDH_B.DATABYTE4 = TxMessage->data[4]; + + CAN->sTxMailBox[TxMailbox].TXMDL_B.DATABYTE3 = TxMessage->data[3]; + CAN->sTxMailBox[TxMailbox].TXMDL_B.DATABYTE2 = TxMessage->data[2]; + CAN->sTxMailBox[TxMailbox].TXMDL_B.DATABYTE1 = TxMessage->data[1]; + CAN->sTxMailBox[TxMailbox].TXMDL_B.DATABYTE0 = TxMessage->data[0]; + + /* Request transmission */ + CAN->sTxMailBox[TxMailbox].TXMID |= BIT0; + } + + return TxMailbox; +} + +/*! + * @brief Reads the status of a transmission. + * + * @param TxMailbox: the number of the mailbox + * This parameter can be one of the following values: + * @arg CAN_MAILBOX_0 : Transmit mailbox 0 + * @arg CAN_MAILBOX_1 : Transmit mailbox 1 + * @arg CAN_MAILBOX_2 : Transmit mailbox 2 + * + * @retval Returns the transmission state. + * It can be one of the following values: + * @arg CAN_TX_FAILED + * @arg CAN_TX_OK + * @arg CAN_TX_WAITING + */ +uint8_t CAN_TxMessageStatus(CAN_MAILBOX_T TxMailbox) +{ + uint8_t state = CAN_TX_FAILED; + + switch (TxMailbox) + { + case (CAN_MAILBOX_0): + if (CAN->TXSTS_B.REQCFLG0 && CAN->TXSTS_B.TXSUSFLG0 && CAN->TXSTS_B.TXMEFLG0) + { + state = CAN_TX_OK; + } + else if (!(CAN->TXSTS_B.REQCFLG0 || CAN->TXSTS_B.TXSUSFLG0 || CAN->TXSTS_B.TXMEFLG0)) + { + state = CAN_TX_WAITING; + } + break; + + case (CAN_MAILBOX_1): + if (CAN->TXSTS_B.REQCFLG1 && CAN->TXSTS_B.TXSUSFLG1 && CAN->TXSTS_B.TXMEFLG1) + { + state = CAN_TX_OK; + } + else if (!(CAN->TXSTS_B.REQCFLG1 || CAN->TXSTS_B.TXSUSFLG1 || CAN->TXSTS_B.TXMEFLG1)) + { + state = CAN_TX_WAITING; + } + break; + + case (CAN_MAILBOX_2): + if (CAN->TXSTS_B.REQCFLG2 && CAN->TXSTS_B.TXSUSFLG2 && CAN->TXSTS_B.TXMEFLG2) + { + state = CAN_TX_OK; + } + else if (!(CAN->TXSTS_B.REQCFLG2 || CAN->TXSTS_B.TXSUSFLG2 || CAN->TXSTS_B.TXMEFLG2)) + { + state = CAN_TX_WAITING; + } + break; + + default: + break; + } + + return state; +} + +/*! + * @brief Cancels a transmit request. + * + * @param TxMailbox: the number of the mailbox + * This parameter can be one of the following values: + * @arg CAN_MAILBOX_0 : Abort transmission request for mailbox 0 + * @arg CAN_MAILBOX_1 : Abort transmission request for mailbox 1 + * @arg CAN_MAILBOX_2 : Abort transmission request for mailbox 2 + * + * @retval None + */ +void CAN_CancelTx(CAN_MAILBOX_T TxMailbox) +{ + switch (TxMailbox) + { + case 0: + CAN->TXSTS_B.ABREQFLG0 = BIT_SET; + break; + + case 1: + CAN->TXSTS_B.ABREQFLG1 = BIT_SET; + break; + + case 2: + CAN->TXSTS_B.ABREQFLG2 = BIT_SET; + break; + + default: + break; + } +} + +/*! + * @brief Receive a valid message through the filter. + * + * @param FIFONumber: The number of Receive FIFO + * This parameter can be one of the following values: + * @arg CAN_FIFO_0 : CAN FIFO 0 used to receive + * @arg CAN_FIFO_1 : CAN FIFO 1 used to receive + * + * @param RxMessage : pointer to a structure that is used to receive message + * + * @retval None + */ +void CAN_RxMessage(uint8_t FIFONumber, CAN_Rx_Message* RxMessage) +{ + RxMessage->typeID = (CAN_TYPEID_T)(BIT2 & CAN->sRxFIFO[FIFONumber].RXMID); + + if (RxMessage->typeID == CAN_TYPEID_STD) + { + RxMessage->stanID = CAN->sRxFIFO[FIFONumber].RXMID_B.STDID; + } + else + { + RxMessage->extenID = (CAN->sRxFIFO[FIFONumber].RXMID_B.STDID << 18); + RxMessage->extenID |= CAN->sRxFIFO[FIFONumber].RXMID_B.EXTID; + } + + RxMessage->remoteTxReq = (CAN_RTXR_T)(BIT1 & CAN->sRxFIFO[FIFONumber].RXMID); + RxMessage->dataLengthCode = CAN->sRxFIFO[FIFONumber].RXDLEN_B.DLCODE; + RxMessage->filterMatchIndex = CAN->sRxFIFO[FIFONumber].RXDLEN_B.FMIDX; + + RxMessage->data[7] = CAN->sRxFIFO[FIFONumber].RXMDH_B.DATABYTE7; + RxMessage->data[6] = CAN->sRxFIFO[FIFONumber].RXMDH_B.DATABYTE6; + RxMessage->data[5] = CAN->sRxFIFO[FIFONumber].RXMDH_B.DATABYTE5; + RxMessage->data[4] = CAN->sRxFIFO[FIFONumber].RXMDH_B.DATABYTE4; + + RxMessage->data[3] = CAN->sRxFIFO[FIFONumber].RXMDL_B.DATABYTE3; + RxMessage->data[2] = CAN->sRxFIFO[FIFONumber].RXMDL_B.DATABYTE2; + RxMessage->data[1] = CAN->sRxFIFO[FIFONumber].RXMDL_B.DATABYTE1; + RxMessage->data[0] = CAN->sRxFIFO[FIFONumber].RXMDL_B.DATABYTE0; + + if (FIFONumber == CAN_FIFO_0) + { + CAN->RXF0_B.RFOM0 = BIT_SET; + } + else + { + CAN->RXF1_B.RFOM1 = BIT_SET; + } +} + +/*! + * @brief Releases the specified receive FIFO. + * + * @param FIFONumber : the number of receive FIFO + * This parameter can be one of the following values: + * @arg CAN_FIFO_0 : CAN FIFO 0 used to receive + * @arg CAN_FIFO_1 : CAN FIFO 1 used to receive + * + * @retval None + */ +void CAN_ReleaseFIFO(uint8_t FIFONumber) +{ + if (FIFONumber == CAN_FIFO_0) + { + CAN->RXF0_B.RFOM0 = BIT_SET; + } + else + { + CAN->RXF1_B.RFOM1 = BIT_SET; + } +} + +/*! + * @brief Reads the number of pending messages. + * + * @param FIFONumber : the number of receive FIFO + * This parameter can be one of the following values: + * @arg CAN_FIFO_0 : CAN FIFO 0 used to receive + * @arg CAN_FIFO_1 : CAN FIFO 1 used to receive + * + * @retval which is the number of pending message. + */ +uint8_t CAN_PendingMessage(uint8_t FIFONumber) +{ + if (FIFONumber == CAN_FIFO_0) + { + return CAN->RXF0_B.FMNUM0; + } + else + { + return CAN->RXF1_B.FMNUM1; + } +} + +/*! + * @brief Select the CAN Operation mode. + * + * @param operatingMode: CAN Operating Mode + * This parameter can be one of the following values: + * @arg CAN_OPERATING_MODE_INIT : Initialization mode + * @arg CAN_OPERATING_MODE_NORMAL: Normal mode + * @arg CAN_OPERATING_MODE_SLEEP : sleep mode + * + * @retval status: 0 : CAN failed entering the specific mode + * 1 : CAN Succeed entering the specific mode + */ +uint8_t CAN_OperatingMode(CAN_OPERATING_MODE_T operatingMode) +{ + uint8_t status = RESET; + uint32_t timeout = 0x00FFFFFF; + uint8_t sleepflg, initfig; + + sleepflg = CAN->MSTS_B.SLEEPFLG; + initfig = CAN->MSTS_B.INITFLG; + + switch ((uint8_t)operatingMode) + { + case CAN_OPERATING_MODE_INIT: + CAN->MCTRL_B.SLEEPREQ = BIT_RESET; + CAN->MCTRL_B.INITREQ = BIT_SET; + + while ((sleepflg | !initfig) && (timeout != 0)) + { + sleepflg = CAN->MSTS_B.SLEEPFLG; + initfig = CAN->MSTS_B.INITFLG; + timeout--; + } + + if (sleepflg | !initfig) + { + status = RESET; + } + else + { + status = SET; + } + break; + + case CAN_OPERATING_MODE_NORMAL: + + CAN->MCTRL_B.INITREQ = BIT_RESET; + CAN->MCTRL_B.SLEEPREQ = BIT_RESET; + + while ((sleepflg | initfig) && (timeout != 0)) + { + sleepflg = CAN->MSTS_B.SLEEPFLG; + initfig = CAN->MSTS_B.INITFLG; + timeout--; + } + + if (sleepflg | initfig) + { + status = RESET; + } + else + { + status = SET; + } + break; + + case CAN_OPERATING_MODE_SLEEP: + CAN->MCTRL_B.INITREQ = BIT_RESET; + CAN->MCTRL_B.SLEEPREQ = BIT_SET; + + while ((!sleepflg | initfig) && (timeout != 0)) + { + sleepflg = CAN->MSTS_B.SLEEPFLG; + initfig = CAN->MSTS_B.INITFLG; + timeout--; + } + + if (!sleepflg | initfig) + { + status = RESET; + } + else + { + status = SET; + } + break; + + default: + status = RESET; + break; + } + + return status; +} + +/*! + * @brief Enters the sleep mode. + * + * @param None + * + * @retval status: 0 : Into sleep fail + * 1 : Into sleep success + */ +uint8_t CAN_SleepMode(void) +{ + CAN_SLEEP_T sleepstatus = CAN_SLEEP_FAILED; + + CAN->MCTRL_B.INITREQ = BIT_RESET; + CAN->MCTRL_B.SLEEPREQ = BIT_SET; + + if ((CAN->MSTS_B.SLEEPFLG == BIT_SET) && (CAN->MSTS_B.INITFLG == BIT_RESET)) + { + sleepstatus = CAN_SLEEP_OK; + } + + return (uint8_t)sleepstatus; +} + +/*! + * @brief Wakes up the CAN from sleep mode. + * + * @param None + * + * @retval status: 0 : WakeUp CAN fail + * 1 : WakeUp CAN success + */ +uint8_t CAN_WakeUpMode(void) +{ + uint32_t slakWait = 0x00FFFFFF; + CAN_WUP_T wakeupstatus = CAN_WAKEUP_FAILED; + + CAN->MCTRL_B.SLEEPREQ = BIT_RESET; + + while ((CAN->MSTS_B.SLEEPFLG == BIT_SET) && (slakWait != 0x00)) + { + slakWait--; + } + if (CAN->MSTS_B.SLEEPFLG != BIT_SET) + { + wakeupstatus = CAN_WAKEUP_OK; + } + return (uint8_t)wakeupstatus; +} + +/*! + * @brief Read the last error code of CAN. + * + * @param None + * + * @retval CAN_ErrorCode + */ +uint8_t CAN_ReadLastErrorCode(void) +{ + uint8_t errorcode = 0; + errorcode = CAN->ERRSTS_B.LERRC; + return errorcode; +} + +/*! + * @brief Read the Receive Error Counter of CAN. + * + * @param None + * + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_ReadRxErrorCounter(void) +{ + uint8_t counter = 0; + counter = CAN->ERRSTS_B.RXERRCNT; + return counter; +} + +/*! + * @brief Reads the Least significant byte of the 9-bit CAN Transmit Error Counter. + * + * @param None + * + * @retval Least significant byte of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_ReadLSBTxErrorCounter(void) +{ + uint8_t counter = 0; + counter = CAN->ERRSTS_B.TXERRCNT; + return counter; +} + +/*! + * @brief Enables the specified CAN interrupts. + * + * @param interrupt: Selects the CAN interrupt sources to be enabled. + * The parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FUL: FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR: FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FUL: FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR: FIFO 1 overrun Interrupt + * @arg CAN_INT_EWIE : Error warning Interrupt + * @arg CAN_INT_EPIE : Error passive Interrupt + * @arg CAN_INT_BOIE : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLE : Sleep acknowledge Interrupt + * + * @retval None + */ +void CAN_EnableInterrupt(uint32_t interrupt) +{ + CAN->INTEN |= interrupt; +} + +/*! + * @brief Disables the specified CAN interrupts. + * + * @param interrupt: Selects the CAN interrupt sources to be disabled. + * The parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FUL: FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR: FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FUL: FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR: FIFO 1 overrun Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLE : Sleep acknowledge Interrupt + * @arg CAN_INT_EWIE : Error warning Interrupt + * @arg CAN_INT_EPIE : Error passive Interrupt + * @arg CAN_INT_BOIE : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * + * @retval None + */ +void CAN_DisableInterrupt(uint32_t interrupt) +{ + CAN->INTEN &= ~interrupt; +} + +/*! + * @brief Reads the specified CAN flag status. + * + * @param flag: specifies the flag of CAN. + * The parameter can be one of following values: + * @arg CAN_FLAG_EWF : Error Warning Flag + * @arg CAN_FLAG_EPF : Error Passive Flag + * @arg CAN_FLAG_BOF : Bus-Off Flag + * @arg CAN_FLAG_LEC : Last error code Flag + * @arg CAN_FLAG_WUP : Wake up Flag + * @arg CAN_FLAG_SLAK : Sleep acknowledge Flag + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FMP0 : FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0 : FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0 : FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1 : FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1 : FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1 : FIFO 1 Overrun Flag + * + * @retval staus : RESET or SET + */ +uint8_t CAN_ReadStatusFlag(CAN_FLAG_T flag) +{ + uint8_t status = RESET; + + if ((flag & 0x00F00000) != (uint32_t)RESET) + { + if ((CAN->ERRSTS & (flag & 0x000FFFFF)) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + else if ((flag & 0x01000000) != (uint32_t)RESET) + { + if ((CAN->MSTS & (flag & 0x000FFFFF)) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + else if ((flag & 0x02000000) != (uint32_t)RESET) + { + if ((CAN->TXSTS & (flag & 0x000FFFFF)) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + else if ((flag & 0x04000000) != (uint32_t)RESET) + { + if ((CAN->RXF0 & (flag & 0x000FFFFF)) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + else + { + if ((CAN->RXF1 & (flag & 0x000FFFFF)) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + return status; +} + +/*! + * @brief Clears the status flags of CAN. + * + * @param flag : specifies the flag to clear. + * The parameter can be one of following values: + * @arg CAN_FLAG_LEC : Last error code Flag + * @arg CAN_FLAG_WUP : Wake up Flag + * @arg CAN_FLAG_SLAK : Sleep acknowledge Flag + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FF0 : FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0 : FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1 : FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1 : FIFO 1 Overrun Flag + * + * @retval None + */ +void CAN_ClearStatusFlag(CAN_FLAG_T flag) +{ + uint32_t flagtmp = 0; + + if (flag == CAN_FLAG_LEC) + { + CAN->ERRSTS_B.LERRC = 0; + } + else + { + flagtmp = flag & 0x000FFFFF; + + if ((flag & 0x01000000) != RESET) + { + CAN->MSTS = flagtmp; + } + else if ((flag & 0x02000000) != RESET) + { + CAN->TXSTS = flagtmp; + } + else if ((flag & 0x04000000) != RESET) + { + CAN->RXF0 = flagtmp; + } + else + { + CAN->RXF1 = flagtmp; + } + } +} + +/*! + * @brief Reads the specified CAN interrupt flag status. + * + * @param interrupt: specifies the CAN interrupt source. + * The parameter can be one of following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FUL: FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR: FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FUL: FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR: FIFO 1 overrun Interrupt + * @arg CAN_INT_EWIE : Error warning Interrupt + * @arg CAN_INT_EPIE : Error passive Interrupt + * @arg CAN_INT_BOIE : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLE : Sleep acknowledge Interrupt + * + * @retval status : SET or RESET + */ +uint8_t CAN_ReadIntFlag(CAN_INT_T interrupt) +{ + uint8_t status = 0; + + if ((CAN->INTEN & interrupt) != RESET) + { + switch (interrupt) + { + case CAN_INT_TXME: + status = CAN->TXSTS_B.REQCFLG0; + status |= CAN->TXSTS_B.REQCFLG1; + status |= CAN->TXSTS_B.REQCFLG2; + break; + case CAN_INT_F0MP: + status = !(!CAN->RXF0_B.FMNUM0); + break; + case CAN_INT_F0FUL: + status = CAN->RXF0_B.FFULLFLG0; + break; + case CAN_INT_F0OVR: + status = CAN->RXF0_B.FOVRFLG0; + break; + case CAN_INT_F1MP: + status = !(!CAN->RXF1_B.FMNUM1); + break; + case CAN_INT_F1FUL: + status = CAN->RXF1_B.FFULLFLG1; + break; + case CAN_INT_F1OVR: + status = CAN->RXF1_B.FOVRFLG1; + break; + case CAN_INT_EWIE: + status = CAN->ERRSTS_B.ERRWFLG; + break; + case CAN_INT_EPIE: + status = CAN->ERRSTS_B.ERRPFLG; + break; + case CAN_INT_BOIE: + status = CAN->ERRSTS_B.BOFLG; + break; + case CAN_INT_LEC: + status = !(!CAN->ERRSTS_B.LERRC); + break; + case CAN_INT_ERR: + status = CAN->MSTS_B.ERRIFLG; + break; + case CAN_INT_WUP: + status = CAN->MSTS_B.WUPIFLG; + break; + case CAN_INT_SLE: + status = CAN->MSTS_B.SLEEPIFLG; + break; + default: + status = RESET; + break; + } + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the CAN's interrupt flag. + * + * @param interrupt: specifies the interrupt flag to clear. + * The parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0FUL: FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR: FIFO 0 overrun Interrupt + * @arg CAN_INT_F1FUL: FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR: FIFO 1 overrun Interrupt + * @arg CAN_INT_EWIE : Error warning Interrupt + * @arg CAN_INT_EPIE : Error passive Interrupt + * @arg CAN_INT_BOIE : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLE : Sleep acknowledge Interrupt + * + * @retval None + */ +void CAN_ClearIntFlag(uint32_t interrupt) +{ + if (interrupt & CAN_INT_TXME) + { + CAN->TXSTS_B.REQCFLG0 = BIT_SET; + CAN->TXSTS_B.REQCFLG1 = BIT_SET; + CAN->TXSTS_B.REQCFLG2 = BIT_SET; + } + if (interrupt & CAN_INT_F0FUL) + { + CAN->RXF0_B.FFULLFLG0 = BIT_SET; + } + if (interrupt & CAN_INT_F0OVR) + { + CAN->RXF0_B.FOVRFLG0 = BIT_SET; + } + if (interrupt & CAN_INT_F1FUL) + { + CAN->RXF1_B.FFULLFLG1 = BIT_SET; + } + if (interrupt & CAN_INT_F1OVR) + { + CAN->RXF1_B.FOVRFLG1 = BIT_SET; + } + if (interrupt & CAN_INT_EWIE) + { + /** Note : the corresponding Flag is cleared by hardware + * depending of the CAN Bus status + */ + CAN->MSTS_B.ERRIFLG = BIT_SET; + } + if (interrupt & CAN_INT_EPIE) + { + /** Note : the corresponding Flag is cleared by hardware + * depending of the CAN Bus status + */ + CAN->MSTS_B.ERRIFLG = BIT_SET; + } + if (interrupt & CAN_INT_BOIE) + { + /** Note : the corresponding Flag is cleared by hardware + * depending of the CAN Bus status + */ + CAN->MSTS_B.ERRIFLG = BIT_SET; + } + if (interrupt & CAN_INT_LEC) + { + CAN->ERRSTS_B.LERRC = 0; + CAN->MSTS_B.ERRIFLG = BIT_SET; + } + if (interrupt & CAN_INT_ERR) + { + CAN->ERRSTS_B.LERRC = 0; + CAN->MSTS_B.ERRIFLG = BIT_SET; + } + if (interrupt & CAN_INT_WUP) + { + CAN->MSTS_B.WUPIFLG = BIT_SET; + } + if (interrupt & CAN_INT_SLE) + { + CAN->MSTS_B.SLEEPIFLG = BIT_SET; + } +} + +/**@} end of group CAN_Functions */ +/**@} end of group CAN_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_cec.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_cec.c new file mode 100644 index 0000000000..b82849ab98 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_cec.c @@ -0,0 +1,418 @@ +/*! + * @file apm32f0xx_cec.c + * + * @brief This file contains all the functions for the CEC peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_cec.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CEC_Driver + @{ +*/ + +/** @defgroup CEC_Macros Macros + @{ +*/ + +/**@} end of group CEC_Macros */ + +/** @defgroup CEC_Enumerations Enumerations + @{ +*/ + +/**@} end of group CEC_Enumerations */ + +/** @defgroup CEC_Structures Structures + @{ +*/ + +/**@} end of group CEC_Structures */ + +/** @defgroup CEC_Variables Variables + @{ +*/ + +/**@} end of group CEC_Variables */ + +/** @defgroup CEC_Functions Functions + @{ +*/ + +/*! + * @brief Reset CEC peripheral registers to their default values. + * + * @param None + * + * @retval None + */ +void CEC_Reset(void) +{ + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_CEC); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CEC); +} + +/*! + * @brief Configs the CEC peripheral according to the specified parameters + * in the cecConfig. + * + * @param cecConfig: pointer to an CEC_Config_T structure that is used to + * the configuration information for the specified CEC peripheral. + * + * @retval None + * + * @note The CEC parameters must be configured before enabling the CEC peripheral. + */ +void CEC_Config(CEC_Config_T* cecConfig) +{ + CEC->CFG_B.SFTCFG = cecConfig->signalFreeTime; + CEC->CFG_B.RXTCFG = cecConfig->RxTolerance; + CEC->CFG_B.RXSBRERR = cecConfig->stopReception; + CEC->CFG_B.GEBRERR = cecConfig->bitRisingError; + CEC->CFG_B.GELBPERR = cecConfig->longPeriodError; + CEC->CFG_B.AEBGIB = cecConfig->broadcastrNoGen; + CEC->CFG_B.SFTOB = cecConfig->signalFreeTimeOption; +} + +/*! + * @brief Fills each CEC_InitStruct member with its default value. + * + * @param cecConfig: pointer to a CEC_InitTypeDef structure which will + * be initialized. + * + * @retval None + */ +void CEC_ConfigStructInit(CEC_Config_T* cecConfig) +{ + cecConfig->signalFreeTime = CEC_SINGANL_FREETIME_STANDARD; + cecConfig->RxTolerance = CEC_RX_TOLERANCE_STANDARD; + cecConfig->stopReception = CEC_STOP_RECEPTION_OFF; + cecConfig->bitRisingError = CEC_BIT_RISING_ERR_OFF; + cecConfig->longPeriodError = CEC_LONG_PERIOD_ERR_OFF; + cecConfig->broadcastrNoGen = CEC_BROADCAST_NO_ERR_OFF; + cecConfig->signalFreeTimeOption = CEC_SIGNAL_FREETIME_OPTION_OFF; +} + +/*! + * @brief Enables the CEC peripheral. + * + * @param None + * + * @retval None + */ +void CEC_Enable(void) +{ + CEC->CTRL_B.CECEN = SET; +} + +/*! + * @brief Disables the CEC peripheral. + * + * @param None + * + * @retval None + */ +void CEC_Disable(void) +{ + CEC->CTRL_B.CECEN = RESET; +} + +/*! + * @brief Enables the CEC Listen Mode. + * + * @param None + * + * @retval None + */ +void CEC_EnableListenMode(void) +{ + CEC->CFG_B.LMODSEL = SET; +} + +/*! + * @brief Disables the CEC Listen Mode. + * + * @param None + * + * @retval None + */ +void CEC_DisableListenMode(void) +{ + CEC->CFG_B.LMODSEL = RESET; +} + +/*! + * @brief Defines the Own Address of the CEC device. + * + * @param ownAddress: The CEC own address. + * + * @retval None + */ +void CEC_ConfigOwnAddress(uint8_t ownAddress) +{ + CEC->CFG_B.OACFG |= (1 << ownAddress); +} + +/*! + * @brief Clears the Own Address of the CEC device. + * + * @param CEC_OwnAddress: The CEC own address. + * + * @retval None + */ +void CEC_ClearQwnAddress(void) +{ + CEC->CFG = 0x00; +} + +/*! + * @brief Transmits single data through the CEC peripheral. + * + * @param Data: the data to transmit. + * + * @retval None + */ +void CEC_TxData(uint8_t Data) +{ + CEC->TXDATA = Data; +} + +/*! + * @brief Returns the most recent received data by the CEC peripheral. + * + * @param None + * + * @retval The received data. + */ +uint8_t CEC_RxData(void) +{ + return (uint8_t)(CEC->RXDATA); +} + +/*! + * @brief Starts a new message. + * + * @param None + * + * @retval None + */ +void CEC_StartNewMessage(void) +{ + CEC->CTRL_B.TXSM = SET; +} + +/*! + * @brief Transmits message with an EOM bit. + * + * @param None + * + * @retval None + */ +void CEC_CompleteMessage(void) +{ + CEC->CTRL_B.TXEM = SET; +} + +/*! + * @brief Enables the selected CEC interrupts. + * + * @param flag: specifies the CEC interrupt source to be enabled. + * This parameter can be any combination of the following values: + * @arg CEC_INT_RXBR Rx-Byte Received + * @arg CEC_INT_RXEND End Of Reception + * @arg CEC_INT_RXOVR Rx Overrun. + * @arg CEC_INT_BRE Rx Bit Rising Error + * @arg CEC_INT_SBPE Rx Short period Error + * @arg CEC_INT_LBPE Rx Long period Error + * @arg CEC_INT_RXACKE Rx-Missing Acknowledge + * @arg CEC_INT_ARBLST Arbitration Lost + * @arg CEC_INT_TXBR Tx-Byte Request. + * @arg CEC_INT_TXEND End of Transmission + * @arg CEC_INT_TXUDR Tx-Buffer Underrun. + * @arg CEC_INT_TXERR Tx Error. + * @arg CEC_INT_TXACKE Tx Missing acknowledge Error + * + * @retval None + */ +void CEC_EnableInterrupt(uint32_t interrupt) +{ + CEC->INTEN |= (uint32_t)interrupt; +} + +/*! + * @brief Disables the selected CEC interrupts. + * + * @param flag: specifies the CEC interrupt source to be enabled. + * This parameter can be any combination of the following values: + * @arg CEC_INT_RXBR Rx-Byte Received + * @arg CEC_INT_RXEND End Of Reception + * @arg CEC_INT_RXOVR Rx Overrun. + * @arg CEC_INT_BRE Rx Bit Rising Error + * @arg CEC_INT_SBPE Rx Short period Error + * @arg CEC_INT_LBPE Rx Long period Error + * @arg CEC_INT_RXACKE Rx-Missing Acknowledge + * @arg CEC_INT_ARBLST Arbitration Lost + * @arg CEC_INT_TXBR Tx-Byte Request. + * @arg CEC_INT_TXEND End of Transmission + * @arg CEC_INT_TXUDR Tx-Buffer Underrun. + * @arg CEC_INT_TXERR Tx Error. + * @arg CEC_INT_TXACKE Tx Missing acknowledge Error + * + * @retval None + */ +void CEC_DisableInterrupt(uint32_t interrupt) +{ + CEC->INTEN &= ~(uint32_t)interrupt; +} + +/*! + * @brief Read the CEC flag status. + * + * @param flag: specifies the CEC interrupt source to be enabled. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_RXBR Rx-Byte Received + * @arg CEC_FLAG_RXEND End Of Reception + * @arg CEC_FLAG_RXOVR Rx Overrun. + * @arg CEC_FLAG_BRE Rx Bit Rising Error + * @arg CEC_FLAG_SBPE Rx Short period Error + * @arg CEC_FLAG_LBPE Rx Long period Error + * @arg CEC_FLAG_RXACKE Rx-Missing Acknowledge + * @arg CEC_FLAG_ARBLST Arbitration Lost + * @arg CEC_FLAG_TXBR Tx-Byte Request. + * @arg CEC_FLAG_TXEND End of Transmission + * @arg CEC_FLAG_TXUDR Tx-Buffer Underrun. + * @arg CEC_FLAG_TXERR Tx Error. + * @arg CEC_FLAG_TXACKE Tx Missing acknowledge Error + * + * @retval The new state of CEC_FLAG (SET or RESET) + */ +uint8_t CEC_ReadStatusFlag(uint32_t flag) +{ + uint32_t status; + + status = (uint32_t)(CEC->STS & flag); + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the CEC's pending flags. + * + * @param flag: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_RXBR Rx-Byte Received + * @arg CEC_FLAG_RXEND End Of Reception + * @arg CEC_FLAG_RXOVR Rx Overrun. + * @arg CEC_FLAG_BRE Rx Bit Rising Error + * @arg CEC_FLAG_SBPE Rx Short period Error + * @arg CEC_FLAG_LBPE Rx Long period Error + * @arg CEC_FLAG_RXACKE Rx-Missing Acknowledge + * @arg CEC_FLAG_ARBLST Arbitration Lost + * @arg CEC_FLAG_TXBR Tx-Byte Request. + * @arg CEC_FLAG_TXEND End of Transmission + * @arg CEC_FLAG_TXUDR Tx-Buffer Underrun. + * @arg CEC_FLAG_TXERR Tx Error. + * @arg CEC_FLAG_TXACKE Tx Missing acknowledge Error + * + * @retval None + */ +void CEC_ClearStatusFlag(uint32_t flag) +{ + CEC->STS = flag; +} + +/*! + * @brief Checks whether the specified CEC interrupt has occurred or not. + * + * @param flag: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_INT_RXBR Rx-Byte Received + * @arg CEC_INT_RXEND End Of Reception + * @arg CEC_INT_RXOVR Rx Overrun. + * @arg CEC_INT_BRE Rx Bit Rising Error + * @arg CEC_INT_SBPE Rx Short period Error + * @arg CEC_INT_LBPE Rx Long period Error + * @arg CEC_INT_RXACKE Rx-Missing Acknowledge + * @arg CEC_INT_ARBLST Arbitration Lost + * @arg CEC_INT_TXBR Tx-Byte Request. + * @arg CEC_INT_TXEND End of Transmission + * @arg CEC_INT_TXUDR Tx-Buffer Underrun. + * @arg CEC_INT_TXERR Tx Error. + * @arg CEC_INT_TXACKE Tx Missing acknowledge Error + * + * @retval The new state of Flag (SET or RESET). + */ +uint8_t CEC_ReadIntFlag(uint16_t flag) +{ + uint32_t intEnable; + uint32_t intStatus; + intEnable = (CEC->INTEN & flag); + intStatus = (CEC->STS & flag); + if ((intStatus != (uint32_t)RESET) && intEnable) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the CEC's interrupt flag. + * + * @param flag: specifies the CEC interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_INT_RXBR Rx-Byte Received + * @arg CEC_INT_RXEND End Of Reception + * @arg CEC_INT_RXOVR Rx Overrun. + * @arg CEC_INT_BRE Rx Bit Rising Error + * @arg CEC_INT_SBPE Rx Short period Error + * @arg CEC_INT_LBPE Rx Long period Error + * @arg CEC_INT_RXACKE Rx-Missing Acknowledge + * @arg CEC_INT_ARBLST Arbitration Lost + * @arg CEC_INT_TXBR Tx-Byte Request. + * @arg CEC_INT_TXEND End of Transmission + * @arg CEC_INT_TXUDR Tx-Buffer Underrun. + * @arg CEC_INT_TXERR Tx Error. + * @arg CEC_INT_TXACKE Tx Missing acknowledge Error + * + * @retval None + */ +void CEC_ClearIntFlag(uint16_t flag) +{ + CEC->STS = flag; +} + +/**@} end of group CEC_Functions */ +/**@} end of group CEC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_comp.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_comp.c new file mode 100644 index 0000000000..9f2f034af3 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_comp.c @@ -0,0 +1,298 @@ +/*! + * @file apm32f0xx_comp.c + * + * @brief This file contains all the functions for the COMP peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_comp.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup COMP_Driver + @{ +*/ + +/** @defgroup COMP_Macros Macros + @{ +*/ + +/**@} end of group COMP_Macros */ + +/** @defgroup COMP_Enumerations Enumerations + @{ +*/ + +/**@} end of group COMP_Enumerations */ + +/** @defgroup COMP_Structures Structures + @{ +*/ + +/**@} end of group COMP_Structures */ + +/** @defgroup COMP_Variables Variables + @{ +*/ + +/**@} end of group COMP_Variables */ + +/** @defgroup COMP_Functions Functions + @{ +*/ + +/*! + * @brief Reset COMP peripheral registers to their default values. + * + * @param None + * + * @retval None + * + * @note Deinitialization can't be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + */ +void COMP_Reset(void) +{ + COMP->CSTS = ((uint32_t)0x00000000); +} + +/*! + * @brief Configs the COMP peripheral according to the specified parameters + * in COMP_InitStruct + * + * @param compSelect: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_SELECT_COMP1: COMP1 selected + * @arg COMP_SELECT_COMP2: COMP2 selected + * + * @param compConfig: pointer to an COMP_Config_T structure that contains + * the configuration information for the specified COMP peripheral. + * + * @retval None + * + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * + * @note By default, PA1 is selected as COMP1 non inverting input. + * To use PA4 as COMP1 non inverting input call COMP_EnableSwitch() after COMP_Config() + * + */ +void COMP_Config(COMP_SELECT_T compSelect, COMP_Config_T* compConfig) +{ + if (compSelect == COMP_SELECT_COMP1) + { + COMP->CSTS_B.INVINSEL1 = compConfig->invertingInput; + COMP->CSTS_B.OUTSEL1 = compConfig->output; + COMP->CSTS_B.OPINV1 = compConfig->outputPol; + COMP->CSTS_B.HYSCFG1 = compConfig->hysterrsis; + COMP->CSTS_B.MOD1 = compConfig->mode; + } + else + { + COMP->CSTS_B.INVINSEL2 = compConfig->invertingInput; + COMP->CSTS_B.OUTSEL2 = compConfig->output; + COMP->CSTS_B.OPINV2 = compConfig->outputPol; + COMP->CSTS_B.HYSCFG2 = compConfig->hysterrsis; + COMP->CSTS_B.MOD2 = compConfig->mode; + } +} + +/*! + * @brief Fills each compConfig member with initial value value. + * + * @param compConfig: pointer to an COMP_InitTypeDef structure which will + * be initialized. + * + * @retval None + */ +void COMP_ConfigStructInit(COMP_Config_T* compConfig) +{ + compConfig->invertingInput = COMP_INVERTING_INPUT_1_4VREFINT; + compConfig->output = COMP_OUTPUT_NONE; + compConfig->outputPol = COMP_OUTPUTPOL_NONINVERTED; + compConfig->hysterrsis = COMP_HYSTERRSIS_NO; + compConfig->mode = COMP_MODE_HIGHSPEED; +} + +/*! + * @brief Enable the COMP peripheral. + * + * @param compSelect: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_SELECT_COMP1: COMP1 selected + * @arg COMP_SELECT_COMP2: COMP2 selected + * + * @retval None + * + * @note If the selected comparator is locked, enable can't be performed. + * To unlock the configuration, perform a system reset. + */ +void COMP_Enable(COMP_SELECT_T compSelect) +{ + if (compSelect == COMP_SELECT_COMP1) + { + COMP->CSTS_B.EN1 = SET; + } + else + { + COMP->CSTS_B.EN2 = SET; + } +} + +/*! + * @brief Disable the COMP peripheral. + * + * @param compSelect: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_SELECT_COMP1: COMP1 selected + * @arg COMP_SELECT_COMP2: COMP2 selected + * + * @retval None + * + * @note If the selected comparator is locked, disable can't be performed. + * To unlock the configuration, perform a system reset. + */ +void COMP_Disable(COMP_SELECT_T compSelect) +{ + if (compSelect == COMP_SELECT_COMP1) + { + COMP->CSTS_B.EN1 = RESET; + } + else + { + COMP->CSTS_B.EN2 = RESET; + } +} + +/*! + * @brief Close the SW1 switch. + * + * @param None + * + * @retval None + * + * @note This switch is solely intended to redirect signals onto high + * impedance input, such as COMP1 non-inverting input (highly resistive switch) + */ +void COMP_EnableSwitch(void) +{ + COMP->CSTS_B.SW1 = SET; +} + +/*! + * @brief Open the SW1 switch. + * + * @param None + * + * @retval None + */ +void COMP_DisableSwitch(void) +{ + COMP->CSTS_B.SW1 = RESET; +} + +/*! + * @brief Return the output level (high or low) of the selected comparator. + * + * @param compSelect: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_SELECT_COMP1: COMP1 selected + * @arg COMP_SELECT_COMP2: COMP2 selected + * + * @retval Returns the selected comparator output level: low or high. + */ +uint32_t COMP_ReadOutPutLevel(COMP_SELECT_T compSelect) +{ + uint32_t compOUT = 0x00; + if (compSelect == COMP_SELECT_COMP1) + { + if ((COMP->CSTS & COMP_CSTS_COMP1OUT) != 0) + { + compOUT = COMP_OUTPUTLEVEL_HIGH; + } + else + compOUT = COMP_OUTPUTLEVEL_LOW; + } + else + { + if ((COMP->CSTS & COMP_CSTS_COMP2OUT) != 0) + { + compOUT = COMP_OUTPUTLEVEL_HIGH; + } + else + compOUT = COMP_OUTPUTLEVEL_LOW; + } + return (uint32_t)(compOUT); +} + +/*! + * @brief Enablesthe window mode. + * + * @param None + * + * @retval None + */ +void COMP_EnableWindow(void) +{ + COMP->CSTS_B.WMODEN = SET; +} + +/*! + * @brief Disables the window mode. + * + * @param None + * + * @retval None + */ +void COMP_DisnableWindow(void) +{ + COMP->CSTS_B.WMODEN = RESET; +} + +/*! + * @brief Lock the selected comparator configuration. + * + * @param compSelect: selects the comparator to be locked + * This parameter can be one of the following values: + * @arg COMP_SELECT_COMP1: COMP1 configuration is locked. + * @arg COMP_SELECT_COMP2: COMP2 configuration is locked. + * + * @retval None + */ +void COMP_ConfigLOCK(COMP_SELECT_T compSelect) +{ + if (compSelect == COMP_SELECT_COMP1) + { + COMP->CSTS_B.LOCK1 = SET; + } + else + { + COMP->CSTS_B.LOCK2 = SET; + } +} + +/**@} end of group COMP_Functions */ +/**@} end of group COMP_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_crc.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_crc.c new file mode 100644 index 0000000000..ae2f6b4426 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_crc.c @@ -0,0 +1,284 @@ +/*! + * @file apm32f0xx_crc.c + * + * @brief This file provides all the CRC firmware functions + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* include */ +#include "apm32f0xx_crc.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CRC_Driver + @{ +*/ + +/** @defgroup CRC_Macros Macros + @{ +*/ + +/**@} end of group CRC_Macros */ + +/** @defgroup CRC_Enumerations Enumerations + @{ +*/ + +/**@} end of group CRC_Enumerations */ + +/** @defgroup CRC_Structures Structures + @{ +*/ + +/**@} end of group CRC_Structures */ + +/** @defgroup CRC_Variables Variables + @{ +*/ + +/**@} end of group CRC_Variables */ + +/** @defgroup CRC_Functions Functions + @{ +*/ + +/*! + * @brief Resets the CRC peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void CRC_Reset(void) +{ + CRC->DATA = 0xFFFFFFFF; + CRC->INDATA = 0x00; + CRC->INITVAL = 0xFFFFFFFF; + CRC->CTRL = 0x00000000; + CRC->POL = 0x04C11DB7; +} + +/*! + * @brief Reset CRC data register (DATA) + * + * @param None + * + * @retval None + */ +void CRC_ResetDATA(void) +{ + CRC->CTRL_B.RST = BIT_SET; +} + +/*! + * @brief Set the CRC polynomial size. + * + * @param polynomialSize: CRC polynomial size + * The parameter can be one of following values: + * @arg CRC_POLYNOMIAL_SIZE_7: 7-bit polynomial for CRC calculation + * @arg CRC_POLYNOMIAL_SIZE_8: 8-bit polynomial for CRC calculation + * @arg CRC_POLYNOMIAL_SIZE_16: 16-bit polynomial for CRC calculation + * @arg CRC_POLYNOMIAL_SIZE_32: 32-bit polynomial for CRC calculation + * + * @retval None + * + * @note It's only for APM32F072 and APM32F091 devices + */ +void CRC_SetPolynomialSize(CRC_POLYNOMIAL_SIZE_T polynomialSize) +{ + CRC->CTRL_B.POLSIZE = polynomialSize; +} + +/*! + * @brief Set the CRC polynomail coefficients. + * + * @param polynomialValue: Polynomial to be used for CRC calculation + * + * @retval None + * + * @note It's only for APM32F072 and APM32F091 devices + */ +void CRC_SetPolynomialValue(uint32_t polynomialValue) +{ + CRC->POL = polynomialValue; +} + +/*! + * @brief Selects the reverse operation to be performed on input data + * + * @param revInData: Reverse input data + * The parameter can be one of following values: + * @arg CRC_REVERSE_INPUT_DATA_NO: Bit order not affected + * @arg CRC_REVERSE_INPUT_DATA_8B: Bit reversal done by byte + * @arg CRC_REVERSE_INPUT_DATA_16B: Bit reversal done by half-word + * @arg CRC_REVERSE_INPUT_DATA_32B: Bit reversal done by word + * + * @retval None + */ +void CRC_SelectReverseInputData(CRC_REVERSE_INPUT_DATA_T revInData) +{ + CRC->CTRL_B.REVI = revInData; +} + +/*! + * @brief Enable the reverse operation on output data + * + * @param None + * + * @retval None + */ +void CRC_EnableReverseOutputData(void) +{ + CRC->CTRL_B.REVO = BIT_SET; +} + +/*! + * @brief Disable the reverse operation on output data + * + * @param None + * + * @retval None + */ +void CRC_DisableReverseOutputData(void) +{ + CRC->CTRL_B.REVO = BIT_RESET; +} + +/*! + * @brief Initializes the INITVAL register. + * + * @param initValue: Programmable initial CRC value + * + * @retval None + */ +void CRC_WriteInitRegister(uint32_t initValue) +{ + CRC->INITVAL = initValue; +} + +/*! + * @brief Calculate a 32-bit CRC for a given data word (32 bits) + * + * @param data: data word(32-bit) to compute its CRC + * + * @retval 32-bit CRC + */ +uint32_t CRC_CalculateCRC(uint32_t data) +{ + CRC->DATA = data; + + return (CRC->DATA); +} + +/*! + * @brief Calculate a 32-bit CRC for a given data word (16 bits) + * + * @param data: data word(16-bit) to compute its CRC + * + * @retval 16-bit CRC + * + * @note It's only for APM32F072 and APM32F091 devices + */ +uint32_t CRC_CalculateCRC16bits(uint16_t data) +{ + *(uint16_t*)(CRC_BASE) = (uint16_t) data; + + return (CRC->DATA); +} + +/*! + * @brief Calculate a 32-bit CRC for a given data word (8 bits) + * + * @param data: data word(8-bit) to compute its CRC + * + * @retval 8-bit CRC + * + * @note It's only for APM32F072 and APM32F091 devices + */ +uint32_t CRC_CalculateCRC8bits(uint8_t data) +{ + *(uint8_t*)(CRC_BASE) = (uint8_t) data; + + return (CRC->DATA); +} + +/*! + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit) + * + * @param pBuffer: Pointer to the buffer containing the data to be computed + * + * @param bufferLength: buffer length + * + * @retval 32-bit CRC + */ +uint32_t CRC_CalculateBlockCRC(uint32_t pBuffer[], uint32_t bufferLength) +{ + uint32_t index = 0; + + for (index = 0; index < bufferLength; index++) + { + CRC->DATA = pBuffer[index]; + } + + return (CRC->DATA); +} + +/*! + * @brief Returns the current CRC value + * + * @param None + * + * @retval 32-bit CRC + */ +uint32_t CRC_ReadCRC(void) +{ + return (CRC->DATA); +} + +/*! + * @brief Stores a 8-bit data in the Independent Data(INDATA) register + * + * @param IDValue: 8-bit value to be stored in the INDATA register + * + * @retval None + */ +void CRC_WriteIDRegister(uint8_t IDValue) +{ + CRC->INDATA = IDValue; +} + +/*! + * @brief Returns a 8-bit data stored in the Independent Data(INDATA) register + * + * @param None + * + * @retval 8-bit value of the INDATA register + */ +uint8_t CRC_ReadIDRegister(void) +{ + return (CRC->INDATA); +} + +/**@} end of group CRC_Functions */ +/**@} end of group CRC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_crs.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_crs.c new file mode 100644 index 0000000000..0ecec279f3 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_crs.c @@ -0,0 +1,424 @@ +/*! + * @file apm32f0xx_crs.c + * + * @brief This file contains all the functions for the CRS peripheral + * + * @note It's only for APM32F072 and APM32F091 devices + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_crs.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup CRS_Driver + @{ +*/ + +/** @defgroup CRS_Macros Macros + @{ +*/ + +/**@} end of group CRS_Macros */ + +/** @defgroup CRS_Enumerations Enumerations + @{ +*/ + +/**@} end of group CRS_Enumerations */ + +/** @defgroup CRS_Structures Structures + @{ +*/ + +/**@} end of group CRS_Structures */ + +/** @defgroup CRS_Variables Variables + @{ +*/ + +/**@} end of group CRS_Variables */ + +/** @defgroup CRS_Functions Functions + @{ +*/ + +/*! + * @brief Resets the CRS peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void CRS_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CRS); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CRS); +} + +/*! + * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. + * + * @param calibrationVal: HSI48 oscillator smooth trimming value. It can be 0x0 to 0xF. + * + * @retval None + */ +void CRS_AdjustHSI48CalibrationValue(uint8_t calibrationVal) +{ + CRS->CTRL_B.HSI48TRM = calibrationVal; +} + +/*! + * @brief Enables the oscillator clock for frequency error counter. + * + * @param None + * + * @retval None + */ +void CRS_EnableFrequencyErrorCounter(void) +{ + CRS->CTRL_B.CNTEN = SET; +} + +/*! + * @brief Disables the oscillator clock for frequency error counter. + * + * @param None + * + * @retval None + */ +void CRS_DisableFrequencyErrorCounter(void) +{ + CRS->CTRL_B.CNTEN = RESET; +} + +/*! + * @brief Enables the automatic hardware adjustement of HSI48TRM bits. + * + * @param None + * + * @retval None + */ +void CRS_EnableAutomaticCalibration(void) +{ + CRS->CTRL_B.AUTOTRMEN = SET; +} + +/*! + * @brief Disables the automatic hardware adjustement of HSI48TRM bits. + * + * @param None + * + * @retval None + */ +void CRS_DisableAutomaticCalibration(void) +{ + CRS->CTRL_B.AUTOTRMEN = RESET; +} + +/*! + * @brief Generate the software synchronization event. + * + * @param None + * + * @retval None + */ +void CRS_GenerateSoftwareSynchronization(void) +{ + CRS->CTRL_B.SWSGNR = SET; +} + +/*! + * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. + * + * @param reloadVal: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and 0xFFFF. + * + * @retval None + */ +void CRS_FrequencyErrorCounterReloadValue(uint16_t reloadVal) +{ + CRS->CFG_B.RLDVAL = reloadVal; +} + +/** + * @brief Configs the frequency error limit value. + * + * @param errLimitVal: specifies the HSI calibration trimming value. + * + * @retval None + */ +void CRS_ConfigFrequencyErrorLimit(uint8_t errLimitVal) +{ + CRS->CFG_B.FELMT = errLimitVal; +} + +/*! + * @brief Configs SYNC divider. + * + * @param div: defines the SYNC divider. + * This parameter can be one of the following values: + * @arg CRS_SYNC_DIV1 + * @arg CRS_SYNC_DIV2 + * @arg CRS_SYNC_DIV4 + * @arg CRS_SYNC_DIV8 + * @arg CRS_SYNC_DIV16 + * @arg CRS_SYNC_DIV32 + * @arg CRS_SYNC_DIV64 + * @arg CRS_SYNC_DIV128 + * + * @retval None + */ +void CRS_ConfigSynchronizationPrescaler(CRS_SYNC_DIV_T div) +{ + CRS->CFG_B.SYNCPSC = div; +} + +/*! + * @brief Configs the SYNC signal source. + * + * @param source: specifies the SYNC signal source. + * This parameter can be one of the following values: + * @arg CRS_SYNC_SOURCE_GPIO + * @arg CRS_SYNC_SOURCE_LSE + * @arg CRS_SYNC_SOURCE_USB + * + * @retval None + */ +void CRS_ConfigSynchronizationSource(CRS_SYNC_SOURCE_T source) +{ + CRS->CFG_B.SYNCSRCSEL = source; +} + +/*! + * @brief Configs the SYNC polarity. + * + * @param polarity: specifies SYNC polarity. + * This parameter can be one of the following values: + * @arg CRS_SYNC_POL_RISING + * @arg CRS_SYNC_POL_FALLING + * + * @retval None + */ +void CRS_ConfigSynchronizationPolarity(CRS_SYNC_POL_T polarity) +{ + CRS->CFG_B.SYNCPOLSEL = polarity; +} + +/*! + * @brief Returns the Relaod value. + * + * @param None + * + * @retval The reload value + */ +uint32_t CRS_ReadReloadValue(void) +{ + return (uint32_t)CRS->CFG_B.RLDVAL; +} + +/*! + * @brief Returns the HSI48 Calibration value. + * + * @param None + * + * @retval The reload value + */ +uint32_t CRS_ReadHSI48CalibrationValue(void) +{ + return (uint32_t)CRS->CTRL_B.HSI48TRM; +} + +/*! + * @brief Returns the frequency error capture. + * + * @param None + * + * @retval The frequency error capture value + */ +uint32_t CRS_ReadFrequencyErrorValue(void) +{ + return (uint32_t)CRS->INTSTS_B.FECPT; +} + +/*! + * @brief Returns the frequency error direction. + * + * @param None + * + * @retval The frequency error direction. + * The returned value can be one of the following values: + * 0: Up counting + * 1: Down counting + */ +uint32_t CRS_ReadFrequencyErrorDirection(void) +{ + return (uint32_t)CRS->INTSTS_B.CNTDRCT; +} + +/*! + * @brief Enables the specified CRS interrupts. + * + * @param interrupt: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRS_INT_SYNCOK : SYNC event OK interrupt + * @arg CRS_INT_SYNCWARN: SYNC warning interrupt + * @arg CRS_INT_ERR : Synchronization or trimming error interrupt + * @arg CRS_INT_ESYNC : Expected SYNC interrupt + * + * @retval None + */ +void CRS_EnableInterrupt(CRS_INT_T interrupt) +{ + CRS->CTRL |= interrupt; +} + +/*! + * @brief Disables the specified CRS interrupts. + * + * @param interrupt: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRS_INT_SYNCOK : SYNC event OK interrupt + * @arg CRS_INT_SYNCWARN: SYNC warning interrupt + * @arg CRS_INT_ERR : Synchronization or trimming error interrupt + * @arg CRS_INT_ESYNC : Expected SYNC interrupt + * + * @retval None + */ +void CRS_DisableInterrupt(CRS_INT_T interrupt) +{ + CRS->CTRL &= ~interrupt; +} + +/*! + * @brief Checks whether the specified CRS flag is set or not. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRS_FLAG_SYNCOK : SYNC event OK flag + * @arg CRS_FLAG_SYNCWARN: SYNC warning flag + * @arg CRS_FLAG_ERR : Synchronization or trimming error flag + * @arg CRS_FLAG_ESYNC : Expected SYNC flag + * @arg CRS_FLAG_SYNCERR : SYNC error flag + * @arg CRS_FLAG_SYNCMISS: SYNC missed flag + * @arg CRS_FLAG_TRIMOVF : Trimming overflow or underflow falg + * + * @retval The new state of CRS_FLAG (SET or RESET). + */ +uint8_t CRS_ReadStatusFlag(CRS_FLAG_T flag) +{ + uint32_t status; + status = (uint32_t)(CRS->INTSTS & flag); + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the CRS specified flag. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRS_FLAG_SYNCOK : SYNC event OK flag + * @arg CRS_FLAG_SYNCWARN: SYNC warning flag + * @arg CRS_FLAG_ERR : Synchronization or trimming error flag + * @arg CRS_FLAG_ESYNC : Expected SYNC flag + * @arg CRS_FLAG_SYNCERR : SYNC error flag + * @arg CRS_FLAG_SYNCMISS: SYNC missed flag + * @arg CRS_FLAG_TRIMOVF : Trimming overflow or underflow falg + * + * @retval None + */ +void CRS_ClearStatusFlag(CRS_FLAG_T flag) +{ + if ((flag & 0x00000700) != 0) + { + CRS->INTCLR_B.ECLR = BIT_SET; + } + + CRS->INTCLR |= (uint32_t)flag; +} + +/*! + * @brief Checks CRS interrupt flag. + * + * @param flag: specifies the IT pending bit to check. + * This parameter can be one of the following values: + * @arg CRS_INT_SYNCOK : SYNC event OK interrupt + * @arg CRS_INT_SYNCWARN: SYNC warning interrupt + * @arg CRS_INT_ERR : Synchronization or trimming error interrupt + * @arg CRS_INT_ESYNC : Expected SYNC interrupt + * @arg CRS_INT_SYNCERR : SYNC error + * @arg CRS_INT_SYNCMISS: SYNC missed + * @arg CRS_INT_TRIMOVF : Trimming overflow or underflow + * + * @retval The new state of CRS_IT (SET or RESET). + */ +uint8_t CRS_ReadIntFlag(CRS_INT_T flag) +{ + if ((CRS->INTSTS & flag)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the CRS specified interrupt flag. + * + * @param intFlag: specifies the IT pending bi to clear. + * This parameter can be one of the following values: + * @arg CRS_INT_SYNCOK : SYNC event OK interrupt + * @arg CRS_INT_SYNCWARN: SYNC warning interrupt + * @arg CRS_INT_ERR : Synchronization or trimming error interrupt + * @arg CRS_INT_ESYNC : Expected SYNC interrupt + * @arg CRS_INT_SYNCERR : SYNC error + * @arg CRS_INT_SYNCMISS: SYNC missed + * @arg CRS_INT_TRIMOVF : Trimming overflow or underflow + * + * @retval None + */ +void CRS_ClearIntFlag(CRS_INT_T intFlag) +{ + if ((intFlag & (uint32_t)0x700) != 0) + { + CRS->INTCLR |= CRS_INT_ERR; + } + else + { + CRS->INTCLR |= intFlag; + } +} + +/**@} end of group CRS_Functions */ +/**@} end of group CRS_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dac.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dac.c new file mode 100644 index 0000000000..5089bb33b9 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dac.c @@ -0,0 +1,595 @@ +/*! + * @file apm32f0xx_dac.c + * + * @brief This file contains all the functions for the DAC peripheral + * + * @note It's only for APM32F051,APM32F072,APM32F091 devices + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_dac.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup DAC_Driver + @{ +*/ + +/** @defgroup DAC_Macros Macros + @{ +*/ + +/**@} end of group DAC_Macros */ + +/** @defgroup DAC_Enumerations Enumerations + @{ +*/ + +/**@} end of group DAC_Enumerations */ + +/** @defgroup DAC_Structures Structures + @{ +*/ + +/**@} end of group DAC_Structures */ + +/** @defgroup DAC_Variables Variables + @{ +*/ + +/**@} end of group DAC_Variables */ + +/** @defgroup DAC_Functions Functions + @{ +*/ + +/*! + * @brief Resets the DAC peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void DAC_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_DAC); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_DAC); +} + +/*! + * @brief Initializes the DAC peripheral according to the specified parameters in the dacConfig. + * + * @param channel: the selected DAC channel. + * This parameter can be: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * + * @param dacConfig: pointer to a DAC_Config_T structure that contains + * the configuration information for the specified DAC channel. + * + * @retval None + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig) +{ + uint32_t tmpcfg; + + tmpcfg = ((uint32_t)dacConfig->trigger | \ + (uint32_t)dacConfig->waveGeneration | \ + (uint32_t)dacConfig->maskAmplitudeSelect | \ + (uint32_t)dacConfig->outputBuff); + DAC->CTRL = (tmpcfg << channel); +} + +/*! + * @brief Fills each DAC_InitStruct member with its default value. + * + * @param dacConfig: pointer to a DAC_InitTypeDef structure which will + * be configed. + * + * @retval None + */ +void DAC_ConfigStructInit(DAC_Config_T* dacConfig) +{ + dacConfig->trigger = DAC_TRIGGER_NONE; + dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE; + dacConfig->maskAmplitudeSelect = DAC_LFSRUNAMASK_BIT0; + dacConfig->outputBuff = DAC_OUTPUTBUFF_ENABLE; +} + +/*! + * @brief Enables the specified DAC channel. + * + * @param channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note When the DAC channel is enabled the trigger source can no more be modified. + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_Enable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.ENCH1 = SET; + } + else + { + DAC->CTRL_B.ENCH2 = SET; + } +} + +/*! + * @brief Disables the specified DAC channel. + * + * @param channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_Disable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.ENCH1 = RESET; + } + else + { + DAC->CTRL_B.ENCH2 = RESET; + } +} + +/*! + * @brief Enables the selected DAC channel software trigger. + * + * @param channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->SWTRG_B.SWTRG1 = SET; + } + else + { + DAC->SWTRG_B.SWTRG2 = SET; + } +} + +/*! + * @brief Disable the selected DAC channel software trigger. + * + * @param channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->SWTRG_B.SWTRG1 = RESET; + } + else + { + DAC->SWTRG_B.SWTRG2 = RESET; + } +} + +/*! + * @brief Enables simultaneously the two DAC channels software triggers. + * + * @param None + * + * @retval None + * + * @note This function is only for APM32F072 and APM32F091 devices + */ +void DAC_EnableDualSoftwareTrigger(void) +{ + DAC->SWTRG |= DUAL_SWTRIG_SET; +} + +/*! + * @brief Disables simultaneously the two DAC channels software triggers. + * + * @param None + * + * @retval None + * + * @note This function is only for APM32F072 and APM32F091 devices + */ +void DAC_DisableDualSoftwareTrigger(void) +{ + DAC->SWTRG &= DUAL_SWTRIG_RESET; +} + +/*! + * @brief Enables the selected DAC channel wave generation. + * + * @param channel: The selected DAC channel. + * This parameter can be: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @param wave: specifies the wave type to enable or disable. + * This parameter can be: + * @arg DAC_WAVE_GENERATION_NOISE: noise wave generation + * @arg DAC_WAVE_GENERATION_TRIANGLE: triangle wave generation + * + * @retval None + * + * @note This function is only for APM32F072 and APM32F091 devices + */ +void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave) +{ + DAC->CTRL |= ((uint32_t)wave) << ((uint32_t)channel); +} + +/*! + * @brief Disable the selected DAC channel wave generation. + * + * @param channel: The selected DAC channel. + * This parameter can be: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @param wave: specifies the wave type to enable or disable. + * This parameter can be: + * @arg DAC_WAVE_GENERATION_NOISE: noise wave generation + * @arg DAC_WAVE_GENERATION_TRIANGLE: triangle wave generation + * + * @retval None + * + * @note This function is only for APM32F072 and APM32F091 devices + */ +void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave) +{ + DAC->CTRL &= ~((uint32_t)wave) << ((uint32_t)channel); +} + +/*! + * @brief Sets the specified data holding register value for DAC channel1. + * + * @param dataAlign: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * + * @param data: Data to be loaded in the selected data holding register. + * + * @retval None + */ +void DAC_ConfigChannel1Data(DAC_DATA_ALIGN_T dataAlign, uint16_t data) +{ + __IO uint32_t tmp = 0; + tmp = (uint32_t)DAC_BASE; + tmp += DH12RCH1_OFFSET + dataAlign; + *(__IO uint32_t*) tmp = data; +} + +/*! + * @brief Sets the specified data holding register value for DAC channel2. + * + * @param dataAlign: Specifies the data alignment for DAC channel2. + * This parameter can be: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * + * @param data: Data to be loaded in the selected data holding register. + * + * @retval None + * + * @note This function is only for APM32F072 and APM32F091 devices + */ +void DAC_ConfigChannel2Data(DAC_DATA_ALIGN_T dataAlign, uint16_t data) +{ + __IO uint32_t tmp = 0; + tmp = (uint32_t)DAC_BASE; + tmp += DH12RCH2_OFFSET + dataAlign; + *(__IO uint32_t*)tmp = data; +} + +/*! + * @brief Sets the specified data holding register value for dual channel DAC. + * + * @param dataAlign: Specifies the data alignment for dual channel DAC. + * This parameter can be: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param data2: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param data1: Data for DAC Channel1 to be loaded in the selected data holding register. + * + * @retval None + * + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * + * @note This function is only for APM32F072 and APM32F091 devices + */ +void DAC_ConfigDualChannelData(DAC_DATA_ALIGN_T dataAlign, uint16_t data2, uint16_t data1) +{ + uint32_t data = 0, tmp = 0; + + if (dataAlign == DAC_ALIGN_8B_R) + { + data = ((uint32_t)data2 << 8) | data1; + } + else + { + data = ((uint32_t)data2 << 16) | data1; + } + tmp = (uint32_t)DAC_BASE; + tmp += DH12RD_OFFSET + dataAlign; + *(__IO uint32_t*)tmp = data; +} + +/*! + * @brief Returns the last data output value of the selected DAC channel. + * + * @param channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval The selected DAC channel data output value. + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel) +{ + uint16_t data; + if (channel == DAC_CHANNEL_1) + { + data = DAC->DATAOCH1_B.DATA; + } + else + { + data = DAC->DATAOCH2_B.DATA; + } + return data; +} + +/*! + * @brief Enables the specified DAC channel DMA request. + * When enabled DMA1 is generated when an external trigger (EINT Line9, + * TMR2, TMR3, TMR6 or TMR15 but not a software trigger) occurs + + * @param channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured. + * + * @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured. + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_EnableDMA(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAENCH1 = SET; + } + else + { + DAC->CTRL_B.DMAENCH2 = SET; + } +} + +/*! + * @brief Disable the specified DAC channel DMA request. + * + * @param channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured. + * + * @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured. + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_DisableDMA(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAENCH1 = RESET; + } + else + { + DAC->CTRL_B.DMAENCH2 = RESET; + } +} + +/*! + * @brief Enables the specified DAC interrupts. + * + * @param channel: The selected DAC channel. + * This parameter can be: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_EnableInterrupt(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAUDRIEN1 = SET; + } + else + { + DAC->CTRL_B.DMAUDRIEN2 = SET; + } +} + +/*! + * @brief Disables the specified DAC interrupts. + * + * @param channel: The selected DAC channel. + * This parameter can be: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * + * @retval None + * + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * + * @note DAC_Channel_2 is only for APM32F072 and APM32F091 devices + */ +void DAC_DisableInterrupt(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAUDRIEN1 = RESET; + } + else + { + DAC->CTRL_B.DMAUDRIEN2 = RESET; + } +} + +/*! + * @brief Reads the DAC status flag. + * + * @param flag: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_CH1_DMAUDR: DMA Channel1 underrun flag + * @arg DAC_FLAG_CH2_DMAUDR: DMA Channel2 underrun flag, only for APM32F072 and APM32F091 devices + * + * @retval The new state of DAC flag (SET or RESET). + * + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + */ +uint8_t DAC_ReadStatusFlag(DAC_FLAG_T flag) +{ + uint16_t status; + + status = (uint16_t)(DAC->STS & flag); + if (status == flag) + { + return SET; + } + else + return RESET; +} +/*! + * @brief Clears the DAC status flags. + * + * @param flag: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_CH1_DMAUDR: DMA Channel1 underrun flag + * @arg DAC_FLAG_CH2_DMAUDR: DMA Channel2 underrun flag, , only for APM32F072 and APM32F091 devices + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * + * @retval None + */ +void DAC_ClearStatusFlag(DAC_FLAG_T flag) +{ + DAC->STS &= (uint32_t)~flag; +} + +/*! + * @brief Reads teh DAC interrupt flag. + * + * @param intFlag: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_INT_CH1_DMAUDR: DMA Channel1 underrun interrupt mask + * @arg DAC_INT_CH2_DMAUDR: DMA Channel2 underrun interrupt mask, , only for APM32F072 and APM32F091 devices + * + * @retval The new state of DAC interrupt flag (SET or RESET). + * + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + */ +uint8_t DAC_ReadIntFlag(DAC_INT_T intFlag) +{ + uint32_t intEnable; + intEnable = (DAC->CTRL & intFlag); + if (((DAC->STS & intFlag) != (uint32_t)RESET) && intEnable) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the DAC channel's interrupt flag. + * + * @param intFlag: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_INT_CH1_DMAUDR: DMA Channel1 underrun interrupt mask + * @arg DAC_INT_CH2_DMAUDR: DMA Channel2 underrun interrupt mask, , only for APM32F072 and APM32F091 devices + * + * @retval None + */ +void DAC_ClearIntFlag(DAC_INT_T intFlag) +{ + DAC->STS = intFlag; +} + +/**@} end of group DAC_Functions */ +/**@} end of group DAC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dbg.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dbg.c new file mode 100644 index 0000000000..060a13026a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dbg.c @@ -0,0 +1,196 @@ +/*! + * @file apm32f0xx_dbg.c + * + * @brief This file provides all the DBG firmware functions + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_dbg.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup DBG_Driver + @{ +*/ + +/** @defgroup DBG_Macros Macros + @{ +*/ + +/**@} end of group DBG_Macros */ + +/** @defgroup DBG_Enumerations Enumerations + @{ +*/ + +/**@} end of group DBG_Enumerations*/ + +/** @defgroup DBG_Structures Structures + @{ +*/ + +/**@} end of group DBG_Structures */ + +/** @defgroup DBG_Variables Variables + @{ +*/ + +/**@} end of group DBG_Variables */ + +/** @defgroup DBG_Functions Functions + @{ +*/ + +/*! + * @brief Read Device Identifier + * + * @param None + * + * @retval The value of the Device Identifier + */ +uint32_t DBG_ReadDevId(void) +{ + return ((uint32_t)DBG->IDCODE_B.EQR); +} + +/*! + * @brief Read Revision Identifier + * + * @param None + * + * @retval The value of the Revision Identifier + */ +uint32_t DBG_ReadRevId(void) +{ + return ((uint32_t)DBG->IDCODE_B.WVR); +} + +/*! + * @brief Enable Debug Mode + * + * @param mode: specifies the low power mode. + * The parameter can be combination of following values: + * @arg DBG_MODE_STOP: Keep debugger connection during STOP mode + * @arg DBG_MODE_STANDBY: Keep debugger connection during STANDBY mode + * @retval None + */ +void DBG_EnableDebugMode(uint32_t mode) +{ + DBG->CFG |= (uint32_t)mode; +} + +/*! + * @brief Disable Debug Mode + * + * @param mode: specifies the low power mode. + * The parameter can be combination of following values: + * @arg DBG_MODE_STOP: Keep debugger connection during STOP mode + * @arg DBG_MODE_STANDBY: Keep debugger connection during STANDBY mode + * @retval None + */ +void DBG_DisableDebugMode(uint32_t mode) +{ + DBG->CFG &= (uint32_t)~mode; +} + +/*! + * @brief Enable APB1 peripheral in Debug mode. + * + * @param peripheral: Specifies the APB1 peripheral. + * The parameter can be combination of following values: + * @arg DBG_APB1_PER_TMR2_STOP: TMR2 counter stopped when Core is halted, Not for APM32F030 devices + * @arg DBG_APB1_PER_TMR3_STOP: TMR3 counter stopped when Core is halted + * @arg DBG_APB1_PER_TMR6_STOP: TMR6 counter stopped when Core is halted + * @arg DBG_APB1_PER_TMR7_STOP: TMR7 counter stopped when Core is haltedOnly for APM32F072 and APM32F091 devices + * @arg DBG_APB1_PER_TMR14_STOP: TMR14 counter stopped when Core is halted + * @arg DBG_APB1_PER_RTC_STOP: RTC counter stopped when Core is halted + * @arg DBG_APB1_PER_WWDT_STOP: Debug WWDT stopped when Core is halted + * @arg DBG_APB1_PER_IWDT_STOP: Debug IWDT stopped when Core is halted + * @arg DBG_APB1_PER_CAN_STOP: Debug CAN stopped when Core is haltedOnly for APM32F072 and APM32F091 devices + * @arg DBG_APB1_PER_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @retval None + */ +void DBG_EnableAPB1Periph(uint32_t peripheral) +{ + DBG->APB1F |= (uint32_t)peripheral; +} + +/*! + * @brief Disable APB1 peripheral in Debug mode. + * + * @param peripheral: Specifies the APB1 peripheral. + * The parameter can be combination of following values: + * @arg DBG_APB1_PER_TMR2_STOP: TMR2 counter stopped when Core is halted, Not for APM32F030 devices + * @arg DBG_APB1_PER_TMR3_STOP: TMR3 counter stopped when Core is halted + * @arg DBG_APB1_PER_TMR6_STOP: TMR6 counter stopped when Core is halted + * @arg DBG_APB1_PER_TMR7_STOP: TMR7 counter stopped when Core is haltedOnly for APM32F072 and APM32F091 devices + * @arg DBG_APB1_PER_TMR14_STOP: TMR14 counter stopped when Core is halted + * @arg DBG_APB1_PER_RTC_STOP: RTC counter stopped when Core is halted + * @arg DBG_APB1_PER_WWDT_STOP: Debug WWDT stopped when Core is halted + * @arg DBG_APB1_PER_IWDT_STOP: Debug IWDT stopped when Core is halted + * @arg DBG_APB1_PER_CAN_STOP: Debug CAN stopped when Core is haltedOnly for APM32F072 and APM32F091 devices + * @arg DBG_APB1_PER_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @retval None + */ +void DBG_DisableAPB1Periph(uint32_t peripheral) +{ + DBG->APB1F &= (uint32_t)~peripheral; +} + +/*! + * @brief Enable APB2 peripheral in Debug mode. + * + * @param peripheral: Specifies the APB2 peripheral. + * The parameter can be combination of following values: + * @arg DBG_APB2_PER_TMR1_STOP: TMR1 counter stopped when Core is halted + * @arg DBG_APB2_PER_TMR15_STOP: TMR15 counter stopped when Core is halted + * @arg DBG_APB2_PER_TMR16_STOP: TMR16 counter stopped when Core is halted + * @arg DBG_APB2_PER_TMR17_STOP: TMR17 counter stopped when Core is halted + * @retval None + */ +void DBG_EnableAPB2Periph(uint32_t peripheral) +{ + DBG->APB2F |= (uint32_t)peripheral; +} + +/*! + * @brief Disable APB2 peripheral in Debug mode. + * + * @param peripheral: Specifies the APB2 peripheral. + * The parameter can be combination of following values: + * @arg DBG_APB2_PER_TMR1_STOP: TMR1 counter stopped when Core is halted + * @arg DBG_APB2_PER_TMR15_STOP: TMR15 counter stopped when Core is halted + * @arg DBG_APB2_PER_TMR16_STOP: TMR16 counter stopped when Core is halted + * @arg DBG_APB2_PER_TMR17_STOP: TMR17 counter stopped when Core is halted + * + * @retval None + */ +void DBG_DisableAPB2Periph(uint32_t peripheral) +{ + DBG->APB2F &= (uint32_t)~peripheral; +} + +/**@} end of group DBG_Functions */ +/**@} end of group DBG_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dma.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dma.c new file mode 100644 index 0000000000..e7cc47e92e --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_dma.c @@ -0,0 +1,695 @@ +/*! + * @file apm32f0xx_dma.c + * + * @brief This file contains all the functions for the DMA peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_dma.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup DMA_Driver + @{ +*/ + +/** @defgroup DMA_Macros Macros + @{ + */ + +/**@} end of group DMA_Macros */ + +/** @defgroup DMA_Enumerates Enumerates + @{ + */ + +/**@} end of group DMA_Enumerates */ + +/** @defgroup DMA_Structures Structures + @{ + */ + +/**@} end of group DMA_Structures */ + +/** @defgroup DMA_Variables Variables + @{ + */ + +/**@} end of group DMA_Variables */ + +/** @defgroup DMA_Functions Functions + @{ + */ + +/*! + * @brief Set the DMA peripheral registers to their default reset values + * + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * @retval None + */ +void DMA_Reset(DMA_CHANNEL_T* channel) +{ + channel->CHCFG_B.CHEN = 0; + channel->CHCFG = 0; + channel->CHNDATA = 0; + channel->CHPADDR = 0; + channel->CHMADDR = 0; + + if (channel == DMA1_CHANNEL_1) + { + DMA1->INTFCLR = (uint32_t)0x0000000F; + } + else if (channel == DMA1_CHANNEL_2) + { + DMA1->INTFCLR = (uint32_t)0x000000F0; + } + else if (channel == DMA1_CHANNEL_3) + { + DMA1->INTFCLR = (uint32_t)0x00000F00; + } + else if (channel == DMA1_CHANNEL_4) + { + DMA1->INTFCLR = (uint32_t)0x0000F000; + } + else if (channel == DMA1_CHANNEL_5) + { + DMA1->INTFCLR = (uint32_t)0x000F0000; + } + else if (channel == DMA1_CHANNEL_6) + { + DMA1->INTFCLR = (uint32_t)0x00F00000; + } + else if (channel == DMA1_CHANNEL_7) + { + DMA1->INTFCLR = (uint32_t)0x0F000000; + } + else if (channel == DMA2_CHANNEL_1) + { + DMA2->INTFCLR = (uint32_t)0x0000000F; + } + else if (channel == DMA2_CHANNEL_2) + { + DMA2->INTFCLR = (uint32_t)0x000000F0; + } + else if (channel == DMA2_CHANNEL_3) + { + DMA2->INTFCLR = (uint32_t)0x00000F00; + } + else if (channel == DMA2_CHANNEL_4) + { + DMA2->INTFCLR = (uint32_t)0x0000F000; + } + else if (channel == DMA2_CHANNEL_5) + { + DMA2->INTFCLR = (uint32_t)0x000F0000; + } +} + +/*! + * @brief Config the DMA peripheral according to the specified parameters in the dmaConfig + * + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @param dmaConfig: Pointer to a DMA_Config_T structure that + * contains the configuration information for the DMA peripheral + * + * @retval None + */ +void DMA_Config(DMA_CHANNEL_T* channel, DMA_Config_T* dmaConfig) +{ + channel->CHCFG_B.DIRCFG = dmaConfig->direction; + channel->CHCFG_B.CIRMODE = dmaConfig->circular; + channel->CHCFG_B.M2MMODE = dmaConfig->memoryTomemory; + channel->CHCFG_B.CHPL = dmaConfig->priority; + channel->CHCFG_B.MIMODE = dmaConfig->memoryInc; + channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc; + channel->CHCFG_B.MSIZE = dmaConfig->memoryDataSize; + channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize; + + channel->CHNDATA = dmaConfig->bufferSize; + channel->CHMADDR = dmaConfig->memoryAddress; + channel->CHPADDR = dmaConfig->peripheralAddress; + +} + +/*! + * @brief Fills each dmaConfig member with its default value + * + * @param dmaConfig: Pointer to a DMA_Config_T structure which will be initialized + * + * @retval None + */ +void DMA_ConfigStructInit(DMA_Config_T* dmaConfig) +{ + dmaConfig->direction = DMA_DIR_PERIPHERAL; + dmaConfig->circular = DMA_CIRCULAR_DISABLE; + dmaConfig->memoryTomemory = DMA_M2M_DISABLE; + dmaConfig->priority = DMA_PRIORITY_LEVEL_LOW; + dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE; + dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE; + dmaConfig->memoryDataSize = DMA_MEMORY_DATASIZE_BYTE; + dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATASIZE_BYTE; + + dmaConfig->bufferSize = 0; + dmaConfig->memoryAddress = 0; + dmaConfig->peripheralAddress = 0; +} + +/*! + * @brief Enable the DMA peripheral + * + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @retval None + */ +void DMA_Enable(DMA_CHANNEL_T* channel) +{ + channel->CHCFG_B.CHEN = BIT_SET; +} + +/*! + * @brief Disable the DMA peripheral + * + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @retval None + */ +void DMA_Disable(DMA_CHANNEL_T* channel) +{ + channel->CHCFG_B.CHEN = BIT_RESET; +} + +/*! + * @brief Set the DMA Channelx transfer data of number + * + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @param dataNumber: The number of data units in the current DMA Channel transfer + * + * @retval None + */ +void DMA_SetDataNumber(DMA_CHANNEL_T* channel, uint32_t dataNumber) +{ + channel->CHNDATA = (uint32_t)dataNumber; +} + +/*! + * @brief Read the DMA Channelx transfer data of number + * + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @retval The number of data units in the current DMA Channel transfer + */ +uint32_t DMA_ReadDataNumber(DMA_CHANNEL_T* channel) +{ + return ((uint32_t)channel->CHNDATA); +} + +/*! + * @brief Configure the DMA channels remapping. + * + * @param dma: Select the the DMA peripheral. + It can be DMA1/DMA2. + * + * @param remap: Select the the DMA_CHANNEL_REMAP_T. + When select DMA1, the DMA channel can be 1 to 7. + * When select DMA2, the DMA channel can be 1 to 5. + * + * @retval It's only for APM32F091 devices. + */ +void DMA_ConfigRemap(DMA_T* dma, DMA_CHANNEL_REMAP_T remap) +{ + dma->CHSEL &= ~((uint32_t)0x0F << (uint32_t)(remap >> 28) * 4); + dma->CHSEL |= (uint32_t)(remap & 0x0FFFFFFF); +} + +/*! + * @brief Enables the specified interrupts + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @param interrupt: Specifies the DMA interrupts sources + * The parameter can be combination of following values: + * @arg DMA_INT_TFIE: Transfer complete interrupt + * @arg DMA_INT_HTIE: Half Transfer interrupt + * @arg DMA_INT_TEIE: Transfer error interrupt + * + * @retval None + */ +void DMA_EnableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt) +{ + channel->CHCFG |= (uint32_t)interrupt; +} + +/*! + * @brief Disables the specified interrupts + * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that + * set DMA channel for the DMA peripheral + * This parameter can be one of the following values: + * @arg DMA1_CHANNEL_1 + * @arg DMA1_CHANNEL_2 + * @arg DMA1_CHANNEL_3 + * @arg DMA1_CHANNEL_4 + * @arg DMA1_CHANNEL_5 + * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091) + * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091) + * @arg DMA2_CHANNEL_1(only for APM32F091) + * @arg DMA2_CHANNEL_2(only for APM32F091) + * @arg DMA2_CHANNEL_3(only for APM32F091) + * @arg DMA2_CHANNEL_4(only for APM32F091) + * @arg DMA2_CHANNEL_5(only for APM32F091) + * + * @param interrupt: Specifies the DMA interrupts sources + * The parameter can be combination of following values: + * @arg DMA_INT_TFIE: Transfer complete interrupt + * @arg DMA_INT_HTIE: Half Transfer interrupt + * @arg DMA_INT_TEIE: Transfer error interrupt + * + * @retval None + */ +void DMA_DisableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt) +{ + channel->CHCFG &= (uint32_t)~interrupt; +} + +/*! + * @brief Checks whether the specified DMA flag is set or not + * + * @param flag: Specifies the flag to check + * This parameter can be one of the following values: + * @arg DMA1_FLAG_AL1: DMA1 Channel 1 All flag + * @arg DMA1_FLAG_TF1: DMA1 Channel 1 Transfer Complete flag + * @arg DMA1_FLAG_HT1: DMA1 Channel 1 Half Transfer Complete flag + * @arg DMA1_FLAG_TE1: DMA1 Channel 1 Transfer Error flag + * @arg DMA1_FLAG_AL2: DMA1 Channel 2 All flag + * @arg DMA1_FLAG_TF2: DMA1 Channel 2 Transfer Complete flag + * @arg DMA1_FLAG_HT2: DMA1 Channel 2 Half Transfer Complete flag + * @arg DMA1_FLAG_TE2: DMA1 Channel 2 Transfer Error flag + * @arg DMA1_FLAG_AL3: DMA1 Channel 3 All flag + * @arg DMA1_FLAG_TF3: DMA1 Channel 3 Transfer Complete flag + * @arg DMA1_FLAG_HT3: DMA1 Channel 3 Half Transfer Complete flag + * @arg DMA1_FLAG_TE3: DMA1 Channel 3 Transfer Error flag + * @arg DMA1_FLAG_AL4: DMA1 Channel 4 All flag + * @arg DMA1_FLAG_TF4: DMA1 Channel 4 Transfer Complete flag + * @arg DMA1_FLAG_HT4: DMA1 Channel 4 Half Transfer Complete flag + * @arg DMA1_FLAG_TE4: DMA1 Channel 4 Transfer Error flag + * @arg DMA1_FLAG_AL5: DMA1 Channel 5 All flag + * @arg DMA1_FLAG_TF5: DMA1 Channel 5 Transfer Complete flag + * @arg DMA1_FLAG_HT5: DMA1 Channel 5 Half Transfer Complete flag + * @arg DMA1_FLAG_TE5: DMA1 Channel 5 Transfer Error flag + * Below is only for APM32F072 and APM32F091 devices: + * @arg DMA1_FLAG_AL6: DMA1 Channel 6 All flag + * @arg DMA1_FLAG_TF6: DMA1 Channel 6 Transfer Complete flag + * @arg DMA1_FLAG_HT6: DMA1 Channel 6 Half Transfer Complete flag + * @arg DMA1_FLAG_TE6: DMA1 Channel 6 Transfer Error flag + * @arg DMA1_FLAG_AL7: DMA1 Channel 7 All flag + * @arg DMA1_FLAG_TF7: DMA1 Channel 7 Transfer Complete flag + * @arg DMA1_FLAG_HT7: DMA1 Channel 7 Half Transfer Complete flag + * @arg DMA1_FLAG_TE7: DMA1 Channel 7 Transfer Error flag + * Below is only for APM32F091 devices: + * @arg DMA2_FLAG_AL1: DMA2 Channel 1 All flag + * @arg DMA2_FLAG_TF1: DMA2 Channel 1 Transfer Complete flag + * @arg DMA2_FLAG_HT1: DMA2 Channel 1 Half Transfer Complete flag + * @arg DMA2_FLAG_TE1: DMA2 Channel 1 Transfer Error flag + * @arg DMA2_FLAG_AL2: DMA2 Channel 2 All flag + * @arg DMA2_FLAG_TF2: DMA2 Channel 2 Transfer Complete flag + * @arg DMA2_FLAG_HT2: DMA2 Channel 2 Half Transfer Complete flag + * @arg DMA2_FLAG_TE2: DMA2 Channel 2 Transfer Error flag + * @arg DMA2_FLAG_AL3: DMA2 Channel 3 All flag + * @arg DMA2_FLAG_TF3: DMA2 Channel 3 Transfer Complete flag + * @arg DMA2_FLAG_HT3: DMA2 Channel 3 Half Transfer Complete flag + * @arg DMA2_FLAG_TE3: DMA2 Channel 3 Transfer Error flag + * @arg DMA2_FLAG_AL4: DMA2 Channel 4 All flag + * @arg DMA2_FLAG_TF4: DMA2 Channel 4 Transfer Complete flag + * @arg DMA2_FLAG_HT4: DMA2 Channel 4 Half Transfer Complete flag + * @arg DMA2_FLAG_TE4: DMA2 Channel 4 Transfer Error flag + * @arg DMA2_FLAG_AL5: DMA2 Channel 5 All flag + * @arg DMA2_FLAG_TF5: DMA2 Channel 5 Transfer Complete flag + * @arg DMA2_FLAG_HT5: DMA2 Channel 5 Half Transfer Complete flag + * @arg DMA2_FLAG_TE5: DMA2 Channel 5 Transfer Error flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag) +{ + uint32_t status; + + if ((flag & 0x10000000) == SET) + { + status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF); + } + else + { + status = DMA1->INTSTS & ((uint32_t)flag & 0x0FFFFFFF); + } + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear whether the specified DMA flag is set or not + * + * @param flag: Specifies the flag to Clear + * This parameter can be any combination of the following values: + * @arg DMA1_FLAG_AL1: DMA1 Channel 1 All flag + * @arg DMA1_FLAG_TF1: DMA1 Channel 1 Transfer Complete flag + * @arg DMA1_FLAG_HT1: DMA1 Channel 1 Half Transfer Complete flag + * @arg DMA1_FLAG_TE1: DMA1 Channel 1 Transfer Error flag + * @arg DMA1_FLAG_AL2: DMA1 Channel 2 All flag + * @arg DMA1_FLAG_TF2: DMA1 Channel 2 Transfer Complete flag + * @arg DMA1_FLAG_HT2: DMA1 Channel 2 Half Transfer Complete flag + * @arg DMA1_FLAG_TE2: DMA1 Channel 2 Transfer Error flag + * @arg DMA1_FLAG_AL3: DMA1 Channel 3 All flag + * @arg DMA1_FLAG_TF3: DMA1 Channel 3 Transfer Complete flag + * @arg DMA1_FLAG_HT3: DMA1 Channel 3 Half Transfer Complete flag + * @arg DMA1_FLAG_TE3: DMA1 Channel 3 Transfer Error flag + * @arg DMA1_FLAG_AL4: DMA1 Channel 4 All flag + * @arg DMA1_FLAG_TF4: DMA1 Channel 4 Transfer Complete flag + * @arg DMA1_FLAG_HT4: DMA1 Channel 4 Half Transfer Complete flag + * @arg DMA1_FLAG_TE4: DMA1 Channel 4 Transfer Error flag + * @arg DMA1_FLAG_AL5: DMA1 Channel 5 All flag + * @arg DMA1_FLAG_TF5: DMA1 Channel 5 Transfer Complete flag + * @arg DMA1_FLAG_HT5: DMA1 Channel 5 Half Transfer Complete flag + * @arg DMA1_FLAG_TE5: DMA1 Channel 5 Transfer Error flag + * Below is only for APM32F072 and APM32F091 devices: + * @arg DMA1_FLAG_AL6: DMA1 Channel 6 All flag + * @arg DMA1_FLAG_TF6: DMA1 Channel 6 Transfer Complete flag + * @arg DMA1_FLAG_HT6: DMA1 Channel 6 Half Transfer Complete flag + * @arg DMA1_FLAG_TE6: DMA1 Channel 6 Transfer Error flag + * @arg DMA1_FLAG_AL7: DMA1 Channel 7 All flag + * @arg DMA1_FLAG_TF7: DMA1 Channel 7 Transfer Complete flag + * @arg DMA1_FLAG_HT7: DMA1 Channel 7 Half Transfer Complete flag + * @arg DMA1_FLAG_TE7: DMA1 Channel 7 Transfer Error flag + * Below is only for APM32F091 devices: + * @arg DMA2_FLAG_AL1: DMA2 Channel 1 All flag + * @arg DMA2_FLAG_TF1: DMA2 Channel 1 Transfer Complete flag + * @arg DMA2_FLAG_HT1: DMA2 Channel 1 Half Transfer Complete flag + * @arg DMA2_FLAG_TE1: DMA2 Channel 1 Transfer Error flag + * @arg DMA2_FLAG_AL2: DMA2 Channel 2 All flag + * @arg DMA2_FLAG_TF2: DMA2 Channel 2 Transfer Complete flag + * @arg DMA2_FLAG_HT2: DMA2 Channel 2 Half Transfer Complete flag + * @arg DMA2_FLAG_TE2: DMA2 Channel 2 Transfer Error flag + * @arg DMA2_FLAG_AL3: DMA2 Channel 3 All flag + * @arg DMA2_FLAG_TF3: DMA2 Channel 3 Transfer Complete flag + * @arg DMA2_FLAG_HT3: DMA2 Channel 3 Half Transfer Complete flag + * @arg DMA2_FLAG_TE3: DMA2 Channel 3 Transfer Error flag + * @arg DMA2_FLAG_AL4: DMA2 Channel 4 All flag + * @arg DMA2_FLAG_TF4: DMA2 Channel 4 Transfer Complete flag + * @arg DMA2_FLAG_HT4: DMA2 Channel 4 Half Transfer Complete flag + * @arg DMA2_FLAG_TE4: DMA2 Channel 4 Transfer Error flag + * @arg DMA2_FLAG_AL5: DMA2 Channel 5 All flag + * @arg DMA2_FLAG_TF5: DMA2 Channel 5 Transfer Complete flag + * @arg DMA2_FLAG_HT5: DMA2 Channel 5 Half Transfer Complete flag + * @arg DMA2_FLAG_TE5: DMA2 Channel 5 Transfer Error flag + * + * @retval None + */ + +void DMA_ClearStatusFlag(uint32_t flag) +{ + if ((flag & 0x10000000) == SET) + { + DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF); + } + else + { + DMA1->INTFCLR |= (uint32_t)(flag & 0x0FFFFFFF); + } +} + +/*! + * @brief Checks whether the specified interrupt has occurred or not + * + * @param flag: Specifies the DMA interrupt pending bit to check + * The parameter can be one following values: + * @arg DMA1_INT_FLAG_AL1: DMA1_Channel 1 All interrupt flag + * @arg DMA1_INT_FLAG_TF1: DMA1_Channel 1 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT1: DMA1_Channel 1 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE1: DMA1_Channel 1 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL2: DMA1_Channel 2 All interrupt flag + * @arg DMA1_INT_FLAG_TF2: DMA1_Channel 2 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT2: DMA1_Channel 2 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE2: DMA1_Channel 2 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL3: DMA1_Channel 3 All interrupt flag + * @arg DMA1_INT_FLAG_TF3: DMA1_Channel 3 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT3: DMA1_Channel 3 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE3: DMA1_Channel 3 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL4: DMA1_Channel 4 All interrupt flag + * @arg DMA1_INT_FLAG_TF4: DMA1_Channel 4 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT4: DMA1_Channel 4 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE4: DMA1_Channel 4 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL5: DMA1_Channel 5 All interrupt flag + * @arg DMA1_INT_FLAG_TF5: DMA1_Channel 5 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT5: DMA1_Channel 5 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE5: DMA1_Channel 5 Transfer Error interrupt flag + * Below is only for APM32F072 and APM32F091 devices: + * @arg DMA1_INT_FLAG_AL6: DMA1_Channel 6 All interrupt flag + * @arg DMA1_INT_FLAG_TF6: DMA1_Channel 6 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT6: DMA1_Channel 6 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE6: DMA1_Channel 6 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL7: DMA1_Channel 7 All interrupt flag + * @arg DMA1_INT_FLAG_TF7: DMA1_Channel 7 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT7: DMA1_Channel 7 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE7: DMA1_Channel 7 Transfer Error interrupt flag + * Below is only for APM32F091 devices: + * @arg DMA2_INT_FLAG_AL1: DMA2_Channel 1 All interrupt flag + * @arg DMA2_INT_FLAG_TF1: DMA2_Channel 1 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT1: DMA2_Channel 1 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE1: DMA2_Channel 1 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL2: DMA2_Channel 2 All interrupt flag + * @arg DMA2_INT_FLAG_TF2: DMA2_Channel 2 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT2: DMA2_Channel 2 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE2: DMA2_Channel 2 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL3: DMA2_Channel 3 All interrupt flag + * @arg DMA2_INT_FLAG_TF3: DMA2_Channel 3 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT3: DMA2_Channel 3 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE3: DMA2_Channel 3 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL4: DMA2_Channel 4 All interrupt flag + * @arg DMA2_INT_FLAG_TF4: DMA2_Channel 4 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT4: DMA2_Channel 4 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE4: DMA2_Channel 4 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL5: DMA2_Channel 5 All interrupt flag + * @arg DMA2_INT_FLAG_TF5: DMA2_Channel 5 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT5: DMA2_Channel 5 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE5: DMA2_Channel 5 Transfer Error interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag) +{ + uint32_t status; + + if ((flag & 0x10000000) == SET) + { + status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF); + } + else + { + status = DMA1->INTSTS & ((uint32_t)flag & 0x0FFFFFFF); + } + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the specified interrupt pending bits + * + * @param flag: Specifies the DMA interrupt pending bit to clear + * The parameter can be combination of following values: + * @arg DMA1_INT_FLAG_AL1: DMA1_Channel 1 All interrupt flag + * @arg DMA1_INT_FLAG_TF1: DMA1_Channel 1 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT1: DMA1_Channel 1 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE1: DMA1_Channel 1 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL2: DMA1_Channel 2 All interrupt flag + * @arg DMA1_INT_FLAG_TF2: DMA1_Channel 2 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT2: DMA1_Channel 2 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE2: DMA1_Channel 2 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL3: DMA1_Channel 3 All interrupt flag + * @arg DMA1_INT_FLAG_TF3: DMA1_Channel 3 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT3: DMA1_Channel 3 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE3: DMA1_Channel 3 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL4: DMA1_Channel 4 All interrupt flag + * @arg DMA1_INT_FLAG_TF4: DMA1_Channel 4 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT4: DMA1_Channel 4 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE4: DMA1_Channel 4 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL5: DMA1_Channel 5 All interrupt flag + * @arg DMA1_INT_FLAG_TF5: DMA1_Channel 5 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT5: DMA1_Channel 5 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE5: DMA1_Channel 5 Transfer Error interrupt flag + * Below is only for APM32F072 and APM32F091 devices: + * @arg DMA1_INT_FLAG_AL6: DMA1_Channel 6 All interrupt flag + * @arg DMA1_INT_FLAG_TF6: DMA1_Channel 6 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT6: DMA1_Channel 6 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE6: DMA1_Channel 6 Transfer Error interrupt flag + * @arg DMA1_INT_FLAG_AL7: DMA1_Channel 7 All interrupt flag + * @arg DMA1_INT_FLAG_TF7: DMA1_Channel 7 Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_HT7: DMA1_Channel 7 Half Transfer Complete interrupt flag + * @arg DMA1_INT_FLAG_TE7: DMA1_Channel 7 Transfer Error interrupt flag + * Below is only for APM32F091 devices: + * @arg DMA2_INT_FLAG_AL1: DMA2_Channel 1 All interrupt flag + * @arg DMA2_INT_FLAG_TF1: DMA2_Channel 1 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT1: DMA2_Channel 1 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE1: DMA2_Channel 1 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL2: DMA2_Channel 2 All interrupt flag + * @arg DMA2_INT_FLAG_TF2: DMA2_Channel 2 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT2: DMA2_Channel 2 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE2: DMA2_Channel 2 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL3: DMA2_Channel 3 All interrupt flag + * @arg DMA2_INT_FLAG_TF3: DMA2_Channel 3 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT3: DMA2_Channel 3 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE3: DMA2_Channel 3 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL4: DMA2_Channel 4 All interrupt flag + * @arg DMA2_INT_FLAG_TF4: DMA2_Channel 4 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT4: DMA2_Channel 4 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE4: DMA2_Channel 4 Transfer Error interrupt flag + * @arg DMA2_INT_FLAG_AL5: DMA2_Channel 5 All interrupt flag + * @arg DMA2_INT_FLAG_TF5: DMA2_Channel 5 Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_HT5: DMA2_Channel 5 Half Transfer Complete interrupt flag + * @arg DMA2_INT_FLAG_TE5: DMA2_Channel 5 Transfer Error interrupt flag + * + * @retval None + */ +void DMA_ClearIntFlag(uint32_t flag) +{ + if ((flag & 0x10000000) == SET) + { + DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF); + } + else + { + DMA1->INTFCLR |= (uint32_t)(flag & 0x0FFFFFFF); + } +} + +/**@} end of group DMA_Functions */ +/**@} end of group DMA_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ + diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_eint.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_eint.c new file mode 100644 index 0000000000..4232c160c0 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_eint.c @@ -0,0 +1,231 @@ +/*! + * @file apm32f0xx_eint.c + * + * @brief This file contains all the functions for the EINT peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_eint.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ + */ + +/** @addtogroup EINT_Driver + @{ + */ + +/** @defgroup EINT_Macros Macros + @{ + */ + +/**@} end of group EINT_Macros */ + +/** @defgroup EINT_Enumerates Enumerates + @{ + */ + +/**@} end of group EINT_Enumerates */ + +/** @defgroup EINT_Structures Structures + @{ + */ + +/**@} end of group EINT_Structures */ + +/** @defgroup EINT_Variables Variables + @{ + */ + +/**@} end of group EINT_Variables */ + +/** @defgroup EINT_Functions Functions + @{ + */ + +/*! + * @brief Set the EINT peripheral registers to their default reset values + * + * @param None + * + * @retval None + */ +void EINT_Reset(void) +{ + EINT->IMASK = EINT_INTMASK_RESET_VALUE; + EINT->EMASK = EINT_EVTMASK_RESET_VALUE; + EINT->RTEN = EINT_RTSEL_RESET_VALUE; + EINT->FTEN = EINT_FTSEL_RESET_VALUE; + EINT->IPEND = EINT_PEND_RESET_VALUE; +} + +/*! + * @brief Configure the EINT + * + * @param eintConfig: Pointer to EINT_Config_T structure + * + * @retval None + */ +void EINT_Config(EINT_Config_T* eintConfig) +{ + if (eintConfig->lineCmd == DISABLE) + { + if (eintConfig->mode == EINT_MODE_INTERRUPT) + { + EINT->IMASK &= ~eintConfig->line; + } + else if (eintConfig->mode == EINT_MODE_EVENT) + { + EINT->EMASK &= ~eintConfig->line; + } + } + else + { + if (eintConfig->mode == EINT_MODE_INTERRUPT) + { + EINT->IMASK |= eintConfig->line; + } + else if (eintConfig->mode == EINT_MODE_EVENT) + { + EINT->EMASK |= eintConfig->line; + } + + if (eintConfig->trigger == EINT_TRIGGER_RISING) + { + EINT->RTEN |= eintConfig->line; + } + else if (eintConfig->trigger == EINT_TRIGGER_FALLING) + { + EINT->FTEN |= eintConfig->line; + } + else + { + EINT->RTEN |= eintConfig->line; + EINT->FTEN |= eintConfig->line; + } + + } +} + +/*! + * @brief Fills each EINT_Config_T member with its default value + * + * @param eintConfig: Pointer to a EINT_Config_T structure which will be initialized + * + * @retval None + */ +void EINT_ConfigStructInit(EINT_Config_T* eintConfig) +{ + eintConfig->line = EINT_LINENONE; + eintConfig->mode = EINT_MODE_INTERRUPT; + eintConfig->trigger = EINT_TRIGGER_FALLING; + eintConfig->lineCmd = DISABLE; +} + +/*! + * @brief Select software interrupt on EINT line + * + * @param line: specifies the EINT line on which the software interrupt + * + * @retval None + */ +void EINT_SelectSWInterrupt(uint32_t line) +{ + EINT->SWINTE |= (uint32_t)line; +} + +/*! + * @brief Read the specified EINT line flag + * + * @param line: Select the EINT line + * + * @retval status: The new state of flag (SET or RESET) + */ +uint8_t EINT_ReadStatusFlag(uint32_t line) +{ + uint8_t status = RESET; + + if ((EINT->IPEND & line) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/*! + * @brief Clears the EINT line pending bits + * + * @param line: Select the EINT line + * + * @retval None + */ +void EINT_ClearStatusFlag(uint32_t line) +{ + EINT->IPEND = line; +} + +/*! + * @brief Read the specified EINT line interrupt flag + * + * @param line: Select the EINT line + * + * @retval None + */ +uint8_t EINT_ReadIntFlag(uint32_t line) +{ + uint8_t status = RESET; + uint32_t enablestatus = 0; + + enablestatus = EINT->IMASK & line; + + if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/*! + * @brief Clears the EINT line pending bits + * + * @param line: Select the EINT line + * + * @retval None + */ +void EINT_ClearIntFlag(uint32_t line) +{ + EINT->IPEND = line; +} + +/**@} end of group EINT_Functions */ +/**@} end of group EINT_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_fmc.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_fmc.c new file mode 100644 index 0000000000..e5aa8143fb --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_fmc.c @@ -0,0 +1,1005 @@ +/*! + * @file apm32f0xx_fmc.c + * + * @brief This file provides all the FMC firmware functions + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_fmc.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup FMC_Driver + @{ +*/ + +/** @defgroup FMC_Macros Macros + @{ + */ + +/**@} end of group FMC_Macros */ + +/** @defgroup FMC_Enumerates Enumerates + @{ + */ + +/**@} end of group FMC_Enumerates */ + +/** @defgroup FMC_Structures Structures + @{ + */ + +/**@} end of group FMC_Structures */ + +/** @defgroup FMC_Variables Variables + @{ + */ + +/**@} end of group FMC_Variables */ + +/** @defgroup FMC_Functions Functions + @{ + */ + +/*! + * @brief Sets the code latency value. + * + * @param latency: the flash latency value. + * The parameter can be one of following values: + * @arg FMC_LATENCY_0 + * @arg FMC_LATENCY_1 + * @retval None + */ +void FMC_SetLatency(FMC_LATENCY_T latency) +{ + FMC->CTRL1_B.WS = latency; +} + +/*! + * @brief Enables the Prefetch Buffer. + * + * @param None + * + * @retval None + */ +void FMC_EnablePrefetchBuffer(void) +{ + FMC->CTRL1_B.PBEN = ENABLE; +} + +/*! + * @brief Disables the Prefetch Buffer. + * + * @param None + * + * @retval None + */ +void FMC_DisablePrefetchBuffer(void) +{ + FMC->CTRL1_B.PBEN = DISABLE; +} + +/*! + * @brief Checks whether the flash Prefetch Buffer status is set or not + * + * @param None + * + * @retval flash Prefetch Buffer Status (SET or RESET) + */ +uint8_t FMC_ReadPrefetchBufferStatus(void) +{ + if (FMC->CTRL1_B.PBSF) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Unlocks the flash Program Erase Controller + * + * @param None + * + * @retval None + */ +void FMC_Unlock(void) +{ + FMC->KEY = FMC_KEY_1; + FMC->KEY = FMC_KEY_2; +} + +/*! + * @brief Locks the flash Program Erase Controller + * + * @param None + * + * @retval None + */ +void FMC_Lock(void) +{ + FMC->CTRL2_B.LOCK = BIT_SET; +} + +/*! + * @brief Read flash state + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_BUSY + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + */ +FMC_STATE_T FMC_ReadState(void) +{ + uint32_t status; + FMC_STATE_T state = FMC_STATE_COMPLETE; + + status = FMC->STS; + + if (status & FMC_FLAG_PE) + { + state = FMC_STATE_PG_ERR; + } + else if (status & FMC_FLAG_WPE) + { + state = FMC_STATE_WRP_ERR; + } + else if (status & FMC_FLAG_BUSY) + { + state = FMC_STATE_BUSY; + } + + return state; +} + +/*! + * @brief Wait for flash controler ready + * + * @param timeOut: Specifies the time to wait + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_BUSY + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOUT + */ +FMC_STATE_T FMC_WaitForReady(uint32_t timeOut) +{ + FMC_STATE_T state; + + do + { + state = FMC_ReadState(); + timeOut--; + } + while ((state == FMC_STATE_BUSY) && (timeOut)); + + if (!timeOut) + { + state = FMC_STATE_TIMEOUT; + } + + return state; +} + +/*! + * @brief Erases a specified flash page + * + * @param pageAddr: Specifies the page address + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOUT + */ +FMC_STATE_T FMC_ErasePage(uint32_t pageAddr) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.PAGEERA = BIT_SET; + + FMC->ADDR = pageAddr; + + FMC->CTRL2_B.STA = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + FMC->CTRL2_B.PAGEERA = BIT_RESET; + } + + return state; +} + +/*! + * @brief Erases all flash pages + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOUT + * @note + */ +FMC_STATE_T FMC_EraseAllPages(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.MASSERA = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + FMC->CTRL2_B.MASSERA = BIT_RESET; + } + + return state; +} + +/*! + * @brief Program a word at a specified address + * + * @param addr: Specifies the address to be programmed + * + * @param data: Specifies the data to be programmed + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOUT + */ +FMC_STATE_T FMC_ProgramWord(uint32_t addr, uint32_t data) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.PG = BIT_SET; + + *(__IO uint16_t*)addr = (uint16_t)data; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state == FMC_STATE_COMPLETE) + { + *(__IO uint16_t*)(addr + 2) = (uint16_t)(data >> 16); + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + } + + FMC->CTRL2_B.PG = BIT_RESET; + } + + return state; +} + +/*! + * @brief Programs a half word at a specified address + * + * @param addr: Specifies the address to be programmed + * + * @param data: Specifies the data to be programmed + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOUT + */ +FMC_STATE_T FMC_ProgramHalfWord(uint32_t addr, uint16_t data) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.PG = BIT_SET; + + *(__IO uint16_t*)addr = data; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + FMC->CTRL2_B.PG = BIT_RESET; + } + + return state; +} + +/*! + * @brief Unlocks the option bytes block access + * + * @param None + * + * @retval None + */ +void FMC_UnlockOptionByte(void) +{ + FMC->OBKEY = FMC_OB_KEY_1; + FMC->OBKEY = FMC_OB_KEY_2; +} + +/*! + * @brief Locks the option bytes block access + * + * @param None + * + * @retval None + */ +void FMC_LockOptionByte(void) +{ + FMC->CTRL2_B.OBWEN = BIT_RESET; +} + +/*! + * @brief Launch the option byte loading + * + * @param None + * + * @retval None + */ +void FMC_LaunchOptionByte(void) +{ + FMC->CTRL2_B.OBLOAD = BIT_SET; +} + +/*! + * @brief Erase the flash option bytes + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOUT + */ +FMC_STATE_T FMC_EraseOptionByte(void) +{ + uint16_t rpKey; + FMC_STATE_T state; + + rpKey = FMC->OBCS_B.READPROT ? 0 : FMC_RP_KEY; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->OBKEY = FMC_KEY_1; + FMC->OBKEY = FMC_KEY_2; + + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + + FMC->CTRL2_B.OBP = BIT_SET; + + OB->READPROT = rpKey; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBE = BIT_RESET; + } + } + + return state; +} + +/*! + * @brief Enable the specified page write protection + * + * @param page: Specifies the address of the pages to be write protected + * This parameter can be any combination of the flowing values: + * @arg FMC_WRP_PAGE_0_1 ... FMC_WRP_PAGE_60_61 + * @arg FMC_WRP_PAGE_ALL + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_EnableWriteProtection(uint32_t page) +{ + uint8_t i; + uint16_t temp; + __IO uint16_t* WRPT; + FMC_STATE_T state; + + WRPT = &OB->WRTPROT0; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state == FMC_STATE_COMPLETE) + { + FMC->OBKEY = FMC_KEY_1; + FMC->OBKEY = FMC_KEY_2; + + FMC->CTRL2_B.OBP = BIT_SET; + + for (i = 0; i < 4; i++) + { + temp = (uint16_t)~(page & 0xff); + + if ((temp != 0xff) && (state == FMC_STATE_COMPLETE)) + { + WRPT[i] = temp; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + } + + page >>= 8; + } + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; +} + +/*! + * @brief Read out protection configuration. + * + * @param rdp: specifies the read protection level + * This parameter can be any combination of the flowing values: + * @arg FMC_RDP_LEVEL_0 + * @arg FMC_RDP_LEVEL_1 + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_ConfigReadOutProtection(FMC_RDP_T rdp) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->OBKEY = FMC_KEY_1; + FMC->OBKEY = FMC_KEY_2; + + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + + FMC->CTRL2_B.OBP = BIT_SET; + + OB->READPROT = rdp; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBE = BIT_SET; + } + } + + return state; +} + +/*! + * @brief User option byte configuration + * + * @param userConfig: Pointer to a FMC_UserConfig_T structure that + * contains the configuration information for User option byte + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_ConfigOptionByteUser(FMC_UserConfig_T* userConfig) +{ + FMC_STATE_T state; + uint16_t temp; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state == FMC_STATE_COMPLETE) + { + FMC->OBKEY = FMC_OB_KEY_1; + FMC->OBKEY = FMC_OB_KEY_2; + + FMC->CTRL2_B.OBP = BIT_SET; + + temp = (uint32_t)userConfig->iwdtSw | \ + (uint32_t)userConfig->stopce | \ + (uint32_t)userConfig->stdbyce | 0xF8; + + OB->USER = temp; + + state = FMC_WaitForReady(FMC_DELAY_PROGRAM); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; +} + +/*! + * @brief Enable the BOOT1 option bit + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_EnableOptionByteBOOT(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER_B.BOT1 = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; +} + +/*! + * @brief Disable the BOOT1 option bit + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_DisableOptionByteBOOT(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER_B.BOT1 = BIT_RESET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} + +/*! + * @brief Enable the analogue monitoring on VDDA Power source + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_EnableOptionByteVDDA(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER_B.VDDAMON = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} + +/*! + * @brief Disable the analogue monitoring on VDDA Power source + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_DisableOptionByteVDDA(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER_B.VDDAMON = BIT_RESET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} + +/*! + * @brief Enable the SRAM parity + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_EnableOptionByteSRAMParity(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER_B.RPC = BIT_SET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} + +/*! + * @brief Disable the SRAM parity + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_DisableOptionByteSRAMParity(void) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER_B.RPC = BIT_RESET; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} +/*! + * @brief Programs the FMC User Option Byte: WDT, STOP, STDBY, + * BOOT1 and VDDA ANALOG monitoring + * + * @param ob_user: Selects all user option bytes + * This parameter is a combination of the following values: + * @arg FMC_OB_IWDT_HW / FMC_OB_IWDT_SW + * @arg FMC_OB_STOP_RESET / FMC_OB_STOP_NRST + * @arg FMC_OB_STDBY_RESET / FMC_OB_STDBY_NRST + * @arg FMC_OB_BOOT0_RESET / FMC_OB_BOOT0_SET + * @arg FMC_OB_BOOT1_RESET / FMC_OB_BOOT1_SET + * @arg FMC_OB_VDDA_ANALOG_OFF / FMC_OB_VDDA_ANALOG_ON + * @arg FMC_OB_SRAM_PARITY_SET / FMC_OB_SRAM_PARITY_RESET + * @arg FMC_OB_BOOT0_SW / FMC_OB_BOOT0_HW + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_WriteOptionByteUser(uint8_t ob_user) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + OB->USER = ob_user; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} + +/*! + * @brief Programs a half word at a specified Option Byte Data address + * + * @param addr: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param data: specifies the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATE_COMPLETE + * @arg FMC_STATE_PG_ERR + * @arg FMC_STATE_WRP_ERR + * @arg FMC_STATE_TIMEOU + */ +FMC_STATE_T FMC_ProgramOptionByteData(uint32_t addr, uint8_t data) +{ + FMC_STATE_T state; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state == FMC_STATE_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + + *(__IO uint16_t*)addr = data; + + state = FMC_WaitForReady(FMC_DELAY_ERASE); + + if (state != FMC_STATE_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + + return state; + +} + +/*! + * @brief Returns the Flash User Option Bytes values + * + * @param None + * + * @retval The flash User Option Bytes + */ +uint8_t FMC_ReadOptionByteUser(void) +{ + return (uint8_t)(FMC->OBCS >> 8); +} + +/*! + * @brief Returns the flash Write Protection Option Bytes value: + * + * @param None + * + * @retval The Flash Write Protection Option Bytes value: + */ +uint32_t FMC_ReadOptionByteWriteProtection(void) +{ + return (uint32_t)(FMC->WRTPROT); +} + +/*! + * @brief Checks whether the Flash Read Protection Status is set or not + * + * @param None + * + * @retval Flash ReadOut Protection Status(SET or RESET) + */ +uint8_t FMC_GetReadProtectionStatus(void) +{ + if (FMC->OBCS_B.READPROT) + { + return SET; + } + + return RESET; +} +/*! + * @brief Enable the specified flash interrupts + * + * @param interrupt: Specifies the flash interrupt sources + * The parameter can be combination of following values: + * @arg FMC_INT_ERROR: Error interruption + * @arg FMC_INT_COMPLETE: operation complete interruption + * + * @retval None + */ +void FMC_EnableInterrupt(uint32_t interrupt) +{ + FMC->CTRL2 |= interrupt; +} + +/*! + * @brief Disable the specified flash interrupts + * + * @param interrupt: Specifies the flash interrupt sources + * The parameter can be combination of following values: + * @arg FMC_INT_ERROR: Error interruption + * @arg FMC_INT_COMPLETE: operation complete interruption + * + * @retval None + */ +void FMC_DisableInterrupt(uint32_t interrupt) +{ + FMC->CTRL2 &= ~interrupt; +} + +/*! + * @brief Checks whether the specified flash flag is set or not + * + + * @param flag: Specifies the flash flag to check + * The parameter can be one of following values: + * @arg FMC_FLAG_BUSY: Busy flag + * @arg FMC_FLAG_PE: Program error flag + * @arg FMC_FLAG_WPE: Write protection flag + * @arg FMC_FLAG_OC: Operation complete flag + * + * @retval None + */ +uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag) +{ + uint8_t status; + + if (flag & 0xff) + { + status = FMC->STS & flag; + } + else + { + status = FMC->OBCS & flag; + } + + if (status) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear the specified flash flag + * + * @param flag: Specifies the flash flag to clear + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_BUSY: Busy flag + * @arg FMC_FLAG_PE: Program error flag + * @arg FMC_FLAG_WPE: Write protection error flag + * @arg FMC_FLAG_OC: Operation complete flag + * + * @retval None + */ +void FMC_ClearStatusFlag(uint8_t flag) +{ + if (flag & 0xff) + { + FMC->STS = flag; + } +} + +/**@} end of group FMC_Functions*/ +/**@} end of group FMC_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_gpio.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_gpio.c new file mode 100644 index 0000000000..bea8569b40 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_gpio.c @@ -0,0 +1,378 @@ +/*! + * @file apm32f0xx_gpio.c + * + * @brief This file contains all the functions for the GPIO peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_gpio.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup GPIO_Driver + @{ +*/ + + +/** @defgroup GPIO_Macros Macros + @{ + */ + +/**@} end of group GPIO_Macros */ + +/** @defgroup GPIO_Enumerates Enumerates + @{ + */ + +/**@} end of group GPIO_Enumerates */ + +/** @defgroup GPIO_Structures Structures + @{ + */ + +/**@} end of group GPIO_Structures */ + +/** @defgroup GPIO_Variables Variables + @{ + */ + +/**@} end of group GPIO_Variables */ + +/** @defgroup GPIO_Functions Functions + @{ + */ + +/*! + * @brief Reset GPIO peripheral registers to their default reset values + * + * @param port: GPIO peripheral.It can be GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF + * + * @retval None + * + * @note GPIOE is available only for APM32F072 and APM32F091 + */ +void GPIO_Reset(GPIO_T* port) +{ + if (port == GPIOA) + { + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOA); + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOA); + } + else if (port == GPIOB) + { + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOB); + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOB); + } + else if (port == GPIOC) + { + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOC); + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOC); + } + else if (port == GPIOD) + { + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOD); + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOD); + } + else if (port == GPIOE) + { + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOE); + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOE); + } + else if (port == GPIOF) + { + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_GPIOF); + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_GPIOF); + } +} + +/*! + * @brief Config the GPIO peripheral according to the specified parameters in the gpioConfig + * + * @param port: GPIO peripheral.It can be GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF + * + * @param gpioConfig: Pointer to a GPIO_Config_T structure that + * contains the configuration information for the specified GPIO peripheral + * + * @retval None + * + * @note GPIOE is available only for APM32F072 and APM32F091 + */ +void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig) +{ + uint32_t i; + uint32_t bit; + + for (i = 0; i < 16; i++) + { + bit = (uint32_t)1 << i; + + if (!(gpioConfig->pin & bit)) + { + continue; + } + + if ((gpioConfig->mode == GPIO_MODE_OUT) || (gpioConfig->mode == GPIO_MODE_AF)) + { + /* speed */ + port->OSSEL &= ~((0x03) << (i * 2)); + port->OSSEL |= ((uint32_t)(gpioConfig->speed) << (i * 2)); + + /* Output mode configuration */ + port->OMODE &= ~(((uint16_t)gpioConfig->outtype) << ((uint16_t)i)); + port->OMODE |= (uint16_t)(((uint16_t)gpioConfig->outtype) << ((uint16_t)i)); + } + + /* input/output mode */ + port->MODE &= ~(0x03 << (i * 2)); + port->MODE |= (((uint32_t)gpioConfig->mode) << (i * 2)); + + /* Pull-up Pull down resistor configuration */ + port->PUPD &= ~(0x03 << ((uint16_t)i * 2)); + port->PUPD |= (((uint32_t)gpioConfig->pupd) << (i * 2)); + } +} + +/*! + * @brief Fills each GPIO_Config_T member with its default value + * + * @param gpioConfig: Pointer to a GPIO_Config_T structure which will be initialized + * + * @retval None + */ +void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig) +{ + gpioConfig->pin = GPIO_PIN_ALL; + gpioConfig->mode = GPIO_MODE_IN; + gpioConfig->outtype = GPIO_OUT_TYPE_PP; + gpioConfig->speed = GPIO_SPEED_10MHz; + gpioConfig->pupd = GPIO_PUPD_NO; +} + +/*! + * @brief Locks GPIO Pins configuration registers + * + * @param port: GPIOA/B peripheral + * + * @param pin: specifies the port bit to be written + * + * @retval None + */ +void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin) +{ + uint32_t val = 0x00010000; + + val |= pin; + /* Set LOCK bit */ + port->LOCK = val ; + /* Reset LOCK bit */ + port->LOCK = pin; + /* Set LOCK bit */ + port->LOCK = val; + /* Read LOCK bit*/ + val = port->LOCK; + /* Read LOCK bit*/ + val = port->LOCK; +} + +/*! + * @brief Reads the specified input port pin + * + * @param port: GPIO peripheral.It can be GPIOA/GPIOB/GPIOC/GPIOD/GPIOE/GPIOF + * + * @param pin: specifies pin to read + * + * @retval The input port pin value + * + * @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + */ +uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin) +{ + uint8_t ret; + + ret = (port->IDATA & pin) ? BIT_SET : BIT_RESET; + + return ret; +} + +/*! + * @brief Reads the specified GPIO input data port + * + * @param port: GPIO peripheral + * + * @retval GPIO input data port value + * + * @note GPIOE is available only for APM32F072 and APM32F091 + */ +uint16_t GPIO_ReadInputPort(GPIO_T* port) +{ + return ((uint16_t)port->IDATA); +} + +/*! + * @brief Reads the specified output data port bit + * + * @param port: GPIO peripheral + * + * @param pin: specifies pin to read + * + * @retval The output port pin value + * + * @note GPIOE is available only for APM32F072 and APM32F091 + */ +uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin) +{ + + uint8_t ret; + + ret = (port->ODATA & pin) ? BIT_SET : BIT_RESET; + + return ret; +} + +/*! + * @brief Reads the specified GPIO output data port + * + * @param port: GPIO peripheral + * + * @retval output data port value + * + * @note GPIOE is available only for APM32F072 and APM32F091 + */ +uint16_t GPIO_ReadOutputPort(GPIO_T* port) +{ + return ((uint16_t)port->ODATA); +} + +/*! + * @brief Sets the selected data port bits + * + * @param port: GPIO peripheral + * + * @param pin: specifies the port bits to be written + * + * @retval None + * + * @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + */ +void GPIO_SetBit(GPIO_T* port, uint16_t pin) +{ + port->BSC = (uint32_t)pin; +} + +/*! + * @brief Clears the selected data port bits + * + * @param port: GPIO peripheral + * + * @param pin: specifies the port bits to be written + * + * @retval None + * + * @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + */ +void GPIO_ClearBit(GPIO_T* port, uint16_t pin) +{ + port->BR = (uint32_t)pin; +} + +/*! + * @brief Sets or clears the selected data port bit + * + * @param port: GPIO peripheral + * + * @param pin: specifies the port bits to be written + * + * @param bitVal + * + * @retval None + * + * @note APM32F072 and APM32F091: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. + */ +void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, GPIO_BSRET_T bitVal) +{ + if (bitVal != Bit_RESET) + { + port->BSC = pin; + } + else + { + port->BR = pin ; + } +} + +/*! + * @brief Writes data to the specified GPIO data port + * + * @param port: GPIO peripheral + * + * @param portVal: Write value to the port output data register + * + * @retval None + * + * @note GPIOE is available only for APM32F072 and APM32F091 + */ +void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue) +{ + port->ODATA = (uint32_t)portValue; +} + +/*! + * @brief Changes the mapping of the specified pin + * + * @param port: GPIO peripheral + * + * @param pinSource: Specifies the pin for the Alternate function. + * This parameter can be one of the following values: + * @arg GPIOA,GPIOB,GPIOD,GPIOE for 0..15 + * @arg GPIOC for 0..12 + * @arg GPIOF for 0, 2..5, 9..10 + * + * @param afPin: Selects the pin to used as Alternate function. + * + * @retval None + * + * @note GPIOC, GPIOD, GPIOE and GPIOF are available only for APM32F072 and APM32F091 + */ +void GPIO_ConfigPinAF(GPIO_T* port, GPIO_PIN_SOURCE_T pinSource, GPIO_AF_T afPin) +{ + uint32_t temp = 0x00; + uint32_t temp1 = 0x00; + + if (pinSource <= 0x07) + { + temp = (uint8_t)afPin << ((uint32_t)pinSource * 4); + port->ALFL &= ~((uint32_t)0xf << ((uint32_t)pinSource * 4)); + port->ALFL |= temp; + } + else + { + temp1 = (uint8_t)afPin << ((uint32_t)(pinSource & 0x07) * 4); + port->ALFH &= ~((uint32_t)0xf << (((uint32_t)pinSource & 0x07) * 4)); + port->ALFH |= temp1; + } +} +/**@} end of group GPIO_Functions */ +/**@} end of group GPIO_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_i2c.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_i2c.c new file mode 100644 index 0000000000..3156024c9a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_i2c.c @@ -0,0 +1,1177 @@ +/*! + * @file apm32f0xx_i2c.c + * + * @brief This file contains all the functions for the I2C peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_i2c.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup I2C_Driver + @{ +*/ + +/** @defgroup I2C_Macros Macros + @{ + */ + +/**@} end of group I2C_Macros */ + +/** @defgroup I2C_Enumerates Enumerates + @{ + */ + +/**@} end of group I2C_Enumerates */ + +/** @defgroup I2C_Structures Structures + @{ + */ + +/**@} end of group I2C_Structures */ + +/** @defgroup I2C_Variables Variables + @{ + */ + +/**@} end of group I2C_Variables */ + +/** @defgroup I2C_Functions Functions + @{ + */ + +/*! + * @brief Set the I2C peripheral registers to their default reset values + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Reset(I2C_T* i2c) +{ + if (i2c == I2C1) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + } + else + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + } +} + +/*! + * @brief Config the I2C peripheral according to the specified parameters in the adcConfig + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param adcConfig: Pointer to a I2C_Config_T structure that + * contains the configuration information for the I2C peripheral + * + * @retval None + */ +void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) +{ + uint32_t temp = 0; + + /* Disable I2C */ + i2c->CTRL1_B.I2CEN = BIT_RESET; + + /* FILTERS Configuration */ + temp = i2c->CTRL1; + temp &= ((uint32_t)0x00CFE0FF); + i2c->CTRL1_B.DNFCFG = i2cConfig->digitalfilter; + i2c->CTRL1_B.ANFD = i2cConfig->analogfilter; + + /* TIMING Configuration */ + i2c->TIMING = i2cConfig-> timing & ((uint32_t)0xF0FFFFFF); + + /* Enable I2C */ + i2c->CTRL1_B.I2CEN = BIT_SET; + + /* ADDR1 Configuration */ + temp = 0; + i2c->ADDR1 = 0; + i2c->ADDR2 = 0; + + temp = (uint32_t)((uint32_t)i2cConfig->ackaddress << 10 | \ + (uint32_t)i2cConfig->address1); + + /* Write to I2C ADDR1 */ + i2c->ADDR1 = temp; + + /* Enable Own Address1 acknowledgement */ + i2c->ADDR1_B.ADDR1EN = BIT_SET; + + /* Mode Configuration */ + i2c->CTRL1 &= 0xFFCFFFF; + temp = i2cConfig->mode; + i2c->CTRL1 |= temp; + + /* Ack Configuration */ + i2c->CTRL2_B.NACKEN = i2cConfig->ack; +} + +/*! + * @brief Fills each i2cConfig member with its default value + * + * @param i2cConfig: Pointer to a I2C_Config_T structure which will be initialized + * + * @retval None + */ +void I2C_ConfigStructInit(I2C_Config_T* i2cConfig) +{ + i2cConfig->timing = 0; + i2cConfig->address1 = 0; + i2cConfig->mode = I2C_MODE_I2C; + i2cConfig->analogfilter = I2C_ANALOG_FILTER_ENABLE; + i2cConfig->digitalfilter = I2C_DIGITAL_FILTER_0; + + i2cConfig->ack = I2C_ACK_DISABLE; + i2cConfig->ackaddress = I2C_ACK_ADDRESS_7BIT; +} + +/*! + * @brief Enable the I2C peripheral + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Enable(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = BIT_SET; +} + +/*! + * @brief Disable the I2C peripheral + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Disable(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = BIT_RESET; +} + +/*! + * @brief I2C Soft ware Reset + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_SoftwareReset(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = BIT_RESET; + *(__IO uint32_t*)(uint32_t)i2c; + i2c->CTRL1_B.I2CEN = BIT_SET; +} + +/*! + * @brief Enables the specified interrupts + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param interrupt: Specifies the I2C interrupts sources + * The parameter can be combination of following values: + * @arg I2C_INT_TXIE: TX Interrupt enable + * @arg I2C_INT_RXIE: RX Interrupt enable + * @arg I2C_INT_ADDRIE: Address match interrupt enable (slave only) + * @arg I2C_INT_NACKIE: Not acknowledge received interrupt enable + * @arg I2C_INT_STOPIE: STOP detection Interrupt enable + * @arg I2C_INT_TXCIE: Transfer complete interrupt enable + * @arg I2C_INT_ERRIE: Error interrupts enable + * + * @retval None + */ +void I2C_EnableInterrupt(I2C_T* i2c, uint8_t interrupt) +{ + i2c->CTRL1 |= (uint32_t)interrupt; +} + +/*! + * @brief Disable the specified interrupts + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param interrupt: Specifies the I2C interrupts sources + * The parameter can be combination of following values: + * @arg I2C_INT_TXIE: TX Interrupt enable + * @arg I2C_INT_RXIE: RX Interrupt enable + * @arg I2C_INT_ADDRIE: Address match interrupt enable (slave only) + * @arg I2C_INT_NACKIE: Not acknowledge received interrupt enable + * @arg I2C_INT_STOPIE: STOP detection Interrupt enable + * @arg I2C_INT_TXCIE: Transfer complete interrupt enable + * @arg I2C_INT_ERRIE: Error interrupts enable + * + * @retval None + */ +void I2C_DisableInterrupt(I2C_T* i2c, uint8_t interrupt) +{ + i2c->CTRL1 &= (uint32_t)~interrupt; +} + +/*! + * @brief Enables the stretch clock + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableStretchClock(I2C_T* i2c) +{ + i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET; +} + +/*! + * @brief Disables the stretch clock + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableStretchClock(I2C_T* i2c) +{ + i2c->CTRL1_B.CLKSTRETCHD = BIT_SET; +} + +/*! + * @brief Enables the stop mode + * + * @param i2c: Select I2C peripheral, It can be I2C1. + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void I2C_EnableStopMode(I2C_T* i2c) +{ + i2c->CTRL1_B.WUPEN = BIT_SET; +} + +/*! + * @brief Disable the stop mode + * + * @param i2c: Select I2C peripheral, It can be I2C1. + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void I2C_DisableStopMode(I2C_T* i2c) +{ + i2c->CTRL1_B.WUPEN = BIT_RESET; +} + +/*! + * @brief Enables the I2C own address 2 + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableOwnAddress2(I2C_T* i2c) +{ + i2c->ADDR2_B.ADDR2EN = BIT_SET; +} + +/*! + * @brief Disables the I2C own address 2 + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableOwnAddress2(I2C_T* i2c) +{ + i2c->ADDR2_B.ADDR2EN = BIT_RESET; +} + +/*! + * @brief I2C slave own address 2 and mask + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param mask: Own address 2 mask selection + * The parameter can be one of following values: + * @arg I2C_ADDR2MSK_NOMASK: No masked + * @arg I2C_ADDR2MSK_MASK01: Don't care masked ADDR2[1:0] + * @arg I2C_ADDR2MSK_MASK02: Don't care masked ADDR2[2:1] + * @arg I2C_ADDR2MSK_MASK03: Don't care masked ADDR2[3:1] + * @arg I2C_ADDR2MSK_MASK04: Don't care masked ADDR2[4:1] + * @arg I2C_ADDR2MSK_MASK05: Don't care masked ADDR2[5:1] + * @arg I2C_ADDR2MSK_MASK06: Don't care masked ADDR2[6:1] + * @arg I2C_ADDR2MSK_MASK07: Don't care masked ADDR2[7:1] + * + * @retval None + */ +void I2C_OwnAddress2Mask(I2C_T* i2c, uint16_t address, I2C_ADDR2MSK_T mask) +{ + i2c->ADDR2_B.ADDR2 = address; + i2c->ADDR2_B.ADDR2MSK = mask; + +} + +/*! + * @brief Enables the Broadcast call mode + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableBroadcastCall(I2C_T* i2c) +{ + i2c->CTRL1_B.RBEN = BIT_SET; +} + +/*! + * @brief Disables the Broadcast call mode + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableBroadcastCall(I2C_T* i2c) +{ + i2c->CTRL1_B.RBEN = BIT_RESET; +} + +/*! + * @brief Enables the slave byte control + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableSlaveByteControl(I2C_T* i2c) +{ + i2c->CTRL1_B.SBCEN = BIT_SET; +} + +/*! + * @brief Disables the slave byte control + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableSlaveByteControl(I2C_T* i2c) +{ + i2c->CTRL1_B.SBCEN = BIT_RESET; +} + +/*! + * @brief Configures the slave address + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param address: set I2C slave uint16_t Address + * + * @retval None + */ +void I2C_SlaveAddress(I2C_T* i2c, uint16_t address) +{ + uint32_t temp = 0; + temp = i2c->CTRL2; + + temp &= (uint32_t)~((uint32_t)0x000003FF); + i2c->CTRL2 = temp; + + i2c->ADDR2_B.ADDR2 = address; +} + +/*! + * @brief Enables I2C 10-bit addressing mode for the master + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Enable10BitAddressingMode(I2C_T* i2c) +{ + i2c->CTRL2_B.SADDRLEN = BIT_SET; +} + +/*! + * @brief Disables I2C 10-bit addressing mode for the master + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Disable10BitAddressingMode(I2C_T* i2c) +{ + i2c->CTRL2_B.SADDRLEN = BIT_RESET; +} + +/*! + * @brief Enables the I2C automatic end mode + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableAutoEnd(I2C_T* i2c) +{ + i2c->CTRL2_B.ENDCFG = BIT_SET; +} + +/*! + * @brief Disables the I2C automatic end mode + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableAutoEnd(I2C_T* i2c) +{ + i2c->CTRL2_B.ENDCFG = BIT_RESET; +} + +/*! + * @brief Enables the I2C nbytes reload mode + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableReload(I2C_T* i2c) +{ + i2c->CTRL2_B.RELOADEN = BIT_SET; +} + +/*! + * @brief Disables the I2C nbytes reload mode + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableReload(I2C_T* i2c) +{ + i2c->CTRL2_B.RELOADEN = BIT_RESET; +} + +/*! + * @brief Configures the number of bytes to be transmitted/received + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param number:Set uint8_t bytes to read or write + * + * @retval None + */ +void I2C_ConfigNumberOfBytes(I2C_T* i2c, uint8_t number) +{ + i2c->CTRL2_B.NUMBYT = 0xFF; + i2c->CTRL2_B.NUMBYT &= (uint8_t) number ; +} + +/*! + * @brief Configures the type of transfer request for the master + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param direction: selects the I2C transfer direction. + * The parameter can be one of following values: + * @arg I2C_DIRECTION_TX: Transmission direction + * @arg I2C_DIRECTION_RX: Reception direction + * + * @retval None + */ +void I2C_ConfigMasterRequest(I2C_T* i2c, I2C_DIRECTION_T direction) +{ + i2c->CTRL2_B.TXDIR = direction ; +} + +/*! + * @brief Enables the generates i2c communication start condition + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableGenerateStart(I2C_T* i2c) +{ + i2c->CTRL2_B.START = BIT_SET; +} + +/*! + * @brief Disables the generates i2c communication start condition + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableGenerateStart(I2C_T* i2c) +{ + i2c->CTRL2_B.START = BIT_RESET; +} + +/*! + * @brief Enables the generates i2c communication stop condition + * + * @param i2c: Select I2C peripheral + * This parameter can be any combination of the following values: + * @arg I2C1 + * @arg I2C2 + * + * @retval None + */ +void I2C_EnableGenerateStop(I2C_T* i2c) +{ + i2c->CTRL2_B.STOP = BIT_SET; +} + +/*! + * @brief Disables the generates i2c communication stop condition + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableGenerateStop(I2C_T* i2c) +{ + i2c->CTRL2_B.STOP = BIT_RESET; +} + +/*! + * @brief Enables I2C 10-bit header only mode with read direction + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Enable10BitAddressHeader(I2C_T* i2c) +{ + i2c->CTRL2_B.ADDR10 = BIT_SET; +} + +/*! + * @brief Disables I2C 10-bit header only mode with read direction + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_Disable10BitAddressHeader(I2C_T* i2c) +{ + i2c->CTRL2_B.ADDR10 = BIT_RESET; +} + +/*! + * @brief Enables I2C communication Acknowledge + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableAcknowledge(I2C_T* i2c) +{ + i2c->CTRL2_B.NACKEN = BIT_RESET; +} + +/*! + * @brief Disables I2C communication Acknowledge + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableAcknowledge(I2C_T* i2c) +{ + i2c->CTRL2_B.NACKEN = BIT_SET; +} + +/*! + * @brief Returns the I2C slave matched address + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval The value is slave matched address + */ +uint8_t I2C_ReadAddressMatched(I2C_T* i2c) +{ + return ((uint8_t)i2c->STS_B.ADDRCMFLG); +} + +/*! + * @brief Returns the I2C slave received request + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval The value of the received request + */ +uint16_t I2C_ReadTransferDirection(I2C_T* i2c) +{ + uint16_t direction = 0; + uint32_t temp = 0; + + temp = (uint32_t) i2c->STS_B.TXDIRFLG; + + if (temp == 0) + { + direction = (uint16_t)I2C_DIRECTION_TX; + } + else + { + direction = (uint16_t)(I2C_DIRECTION_RX << 10); + } + + return direction; +} + +/*! + * @brief Handles I2Cx communication when starting transfer or during transfer + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param address: specifies the slave address to be programmed. + * + * @param number: specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * + * @param reloadend: the I2C reload end mode + * The parameter can be one of following values: + * @arg I2C_RELOAD_MODE_RELOAD: Enable Reload mode. + * @arg I2C_RELOAD_MODE_AUTOEND: Enable Automatic end mode. + * @arg I2C_RELOAD_MODE_SOFTEND: Enable Software end mode. + * + * @param generates: the I2C start/stop mode + * The parameter can be one of following values: + * @arg I2C_GENERATE_NO_STARTSTOP: Don't Generate stop and start condition. + * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request. + * @arg I2C_GENERATE_STOP: Generate stop condition + * @arg I2C_GENERATE_START_READ: Generate Restart for read request. + * + * @retval None + */ +void I2C_HandlingTransfer(I2C_T* i2c, uint16_t address, uint8_t number, I2C_RELOAD_MODE_T reloadend, I2C_GENERATE_T generates) +{ + uint32_t temp = 0; + + /* Get the CTRL2 register value */ + temp = i2c->CTRL2; + + /* clear temp specific bits */ + temp &= (uint32_t)~((uint32_t)(I2C_CTRL2_SADD | I2C_CTRL2_NUMBYT | I2C_CTRL2_MASK)); + + /* update temp */ + temp |= (uint32_t)(((uint32_t)address & I2C_CTRL2_SADD) | (((uint32_t)number << 16) & I2C_CTRL2_NUMBYT) | \ + (uint32_t)reloadend | (uint32_t)generates); + + /* update CTRL2 register */ + i2c->CTRL2 = temp; +} + +/*! + * @brief Enables I2C SMBus alert + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_EnableSMBusAlert(I2C_T* i2c) +{ + i2c->CTRL1_B.ALTEN = BIT_SET; +} + +/*! + * @brief Disables I2C SMBus alert + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_DisableSMBusAlert(I2C_T* i2c) +{ + i2c->CTRL1_B.ALTEN = BIT_RESET; +} + +/*! + * @brief Enable I2C SMBus HADDREN + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_EnableSMBusHAEN(I2C_T* i2c) +{ + i2c->CTRL1_B.HADDREN = BIT_SET; +} + +/*! + * @brief Disable I2C SMBus HADDREN + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableSMBusHAEN(I2C_T* i2c) +{ + i2c->CTRL1_B.HADDREN = BIT_RESET; +} + +/*! + * @brief Enable I2C SMBus DEADDREN + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ + +void I2C_EnableSMBusDAEN(I2C_T* i2c) +{ + i2c->CTRL1_B.DEADDREN = BIT_SET; +} + +/*! + * @brief Disable I2C SMBus DEADDREN + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval None + */ +void I2C_DisableSMBusDAEN(I2C_T* i2c) +{ + i2c->CTRL1_B.DEADDREN = BIT_RESET; +} + +/*! + * @brief Enables I2C Clock Timeout + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_EnableClockTimeout(I2C_T* i2c) +{ + i2c->TIMEOUT_B.CLKTOEN = BIT_SET; +} + +/*! + * @brief Disables I2C Clock Timeout + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_DisableClockTimeout(I2C_T* i2c) +{ + i2c->TIMEOUT_B.CLKTOEN = BIT_RESET; +} + +/*! + * @brief Enables I2C Extend Clock Timeout + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_EnableExtendClockTimeout(I2C_T* i2c) +{ + i2c->TIMEOUT_B.EXCLKTOEN = BIT_SET; +} + +/*! + * @brief Disables I2C Extend Clock Timeout + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_DisableExtendClockTimeout(I2C_T* i2c) +{ + i2c->TIMEOUT_B.EXCLKTOEN = BIT_RESET; +} + +/*! + * @brief Enables I2C Idle Clock Timeout + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_EnableIdleClockTimeout(I2C_T* i2c) +{ + i2c->TIMEOUT_B.IDLECLKTO = BIT_SET; +} + +/*! + * @brief Disables I2C Idle Clock Timeout + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_DisableIdleClockTimeout(I2C_T* i2c) +{ + i2c->TIMEOUT_B.IDLECLKTO = BIT_RESET; +} + +/*! + * @brief Configures the I2C Bus Timeout A + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @param timeout: specifies the Timeout A to be programmed + * + * @retval None + */ +void I2C_ConfigTimeoutA(I2C_T* i2c, uint16_t timeout) +{ + i2c->TIMEOUT_B.TIMEOUTA = timeout; +} + +/*! + * @brief Configures the I2C Bus Timeout B + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @param timeout: specifies the Timeout B to be programmed + * + * @retval None + */ +void I2C_ConfigTimeoutB(I2C_T* i2c, uint16_t timeout) +{ + i2c->TIMEOUT_B.TIMEOUTB = timeout; +} + +/*! + * @brief Enables I2C PEC calculation + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_EnablePEC(I2C_T* i2c) +{ + i2c->CTRL1_B.PECEN = BIT_SET; +} + +/*! + * @brief Disables I2C PEC calculation + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_DisablePEC(I2C_T* i2c) +{ + i2c->CTRL1_B.PECEN = BIT_RESET; +} + +/*! + * @brief Enables I2C PEC transmission/reception request + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_EnablePECRequest(I2C_T* i2c) +{ + i2c->CTRL2_B.PEC = BIT_SET; +} + +/*! + * @brief Disables I2C PEC transmission/reception request + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval None + */ +void I2C_DisablePECRequest(I2C_T* i2c) +{ + i2c->CTRL2_B.PEC = BIT_RESET; +} + +/*! + * @brief Returns the I2C PEC + * + * @param i2c: Select I2C peripheral,it can be I2C1. + * + * @retval The value is PEC + */ +uint8_t I2C_ReadPEC(I2C_T* i2c) +{ + return ((uint8_t)i2c->PEC_B.PEC); +} + +/*! + * @brief Reads the specified I2C register and returns its value + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param registers: Specifies the I2C interrupts sources + * The parameter can be one of following values: + * @arg I2C_REGISTER_CTRL1: CTRL1 register + * @arg I2C_REGISTER_CTRL2: CTRL2 register + * @arg I2C_REGISTER_ADDR1: ADDR1 register + * @arg I2C_REGISTER_ADDR2: ADDR2 register + * @arg I2C_REGISTER_TIMING: TIMING register + * @arg I2C_REGISTER_TIMEOUT: TIMEOUT register + * @arg I2C_REGISTER_STS: STS register + * @arg I2C_REGISTER_INTFCLR: INTFCLR register + * @arg I2C_REGISTER_PEC: PEC register + * @arg I2C_REGISTER_RXDATA: RXDATA register + * @arg I2C_REGISTER_TXDATA: TXDATA register + * + * @retval None + */ +uint32_t I2C_ReadRegister(I2C_T* i2c, uint8_t registers) +{ + __IO uint32_t temp = 0; + + temp = (uint32_t)i2c; + temp += registers; + + return (*(__IO uint32_t*) temp); +} + +/*! + * @brief Send a byte by writing in the TXDATA register + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param data: Byte to be sent + * + * @retval None + */ +void I2C_TxData(I2C_T* i2c, uint8_t data) +{ + i2c->TXDATA = (uint32_t)data; +} + +/*! + * @brief Returns the most recent received data + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @retval The value of the received byte data + */ +uint8_t I2C_RxData(I2C_T* i2c) +{ + return (uint8_t)i2c->RXDATA; +} + +/*! + * @brief Enables the I2C DMA interface + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param request: DMA transfer request + * The parameter can be one of following values: + * @arg I2C_DMA_REQ_TX: TX DMA Transmission request + * @arg I2C_DMA_REQ_RX: RX DMA Transmission request + * + * @retval None + */ +void I2C_EnableDMA(I2C_T* i2c, I2C_DMA_REQ_T request) +{ + if (request == I2C_DMA_REQ_TX) + { + i2c->CTRL1_B.DMATXEN = BIT_SET; + } + else + { + i2c->CTRL1_B.DMARXEN = BIT_SET; + } +} + +/*! + * @brief Disables the I2C DMA interface + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param request: DMA transfer request + * The parameter can be one of following values: + * @arg I2C_DMA_REQ_TX: TX DMA Transmission request + * @arg I2C_DMA_REQ_RX: RX DMA Transmission request + * + * @retval None + */ +void I2C_DisableDMA(I2C_T* i2c, I2C_DMA_REQ_T request) +{ + if (request == I2C_DMA_REQ_TX) + { + i2c->CTRL1_B.DMATXEN = BIT_RESET; + } + else + { + i2c->CTRL1_B.DMARXEN = BIT_RESET; + } +} + +/*! + * @brief Checks whether the specified I2C flag is set or not + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param flag: Specifies the flag to check + * The parameter can be one of following values: + * @arg I2C_FLAG_TXBE: Transmit buffer data register empty flag + * @arg I2C_FLAG_TXINT: Transmit interrupt flag + * @arg I2C_FLAG_RXBNE: Read buffer data register not empty flag + * @arg I2C_FLAG_ADDR: Address Sent/Matched (master/slave) flag + * @arg I2C_FLAG_NACK: Not acknowledge received flag + * @arg I2C_FLAG_STOP: Stop detected flag + * @arg I2C_FLAG_TXCF: Transfer complete flag + * @arg I2C_FLAG_TCRF: Transfer complete reload flag + * @arg I2C_FLAG_BUSERR:Bus error flag + * @arg I2C_FLAG_ALF: Arbitration Loss flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_PECERR:PEC error flag + * @arg I2C_FLAG_TIMEOUT: Timeout or t_low detection flag + * @arg I2C_FLAG_ALERT: SMBus alert flag + * @arg I2C_FLAG_BUSY: Bus Busy Flag + * + * @retval Status of interrupt flag(SET or RESET) + */ +uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +{ + uint32_t status = 0; + + status = (uint32_t)(i2c->STS & (flag)); + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear flags + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param flag: Specifies the flag to clear + * The parameter can be combination of following values: + * @arg I2C_FLAG_ADDR: Address Sent/Matched (master/slave) flag + * @arg I2C_FLAG_NACK: Not acknowledge received flag + * @arg I2C_FLAG_STOP: Stop detected flag + * @arg I2C_FLAG_BUSERR:Bus error flag + * @arg I2C_FLAG_ALF: Arbitration Loss flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_PECERR:PEC error flag + * @arg I2C_FLAG_TIMEOUT: Timeout or t_low detection flag + * @arg I2C_FLAG_ALERT: SMBus alert flag + * + * @retval None + */ +void I2C_ClearStatusFlag(I2C_T* i2c, uint32_t flag) +{ + i2c->INTFCLR = (uint32_t)flag; +} + +/*! + * @brief Checks whether the specified interrupt has occurred or not + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param flag: Specifies the I2C interrupt pending bit to check + * The parameter can be one of following values: + * @arg I2C_INT_FLAG_TXINT: Transmit interrupt flag + * @arg I2C_INT_FLAG_RXBNE: Read Buffer Data Register Not Empty interrupt flag + * @arg I2C_INT_FLAG_ADDR: Address Sent/Matched (master/slave) interrupt flag + * @arg I2C_INT_FLAG_NACK: Not acknowledge received interrupt flag + * @arg I2C_INT_FLAG_STOP: Stop detected interrupt flag + * @arg I2C_INT_FLAG_TXCF: Transfer complete interrupt flag + * @arg I2C_INT_FLAG_TCRF: Transfer Complete Reloadinterrupt flag + + * @arg I2C_INT_FLAG_BUSERR: Bus error interrupt flag + * @arg I2C_INT_FLAG_ALF: Arbitration Loss interrupt flag + * @arg I2C_INT_FLAG_OVR: Overrun/Underrun interrupt flag + * @arg I2C_INT_FLAG_PECERR: PEC error interrupt flag + * @arg I2C_INT_FLAG_TIMEOUT: Timeout or t_low detection interrupt flag + * @arg I2C_INT_FLAG_ALERT: SMBus alert interrupt flag + * + * @retval Status of interrupt flag(SET or RESET) + */ +uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +{ + uint32_t temp = 0; + uint32_t enable = 0; + + if (flag & ((uint32_t)0x000000C0)) + { + enable = (uint32_t)((BIT6) & (i2c->CTRL1)); + } + else if (flag & ((uint32_t)0x00003F00)) + { + enable = (uint32_t)((BIT7) & (i2c->CTRL1)); + } + else + { + enable = (uint32_t)((flag) & (i2c->CTRL1)); + } + + temp = i2c->STS; + + temp &= flag; + + if ((temp != 0) && enable) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the specified interrupt pending bits + * + * @param i2c: Select I2C peripheral,it can be I2C1/I2C2. + * + * @param flag: Specifies the I2C interrupt pending bit to clear + * The parameter can be combination of following values: + * @arg I2C_INT_FLAG_ADDR: Address Sent/Matched (master/slave) flag + * @arg I2C_INT_FLAG_NACK: Not acknowledge received flag + * @arg I2C_INT_FLAG_STOP: Stop detected flag + * @arg I2C_INT_FLAG_BUSERR:Bus error flag + * @arg I2C_INT_FLAG_ALF: Arbitration Loss flag + * @arg I2C_INT_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_INT_FLAG_PECERR:PEC error flag + * @arg I2C_INT_FLAG_TIMEOUT: Timeout or t_low detection flag + * @arg I2C_INT_FLAG_ALERT: SMBus alert flag + * + * @retval + */ + +void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag) +{ + i2c->INTFCLR = (uint32_t)flag; +} + +/**@} end of group I2C_Functions */ +/**@} end of group I2C_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_iwdt.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_iwdt.c new file mode 100644 index 0000000000..e5dc5a2821 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_iwdt.c @@ -0,0 +1,184 @@ +/*! + * @file apm32f0xx_iwdt.c + * + * @brief This file contains all the functions for the IWDT peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_iwdt.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup IWDT_Driver + @{ +*/ + +/** @defgroup IWDT_Macros Macros + @{ +*/ + +/**@} end of group IWDT_Macros*/ + +/** @defgroup IWDT_Enumerations Enumerations + @{ +*/ + +/**@} end of group IWDT_Enumerations*/ + +/** @defgroup IWDT_Structures Structures + @{ +*/ + +/**@} end of group IWDT_Structures*/ + +/** @defgroup IWDT_Variables Variables + @{ +*/ + +/**@} end of group IWDT_Variables*/ + +/** @defgroup IWDT_Functions Functions + @{ +*/ + +/*! + * @brief Enable IWDT + * + * @param None + * + * @retval None + */ +void IWDT_Enable(void) +{ + IWDT->KEY = IWDT_KEY_ENABLE; +} + +/*! + * @brief Enable write access to Divider and Counter Reload registers + * + * @param None + * + * @retval None + */ +void IWDT_EnableWriteAccess(void) +{ + IWDT->KEY = IWDT_KEY_ACCESS; +} + +/*! + * @brief Disable write access to Divider and Counter Reload registers + * + * @param None + * + * @retval None + */ +void IWDT_DisableWriteAccess(void) +{ + IWDT->KEY = 0; +} + +/*! + * @brief Refresh IWDT + * + * @param None + * + * @retval None + */ +void IWDT_Refresh(void) +{ + IWDT->KEY = IWDT_KEY_REFRESH; +} + +/*! + * @brief Divider configuration + * + * @param div: Specifies the divider + * The parameter can be one of following values: + * @arg IWDT_DIV_4: Prescaler divider 4 + * @arg IWDT_DIV_8: Prescaler divider 8 + * @arg IWDT_DIV_16: Prescaler divider 16 + * @arg IWDT_DIV_32: Prescaler divider 32 + * @arg IWDT_DIV_64: Prescaler divider 64 + * @arg IWDT_DIV_128: Prescaler divider 128 + * @arg IWDT_DIV_256: Prescaler divider 256 + * + * @retval None + */ +void IWDT_ConfigDivider(IWDT_DIV_T div) +{ + IWDT->PSC = (uint32_t)div; +} + +/*! + * @brief Set counter reload value + * + * @param reload: Specifies the reload value + * + * @retval None + */ +void IWDT_ConfigReload(uint16_t reload) +{ + IWDT->CNTRLD = (uint32_t)reload; +} + +/*! + * @brief Set counter reload value + * + * @param reload: Specifies the reload value + * + * @retval None + */ +void IWDT_ConfigWindowValue(uint16_t windowValue) +{ + IWDT->WIN = (uint32_t)windowValue; +} +/*! + * @brief Read the specified IWDT flag + * + * @param flag: Specifies the flag to read + * The parameter can be one of following values: + * @arg IWDT_FLAG_DIVU: Watchdog prescaler value update + * @arg IWDT_FLAG_CNTU: Watchdog counter reload value update + * @arg IWDT_FLAG_WINU: Watchdog counter window value update + * + * @retval status of IWDT_FLAG (SET or RESET) + */ +uint8_t IWDT_ReadStatusFlag(uint8_t flag) +{ + uint8_t bitStatus = RESET; + + if ((IWDT->STS & flag) != (uint32_t)RESET) + { + bitStatus = SET; + } + else + { + bitStatus = RESET; + } + + return bitStatus; +} + +/**@} end of group IWDT_Functions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_misc.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_misc.c new file mode 100644 index 0000000000..a79c13b679 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_misc.c @@ -0,0 +1,190 @@ +/*! + * @file apm32f0xx_misc.c + * + * @brief This file provides all the miscellaneous firmware functions (add-on to CMSIS functions). + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx_misc.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup MISC_Driver + @{ +*/ + +/** @defgroup MISC_Macros Macros + @{ +*/ + +/**@} end of group MISC_Macros*/ + +/** @defgroup MISC_Enumerations Enumerations + @{ +*/ + +/**@} end of group MISC_Enumerations*/ + +/** @defgroup MISC_Structures Structures + @{ +*/ + +/**@} end of group MISC_Structures*/ + +/** @defgroup MISC_Variables Variables + @{ +*/ + +/**@} end of group MISC_Variables*/ + +/** @defgroup MISC_Functions Functions + @{ +*/ + +/*! + * @brief Enable NVIC request + * + * @param irq: The NVIC interrupt request, detailed in IRQn_Type + * + * @param priority: Specifies the priority needed to set + * + * @retval None + */ +void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t priority) +{ + NVIC_SetPriority(irq, priority); + + NVIC_EnableIRQ(irq); +} + +/*! + * @brief Disable NVIC request + * + * @param irq: The NVIC interrupt request, detailed in IRQn_Type + * + * @retval None + */ +void NVIC_DisableIRQRequest(IRQn_Type irq) +{ + NVIC_DisableIRQ(irq); +} + +/** + * @brief Enables the system to enter low power mode. + * + * @param lowPowerMode: Specifies the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LOWPOER_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LOWPOER_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LOWPOER_SLEEPONEXIT: Low Power Sleep on Exit. + * + * @retval None + */ +void NVIC_EnableSystemLowPower(uint8_t lowPowerMode) +{ + SCB->SCR |= lowPowerMode; +} + +/** + * @brief Disables the system to enter low power mode. + * + * @param lowPowerMode: Specifies the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LOWPOER_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LOWPOER_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LOWPOER_SLEEPONEXIT: Low Power Sleep on Exit. + * + * @retval None + */ +void NVIC_DisableSystemLowPower(uint8_t lowPowerMode) +{ + SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode); +} + +/** + * @brief Configures the SysTick clock source. + * + * @param sysTickCLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * + * @retval None + */ +void SysTick_ConfigCLKSource(uint32_t sysTickCLKSource) +{ + if (sysTickCLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/*! + * @brief Enter Wait Mode + * + * @param None + * + * @retval None + */ +void PMU_EnterWaitMode(void) +{ + SCB->SCR &= (uint32_t)(~(uint32_t)NVIC_LOWPOER_SLEEPDEEP); + __WFI(); +} + +/*! + * @brief Enter Stop Mode with WFI instruction + * + * @param None + * + * @retval None + */ +void PMU_EnterHaltModeWFI(void) +{ + SCB->SCR |= NVIC_LOWPOER_SLEEPDEEP; + __DSB(); + __WFI(); +} + +/*! + * @brief Enter Stop Mode with WFE instruction + * + * @param None + * + * @retval None + */ +void PMU_EnterHaltModeWFE(void) +{ + SCB->SCR |= NVIC_LOWPOER_SLEEPDEEP; + __DSB(); + __WFE(); +} + +/**@} end of group MISC_Functions */ +/**@} end of group MISC_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_ob.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_ob.c new file mode 100644 index 0000000000..fc7ace7881 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_ob.c @@ -0,0 +1,152 @@ +/*! + * @file apm32f0xx_ob.c + * + * @brief This file contains all the functions for the OB peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_ob.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup OB_Driver + @{ +*/ + +/** @defgroup OB_Macros Macros + @{ +*/ + +/**@} end of group OB_Macros*/ + +/** @defgroup OB_Enumerations Enumerations + @{ +*/ + +/**@} end of group OB_Enumerations*/ + +/** @defgroup OB_Structures Structures + @{ +*/ + +/**@} end of group OB_Structures*/ + +/** @defgroup OB_Variables Variables + @{ +*/ + +/**@} end of group OB_Variables*/ + +/** @defgroup OB_Functions Functions + @{ +*/ + +/*! + * @brief Read Flash Protection Level + * + * @param readProtection: Specifies the read protection level. + * The parameter can be one of following values: + * @arg OB_READ_PRO_LEVEL0: No protection + * @arg OB_READ_PRO_LEVEL1: Read protection of the memory + * @retval None + */ +void OB_ReadProtectionOptionByte(OB_READ_PRO_T readProtection) +{ + OB->READPORT_B.READPROT = readProtection; +} + +/*! + * @brief Option Bytes Watchdog + * + * @param wdt: Select Watchdog SW/HW + * + * @retval None + */ +void OB_OptionBytesWatchdog(OB_WDT_T wdt) +{ + OB->USER_B.WDTSEL = wdt; +} + +/*! + * @brief Option Bytes nRST STOP + * + * @param stop: Select nRST STOP RST/SET + * + * @retval None + */ +void OB_OptionBytesStop(OB_STOP_T stop) +{ + OB->USER_B.RSTSTOP = stop; +} + +/*! + * @brief Option Bytes nRST STDBY + * + * @param standby: Select nRST STDBY RST/SET + * + * @retval None + */ +void OB_OptionBytesStandby(OB_STANDBY_T standby) +{ + OB->USER_B.RSTSTDBY = standby; +} + +/*! + * @brief Option Bytes nBOOT1 + * + * @param boot: Select nRST BOOT1 RST/SET + * + * @retval None + */ +void OB_OptionBytesBoot1(OB_BOOT1_T boot) +{ + OB->USER_B.BOT1 = boot; +} + +/*! + * @brief Option Bytes VDDA_Analog_Monitoring + * + * @param vdda: Select VDDA ANALOG OFF/ON + * + * @retval None + */ +void OB_OptionBytesVddaAnalog(OB_VDDA_T vdda) +{ + OB->USER_B.VDDAMON = vdda; +} + +/*! + * @brief Option Bytes RAM PARITY CHECK + * + * @param rpc: Select RAM PARITY OFF/ON + * + * @retval None + */ +void OB_OptionBytesRamParity(OB_RAM_PARITY_CHECK_T ramParityCheck) +{ + OB->USER_B.RPC = ramParityCheck; +} + +/**@} end of group OB_Functions */ +/**@} end of group OB_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_pmu.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_pmu.c new file mode 100644 index 0000000000..7cbfa4ad5c --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_pmu.c @@ -0,0 +1,335 @@ +/*! + * @file apm32f0xx_pmu.c + * + * @brief This file contains all the functions for the PMU peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_pmu.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup PMU_Driver PMU Driver + @{ +*/ + +/** @defgroup PMU_Macros Macros + @{ +*/ + +/**@} end of group PMU_Macros*/ + +/** @defgroup PMU_Enumerations Enumerations + @{ +*/ + +/**@} end of group PMU_Enumerations*/ + +/** @defgroup PMU_Structures Structures + @{ +*/ + +/**@} end of group PMU_Structures*/ + +/** @defgroup PMU_Variables Variables + @{ +*/ + +/**@} end of group PMU_Variables*/ + +/** @defgroup PMU_Functions Functions + @{ +*/ + +/*! + * @brief Resets the PWR peripheral registers to their default reset values + * + * @param None + * + * @retval None + */ +void PMU_Reset(void) +{ + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); + RCM_DisableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); +} + +/*! + * @brief Enables access to the Backup domain registers + * + * @param None + * + * @retval None + */ +void PMU_EnableBackupAccess(void) +{ + PMU->CTRL_B.BPWEN = BIT_SET; +} + +/*! + * @brief Disables access to the Backup domain registers + * + * @param None + * + * @retval None + */ +void PMU_DisableBackupAccess(void) +{ + PMU->CTRL_B.BPWEN = BIT_RESET; +} + +/*! + * @brief Configures the PMU PVD Level + * + * @param level: specifies the PVD Level + * This parameter can be one of the following values + * @arg PMU_PVDLEVEL_0 + * @arg PMU_PVDLEVEL_1 + * @arg PMU_PVDLEVEL_2 + * @arg PMU_PVDLEVEL_3 + * @arg PMU_PVDLEVEL_4 + * @arg PMU_PVDLEVEL_5 + * @arg PMU_PVDLEVEL_6 + * @arg PMU_PVDLEVEL_7 + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void PMU_ConfigPVDLevel(PMU_PVDLEVEL_T level) +{ + PMU->CTRL_B.PLSEL = level; +} + +/*! + * @brief Enables Power voltage detector + * + * @param None + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void PMU_EnablePVD(void) +{ + PMU->CTRL_B.PVDEN = BIT_SET; +} +/*! + * @brief Disables Power voltage detector + * + * @param None + * + * @retval None + * + * @note It's not for APM32F030 devices + */ +void PMU_DisablePVD(void) +{ + PMU->CTRL_B.PVDEN = BIT_RESET; +} + +/*! + * @brief Enables the WakeUp Pin functionality + * + * @param pin: specifies the WakeUpPin + * This parameter can be one of the following values + * @arg PMU_WAKEUPPIN_1 + * @arg PMU_WAKEUPPIN_2 + * @arg PMU_WAKEUPPIN_3 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_4 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_5 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_6 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_7 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_8 It's Only for APM32F072/091 devices + * + * @retval None + */ +void PMU_EnableWakeUpPin(PMU_WAKEUPPIN_T pin) +{ + PMU->CSTS |= pin; +} + +/*! + * @brief DIsable the WakeUp Pin functionality + * + * @param pin: specifies the WakeUpPin + * This parameter can be one of the following values + * @arg PMU_WAKEUPPIN_1 + * @arg PMU_WAKEUPPIN_2 + * @arg PMU_WAKEUPPIN_3 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_4 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_5 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_6 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_7 It's Only for APM32F072/091 devices + * @arg PMU_WAKEUPPIN_8 It's Only for APM32F072/091 devices + * + * @retval None + */ +void PMU_DisableWakeUpPin(PMU_WAKEUPPIN_T pin) +{ + PMU->CSTS &= ~pin; +} + +/*! + * @brief Enters Sleep mode + * + * @param entry :specifies if SLEEP mode in entered with WFI or WFE instruction + * This parameter can be one of the following values: + * @arg PMU_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PMU_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * + * @retval None + */ +void PMU_EnterSleepMode(PMU_SLEEPENTRY_T entry) +{ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + if (entry == PMU_SLEEPENTRY_WFI) + { + __WFI(); + } + else + { + __SEV(); + __WFE(); + __WFE(); + } +} + +/*! + * @brief Enters STOP mode + * + * @param regulator: specifies the regulator state in STOP mode + * This parameter can be one of the following values: + * @arg PMU_REGULATOR_ON: STOP mode with regulator ON + * @arg PMU_REGULATOR_LowPower: STOP mode with regulator in low power mode + * + * @param entry: specifies if STOP mode in entered with WFI or WFE instruction + * This parameter can be one of the following values: + * @arg PMU_STOPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PMU_STOPENTRY_WFE: enter STOP mode with WFE instruction + * @arg PMU_STOPENTRY_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction + * + * @retval None + */ +void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOPENTRY_T entry) +{ + PMU->CTRL_B.PDDSCFG = BIT_RESET; + + PMU->CTRL_B.LPDSCFG = regulator; + + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + switch (entry) + { + case PMU_STOPENTRY_WFI: + + __WFI(); + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + break; + + case PMU_STOPENTRY_WFE: + __WFE(); + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + break; + + case PMU_STOPENTRY_SLEEPONEXIT: + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + break; + + default: + break; + } +} + +/*! + * @brief Enters STANDBY mode + * + * @param None + * + * @retval None + */ +void PMU_EnterSTANDBYMode(void) +{ + PMU->CTRL_B.PDDSCFG = BIT_SET; + + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + __WFI(); +} + +/*! + * @brief Checks whether the specified PMU flag is set or not + * + * @param flag: specifies the flag to check + * This parameter can be one of the following values: + * @arg PMU_FLAG_WUPF: Wake Up flag + * @arg PMU_FLAG_STDBYF: StandBy flag + * @arg PMU_FLAG_PVDOF: PVD output flag (Not for APM32F030) + * @arg PMU_FLAG_VREFINTF: VREFINT flag + * + * @retval The new state of PMU_FLAG (SET or RESET) + */ +uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) +{ + uint8_t bit; + + if ((PMU->CSTS & flag) != (uint32_t)RESET) + { + bit = SET; + } + else + { + bit = RESET; + } + + /** Return the flag status */ + return bit; +} + +/*! + * @brief Clears the PWR's pending flags + * + * @param flag: specifies the flag to clear + * This parameter can be one of the following values: + * @arg PMU_FLAG_WUPF: Wake Up flag + * @arg PMU_FLAG_STDBYF: StandBy flag + * + * @retval None + */ +void PMU_ClearStatusFlag(uint8_t flag) +{ + if (flag == PMU_FLAG_WUPF) + { + PMU->CTRL_B.WUFLGCLR = BIT_SET; + } + else if (flag == PMU_FLAG_STDBYF) + { + PMU->CTRL_B.SBFLGCLR = BIT_SET; + } +} + +/**@} end of group PMU_Functions*/ +/**@} end of group PMU_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_rcm.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_rcm.c new file mode 100644 index 0000000000..9214eb978a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_rcm.c @@ -0,0 +1,1520 @@ +/*! + * @file apm32f0xx_rcm.h + * + * @brief This file provides all the RCM firmware functions + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup RCM_Driver RCM Driver + @{ +*/ + +/** @defgroup RCM_Macros Macros + @{ +*/ + +/**@} end of group RCM_Macros*/ + +/** @defgroup RCM_Enumerations Enumerations + @{ +*/ + +/**@} end of group RCM_Enumerations*/ + +/** @defgroup RCM_Structures Structures + @{ +*/ + +/**@} end of group RCM_Structures*/ + +/** @defgroup RCM_Variables Variables + @{ +*/ + +/**@} end of group RCM_Variables*/ + +/** @defgroup RCM_Functions Functions + @{ +*/ + +/*! + * @brief Resets the clock configuration + * + * @param None + * + * @retval None + */ +void RCM_Reset(void) +{ + /** Set HSIEN bit */ + RCM->CTRL1_B.HSIEN = BIT_SET; + RCM->CFG1 &= (uint32_t)0x08FFB80C; + RCM->CTRL1 &= (uint32_t)0xFEF6FFFF; + RCM->CTRL1_B.HSEBCFG = BIT_RESET; + RCM->CFG1 &= (uint32_t)0xFFC0FFFF; + RCM->CFG2 &= (uint32_t)0xFFFFFFF0; + RCM->CFG3 &= (uint32_t)0xFFF0FEAC; + RCM->CTRL2_B.HSI14EN = BIT_RESET; + + /** Disable all interrupts and clear pending bits */ + RCM->INT = 0x00FF0000; +} + +/*! + * @brief Configures HSE + * + * @param state: state of the HSE + * This parameter can be one of the following values: + * @arg RCM_HSE_OPEN: turn ON the HSE oscillator + * @arg RCM_HSE_BYPASS: HSE oscillator bypassed with external clock + * + * @retval None + * + * @note HSE can not be stopped if it is used directly or through the PLL as system clock + */ +void RCM_ConfigHSE(RCM_HSE_T state) +{ + RCM->CTRL1_B.HSEEN = BIT_RESET; + + RCM->CTRL1_B.HSEBCFG = BIT_RESET; + + if (state == RCM_HSE_OPEN) + { + RCM->CTRL1_B.HSEEN = BIT_SET; + } + else if (state == RCM_HSE_BYPASS) + { + RCM->CTRL1_B.HSEBCFG = BIT_SET; + RCM->CTRL1_B.HSEEN = BIT_SET; + } +} + +/*! + * @brief Waits for HSE be ready + * + * @param None + * + * @retval SUCCESS HSE oscillator is stable and ready to use + * ERROR HSE oscillator not yet ready + */ +uint8_t RCM_WaitHSEReady(void) +{ + __IO uint32_t cnt; + + for (cnt = 0; cnt < HSE_STARTUP_TIMEOUT; cnt++) + { + if (RCM->CTRL1_B.HSERDYFLG == BIT_SET) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*! + * @brief Set HSI trimming value + * +* @param HSITrim: HSI trimming value + * This parameter must be a number between 0 and 0x1F. + * + * @retval None + */ +void RCM_SetHSITrim(uint8_t HSITrim) +{ + RCM->CTRL1_B.HSITRM = HSITrim; +} + +/*! + * @brief Enable HSI + * + * @param None + * + * @retval None + * + * @note HSI can not be stopped if it is used directly or through the PLL as system clock + */ +void RCM_EnableHSI(void) +{ + RCM->CTRL1_B.HSIEN = BIT_SET; +} + +/*! + * @brief Disable HSI + * + * @param None + * + * @retval None + * + * @note HSI can not be stopped if it is used directly or through the PLL as system clock + */ +void RCM_DisableHSI(void) +{ + RCM->CTRL1_B.HSIEN = BIT_RESET; +} + +/*! + * @brief Set HSI14 trimming value + * + * @param HSI14TRM: HSI trimming value + * This parameter must be a number between 0 and 0x1F. + * + * @retval None + */ +void RCM_SetHSI14Trim(uint8_t HSI14Trim) +{ + RCM->CTRL2_B.HSI14TRM = HSI14Trim; +} + +/*! + * @brief Enable HSI14 + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_EnableHSI14(void) +{ + RCM->CTRL2_B.HSI14EN = BIT_SET; +} + +/*! + * @brief Disable HSI14 + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_DisableHSI14(void) +{ + RCM->CTRL2_B.HSI14EN = BIT_RESET; +} + +/*! + * @brief Enable HSI14 ADC + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_EnableHSI14ADC(void) +{ + RCM->CTRL2_B.HSI14TO = BIT_SET; +} + +/*! + * @brief Disable HSI14 ADC + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_DisableHSI14ADC(void) +{ + RCM->CTRL2_B.HSI14TO = BIT_RESET; +} + +/*! + * @brief Configures LSE + * + * @param state: state of the LSE + * This parameter can be one of the following values: + * @arg RCM_LSE_OPEN: turn ON the HSE oscillator + * @arg RCM_LSE_BYPASS: HSE oscillator bypassed with external clock + * + * @retval None + * + * @note LSE can not be stopped if it is used directly or through the PLL as system clock + */ +void RCM_ConfigLSE(RCM_LSE_T state) +{ + RCM->BDCTRL_B.LSEEN = BIT_RESET; + + RCM->BDCTRL_B.LSEBCFG = BIT_RESET; + + if (state == RCM_LSE_OPEN) + { + RCM->BDCTRL_B.LSEEN = BIT_SET; + } + else if (state == RCM_LSE_BYPASS) + { + RCM->BDCTRL_B.LSEBCFG = BIT_SET; + RCM->BDCTRL_B.LSEEN = BIT_SET; + } +} + +/*! + * @brief Configures LSE drive capability + * + * @param state: State of the LSE Drive + * This parameter can be one of the following values: + * @arg RCM_LSE_DRIVE_Low: LSE oscillator low drive capability. + * @arg RCM_LSE_DRIVE_MediumLow: LSE oscillator medium low drive capability. + * @arg RCM_LSE_DRIVE_MediumHigh: LSE oscillator medium high drive capability. + * @arg RCM_LSE_DRIVE_High: LSE oscillator high drive capability. + * + * @retval None + * + * @note LSE can not be stopped if it is used directly or through the PLL as system clock + */ +void RCM_ConfigDriveLSE(RCM_LSE_DRIVE_T state) +{ + RCM->BDCTRL_B.LSEDRVCFG = state; +} + +/*! + * @brief Enable LSI + * + * @param None + * + * @retval None + * + * @note LSI can not be stopped if the IWDT is running + */ +void RCM_EnableLSI(void) +{ + RCM->CSTS_B.LSIEN = BIT_SET; +} + +/*! + * @brief Disable LSI + * + * @param None + * + * @retval None + * + * @note LSI can not be stopped if the IWDT is running + */ +void RCM_DisableLSI(void) +{ + RCM->CSTS_B.LSIEN = BIT_RESET; +} + +/*! + * @brief Configures the PLL clock source and multiplication factor + * + * @param pllSelect: PLL entry clock source select + * This parameter can be one of the following values: + * @arg RCM_PLL_SEL_HSI_DIV2: HSI clock divided by 2 selected as PLL clock source + * @arg RCM_PLL_SEL_HSE: HSE/CLKDIV1 selected as PLL clock entry + * @arg RCM_PLL_SEL_HSI48: HSI48 oscillator clock selected as PLL clock source, It's only for 072 and 091 devices + * @arg RCM_PLL_SEL_HSI: HSI clock selected as PLL clock entry, It's only for 072 and 091 devices + * + * @param pllMf: PLL multiplication factor + * This parameter can be RCM_PLLMF_x where x:[2,16] + * + * @retval None + * + * @note + */ +void RCM_ConfigPLL(RCM_PLL_SEL_T pllSelect, RCM_PLLMF_T pllMf) +{ + RCM->CFG1_B.PLLMULCFG = pllMf; + RCM->CFG1_B.PLLSRCSEL = pllSelect; +} + +/*! + * @brief Enables PLL + * + * @param None + * + * @retval None + * + * @note The PLL can not be disabled if it is used as system clock + */ +void RCM_EnablePLL(void) +{ + RCM->CTRL1_B.PLLEN = BIT_SET; +} + +/*! + * @brief Disable PLL + * + * @param None + * + * @retval None + * + * @note The PLL can not be disabled if it is used as system clock + */ +void RCM_DisablePLL(void) +{ + RCM->CTRL1_B.PLLEN = BIT_RESET; +} + +/*! + * @brief Enables HSI48 + * + * @param None + * + * @retval None + * + * @note It's only for APM32F072 and APM32F091 devices + */ +void RCM_EnableHSI48(void) +{ + RCM->CTRL2_B.HSI48EN = BIT_SET; +} + +/*! + * @brief Enables HSI48 + * + * @param None + * + * @retval None + * + * @note It's only for APM32F072 and APM32F091 devices + */ +void RCM_DisableHSI48(void) +{ + RCM->CTRL2_B.HSI48EN = BIT_RESET; +} + +/*! + * @brief Read HSI48 Calibration Value + * + * @param None + * + * @retval Return of HSI48 Value + */ +uint32_t RCM_ReadHSI48CalibrationValue(void) +{ + uint32_t calValue; + + calValue = RCM->CTRL2_B.HSI48CAL; + + return calValue; +} +/*! + * @brief Configures the CLK division factor + * + * @param state: specifies the PLLDIVCFG clock division factor. + * This parameter can be RCM_CLK_Divx where x:[1,16] + * + * @retval None + * + * @note This function must be used only when the PLL is disabled + */ +void RCM_ConfigCLKDIV(RCM_CLK_DIV_T state) +{ + RCM->CFG2_B.PLLDIVCFG = state; +} + +/*! + * @brief Enable Clock Security System + * + * @param None + * + * @retval None + */ +void RCM_EnableCCS(void) +{ + RCM->CTRL1_B.CSSEN = BIT_SET; +} + +/*! + * @brief Disable Clock Security System + * + * @param None + * + * @retval None + */ +void RCM_DisableCCS(void) +{ + RCM->CTRL1_B.CSSEN = BIT_RESET; +} + +#if defined (APM32F030) || defined (APM32F051) +/*! + * @brief Selects clock ouput source + * + * @param cocClock: specifies the clock source to output + * This parameter can be one of the following values: + * @arg RCM_COC_NO_CLOCK: No clock selected. + * @arg RCM_COC_HSI14: HSI14 oscillator clock selected. + * @arg RCM_COC_LSI: LSI oscillator clock selected. + * @arg RCM_COC_LSE: LSE oscillator clock selected. + * @arg RCM_COC_SYSCLK: System clock selected. + * @arg RCM_COC_HSI: HSI oscillator clock selected. + * @arg RCM_COC_HSE: HSE oscillator clock selected. + * @arg RCM_COC_PLLCLK_DIV_2: PLL clock divided by 2 selected. + * + * @retval None + */ +void RCM_ConfigCOC(RCM_COCCLK_T cocClock) +{ + RCM->CFG1_B.MCOSEL = cocClock; +} +#else + +/*! + * @brief Selects clock ouput source + * + * @param cocClock: specifies the clock source to output + * This parameter can be one of the following values: + * @arg RCM_COC_NO_CLOCK: No clock selected. + * @arg RCM_COC_HSI14: HSI14 oscillator clock selected. + * @arg RCM_COC_LSI: LSI oscillator clock selected. + * @arg RCM_COC_LSE: LSE oscillator clock selected. + * @arg RCM_COC_SYSCLK: System clock selected. + * @arg RCM_COC_HSI: HSI oscillator clock selected. + * @arg RCM_COC_HSE: HSE oscillator clock selected. + * @arg RCM_COC_PLLCLK_DIV_2: PLL clock divided by 2 selected. + * @arg RCM_COC_PLLCLK: PLL clock divided selected. + * @arg RCM_COC_HSI48: HSI48 oscillator clock selected. + * + * @param divided: specifies the prescaler on COC pin. + * This parameter can only be the following value: + * @arg RCM_COC_DIV_1: MCOSEL clock is divided by 1. + * @arg RCM_COC_DIV_2: MCOSEL clock is divided by 2. + * @arg RCM_COC_DIV_4: MCOSEL clock is divided by 4. + * @arg RCM_COC_DIV_8: MCOSEL clock is divided by 8. + * @arg RCM_COC_DIV_16: MCOSEL clock is divided by 16. + * @arg RCM_COC_DIV_32: MCOSEL clock is divided by 32. + * @arg RCM_COC_DIV_64: MCOSEL clock is divided by 64. + * @arg RCM_COC_DIV_128: MCOSEL clock is divided by 128. + * + * @retval None + */ +void RCM_ConfigCOC(RCM_COCCLK_T cocClock, RCM_COCPRE_T divided) +{ + RCM->CFG1_B.MCOPSC = divided; + + if (cocClock != RCM_COC_PLLCLK) + { + RCM->CFG1_B.MCOPLLPSC = BIT_RESET; + RCM->CFG1_B.MCOSEL = cocClock; + } + else + { + RCM->CFG1_B.MCOPLLPSC = BIT_SET; + RCM->CFG1_B.MCOSEL = 0x07; + } +} +#endif /* APM32F072 */ + +/*! + * @brief Configures the system clock + * + * @param sysClkSelect: specifies the clock source used as system clock + * This parameter can be one of the following values: + * @arg RCM_SYSCLK_SEL_HSI: HSI selected as system clock source + * @arg RCM_SYSCLK_SEL_HSE: HSE selected as system clock source + * @arg RCM_SYSCLK_SEL_PLL: PLL selected as system clock source + * @arg RCM_SYSCLK_SEL_HSI48: HSI48 selected as system clock source,It's only for 072 devices + * + * @retval None + */ +void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) +{ + RCM->CFG1_B.SCLKSEL = sysClkSelect; +} + +/*! + * @brief returns the clock source used as system clock + * + * @param None + * + * @retval The clock source used as system clock + */ +RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void) +{ + RCM_SYSCLK_SEL_T sysClock; + + sysClock = (RCM_SYSCLK_SEL_T)RCM->CFG1_B.SCLKSWSTS; + + return sysClock; +} + +/*! + * @brief Configures the AHB clock + * + * @param AHBDiv: AHB divider number. This clock is derived from the system clock (SYSCLK) + * This parameter can be one of the following values: + * @arg RCM_SYSCLK_DIV_1: AHB clock = SYSCLK + * @arg RCM_SYSCLK_DIV_2: AHB clock = SYSCLK/2 + * @arg RCM_SYSCLK_DIV_4: AHB clock = SYSCLK/4 + * @arg RCM_SYSCLK_DIV_8: AHB clock = SYSCLK/8 + * @arg RCM_SYSCLK_DIV_16: AHB clock = SYSCLK/16 + * @arg RCM_SYSCLK_DIV_64: AHB clock = SYSCLK/64 + * @arg RCM_SYSCLK_DIV_128: AHB clock = SYSCLK/128 + * @arg RCM_SYSCLK_DIV_256: AHB clock = SYSCLK/256 + * @arg RCM_SYSCLK_DIV_512: AHB clock = SYSCLK/512 + * + * @retval None + */ +void RCM_ConfigAHB(RCM_AHBDIV_T AHBDiv) +{ + RCM->CFG1_B.AHBPSC = AHBDiv; +} + +/*! + * @brief Configures the APB clock + * + * @param APBDiv: defines the APB clock divider. This clock is derived from the AHB clock (HCLK) + * This parameter can be one of the following values: + * @arg RCM_HCLK_DIV_1: APB clock = HCLK + * @arg RCM_HCLK_DIV_2: APB clock = HCLK/2 + * @arg RCM_HCLK_DIV_4: APB clock = HCLK/4 + * @arg RCM_HCLK_DIV_8: APB clock = HCLK/8 + * @arg RCM_HCLK_DIV_16: APB clock = HCLK/16 + * + * @retval None + */ +void RCM_ConfigAPB(RCM_APBDIV_T APBDiv) +{ + RCM->CFG1_B.APB1PSC = APBDiv; +} + +/*! + * @brief Configures the CEC clock + * + * @param CECClk: defines the CEC clock divider. This clock is derived + * from the HSI/244 (32768Hz) clock or LSI clock + * This parameter can be one of the following values: + * @arg RCM_CECCLK_HSI_DIV_224: CEC clock = HSI/244 (32768Hz) + * @arg RCM_CECCLK_LSI_DIV: CEC clock = LSI + * + * @retval None + */ +void RCM_ConfigCECCLK(RCM_CECCLK_T CECClk) +{ + RCM->CFG3_B.CECSEL = CECClk; +} + +/*! + * @brief Configures the I2C clock + * + * @param I2CClk: defines the I2C1 clock source. This clock is derived + * from the HSI or System clock. + * This parameter can be one of the following values: + * @arg RCM_I2C1CLK_HSI: I2C1 clock = HSI + * @arg RCM_I2C1CLK_SYSCLK: I2C1 clock = System Clock + * + * @retval None + */ +void RCM_ConfigI2CCLK(RCM_I2CCLK_T I2CClk) +{ + RCM->CFG3_B.I2C1SEL = I2CClk; +} + +/*! + * @brief Configures the USART clock (USARTCLK) + * + * @param USARTClk: defines the USART clock source. This clock is derived + * from the HSI or System clock. + * This parameter can be one of the following values: + * @arg RCM_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK) + * @arg RCM_USART1CLK_SYSCLK: USART1 clock = System Clock + * @arg RCM_USART1CLK_LSE: USART1 clock = LSE Clock + * @arg RCM_USART1CLK_HSI: USART1 clock = HSI Clock + * Under it's only for APM32F072 and APM32F091 devices + * @arg RCM_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK) + * @arg RCM_USART2CLK_SYSCLK: USART2 clock = System Clock + * @arg RCM_USART2CLK_LSE: USART2 clock = LSE Clock + * @arg RCM_USART2CLK_HSI: USART2 clock = HSI Clock + * Under it's only for APM32F091 devices + * @arg RCM_USART3CLK_PCLK: USART3 clock = APB Clock (PCLK) + * @arg RCM_USART3CLK_SYSCLK: USART3 clock = System Clock + * @arg RCM_USART3CLK_LSE: USART3 clock = LSE Clock + * @arg RCM_USART3CLK_HSI: USART3 clock = HSI Clock + * + * @retval None + */ +void RCM_ConfigUSARTCLK(RCM_USARTCLK_T USARTClk) +{ + if (USARTClk >> 16 == 1) + { + RCM->CFG3_B.USART1SEL = (uint32_t)(USARTClk & 0x00000003); + } + else if (USARTClk >> 17 == 1) + { + RCM->CFG3_B.USART2SEL = (uint32_t)(USARTClk & 0x00000003); + } + else + { + RCM->CFG3_B.USART3SEL = (uint32_t)(USARTClk & 0x00000003); + } +} + +/*! + * @brief Configures the USB clock (USBCLK) + * + * @param USBClk: defines the USB clock source. This clock is derived + * from the HSI48 or System clock. + * This parameter can be one of the following values: + * @arg RCM_USBCLK_HSI48: USB clock = HSI48 + * @arg RCM_USBCLK_PLLCLK: USB clock = PLL Clock + * + * @retval None + * + * @note It's only for APM32F072 devices + */ +void RCM_ConfigUSBCLK(RCM_USBCLK_T USBClk) +{ + RCM->CFG3_B.USBDSEL = USBClk; +} + +/*! + * @brief Read frequency of SYSCLK + * + * @param None + * + * @retval Return frequency of SYSCLK + */ +uint32_t RCM_ReadSYSCLKFreq(void) +{ + uint32_t sysClock, pllMull, plldiv, pllSource; + + sysClock = RCM->CFG1_B.SCLKSEL; + + switch (sysClock) + { + case RCM_SYSCLK_SEL_HSI: + sysClock = HSI_VALUE; + break; + + case RCM_SYSCLK_SEL_HSE: + sysClock = HSE_VALUE; + break; + + case RCM_SYSCLK_SEL_PLL: + pllMull = RCM->CFG1_B.PLLMULCFG + 2; + pllSource = RCM->CFG1_B.PLLSRCSEL; + plldiv = RCM->CFG2_B.PLLDIVCFG + 1; + + if (pllSource == 0x00) + { + sysClock = ((HSI_VALUE >> 1) / plldiv) * pllMull; + } + else if (pllSource == 0x01) + { + sysClock = (HSI_VALUE / plldiv) * pllMull; + } + else if (pllSource == 0x02) + { + sysClock = (HSE_VALUE / plldiv) * pllMull; + } + else + { + sysClock = (HSI48_VALUE / plldiv) * pllMull; + } + break; + + case RCM_SYSCLK_SEL_HSI48: + sysClock = HSI48_VALUE; + break; + + default: + sysClock = HSI_VALUE; + break; + } + + return sysClock; +} + +/*! + * @brief Read frequency of HCLK(AHB) + * + * @param None + * + * @retval Return frequency of HCLK + */ +uint32_t RCM_ReadHCLKFreq(void) +{ + uint32_t divider; + uint32_t sysClk, hclk; + uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sysClk = RCM_ReadSYSCLKFreq(); + divider = AHBPrescTable[RCM->CFG1_B.AHBPSC]; + hclk = sysClk >> divider; + + return hclk; +} + +/*! + * @brief Read frequency of PCLK + * + * @param None + * + * @retval PCLK1 return frequency of PCLK + */ +uint32_t RCM_ReadPCLKFreq(void) +{ + uint32_t hclk, pclk, divider; + uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + hclk = RCM_ReadSYSCLKFreq(); + + divider = APBPrescTable[RCM->CFG1_B.APB1PSC]; + pclk = hclk >> divider; + + return pclk; + +} + +/*! + * @brief Read frequency of ADC CLK + * + * @param None + * + * @retval Return frequency of ADC CLK + */ +uint32_t RCM_ReadADCCLKFreq(void) +{ + uint32_t adcClk, pclk; + + pclk = RCM_ReadPCLKFreq(); + + if (RCM->CFG3_B.ADCSEL) + { + if (RCM->CFG1_B.ADCPSC) + { + adcClk = pclk >> 2; + } + else + { + adcClk = pclk >> 1; + } + } + else + { + adcClk = HSI14_VALUE; + } + + return adcClk; +} + +/*! + * @brief Read frequency of CEC CLK + * + * @param None + * + * @retval Return frequency of CEC CLK + */ +uint32_t RCM_ReadCECCLKFreq(void) +{ + uint32_t cecClk; + + if (RCM->CFG3_B.CECSEL) + { + cecClk = LSE_VALUE; + } + else + { + cecClk = LSI_VALUE / 244; + } + + return cecClk; +} + +/*! + * @brief Read frequency of I2C1 CLK + * + * @param None + * + * @retval Return frequency of I2C1 CLK + */ +uint32_t RCM_ReadI2C1CLKFreq(void) +{ + uint32_t i2c1Clk, sysClk; + + sysClk = RCM_ReadSYSCLKFreq(); + + if (RCM->CFG3_B.I2C1SEL) + { + i2c1Clk = sysClk; + } + else + { + i2c1Clk = HSI_VALUE; + } + + return i2c1Clk; +} + +/*! + * @brief Read frequency of USART1 CLK + * + * @param None + * + * @retval Return frequency of USART1 CLK + */ +uint32_t RCM_ReadUSART1CLKFreq(void) +{ + uint32_t usart1Clk; + + if (RCM->CFG3_B.USART1SEL == 0x00) + { + usart1Clk = RCM_ReadPCLKFreq(); + } + else if (RCM->CFG3_B.USART1SEL == 0x01) + { + usart1Clk = RCM_ReadSYSCLKFreq(); + } + else if (RCM->CFG3_B.USART1SEL == 0x02) + { + usart1Clk = LSE_VALUE; + } + else if (RCM->CFG3_B.USART1SEL == 0x03) + { + usart1Clk = HSI_VALUE; + } + + return usart1Clk; +} + +/*! + * @brief Read frequency of USB CLK + * + * @param None + * + * @retval Return frequency of USB CLK + */ +uint32_t RCM_ReadUSBCLKFreq(void) +{ + uint32_t usbClk, pllClk, pllMull, clkDiv; + + if (RCM->CFG1_B.SCLKSWSTS & 0x02) + { + pllMull = RCM->CFG1_B.PLLMULCFG; + pllMull = pllMull + 2; + } + + if (RCM->CFG3_B.USBDSEL) + { + if (RCM->CFG1_B.PLLSRCSEL == 0x00) + { + pllClk = (HSI_VALUE >> 1) * pllMull; + } + else + { + clkDiv = (RCM->CFG2_B.PLLDIVCFG) + 1; + pllClk = (HSE_VALUE / clkDiv) * pllMull; + } + usbClk = pllClk; + } + else + { + usbClk = HSI48_VALUE; + } + + return usbClk; +} + +/*! + * @brief Read frequency of USART2 CLK + * + * @param None + * + * @retval Return frequency of USART2 CLK + */ +uint32_t RCM_ReadUSART2CLKFreq(void) +{ + uint32_t usart1Clk; + + if (RCM->CFG3_B.USART2SEL == 0x00) + { + usart1Clk = RCM_ReadPCLKFreq(); + } + else if (RCM->CFG3_B.USART2SEL == 0x01) + { + usart1Clk = RCM_ReadSYSCLKFreq(); + } + else if (RCM->CFG3_B.USART2SEL == 0x02) + { + usart1Clk = LSE_VALUE; + } + else if (RCM->CFG3_B.USART2SEL == 0x03) + { + usart1Clk = HSI_VALUE; + } + + return usart1Clk; +} + +/*! + * @brief Configures the RTC clock (RTCCLK) + * + * @param RTCClk: specifies the RTC clock source + * This parameter can be one of the following values: + * @arg RCM_RTCCLK_LSE: LSE selected as RTC clock + * @arg RCM_RTCCLK_LSI: LSI selected as RTC clock + * @arg RCM_RTCCLK_HSE_DIV_32: HSE divided by 32 selected as RTC clock + * + * @retval None + * + * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset + */ +void RCM_ConfigRTCCLK(RCM_RTCCLK_T RTCClk) +{ + RCM->BDCTRL_B.RTCSRCSEL = RTCClk; +} + +/*! + * @brief Enables the RTC clock + * + * @param None + * + * @retval None + */ +void RCM_EnableRTCCLK(void) +{ + RCM->BDCTRL_B.RTCCLKEN = BIT_SET; +} + +/*! + * @brief Disables the RTC clock + * + * @param None + * + * @retval None + */ +void RCM_DisableRTCCLK(void) +{ + RCM->BDCTRL_B.RTCCLKEN = BIT_RESET; +} + +/*! + * @brief Enable the Backup domain reset + * + * @param None + * + * @retval None + */ +void RCM_EnableBackupReset(void) +{ + RCM->BDCTRL_B.BDRST = BIT_SET; +} + +/*! + * @brief Disable the Backup domain reset + * + * @param None + * + * @retval None + */ +void RCM_DisableBackupReset(void) +{ + RCM->BDCTRL_B.BDRST = BIT_RESET; +} + +/*! + * @brief Enables AHB peripheral clock + * + * @param AHBPeriph: specifies the AHB peripheral to gates its clock + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_DMA1: DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2: DMA2 clock + * @arg RCM_AHB_PERIPH_SRAM: SRAM clock + * @arg RCM_AHB_PERIPH_FPU: FPU clock + * @arg RCM_AHB_PERIPH_CRC: CRC clock + * @arg RCM_AHB_PERIPH_GPIOA: GPIOA clock + * @arg RCM_AHB_PERIPH_GPIOB: GPIOB clock + * @arg RCM_AHB_PERIPH_GPIOC: GPIOC clock + * @arg RCM_AHB_PERIPH_GPIOD: GPIOD clock + * @arg RCM_AHB_PERIPH_GPIOE: GPIOE clock(Only for APM32F072 and APM32F091) + * @arg RCM_AHB_PERIPH_GPIOF: GPIOF clock + * @arg RCM_AHB_PERIPH_TSC: TSC clock + * + * @retval None + */ +void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph) +{ + RCM->AHBCLKEN |= AHBPeriph; +} + +/*! + * @brief Disable AHB peripheral clock + * + * @param AHBPeriph: specifies the AHB peripheral to gates its clock + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_DMA1: DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2: DMA2 clock + * @arg RCM_AHB_PERIPH_SRAM: SRAM clock + * @arg RCM_AHB_PERIPH_FPU: FPU clock + * @arg RCM_AHB_PERIPH_CRC: CRC clock + * @arg RCM_AHB_PERIPH_GPIOA: GPIOA clock + * @arg RCM_AHB_PERIPH_GPIOB: GPIOB clock + * @arg RCM_AHB_PERIPH_GPIOC: GPIOC clock + * @arg RCM_AHB_PERIPH_GPIOD: GPIOD clock + * @arg RCM_AHB_PERIPH_GPIOE: GPIOE clock(Only for APM32F072 and APM32F091) + * @arg RCM_AHB_PERIPH_GPIOF: GPIOF clock + * @arg RCM_AHB_PERIPH_TSC: TSC clock + * + * @retval None + */ +void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph) +{ + RCM->AHBCLKEN &= (uint32_t)~AHBPeriph; +} + +/*! + * @brief Enable the High Speed APB (APB2) peripheral clock + * + * @param APB2Periph: specifies the APB2 peripheral to gates its clock + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_SYSCFG: SYSCFG clock + * @arg RCM_APB2_PERIPH_USART6: USART6 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART7: USART7 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART8: USART8 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_ADC1: ADC1 clock + * @arg RCM_APB2_PERIPH_TMR1: TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1: SPI1 clock + * @arg RCM_APB2_PERIPH_USART1: USART1 clock + * @arg RCM_APB2_PERIPH_TMR15: TMR15 clock + * @arg RCM_APB2_PERIPH_TMR16: TMR16 clock + * @arg RCM_APB2_PERIPH_TMR17: TMR17 clock + * @arg RCM_APB2_PERIPH_DBGMCU: DBGMCU clock + * + * @retval None + */ +void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph) +{ + RCM->APBCLKEN2 |= APB2Periph; +} + +/*! + * @brief Disable the High Speed APB (APB2) peripheral clock + * + * @param APB2Periph: specifies the APB2 peripheral to gates its clock + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_SYSCFG: SYSCFG clock + * @arg RCM_APB2_PERIPH_USART6: USART6 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART7: USART7 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART8: USART8 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_ADC1: ADC1 clock + * @arg RCM_APB2_PERIPH_TMR1: TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1: SPI1 clock + * @arg RCM_APB2_PERIPH_USART1: USART1 clock + * @arg RCM_APB2_PERIPH_TMR15: TMR15 clock + * @arg RCM_APB2_PERIPH_TMR16: TMR16 clock + * @arg RCM_APB2_PERIPH_TMR17: TMR17 clock + * @arg RCM_APB2_PERIPH_DBGMCU: DBGMCU clock + * + * @retval None + */ +void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph) +{ + RCM->APBCLKEN2 &= (uint32_t)~APB2Periph; +} + +/*! + * @brief Enable the Low Speed APB (APB1) peripheral clock + * + * @param APB1Periph: specifies the APB1 peripheral to gates its clock + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2: TMR2 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_TMR3: TMR3 clock + * @arg RCM_APB1_PERIPH_TMR6: TMR6 clock + * @arg RCM_APB1_PERIPH_TMR7: TMR7 clock(Only for APM32F072) + * @arg RCM_APB1_PERIPH_TMR14: TMR14 clock + * @arg RCM_APB1_PERIPH_WWDT: WWDG clock + * @arg RCM_APB1_PERIPH_SPI2: SPI2 clock + * @arg RCM_APB1_PERIPH_USART2: USART2 clock + * @arg RCM_APB1_PERIPH_USART3: USART3 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART4: USART4 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART5: USART5 clock(Only for APM32F091) + * @arg RCM_APB1_PERIPH_I2C1: I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2: I2C2 clock + * @arg RCM_APB1_PERIPH_USB: USB clock(Only for APM32F072) + * @arg RCM_APB1_PERIPH_CAN: CAN clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CRS: CRS clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_PMU: PMU clock + * @arg RCM_APB1_PERIPH_DAC: DAC clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CEC: CEC clock(Only for APM32F072 and APM32F091) + * + * @retval None + */ +void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph) +{ + RCM->APBCLKEN1 |= APB1Periph; +} + +/*! + * @brief Disable the Low Speed APB (APB1) peripheral clock + * + * @param APB1Periph: specifies the APB1 peripheral to gates its clock + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2: TMR2 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_TMR3: TMR3 clock + * @arg RCM_APB1_PERIPH_TMR6: TMR6 clock + * @arg RCM_APB1_PERIPH_TMR7: TMR7 clock(Only for APM32F072) + * @arg RCM_APB1_PERIPH_TMR14: TMR14 clock + * @arg RCM_APB1_PERIPH_WWDT: WWDG clock + * @arg RCM_APB1_PERIPH_SPI2: SPI2 clock + * @arg RCM_APB1_PERIPH_USART2: USART2 clock + * @arg RCM_APB1_PERIPH_USART3: USART3 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART4: USART4 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART5: USART5 clock(Only for APM32F091) + * @arg RCM_APB1_PERIPH_I2C1: I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2: I2C2 clock + * @arg RCM_APB1_PERIPH_USB: USB clock(Only for APM32F072) + * @arg RCM_APB1_PERIPH_CAN: CAN clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CRS: CRS clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_PMU: PMU clock + * @arg RCM_APB1_PERIPH_DAC: DAC clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CEC: CEC clock(Only for APM32F072 and APM32F091) + * + * @retval None + */ +void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph) +{ + RCM->APBCLKEN1 &= (uint32_t)~APB1Periph; +} + +/*! + * @brief Enable Low Speed AHB peripheral reset + * + * @param AHBPeriph: specifies the AHB peripheral to reset + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_GPIOA: GPIOA reset + * @arg RCM_AHB_PERIPH_GPIOB: GPIOB reset + * @arg RCM_AHB_PERIPH_GPIOC: GPIOC reset + * @arg RCM_AHB_PERIPH_GPIOD: GPIOD reset + * @arg RCM_AHB_PERIPH_GPIOE: GPIOE clock(Only for APM32F072 and APM32F091) + * @arg RCM_AHB_PERIPH_GPIOF: GPIOF reset + * @arg RCM_AHB_PERIPH_TSC: TSC clock + * + * @retval None + */ +void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph) +{ + RCM->AHBRST |= AHBPeriph; +} + +/*! + * @brief Disable Low Speed AHB peripheral reset + * + * @param AHBPeriph: specifies the AHB peripheral to reset + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_GPIOA: GPIOA reset + * @arg RCM_AHB_PERIPH_GPIOB: GPIOB reset + * @arg RCM_AHB_PERIPH_GPIOC: GPIOC reset + * @arg RCM_AHB_PERIPH_GPIOD: GPIOD reset + * @arg RCM_AHB_PERIPH_GPIOE: GPIOE clock(Only for APM32F072 and APM32F091) + * @arg RCM_AHB_PERIPH_GPIOF: GPIOF reset + * @arg RCM_AHB_PERIPH_TSC: TSC clock + * + * @retval None + */ +void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph) +{ + RCM->AHBRST &= (uint32_t)~AHBPeriph; +} + +/*! + * @brief Enable Low Speed APB (APB1) peripheral reset + * + * @param APB1Periph: specifies the APB1 peripheral to reset + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2: TMR2 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_TMR3: TMR3 clock + * @arg RCM_APB1_PERIPH_TMR6: TMR6 clock + * @arg RCM_APB1_PERIPH_TMR7: TMR7 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_TMR14: TMR14 clock + * @arg RCM_APB1_PERIPH_WWDT: WWDG clock + * @arg RCM_APB1_PERIPH_SPI2: SPI2 clock + * @arg RCM_APB1_PERIPH_USART2: USART2 clock + * @arg RCM_APB1_PERIPH_USART3: USART3 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART4: USART4 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART5: USART5 clock(Only for APM32F091) + * @arg RCM_APB1_PERIPH_I2C1: I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2: I2C2 clock + * @arg RCM_APB1_PERIPH_USB: USB clock(Only for APM32F072) + * @arg RCM_APB1_PERIPH_CAN: CAN clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CRS: CRS clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_PMU: PMU clock + * @arg RCM_APB1_PERIPH_DAC: DAC clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CEC: CEC clock(Only for APM32F072 and APM32F091) + * + * @retval None + */ +void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph) +{ + RCM->APBRST1 |= APB1Periph; +} + +/*! + * @brief Disable Low Speed APB (APB1) peripheral reset + * + * @param APB1Periph: specifies the APB1 peripheral to reset + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2: TMR2 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_TMR3: TMR3 clock + * @arg RCM_APB1_PERIPH_TMR6: TMR6 clock + * @arg RCM_APB1_PERIPH_TMR7: TMR7 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_TMR14: TMR14 clock + * @arg RCM_APB1_PERIPH_WWDT: WWDG clock + * @arg RCM_APB1_PERIPH_SPI2: SPI2 clock + * @arg RCM_APB1_PERIPH_USART2: USART2 clock + * @arg RCM_APB1_PERIPH_USART3: USART3 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART4: USART4 clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_USART5: USART5 clock(Only for APM32F091) + * @arg RCM_APB1_PERIPH_I2C1: I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2: I2C2 clock + * @arg RCM_APB1_PERIPH_USB: USB clock(Only for APM32F072) + * @arg RCM_APB1_PERIPH_CAN: CAN clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CRS: CRS clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_PMU: PMU clock + * @arg RCM_APB1_PERIPH_DAC: DAC clock(Only for APM32F072 and APM32F091) + * @arg RCM_APB1_PERIPH_CEC: CEC clock(Only for APM32F072 and APM32F091) + * + * @retval None + */ +void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph) +{ + RCM->APBRST1 &= (uint32_t)~APB1Periph; +} + +/*! + * @brief Enable High Speed APB (APB2) peripheral reset + * + * @param APB2Periph: specifies the APB2 peripheral to reset + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_SYSCFG: SYSCFG clock + * @arg RCM_APB2_PERIPH_USART6: USART6 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART7: USART7 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART8: USART8 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_ADC1: ADC1 clock + * @arg RCM_APB2_PERIPH_TMR1: TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1: SPI1 clock + * @arg RCM_APB2_PERIPH_USART1: USART1 clock + * @arg RCM_APB2_PERIPH_TMR15: TMR15 clock + * @arg RCM_APB2_PERIPH_TMR16: TMR16 clock + * @arg RCM_APB2_PERIPH_TMR17: TMR17 clock + * @arg RCM_APB2_PERIPH_DBGMCU: DBGMCU clock + * + * @retval None + */ +void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph) +{ + RCM->APBRST2 |= APB2Periph; +} + +/*! + * @brief Disable High Speed APB (APB2) peripheral reset + * + * @param APB2Periph: specifies the APB2 peripheral to reset + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_SYSCFG: SYSCFG clock + * @arg RCM_APB2_PERIPH_USART6: USART6 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART7: USART7 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_USART8: USART8 clock(Only for APM32F091) + * @arg RCM_APB2_PERIPH_ADC1: ADC1 clock + * @arg RCM_APB2_PERIPH_TMR1: TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1: SPI1 clock + * @arg RCM_APB2_PERIPH_USART1: USART1 clock + * @arg RCM_APB2_PERIPH_TMR15: TMR15 clock + * @arg RCM_APB2_PERIPH_TMR16: TMR16 clock + * @arg RCM_APB2_PERIPH_TMR17: TMR17 clock + * @arg RCM_APB2_PERIPH_DBGMCU: DBGMCU clock + * + * @retval None + */ +void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph) +{ + RCM->APBRST2 &= (uint32_t)~APB2Periph; +} + +/*! + * @brief Enable the specified RCM interrupts + * + * @param interrupt: specifies the RCM interrupt source to check + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY: LSI ready interrupt + * @arg RCM_INT_LSERDY: LSE ready interrupt + * @arg RCM_INT_HSIRDY: HSI ready interrupt + * @arg RCM_INT_HSERDY: HSE ready interrupt + * @arg RCM_INT_PLLRDY: PLL ready interrupt + * @arg RCM_INT_HSI14RDY: HSI14 ready interrupt + * @arg RCM_INT_HSI48RDY: HSI48 ready interrupt(Only for APM32F072 and APM32F091 devices) + * + * @retval None + */ +void RCM_EnableInterrupt(uint8_t interrupt) +{ + RCM->INT |= (interrupt << 8); +} + +/*! + * @brief Disable the specified RCM interrupts + * + * @param interrupt: specifies the RCM interrupt source to check + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY: LSI ready interrupt + * @arg RCM_INT_LSERDY: LSE ready interrupt + * @arg RCM_INT_HSIRDY: HSI ready interrupt + * @arg RCM_INT_HSERDY: HSE ready interrupt + * @arg RCM_INT_PLLRDY: PLL ready interrupt + * @arg RCM_INT_HSI14RDY: HSI14 ready interrupt + * @arg RCM_INT_HSI48RDY: HSI48 ready interrupt(Only for APM32F072 and APM32F091 devices) + * + * @retval None + */ +void RCM_DisableInterrupt(uint8_t interrupt) +{ + RCM->INT &= ~(interrupt << 8); +} + +/*! + * @brief Read the specified RCM flag status + * + * @param flag: specifies the flag to check + * This parameter can be one of the following values: + * @arg RCM_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCM_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCM_FLAG_PLLRDY: PLL clock ready + * @arg RCM_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCM_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCM_FLAG_V18PRRST: V1.8 power domain reset + * @arg RCM_FLAG_OBRST: Option Byte Loader (OBL) reset + * @arg RCM_FLAG_PINRST: Pin reset + * @arg RCM_FLAG_PWRRST: POR/PDR reset + * @arg RCM_FLAG_SWRST: Software reset + * @arg RCM_FLAG_IWDTRST: Independent Watchdog reset + * @arg RCM_FLAG_WWDTRST: Window Watchdog reset + * @arg RCM_FLAG_LPRRST: Low Power reset + * @arg RCM_FLAG_HSI14RDY: HSI14 clock ready + * @arg RCM_FLAG_HSI48RDY: HSI48 clock ready(Only for APM32F072 and APM32F091) + * + * @retval The new state of flag (SET or RESET) + */ +uint16_t RCM_ReadStatusFlag(RCM_FLAG_T flag) +{ + uint32_t reg, bit; + + bit = (uint32_t)(1 << (flag & 0xff)); + + reg = (flag >> 8) & 0xff; + + switch (reg) + { + case 0: + reg = RCM->CTRL1; + break; + + case 1: + reg = RCM->BDCTRL; + break; + + case 2: + reg = RCM->CSTS; + break; + + case 3: + reg = RCM->CTRL2; + break; + + default: + break; + } + + if (reg & bit) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the RCM reset flags + * + * @param None + * + * @retval None + * + * @note The reset flags are: + * RCM_FLAG_V18PRRST; RCM_FLAG_OBRST; RCM_FLAG_PINRST; RCM_FLAG_PWRRST; + * RCM_FLAG_SWRST; RCM_FLAG_IWDTRST; RCM_FLAG_WWDTRST; RCM_FLAG_LPRRST; + */ +void RCM_ClearStatusFlag(void) +{ + RCM->CSTS_B.RSTFLGCLR = BIT_SET; +} + +/*! + * @brief Read the specified RCM interrupt Flag + * + * @param flag: specifies the RCM interrupt source to check + * This parameter can be one of the following values: + * @arg RCM_INT_LSIRDY: LSI ready interrupt + * @arg RCM_INT_LSERDY: LSE ready interrupt + * @arg RCM_INT_HSIRDY: HSI ready interrupt + * @arg RCM_INT_HSERDY: HSE ready interrupt + * @arg RCM_INT_PLLRDY: PLL ready interrupt + * @arg RCM_INT_HSI14RDY: HSI14 ready interrupt + * @arg RCM_INT_HSI48RDY: HSI48 ready interrupt(Only for APM32F072 and APM32F091 devices) + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of intFlag (SET or RESET) + */ +uint8_t RCM_ReadIntFlag(RCM_INT_T flag) +{ + uint8_t ret; + + ret = (RCM->INT& flag) ? SET : RESET; + + return ret; +} + +/*! + * @brief Clears the interrupt flag + * + * @param flag: specifies the RCM interrupt source to check + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY: LSI ready interrupt + * @arg RCM_INT_LSERDY: LSE ready interrupt + * @arg RCM_INT_HSIRDY: HSI ready interrupt + * @arg RCM_INT_HSERDY: HSE ready interrupt + * @arg RCM_INT_PLLRDY: PLL ready interrupt + * @arg RCM_INT_HSI14RDY: HSI14 ready interrupt + * @arg RCM_INT_HSI48RDY: HSI48 ready interrupt(Only for APM32F072 and APM32F091 devices) + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval None + */ +void RCM_ClearIntFlag(uint8_t flag) +{ + uint32_t temp; + + temp = flag << 16; + RCM->INT |= temp; +} + +/**@} end of group RCM_Functions*/ +/**@} end of group RCM_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_rtc.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_rtc.c new file mode 100644 index 0000000000..fcc600a67b --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_rtc.c @@ -0,0 +1,1753 @@ +/*! + * @file apm32f0xx_rtc.c + * + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_rtc.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @defgroup RTC_Macros Macros + @{ +*/ + +/**@} end of group RTC_Macros */ + +/** @defgroup RRTC_Enumerations Enumerations + @{ +*/ + +/**@} end of group RTC_Macros */ + +/** @defgroup RTC_Structures Structures + @{ +*/ + +/**@} end of group RTC_Structures */ + +/** @defgroup RTC_Variables Variables + @{ +*/ + +/**@} end of group RTC_Variables */ + +/** @defgroup RTC_Functions Functions + @{ +*/ + +static uint8_t RTC_ByteConBcd2(uint8_t val); +static uint8_t RTC_Bcd2ConByte(uint8_t val); + +/*! + * @brief Deinitializes the RTC registers to their default reset values + * + * @param None + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_Reset(void) +{ + RTC_DisableWriteProtection(); + + if (RTC_EnableInit() == ERROR) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC->TIME = (uint32_t)0x00000000; + RTC->AUTORLD = (uint32_t)0x0000FFFF; + RTC->DATE = (uint32_t)0x00002101; + RTC->CTRL &= (uint32_t)0x00000000; + RTC->PSC = (uint32_t)0x007F00FF; + RTC->ALRMA = (uint32_t)0x00000000; + RTC->SHIFT = (uint32_t)0x00000000; + RTC->CAL = (uint32_t)0x00000000; + RTC->ALRMASS = (uint32_t)0x00000000; + + RTC->STS = (uint32_t)0x00000007; + RTC->TACFG = 0x00000000; + + if (RTC_WaitForSynchro() == ERROR) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC_EnableWriteProtection(); + return SUCCESS; + } + } +} + +/*! + * @brief Deinitializes the RTC registers to their default reset values + * + * @param Struct : pointer to a RTC_Config_T structure which will be initialized + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_Config(RTC_Config_T* Struct) +{ + RTC_DisableWriteProtection(); + + if (RTC_EnableInit() == ERROR) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC->CTRL_B.TIMEFCFG = (Struct->format); + RTC->PSC_B.SPSC = (Struct->SynchPrediv); + RTC->PSC_B.APSC = (Struct->AsynchPrediv); + + RTC_DisableInit(); + RTC_EnableWriteProtection(); + return SUCCESS; + } +} + +/*! + * @brief Fills each RTC_ConfigStruct member with its default value + * + * @param Struct : pointer to a RTC_Config_T structure which will be initialized + * + * @retval None + */ +void RTC_ConfigStructInit(RTC_Config_T* Struct) +{ + Struct->format = RTC_HourFormat_24; + Struct->AsynchPrediv = (uint32_t)0x7F; + Struct->SynchPrediv = (uint32_t)0xFF; +} + +/*! + * @brief Enable the write protection for RTC registers + * + * @param None + * + * @retval None + */ +void RTC_EnableWriteProtection(void) +{ + RTC->WRPROT = 0xFF; +} + +/*! + * @brief Disable the write protection for RTC registers + * + * @param None + * + * @retval None + */ +void RTC_DisableWriteProtection(void) +{ + RTC->WRPROT = 0xCA; + RTC->WRPROT = 0x53; +} + +/*! + * @brief Enable the RTC Initialization mode. + * + * @param None + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_EnableInit(void) +{ + __IO uint32_t cnt = 0x00; + uint32_t initstatus = 0x00; + + if (RTC->STS_B.RINITFLG == BIT_RESET) + { + RTC->STS = (uint32_t)0xFFFFFFFF; + + do + { + initstatus = RTC->STS_B.RINITFLG; + cnt++; + } + while ((cnt != RTC_INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if (RTC->STS_B.RINITFLG != BIT_RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + return SUCCESS; + } +} + +/*! + * @brief Disable the RTC Initialization mode. + * + * @param None + * + * @retval None + */ +void RTC_DisableInit(void) +{ + RTC->STS_B.INITEN = BIT_RESET; +} + +/*! + * @brief Waits until the RTC Time and Date registers (RTC_TIME and RTC_DATA) are + * synchronized with RTC APB clock + * @param None + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_WaitForSynchro(void) +{ + __IO uint32_t cnt = 0x00; + uint32_t synchrostatus = 0x00; + + if (RTC->CTRL_B.RCMCFG == BIT_RESET) + { + return SUCCESS; + } + else + { + RTC_DisableWriteProtection(); + RTC->STS &= (uint32_t)0xFFFFFF5F; + + do + { + synchrostatus = RTC->STS_B.RSFLG; + cnt++; + } + while ((cnt != RTC_SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if (RTC->STS_B.RSFLG != BIT_RESET) + { + RTC_EnableWriteProtection(); + return SUCCESS; + } + else + { + RTC_EnableWriteProtection(); + return ERROR; + } + } +} + +/*! + * @brief Enables the RTC reference clock detection + * + * @param None + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_EnableRefClock(void) +{ + RTC_DisableWriteProtection(); + + if (RTC_EnableInit() == ERROR) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC->CTRL_B.RCLKDEN = BIT_SET; + RTC_DisableInit(); + RTC_EnableWriteProtection(); + return SUCCESS; + } +} + +/*! + * @brief Disable the RTC reference clock detection + * + * @param None + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_DisableRefClock(void) +{ + RTC_DisableWriteProtection(); + + if (RTC_EnableInit() == ERROR) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC->CTRL_B.RCLKDEN = BIT_RESET; + RTC_DisableInit(); + RTC_EnableWriteProtection(); + return SUCCESS; + } +} + +/*! + * @brief Enable the RTC reference clock detection + * + * @param None + * + * @retval None + */ +void RTC_EnableBypassShadow(void) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.RCMCFG = BIT_SET; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Disable the RTC reference clock detection + * + * @param None + * + * @retval None + */ +void RTC_DisableBypassShadow(void) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.RCMCFG = BIT_RESET; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Config the RTC current time + * + * @param format: specifies the format to write + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: format in Bin + * @arg RTC_FORMAT_BCD: format in BCD + * + * @param timeStruct: Pointer to a RTC_TIME_T structure that + * contains the configuration information for the RTC peripheral + * + * @retval None + */ +uint8_t RTC_ConfigTime(RTC_FORMAT_T format, RTC_TIME_T* timeStruct) +{ + uint8_t state = ERROR; + uint32_t temp = 0; + + if (format == RTC_FORMAT_BIN) + { + if (RTC->CTRL_B.TIMEFCFG == BIT_RESET) + { + timeStruct->H12 = RTC_H12_AM; + } + } + else + { + if (RTC->CTRL_B.TIMEFCFG == BIT_RESET) + { + timeStruct->H12 = RTC_H12_AM; + } + else + { + temp = RTC_Bcd2ConByte(timeStruct->hours); + } + } + + if (format != RTC_FORMAT_BIN) + { + temp = (((uint32_t)(timeStruct->hours) << 16) | \ + ((uint32_t)(timeStruct->minutes) << 8) | \ + ((uint32_t)(timeStruct->seconds)) | \ + ((uint32_t)(timeStruct->H12) << 22)); + } + else + { + temp = (((uint32_t)RTC_ByteConBcd2(timeStruct->hours) << 16) | \ + ((uint32_t)RTC_ByteConBcd2(timeStruct->minutes) << 8) | \ + ((uint32_t)RTC_ByteConBcd2(timeStruct->seconds)) | \ + ((uint32_t)(timeStruct->H12) << 22)); + } + + RTC_DisableWriteProtection(); + + if (RTC_EnableInit() == ERROR) + { + state = ERROR; + } + else + { + RTC->TIME = (uint32_t)(temp & 0x007F7F7F); + RTC_DisableInit(); + + if (RTC->CTRL_B.RCMCFG == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + state = ERROR; + } + else + { + state = SUCCESS; + } + } + else + { + state = SUCCESS; + } + } + + RTC_EnableWriteProtection(); + return state; +} + +/*! + * @brief Fills each timeStruct member with its default value + * + * @param timeStruct: Pointer to a RTC_TIME_T structure that + * contains the configuration information for the RTC peripheral + * + * @retval None + */ +void RTC_ConfigTimeStructInit(RTC_TIME_T* timeStruct) +{ + /** ALRMA Time Settings : Time = 00h:00mn:00sec */ + timeStruct->hours = 0; + timeStruct->minutes = 0; + timeStruct->seconds = 0; + timeStruct->H12 = RTC_H12_AM; +} + +/*! + * @brief Read the RTC current Time + * + * @param format: specifies the format to write + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: format in Bin + * @arg RTC_FORMAT_BCD: format in BCD + * + * @param timeStruct: Pointer to a RTC_TIME_T structure that + * contains the configuration information for the RTC peripheral + * + * @retval None + */ +void RTC_ReadTime(RTC_FORMAT_T format, RTC_TIME_T* timeStruct) +{ + uint32_t temp = 0; + temp = (uint32_t)((RTC->TIME) & 0x007F7F7F); + + timeStruct->hours = (uint8_t)((temp & 0x003F0000) >> 16); + timeStruct->minutes = (uint8_t)((temp & 0x00007F00) >> 8); + timeStruct->seconds = (uint8_t)(temp & 0x0000007F); + timeStruct->H12 = (uint8_t)((temp & 0x00400000) >> 22); + + if (format == RTC_FORMAT_BIN) + { + timeStruct->hours = (uint8_t)RTC_Bcd2ConByte(timeStruct->hours); + timeStruct->minutes = (uint8_t)RTC_Bcd2ConByte(timeStruct->minutes); + timeStruct->seconds = (uint8_t)RTC_Bcd2ConByte(timeStruct->seconds); + } +} + +/*! + * @brief Read the RTC current Calendar Subseconds value + * + * @param None + * + * @retval RTC current Calendar Subseconds value + */ +uint32_t RTC_ReadSubSecond(void) +{ + uint32_t temp = 0; + temp = (uint32_t)(RTC->SUBSEC); + (void)(RTC->DATE); + return (temp); +} + +/*! + * @brief Config the RTC current time + * + * @param format: specifies the format to write + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: format in Bin + * @arg RTC_FORMAT_BCD: format in BCD + * + * @param dateStruct: Pointer to a RTC_DATE_T structure that + * contains the configuration DATE information for the RTC peripheral + * + * @retval None + */ +uint8_t RTC_ConfigDate(RTC_FORMAT_T format, RTC_DATE_T* dateStruct) +{ + uint8_t state = ERROR; + uint32_t temp = 0; + + if (format != RTC_FORMAT_BIN) + { + temp = RTC_Bcd2ConByte(dateStruct->month); + temp = RTC_Bcd2ConByte(dateStruct->date); + } + + if (format != RTC_FORMAT_BIN) + { + temp = (((uint32_t)(dateStruct->year) << 16) | \ + ((uint32_t)(dateStruct->month) << 8) | \ + ((uint32_t)(dateStruct->date)) | \ + ((uint32_t)(dateStruct->weekday) << 13)); + } + else + { + temp = (((uint32_t)RTC_ByteConBcd2(dateStruct->year) << 16) | \ + ((uint32_t)RTC_ByteConBcd2(dateStruct->month) << 8) | \ + ((uint32_t)RTC_ByteConBcd2(dateStruct->date)) | \ + ((uint32_t)(dateStruct->weekday) << 13)); + + } + + RTC_DisableWriteProtection(); + + if (RTC_EnableInit() == ERROR) + { + state = ERROR; + } + else + { + RTC->DATE = (uint32_t)(temp & 0x00FFFF3F); + RTC_DisableInit(); + + if (RTC->CTRL_B.RCMCFG == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + state = ERROR; + } + else + { + state = SUCCESS; + } + } + else + { + state = SUCCESS; + } + } + + RTC_EnableWriteProtection(); + return state; +} + +/*! + * @brief Fills each dateStruct member with its default value + * + * @param dateStruct: Pointer to a RTC_DATE_T structure that + * contains the configuration DATE information for the RTC peripheral + * @retval None + */ +void RTC_ConfigDateStructInit(RTC_DATE_T* dateStruct) +{ + dateStruct->weekday = RTC_WEEKDAY_MONDAY; + dateStruct->month = RTC_MONTH_JANUARY; + dateStruct->date = 1; + dateStruct->year = 0; +} + +/*! + * @brief the RTC current date + * + * @param format: specifies the format to write + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: format in Bin + * @arg RTC_FORMAT_BCD: format in BCD + * + * @param dateStruct: Pointer to a RTC_DATE_T structure that + * contains the configuration DATE information for the RTC peripheral + * + * @retval None + */ +void RTC_ReadDate(RTC_FORMAT_T format, RTC_DATE_T* dateStruct) +{ + uint32_t temp = 0; + temp = (uint32_t)((RTC->DATE) & 0x00FFFF3F); + + dateStruct->year = (uint8_t)((temp & 0x00FF0000) >> 16); + dateStruct->month = (uint8_t)((temp & 0x00001F00) >> 8); + dateStruct->date = (uint8_t)(temp & 0x0000003F); + dateStruct->weekday = (uint8_t)((temp & 0x0000E000) >> 13); + + if (format == RTC_FORMAT_BIN) + { + dateStruct->year = (uint8_t)RTC_Bcd2ConByte(dateStruct->year); + dateStruct->month = (uint8_t)RTC_Bcd2ConByte(dateStruct->month); + dateStruct->date = (uint8_t)RTC_Bcd2ConByte(dateStruct->date); + dateStruct->weekday = (uint8_t)(dateStruct->weekday); + } +} + +/*! + * @brief Config the specified RTC ALRMA + * + * @param format: specifies the format to write + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: format in Bin + * @arg RTC_FORMAT_BCD: format in BCD + * + * @param alarmStruct: Pointer to a RTC_ALARM_T structure that + * contains the configuration ALRMA information for the RTC peripheral + * + * @retval None + */ +void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T* alarmStruct) +{ + uint32_t temp = 0; + + if (format != RTC_FORMAT_BCD) + { + if (RTC->CTRL_B.TIMEFCFG == BIT_RESET) + { + alarmStruct->time.H12 = 0x00; + } + } + else + { + if (RTC->CTRL_B.TIMEFCFG == BIT_RESET) + { + alarmStruct->time.H12 = 0x00; + } + else + { + temp = RTC_Bcd2ConByte(alarmStruct->time.hours); + } + + if (alarmStruct->AlarmDateWeekDaySel == RTC_WEEKDAY_SEL_DATE) + { + temp = RTC_ByteConBcd2(alarmStruct->AlarmDateWeekDay); + } + else + { + temp = RTC_ByteConBcd2(alarmStruct->AlarmDateWeekDay); + } + } + + if (format == RTC_FORMAT_BCD) + { + temp = (((uint32_t)(alarmStruct->time.hours) << 16) | \ + ((uint32_t)(alarmStruct->time.minutes) << 8) | \ + ((uint32_t)alarmStruct->time.seconds) | \ + ((uint32_t)(alarmStruct->time.H12) << 22) | \ + ((uint32_t)(alarmStruct->AlarmDateWeekDay) << 24) | \ + ((uint32_t)alarmStruct->AlarmDateWeekDaySel << 30) | \ + ((uint32_t)alarmStruct->AlarmMask)); + } + else + { + temp = (((uint32_t)RTC_ByteConBcd2(alarmStruct->time.hours) << 16) | \ + ((uint32_t)RTC_ByteConBcd2(alarmStruct->time.minutes) << 8) | \ + ((uint32_t)RTC_ByteConBcd2(alarmStruct->time.seconds)) | \ + ((uint32_t)(alarmStruct->time.H12) << 22) | \ + ((uint32_t)RTC_ByteConBcd2(alarmStruct->AlarmDateWeekDay) << 24) | \ + ((uint32_t)alarmStruct->AlarmDateWeekDaySel << 30) | \ + ((uint32_t)alarmStruct->AlarmMask)); + } + + RTC_DisableWriteProtection(); + RTC->ALRMA = temp; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Fills each alarmStruct member with its default value + * + * @param alarmStruct: Pointer to a RTC_ALARM_T structure that + * contains the configuration ALRMA information for the RTC peripheral + * + * @retval None + */ +void RTC_ConfigAlarmStructInit(RTC_ALARM_T* alarmStruct) +{ + alarmStruct->time.hours = 1; + alarmStruct->time.minutes = 2; + alarmStruct->time.seconds = 3; + alarmStruct->time.H12 = RTC_H12_AM; + alarmStruct->AlarmDateWeekDay = 1; + alarmStruct->AlarmDateWeekDaySel = RTC_WEEKDAY_SEL_DATE; + alarmStruct->AlarmMask = RTC_MASK_NONE; +} + +/*! + * @brief Get the RTC ALRMA value and masks + * + * @param format: specifies the format to write + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: format in Bin + * @arg RTC_FORMAT_BCD: format in BCD + * + * @param alarmStruct: Pointer to a RTC_ALARM_T structure that + * contains the configuration ALRMA information for the RTC peripheral + * + * @retval None + */ +void RTC_ReadAlarm(RTC_FORMAT_T format, RTC_ALARM_T* alarmStruct) +{ + uint8_t day_d, day_u, hours_d, hours_u, minutes_d, minutes_u, seconds_d, seconds_u; + uint32_t day_mask, hours_mask, minutes_mask, seconds_mask; + + day_d = RTC->ALRMA_B.DAYT << 0x04; + day_u = RTC->ALRMA_B.DAYU; + hours_d = RTC->ALRMA_B.HRT << 0x04; + hours_u = RTC->ALRMA_B.HRU; + minutes_d = RTC->ALRMA_B.MINT << 0x04; + minutes_u = RTC->ALRMA_B.MINU; + seconds_d = RTC->ALRMA_B.SECT << 0x04; + seconds_u = RTC->ALRMA_B.SECU; + + day_mask = RTC->ALRMA_B.DATEMEN << 8; + hours_mask = RTC->ALRMA_B.HRMEN << 8; + minutes_mask = RTC->ALRMA_B.MINMEN << 8; + seconds_mask = RTC->ALRMA_B.SECMEN << 7; + + alarmStruct->time.hours = (uint8_t)(hours_d | hours_u); + alarmStruct->time.minutes = (uint8_t)(minutes_d | minutes_u); + alarmStruct->time.seconds = (uint8_t)(seconds_d | seconds_u); + alarmStruct->time.H12 = (uint8_t)(RTC->ALRMA_B.TIMEFCFG); + alarmStruct->AlarmDateWeekDay = (uint8_t)(day_d | day_u); + alarmStruct->AlarmDateWeekDaySel = (RTC_WEEKDAY_SEL_T)(RTC->ALRMA_B.WEEKSEL); + alarmStruct->AlarmMask = (uint32_t)(day_mask | hours_mask | minutes_mask | seconds_mask); + + if (format == RTC_FORMAT_BIN) + { + alarmStruct->time.hours = (uint8_t)RTC_Bcd2ConByte(alarmStruct->time.hours); + alarmStruct->time.minutes = (uint8_t)RTC_Bcd2ConByte(alarmStruct->time.minutes); + alarmStruct->time.seconds = (uint8_t)RTC_Bcd2ConByte(alarmStruct->time.seconds); + alarmStruct->AlarmDateWeekDay = (uint8_t)RTC_Bcd2ConByte(alarmStruct->AlarmDateWeekDay); + } +} + +/*! + * @brief Enable the RTC ALRMA. + * + * @param None + * + * @retval None + */ +void RTC_EnableAlarm(void) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.ALREN = BIT_SET; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Disable the the RTC ALRMA. + * + * @param None + * + * @retval None + */ +uint8_t RTC_DisableAlarm(void) +{ + __IO uint32_t count = 0x00; + RTC_DisableWriteProtection(); + RTC->CTRL_B.ALREN = BIT_RESET; + + while ((count != RTC_INITMODE_TIMEOUT) && ((RTC->STS_B.ALRWFLG) == BIT_RESET)) + { + count++; + } + + if ((RTC->STS_B.ALRWFLG) == BIT_RESET) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC_EnableWriteProtection(); + return SUCCESS; + } +} + +/*! + * @brief Read the RTC ALRMA Subseconds value + * + * @param val: specifies the value for ALRMA Sub Second + * this value must less than 0x00007FFF + * + * @param mask: specifies the mask for ALRMA Sub Second + * this value must less than 0x0f + * + * @retval None + */ +void RTC_ConfigAlarmSubSecond(uint32_t val, uint8_t mask) +{ + RTC_DisableWriteProtection(); + RTC->ALRMASS_B.SUBSEC = val; + RTC->ALRMASS_B.MASKSEL = mask; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Read the RTC ALRMA Subseconds value + * + * @param None + * + * @retval RTC ALRMA Subseconds value + */ +uint32_t RTC_ReadAlarmSubSecond(void) +{ + return (uint32_t)(RTC->ALRMASS_B.SUBSEC); +} + +/*! + * @brief Configure the RTC Wakeup clock source. + * + * @param wakeUpClock: Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WAKEUP_CLOCK_RTCDIV16 + * @arg RTC_WAKEUP_CLOCK_RTCDIV8 + * @arg RTC_WAKEUP_CLOCK_RTCDIV4 + * @arg RTC_WAKEUP_CLOCK_RTCDIV2 + * @arg RTC_WAKEUP_CLOCK_CK_SPRE_16B + * @arg RTC_WAKEUP_CLOCK_CK_SPRE_17B + * + * @retval None + * + * @note It's only for APM32F072 and APM32F091 devices + */ +void RTC_ConfigWakeUpClock(RTC_WAKEUP_CLOCK_T wakeUpClock) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.WUCLKSEL = wakeUpClock; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Configure the RTC Wakeup counter value. + * + * @param wakeUpValue: Wakeup auto-reload value. + * This parameter can be a value from 0x0000 to 0xFFFF. + * + * @retval None + * + * @note The value from 0x0000 to 0xFFFF. + */ +void RTC_SetWakeUpValue(uint32_t wakeUpValue) +{ + RTC_DisableWriteProtection(); + RTC->AUTORLD = wakeUpValue; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Read the RTC Wakeup counter value. + * + * @param None + * + * @retval The RTC WakeUp Counter value. + */ +uint32_t RTC_ReadWakeUpValue(void) +{ + return ((uint32_t)(RTC->AUTORLD & 0x0000FFFF)); +} + +/*! + * @brief Enable the RTC WakeUp timer. + * + * @param None + * + * @retval None + */ +void RTC_EnableWakeUp(void) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.WUTEN = BIT_SET; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Disable the RTC WakeUp timer. + * + * @param None + * + * @retval None + */ +uint8_t RTC_DisableWakeUp(void) +{ + __IO uint32_t count = 0x00; + RTC_DisableWriteProtection(); + + RTC->CTRL_B.WUTEN = BIT_RESET; + + while ((count != RTC_INITMODE_TIMEOUT) && ((RTC->STS_B.WUTWFLG) == BIT_RESET)) + { + count++; + } + + if ((RTC->STS_B.WUTWFLG) == BIT_RESET) + { + RTC_EnableWriteProtection(); + return ERROR; + } + else + { + RTC_EnableWriteProtection(); + return SUCCESS; + } +} + +/*! + * @brief Adds or substract one hour from the current time + * + * @param sav: specifies the DayLightSaving + * This parameter can be one of the following values: + * @arg RTC_DLS_SUB1H + * @arg RTC_DLS_ADD1H + * + * @param bit: specifies the DayLightSaving + * This parameter can be one of the following values: + * @arg RTC_SO_RESET + * @arg RTC_SO_SET + * + * @retval None + */ +void RTC_ConfigDayLightSaving(RTC_DAYLIGHT_SAVING_T sav, RTC_STORE_OPERATION_T bit) +{ + RTC_DisableWriteProtection(); + + if (sav == RTC_DLS_ADD1H) + { + RTC->CTRL_B.STCCFG = (uint32_t)BIT_SET; + RTC->CTRL_B.WTCCFG = (uint32_t)BIT_RESET; + } + else + { + RTC->CTRL_B.STCCFG = (uint32_t)BIT_RESET; + RTC->CTRL_B.WTCCFG = (uint32_t)BIT_SET; + } + + RTC->CTRL_B.BAKP = (uint32_t)bit; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Returns the RTC Day Light Saving stored operation + * + * @param None + * + * @retval RTC Day Light Saving stored operation + */ +uint32_t RTC_ReadStoreOperation(void) +{ + return (RTC->CTRL_B.BAKP); +} + +/*! + * @brief Enables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge + * + * @param opsel: specifies RTC TimeStamp functionality + * This parameter can be one of the following values: + * @arg RTC_OPSEL_DISABLE + * @arg RTC_OPSEL_ALARMA +* @arg RTC_OPSEL_WAKEUP: available only for APM32F072 and APM32F091 devices + * + * @param opp: specified time stamp pin stimulating edge + * This parameter can be one of the following values: + * @arg RTC_OPP_HIGH + * @arg RTC_OPP_LOW + * + * @retval None + */ +void RTC_ConfigOutput(RTC_OPSEL_T opsel, RTC_OPP_T opp) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.OUTSEL = (uint32_t)opsel; + RTC->CTRL_B.POLCFG = (uint32_t)opp; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Enable the RTC clock to be output through the relative pin + * + * @param None + * + * @retval None + */ +void RTC_EnableCalibOutput(void) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.CALOEN = BIT_SET; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Disable the RTC clock to be output through the relative pin + * + * @param None + * + * @retval None + */ +void RTC_DisableCalibOutput(void) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.CALOEN = BIT_RESET; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Configure the Calibration Pinout Selection (1Hz or 512Hz). + * + * @param calib: Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512Hz + * @arg RTC_CALIBOUTPUT_1Hz + * + * @retval None + */ +void RTC_ConfigCalibOutput(RTC_CALIB_OUTPUT_T calib) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.CALOSEL = (uint32_t)calib; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Configures the Synchronization Shift Control Settings. + * + * @param period: Select the Smooth Calibration period. + * This parameter can be can be one of the following values: + * @arg RTC_SCP_16SEC: The smooth calibration periode is 16. + * @arg RTC_SCP_8SEC: The smooth calibartion periode is 8s. + * + * @param bit: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SCPP_RESET: Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SCPP_SET: No RTCCLK pulses are added. + * + * @param value: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_ConfigSmoothCalib(RTC_SCP_T period, RTC_SCPP_T bit, uint32_t value) +{ + uint8_t state = ERROR; + uint32_t count = 0; + + RTC_DisableWriteProtection(); + + if (RTC->STS_B.RCALPFLG != BIT_RESET) + { + while ((RTC->STS_B.RCALPFLG != BIT_RESET) && (count != RTC_RECALPF_TIMEOUT)) + { + count++; + } + } + + if (RTC->STS_B.RCALPFLG == BIT_RESET) + { + if (period == RTC_SCP_16SEC) + { + RTC->CAL = ((((uint32_t)bit << 15) | \ + (uint32_t)BIT_SET << 13) | \ + (uint32_t)value); + } + else + { + RTC->CAL = ((((uint32_t)bit << 15) | \ + (uint32_t)BIT_SET << 14) | \ + (uint32_t)value); + } + + state = SUCCESS; + } + else + { + state = ERROR; + } + + RTC_EnableWriteProtection(); + return (state); +} + +/*! + * @brief Enables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge + * + * @param edge: Specifies the pin edge on which the TimeStamp is activated. + * This paramete can be one of the following: + * @arg RTC_TIME_STAMPEDGE_RISING: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TIME_STAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @retval None + */ +void RTC_EnableTimeStamp(RTC_TIMESTAMP_EDGE_T edge) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.TSEN = BIT_SET; + RTC->CTRL_B.TSETECFG = (uint32_t)edge; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge + * + * @param edge: Specifies the pin edge on which the TimeStamp is activated. + * This paramete can be one of the following: + * @arg RTC_TIME_STAMPEDGE_RISING: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TIME_STAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * + * @retval None + */ +void RTC_DisableTimeStamp(RTC_TIMESTAMP_EDGE_T edge) +{ + RTC_DisableWriteProtection(); + RTC->CTRL_B.TSEN = BIT_RESET; + RTC->CTRL_B.TSETECFG = (uint32_t)edge; + RTC_EnableWriteProtection(); +} + +/*! + * @brief Read the RTC TimeStamp value and masks + * + * @param format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: data in Binary format + * @arg RTC_Format_BCD: data in BCD format + * + * @param timeStruct: pointer to a RTC_TIME_T structure that will + * contains the TimeStamp time values. + * + * @param dateStruct: pointer to a RTC_DATE_T structure that will + * contains the TimeStamp date values. + * + * @retval None + */ +void RTC_ReadTimeDate(RTC_FORMAT_T format, RTC_TIME_T* timeStruct, RTC_DATE_T* dateStruct) +{ + uint32_t temptime = 0, tempdate = 0; + temptime = (uint32_t)((RTC->TSTIME) & 0x007F7F7F); + tempdate = (uint32_t)((RTC->TSDATE) & 0x00FFFF3F); + + timeStruct->hours = (uint8_t)((temptime & 0x003F0000) >> 16); + timeStruct->minutes = (uint8_t)((temptime & 0x00007F00) >> 8); + timeStruct->seconds = (uint8_t)(temptime & 0x0000007F); + timeStruct->H12 = (uint8_t)((temptime & 0x00400000) >> 22); + + dateStruct->year = 0; + dateStruct->month = (uint8_t)((tempdate & 0x00001F00) >> 8); + dateStruct->date = (uint8_t)(tempdate & 0x0000003F); + dateStruct->weekday = (uint8_t)((tempdate & 0x0000E000) >> 13); + + if (format == RTC_FORMAT_BIN) + { + timeStruct->hours = (uint8_t)RTC_Bcd2ConByte(timeStruct->hours); + timeStruct->minutes = (uint8_t)RTC_Bcd2ConByte(timeStruct->minutes); + timeStruct->seconds = (uint8_t)RTC_Bcd2ConByte(timeStruct->seconds); + + dateStruct->month = (uint8_t)RTC_Bcd2ConByte(dateStruct->month); + dateStruct->date = (uint8_t)RTC_Bcd2ConByte(dateStruct->date); + dateStruct->weekday = (uint8_t)(dateStruct->weekday); + } +} + +/*! + * @brief Get the RTC timestamp Subseconds value + * + * @param None + * + * @retval RTC current timestamp Subseconds value + */ +uint32_t RTC_ReadTimeStampSubSecond(void) +{ + return (uint32_t)(RTC->TSSUBSEC); +} + +/*! + * @brief Configures the select Tamper pin edge + * + * @param tamper: Selected tamper pin. + * This parameter can be one of the following values: + * @arg RTC_TAMPER_1: Select Tamper 1. + * @arg RTC_TAMPER_2: Select Tamper 2. + * @arg RTC_TAMPER_3: Select Tamper 3. (Only for APM32F072 and APM32F091 devices) + * + * @param trigger: Specifies the trigger on the tamper pin that stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TAMPER_TRIGGER_RISINGEDGE: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TAMPER_TRIGGER_FALLINGEDGE: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TAMPER_TRIGGER_LOWLEVEL: Low Level of the tamper pin causes tamper event. + * @arg RTC_TAMPER_TRIGGER_HIGHLEVEL: High Level of the tamper pin causes tamper event. + * + * @retval None + */ +void RTC_ConfigTamperTrigger(RTC_TAMPER_T tamper, RTC_TAMPER_TRIGGER_T trigger) +{ + if (trigger == RTC_TAMPER_TRIGGER_RISINGEDGE) + { + if (tamper == RTC_TAMPER_1) + { + RTC->TACFG_B.TP1ALCFG = BIT_RESET; + } + if (tamper == RTC_TAMPER_2) + { + RTC->TACFG_B.TP2ALCFG = BIT_RESET; + } + if (tamper == RTC_TAMPER_3) + { + RTC->TACFG_B.TP3ALCFG = BIT_RESET; + } + } + else + { + if (tamper == RTC_TAMPER_1) + { + RTC->TACFG_B.TP1ALCFG = BIT_SET; + } + if (tamper == RTC_TAMPER_2) + { + RTC->TACFG_B.TP2ALCFG = BIT_SET; + } + if (tamper == RTC_TAMPER_3) + { + RTC->TACFG_B.TP3ALCFG = BIT_SET; + } + } +} + +/*! + * @brief Enables the Tamper detection + * + * @param tamper: Selected tamper pin. + * This parameter can be one of the following values: + * @arg RTC_TAMPER_1: Select Tamper 1. + * @arg RTC_TAMPER_2: Select Tamper 2. + * @arg RTC_TAMPER_3: Select Tamper 3.(Only for APM32F072 and APM32F091 devices) + * + * @retval None + */ +void RTC_EnableTamper(RTC_TAMPER_T tamper) +{ + if (tamper == RTC_TAMPER_1) + { + RTC->TACFG_B.TP1EN = BIT_SET; + } + if (tamper == RTC_TAMPER_2) + { + RTC->TACFG_B.TP2EN = BIT_SET; + } + if (tamper == RTC_TAMPER_3) + { + RTC->TACFG_B.TP3EN = BIT_SET; + } + +} + +/*! + * @brief Disables the Tamper detection + * + * @param tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1: Select Tamper 1. + * @arg RTC_TAMPER_2: Select Tamper 2. + * @arg RTC_TAMPER_3: Select Tamper 3.(Only for APM32F072 and APM32F091 devices) + * + * @retval None + */ +void RTC_DisableTamper(RTC_TAMPER_T tamper) +{ + if (tamper == RTC_TAMPER_1) + { + RTC->TACFG_B.TP1EN = BIT_RESET; + } + if (tamper == RTC_TAMPER_2) + { + RTC->TACFG_B.TP2EN = BIT_RESET; + } + if (tamper == RTC_TAMPER_3) + { + RTC->TACFG_B.TP3EN = BIT_RESET; + } +} + +/*! + * @brief Configures the Tampers Filter + * + * @param filter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TAMPER_FILTER_DISABLE: Tamper filter is disabled. + * @arg RTC_TAMPER_FILTER_2SAMPLE: Tamper is activated after 2 consecutive samples at the active level + * @arg RTC_TAMPER_FILTER_4SAMPLE: Tamper is activated after 4 consecutive samples at the active level + * @arg RTC_TAMPER_FILTER_8SAMPLE: Tamper is activated after 8 consecutive samples at the active level + * + * + * @retval None + */ +void RTC_ConfigFilter(RTC_TAMPER_FILTER_T filter) +{ + RTC->TACFG_B.TPFCSEL = (uint32_t)filter; +} + +/*! + * @brief Configures the Tampers Sampling Frequency + * + * @param freq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * + * @retval None + */ +void RTC_ConfigSamplingFreq(RTC_TAMPER_SAMPLING_FREQ_T freq) +{ + RTC->TACFG_B.TPSFSEL = (uint32_t)freq; +} + +/*! + * @brief Configures the Precharge Duration + * + * @param duration: Specifies the Tampers Pins input Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_PRECHARGEDURATION_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle + * @arg RTC_PRECHARGEDURATION_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle + * @arg RTC_PRECHARGEDURATION_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle + * @arg RTC_PRECHARGEDURATION_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle + * + * @retval None + */ +void RTC_PinsPrechargeDuration(RTC_PRECHARGE_DURATION_T duration) +{ + RTC->TACFG_B.TPPRDUSEL = (uint32_t)duration; +} + +/*! + * @brief Enables the TimeStamp on Tamper Detection Event + * + * @param None + * + * @retval None + */ +void RTC_EnableTDE(void) +{ + RTC->TACFG_B.TPTSEN = BIT_SET; +} + +/*! + * @brief Disable the TimeStamp on Tamper Detection Event + * + * @param None + * + * @retval None + */ +void RTC_DisableTDE(void) +{ + RTC->TACFG_B.TPTSEN = BIT_RESET; +} + +/*! + * @brief Enable precharge of the selected Tamper pin + * + * @param None + * + * @retval None + */ +void RTC_EnablePullUp(void) +{ + RTC->TACFG_B.TPPUDIS = BIT_SET; +} + +/*! + * @brief Disable precharge of the selected Tamper pin + * + * @param None + * + * @retval None + */ +void RTC_DisablePullUp(void) +{ + RTC->TACFG_B.TPPUDIS = BIT_RESET; +} + +/*! + * @brief Writes a data in RTC Backup data. + * + * @param backup: RTC Backup data Register number. + * This parameter can be one of the following values: + * @arg RTC_BAKP_DATA0 + * @arg RTC_BAKP_DATA1 + * @arg RTC_BAKP_DATA2 + * @arg RTC_BAKP_DATA3 + * @arg RTC_BAKP_DATA4 + * @param data: Data to be written in the specified RTC Backup data register. + * + * @retval None + */ +void RTC_WriteBackup(RTC_BAKP_DATA_T backup, uint32_t data) +{ + switch (backup) + { + case 0: + RTC->BAKP0 = data; + break; + + case 1: + RTC->BAKP1 = data; + break; + + case 2: + RTC->BAKP2 = data; + break; + + case 3: + RTC->BAKP3 = data; + break; + + case 4: + RTC->BAKP4 = data; + break; + + default: + break; + } +} + +/*! + * @brief Reads a data in RTC Backup data. + * + * @param backup: RTC Backup data Register number. + * This parameter can be one of the following values: + * @arg RTC_BAKP_DATA0 + * @arg RTC_BAKP_DATA1 + * @arg RTC_BAKP_DATA2 + * @arg RTC_BAKP_DATA3 + * @arg RTC_BAKP_DATA4 + * + * @retval None + */ +uint32_t RTC_ReadBackup(RTC_BAKP_DATA_T backup) +{ + uint32_t data; + + switch (backup) + { + case 0: + data = RTC->BAKP0; + break; + + case 1: + data = RTC->BAKP1; + break; + + case 2: + data = RTC->BAKP2; + break; + + case 3: + data = RTC->BAKP3; + break; + + case 4: + data = RTC->BAKP4; + break; + + default: + break; + } + + return (data); +} + +/*! + * @brief Configures the RTC Output Pin mode + * + * @param output: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OPENDRAIN: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_PUSHPULL: RTC Output (PC13) is configured in + * Push Pull mode. + * + * @retval None + */ +void RTC_ConfigOutputType(RTC_OUTPUT_T output) +{ + RTC->TACFG_B.PC13VAL = (uint32_t)output; +} + +/*! + * @brief Configures the Synchronization Shift Control Settings. + * + * @param add1S: Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * + * @param subFS: Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * + * @retval SUCCESS or ERROR + */ +uint8_t RTC_ConfigSynchroShift(RTC_SHIFT_ADD1S_T add1S, uint32_t subFS) +{ + uint8_t state = ERROR; + uint32_t shpfcount = 0; + RTC_DisableWriteProtection(); + + if (RTC->STS_B.SOPFLG != BIT_RESET) + { + while ((RTC->STS_B.SOPFLG != BIT_RESET) && (shpfcount != RTC_SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + if (RTC->STS_B.SOPFLG == BIT_RESET) + { + if (RTC->CTRL_B.RCLKDEN == BIT_RESET) + { + RTC->SHIFT_B.ADD1SECEN = add1S; + RTC->SHIFT_B.SFSEC = subFS; + + if (RTC_WaitForSynchro() == ERROR) + { + state = ERROR; + } + else + { + state = SUCCESS; + } + } + else + { + state = ERROR; + } + } + else + { + state = ERROR; + } + + RTC_EnableWriteProtection(); + return (state); +} + +/*! + * @brief Enable RTC interrupts. + * + * @param interrupt: specifies the RTC interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_INT_ALR: ALRMA A interrupt mask + * @arg RTC_INT_WT: WakeUp Timer interrupt mask(only APM32F072 and APM32F091 devices) + * @arg RTC_INT_TS: Time Stamp interrupt mask + * @arg RTC_INT_TAMP: Tamper event interrupt mask + * + * @retval None + */ +void RTC_EnableInterrupt(uint32_t interrupt) +{ + RTC_DisableWriteProtection(); + RTC->CTRL |= (uint32_t)(interrupt & ~0x00000004); + RTC->TACFG |= (uint32_t)(interrupt & 0x00000004); + RTC_EnableWriteProtection(); +} + +/*! + * @brief Disable RTC interrupts. + * + * @param interrupt: specifies the RTC interrupt sources to be disable + * This parameter can be any combination of the following values: + * @arg RTC_INT_ALR: ALRMA A interrupt mask + * @arg RTC_INT_WT: WakeUp Timer interrupt mask(only APM32F072 and APM32F091 devices) + * @arg RTC_INT_TS: Time Stamp interrupt mask + * @arg RTC_INT_TAMP: Tamper event interrupt mask + * + * @retval None + */ +void RTC_DisableInterrupt(uint32_t interrupt) +{ + RTC_DisableWriteProtection(); + RTC->CTRL &= (uint32_t)~(interrupt & ~0x00000004); + RTC->TACFG &= (uint32_t)~(interrupt & 0x00000004); + RTC_EnableWriteProtection(); +} + +/*! + * @brief Read interrupt flag bit is set + * + * @param flag: specifies the flag to read. + * This parameter can be one of the following values: + * @arg RTC_INT_FLAG_ALR: ALRMA interrupt + * @arg RTC_INT_FLAG_TS: Time Stamp interrupt + * @arg RTC_INT_FLAG_WT: WakeUp Timer interrupt (only APM32F072 and APM32F091 devices) + * @arg RTC_INT_FLAG_TAMP1: Tamper1 event interrupt + * @arg RTC_INT_FLAG_TAMP2: Tamper2 event interrupt + * @arg RTC_INT_FLAG_TAMP3: Tamper3 event interrupt (Only for APM32F072 and APM32F091 devices) + * @retval The new state of flag (SET or RESET). + */ +uint8_t RTC_ReadIntFlag(RTC_INT_FLAG_T flag) +{ + uint32_t intEnable; + uint32_t intStatus; + + if (flag & 0x04) + { + intEnable = (uint32_t)RTC->TACFG_B.TPIEN; + intStatus = (uint32_t)(RTC->STS & (flag >> 4)); + } + else + { + intEnable = (uint32_t)RTC->CTRL; + intStatus = (uint32_t)(RTC->STS & (flag >> 4)); + } + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear RTC interrupt flag bit + * + * @param flag: specifies the flag to clear. + * This parameter can be any combination the following values: + * @arg RTC_INT_FLAG_ALR: ALRMA interrupt + * @arg RTC_INT_FLAG_TS: Time Stamp interrupt + * @arg RTC_INT_FLAG_WT: WakeUp Timer interrupt (only APM32F072 and APM32F091 devices) + * @arg RTC_INT_FLAG_TAMP1: Tamper1 event interrupt + * @arg RTC_INT_FLAG_TAMP2: Tamper2 event interrupt + * @arg RTC_INT_FLAG_TAMP3: Tamper3 event interrupt (Only for APM32F072 and APM32F091 devices) + * @retval The new state of flag (SET or RESET). + */ +void RTC_ClearIntFlag(uint32_t flag) +{ + RTC->STS &= (uint32_t) ~(flag >> 4); +} + +/*! + * @brief Checks whether the specified RTC flag is set or not. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_ISF + * @arg RTC_FLAG_RSF + * @arg RTC_FLAG_INTF + * @arg RTC_FLAG_ALRF + * @arg RTC_FLAG_WTF (only APM32F072 and APM32F091 devices) + * @arg RTC_FLAG_TSF + * @arg RTC_FLAG_TSOF + * @arg RTC_FLAG_TP1F + * @arg RTC_FLAG_TP2F + * @arg RTC_FLAG_TP3F (only APM32F072 and APM32F091 devices) + * @arg RTC_FLAG_RPF + * @retval The new state of RTC_FLAG (SET or RESET). + */ +uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag) +{ + return (RTC->STS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the RTC's status flags. + * @param flag: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TP3F: Tamper 3 event flag (only APM32F072 and APM32F091 devices) + * @arg RTC_FLAG_TP2F: Tamper 2 event flag + * @arg RTC_FLAG_TP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF : Time Stamp event flag + * @arg RTC_FLAG_WTF WakeUp Timer flag (only APM32F072 and APM32F091 devices) + * @arg RTC_FLAG_ALRF: ALRMA A flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + */ +void RTC_ClearStatusFlag(uint32_t flag) +{ + RTC->STS &= (uint32_t)~flag; +} + +/*! + * @brief Converts a 2 digit decimal to BCD format + * + * @param val: Byte to be converted + * + * @retval Converted byte + */ +static uint8_t RTC_ByteConBcd2(uint8_t val) +{ + uint8_t bcdhigh = 0; + + while (val >= 10) + { + bcdhigh++; + val -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | val); +} + +/*! + * @brief Convert from 2 digit BCD to Binary + * + * @param val: BCD value to be converted + * + * @retval Converted word + */ +static uint8_t RTC_Bcd2ConByte(uint8_t val) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(val & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (val & (uint8_t)0x0F)); +} + +/**@} end of group RTC_Functions*/ +/**@} end of group RTC_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver*/ + diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_spi.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_spi.c new file mode 100644 index 0000000000..3cbb93d35f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_spi.c @@ -0,0 +1,786 @@ +/*! + * @file apm32f0xx_spi.c + * + * @brief This file contains all the functions for the SPI peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_spi.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @defgroup SPI_Macros Macros + @{ +*/ + +/**@} end of group SPI_Macros */ + +/** @defgroup SPI_Enumerations Enumerations + @{ +*/ + +/**@} end of group SPI_Enumerations */ + +/** @defgroup SPI_Structures Structures + @{ +*/ + +/**@} end of group SPI_Structures */ + +/** @defgroup SPI_Variables Variables + @{ +*/ + +/**@} end of group SPI_Variables */ + +/** @defgroup SPI_Functions Functions + @{ +*/ + +/*! + * @brief Set the SPI peripheral registers to their default reset values + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_Reset(SPI_T* spi) +{ + if (spi == SPI1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); + } + else + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); + } +} + +/*! + * @brief Config the SPI peripheral according to the specified parameters in the adcConfig + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @param spiConfig: Pointer to a SPI_Config_T structure that + * contains the configuration information for the SPI peripheral + * + * @retval None + */ +void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig) +{ + spi->CTRL1_B.MSMCFG = spiConfig->mode; + spi->CTRL2_B.DSCFG = spiConfig->length; + spi->CTRL1_B.CPHA = spiConfig->phase; + spi->CTRL1_B.CPOL = spiConfig->polarity; + spi->CTRL1_B.SSEN = spiConfig->slaveSelect; + spi->CTRL1_B.LSBSEL = spiConfig->firstBit; + + spi->CTRL1 &= (uint16_t)~0xC400; + spi->CTRL1 |= (uint32_t)spiConfig->direction; + + spi->CTRL1_B.BRSEL = spiConfig->baudrateDiv; + + spi->CRCPOLY |= spiConfig->crcPolynomial; +} + +/*! + * @brief Config the SPI peripheral according to the specified parameters in the adcConfig + * + * @param spi: Select the the SPI peripheral.It can be SPI1 + * + * @param i2sConfig: Pointer to a SPI_Config_T structure that + * contains the configuration information for the SPI peripheral + * + * @retval None + */ +void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) +{ + uint16_t i2sDiv = 2, i2sOdd = 0, i2sLen = 1; + uint32_t sourceClock = 0, value = 0, temp = 0; + + spi->I2SPSC = 0x0002; + spi->I2SCFG &= 0xF040; + temp = spi->I2SCFG; + + if (i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT) + { + i2sDiv = (uint16_t)2; + i2sOdd = (uint16_t)0; + } + else + { + if (i2sConfig->length == I2S_DATA_LENGTH_16B) + { + i2sLen = 1; + } + else + { + i2sLen = 2; + } + + sourceClock = RCM_ReadSYSCLKFreq(); + + if (i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE) + { + value = (uint16_t)(((((sourceClock / 256) * 10) / i2sConfig->audioDiv)) + 5); + } + else + { + value = (uint16_t)(((((sourceClock / (32 * i2sLen)) * 10) / i2sConfig->audioDiv)) + 5); + } + + value = value / 10; + i2sOdd = (uint16_t)(value & (uint16_t)0x0001); + i2sDiv = (uint16_t)((value - i2sOdd) / 2); + } + + if ((i2sDiv < 2) || (i2sDiv > 0xFF)) + { + i2sDiv = 2; + i2sOdd = 0; + } + + spi->I2SPSC_B.I2SPSC = i2sDiv; + spi->I2SPSC_B.ODDPSC = i2sOdd; + spi->I2SPSC_B.MCOEN = i2sConfig->MCLKOutput; + spi->I2SCFG_B.MODESEL = BIT_SET; + spi->I2SCFG_B.I2SMOD = i2sConfig->mode; + spi->I2SCFG_B.CPOL = i2sConfig->polarity; + + temp = (uint16_t)((uint16_t)i2sConfig->standard | (uint16_t)i2sConfig->length); + spi->I2SCFG |= temp; +} + +/*! + * @brief Fills each spiConfig member with its default value + * + * @param spiConfig: Pointer to a SPI_Config_T structure which will be initialized + * + * @retval None + */ +void SPI_ConfigStructInit(SPI_Config_T* spiConfig) +{ + spiConfig->mode = SPI_MODE_SLAVE; + spiConfig->length = SPI_DATA_LENGTH_8B; + spiConfig->phase = SPI_CLKPHA_1EDGE; + spiConfig->polarity = SPI_CLKPOL_HIGH; + spiConfig->slaveSelect = SPI_SSC_DISABLE; + spiConfig->firstBit = SPI_FIRST_BIT_MSB; + spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX; + spiConfig->baudrateDiv = SPI_BAUDRATE_DIV_2; + spiConfig->crcPolynomial = 7; +} + +/*! + * @brief Fills each i2sConfig member with its default value + * + * @param i2sConfig: Pointer to a SPI_Config_T structure which will be initialized + * + * @retval None + */ +void I2S_ConfigStructInit(I2S_Config_T* i2sConfig) +{ + i2sConfig->mode = I2S_MODE_SLAVER_TX; + i2sConfig->standard = I2S_STANDARD_PHILIPS; + i2sConfig->length = I2S_DATA_LENGTH_16B; + i2sConfig->MCLKOutput = I2S_MCLK_OUTPUT_DISABLE; + i2sConfig->audioDiv = I2S_AUDIO_DIV_DEFAULT; + i2sConfig->polarity = I2S_CLKPOL_LOW; +} + +/*! + * @brief Enable the SPI peripheral + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_Enable(SPI_T* spi) +{ + spi->CTRL1_B.SPIEN = BIT_SET; +} + +/*! + * @brief Disable the SPI peripheral + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_Disable(SPI_T* spi) +{ + spi->CTRL1_B.SPIEN = BIT_RESET; +} + +/*! + * @brief Enable the SPI peripheral + * + * @param spi: Select the the SPI peripheral.It can be SPI1 + * + * @retval None + * + * @note Not supported for APM32F030 devices. + */ +void I2S_Enable(SPI_T* spi) +{ + spi->I2SCFG_B.I2SEN = BIT_SET; +} + +/*! + * @brief Disable the SPI peripheral + * + * @param spi: Select the the SPI peripheral.It can be SPI1 + * + * @retval None + * + * @note Not supported for APM32F030 devices. + */ +void I2S_Disable(SPI_T* spi) +{ + spi->I2SCFG_B.I2SEN = BIT_RESET; +} + +/*! + * @brief Enable the frame format mode + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableFrameFormatMode(SPI_T* spi) +{ + spi->CTRL2_B.FRFCFG = BIT_SET; +} + +/*! + * @brief Disable the frame format mode + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableFrameFormatMode(SPI_T* spi) +{ + spi->CTRL2_B.FRFCFG = BIT_RESET; +} + +/*! + * @brief Configures the SPI data length + * + * @param length: specifies the SPI length + * The parameter can be one of following values: + * @arg SPI_DATA_LENGTH_4B: Set data length to 4 bits + * @arg SPI_DATA_LENGTH_5B: Set data length to 5 bits + * @arg SPI_DATA_LENGTH_6B: Set data length to 6 bits + * @arg SPI_DATA_LENGTH_7B: Set data length to 7 bits + * @arg SPI_DATA_LENGTH_8B: Set data length to 8 bits + * @arg SPI_DATA_LENGTH_9B: Set data length to 9 bits + * @arg SPI_DATA_LENGTH_10B: Set data length to 10 bits + * @arg SPI_DATA_LENGTH_11B: Set data length to 11 bits + * @arg SPI_DATA_LENGTH_12B: Set data length to 12 bits + * @arg SPI_DATA_LENGTH_13B: Set data length to 13 bits + * @arg SPI_DATA_LENGTH_14B: Set data length to 14 bits + * @arg SPI_DATA_LENGTH_15B: Set data length to 15 bits + * @arg SPI_DATA_LENGTH_16B: Set data length to 16 bits + * + * @retval None + */ +void SPI_ConfigDatalength(SPI_T* spi, uint8_t length) +{ + spi->CTRL2_B.DSCFG = (uint8_t)length; +} + +/*! + * @brief Configures the FIFO reception threshold + * + * @param threshold: selects the SPI FIFO reception threshold + * The parameter can be one of following values: + * @arg SPI_RXFIFO_HALF: FIFO level is greater than or equal to 1/2 (16-bit) + * @arg SPI_RXFIFO_QUARTER: FIFO level is greater than or equal to 1/4 (8-bit) + * + * @retval None + */ +void SPI_ConfigFIFOThreshold(SPI_T* spi, SPI_RXFIFO_T threshold) +{ + spi->CTRL2_B.FRTCFG = threshold; +} + +/*! + * @brief Enable the data transfer direction + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableOutputDirection(SPI_T* spi) +{ + spi->CTRL1_B.BMOEN = BIT_SET; +} + +/*! + * @brief Disable the data transfer direction + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableOutputDirection(SPI_T* spi) +{ + spi->CTRL1_B.BMOEN = BIT_RESET; +} + +/*! + * @brief Enable internal slave select + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableInternalSlave(SPI_T* spi) +{ + spi->CTRL1_B.ISSEL = BIT_SET; +} + +/*! + * @brief Disable internal slave select + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableInternalSlave(SPI_T* spi) +{ + spi->CTRL1_B.ISSEL = BIT_RESET; +} + +/*! + * @brief Enable the SS output mode + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableSSoutput(SPI_T* spi) +{ + spi->CTRL2_B.SSOEN = BIT_SET; +} + +/*! + * @brief Disable the SS output mode + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableSSoutput(SPI_T* spi) +{ + spi->CTRL2_B.SSOEN = BIT_RESET; +} + +/*! + * @brief Enable the NSS pulse management mode + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableNSSPulse(SPI_T* spi) +{ + spi->CTRL2_B.NSSPEN = BIT_SET; +} + +/*! + * @brief Disable the NSS pulse management mode + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableNSSPulse(SPI_T* spi) +{ + spi->CTRL2_B.NSSPEN = BIT_RESET; +} + +/*! + * @brief Transmits a Data + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @param data: Byte to be transmitted + * + * @retval None + */ +void SPI_I2S_TxData16(SPI_T* spi, uint16_t data) +{ + spi->DATA = (uint16_t)data; +} + +/*! + * @brief Transmits a uint8_t Data + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @param data: Byte to be transmitted + * + * @retval None + */ +void SPI_TxData8(SPI_T* spi, uint8_t data) +{ + *((uint8_t*) & (spi->DATA)) = data; +} + +/*! + * @brief Returns the most recent received data by the SPI peripheral + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @param None + * + * @retval The value of the received data + */ +uint16_t SPI_I2S_RxData16(SPI_T* spi) +{ + return ((uint16_t)spi->DATA); +} + +/*! + * @brief Returns the most recent received data by the SPI peripheral + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @param None + * + * @retval The value of the received data + */ +uint8_t SPI_RxData8(SPI_T* spi) +{ + return *((uint8_t*) & (spi->DATA)); +} + +/*! + * @brief Selects the data transfer direction + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * @param crcLength: selects the SPI transfer direction + * The parameter can be one of following values: + * @arg SPI_CRC_LENGTH_8B: 8-bit CRC length + * @arg SPI_CRC_LENGTH_16B: 16-bit CRC length + * + * @retval None + */ +void SPI_CRCLength(SPI_T* spi, SPI_CRC_LENGTH_T crcLength) +{ + spi->CTRL1_B.CRCLSEL = crcLength; +} + +/*! + * @brief Enable the CRC value calculation + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCEN = BIT_SET; +} + +/*! + * @brief Disable the CRC value calculation + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCEN = BIT_RESET; +} + +/*! + * @brief Transmit CRC value + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_TxCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCNXT = BIT_SET; +} + +/*! + * @brief Returns the receive CRC register value + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + * + * @note None + */ +uint16_t SPI_ReadRxCRC(SPI_T* spi) +{ + return (uint16_t)spi->RXCRC; +} + +/*! + * @brief Returns the transmit CRC register value + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + * + * @note None + */ +uint16_t SPI_ReadTxCRC(SPI_T* spi) +{ + return (uint16_t)spi->TXCRC; +} + +/*! + * @brief Returns the CRC Polynomial register value + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +uint16_t SPI_ReadCRCPolynomial(SPI_T* spi) +{ + return (uint16_t)spi->CRCPOLY; +} + +/*! + * @brief Enable the DMA Rx buffer + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableDMARxBuffer(SPI_T* spi) +{ + spi->CTRL2_B.RXDEN = BIT_SET; +} + +/*! + * @brief Disable the DMA Rx buffer + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableDMARxBuffer(SPI_T* spi) +{ + spi->CTRL2_B.RXDEN = BIT_RESET; +} + +/*! + * @brief Enable the DMA Tx buffer + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_EnableDMATxBuffer(SPI_T* spi) +{ + spi->CTRL2_B.TXDEN = BIT_SET; +} + +/*! + * @brief Disable the DMA Tx buffer + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval None + */ +void SPI_DisableDMATxBuffer(SPI_T* spi) +{ + spi->CTRL2_B.TXDEN = BIT_RESET; +} + +/*! + * @brief Selects the last DMA transfer is type(Even/Odd) + * + * @param crcLength: specifies the SPI last DMA transfers + * The parameter can be one of following values: + * @arg SPI_LAST_DMA_TXRXEVEN: transmission Even reception Even + * @arg SPI_LAST_DMA_TXEVENRXODD: transmission Even reception Odd + * @arg SPI_LAST_DMA_TXODDRXEVEN: transmission Odd reception Even + * @arg SPI_LAST_DMA_TXRXODD: transmission Odd reception Odd + * + * @retval None + */ +void SPI_LastDMATransfer(SPI_T* spi, SPI_LAST_DMA_T lastDMA) +{ + spi->CTRL2 &= 0x9FFF; + spi->CTRL2 |= (uint16_t)lastDMA; +} + +/*! + * @brief Returns the SPI Transmission FIFO filled level + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval Transmission FIFO filled level: + * SPI_TXFIFO_LEVEL_EMPTY: Transmission FIFO filled level is empty + * SPI_TXFIFO_LEVEL_QUARTER: Transmission FIFO filled level is more than quarter + * SPI_TXFIFO_LEVEL_HALF: Transmission FIFO filled level is more than half + * SPI_TXFIFO_LEVEL_FULL: Transmission FIFO filled level is full + */ +uint8_t SPI_ReadTransmissionFIFOLeve(SPI_T* spi) +{ + return (uint8_t)((spi->STS_B.FTLSEL & 0x03)); +} + +/*! + * @brief Returns the SPI Reception FIFO filled level + * + * @param spi: Select the the SPI peripheral.It can be SPI1/SPI2 + * + * @retval Reception FIFO filled level: + * SPI_RXFIFO_LEVEL_EMPTY: Reception FIFO filled level is empty + * SPI_RXFIFO_LEVEL_QUARTER: Reception FIFO filled level is more than quarter + * SPI_RXFIFO_LEVEL_HALF: Reception FIFO filled level is more than half + * SPI_RXFIFO_LEVEL_FULL: Reception FIFO filled level is full + */ +uint8_t SPI_ReadReceptionFIFOLeve(SPI_T* spi) +{ + return (uint8_t)((spi->STS_B.FRLSEL & 0x03)); +} + +/*! + * @brief Enable the SPI interrupts + * + * @param interrupt: Specifies the SPI interrupts sources + * The parameter can be combination of following values: + * @arg SPI_INT_ERRIE: Error interrupt + * @arg SPI_INT_RXBNEIE: Receive buffer not empty interrupt + * @arg SPI_INT_TXBEIE: Transmit buffer empty interrupt + * + * @retval None + */ +void SPI_EnableInterrupt(SPI_T* spi, uint8_t interrupt) +{ + spi->CTRL2 |= (uint8_t)interrupt; +} + +/*! + * @brief Disable the SPI interrupts + * + * @param interrupt: Specifies the SPI interrupts sources + * The parameter can be combination of following values: + * @arg SPI_INT_ERRIE: Error interrupt + * @arg SPI_INT_RXBNEIE: Receive buffer not empty interrupt + * @arg SPI_INT_TXBEIE: Transmit buffer empty interrupt + * + * @retval None + */ +void SPI_DisableInterrupt(SPI_T* spi, uint8_t interrupt) +{ + spi->CTRL2 &= (uint8_t)~interrupt; +} + +/*! + * @brief Checks whether the specified SPI flag is set or not + * + * @param flag: Specifies the flag to check + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXBNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXBE: Transmit buffer empty flag + * @arg I2S_FLAG_CHDIR: Channel direction flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg SPI_FLAG_CRCE: CRC error flag + * @arg SPI_FLAG_MME: Master mode error flag + * @arg SPI_FLAG_OVR: Receive Overrun flag + * @arg SPI_FLAG_BUSY: Busy flag + * @arg SPI_FLAG_FFE: Frame format error flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SPI_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +{ + uint16_t status; + + status = (uint16_t)(spi->STS & flag); + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear the specified SPI flag + * + * @param flag: Specifies the flag to clear + * This parameter can be any combination of the following values: + * @arg SPI_FLAG_CRCE: CRC error flag + + * @retval None + */ +void SPI_ClearStatusFlag(SPI_T* spi, uint8_t flag) +{ + spi->STS &= (uint32_t)~flag; +} + +/*! + * @brief Checks whether the specified interrupt has occurred or not + * + * @param flag: Specifies the SPI interrupt pending bit to check + * This parameter can be one of the following values: + * @arg SPI_INT_FLAG_RXBNE: Receive buffer not empty flag + * @arg SPI_INT_FLAG_TXBE: Transmit buffer empty flag + * @arg SPI_INT_FLAG_UDR: Underrun flag interrupt flag + * @arg SPI_INT_FLAG_MME: Master mode error flag + * @arg SPI_INT_FLAG_OVR: Receive Overrun flag + * @arg SPI_INT_FLAG_FFE: Frame format error interrupt flag + * + * @retval None + */ +uint8_t SPI_ReadIntFlag(SPI_T* spi, SPI_INT_FLAG_T flag) +{ + uint32_t intEnable; + uint32_t intStatus; + + intEnable = (uint32_t)(spi->CTRL2 & (uint32_t)(flag >> 16)); + + intStatus = (uint32_t)(spi->STS & (uint32_t)(flag & 0x1ff)); + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/**@} end of group SPI_Functions*/ +/**@} end of group SPI_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_syscfg.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_syscfg.c new file mode 100644 index 0000000000..d8761379f2 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_syscfg.c @@ -0,0 +1,316 @@ +/*! + * @file apm32f0xx_syscfg.c + * + * @brief This file contains all the functions for the SYSCFG peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_syscfg.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup SYSCFG_Driver SYSCFG Driver + @{ +*/ + +/** @defgroup SYSCFG_Macros Macros + @{ +*/ + +/**@} end of group SYSCFG_Macros */ + +/** @defgroup SYSCFG_Enumerations Enumerations + @{ +*/ + +/**@} end of group SYSCFG_Enumerations */ + +/** @defgroup SYSCFG_Structures Structures + @{ +*/ + +/**@} end of group SYSCFG_Structures */ + +/** @defgroup SYSCFG_Variables Variables + @{ +*/ + +/**@} end of group SYSCFG_Variables */ + +/** @defgroup SYSCFG_Functions Functions + @{ +*/ + +/*! + * @brief Set SYSCFG CFG0/1 EINTCFG1/2/3/4 register to reset value + * + * @param None + * + * @retval None + */ +void SYSCFG_Reset(void) +{ + SYSCFG->CFG1 &= (uint32_t) SYSCFG_CFG1_MEMMODE; + SYSCFG->EINTCFG1 = 0; + SYSCFG->EINTCFG2 = 0; + SYSCFG->EINTCFG3 = 0; + SYSCFG->EINTCFG4 = 0; + SYSCFG->CFG2 |= (uint32_t) SYSCFG_CFG2_SRAMPEF; +} + +/*! + * @brief SYSCFG Memory Remap selects + * + * @param memory: selects the memory remapping + * The parameter can be one of following values: + * @arg SYSCFG_MEMORY_REMAP_FMC: SYSCFG MemoryRemap Flash + * @arg SYSCFG_MEMORY_REMAP_SYSTEM: SYSCFG MemoryRemap SystemMemory + * @arg SYSCFG_MEMORY_REMAP_SRAM: SYSCFG MemoryRemap SRAM + * + * @retval None + */ +void SYSCFG_MemoryRemapSelect(uint8_t memory) +{ + SYSCFG->CFG1_B.MMSEL = (uint8_t)memory; +} + +/*! + * @brief Enables SYSCFG DMA Channel Remap + * + * @param channel: selects the DMA channels remap. + * The parameter can be any combination of following values: + * @arg SYSCFG_DAM_REMAP_ADC: ADC DMA remap + * @arg SYSCFG_DAM_REMAP_USART1TX: USART1 TX DMA remap + * @arg SYSCFG_DAM_REMAP_USART1RX: USART1 RX DMA remap + * @arg SYSCFG_DAM_REMAP_TMR16: Timer 16 DMA remap + * @arg SYSCFG_DAM_REMAP_TMR17: Timer 17 DMA remap + * @arg SYSCFG_DAM_REMAP_TMR16_2 Timer 16 DMA remap2(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR17_2 Timer 17 DMA remap2(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_SPI2 SPI2 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_USART2 USART1 TX DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_USART3 USART1 RX DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_I2C1 I2C1 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR1 Timer 1 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR2 Timer 2 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR3 Timer 3 DMA remap(only for APM32F072) + * + * @retval None + */ +void SYSCFG_EnableDMAChannelRemap(uint32_t channel) +{ + SYSCFG->CFG1 |= (uint32_t)channel; +} + +/*! + * @brief Disables SYSCFG DMA Channel Remap + * + * @param channel: selects the DMA channels remap. + * The parameter can be any combination of following values: + * @arg SYSCFG_DAM_REMAP_ADC: ADC DMA remap + * @arg SYSCFG_DAM_REMAP_USART1TX: USART1 TX DMA remap + * @arg SYSCFG_DAM_REMAP_USART1RX: USART1 RX DMA remap + * @arg SYSCFG_DAM_REMAP_TMR16: Timer 16 DMA remap + * @arg SYSCFG_DAM_REMAP_TMR17: Timer 17 DMA remap + * @arg SYSCFG_DAM_REMAP_TMR16_2 Timer 16 DMA remap2(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR17_2 Timer 17 DMA remap2(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_SPI2 SPI2 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_USART2 USART1 TX DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_USART3 USART1 RX DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_I2C1 I2C1 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR1 Timer 1 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR2 Timer 2 DMA remap(only for APM32F072) + * @arg SYSCFG_DAM_REMAP_TMR3 Timer 3 DMA remap(only for APM32F072) + * + * @retval None + */ +void SYSCFG_DisableDMAChannelRemap(uint32_t channel) +{ + SYSCFG->CFG1 &= (uint32_t)~channel; +} + +/*! + * @brief Enables SYSCFG I2C Fast Mode Plus + * + * @param pin: selects the pin. + * The parameter can be combination of following values: + * @arg SYSCFG_I2C_FMP_PB6: I2C PB6 Fast mode plus + * @arg SYSCFG_I2C_FMP_PB7: I2C PB7 Fast mode plus + * @arg SYSCFG_I2C_FMP_PB8: I2C PB8 Fast mode plus + * @arg SYSCFG_I2C_FMP_PB9: I2C PB9 Fast mode plus + * @arg SYSCFG_I2C_FMP_PA9: I2C PA9 Fast mode plus(only for APM32F030 and APM32F091) + * @arg SYSCFG_I2C_FMP_PA10: I2C PA10 Fast mode plus(only for APM32F030 and APM32F091) + * @arg SYSCFG_I2C_FMP_I2C1: PB10, PB11, PF6 and PF7 + * @arg SYSCFG_I2C_FMP_I2C2: I2C2 Fast mode plus(only for APM32F072 and APM32F091) + * + * @retval None + */ +void SYSCFG_EnableI2CFastModePlus(uint32_t pin) +{ + SYSCFG->CFG1 |= (uint32_t)pin; +} + +/*! + * @brief Disables SYSCFG I2C Fast Mode Plus + * + * @param pin: selects the pin. + * The parameter can be combination of following values: + * @arg SYSCFG_I2C_FMP_PB6: I2C PB6 Fast mode plus + * @arg SYSCFG_I2C_FMP_PB7: I2C PB7 Fast mode plus + * @arg SYSCFG_I2C_FMP_PB8: I2C PB8 Fast mode plus + * @arg SYSCFG_I2C_FMP_PB9: I2C PB9 Fast mode plus + * @arg SYSCFG_I2C_FMP_PA9: I2C PA9 Fast mode plus(only for APM32F030 and APM32F091) + * @arg SYSCFG_I2C_FMP_PA10: I2C PA10 Fast mode plus(only for APM32F030 and APM32F091) + * @arg SYSCFG_I2C_FMP_I2C1: PB10, PB11, PF6 and PF7 + * @arg SYSCFG_I2C_FMP_I2C2: I2C2 Fast mode plus(only for APM32F072 and APM32F091) + * + * @retval None + */ +void SYSCFG_DisableI2CFastModePlus(uint32_t pin) +{ + SYSCFG->CFG1 &= (uint32_t)~pin; +} + +/*! + * @brief Select the modulation envelope source + * + * @param IRDAEnv: selects the envelope source + * The parameter can be one of following values: + * @arg SYSCFG_IRDA_ENV_TMR16: Timer16 as IRDA Modulation envelope source + * @arg SYSCFG_IRDA_ENV_USART1: USART1 as IRDA Modulation envelope source + * @arg SYSCFG_IRDA_ENV_USART2: USART4 as IRDA Modulation envelope source + * + * @retval None + * + * @note It's only for APM32F091 devices. + */ +void SYSCFG_SelectIRDAEnv(SYSCFG_IRDA_ENV_T IRDAEnv) +{ + SYSCFG->CFG1 &= ~(0x000000C0); + SYSCFG->CFG1 |= (IRDAEnv); +} + +/*! + * @brief Selects the GPIO pin used as EINT Line. + * + * @param port: selects the port can be GPIOA/B/C/D/E/F + * + * @param pin: selects the pin can be SYSCFG_PIN_(0..15) + * + * @retval None + * + * @note GPIOE only for APM32F072 and APM32F091 + */ + +void SYSCFG_EINTLine(SYSCFG_PORT_T port, SYSCFG_PIN_T pin) +{ + uint32_t status; + + status = (((uint32_t)0x0F) & port) << (0x04 * (pin & (uint8_t)0x03)); + + if (pin <= 0x03) + { + SYSCFG->EINTCFG1 |= status; + } + else if ((0x04 <= pin) & (pin <= 0x07)) + { + SYSCFG->EINTCFG2 |= status; + } + else if ((0x08 <= pin) & (pin <= 0x0B)) + { + SYSCFG->EINTCFG3 |= status; + } + else if ((0x0C <= pin) & (pin <= 0x0F)) + { + SYSCFG->EINTCFG4 |= status; + } +} + +/*! + * @brief Selected parameter to the break input of TMR1. + * + * @param lock: selects the configuration to break + * The parameter can be one of following values: + * @arg SYSCFG_LOCK_LOCKUP: Cortex-M0 LOCKUP bit + * @arg SYSCFG_LOCK_SRAM: SRAM parity lock bit + * @arg SYSCFG_LOCK_PVD: PVD lock enable bit + * + * @retval None + */ +void SYSCFG_BreakLock(uint32_t lock) +{ + SYSCFG->CFG2_B.LOCK = 0; + SYSCFG->CFG2_B.SRAMLOCK = 0; + SYSCFG->CFG2_B.PVDLOCK = 0; + + if (lock == SYSCFG_LOCK_LOCKUP) + { + SYSCFG->CFG2_B.LOCK = BIT_SET; + } + if (lock == SYSCFG_LOCK_SRAM) + { + SYSCFG->CFG2_B.SRAMLOCK = BIT_SET; + } + if (lock == SYSCFG_LOCK_PVD) + { + SYSCFG->CFG2_B.PVDLOCK = BIT_SET; + } +} + +/*! + * @brief Read the specified SYSCFG flag + * + * @param flag: SRAM Parity error flag + * @arg SYSCFG_CFG2_SRAMPEF + * + * @retval None + */ +uint8_t SYSCFG_ReadStatusFlag(uint32_t flag) +{ + uint32_t status; + + status = (uint32_t)(SYSCFG->CFG2 & flag); + + if (status == flag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear the specified SYSCFG flag + * + * @param flag: SRAM Parity error flag + * @arg SYSCFG_CFG2_SRAMPEF + * + * @retval None + */ +void SYSCFG_ClearStatusFlag(uint8_t flag) +{ + SYSCFG->CFG2 |= (uint32_t) flag; +} + +/**@} end of group SYSCFG_Functions*/ +/**@} end of group SYSCFG_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_tmr.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_tmr.c new file mode 100644 index 0000000000..9f4dea8e07 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_tmr.c @@ -0,0 +1,2394 @@ +/*! + * @file apm32f0xx_tmr.c + * + * @brief This file contains all the functions for the TMR peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_tmr.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup TMR_Driver TMR Driver + @{ +*/ + +/** @defgroup TMR_Marcos Marcos + @{ + */ + +/**@} end of group TMR_Marcos */ + +/** @defgroup TMR_Enumerations Enumerations + @{ + */ + +/**@} end of group TMR_Enumerations */ + +/** @defgroup TMR_Structures Structures + @{ + */ + +/**@} end of group TMR_Structures */ + +/** @defgroup TMR_Variables Variables + @{ + */ + +/**@} end of group TMR_Variables */ + +/** @defgroup TMR_Functions Functions + @{ +*/ + +/*! + * @brief Reset the TMR peripheral registers to their default reset values + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 TMR15 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_Reset(TMR_T* TMRx) +{ + if (TMRx == TMR1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); + } + else if (TMRx == TMR2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); + } + else if (TMRx == TMR3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); + } + else if (TMRx == TMR6) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); + } + else if (TMRx == TMR7) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); + } + else if (TMRx == TMR14) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR14); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR14); + } + else if (TMRx == TMR15) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR15); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR15); + } + else if (TMRx == TMR16) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR16); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR16); + } + else if (TMRx == TMR17) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR17); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR17); + } +} + +/*! + * @brief Initializes the TMRx Time Base Unit peripheral according to + * the specified parameters in the TMR_ConfigTimeBase + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param timeBaseConfig: pointer to a TMR_TimeBase_T structure that contains + * the configuration information for the specified TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_ConfigTimeBase(TMR_T* TMRx, TMR_TimeBase_T* timeBaseConfig) +{ + if ((TMRx == TMR1) || (TMRx == TMR3)) + { + /** Select the Counter Mode */ + TMRx->CTRL1_B.CNTDIR = timeBaseConfig->counterMode; + TMRx->CTRL1_B.CAMSEL = (timeBaseConfig->counterMode) >> 1; + } + + if (TMRx != TMR6) + { + /** Set the clock division */ + TMRx->CTRL1_B.CLKDIV = timeBaseConfig->clockDivision; + } + + /** Set the Autoreload value */ + TMRx->AUTORLD = timeBaseConfig->period ; + + /** Set the Prescaler value */ + TMRx->PSC = timeBaseConfig->div ; + + if ((TMRx == TMR1) || (TMRx == TMR15) || (TMRx == TMR16) || (TMRx == TMR17)) + { + /** Set the Repetition Counter value */ + TMRx->REPCNT = timeBaseConfig->repetitionCounter; + } + + /** Enable Update generation */ + TMRx->CEG_B.UEG = BIT_SET; +} + +/*! + * @brief Fills each TMR_ConfigTimeBaseStruct member with its default value + * + * @param timeBaseConfig: pointer to a TMR_TimeBase_T structure that contains + * the configuration information for the specified TMR peripheral + * + * @retval None + */ +void TMR_ConfigTimeBaseStruct(TMR_TimeBase_T* timeBaseConfig) +{ + timeBaseConfig->period = 0xFFFFFFFF; + timeBaseConfig->div = 0x0000; + timeBaseConfig->clockDivision = TMR_CKD_DIV1; + timeBaseConfig->counterMode = TMR_COUNTER_MODE_UP; + timeBaseConfig->repetitionCounter = 0x0000; +} + +/*! + * @brief Configures the TMRx Div + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param div: specifies the Div Register value + * + * @param mode: specifies the TMR Prescaler Reload mode + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_ConfigDIV(TMR_T* TMRx, uint16_t div, TMR_PRESCALER_RELOAD_T mode) +{ + TMRx->PSC = div; + TMRx->CEG_B.UEG = mode; +} + +/*! + * @brief Specifies the TMRx Counter Mode to be used + * + * @param TMRx: x can be can be 1 or 3 to select Timer + * + * @param mode : specifies the Counter Mode to be used + * + * @retval None + */ +void TMR_ConfigCounterMode(TMR_T* TMRx, TMR_COUNTER_MODE_T mode) +{ + TMRx->CTRL1_B.CNTDIR = mode; + TMRx->CTRL1_B.CAMSEL = (mode) >> 1; +} + +/*! + * @brief Sets the TMRx Counter Register value + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param counter: specifies the Counter register new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_SetCounter(TMR_T* TMRx, uint32_t counter) +{ + TMRx->CNT = counter; +} + +/*! + * @brief Read the TMRx Counter value + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval Counter Register value + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +uint32_t TMR_ReadCounter(TMR_T* TMRx) +{ + return (uint32_t)TMRx->CNT; +} + +/*! + * @brief Sets the AutoReload Register value + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param autoReload: autoReload register new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_SetAutoReload(TMR_T* TMRx, uint32_t autoReload) +{ + TMRx->AUTORLD = autoReload; +} + +/*! + * @brief Read the TMRx Div value + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval Div Register value + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +uint32_t TMR_ReadDiv(TMR_T* TMRx) +{ + return (uint32_t)TMRx->PSC; +} + +/*! + * @brief Enable the No update event + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_EnableNGUpdate(TMR_T* TMRx) +{ + TMRx->CTRL1_B.UD = ENABLE; +} + +/*! + * @brief Enable the No update event + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_DisableNGUpdate(TMR_T* TMRx) +{ + TMRx->CTRL1_B.UD = DISABLE; +} + +/*! + * @brief Configures the Update Request Interrupt source. + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param source: Config the Update source + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_ConfigUPdateRequest(TMR_T* TMRx, TMR_UPDATE_SOURCE_T source) +{ + if (source != TMR_UPDATE_SOURCE_GLOBAL) + { + TMRx->CTRL1_B.URSSEL = BIT_SET; + } + else + { + TMRx->CTRL1_B.URSSEL = BIT_RESET; + } +} + +/*! + * @brief Enables peripheral Preload register on AUTORLD + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_EnableAUTOReload(TMR_T* TMRx) +{ + TMRx->CTRL1_B.ARPEN = ENABLE; +} + +/*! + * @brief Disable peripheral Preload register on AUTORLD + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_DisableAUTOReload(TMR_T* TMRx) +{ + TMRx->CTRL1_B.ARPEN = DISABLE; +} + +/*! + * @brief Selects the One Pulse Mode + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param OPMode:Config OP Mode to be used + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_SelectOnePulseMode(TMR_T* TMRx, TMR_OPMODE_T OPMode) +{ + TMRx->CTRL1_B.SPMEN = OPMode; +} + +/*! + * @brief Sets the Clock Division value + * + * @param TMRx: x can be can be 123, 14, 15, 16 and 17 to select Timer + * + * @param clockDivision: clock division value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_SetClockDivision(TMR_T* TMRx, TMR_CKD_T clockDivision) +{ + TMRx->CTRL1_B.CLKDIV = clockDivision; +} + +/*! + * @brief Enable the specified TMR peripheral + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_Enable(TMR_T* TMRx) +{ + TMRx->CTRL1_B.CNTEN = ENABLE; +} + +/*! + * @brief Disable the specified TMR peripheral + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_Disable(TMR_T* TMRx) +{ + TMRx->CTRL1_B.CNTEN = DISABLE; +} + +/*! + * @brief Configures the: Break feature, dead time, Lock level, the OSSI + * + * @param TMRx: x can be can be 1, 15, 16 and 17 to select Timer + * + * @param structure: pointer to a TMR_BDTInit_T structure that contains + * the BDT Register configuration information for the TMR peripheral + * + * @retval None + */ +void TMR_ConfigBDT(TMR_T* TMRx, TMR_BDTInit_T* structure) +{ + TMRx->BDT = (uint32_t)(((uint32_t)structure->automaticOutput) << 14) | + (((uint32_t)structure->breakPolarity) << 13) | + (((uint32_t)structure->breakState) << 12) | + (((uint32_t)structure->RMOS_State) << 11) | + (((uint32_t)structure->IMOS_State) << 10) | + (((uint32_t)structure->lockLevel) << 8) | + ((uint32_t)structure->deadTime); +} + +/*! + * @brief Initialize the BDT timer with its default value. + * + * @param structure: pointer to a TMR_BDTInit_T structure that contains + * the BDT Register configuration information for the TMR peripheral + * + * @retval None + */ +void TMR_ConfigBDTStructInit(TMR_BDTInit_T* structure) +{ + structure->RMOS_State = TMR_RMOS_STATE_DISABLE; + structure->IMOS_State = TMR_IMOS_STATE_DISABLE; + structure->lockLevel = TMR_LOCK_LEVEL_OFF; + structure->deadTime = 0x00; + structure->breakState = TMR_BREAK_STATE_DISABLE; + structure->breakPolarity = TMR_BREAK_POLARITY_LOW; + structure->automaticOutput = TMR_AUTOMATIC_OUTPUT_DISABLE; +} + +/*! + * @brief Enable TMRx PWM output. + * + * @param TMRx: x can be can be 1, 15, 16 and 17 to select Timer + * + * @retval None + */ +void TMR_EnablePWMOutputs(TMR_T* TMRx) +{ + TMRx->BDT_B.MOEN = ENABLE; +} + +/*! + * @brief Disable TMRx PWM output. + * + * @param TMRx: x can be can be 1, 15, 16 and 17 to select Timer + * + * @retval None + */ +void TMR_DisablePWMOutputs(TMR_T* TMRx) +{ + TMRx->BDT_B.MOEN = DISABLE; +} + +/*! + * @brief Configure channel 1 according to parameters + * + * @param TMRx: x can be can be 1, 2, 3, 14, 15, 16 and 17 to select Timer + * + * @param OCcongigStruct: Channel configuration structure + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC1Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct) +{ + + /** Disable the Channel 1: Reset the CC1EN Bit */ + TMRx->CCEN_B.CC1EN = BIT_RESET; + + /** Reset and Select the Output Compare Mode Bits */ + TMRx->CCM1_OUTPUT_B.CC1SEL = BIT_RESET; + TMRx->CCM1_OUTPUT_B.OC1MOD = OCcongigStruct->OC_Mode; + + /** Reset and Set the Output Polarity level */ + TMRx->CCEN_B.CC1POL = OCcongigStruct->OC_Polarity; + + /** Set the Output State */ + TMRx->CCEN_B.CC1EN = OCcongigStruct->OC_OutputState; + + if ((TMRx == TMR1) || (TMRx == TMR15) || (TMRx == TMR16) + || (TMRx == TMR17)) + { + /** Reset and Set the Output N Polarity level */ + TMRx->CCEN_B.CC1NPOL = OCcongigStruct->OC_NPolarity; + + /** Reset and Set the Output N State */ + TMRx->CCEN_B.CC1NEN = OCcongigStruct->OC_OutputNState; + + /** Reset the Output Compare and Output Compare N IDLE State */ + TMRx->CTRL2_B.OC1OIS = BIT_RESET; + TMRx->CTRL2_B.OC1NOIS = BIT_RESET; + + /** Set the Output Idle state */ + TMRx->CTRL2_B.OC1OIS = OCcongigStruct->OC_Idlestate; + /** Set the Output N State */ + TMRx->CTRL2_B.OC1NOIS = OCcongigStruct->OC_NIdlestate; + } + + /** Set the Capture Compare Register value */ + TMRx->CC1 = OCcongigStruct->Pulse; +} + +/*! + * @brief Configure channel 2 according to parameters + * + * @param TMRx: x can be can be 123 and 15 to select Timer + * + * @param OCcongigStruct: Channel configuration structure + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC2Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct) +{ + + /** Disable the Channel 2: Reset the CC2EN Bit */ + TMRx->CCEN_B.CC2EN = BIT_RESET; + + /** Reset and Select the Output Compare Mode Bits */ + TMRx->CCM1_OUTPUT_B.CC2SEL = BIT_RESET; + TMRx->CCM1_OUTPUT_B.OC2MOD = OCcongigStruct->OC_Mode; + + /** Reset and Set the Output Polarity level */ + TMRx->CCEN_B.CC2POL = BIT_RESET; + TMRx->CCEN_B.CC2POL = OCcongigStruct->OC_Polarity; + + /** Set the Output State */ + TMRx->CCEN_B.CC2EN = OCcongigStruct->OC_OutputState; + + if (TMRx == TMR1) + { + /** Reset and Set the Output N Polarity level */ + TMRx->CCEN_B.CC2NPOL = BIT_RESET; + TMRx->CCEN_B.CC2NPOL = OCcongigStruct->OC_NPolarity; + + /** Reset and Set the Output N State */ + TMRx->CCEN_B.CC2NEN = BIT_RESET; + TMRx->CCEN_B.CC2NEN = OCcongigStruct->OC_OutputNState; + + /** Reset the Output Compare and Output Compare N IDLE State */ + TMRx->CTRL2_B.OC2OIS = BIT_RESET; + TMRx->CTRL2_B.OC2NOIS = BIT_RESET; + + /** Set the Output Idle state */ + TMRx->CTRL2_B.OC2OIS = OCcongigStruct->OC_Idlestate; + /** Set the Output N State */ + TMRx->CTRL2_B.OC2NOIS = OCcongigStruct->OC_NIdlestate; + } + + /** Set the Capture Compare Register value */ + TMRx->CC2 = OCcongigStruct->Pulse; +} + +/*! + * @brief Configure channel 3 according to parameters + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param OCcongigStruct: Channel configuration structure + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC3Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct) +{ + + /** Disable the Channel 3: Reset the CC3EN Bit */ + TMRx->CCEN_B.CC3EN = BIT_RESET; + + /** Reset and Select the Output Compare Mode Bits */ + TMRx->CCM2_OUTPUT_B.CC3SEL = BIT_RESET; + TMRx->CCM2_OUTPUT_B.OC3MOD = OCcongigStruct->OC_Mode; + + /** Reset and Set the Output Polarity level */ + TMRx->CCEN_B.CC3POL = BIT_RESET; + TMRx->CCEN_B.CC3POL = OCcongigStruct->OC_Polarity; + + /** Set the Output State */ + TMRx->CCEN_B.CC3EN = OCcongigStruct->OC_OutputState; + + if (TMRx == TMR1) + { + /** Reset and Set the Output N Polarity level */ + TMRx->CCEN_B.CC3NPOL = BIT_RESET; + TMRx->CCEN_B.CC3NPOL = OCcongigStruct->OC_NPolarity; + + /** Reset and Set the Output N State */ + TMRx->CCEN_B.CC3NEN = BIT_RESET; + TMRx->CCEN_B.CC3NEN = OCcongigStruct->OC_OutputNState; + + /** Reset the Output Compare and Output Compare N IDLE State */ + TMRx->CTRL2_B.OC3OIS = BIT_RESET; + TMRx->CTRL2_B.OC3NOIS = BIT_RESET; + + /** Set the Output Idle state */ + TMRx->CTRL2_B.OC3OIS = OCcongigStruct->OC_Idlestate; + /** Set the Output N State */ + TMRx->CTRL2_B.OC3NOIS = OCcongigStruct->OC_NIdlestate; + } + + /** Set the Capture Compare Register value */ + TMRx->CC3 = OCcongigStruct->Pulse; +} + +/*! + * @brief Configure channel 4 according to parameters + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param OCcongigStruct: Channel configuration structure + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC4Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct) +{ + + /** Disable the Channel 4: Reset the CC4EN Bit */ + TMRx->CCEN_B.CC4EN = BIT_RESET; + + /** Reset and Select the Output Compare Mode Bits */ + TMRx->CCM2_OUTPUT_B.CC4SEL = BIT_RESET; + TMRx->CCM2_OUTPUT_B.OC4MOD = OCcongigStruct->OC_Mode; + + /** Reset and Set the Output Polarity level */ + TMRx->CCEN_B.CC4POL = BIT_RESET; + TMRx->CCEN_B.CC4POL = OCcongigStruct->OC_Polarity; + + /** Set the Output State */ + TMRx->CCEN_B.CC4EN = OCcongigStruct->OC_OutputState; + + if (TMRx == TMR1) + { + /** Reset the Output Compare and Output Compare IDLE State */ + TMRx->CTRL2_B.OC4OIS = BIT_RESET; + + /** Set the Output Idle state */ + TMRx->CTRL2_B.OC4OIS = OCcongigStruct->OC_Idlestate; + } + + /** Set the Capture Compare Register value */ + TMRx->CC4 = OCcongigStruct->Pulse; +} + +/*! + * @brief Initialize the OC timer with its default value. + * + * @param OCcongigStruct: Channel configuration structure + * + * @retval None + */ +void TMR_OCConfigStructInit(TMR_OCConfig_T* OCcongigStruct) +{ + /** Set the default configuration */ + OCcongigStruct->OC_Mode = TMR_OC_MODE_TMRING; + OCcongigStruct->OC_OutputState = TMR_OUTPUT_STATE_DISABLE; + OCcongigStruct->OC_OutputNState = TMR_OUTPUT_NSTATE_DISABLE; + OCcongigStruct->Pulse = 0x0000; + OCcongigStruct->OC_Polarity = TMR_OC_POLARITY_HIGH; + OCcongigStruct->OC_NPolarity = TMR_OC_NPOLARITY_HIGH; + OCcongigStruct->OC_Idlestate = TMR_OCIDLESTATE_RESET; + OCcongigStruct->OC_NIdlestate = TMR_OCNIDLESTATE_RESET; +} + +/*! + * @brief Selects the Output Compare Mode. + * + * @param TMRx: x can be can be 123, 14, 15, 16 and 17 to select Timer + * + * @param channel: specifies the TMR Channel + * This parameter can be one of the following values: + * @arg TMR_CHANNEL_1 + * @arg TMR_CHANNEL_2 + * @arg TMR_CHANNEL_3 + * @arg TMR_CHANNEL_4 + * + * @param OCMode: specifies the TMR Output Compare Mode + * This parameter can be one of the following values: + * @arg TMR_OC_MODE_TMRING + * @arg TMR_OC_MODE_ACTIVE + * @arg TMR_OC_MODE_INACTIVE + * @arg TMR_OC_MODE_LOWLEVEL + * @arg TMR_OC_MODE_HIGHLEVEL + * @arg TMR_OC_MODE_PWM1 + * @arg TMR_OC_MODE_PWM2 + + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SelectOCxMode(TMR_T* TMRx, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) +{ + TMRx->CCEN &= BIT_RESET << channel; + + if (channel == TMR_CHANNEL_1) + { + TMRx->CCM1_OUTPUT_B.OC1MOD = mode; + } + else if (channel == TMR_CHANNEL_2) + { + TMRx->CCM1_OUTPUT_B.OC2MOD = mode; + } + else if (channel == TMR_CHANNEL_3) + { + TMRx->CCM2_OUTPUT_B.OC3MOD = mode; + } + else if (channel == TMR_CHANNEL_4) + { + TMRx->CCM2_OUTPUT_B.OC4MOD = mode; + } +} + +/*! + * @brief Sets the Capture Compare1 Register value + * + * @param TMRx: x can be can be 123, 14, 15, 16 and 17 to select Timer + * + * @param compare: specifies the Capture Compare1 register new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetCompare1(TMR_T* TMRx, uint32_t compare) +{ + TMRx->CC1 = compare; +} + +/*! + * @brief Sets the Capture Compare2 Register value + * + * @param TMRx: x can be can be 123 and 15 to select Timer + * + * @param compare: specifies the Capture Compare1 register new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetCompare2(TMR_T* TMRx, uint32_t compare) +{ + TMRx->CC2 = compare; +} + +/*! + * @brief Sets the Capture Compare3 Register value + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param compare: specifies the Capture Compare1 register new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetCompare3(TMR_T* TMRx, uint32_t compare) +{ + TMRx->CC3 = compare; +} + +/*! + * @brief Sets the Capture Compare4 Register value + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param compare: specifies the Capture Compare1 register new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetCompare4(TMR_T* TMRx, uint32_t compare) +{ + TMRx->CC4 = compare; +} + +/*! + * @brief Forces the output 1 waveform to active or inactive level + * + * @param TMRx: x can be can be 123, 14, 15, 16 and 17 to select Timer + * + * @param action: forced Action to be set to the output waveform + * This parameter can be one of the following values: + * @arg TMR_FORCEDACTION_INACTIVE + * @arg TMR_FORCEDACTION_ACTIVE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ForcedOC1Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action) +{ + TMRx->CCM1_OUTPUT_B.OC1MOD = action; +} + +/*! + * @brief Forces the output 2 waveform to active or inactive level + * + * @param TMRx: x can be can be 123 and 15 to select Timer + * + * @param action: forced Action to be set to the output waveform + * This parameter can be one of the following values: + * @arg TMR_FORCEDACTION_INACTIVE + * @arg TMR_FORCEDACTION_ACTIVE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ForcedOC2Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action) +{ + TMRx->CCM1_OUTPUT_B.OC2MOD = action; +} + +/*! + * @brief Forces the output 3 waveform to active or inactive level + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param action: forced Action to be set to the output waveform + * This parameter can be one of the following values: + * @arg TMR_FORCEDACTION_INACTIVE + * @arg TMR_FORCEDACTION_ACTIVE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ForcedOC3Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action) +{ + TMRx->CCM2_OUTPUT_B.OC3MOD = action; +} + +/*! + * @brief Forces the output 4 waveform to active or inactive level + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param action: forced Action to be set to the output waveform + * This parameter can be one of the following values: + * @arg TMR_FORCEDACTION_INACTIVE + * @arg TMR_FORCEDACTION_ACTIVE + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ForcedOC4Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action) +{ + TMRx->CCM2_OUTPUT_B.OC4MOD = action; +} + +/*! + * @brief Sets Capture Compare Preload Control bit + * + * @param TMRx: x can be can be 123 and 15 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_EnableCCPreload(TMR_T* TMRx) +{ + TMRx->CTRL2_B.CCPEN = ENABLE; +} + +/*! + * @brief Resets Capture Compare Preload Control bit + * + * @param TMRx: x can be can be 123 and 15 to select Timer + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_DisableCCPreload(TMR_T* TMRx) +{ + TMRx->CTRL2_B.CCPEN = DISABLE; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CC1 + * + * @param TMRx: x can be can be 1, 2, 3 ,14, 15, 16 and 17 to select Timer + * + * @param OCPreload: new state of the TMRx peripheral Preload register + * This parameter can be one of the following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC1PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload) +{ + TMRx->CCM1_OUTPUT_B.OC1PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CC2 + * + * @param TMRx: x can be can be 1, 2, 3 and 15 to select Timer + * + * @param OCPreload: new state of the TMRx peripheral Preload register + * This parameter can be one of the following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC2PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload) +{ + TMRx->CCM1_OUTPUT_B.OC2PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CC3 + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param OCPreload: new state of the TMRx peripheral Preload register + * This parameter can be one of the following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC3PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload) +{ + TMRx->CCM2_OUTPUT_B.OC3PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CC4 + * + * @param TMRx: x can be can be 1, 2, 3 to select Timer + * + * @param OCPreload: new state of the TMRx peripheral Preload register + * This parameter can be one of the following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC4PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload) +{ + TMRx->CCM2_OUTPUT_B.OC4PEN = OCPreload; +} + +/*! + * @brief Configures the Output Compare 1 Fast feature + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param OCFast: new state of the Output Compare Fast Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCFAST_DISABLE + * @arg TMR_OCFAST_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ + +void TMR_OC1FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast) +{ + TMRx->CCM1_OUTPUT_B.OC1FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 2 Fast feature + * + * @param TMRx: where x can be 1, 2, 3 and 15 to select the TMR peripheral + * + * @param OCFast: new state of the Output Compare Fast Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCFAST_DISABLE + * @arg TMR_OCFAST_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC2FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast) +{ + TMRx->CCM1_OUTPUT_B.OC2FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 3 Fast feature + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param OCFast: new state of the Output Compare Fast Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCFAST_DISABLE + * @arg TMR_OCFAST_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC3FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast) +{ + TMRx->CCM2_OUTPUT_B.OC3FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 4 Fast feature + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param OCFast: new state of the Output Compare Fast Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCFAST_DISABLE + * @arg TMR_OCFAST_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC4FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast) +{ + TMRx->CCM2_OUTPUT_B.OC4FEN = OCFast; +} + +/*! + * @brief Clears or safeguards the OCREF1 signal on an external event + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param OCCler: new state of the Output Compare Clear Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCCLER_DISABLE + * @arg TMR_OCCLER_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ClearOC1Ref(TMR_T* TMRx, TMR_OCCLER_T OCCler) +{ + TMRx->CCM1_OUTPUT_B.OC1CEN = OCCler; +} + +/*! + * @brief Clears or safeguards the OCREF2 signal on an external event + * + * @param TMRx: where x can be 1, 2, 3 and 15 to select the TMR peripheral + * + * @param OCCler: new state of the Output Compare Clear Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCCLER_DISABLE + * @arg TMR_OCCLER_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ClearOC2Ref(TMR_T* TMRx, TMR_OCCLER_T OCCler) +{ + TMRx->CCM1_OUTPUT_B.OC2CEN = OCCler; +} + +/*! + * @brief Clears or safeguards the OCREF3 signal on an external event + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param OCCler: new state of the Output Compare Clear Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCCLER_DISABLE + * @arg TMR_OCCLER_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ClearOC3Ref(TMR_T* TMRx, TMR_OCCLER_T OCCler) +{ + TMRx->CCM2_OUTPUT_B.OC3CEN = OCCler; +} + +/*! + * @brief Clears or safeguards the OCREF4 signal on an external event + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param OCCler: new state of the Output Compare Clear Enable Bit + * This parameter can be one of the following values: + * @arg TMR_OCCLER_DISABLE + * @arg TMR_OCCLER_ENABLE + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ClearOC4Ref(TMR_T* TMRx, TMR_OCCLER_T OCCler) +{ + TMRx->CCM2_OUTPUT_B.OC4CEN = OCCler; +} + +/*! + * @brief Configures the channel 1 polarity + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TMR_OC_POLARITY_HIGH + * @arg TMR_OC_POLARITY_LOW + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC1PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity) +{ + TMRx->CCEN_B.CC1POL = OCPolarity; +} + +/*! + * @brief Configures the channel 1N polarity + * + * @param TMRx: where x can be 1, 15, 16 and 17 to select the TMR peripheral + * + * @param OCNPolarity: specifies the OC1 NPolarity + * This parameter can be one of the following values: + * @arg TMR_OC_NPOLARITY_HIGH + * @arg TMR_OC_NPOLARITY_LOW + * @retval None + */ +void TMR_OC1NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity) +{ + TMRx->CCEN_B.CC1NPOL = OCNPolarity; +} + +/*! + * @brief Configures the channel 2 polarity + * + * @param TMRx: where x can be 1, 2, 3 and 15 to select the TMR peripheral + * + * @param OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TMR_OC_POLARITY_HIGH + * @arg TMR_OC_POLARITY_LOW + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC2PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity) +{ + TMRx->CCEN_B.CC2POL = OCPolarity; +} + +/*! + * @brief Configures the channel 2N polarity + * + * @param TMRx: where x can be 1 to select the TMR peripheral + * + * @param OCNPolarity: specifies the OC2 NPolarity + * This parameter can be one of the following values: + * @arg TMR_OC_NPOLARITY_HIGH + * @arg TMR_OC_NPOLARITY_LOW + * @retval None + */ +void TMR_OC2NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity) +{ + TMRx->CCEN_B.CC2NPOL = OCNPolarity; +} + +/*! + * @brief Configures the channel 3 polarity + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TMR_OC_POLARITY_HIGH + * @arg TMR_OC_POLARITY_LOW + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC3PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity) +{ + TMRx->CCEN_B.CC3POL = OCPolarity; +} + +/*! + * @brief Configures the channel 3N polarity + * + * @param TMRx: where x can be 1 to select the TMR peripheral + * + * @param OCNPolarity: specifies the OC3 NPolarity + * This parameter can be one of the following values: + * @arg TMR_OC_NPOLARITY_HIGH + * @arg TMR_OC_NPOLARITY_LOW + * @retval None + */ +void TMR_OC3NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity) +{ + TMRx->CCEN_B.CC3NPOL = OCNPolarity; +} + +/*! + * @brief Configures the channel 4 polarity + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TMR_OC_POLARITY_HIGH + * @arg TMR_OC_POLARITY_LOW + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_OC4PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity) +{ + TMRx->CCEN_B.CC4POL = OCPolarity; +} + +/*! + * @brief Selects the OCReference Clear source + * + * @param TMRx: x can be 1, 2, 3 to select Timer. + * + * @param OCReferenceClear: specifies the OCReference Clear source + * This parameter can be one of the following values: + * @arg TMR_OCCS_ETRF + * @arg TMR_OCCS_OCREFCLR + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SelectOCREFClear(TMR_T* TMRx, TMR_OCCSEL_T OCReferenceClear) +{ + TMRx->SMCTRL_B.OCCSEL = OCReferenceClear; +} + +/*! + * @brief Enables the Capture Compare Channel x + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param channel: TMR channel + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_EnableCCxChannel(TMR_T* TMRx, TMR_CHANNEL_T channel) +{ + TMRx->CCEN |= BIT_SET << channel; +} + +/*! + * @brief Disables the Capture Compare Channel x + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param channel: TMR channel + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_DisableCCxChannel(TMR_T* TMRx, TMR_CHANNEL_T channel) +{ + TMRx->CCEN &= ~(BIT_SET << channel); +} + +/*! + * @brief Enables the Capture Compare Channel xN. + * + * @param TMRx: where x can be 1, 15, 16 and 17 to select the TMR peripheral + * + * @param channel: TMR channel + * + * @retval None + */ +void TMR_EnableCCxNChannel(TMR_T* TMRx, TMR_CHANNEL_T channel) +{ + TMRx->CCEN |= 0x04 << channel; +} + +/*! + * @brief Disables the Capture Compare Channel xN + * + * @param TMRx: where x can be 1, 15, 16 and 17 to select the TMR peripheral + * + * @param channel: TMR channel + * + * @retval None + */ +void TMR_DisableCCxNChannel(TMR_T* TMRx, TMR_CHANNEL_T channel) +{ + TMRx->CCEN &= ~(0x04 << channel); +} + +/*! + * @brief Enable Selects the TMR peripheral Commutation event + * + * @param TMRx: where x can be 1, 15, 16 and 17 to select the TMR peripheral + * + * @retval None + */ + +void TMR_EnableSelectCOM(TMR_T* TMRx) +{ + TMRx->CTRL2_B.CCUSEL = ENABLE; +} +/*! + * @brief Disable Selects the TMR peripheral Commutation event + * + * @param TMRx: where x can be 1, 15, 16 and 17 to select the TMR peripheral + * + * @retval None + */ +void TMR_DisableSelectCOM(TMR_T* TMRx) +{ + TMRx->CTRL2_B.CCUSEL = DISABLE; +} + +/*! + * @brief Configure the TI1 as Input. + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param ICpolarity: The Input Polarity. + * + * @param ICselection: specifies the input to be used. + * + * @param ICfilter: Specifies the Input Capture Filter + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +static void TI1Config(TMR_T* TMRx, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + /** Disable the Channel 1: Reset the CC1EN Bit */ + TMRx->CCEN_B.CC1EN = BIT_RESET; + + /** Select the Input and set the filter */ + TMRx->CCM1_INPUT_B.CC1SEL = BIT_RESET; + TMRx->CCM1_INPUT_B.IC1F = BIT_RESET; + TMRx->CCM1_INPUT_B.CC1SEL = ICselection; + TMRx->CCM1_INPUT_B.IC1F = ICfilter; + + /** Select the Polarity */ + tmpchctrl = TMRx->CCEN; + tmpchctrl &= (uint16_t)~((uint16_t)TMR_IC_POLARITY_BOTHEDGE); + tmpchctrl |= ICpolarity; + TMRx->CCEN = tmpchctrl; + + /** Set the CC1EN Bit */ + TMRx->CCEN_B.CC1EN = BIT_SET; +} + +/*! + * @brief Configure the TI2 as Input + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR periphera + * + * @param ICpolarity: The Input Polarity. + * + * @param ICselection: specifies the input to be used. + * + * @param ICfilter: Specifies the Input Capture Filter + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +static void TI2Config(TMR_T* TMRx, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + /** Disable the Channel 2: Reset the CC2EN Bit */ + TMRx->CCEN_B.CC2EN = BIT_RESET; + + /** Select the Input and set the filter */ + TMRx->CCM1_INPUT_B.CC2SEL = BIT_RESET; + TMRx->CCM1_INPUT_B.IC2F = BIT_RESET; + TMRx->CCM1_INPUT_B.CC2SEL = ICselection; + TMRx->CCM1_INPUT_B.IC2F = ICfilter; + + /** Select the Polarity */ + tmpchctrl = TMRx->CCEN; + tmpchctrl &= (uint16_t)~((uint16_t)TMR_IC_POLARITY_BOTHEDGE << 4); + tmpchctrl |= (uint16_t)(ICpolarity << 4); + TMRx->CCEN = tmpchctrl; + + /** Set the CC2EN Bit */ + TMRx->CCEN_B.CC2EN = BIT_SET; +} + +/*! + * @brief Configure the TI3 as Input. + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TMR peripheral + * + * @param ICpolarity: The Input Polarity. + * + * @param ICselection: specifies the input to be used. + * + * @param ICfilter: Specifies the Input Capture Filter + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +static void TI3Config(TMR_T* TMRx, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + /** Disable the Channel 3: Reset the CC3EN Bit */ + TMRx->CCEN_B.CC3EN = BIT_RESET; + + /** Select the Input and set the filter */ + TMRx->CCM2_INPUT_B.CC3SEL = BIT_RESET; + TMRx->CCM2_INPUT_B.IC3F = BIT_RESET; + TMRx->CCM2_INPUT_B.CC3SEL = ICselection; + TMRx->CCM2_INPUT_B.IC3F = ICfilter; + + /** Select the Polarity */ + tmpchctrl = TMRx->CCEN; + tmpchctrl &= (uint16_t)~((uint16_t)TMR_IC_POLARITY_BOTHEDGE << 8); + tmpchctrl |= (uint16_t)(ICpolarity << 8); + TMRx->CCEN = tmpchctrl; + + /** Set the CC3EN Bit */ + TMRx->CCEN_B.CC3EN = BIT_SET; +} + +/*! + * @brief Configure the TI4 as Input + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TMR peripheral + * + * @param ICpolarity: The Input Polarity. + * + * @param ICselection: specifies the input to be used. + * + * @param ICfilter: Specifies the Input Capture Filter + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +static void TI4Config(TMR_T* TMRx, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + /** Disable the Channel 4: Reset the CC4EN Bit */ + TMRx->CCEN_B.CC4EN = BIT_RESET; + + /** Select the Input and set the filter */ + TMRx->CCM2_INPUT_B.CC4SEL = BIT_RESET; + TMRx->CCM2_INPUT_B.IC4F = BIT_RESET; + TMRx->CCM2_INPUT_B.CC4SEL = ICselection; + TMRx->CCM2_INPUT_B.IC4F = ICfilter; + + /** Select the Polarity */ + tmpchctrl = TMRx->CCEN; + tmpchctrl &= (uint16_t)~((uint16_t)TMR_IC_POLARITY_BOTHEDGE << 12); + tmpchctrl |= (uint16_t)(ICpolarity << 12); + TMRx->CCEN = tmpchctrl; + + /** Set the CC4EN Bit */ + TMRx->CCEN_B.CC4EN = BIT_SET; +} + +/*! + * @brief Configure Peripheral equipment + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TMR peripheral + * + * @param ICconfigstruct: pointer to a TMR_ICConfig_T structure + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ICConfig(TMR_T* TMRx, TMR_ICConfig_T* ICconfigstruct) +{ + if (ICconfigstruct->channel == TMR_CHANNEL_1) + { + /** TI1 Configuration */ + TI1Config(TMRx, ICconfigstruct->ICpolarity, ICconfigstruct->ICselection, ICconfigstruct->ICfilter); + TMR_SetIC1Prescal(TMRx, ICconfigstruct->ICprescaler); + } + else if (ICconfigstruct->channel == TMR_CHANNEL_2) + { + /** TI2 Configuration */ + TI2Config(TMRx, ICconfigstruct->ICpolarity, ICconfigstruct->ICselection, ICconfigstruct->ICfilter); + TMR_SetIC2Prescal(TMRx, ICconfigstruct->ICprescaler); + } + else if (ICconfigstruct->channel == TMR_CHANNEL_3) + { + /** TI3 Configuration */ + TI3Config(TMRx, ICconfigstruct->ICpolarity, ICconfigstruct->ICselection, ICconfigstruct->ICfilter); + TMR_SetIC3Prescal(TMRx, ICconfigstruct->ICprescaler); + } + else if (ICconfigstruct->channel == TMR_CHANNEL_4) + { + /** TI4 Configuration */ + TI4Config(TMRx, ICconfigstruct->ICpolarity, ICconfigstruct->ICselection, ICconfigstruct->ICfilter); + TMR_SetIC4Prescal(TMRx, ICconfigstruct->ICprescaler); + } +} + +/*! + * @brief Initialize the IC timer with its default value. + * + * @param ICconfigstruct: pointer to a TMR_ICConfig_T structure + * + * @retval None + */ +void TMR_ICConfigStructInit(TMR_ICConfig_T* ICconfigstruct) +{ + ICconfigstruct->channel = TMR_CHANNEL_1; + ICconfigstruct->ICpolarity = TMR_IC_POLARITY_RISING; + ICconfigstruct->ICselection = TMR_IC_SELECTION_DIRECT_TI; + ICconfigstruct->ICprescaler = TMR_ICPSC_DIV1; + ICconfigstruct->ICfilter = 0x00; +} + +/*! + * @brief Config of PWM output + * + * @param TMRx: where x can be 1, 2, 3 and 15 to select the TMR peripheral + * + * @param ICconfigstruct: pointer to a TMR_ICConfig_T structure + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_PWMConfig(TMR_T* TMRx, TMR_ICConfig_T* ICconfigstruct) +{ + uint16_t icpolarity = TMR_IC_POLARITY_RISING; + uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI; + + /** Select the Opposite Input Polarity */ + if (ICconfigstruct->ICpolarity == TMR_IC_POLARITY_RISING) + { + icpolarity = TMR_IC_POLARITY_FALLING; + } + else + { + icpolarity = TMR_IC_POLARITY_RISING; + } + + /** Select the Opposite Input */ + if (ICconfigstruct->ICselection == TMR_IC_SELECTION_DIRECT_TI) + { + icselection = TMR_IC_SELECTION_INDIRECT_TI; + } + else + { + icselection = TMR_IC_SELECTION_DIRECT_TI; + } + + if (ICconfigstruct->channel == TMR_CHANNEL_1) + { + /** TI1 Configuration */ + TI1Config(TMRx, ICconfigstruct->ICpolarity, ICconfigstruct->ICselection, ICconfigstruct->ICfilter); + /** Set the Input Capture Prescaler value */ + TMR_SetIC1Prescal(TMRx, ICconfigstruct->ICprescaler); + /** TI2 Configuration */ + TI2Config(TMRx, icpolarity, icselection, ICconfigstruct->ICfilter); + /** Set the Input Capture Prescaler value */ + TMR_SetIC2Prescal(TMRx, ICconfigstruct->ICprescaler); + } + else + { + /** TI2 Configuration */ + TI2Config(TMRx, ICconfigstruct->ICpolarity, ICconfigstruct->ICselection, ICconfigstruct->ICfilter); + /** Set the Input Capture Prescaler value */ + TMR_SetIC2Prescal(TMRx, ICconfigstruct->ICprescaler); + /** TI1 Configuration */ + TI1Config(TMRx, icpolarity, icselection, ICconfigstruct->ICfilter); + /** Set the Input Capture Prescaler value */ + TMR_SetIC1Prescal(TMRx, ICconfigstruct->ICprescaler); + } +} + +/*! + * @brief Read Input Capture 1 value + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @retval Capture Compare 1 Register value + * + * @note TMR2 it's not for APM32F030 devices + */ +uint16_t TMR_ReadCaputer1(TMR_T* TMRx) +{ + return TMRx->CC1; +} + +/*! + * @brief Read Input Capture 2 value + * + * @param TMRx: where x can be 1, 2, 3 and 15 to select the TMR peripheral + * + * @retval Capture Compare 2 Register value + * + * @note TMR2 it's not for APM32F030 devices + */ +uint16_t TMR_ReadCaputer2(TMR_T* TMRx) +{ + return TMRx->CC2; +} + +/*! + * @brief Read Input Capture 3 value + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @retval Capture Compare 3 Register value + * + * @note TMR2 it's not for APM32F030 devices + */ +uint16_t TMR_ReadCaputer3(TMR_T* TMRx) +{ + return TMRx->CC3; +} + +/*! + * @brief Read Input Capture 4 value + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @retval Capture Compare 4 Register value + * + * @note TMR2 it's not for APM32F030 devices + */ +uint16_t TMR_ReadCaputer4(TMR_T* TMRx) +{ + return TMRx->CC4; +} + +/*! + * @brief Sets the TMRx Input Capture 1 prescaler + * + * @param TMRx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param prescaler: specifies the Input Capture 1 prescaler new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetIC1Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler) +{ + TMRx->CCM1_INPUT_B.IC1PSC = BIT_RESET; + TMRx->CCM1_INPUT_B.IC1PSC = prescaler; +} +/*! + * @brief Sets the TMRx Input Capture 2 prescaler + * + * @param TMRx: where x can be 1, 2, 3 and 15 to select the TMR peripheral + * + * @param prescaler: specifies the Input Capture 2 prescaler new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetIC2Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler) +{ + TMRx->CCM1_INPUT_B.IC2PSC = BIT_RESET; + TMRx->CCM1_INPUT_B.IC2PSC = prescaler; +} + +/*! + * @brief Sets the TMRx Input Capture 3 prescaler + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param prescaler: specifies the Input Capture 3 prescaler new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetIC3Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler) +{ + TMRx->CCM2_INPUT_B.IC3PSC = BIT_RESET; + TMRx->CCM2_INPUT_B.IC3PSC = prescaler; +} + +/*! + * @brief Sets the TMRx Input Capture 4 prescaler + * + * @param TMRx: where x can be 1, 2, 3 to select the TMR peripheral + * + * @param prescaler: specifies the Input Capture 4 prescaler new value + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SetIC4Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler) +{ + TMRx->CCM2_INPUT_B.IC4PSC = BIT_RESET; + TMRx->CCM2_INPUT_B.IC4PSC = prescaler; +} + +/*! + * @brief Enable intterupts + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_INT_UPDATE: TMR update Interrupt source + * @arg TMR_INT_CH1: TMR Capture Compare 1 Interrupt source + * @arg TMR_INT_CH2: TMR Capture Compare 2 Interrupt source + * @arg TMR_INT_CH3: TMR Capture Compare 3 Interrupt source + * @arg TMR_INT_CH4: TMR Capture Compare 4 Interrupt source + * @arg TMR_INT_CCU: TMR Commutation Interrupt source + * @arg TMR_INT_TRG: TMR Trigger Interrupt source + * @arg TMR_INT_BRK: TMR Break Interrupt source + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_EnableInterrupt(TMR_T* TMRx, uint16_t interrupt) +{ + TMRx->DIEN |= interrupt; +} + +/*! + * @brief Disable intterupts + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_INT_UPDATE: TMR update Interrupt source + * @arg TMR_INT_CH1: TMR Capture Compare 1 Interrupt source + * @arg TMR_INT_CH2: TMR Capture Compare 2 Interrupt source + * @arg TMR_INT_CH3: TMR Capture Compare 3 Interrupt source + * @arg TMR_INT_CH4: TMR Capture Compare 4 Interrupt source + * @arg TMR_INT_CCU: TMR Commutation Interrupt source + * @arg TMR_INT_TRG: TMR Trigger Interrupt source + * @arg TMR_INT_BRK: TMR Break Interrupt source + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_DisableInterrupt(TMR_T* TMRx, uint16_t interrupt) +{ + TMRx->DIEN &= ~interrupt; +} + +/*! + * @brief Configures the TMRx event to be generate by software + * + * @param TMRx: where x can be 123, 14, 15, 16 and 17 to select the TMR peripheral + * + * @param event: specifies the TMR generate event + * The parameter can be any combination of following values: + * @arg TMR_EVENT_UPDATE: TMR update Interrupt source + * @arg TMR_EVENT_CH1: TMR Capture Compare 1 Interrupt source + * @arg TMR_EVENT_CH2: TMR Capture Compare 2 Interrupt source + * @arg TMR_EVENT_CH3: TMR Capture Compare 3 Interrupt source + * @arg TMR_EVENT_CH4: TMR Capture Compare 4 Interrupt source + * @arg TMR_EVENT_CCU: TMR Commutation Interrupt source + * @arg TMR_EVENT_TRG: TMR Trigger Interrupt source + * @arg TMR_EVENT_BRK: TMR Break Interrupt source + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + * TMR6 and TMR7 only TMR_EVENT_UPDATE + * TMR_EVENT_CCU and TMR_EVENT_BRK are used only with TMR1 + */ +void TMR_GenerateEvent(TMR_T* TMRx, uint16_t event) +{ + TMRx->CEG |= event; +} + +/*! + * @brief Check whether the flag is set or reset + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + * + * @param flag: specifies the TMR flag + * The parameter can be one of following values: + * @arg TMR_FLAG_UPDATA: TMR update Flag + * @arg TMR_FLAG_CH1: TMR Capture Compare 1 flag + * @arg TMR_FLAG_CH2: TMR Capture Compare 2 flag + * @arg TMR_FLAG_CH3: TMR Capture Compare 3 flag + * @arg TMR_FLAG_CH4: TMR Capture Compare 4 flag + * @arg TMR_FLAG_CCU: TMR Commutation flag + * @arg TMR_FLAG_TRG: TMR Trigger flag + * @arg TMR_FLAG_BRK: TMR Break flag + * @arg TMR_FLAG_CH1OC: TMR Capture Compare 1 overcapture flag + * @arg TMR_FLAG_CH2OC: TMR Capture Compare 2 overcapture flag + * @arg TMR_FLAG_CH3OC: TMR Capture Compare 3 overcapture flag + * @arg TMR_FLAG_CH4OC: TMR Capture Compare 4 overcapture flag + * + * @retval The new state of the flag is SET or RESET + * + * @note TMR15 can have only TMR_FLAG_UPDATA, TMR_FLAG_CH1, TMR_FLAG_CH2 and TMR_FLAG_TRG + * TMR14, TMR16 and TMR17 can have TMR_FLAG_UPDATA and TMR_FLAG_CH1 + * TMR6, TMR7 only TMR_FLAG_UPDATA + * TMR_FLAG_BRK is used only with TMR1 and TMR15. + * TMR_FLAG_CCU is used only with TMR1, TMR15, TMR16 and TMR17 + */ +uint16_t TMR_ReadStatusFlag(TMR_T* TMRx, TMR_FLAG_T flag) +{ + if ((TMRx->STS & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the TMR's pending flags + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + * + * @param flag: specifies the TMR flag + * The parameter can be any combination of following values: + * @arg TMR_FLAG_UPDATA: TMR update Flag + * @arg TMR_FLAG_CH1: TMR Capture Compare 1 flag + * @arg TMR_FLAG_CH2: TMR Capture Compare 2 flag + * @arg TMR_FLAG_CH3: TMR Capture Compare 3 flag + * @arg TMR_FLAG_CH4: TMR Capture Compare 4 flag + * @arg TMR_FLAG_CCU: TMR Commutation flag + * @arg TMR_FLAG_TRG: TMR Trigger flag + * @arg TMR_FLAG_BRK: TMR Break flag + * @arg TMR_FLAG_CH1OC: TMR Capture Compare 1 overcapture flag + * @arg TMR_FLAG_CH2OC: TMR Capture Compare 2 overcapture flag + * @arg TMR_FLAG_CH3OC: TMR Capture Compare 3 overcapture flag + * @arg TMR_FLAG_CH4OC: TMR Capture Compare 4 overcapture flag + * + * @retval None + */ +void TMR_ClearStatusFlag(TMR_T* TMRx, uint16_t flag) +{ + TMRx->STS = ~flag; +} + +/*! + * @brief Check whether the TMR Interrupt flag is set or reset + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + * + * @param flag: specifies the TMR interrupts flag + * The parameter can be one of following values: + * @arg TMR_INT_FLAG_UPDATE: TMR update Interrupt flag + * @arg TMR_INT_FLAG_CH1: TMR Capture Compare 1 Interrupt flag + * @arg TMR_INT_FLAG_CH2: TMR Capture Compare 2 Interrupt flag + * @arg TMR_INT_FLAG_CH3: TMR Capture Compare 3 Interrupt flag + * @arg TMR_INT_FLAG_CH4: TMR Capture Compare 4 Interrupt flag + * @arg TMR_INT_FLAG_CCU: TMR Commutation Interrupt flag + * @arg TMR_INT_FLAG_TRG: TMR Trigger Interrupt flag + * @arg TMR_INT_FLAG_BRK: TMR Break Interrupt flag + * + * @retval The new state of the INT flag is SET or RESET + * + * @note TMR15 can have only TMR_INT_FLAG_UPDATE, TMR_INT_FLAG_CH1, TMR_INT_FLAG_CH2 and TMR_INT_FLAG_TRG + * TMR14, TMR16 and TMR17 can have TMR_INT_FLAG_UPDATE and TMR_INT_FLAG_CH1 + * TMR6, TMR7 only TMR_INT_FLAG_UPDATE + * TMR_INT_FLAG_BRK is used only with TMR1 and TMR15. + * TMR_INT_FLAG_CCU is used only with TMR1, TMR15, TMR16 and TMR17 + */ +uint16_t TMR_ReadIntFlag(TMR_T* TMRx, TMR_INT_FLAG_T flag) +{ + if (((TMRx->STS & flag) != RESET) && ((TMRx->DIEN & flag) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the TMR's interrupt pending bits + * + * @param TMRx: x can be can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select Timer + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + * + * @param flag: specifies the TMR interrupts flag + * The parameter can be any combination of following values: + * @arg TMR_INT_FLAG_UPDATE: TMR update Interrupt flag + * @arg TMR_INT_FLAG_CH1: TMR Capture Compare 1 Interrupt flag + * @arg TMR_INT_FLAG_CH2: TMR Capture Compare 2 Interrupt flag + * @arg TMR_INT_FLAG_CH3: TMR Capture Compare 3 Interrupt flag + * @arg TMR_INT_FLAG_CH4: TMR Capture Compare 4 Interrupt flag + * @arg TMR_INT_FLAG_CCU: TMR Commutation Interrupt flag + * @arg TMR_INT_FLAG_TRG: TMR Trigger Interrupt flag + * @arg TMR_INT_FLAG_BRK: TMR Break Interrupt flag + * + * @retval None + */ +void TMR_ClearIntFlag(TMR_T* TMRx, uint16_t flag) +{ + TMRx->STS = ~flag; +} + +/*! + * @brief Configures the TMRx's DMA interface. + * + * @param TMRx: where x can be 1, 2, 3, 15, 16 and 17 to select the TMR peripheral + * + * @param address: DMA Base address + * + * @param lenght: DMA Burst length + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigDMA(TMR_T* TMRx, TMR_DMA_BASE_ADDERSS_T address, TMR_DMA_BURST_LENGHT_T lenght) +{ + TMRx->DCTRL = (uint32_t)address | (uint32_t)lenght; +} + +/*! + * @brief Enable TMRx Requests + * + * @param TMRx: where x can be 1, 2, 3, 6, 7, 15, 16 and 17 to select the TMR peripheral + * + * @param souces: specifies the TMR DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_UPDATE: TMR update DMA souces + * @arg TMR_DMA_CH1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_CH2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_CH3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_CH4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_CCU: TMR Commutation DMA souces + * @arg TMR_DMA_TRG: TMR Trigger DMA souces + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_EnableDMASoure(TMR_T* TMRx, uint16_t souces) +{ + TMRx->DIEN |= souces; +} + +/*! + * @brief Disable TMRx Requests + * + * @param TMRx: where x can be 1, 2, 3, 6, 7, 15, 16 and 17 to select the TMR peripheral + * + * @param souces: specifies the TMR DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_UPDATE: TMR update DMA souces + * @arg TMR_DMA_CH1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_CH2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_CH3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_CH4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_CCU: TMR Commutation DMA souces + * @arg TMR_DMA_TRG: TMR Trigger DMA souces + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_DisableDMASoure(TMR_T* TMRx, uint16_t souces) +{ + TMRx->DIEN &= ~souces; +} + +/*! + * @brief Enable Capture Compare DMA source + * + * @param TMRx: where x can be 1, 2, 3, 15, 16 and 17 to select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_EnableCCDMA(TMR_T* TMRx) +{ + TMRx->CTRL2_B.CCDSEL = ENABLE; +} + +/*! + * @brief Disable Capture Compare DMA source + * + * @param TMRx: where x can be 1, 2, 3, 15, 16 and 17 to select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_DisableCCDMA(TMR_T* TMRx) +{ + TMRx->CTRL2_B.CCDSEL = DISABLE; +} + +/*! + * @brief Configures the TMRx internal Clock + * + * @param TMRx: where x can be 1, 2, 3, and 15 select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigInternalClock(TMR_T* TMRx) +{ + TMRx->SMCTRL_B.SMFSEL = DISABLE; +} + +/*! + * @brief Configures the TMRx Internal Trigger as External Clock + * + * @param TMRx: where x can be 1, 2, 3, and 15 select the TMR peripheral + * + * @param input: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TS_ITR0: TMR Internal Trigger 0 + * @arg TMR_TS_ITR1: TMR Internal Trigger 1 + * @arg TMR_TS_ITR2: TMR Internal Trigger 2 + * @arg TMR_TS_ITR3: TMR Internal Trigger 3 + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigITRxExternalClock(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input) +{ + TMR_SelectInputTrigger(TMRx, input); + TMRx->SMCTRL_B.SMFSEL = 0x07; +} + +/*! + * @brief Configures the TMRx Trigger as External Clock + * + * @param TMRx: where x can be 1, 2, 3, and 15 select the TMR peripheral + * + * @param input: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TS_TI1F_ED: TI1 Edge Detector + * @arg TMR_TS_TI1FP1: Filtered Timer Input 1 + * @arg TMR_TS_TI2FP2: Filtered Timer Input 2 + * + * @param ICpolarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * + * @param ICfilter:specifies the filter value.This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigTIxExternalClock(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter) +{ + if (input == TMR_TS_TI2FP2) + { + TI2Config(TMRx, ICpolarity, TMR_IC_SELECTION_DIRECT_TI, ICfilter); + } + else + { + TI1Config(TMRx, ICpolarity, TMR_IC_SELECTION_DIRECT_TI, ICfilter); + } + + TMR_SelectInputTrigger(TMRx, input); + TMRx->SMCTRL_B.SMFSEL = 0x07; +} + +/*! + * @brief Configures the External clock Mode1 + * + * @param TMRx: where x can be 1, 2, 3 select the TMR peripheral + * + * @param prescaler: The external Trigger Prescaler. + * + * @param polarity: The external Trigger Polarity. + * + * @param filter: External Trigger Filter. + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigExternalClockMode1(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler, + TMR_EXTTRG_POLARITY_T polarity, uint16_t filter) +{ + TMR_ConfigExternalTrigger(TMRx, prescaler, polarity, filter); + TMRx->SMCTRL_B.SMFSEL = BIT_RESET; + TMRx->SMCTRL_B.SMFSEL = 0x07; + TMRx->SMCTRL_B.TRGSEL = 0x07; +} + +/*! + * @brief Configures the External clock Mode2 + * + * @param TMRx: where x can be 1, 2, 3 select the TMR peripheral + * + * @param prescaler: The external Trigger Prescaler + * + * @param polarity: The external Trigger Polarity + * + * @param filter: External Trigger Filter + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigExternalClockMode2(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler, + TMR_EXTTRG_POLARITY_T polarity, uint16_t filter) +{ + TMR_ConfigExternalTrigger(TMRx, prescaler, polarity, filter); + TMRx->SMCTRL_B.ECEN = ENABLE; +} + +/*! + * @brief Selects the Input Trigger source + * + * @param TMRx: where x can be 1, 2, 3 and 15 select the TMR peripheral + * + * @param input: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TS_ITR0: TMR Internal Trigger 0 + * @arg TMR_TS_ITR1: TMR Internal Trigger 1 + * @arg TMR_TS_ITR2: TMR Internal Trigger 2 + * @arg TMR_TS_ITR3: TMR Internal Trigger 3 + * @arg TMR_TS_TI1F_ED: TI1 Edge Detector + * @arg TMR_TS_TI1FP1: Filtered Timer Input 1 + * @arg TMR_TS_TI2FP2: Filtered Timer Input 2 + * @arg TMR_TS_ETRF: External Trigger input + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SelectInputTrigger(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input) +{ + TMRx->SMCTRL_B.TRGSEL = BIT_RESET; + TMRx->SMCTRL_B.TRGSEL = input; +} + +/*! + * @brief Selects the Trigger Output Mode. + * + * @param TMRx: where x can be 1, 2, 3, 6, 7 and 15 select the TMR peripheral + * + * @param source: specifies the TMR trigger souces + * The parameter can be one of following values: + * For all TMR: + * @arg TMR_TRGOSOURCE_RESET + * @arg TMR_TRGOSOURCE_ENABLE + * @arg TMR_TRGOSOURCE_UPDATE + For all TMR except TMR6 and TMR7 + * @arg TMR_TRGOSOURCE_OC1, + * @arg TMR_TRGOSOURCE_OC1REF + * @arg TMR_TRGOSOURCE_OC2REF + * @arg TMR_TRGOSOURCE_OC3REF + * @arg TMR_TRGOSOURCE_OC4REF + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + * TMR7 it's only for APM32F072 and APM32F091 devices + */ +void TMR_SelectOutputTrigger(TMR_T* TMRx, TMR_TRGOSOURCE_T source) +{ + TMRx->CTRL2_B.MMSEL = source; +} + +/*! + * @brief Selects the Slave Mode. + * + * @param TMRx: where x can be 1, 2, 3 and 15 select the TMR peripheral + * + * @param mode: TMR_SLAVEMODE_T + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_SelectSlaveMode(TMR_T* TMRx, TMR_SLAVEMODE_T mode) +{ + TMRx->SMCTRL_B.SMFSEL = mode; +} + +/*! + * @brief Enable the Master Slave Mode + * + * @param TMRx: where x can be 1, 2, 3 and 15 select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_EnableMasterSlaveMode(TMR_T* TMRx) +{ + TMRx->SMCTRL_B.MSMEN = ENABLE ; +} + +/*! + * @brief Disable the Master Slave Mode + * + * @param TMRx: where x can be 1, 2, 3 and 15 select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_DisableMasterSlaveMode(TMR_T* TMRx) +{ + TMRx->SMCTRL_B.MSMEN = DISABLE ; +} + +/*! + * @brief Configures the TMRx External Trigger (ETR) + * + * @param TMRx: where x can be 1, 2, 3 select the TMR peripheral + * + * @param prescaler: The external Trigger Prescaler + * + * @param polarity: The external Trigger Polarity + * + * @param filter: External Trigger Filter + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigExternalTrigger(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler, + TMR_EXTTRG_POLARITY_T polarity, uint16_t filter) +{ + TMRx->SMCTRL &= 0x00FF; + TMRx->SMCTRL_B.ETPCFG = prescaler; + TMRx->SMCTRL_B.ETPOL = polarity; + TMRx->SMCTRL_B.ETFCFG = filter; +} + +/*! + * @brief Configures the Encoder Interface + * + * @param TMRx: where x can be 1, 2, 3 select the TMR peripheral + * + * @param encodeMode: specifies the Encoder Mode + * + * @param IC1Polarity: specifies the IC1 Polarity + * + * @param IC2Polarity: specifies the IC2 Polarity + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigEncodeInterface(TMR_T* TMRx, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, + TMR_IC_POLARITY_T IC2Polarity) +{ + /** Set the encoder Mode */ + TMRx->SMCTRL_B.SMFSEL = BIT_RESET; + TMRx->SMCTRL_B.SMFSEL = encodeMode; + + /** Select the Capture Compare 1 and the Capture Compare 2 as input */ + TMRx->CCM1_INPUT_B.CC1SEL = BIT_RESET ; + TMRx->CCM1_INPUT_B.CC2SEL = BIT_RESET ; + TMRx->CCM1_INPUT_B.CC1SEL = BIT_SET ; + TMRx->CCM1_INPUT_B.CC2SEL = BIT_SET ; + + /** Set the TI1 and the TI2 Polarities */ + TMRx->CCEN &= ~(TMR_IC_POLARITY_BOTHEDGE) & ~(TMR_IC_POLARITY_BOTHEDGE << 4); + TMRx->CCEN |= (IC1Polarity | IC2Polarity << 4); +} + +/*! + * @brief Enables Hall sensor interface. + * + * @param TMRx: where x can be 1, 2, 3 select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_EnableHallSensor(TMR_T* TMRx) +{ + TMRx->CTRL2_B.TI1SEL = ENABLE; +} + +/*! + * @brief Disable Hall sensor interface. + * + * @param TMRx: where x can be 1, 2, 3 select the TMR peripheral + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_DisableHallSensor(TMR_T* TMRx) +{ + TMRx->CTRL2_B.TI1SEL = DISABLE; +} + +/*! + * @brief Configures the TMR14 Remapping input Capabilities. + * + * @param TMRx: where x can only for 14 select the TMR peripheral + * + * @param remap: specifies the TMR input reampping source + * The parameter can be one of following values: + * @arg TMR_REMAP_GPIO + * @arg TMR_REMAP_RTC_CLK + * @arg TMR_REMAP_HSEDiv32 + * @arg TMR_REMAP_MCO + * + * @retval None + * + * @note TMR2 it's not for APM32F030 devices + */ +void TMR_ConfigRemap(TMR_T* TMRx, TMR_REMAP_T remap) +{ + TMRx->OPT_B.RMPSEL = remap; +} + +/**@} end of group TMR_Functions*/ +/**@} end of group TMR_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_usart.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_usart.c new file mode 100644 index 0000000000..3ffd8245d5 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_usart.c @@ -0,0 +1,1741 @@ +/*! + * @file apm32f0xx_usart.c + * + * @brief This file provides all the USART firmware functions + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_usart.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup USART_Driver USART Driver + @{ +*/ + +/** @defgroup USART_Macros Macros + @{ + */ + +/**@} end of group USART_Macros */ + +/** @defgroup USART_Enumerations Enumerations + @{ + */ + +/**@} end of group USART_Enumerations */ + +/** @defgroup USART_Structures Structures + @{ + */ + +/**@} end of group USART_Structures */ + +/** @defgroup USART_Variables Variables + @{ + */ + +/**@} end of group USART_Variables */ + +/** @defgroup USART_Functions Functions + @{ +*/ + +/*! + * @brief Reset usart peripheral registers to their default reset values + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ + +void USART_Reset(USART_T* usart) +{ + if (USART1 == usart) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_USART1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_USART1); + } + else if (USART2 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART2); + } + else if (USART3 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART3); + } + else if (USART4 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART4); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART4); + } + else if (USART5 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART5); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART5); + } + else if (USART6 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB2_PERIPH_USART6); + RCM_DisableAPB1PeriphReset(RCM_APB2_PERIPH_USART6); + } + else if (USART7 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB2_PERIPH_USART7); + RCM_DisableAPB1PeriphReset(RCM_APB2_PERIPH_USART7); + } + else if (USART8 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB2_PERIPH_USART8); + RCM_DisableAPB1PeriphReset(RCM_APB2_PERIPH_USART8); + } +} + +/*! + * @brief Config the USART peripheral according to the specified parameters in the USART_InitStruct + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param configStruct pointer to a USART_Config_T structure + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_Config(USART_T* uart, USART_Config_T* configStruct) +{ + uint32_t temp, fCLK, intDiv, fractionalDiv; + + /** Disable USART */ + uart->CTRL1_B.UEN = 0x00; + + /** WLS, PCEN, TXEN, RXEN */ + temp = uart->CTRL1; + temp &= 0xE9F3; + temp |= (uint32_t)configStruct->mode | \ + (uint32_t)configStruct->parity | \ + (uint32_t)configStruct->wordLength; + uart->CTRL1 = temp; + + /** STOP bits */ + temp = uart->CTRL2; + temp &= 0xCFFF; + temp |= configStruct->stopBits; + uart->CTRL2 = temp; + + /** Hardware Flow Control */ + temp = uart->CTRL3; + temp &= 0xFCFF; + temp |= (uint32_t)configStruct->hardwareFlowCtrl; + uart->CTRL3 = temp; + + if (uart == USART1) + { + fCLK = RCM_ReadUSART1CLKFreq(); + } + else if (uart == USART2) + { + fCLK = RCM_ReadUSART2CLKFreq(); + } + else + { + fCLK = RCM_ReadPCLKFreq(); + } + + intDiv = ((25 * fCLK) / (4 * (configStruct->baudRate))); + temp = (intDiv / 100) << 4; + fractionalDiv = intDiv - (100 * (temp >> 4)); + temp |= ((((fractionalDiv * 16) + 50) / 100)) & ((uint8_t)0x0F); + + uart->BR = temp; +} + +/*! + * @brief Fills each USART_InitStruct member with its default value + * + * @param configStruct pointer to a USART_Config_T structure which will be initialized + * + * @retval None + */ +void USART_ConfigStructInit(USART_Config_T* configStruct) +{ + configStruct->baudRate = 9600; + configStruct->wordLength = USART_WORD_LEN_8B; + configStruct->stopBits = USART_STOP_BIT_1; + configStruct->parity = USART_PARITY_NONE ; + configStruct->mode = USART_MODE_TX_RX; + configStruct->hardwareFlowCtrl = USART_FLOW_CTRL_NONE; +} + +/*! + * @brief Synchronous communication clock configuration + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param SyncClockConfig: Pointer to a USART_SyncClockConfig_T structure that + * contains the configuration information for the clock + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ConfigSyncClock(USART_T* usart, USART_SyncClockConfig_T* SyncClockConfig) +{ + usart->CTRL2_B.CLKEN = SyncClockConfig->enable; + usart->CTRL2_B.CPHA = SyncClockConfig->phase; + usart->CTRL2_B.CPOL = SyncClockConfig->polarity; + usart->CTRL2_B.LBCPOEN = SyncClockConfig->lastBitClock; +} + +/*! + * @brief Fills each SyncClockConfig member with its default value + * + * @param SyncClockConfig: Pointer to a USART_SyncClockConfig_T structure + * + * @retval None + */ +void USART_ConfigSyncClockStructInit(USART_SyncClockConfig_T* SyncClockConfig) +{ + SyncClockConfig->enable = USART_CLKEN_DISABLE; + SyncClockConfig->phase = USART_CLKPHA_1EDGE; + SyncClockConfig->polarity = USART_CLKPOL_LOW; + SyncClockConfig->lastBitClock = USART_LBCP_DISABLE; +} + +/*! + * @brief Enables the specified USART peripheral + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_Enable(USART_T* usart) +{ + usart->CTRL1_B.UEN = BIT_SET; +} + +/*! + * @brief Disables the specified USART peripheral + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_Disable(USART_T* usart) +{ + usart->CTRL1_B.UEN = BIT_RESET; +} + +/*! + * @brief Enables the USART direction mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param mode: Specifies the USART direction + * The parameter can be one of following values: + * @arg USART_MODE_RX: USART Transmitter + * @arg USART_MODE_TX: USART Receiver + * @arg USART_MODE_TX_RX: USART Transmitter and Receiver + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableDirectionMode(USART_T* usart, USART_MODE_T mode) +{ + if (mode == USART_MODE_RX) + { + usart->CTRL1_B.RXEN = BIT_SET; + } + + if (mode == USART_MODE_TX) + { + usart->CTRL1_B.TXEN = BIT_SET; + } + + if (mode == USART_MODE_TX_RX) + { + usart->CTRL1_B.TXEN = BIT_SET; + usart->CTRL1_B.RXEN = BIT_SET; + } +} + +/*! + * @brief Disables the USART direction mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param mode: Specifies the USART direction + * The parameter can be one of following values: + * @arg USART_MODE_RX: USART Transmitter + * @arg USART_MODE_TX: USART Receiver + * @arg USART_MODE_TX_RX: USART Transmitter and Receiver + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableDirectionMode(USART_T* usart, USART_MODE_T mode) +{ + if (mode == USART_MODE_RX) + { + usart->CTRL1_B.RXEN = BIT_RESET; + } + + if (mode == USART_MODE_TX) + { + usart->CTRL1_B.TXEN = BIT_RESET; + } + + if (mode == USART_MODE_TX_RX) + { + usart->CTRL1_B.TXEN = BIT_RESET; + usart->CTRL1_B.RXEN = BIT_RESET; + } +} + +/*! + * @brief Enables the Over Sampling 8/16 mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + * + * @note 0: Oversampling by 16 1: Oversampling by 8 + */ +void USART_EnableOverSampling8(USART_T* usart) +{ + usart->CTRL1_B.OSMCFG = BIT_SET; +} + +/*! + * @brief Disables the the Over Sampling 8/16 mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + * + * @note 0: Oversampling by 16 1: Oversampling by 8 + */ +void USART_DisableOverSampling8(USART_T* usart) +{ + usart->CTRL1_B.OSMCFG = BIT_RESET; +} + +/*! + * @brief Enables the USART's one bit sampling method. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableOneBitMethod(USART_T* usart) +{ + usart->CTRL3_B.SAMCFG = BIT_SET; +} + +/*! + * @brief Disables the USART's one bit sampling method. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableOneBitMethod(USART_T* usart) +{ + usart->CTRL3_B.SAMCFG = BIT_RESET; +} + +/*! + * @brief Enables the most significant bit first + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableMSBFirst(USART_T* usart) +{ + usart->CTRL2_B.MSBFEN = BIT_SET; +} + +/*! + * @brief Disables the most significant bit first + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableMSBFirst(USART_T* usart) +{ + usart->CTRL2_B.MSBFEN = BIT_RESET; +} + +/*! + * @brief Enables the the binary data inversion + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableDataInv(USART_T* usart) +{ + usart->CTRL2_B.BINVEN = BIT_SET; +} + +/*! + * @brief Disables the the binary data inversion + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableDataInv(USART_T* usart) +{ + usart->CTRL2_B.BINVEN = BIT_RESET; +} + +/*! + * @brief Enables the specified USART peripheral + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param invPin: specifies the USART pin(s) to invert + * This parameter can be one of the following values: + * @arg USART_INVERSION_RX: USART Tx pin active level inversion + * @arg USART_INVERSION_TX: USART Rx pin active level inversion + * @arg USART_INVERSION_TX_RX: USART TX Rx pin active level inversion + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableInvPin(USART_T* usart, USART_INVERSION_T invPin) +{ + if (invPin == USART_INVERSION_RX) + { + usart->CTRL2_B.RXINVEN = BIT_SET; + } + + if (invPin == USART_INVERSION_TX) + { + usart->CTRL2_B.TXINVEN = BIT_SET; + } + + if (invPin == (USART_INVERSION_TX_RX)) + { + usart->CTRL2_B.TXINVEN = BIT_SET; + usart->CTRL2_B.RXINVEN = BIT_SET; + } +} + +/*! + * @brief Disables the specified USART peripheral + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param invPin: specifies the USART pin(s) to invert + * This parameter can be one of the following values: + * @arg USART_INVERSION_RX: USART Tx pin active level inversion + * @arg USART_INVERSION_TX: USART Rx pin active level inversion + * @arg USART_INVERSION_TX_RX: USART TX Rx pin active level inversion + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableInvPin(USART_T* usart, USART_INVERSION_T invPin) +{ + if (invPin == USART_INVERSION_RX) + { + usart->CTRL2_B.RXINVEN = BIT_RESET; + } + + if (invPin == USART_INVERSION_TX) + { + usart->CTRL2_B.TXINVEN = BIT_RESET; + } + + if (invPin == USART_INVERSION_TX_RX) + { + usart->CTRL2_B.TXINVEN = BIT_RESET; + usart->CTRL2_B.RXINVEN = BIT_RESET; + } +} + +/*! + * @brief Enables the swap Tx/Rx pins + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableSWAPPin(USART_T* usart) +{ + usart->CTRL2_B.SWAPEN = BIT_SET; +} + +/*! + * @brief Disables the swap Tx/Rx pins + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableSWAPPin(USART_T* usart) +{ + usart->CTRL2_B.SWAPEN = BIT_RESET; +} + +/*! + * @brief Enables the receiver Time Out feature + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableReceiverTimeOut(USART_T* usart) +{ + usart->CTRL2_B.RXTODEN = BIT_SET; +} + +/*! + * @brief Disables the receiver Time Out feature + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableReceiverTimeOut(USART_T* usart) +{ + usart->CTRL2_B.RXTODEN = BIT_RESET; +} + +/*! + * @brief Sets the receiver Time Out value + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param timeOut: Specifies the Receiver Time Out value + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + * + * @note The value must less than 0x00FFFFFF + */ +void USART_ReceiverTimeOutValue(USART_T* usart, uint32_t timeOut) +{ + usart->RXTO = (uint32_t)0x00; + + if (timeOut <= (uint32_t)0x00FFFFFF) + { + usart->RXTO = ((uint32_t)timeOut & 0x00FFFFFF); + } +} + +/*! + * @brief Sets the system clock divider. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param divider: Specifies the prescaler clock value + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigDivider(USART_T* usart, uint8_t divider) +{ + usart->GTPSC &= (uint16_t)0xFF00; + usart->GTPSC_B.PSC = (uint8_t)divider; +} + +/*! + * @brief Enables the stop mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableStopMode(USART_T* usart) +{ + usart->CTRL1_B.USWMEN = BIT_SET; +} + +/*! + * @brief Disables the stop mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableStopMode(USART_T* usart) +{ + usart->CTRL1_B.USWMEN = BIT_RESET; +} + +/*! + * @brief Selects the USART WakeUp method form stop mode. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param source: Specifies the selected USART wakeup method + * This parameter can be one of the following values: + * @arg USART_WAKEUP_SOURCE_ADDRESS: WUP active on address match. + * @arg USART_WAKEUP_SOURCE_START: WUP active on Start bit detection. + * @arg USART_WAKEUP_SOURCE_RXNE: WUP active on RXNE. + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigStopModeWakeUpSource(USART_T* usart, USART_WAKEUP_SOURCE_T source) +{ + usart->CTRL3_B.WSIFLGSEL = source; +} + +/*! + * @brief Enables the auto baud rate + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableAutoBaudRate(USART_T* usart) +{ + usart->CTRL2_B.ABRDEN = BIT_SET; +} + +/*! + * @brief Disables the auto baud rate + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableAutoBaudRate(USART_T* usart) +{ + usart->CTRL2_B.ABRDEN = BIT_RESET; +} + +/*! + * @brief Enables the auto baud rate + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param mode: specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_AUTO_BAUD_RATE_STARTBIT: Start Bit duration measurement + * @arg USART_AUTO_BAUD_RATE_FALLINGEDGE: Falling edge to falling edge measurement + * + * @retval None + * + * @note The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigAutoBaudRate(USART_T* usart, USART_AUTO_BAUD_RATE_T mode) +{ + usart->CTRL2_B.ABRDCFG = mode; +} + +/*! + * @brief Transmit Data + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param data: Specifies the Transmits data value + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + * + * @note The value must less than 0x01FF + */ +void USART_TxData(USART_T* usart, uint16_t data) +{ + usart->TXDATA = (data & (uint16_t)0x01FF); +} + +/*! + * @brief Received Data + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval Returns the received data value + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +uint16_t USART_RxData(USART_T* usart) +{ + return (uint16_t)(usart->RXDATA & (uint16_t)0x01FF); +} + +/*! + * @brief Sets USART the address + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_Address(USART_T* usart, uint8_t address) +{ + usart->CTRL2_B.ADDRL = ((uint8_t)address & 0x0F); + usart->CTRL2_B.ADDRH = ((uint8_t)address >> 4 & 0x0F); + +} + +/*! + * @brief Enables the USART's mute mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableMuteMode(USART_T* usart) +{ + usart->CTRL1_B.RXMUTEEN = BIT_SET; +} + +/*! + * @brief Disables the USART's mute mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableMuteMode(USART_T* usart) +{ + usart->CTRL1_B.RXMUTEEN = BIT_RESET; +} + +/*! + * @brief Selects the USART WakeUp method from mute mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param wakeup: Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_WAKEUP_IDLE_LINE: WakeUp by an idle line detection + * @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ConfigMuteModeWakeUp(USART_T* usart, USART_WAKEUP_T wakeup) +{ + usart->CTRL1_B.WUPMCFG = wakeup; +} + +/*! + * @brief Enables the USART's LIN mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableLINmode(USART_T* usart) +{ + usart->CTRL2_B.LINMEN = BIT_SET; +} + +/*! + * @brief Disables the USART's LIN mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableLINmode(USART_T* usart) +{ + usart->CTRL2_B.LINMEN = BIT_RESET; +} + +/*! + * @brief Sets the USART LIN Break detection length. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param length: Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_BREAK_LENGTH_10B: 10-bit break detection + * @arg USART_BREAK_LENGTH_11B: 11-bit break detection + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigLINbreakDetectLength(USART_T* usart, USART_BREAK_LENGTH_T length) +{ + usart->CTRL2_B.LBDLCFG = length; +} + +/*! + * @brief Enables the USART's Half-duplex mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableHalfDuplex(USART_T* usart) +{ + usart->CTRL3_B.HDEN = BIT_SET; +} + +/*! + * @brief Disables the USART's Half-duplex mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableHalfDuplex(USART_T* usart) +{ + usart->CTRL3_B.HDEN = BIT_RESET; +} + +/*! + * @brief Enables the USART's Smart Card mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableSmartCard(USART_T* usart) +{ + usart->CTRL3_B.SCEN = BIT_SET; +} + +/*! + * @brief Disables the USART's Smart Card mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableSmartCard(USART_T* usart) +{ + usart->CTRL3_B.SCEN = BIT_RESET; +} + +/*! + * @brief Enables the USART's NACK transmission + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableSmartCardNACK(USART_T* usart) +{ + usart->CTRL3_B.SCNACKEN = BIT_SET; +} + +/*! + * @brief Disables the USART's NACK transmission + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableSmartCardNACK(USART_T* usart) +{ + usart->CTRL3_B.SCNACKEN = BIT_RESET; +} + +/*! + * @brief Config the specified USART guard time. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param guardTime: specifies the guard time value + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime) +{ + usart->GTPSC &= (uint16_t)0x00FF; + usart->GTPSC_B.GRDT = (uint8_t)guardTime; +} + +/*! + * @brief Config the specified USART Smart Card number. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param autoCount: specifies the Smart Card auto retry count. + * It's <= 0x07. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigAutoCount(USART_T* usart, uint8_t autoCount) +{ + usart->CTRL3_B.SCARCCFG = autoCount; +} + +/*! + * @brief Config the Smart Card Block length. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param blockSize: specifies the Smart Card block size. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigBlockSize(USART_T* usart, uint8_t blockSize) +{ + usart->RXTO_B.BLEN = (uint8_t)blockSize; +} + +/*! + * @brief Enables the USART's IrDA mode. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_EnableIrDA(USART_T* usart) +{ + usart->CTRL3_B.IREN = BIT_SET; +} + +/*! + * @brief Disables the USART's IrDA mode. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_DisableIrDA(USART_T* usart) +{ + usart->CTRL3_B.IREN = BIT_RESET; +} + +/*! + * @brief Configures the USART's IrDA interface. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3. + * + * @param IrDAMode:Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_IRDA_MODE_NORMAL: Normal + * @arg USART_IRDA_MODE_LOWPOWER: Low-Power + * + * @retval None + * + * @note It's not for APM32F030 devices. + * The USART2 only for APM32F072 and APM32F091 devices. + * The USART3 only for APM32F091 devices. + */ +void USART_ConfigIrDAMode(USART_T* usart, USART_IRDA_MODE_T IrDAMode) +{ + usart->CTRL3_B.IRLPEN = IrDAMode; +} + +/*! + * @brief Configure the the USART Address detection length. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param address: Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_ADDRESS_MODE_4B: 4-bit address length detection + * @arg USART_ADDRESS_MODE_7B: 7-bit address length detection + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ConfigAddressDetection(USART_T* usart, USART_ADDRESS_MODE_T address) +{ + usart->CTRL2_B.ADDRLEN = address; +} + +/*! + * @brief Enables the DE functionality + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableDE(USART_T* usart) +{ + usart->CTRL3_B.DEN = BIT_SET; +} + +/*! + * @brief Disables the DE functionality + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableDE(USART_T* usart) +{ + usart->CTRL3_B.DEN = BIT_RESET; +} + +/*! + * @brief Selects the USART WakeUp method from mute mode + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param polarity: Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_DE_POL_HIGH: DE signal is active high + * @arg USART_DE_POL_LOW: DE signal is active low + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ConfigDEPolarity(USART_T* usart, USART_DE_POL_T polarity) +{ + usart->CTRL3_B.DPCFG = polarity; +} + +/*! + * @brief Sets the driver enable assertion time value + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param value: Specifies the DE assertion time value + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DEAssertionTimeValue(USART_T* usart, uint8_t value) +{ + usart->CTRL1_B.DLTEN = (uint8_t)0x00; + + if (value <= (uint8_t)0x1F) + { + usart->CTRL1_B.DLTEN = ((uint8_t)value & 0x1F); + } +} + +/*! + * @brief Sets the driver enable deassertion time value + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param value: Specifies the DE deassertion time value + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DEDeassertionTimeValue(USART_T* usart, uint8_t value) +{ + usart->CTRL1_B.DDLTEN = (uint8_t)0x00; + + if (value <= (uint8_t)0x1F) + { + usart->CTRL1_B.DDLTEN = ((uint8_t)value & 0x1F); + } +} + +/*! + * @brief Enables the USART DMA interface + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param dmaReq: Specifies the DMA request + * This parameter can be any combination of the following values: + * @arg USART_DMA_REQUEST_RX: USART DMA receive request + * @arg USART_DMA_REQUEST_TX: USART DMA transmit request + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableDMA(USART_T* usart, uint32_t dmaReq) +{ + if (dmaReq == USART_DMA_REQUEST_RX) + { + usart->CTRL3_B.DMARXEN = BIT_SET; + } + else if (dmaReq == USART_DMA_REQUEST_TX) + { + usart->CTRL3_B.DMATXEN = BIT_SET; + } + else if (dmaReq == (BIT6 | BIT7)) + { + usart->CTRL3_B.DMATXEN = BIT_SET; + usart->CTRL3_B.DMARXEN = BIT_SET; + } +} + +/*! + * @brief Disables the USART DMA interface + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param dmaReq: Specifies the DMA request + * This parameter can be any combination of the following values: + * @arg USART_DMA_REQUEST_RX: USART DMA receive request + * @arg USART_DMA_REQUEST_TX: USART DMA transmit request + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableDMA(USART_T* usart, uint32_t dmaReq) +{ + if (dmaReq == USART_DMA_REQUEST_RX) + { + usart->CTRL3_B.DMARXEN = BIT_RESET; + } + else if (dmaReq == USART_DMA_REQUEST_TX) + { + usart->CTRL3_B.DMATXEN = BIT_RESET; + } + else if (dmaReq == (BIT6 | BIT7)) + { + usart->CTRL3_B.DMATXEN = BIT_RESET; + usart->CTRL3_B.DMARXEN = BIT_RESET; + } +} + +/*! + * @brief Enables or disables the USART DMA interface when reception error occurs + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param dmaReq: Specifies the DMA request + * This parameter can be one of the following values: + * @arg USART_DMA_RXERR_ENABLE: DMA receive request enabled + * @arg USART_DMA_RXERR_DISABLE: DMA receive request disabled + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ConfigDMAReceptionError(USART_T* usart, USART_DMA_RXERR_T error) +{ + usart->CTRL3_B.DDISRXEEN = error; +} + +/*! + * @brief Enables the specified interrupts + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_WAKEUP: Wake up interrupt (Not for APM32F030 devices) + * @arg USART_INT_CMIE: Character match interrupt + * @arg USART_INT_EOBIE: End of Block interrupt + * @arg USART_INT_RXTOIE: Receive time out interrupt + * @arg USART_INT_CTSIE: CTS change interrupt + * @arg USART_INT_LBDIE: LIN Break detection interrupt (Not for APM32F030 devices) + * @arg USART_INT_TXBEIE: Tansmit Data Register empty interrupt + * @arg USART_INT_TXCIE: Transmission complete interrupt + * @arg USART_INT_RXBNEIE: Receive Data register not empty interrupt + * @arg USART_INT_IDLEIE: Idle line detection interrupt + * @arg USART_INT_PEIE: Parity Error interrupt + * @arg USART_INT_ERRIE: Error interrupt + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt) +{ + if ((interrupt == USART_INT_ERRIE) | (interrupt == USART_INT_CTSIE) | (interrupt == USART_INT_WAKEUP)) + { + usart->CTRL3 |= (uint32_t)interrupt; + } + else if (interrupt == USART_INT_LBDIE) + { + usart->CTRL2 |= (uint32_t)interrupt; + } + else + { + usart->CTRL1 |= (uint32_t)interrupt; + } +} + +/*! + * @brief Disables the specified interrupts + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_WAKEUP: Wake up interrupt (Not for APM32F030 devices) + * @arg USART_INT_CMIE: Character match interrupt + * @arg USART_INT_EOBIE: End of Block interrupt + * @arg USART_INT_RXTOIE: Receive time out interrupt + * @arg USART_INT_CTSIE: CTS change interrupt + * @arg USART_INT_LBDIE: LIN Break detection interrupt (Not for APM32F030 devices) + * @arg USART_INT_TXBEIE: Tansmit Data Register empty interrupt + * @arg USART_INT_TXCIE: Transmission complete interrupt + * @arg USART_INT_RXBNEIE: Receive Data register not empty interrupt + * @arg USART_INT_IDLEIE: Idle line detection interrupt + * @arg USART_INT_PEIE: Parity Error interrupt + * @arg USART_INT_ERRIE: Error interrupt + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt) +{ + if ((interrupt == USART_INT_ERRIE) | (interrupt == USART_INT_CTSIE) | (interrupt == USART_INT_WAKEUP)) + { + usart->CTRL3 &= (uint32_t)~interrupt; + } + else if (interrupt == USART_INT_LBDIE) + { + usart->CTRL2 &= (uint32_t)~interrupt; + } + else + { + usart->CTRL1 &= (uint32_t)~interrupt; + } +} + +/*! + * @brief Enables the specified USART's Request. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param request: specifies the USART request + * This parameter can be one of the following values: + * @arg USART_REQUEST_ABRQ: Auto Baud Rate Request + * @arg USART_REQUEST_SBQ: Send Break Request + * @arg USART_REQUEST_MMQ: Mute Mode Request + * @arg USART_REQUEST_RDFQ: Receive data flush Request + * @arg USART_REQUEST_TDFQ: Transmit data flush Request + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_EnableRequest(USART_T* usart, USART_REQUEST_T request) +{ + if (request == USART_REQUEST_ABRQ) + { + usart->REQUEST_B.ABRDQ = BIT_SET; + } + + if (request == USART_REQUEST_SBQ) + { + usart->REQUEST_B.TXBFQ = BIT_SET; + } + + if (request == USART_REQUEST_MMQ) + { + usart->REQUEST_B.MUTEQ = BIT_SET; + } + + if (request == USART_REQUEST_RDFQ) + { + usart->REQUEST_B.RXDFQ = BIT_SET; + } + + if (request == USART_REQUEST_TDFQ) + { + usart->REQUEST_B.TXDFQ = BIT_SET; + } +} + +/*! + * @brief Disables the specified USART's Request. + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param request: specifies the USART request + * This parameter can be one of the following values: + * @arg USART_REQUEST_ABRQ: Auto Baud Rate Request + * @arg USART_REQUEST_SBQ: Send Break Request + * @arg USART_REQUEST_MMQ: Mute Mode Request + * @arg USART_REQUEST_RDFQ: Receive data flush Request + * @arg USART_REQUEST_TDFQ: Transmit data flush Request + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_DisableRequest(USART_T* usart, USART_REQUEST_T request) +{ + if (request == USART_REQUEST_ABRQ) + { + usart->REQUEST_B.ABRDQ = BIT_RESET; + } + + if (request == USART_REQUEST_SBQ) + { + usart->REQUEST_B.TXBFQ = BIT_RESET; + } + + if (request == USART_REQUEST_MMQ) + { + usart->REQUEST_B.MUTEQ = BIT_RESET; + } + + if (request == USART_REQUEST_RDFQ) + { + usart->REQUEST_B.RXDFQ = BIT_RESET; + } + + if (request == USART_REQUEST_TDFQ) + { + usart->REQUEST_B.TXDFQ = BIT_RESET; + } +} + +/*! + * @brief Enables or disables the USART DMA interface when reception error occurs + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param overDetection: specifies the OVR detection status in case of OVR error + * This parameter can be one of the following values: + * @arg USART_OVER_DETECTION_ENABLE: OVR error detection enabled + * @arg USART_OVER_DETECTION_DISABLE: OVR error detection disabled + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ConfigOverrunDetection(USART_T* usart, USART_OVER_DETECTION_T overDetection) +{ + usart->CTRL3_B.OVRDEDIS = overDetection; +} + +/*! + * @brief Read the specified USART flag + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param flag: Specifies the flag to check + * The parameter can be one of following values: + * @arg USART_FLAG_RXENACKF: Receive Enable Acknowledge Flag + * @arg USART_FLAG_TXENACKF: Transmit Enable Acknowledge Flag + * @arg USART_FLAG_WAKEUP: Wake Up from stop mode Flag (Not for APM32F030 devices) + * @arg USART_FLAG_RWF: Send Break flag (Not for APM32F030 devices) + * @arg USART_FLAG_SBF: Send Break flag + * @arg USART_FLAG_CMF: Character match flag + * @arg USART_FLAG_BUSY: Busy flag + * @arg USART_FLAG_ABRTF: Auto baud rate flag + * @arg USART_FLAG_ABRTE: Auto baud rate error flag + * @arg USART_FLAG_EOBF: End of block flag (Not for APM32F030 devices) + * @arg USART_FLAG_RXTOF: Receive time out flag + * @arg USART_FLAG_CTSF: CTS Change flag + * @arg USART_FLAG_CTSIF: CTS interrupt flag + * @arg USART_FLAG_LBDF LIN Break Detection Flag (Not for APM32F030 devices) + * @arg USART_FLAG_TXBE: Transmit data register empty flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * @arg USART_FLAG_IDLEF: Idle Line detection flag + * @arg USART_FLAG_OVRE: OverRun Error flag + * @arg USART_FLAG_NEF: Noise Error flag + * @arg USART_FLAG_FEF: Framing Error flag + * @arg USART_FLAG_PEF: Parity Error flag + * + * @retval The new state of flag (SET or RESET) + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ + +uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag) +{ + if ((usart->STS & (uint32_t)flag) != RESET) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clear the specified USART flag + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param flag: Specifies the flag to clear + * The parameter can be any combination of following values: + * @arg USART_FLAG_WAKEUP: Wake Up from stop mode Flag (Not for APM32F030 devices) + * @arg USART_FLAG_CMF: Character match flag + * @arg USART_FLAG_EOBF: End of block flag (Not for APM32F030 devices) + * @arg USART_FLAG_RXTOF: Receive time out flag + * @arg USART_FLAG_CTSIF: CTS interrupt flag + * @arg USART_FLAG_LBDF LIN Break Detection Flag (Not for APM32F030 devices) + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_IDLEF: Idle Line detection flag + * @arg USART_FLAG_OVRE: OverRun Error flag + * @arg USART_FLAG_NEF: Noise Error flag + * @arg USART_FLAG_FEF: Framing Error flag + * @arg USART_FLAG_PEF: Parity Error flag + * + * @retval Note + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ + +void USART_ClearStatusFlag(USART_T* usart, uint32_t flag) +{ + usart->INTFCLR = (uint32_t)flag; +} + +/*! + * @brief Read the specified USART interrupt flag + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param flag: Specifies the USART interrupt flag to check + * The parameter can be one of following values: + * @arg USART_INT_FLAG_WAKEUP: Wake up interrupt flag (Not for APM32F030 devices) + * @arg USART_INT_FLAG_CMF: Character match interrupt flag + * @arg USART_INT_FLAG_EOBF: End of block interrupt flag Not for APM32F030 devices) + * @arg USART_INT_FLAG_RXTOF: Receive time out interrupt flag + * @arg USART_INT_FLAG_CTSIF: CTS interrupt flag + * @arg USART_INT_FLAG_LBDF: LIN Break detection interrupt flag (Not for APM32F030 devices) + * @arg USART_INT_FLAG_TXBE: Transmit data register empty interrupt flag + * @arg USART_INT_FLAG_TXC: Transmission Complete interrupt flag + * @arg USART_INT_FLAG_RXBNE: Receive data buffer not empty interrupt flag + * @arg USART_INT_FLAG_IDLE: Idle Line detection interrupt flag + * @arg USART_INT_FLAG_OVRE: OverRun Error interrupt flag + * @arg USART_INT_FLAG_NE: Noise Error interrupt flag + * @arg USART_INT_FLAG_FE: Framing Error interrupt flag + * @arg USART_INT_FLAG_PE: Parity Error interrupt flag + * + * @retval The new state of flag (SET or RESET) + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ + +uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_FLAG_T flag) +{ + uint32_t intEnable = 0; + uint32_t intFlag = 0; + + if (flag & 0x0E) + { + intEnable = usart->CTRL3_B.ERRIEN; + intFlag = (usart->STS) & flag; + } + else if (flag & 0xF0) + { + intEnable = (usart->CTRL1)& flag; + intFlag = (usart->STS) & flag; + } + else if (flag & 0x01) + { + intEnable = usart->CTRL1_B.PEIEN; + intFlag = usart->STS_B.PEFLG; + } + else if (flag & 0x200) + { + intEnable = usart->CTRL3_B.CTSIEN; + intFlag = usart->STS_B.CTSFLG; + } + else if (flag & 0x100) + { + intEnable = usart->CTRL2_B.LBDIEN; + intFlag = usart->STS_B.LBDFLG; + } + else if (flag & 0x800) + { + intEnable = usart->CTRL1_B.RXTOIEN; + intFlag = usart->STS_B.RXTOFLG; + } + else if (flag & 0x1000) + { + intEnable = usart->CTRL1_B.EOBIEN; + intFlag = usart->STS_B.EOBFLG; + } + else if (flag & 0x20000) + { + intEnable = usart->CTRL1_B.CMIEN; + intFlag = usart->STS_B.CMFLG; + } + else if (flag & 0x100000) + { + intEnable = usart->CTRL3_B.WSMIEN; + intFlag = usart->STS_B.WSMFLG; + } + + if (intFlag && intEnable) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the USART interrupt pending bits + * + * @param usart: Select the the USART peripheral. + * It can be USART1/USART2/USART3/USART4/USART5/USART6/USART7/USART8. + * + * @param flag: Specifies the USART interrupt flag to clear + * The parameter can be any combination following values: + * @arg USART_INT_FLAG_WAKEUP: Wake up interrupt flag (Not for APM32F030 devices) + * @arg USART_INT_FLAG_CMF: Character match interrupt flag + * @arg USART_INT_FLAG_EOBF: End of block interrupt flag (Not for APM32F030 devices) + * @arg USART_INT_FLAG_RXTOF: Receive time out interrupt flag + * @arg USART_INT_FLAG_CTSIF: CTS interrupt flag + * @arg USART_INT_FLAG_LBDF: LIN Break detection interrupt flag (Not for APM32F030 devices) + * @arg USART_INT_FLAG_TXC: Transmission Complete interrupt flag + * @arg USART_INT_FLAG_IDLE: Idle Line detection interrupt flag + * @arg USART_INT_FLAG_OVRE: OverRun Error interrupt flag + * @arg USART_INT_FLAG_NE: Noise Error interrupt flag + * @arg USART_INT_FLAG_FE: Framing Error interrupt flag + * @arg USART_INT_FLAG_PE: Parity Error interrupt flag + * + * @retval None + * + * @note The USART3/USART4 only for APM32F072 and APM32F091 devices. + * USART5, USART6, USART7 and USART8 are available only for APM32F091 devices. + */ +void USART_ClearIntFlag(USART_T* usart, uint32_t flag) +{ + usart->INTFCLR |= (uint32_t)flag; +} + +/**@} end of group USART_Functions*/ +/**@} end of group USART_Driver*/ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_wwdt.c b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_wwdt.c new file mode 100644 index 0000000000..2daba3150f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/apm32f0xx_wwdt.c @@ -0,0 +1,175 @@ +/*! + * @file apm32f0xx_wwdt.c + * + * @brief This file contains all the functions for the WWDG peripheral + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f0xx_wwdt.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup APM32F0xx_StdPeriphDriver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @defgroup WWDT_Macros Macros + @{ +*/ + +/**@} end of group WWDT_Macros */ + +/** @defgroup WWDT_Enumerations Enumerations + @{ +*/ + +/**@} end of group WWDT_Enumerations */ + +/** @defgroup WWDT_Structures Structures + @{ +*/ + +/**@} end of group WWDT_Structures */ + +/** @defgroup WWDT_Variables Variables + @{ +*/ + +/**@} end of group WWDT_Variables */ + +/** @defgroup WWDT_Functions Functions + @{ +*/ + +/*! + * @brief Set the WWDT peripheral registers to their default reset values + * + * @param None + + * @retval None + */ +void WWDT_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT); +} + +/*! + * @brief Set the WWDT Timebase + * + * @param timebase: WWDT Prescaler + * The parameter can be one of following values: + * @arg WWDT_DIV_1: WWDT counter clock = (PCLK1/4096)/1 + * @arg WWDT_DIV_2: WWDT counter clock = (PCLK1/4096)/2 + * @arg WWDT_DIV_4: WWDT counter clock = (PCLK1/4096)/4 + * @arg WWDT_DIV_8: WWDT counter clock = (PCLK1/4096)/8 + * + * @retval None + */ +void WWDT_SetTimebase(uint32_t div) +{ + WWDT->CFG_B.TBPSC = 0; + WWDT->CFG_B.TBPSC = div; +} + +/*! + * @brief Set the Window data + * + * @param data: Specifies the window data to be set + * + * @retval None + */ +void WWDT_ConfigWindowValue(uint16_t windowValue) +{ + uint32_t reg; + + reg = (windowValue | BIT6) & 0x7f; + + WWDT->CFG_B.WIN = reg; +} + +/*! + * @brief Enable the WWDT Early Wakeup interrupt + * + * @param None + * + * @retval None + */ +void WWDT_EnableEWI(void) +{ + WWDT->CFG_B.EWIEN = SET; +} + +/*! + * @brief Set counter + * + * @param couter: Specifies the counter to be set + * + * @retval None + */ +void WWDT_ConfigCounter(uint8_t couter) +{ + WWDT->CTRL = (uint32_t)(couter & 0x7f); +} + +/*! + * @brief Enable WWDT and set the counter value + * + * @param count: the window watchdog counter value + * + * @retval None + */ +void WWDT_Enable(uint8_t count) +{ + WWDT->CTRL_B.CNT = count; + WWDT->CTRL_B.WWDTEN = SET; +} + +/*! + * @brief Read the Early Wakeup interrupt flag + * + * @param None + * + * @retval the state of the Early Wakeup interrupt flag + */ +uint8_t WWDT_ReadStatusFlag(void) +{ + return (uint8_t)(WWDT->STS); +} + +/*! + * @brief Clear the Early Wakeup interrupt flag + * + * @param None + * + * @retval None + */ +void WWDT_ClearStatusFlag(void) +{ + WWDT->STS_B.EWIFLG = RESET; +} + +/**@} end of group WWDT_Functions*/ +/**@} end of group WWDT_Driver */ +/**@} end of group APM32F0xx_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cm0plus.h b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..5cea74e9af --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,793 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cmFunc.h b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..0a18fafc30 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cmInstr.h b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..d213f0eed7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/LICENSE.txt b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/LICENSE.txt new file mode 100644 index 0000000000..f0cd2d9ccf --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/CMSIS/LICENSE.txt @@ -0,0 +1,176 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F0XX_H +#define __APM32F0XX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup CMSIS + @{ +*/ + +/** @addtogroup APM32F0xx + * @brief Peripheral Access Layer + @{ +*/ +#if defined (APM32F030x6) || defined (APM32F030x8) || defined (APM32F030xC) +#define APM32F030 +#endif /*!< APM32F030x6 or APM32F030x8 or APM32F030xC */ + +#if defined (APM32F051x6) || defined (APM32F051x8) +#define APM32F051 +#endif /*!< APM32F051x6 or APM32F051x8 */ + +#if defined (APM32F070xB) +#define APM32F070 +#endif /*!< APM32F070xB */ + +#if defined (APM32F071x8) || defined (APM32F071xB) +#define APM32F071 +#endif /*!< APM32F071x8 or APM32F071xB */ + +#if defined (APM32F072x8) || defined (APM32F072xB) +#define APM32F072 +#endif /*!< APM32F072x8 or APM32F072xB */ + +#if defined (APM32F091xB) || defined (APM32F091xC) +#define APM32F091 +#endif /*!< APM32F091xB or APM32F091xC */ + +#if !defined (APM32F030) && !defined (APM32F051) && !defined (APM32F070) && \ + !defined (APM32F071) && !defined (APM32F072) && !defined (APM32F091) +#error "Please select first the target APM32F0xx device used in your application (in apm32f0xx.h file)" +#endif + +/** @defgroup HSE_Macros + @{ +*/ + +/** + * @brief Define Value of the External oscillator in Hz + */ +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) +#endif + +/* Time out for HSE start up */ +#define HSE_STARTUP_TIMEOUT ((uint32_t)0x10000) + +/* Time out for HSI start up */ +#define HSI_STARTUP_TIMEOUT ((uint32_t)0x0500) + +/* Value of the Internal oscillator in Hz */ +#define HSI_VALUE ((uint32_t)8000000) +#define HSI14_VALUE ((uint32_t)14000000) +#define HSI48_VALUE ((uint32_t)48000000) + +#define LSE_VALUE ((uint32_t)32768) +#define LSI_VALUE ((uint32_t)40000) + +/**@} end of group HSE_Macros */ + +/** @defgroup APM32F0xx_StdPeripheral_Library_Version + @{ +*/ + +/*!< [31:16] APM32F0XX Standard Peripheral Library main version V1.0.3*/ +#define __APM32F0_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __APM32F0_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __APM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __APM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __APM32F0_DEVICE_VERSION ((__APM32F0_DEVICE_VERSION_MAIN << 24)\ + |(__APM32F0_DEVICE_VERSION_SUB1 << 16)\ + |(__APM32F0_DEVICE_VERSION_SUB2 << 8 )\ + |(__APM32F0_DEVICE_VERSION_RC)) + +/**@} end of group APM32F0xx_StdPeripheral_Library_Version */ + +/** @defgroup Configuraion_for_CMSIS + @{ +*/ + +/* Core Revision r0p1 */ +#define __CM0PLUS_REV 0 +/* APM32F0xx do not provide MPU */ +#define __MPU_PRESENT 0 +/* APM32F0xx uses 2 Bits for the Priority Levels */ +#define __NVIC_PRIO_BITS 2 +/* Set to 1 if different SysTick Config is used */ +#define __Vendor_SysTickConfig 0 +/* Set to 1 if different Vector Table Offset is used */ +#define __VTOR_PRESENT 1 + +/** + * @brief Interrupt Number Definition + */ +typedef enum +{ + /* Cortex-M0 Processor Exceptions Numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +#if defined (APM32F030) + /* APM32F030 specific Interrupt Numbers */ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EINT Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCM_IRQn = 4, /*!< RCM global Interrupt */ + EINT0_1_IRQn = 5, /*!< EINT Line 0 and 1 Interrupt */ + EINT2_3_IRQn = 6, /*!< EINT Line 2 and 3 Interrupt */ + EINT4_15_IRQn = 7, /*!< EINT Line 4 to 15 Interrupt */ + DMA1_CH1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_CH2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_CH4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TMR1_BRK_UP_TRG_COM_IRQn = 13, /*!< TMR1 Break, Update, Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 14, /*!< TMR1 Capture Compare Interrupt */ + TMR3_IRQn = 16, /*!< TMR3 global Interrupt */ + TMR6_IRQn = 17, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 18, /*!< TMR7 global Interrupt */ + TMR14_IRQn = 19, /*!< TMR14 global Interrupt */ + TMR15_IRQn = 20, /*!< TMR15 global Interrupt */ + TMR16_IRQn = 21, /*!< TMR16 global Interrupt */ + TMR17_IRQn = 22, /*!< TMR17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_6_IRQn = 29 /*!< USART3 to USART6 global Interrupt */ +#elif defined (APM32F051) + /* APM32F051 specific Interrupt Numbers */ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EINT Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCM_IRQn = 4, /*!< RCM global Interrupt */ + EINT0_1_IRQn = 5, /*!< EINT Line 0 and 1 Interrupt */ + EINT2_3_IRQn = 6, /*!< EINT Line 2 and 3 Interrupt */ + EINT4_15_IRQn = 7, /*!< EINT Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_CH1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_CH2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_CH4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ + ADC1_COMP_IRQn = 12, /*!< ADC1 and comparator Interrupt */ + TMR1_BRK_UP_TRG_COM_IRQn = 13, /*!< TMR1 Break, Update, Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 14, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 15, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 16, /*!< TMR3 global Interrupt */ + TMR6_DAC_IRQn = 17, /*!< TMR6 and DAC Interrupt */ + TMR14_IRQn = 19, /*!< TMR14 global Interrupt */ + TMR15_IRQn = 20, /*!< TMR15 global Interrupt */ + TMR16_IRQn = 21, /*!< TMR16 global Interrupt */ + TMR17_IRQn = 22, /*!< TMR17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + CEC_IRQn = 30 /*!< CEC global Interrupt */ +#elif defined (APM32F070) + /* APM32F070 specific Interrupt Numbers */ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EINT Lines */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCM_IRQn = 4, /*!< RCM global Interrupt */ + EINT0_1_IRQn = 5, /*!< EINT Line 0 and 1 Interrupt */ + EINT2_3_IRQn = 6, /*!< EINT Line 2 and 3 Interrupt */ + EINT4_15_IRQn = 7, /*!< EINT Line 4 to 15 Interrupt */ + DMA1_CH1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_CH2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_CH4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TMR1_BRK_UP_TRG_COM_IRQn = 13, /*!< TMR1 Break, Update, Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 14, /*!< TMR1 Capture Compare Interrupt */ + TMR3_IRQn = 16, /*!< TMR3 global Interrupt */ + TMR6_IRQn = 17, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 18, /*!< TMR7 global Interrupt */ + TMR14_IRQn = 19, /*!< TMR14 global Interrupt */ + TMR15_IRQn = 20, /*!< TMR15 global Interrupt */ + TMR16_IRQn = 21, /*!< TMR16 global Interrupt */ + TMR17_IRQn = 22, /*!< TMR17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ + USBD_IRQn = 31 /*!< USB Low Priority global Interrupt */ +#elif defined (APM32F071) + /* APM32F071 specific Interrupt Numbers */ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EINT Lines */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCM_CRS_IRQn = 4, /*!< RCM and CRS global Interrupt */ + EINT0_1_IRQn = 5, /*!< EINT Line 0 and 1 Interrupt */ + EINT2_3_IRQn = 6, /*!< EINT Line 2 and 3 Interrupt */ + EINT4_15_IRQn = 7, /*!< EINT Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_CH1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_CH2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_CH4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1 and comparator Interrupt */ + TMR1_BRK_UP_TRG_COM_IRQn = 13, /*!< TMR1 Break, Update, Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 14, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 15, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 16, /*!< TMR3 global Interrupt */ + TMR6_DAC_IRQn = 17, /*!< TMR6 and DAC Interrupt */ + TMR7_IRQn = 18, /*!< TMR7 global Interrupt */ + TMR14_IRQn = 19, /*!< TMR14 global Interrupt */ + TMR15_IRQn = 20, /*!< TMR15 global Interrupt */ + TMR16_IRQn = 21, /*!< TMR16 global Interrupt */ + TMR17_IRQn = 22, /*!< TMR17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ + CEC_IRQn = 30 /*!< CEC global Interrupt */ +#elif defined (APM32F072) + /* APM32F072 specific Interrupt Numbers */ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EINT Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCM_CRS_IRQn = 4, /*!< RCM and CRS global Interrupt */ + EINT0_1_IRQn = 5, /*!< EINT Line 0 and 1 Interrupt */ + EINT2_3_IRQn = 6, /*!< EINT Line 2 and 3 Interrupt */ + EINT4_15_IRQn = 7, /*!< EINT Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_CH1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_CH2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_CH4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1 and comparator Interrupt */ + TMR1_BRK_UP_TRG_COM_IRQn = 13, /*!< TMR1 Break, Update, Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 14, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 15, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 16, /*!< TMR3 global Interrupt */ + TMR6_DAC_IRQn = 17, /*!< TMR6 and DAC Interrupt */ + TMR7_IRQn = 18, /*!< TMR7 global Interrupt */ + TMR14_IRQn = 19, /*!< TMR14 global Interrupt */ + TMR15_IRQn = 20, /*!< TMR15 global Interrupt */ + TMR16_IRQn = 21, /*!< TMR16 global Interrupt */ + TMR17_IRQn = 22, /*!< TMR17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupt */ + USBD_IRQn = 31 /*!< USB Low Priority global Interrupt */ +#elif defined (APM32F091) + /* APM32F091 specific Interrupt Numbers */ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 Interrupt */ + RTC_IRQn = 2, /*!< RTC Interrupt through EINT Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCM_CRS_IRQn = 4, /*!< RCM and CRS global Interrupt */ + EINT0_1_IRQn = 5, /*!< EINT Line 0 and 1 Interrupt */ + EINT2_3_IRQn = 6, /*!< EINT Line 2 and 3 Interrupt */ + EINT4_15_IRQn = 7, /*!< EINT Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_CH1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_CH2_3_DMA2_CH1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 DMA2 Channel 1 and 2 Interrupts */ + DMA1_CH4_7_DMA2_CH3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 DMA2 Channel 3 to 5 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1 and comparator Interrupt */ + TMR1_BRK_UP_TRG_COM_IRQn = 13, /*!< TMR1 Break, Update, Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 14, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 15, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 16, /*!< TMR3 global Interrupt */ + TMR6_DAC_IRQn = 17, /*!< TMR6 and DAC Interrupt */ + TMR7_IRQn = 18, /*!< TMR7 global Interrupt */ + TMR14_IRQn = 19, /*!< TMR14 global Interrupt */ + TMR15_IRQn = 20, /*!< TMR15 global Interrupt */ + TMR16_IRQn = 21, /*!< TMR16 global Interrupt */ + TMR17_IRQn = 22, /*!< TMR17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_8_IRQn = 29, /*!< USART3 and USART8 global Interrupt */ + CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupt */ +#endif +} IRQn_Type; + +/**@} end of group Configuraion_for_CMSIS */ + +/* Includes */ + +#include "core_cm0plus.h" /*!< Cortex-M0+ processor and core peripherals */ +#include "system_apm32f0xx.h" /*!< APM32F0xx System Header */ +#include + +/** @defgroup Exported_types + * @{ +*/ + +typedef enum {FALSE, TRUE} BOOL; + +enum {BIT_RESET, BIT_SET}; + +enum {RESET = 0, SET = !RESET}; + +enum {DISABLE = 0, ENABLE = !DISABLE}; + +enum {ERROR = 0, SUCCESS = !ERROR}; + +#ifndef __IM +#define __IM __I +#endif +#ifndef __OM +#define __OM __O +#endif +#ifndef __IOM +#define __IOM __IO +#endif + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#if defined (__CC_ARM ) +#pragma anon_unions +#endif + +/**@} end of group Exported_types */ + +/** @defgroup Peripheral_registers_structures + @{ +*/ + + +/** + * @brief Analog-to-digital converter (ADC) + */ + +typedef struct +{ + /* interrupt and status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t ADCRDYFLG : 1; + __IOM uint32_t EOSMPFLG : 1; + __IOM uint32_t EOCFLG : 1; + __IOM uint32_t EOSEQFLG : 1; + __IOM uint32_t OVREFLG : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t AWDFLG : 1; + __IM uint32_t RESERVED2 : 24; + } STS_B; + } ; + + /* interrupt enable register */ + union + { + __IOM uint32_t INT; + + struct + { + __IOM uint32_t ADCRDYIEN : 1; + __IOM uint32_t EOSMPIEN : 1; + __IOM uint32_t EOCIEN : 1; + __IOM uint32_t EOSEQIEN : 1; + __IOM uint32_t OVRIEN : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t AWDIEN : 1; + __IM uint32_t RESERVED2 : 24; + } INT_B; + } ; + + /* control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t ADCEN : 1; + __IOM uint32_t ADCD : 1; + __IOM uint32_t STARTCEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t STOPCEN : 1; + __IM uint32_t RESERVED2 : 26; + __IOM uint32_t CAL : 1; + } CTRL_B; + } ; + + /* configuration register 1 */ + union + { + __IOM uint32_t CFG1; + + struct + { + __IOM uint32_t DMAEN : 1; + __IOM uint32_t DMACFG : 1; + __IOM uint32_t SCANSEQDIR : 1; + __IOM uint32_t DATARESCFG : 2; + __IOM uint32_t DALIGCFG : 1; + __IOM uint32_t EXTTRGSEL : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t EXTPOLSEL : 2; + __IOM uint32_t OVRMAG : 1; + __IOM uint32_t CMODESEL : 1; + __IOM uint32_t WAITCEN : 1; + __IOM uint32_t AOEN : 1; + __IOM uint32_t DISCEN : 1; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t AWDCHEN : 1; + __IOM uint32_t AWDEN : 1; + __IM uint32_t RESERVED3 : 2; + __IOM uint32_t AWDCHSEL : 5; + __IM uint32_t RESERVED4 : 1; + } CFG1_B; + } ; + + /* configuration register 2 */ + union + { + __IOM uint32_t CFG2; + + struct + { + __IM uint32_t RESERVED1 : 30; + __IOM uint32_t CLKCFG : 2; + } CFG2_B; + } ; + + /* sampling time register */ + union + { + __IOM uint32_t SMPTIM; + + struct + { + __IOM uint32_t SMPCYCSEL : 3; + __IM uint32_t RESERVED1 : 29; + } SMPTIM_B; + } ; + __IM uint32_t RESERVED[2]; + + /* watchdog threshold register */ + union + { + __IOM uint32_t AWDT; + + struct + { + __IOM uint32_t AWDLT : 12; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t AWDHT : 12; + __IM uint32_t RESERVED2 : 4; + } AWDT_B; + } ; + __IM uint32_t RESERVED1; + + /* channel selection register */ + union + { + __IOM uint32_t CHSEL; + + struct + { + __IOM uint32_t CH0SEL : 1; + __IOM uint32_t CH1SEL : 1; + __IOM uint32_t CH2SEL : 1; + __IOM uint32_t CH3SEL : 1; + __IOM uint32_t CH4SEL : 1; + __IOM uint32_t CH5SEL : 1; + __IOM uint32_t CH6SEL : 1; + __IOM uint32_t CH7SEL : 1; + __IOM uint32_t CH8SEL : 1; + __IOM uint32_t CH9SEL : 1; + __IOM uint32_t CH10SEL : 1; + __IOM uint32_t CH11SEL : 1; + __IOM uint32_t CH12SEL : 1; + __IOM uint32_t CH13SEL : 1; + __IOM uint32_t CH14SEL : 1; + __IOM uint32_t CH15SEL : 1; + __IOM uint32_t CH16SEL : 1; + __IOM uint32_t CH17SEL : 1; + __IOM uint32_t CH18SEL : 1; + __IM uint32_t RESERVED1 : 13; + } CHSEL_B; + } ; + __IM uint32_t RESERVED2[5]; + + /* data register */ + union + { + __IM uint32_t DATA; + + struct + { + __IM uint32_t DATA : 16; + __IM uint32_t RESERVED1 : 16; + } DATA_B; + } ; + __IM uint32_t RESERVED3[177]; + + /* common configuration register */ + union + { + __IOM uint32_t CCFG; + + struct + { + __IM uint32_t RESERVED1 : 22; + __IOM uint32_t VREFEN : 1; + __IOM uint32_t TSEN : 1; + __IOM uint32_t VBATEN : 1; + __IM uint32_t RESERVED2 : 7; + } CCFG_B; + } ; +} ADC_T; + +/** + * @brief Controller area network (CAN) TxMailBox Typedef + */ +typedef struct +{ + /* TX mailbox identifier register */ + union + { + __IOM uint32_t TXMID; + + struct + { + __IOM uint32_t TXMREQ : 1; + __IOM uint32_t TXRFREQ : 1; + __IOM uint32_t IDTYPESEL : 1; + __IOM uint32_t EXTID : 18; + __IOM uint32_t STDID : 11; + } TXMID_B; + } ; + + /* Mailbox data length control and time stamp register */ + union + { + __IOM uint32_t TXDLEN; + + struct + { + __IOM uint32_t DLCODE : 4; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t TXGT : 1; + __IM uint32_t RESERVED2 : 7; + __IOM uint32_t MTS : 16; + } TXDLEN_B; + } ; + + /* Mailbox data low register 0*/ + union + { + __IOM uint32_t TXMDL; + + struct + { + __IOM uint32_t DATABYTE0 : 8; + __IOM uint32_t DATABYTE1 : 8; + __IOM uint32_t DATABYTE2 : 8; + __IOM uint32_t DATABYTE3 : 8; + } TXMDL_B; + } ; + + /* Mailbox data high register 0*/ + union + { + __IOM uint32_t TXMDH; + + struct + { + __IOM uint32_t DATABYTE4 : 8; + __IOM uint32_t DATABYTE5 : 8; + __IOM uint32_t DATABYTE6 : 8; + __IOM uint32_t DATABYTE7 : 8; + } TXMDH_B; + } ; + +} CAN_TxMailBox_T; + +/** + * @brief Controller area network (CAN) Receive FIFO MailBox Typedef + */ +typedef struct +{ + /* Receive FIFO mailbox identifier register */ + union + { + __IM uint32_t RXMID; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IM uint32_t RFTXREQ : 1; + __IM uint32_t IDTYPESEL : 1; + __IM uint32_t EXTID : 18; + __IM uint32_t STDID : 11; + } RXMID_B; + } ; + + /* Receive FIFO mailbox data length control and time stamp register */ + union + { + __IM uint32_t RXDLEN; + + struct + { + __IM uint32_t DLCODE : 4; + __IM uint32_t RESERVED1 : 4; + __IM uint32_t FMIDX : 8; + __IM uint32_t MTS : 16; + } RXDLEN_B; + } ; + + /* Receive FIFO mailbox data low register */ + union + { + __IM uint32_t RXMDL; + + struct + { + __IM uint32_t DATABYTE0 : 8; + __IM uint32_t DATABYTE1 : 8; + __IM uint32_t DATABYTE2 : 8; + __IM uint32_t DATABYTE3 : 8; + } RXMDL_B; + } ; + + /* Receive FIFO mailbox data high register */ + union + { + __IM uint32_t RXMDH; + + struct + { + __IM uint32_t DATABYTE4 : 8; + __IM uint32_t DATABYTE5 : 8; + __IM uint32_t DATABYTE6 : 8; + __IM uint32_t DATABYTE7 : 8; + } RXMDH_B; + } ; + +} CAN_RxFIFO_T; + +/** + * @brief Controller area network (CAN) Filter register Typedef + */ +typedef struct +{ + /* CAN Filter1 register */ + union + { + __IOM uint32_t R1; + + struct + { + __IOM uint32_t FBIT0 : 1; + __IOM uint32_t FBIT1 : 1; + __IOM uint32_t FBIT2 : 1; + __IOM uint32_t FBIT3 : 1; + __IOM uint32_t FBIT4 : 1; + __IOM uint32_t FBIT5 : 1; + __IOM uint32_t FBIT6 : 1; + __IOM uint32_t FBIT7 : 1; + __IOM uint32_t FBIT8 : 1; + __IOM uint32_t FBIT9 : 1; + __IOM uint32_t FBIT10 : 1; + __IOM uint32_t FBIT11 : 1; + __IOM uint32_t FBIT12 : 1; + __IOM uint32_t FBIT13 : 1; + __IOM uint32_t FBIT14 : 1; + __IOM uint32_t FBIT15 : 1; + __IOM uint32_t FBIT16 : 1; + __IOM uint32_t FBIT17 : 1; + __IOM uint32_t FBIT18 : 1; + __IOM uint32_t FBIT19 : 1; + __IOM uint32_t FBIT20 : 1; + __IOM uint32_t FBIT21 : 1; + __IOM uint32_t FBIT22 : 1; + __IOM uint32_t FBIT23 : 1; + __IOM uint32_t FBIT24 : 1; + __IOM uint32_t FBIT25 : 1; + __IOM uint32_t FBIT26 : 1; + __IOM uint32_t FBIT27 : 1; + __IOM uint32_t FBIT28 : 1; + __IOM uint32_t FBIT29 : 1; + __IOM uint32_t FBIT30 : 1; + __IOM uint32_t FBIT31 : 1; + } R1_B; + }; + + /* CAN Filter2 register */ + union + { + __IOM uint32_t R2; + + struct + { + __IOM uint32_t FBIT0 : 1; + __IOM uint32_t FBIT1 : 1; + __IOM uint32_t FBIT2 : 1; + __IOM uint32_t FBIT3 : 1; + __IOM uint32_t FBIT4 : 1; + __IOM uint32_t FBIT5 : 1; + __IOM uint32_t FBIT6 : 1; + __IOM uint32_t FBIT7 : 1; + __IOM uint32_t FBIT8 : 1; + __IOM uint32_t FBIT9 : 1; + __IOM uint32_t FBIT10 : 1; + __IOM uint32_t FBIT11 : 1; + __IOM uint32_t FBIT12 : 1; + __IOM uint32_t FBIT13 : 1; + __IOM uint32_t FBIT14 : 1; + __IOM uint32_t FBIT15 : 1; + __IOM uint32_t FBIT16 : 1; + __IOM uint32_t FBIT17 : 1; + __IOM uint32_t FBIT18 : 1; + __IOM uint32_t FBIT19 : 1; + __IOM uint32_t FBIT20 : 1; + __IOM uint32_t FBIT21 : 1; + __IOM uint32_t FBIT22 : 1; + __IOM uint32_t FBIT23 : 1; + __IOM uint32_t FBIT24 : 1; + __IOM uint32_t FBIT25 : 1; + __IOM uint32_t FBIT26 : 1; + __IOM uint32_t FBIT27 : 1; + __IOM uint32_t FBIT28 : 1; + __IOM uint32_t FBIT29 : 1; + __IOM uint32_t FBIT30 : 1; + __IOM uint32_t FBIT31 : 1; + } R2_B; + }; +} CAN_FilterRegister_T; + +/** + * @brief Controller area network (CAN) + */ + +typedef struct +{ + /* Master control register */ + union + { + __IOM uint32_t MCTRL; + + struct + { + __IOM uint32_t INITREQ : 1; + __IOM uint32_t SLEEPREQ : 1; + __IOM uint32_t TXFPCFG : 1; + __IOM uint32_t RXFLOCK : 1; + __IOM uint32_t ARTXMD : 1; + __IOM uint32_t AWUPCFG : 1; + __IOM uint32_t ALBOFFM : 1; + __IOM uint32_t TTCM : 1; + __IM uint32_t RESERVED1 : 7; + __IOM uint32_t SWRST : 1; + __IOM uint32_t DBGFRZE : 1; + __IM uint32_t RESERVED2 : 15; + } MCTRL_B; + } ; + + /* Master status register */ + union + { + __IOM uint32_t MSTS; + + struct + { + __IM uint32_t INITFLG : 1; + __IM uint32_t SLEEPFLG : 1; + __IOM uint32_t ERRIFLG : 1; + __IOM uint32_t WUPIFLG : 1; + __IOM uint32_t SLEEPIFLG : 1; + __IM uint32_t RESERVED1 : 3; + __IM uint32_t TXMFLG : 1; + __IM uint32_t RXMFLG : 1; + __IM uint32_t LSAMVALUE : 1; + __IM uint32_t RXSIGL : 1; + __IM uint32_t RESERVED2 : 20; + } MSTS_B; + } ; + + /* Transmit status register */ + union + { + __IOM uint32_t TXSTS; + + struct + { + __IOM uint32_t REQCFLG0 : 1; + __IOM uint32_t TXSUSFLG0 : 1; + __IOM uint32_t ARBLSTFLG0 : 1; + __IOM uint32_t TXERRFLG0 : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ABREQFLG0 : 1; + __IOM uint32_t REQCFLG1 : 1; + __IOM uint32_t TXSUSFLG1 : 1; + __IOM uint32_t ARBLSTFLG1 : 1; + __IOM uint32_t TXERRFLG1 : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t ABREQFLG1 : 1; + __IOM uint32_t REQCFLG2 : 1; + __IOM uint32_t TXSUSFLG2 : 1; + __IOM uint32_t ARBLSTFLG2 : 1; + __IOM uint32_t TXERRFLG2 : 1; + __IM uint32_t RESERVED3 : 3; + __IOM uint32_t ABREQFLG2 : 1; + __IM uint32_t EMNUM : 2; + __IM uint32_t TXMEFLG0 : 1; + __IM uint32_t TXMEFLG1 : 1; + __IM uint32_t TXMEFLG2 : 1; + __IM uint32_t LOWESTP0 : 1; + __IM uint32_t LOWESTP1 : 1; + __IM uint32_t LOWESTP2 : 1; + } TXSTS_B; + } ; + + /* Receive FIFO 0 register */ + union + { + __IOM uint32_t RXF0; + + struct + { + __IM uint32_t FMNUM0 : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t FFULLFLG0 : 1; + __IOM uint32_t FOVRFLG0 : 1; + __IOM uint32_t RFOM0 : 1; + __IM uint32_t RESERVED2 : 26; + } RXF0_B; + } ; + + /* Receive FIFO 1 register */ + union + { + __IOM uint32_t RXF1; + + struct + { + __IM uint32_t FMNUM1 : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t FFULLFLG1 : 1; + __IOM uint32_t FOVRFLG1 : 1; + __IOM uint32_t RFOM1 : 1; + __IM uint32_t RESERVED2 : 26; + } RXF1_B; + } ; + + /* Interrupt enable register */ + union + { + __IOM uint32_t INTEN; + + struct + { + __IOM uint32_t TXMEIE : 1; + __IOM uint32_t FMIEN0 : 1; + __IOM uint32_t FFULLIEN0 : 1; + __IOM uint32_t FOVRIEN0 : 1; + __IOM uint32_t FMPIEN1 : 1; + __IOM uint32_t FFULLIEN1 : 1; + __IOM uint32_t FOVRIEN1 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t ERRWIEN : 1; + __IOM uint32_t ERRPIEN : 1; + __IOM uint32_t BOFFIEN : 1; + __IOM uint32_t LECIEN : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t WUPIEN : 1; + __IOM uint32_t SLEEPIEN : 1; + __IM uint32_t RESERVED3 : 14; + } INTEN_B; + } ; + + /* Error status register */ + union + { + __IOM uint32_t ERRSTS; + + struct + { + __IM uint32_t ERRWFLG : 1; + __IM uint32_t ERRPFLG : 1; + __IM uint32_t BOFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t LERRC : 3; + __IM uint32_t RESERVED2 : 9; + __IM uint32_t TXERRCNT : 8; + __IM uint32_t RXERRCNT : 8; + } ERRSTS_B; + } ; + + /* Bit timing register */ + union + { + __IOM uint32_t BITTIM; + + struct + { + __IOM uint32_t BRPSC : 10; + __IM uint32_t RESERVED1 : 6; + __IOM uint32_t TIMSEG1 : 4; + __IOM uint32_t TIMSEG2 : 3; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t RSYNJW : 2; + __IM uint32_t RESERVED3 : 4; + __IOM uint32_t LBKMEN : 1; + __IOM uint32_t SILMEN : 1; + } BITTIM_B; + } ; + __IM uint32_t RESERVED1[88]; + + CAN_TxMailBox_T sTxMailBox[3]; + + CAN_RxFIFO_T sRxFIFO[2]; + + __IM uint32_t RESERVED2[12]; + + /* Filter master register */ + union + { + __IOM uint32_t FCTRL; + + struct + { + __IOM uint32_t FIM : 1; + __IM uint32_t RESERVED1 : 31; + } FCTRL_B; + } ; + + /* Filter mode register */ + union + { + __IOM uint32_t FMCFG; + + struct + { + __IOM uint32_t FMCFG0 : 1; + __IOM uint32_t FMCFG1 : 1; + __IOM uint32_t FMCFG2 : 1; + __IOM uint32_t FMCFG3 : 1; + __IOM uint32_t FMCFG4 : 1; + __IOM uint32_t FMCFG5 : 1; + __IOM uint32_t FMCFG6 : 1; + __IOM uint32_t FMCFG7 : 1; + __IOM uint32_t FMCFG8 : 1; + __IOM uint32_t FMCFG9 : 1; + __IOM uint32_t FMCFG10 : 1; + __IOM uint32_t FMCFG11 : 1; + __IOM uint32_t FMCFG12 : 1; + __IOM uint32_t FMCFG13 : 1; + __IM uint32_t RESERVED1 : 18; + } FMCFG_B; + } ; + __IM uint32_t RESERVED3; + + /* Filter scale register */ + union + { + __IOM uint32_t FSCFG; + + struct + { + __IOM uint32_t FSCFG0 : 1; + __IOM uint32_t FSCFG1 : 1; + __IOM uint32_t FSCFG2 : 1; + __IOM uint32_t FSCFG3 : 1; + __IOM uint32_t FSCFG4 : 1; + __IOM uint32_t FSCFG5 : 1; + __IOM uint32_t FSCFG6 : 1; + __IOM uint32_t FSCFG7 : 1; + __IOM uint32_t FSCFG8 : 1; + __IOM uint32_t FSCFG9 : 1; + __IOM uint32_t FSCFG10 : 1; + __IOM uint32_t FSCFG11 : 1; + __IOM uint32_t FSCFG12 : 1; + __IOM uint32_t FSCFG13 : 1; + __IM uint32_t RESERVED1 : 18; + } FSCFG_B; + } ; + __IM uint32_t RESERVED4; + + /* Filter FIFO assignment register */ + union + { + __IOM uint32_t FFASS; + + struct + { + __IOM uint32_t FFASS0 : 1; + __IOM uint32_t FFASS1 : 1; + __IOM uint32_t FFASS2 : 1; + __IOM uint32_t FFASS3 : 1; + __IOM uint32_t FFASS4 : 1; + __IOM uint32_t FFASS5 : 1; + __IOM uint32_t FFASS6 : 1; + __IOM uint32_t FFASS7 : 1; + __IOM uint32_t FFASS8 : 1; + __IOM uint32_t FFASS9 : 1; + __IOM uint32_t FFASS10 : 1; + __IOM uint32_t FFASS11 : 1; + __IOM uint32_t FFASS12 : 1; + __IOM uint32_t FFASS13 : 1; + __IM uint32_t RESERVED1 : 18; + } FFASS_B; + } ; + __IM uint32_t RESERVED5; + + /* Filter activation register */ + union + { + __IOM uint32_t FACT; + + struct + { + __IOM uint32_t FACT0 : 1; + __IOM uint32_t FACT1 : 1; + __IOM uint32_t FACT2 : 1; + __IOM uint32_t FACT3 : 1; + __IOM uint32_t FACT4 : 1; + __IOM uint32_t FACT5 : 1; + __IOM uint32_t FACT6 : 1; + __IOM uint32_t FACT7 : 1; + __IOM uint32_t FACT8 : 1; + __IOM uint32_t FACT9 : 1; + __IOM uint32_t FACT10 : 1; + __IOM uint32_t FACT11 : 1; + __IOM uint32_t FACT12 : 1; + __IOM uint32_t FACT13 : 1; + __IM uint32_t RESERVED1 : 18; + } FACT_B; + } ; + __IM uint32_t RESERVED6[8]; + + /* Filter bank register */ + CAN_FilterRegister_T sFilterRegister[14]; +} CAN_T; + +/** + * @brief HDMI-CEC registers (CEC) + */ + +typedef struct +{ + /* Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t CECEN : 1; + __IOM uint32_t TXSM : 1; + __IOM uint32_t TXEM : 1; + __IM uint32_t RESERVED1 : 29; + } CTRL_B; + } ; + + /* Configuration register */ + union + { + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t SFTCFG : 3; + __IOM uint32_t RXTCFG : 1; + __IOM uint32_t RXSBRERR : 1; + __IOM uint32_t GEBRERR : 1; + __IOM uint32_t GELBPERR : 1; + __IOM uint32_t AEBGIB : 1; + __IOM uint32_t SFTOB : 1; + __IM uint32_t RESERVED1 : 7; + __IOM uint32_t OACFG : 15; + __IOM uint32_t LMODSEL : 1; + } CFG_B; + } ; + + /* Tx data register */ + union + { + __OM uint32_t TXDATA; + + struct + { + __OM uint32_t TXDATA : 8; + __IM uint32_t RESERVED1 : 24; + } TXDATA_B; + } ; + + /* Rx data register */ + union + { + __IM uint32_t RXDATA; + + struct + { + __IM uint32_t RXDATA : 8; + __IM uint32_t RESERVED1 : 24; + } RXDATA_B; + } ; + + /* Interrupt and Status Register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t RXBREFLG : 1; + __IOM uint32_t RXEFLG : 1; + __IOM uint32_t RXOVRFLG : 1; + __IOM uint32_t RXBRERRFLG : 1; + __IOM uint32_t RXSBPEFLG : 1; + __IOM uint32_t RXLBPEFLG : 1; + __IOM uint32_t RXMACKFLG : 1; + __IOM uint32_t ARBLOSFLG : 1; + __IOM uint32_t TXBREFLG : 1; + __IOM uint32_t TXEFLG : 1; + __IOM uint32_t TXBUFLG : 1; + __IOM uint32_t TXERRFLG : 1; + __IOM uint32_t TXMACKFLG : 1; + __IM uint32_t RESERVED1 : 19; + } STS_B; + } ; + + /* interrupt enable register */ + union + { + __IOM uint32_t INTEN; + + struct + { + __IOM uint32_t RXBREIEN : 1; + __IOM uint32_t RXEIEN : 1; + __IOM uint32_t RXOVRIEN : 1; + __IOM uint32_t RXBRERRIEN : 1; + __IOM uint32_t RXSBPEIEN : 1; + __IOM uint32_t RXLBPEIEN : 1; + __IOM uint32_t RXMACKIEN : 1; + __IOM uint32_t ARBLOSIEN : 1; + __IOM uint32_t TXBREIEN : 1; + __IOM uint32_t TXIEN : 1; + __IOM uint32_t TXBUIEN : 1; + __IOM uint32_t TXERRIEN : 1; + __IOM uint32_t TXMACKIEN : 1; + __IM uint32_t RESERVED1 : 19; + } INTEN_B; + } ; +} CEC_T; + +/** + * @brief Cyclic redundancy check calculation unit (CRC) + */ + +typedef struct +{ + /* Data register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 32; + } DATA_B; + } ; + + /* Independent data register */ + union + { + __IOM uint32_t INDATA; + + struct + { + __IOM uint32_t INDATA : 8; + __IM uint32_t RESERVED1 : 24; + } INDATA_B; + } ; + + /* Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t RST : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t POLSIZE : 2; + __IOM uint32_t REVI : 2; + __IOM uint32_t REVO : 1; + __IM uint32_t RESERVED2 : 24; + } CTRL_B; + } ; + __IM uint32_t RESERVED; + + /* Initial CRC value */ + union + { + __IOM uint32_t INITVAL; + + struct + { + __IOM uint32_t VALUE : 32; + } INITVAL_B; + } ; + + /* CRC polynomia register*/ + union + { + __IOM uint32_t POL; + + struct + { + __IOM uint32_t PPOL : 32; + } POL_B; + } ; +} CRC_T; + +/** + * @brief CRS registers (CRS) + */ + +typedef struct +{ + /* Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t SNINTEN : 1; + __IOM uint32_t SWINTEN : 1; + __IOM uint32_t EINTEN : 1; + __IOM uint32_t ESINTEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CNTEN : 1; + __IOM uint32_t AUTOTRMEN : 1; + __IOM uint32_t SWSGNR : 1; + __IOM uint32_t HSI48TRM : 6; + __IM uint32_t RESERVED2 : 18; + } CTRL_B; + } ; + + union + { + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t RLDVAL : 16; + __IOM uint32_t FELMT : 8; + __IOM uint32_t SYNCPSC : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t SYNCSRCSEL : 2; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t SYNCPOLSEL : 1; + } CFG_B; + } ; + + union + { + __IM uint32_t INTSTS; + + struct + { + __IM uint32_t SNFLG : 1; + __IM uint32_t SWFLG : 1; + __IM uint32_t EFLG : 1; + __IM uint32_t ESFLG : 1; + __IM uint32_t RESERVED1 : 4; + __IM uint32_t ERRORFLG : 1; + __IM uint32_t SYNCMISS : 1; + __IM uint32_t TRMFLG : 1; + __IM uint32_t RESERVED2 : 4; + __IM uint32_t CNTDRCT : 1; + __IM uint32_t FECPT : 16; + } INTSTS_B; + } ; + + union + { + __IOM uint32_t INTCLR; + + struct + { + __IOM uint32_t SNCLR : 1; + __IOM uint32_t SWCLR : 1; + __IOM uint32_t ECLR : 1; + __IOM uint32_t ESCLR : 1; + __IM uint32_t RESERVED1 : 28; + } INTCLR_B; + } ; +} CRS_T; + +/** + * @brief Comparator (COMP) + */ + +typedef struct +{ + /* control and status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IOM uint32_t EN1 : 1; + __IOM uint32_t SW1 : 1; + __IOM uint32_t MOD1 : 2; + __IOM uint32_t INVINSEL1 : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t OUTSEL1 : 3; + __IOM uint32_t OPINV1 : 1; + __IOM uint32_t HYSCFG1 : 2; + __IM uint32_t OUTSTS1 : 1; + __IOM uint32_t LOCK1 : 1; + __IOM uint32_t EN2 : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t MOD2 : 2; + __IOM uint32_t INVINSEL2 : 3; + __IOM uint32_t WMODEN : 1; + __IOM uint32_t OUTSEL2 : 3; + __IOM uint32_t OPINV2 : 1; + __IOM uint32_t HYSCFG2 : 2; + __IM uint32_t OUTSTS2 : 1; + __IOM uint32_t LOCK2 : 1; + } CSTS_B; + } ; +} COMP_T; + +/** + * @brief Digital-to-Analog converter (DAC) + */ + +typedef struct +{ + /* Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t ENCH1 : 1; + __IOM uint32_t BUFFDCH1 : 1; + __IOM uint32_t TRGENCH1 : 1; + __IOM uint32_t TRGSELCH1 : 3; + __IOM uint32_t WAVENCH1 : 2; + __IOM uint32_t MAMPSELCH1 : 4; + __IOM uint32_t DMAENCH1 : 1; + __IOM uint32_t DMAUDRIEN1 : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t ENCH2 : 1; + __IOM uint32_t BUFFDCH2 : 1; + __IOM uint32_t TRGENCH2 : 1; + __IOM uint32_t TRGSELCH2 : 3; + __IOM uint32_t WAVENCH2 : 2; + __IOM uint32_t MAMPSELCH2 : 4; + __IOM uint32_t DMAENCH2 : 1; + __IOM uint32_t DMAUDRIEN2 : 1; + __IM uint32_t RESERVED2 : 2; + } CTRL_B; + } ; + + /* Software trigger register */ + union + { + __OM uint32_t SWTRG; + + struct + { + __OM uint32_t SWTRG1 : 1; + __OM uint32_t SWTRG2 : 1; + __IM uint32_t RESERVED1 : 30; + } SWTRG_B; + } ; + + /* Channel1 12-bit right-aligned data holding register */ + union + { + __IOM uint32_t DH12R1; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED1 : 20; + } DH12R1_B; + } ; + + /* Channel1 12-bit left-aligned data holding register */ + union + { + __IOM uint32_t DH12L1; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED2 : 16; + } DH12L1_B; + } ; + + /* Channel1 8-bit right-aligned data holding register */ + union + { + __IOM uint32_t DH8R1; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED2 : 24; + } DH8R1_B; + } ; + + /* Channel2 12-bit right-aligned data holding register */ + union + { + __IOM uint32_t DH12R2; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED1 : 20; + } DH12R2_B; + } ; + + /* Channel2 12-bit left-aligned data holding register */ + union + { + __IOM uint32_t DH12L2; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED2 : 16; + } DH12L2_B; + } ; + + /* Channel2 8-bit right-aligned data holding register */ + union + { + __IOM uint32_t DH8R2; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED1 : 24; + } DH8R2_B; + } ; + + /* Dual DAC 12-bit right-aligned data holding register */ + union + { + __IOM uint32_t DH12RDUAL; + + struct + { + __IOM uint32_t DATACH1 : 12; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATACH2 : 12; + __IM uint32_t RESERVED2 : 4; + } DH12RDUAL_B; + } ; + + /* Dual DAC 12-bit left-aligned data holding register */ + union + { + __IOM uint32_t DH12LDUAL; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATACH1 : 12; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t DATACH2 : 12; + } DH12LDUAL_B; + } ; + + /* Dual DAC 8-bit right-aligned data holding register */ + union + { + __IOM uint32_t DH8RDUAL; + + struct + { + __IOM uint32_t DATACH1 : 8; + __IOM uint32_t DATACH2 : 8; + __IM uint32_t RESERVED1 : 16; + } DH8RDUAL_B; + } ; + + /* DAC channel1 data output register */ + union + { + __IM uint32_t DATAOCH1; + + struct + { + __IM uint32_t DATA : 12; + __IM uint32_t RESERVED1 : 20; + } DATAOCH1_B; + } ; + + /* DAC channel2 data output register */ + union + { + __IM uint32_t DATAOCH2; + + struct + { + __IM uint32_t DATA : 12; + __IM uint32_t RESERVED1 : 20; + } DATAOCH2_B; + } ; + + /* Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t RESERVED1 : 13; + __IOM uint32_t DMAUDRFLG1 : 1; + __IM uint32_t RESERVED2 : 15; + __IOM uint32_t DMAUDRFLG2 : 1; + __IM uint32_t RESERVED3 : 2; + } STS_B; + } ; +} DAC_T; + +/** + * @brief Debug support (DBG) + */ + +typedef struct +{ + + /* MCU Device ID Code Register */ + union + { + __IM uint32_t IDCODE; + + struct + { + __IM uint32_t EQR : 12; + __IM uint32_t RESERVED1 : 4; + __IM uint32_t WVR : 16; + } IDCODE_B; + } ; + + /* Debug MCU Configuration Register */ + union + { + __IOM uint32_t CFG; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t STOP_CLK_STS : 1; + __IOM uint32_t STANDBY_CLK_STS : 1; + __IM uint32_t RESERVED2 : 29; + } CFG_B; + } ; + + /* APB Low Freeze Register */ + union + { + __IOM uint32_t APB1F; + + struct + { + __IOM uint32_t TMR2_STS : 1; + __IOM uint32_t TMR3_STS : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t TMR6_STS : 1; + __IOM uint32_t TMR7_STS : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t TMR14_STS : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t RTC_STS : 1; + __IOM uint32_t WWDT_STS : 1; + __IOM uint32_t IWDT_STS : 1; + __IM uint32_t RESERVED4 : 8; + __IOM uint32_t I2C1_SMBUS_TIMEOUT_STS : 1; + __IM uint32_t RESERVED5 : 3; + __IOM uint32_t CAN_STS : 1; + __IM uint32_t RESERVED6 : 6; + } APB1F_B; + } ; + + /* APB High Freeze Register */ + union + { + __IOM uint32_t APB2F; + + struct + { + __IM uint32_t RESERVED1 : 11; + __IOM uint32_t TMR1_STS : 1; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t TMR15_STS : 1; + __IOM uint32_t TMR16_STS : 1; + __IOM uint32_t TMR17_STS : 1; + __IM uint32_t RESERVED3 : 13; + } APB2F_B; + } ; +} DBG_T; + +/** + * @brief DMA controller (DMA) + */ + +typedef struct +{ + + /* DMA interrupt status register */ + union + { + __IM uint32_t INTSTS; + + struct + { + __IM uint32_t GINTFLG1 : 1; + __IM uint32_t TCFLG1 : 1; + __IM uint32_t HTFLG1 : 1; + __IM uint32_t TERRFLG1 : 1; + __IM uint32_t GINTFLG2 : 1; + __IM uint32_t TCFLG2 : 1; + __IM uint32_t HTFLG2 : 1; + __IM uint32_t TERRFLG2 : 1; + __IM uint32_t GINTFLG3 : 1; + __IM uint32_t TCFLG3 : 1; + __IM uint32_t HTFLG3 : 1; + __IM uint32_t TERRFLG3 : 1; + __IM uint32_t GINTFLG4 : 1; + __IM uint32_t TCFLG4 : 1; + __IM uint32_t HTFLG4 : 1; + __IM uint32_t TERRFLG4 : 1; + __IM uint32_t GINTFLG5 : 1; + __IM uint32_t TCFLG5 : 1; + __IM uint32_t HTFLG5 : 1; + __IM uint32_t TERRFLG5 : 1; + __IM uint32_t GINTFLG6 : 1; + __IM uint32_t TCFLG6 : 1; + __IM uint32_t HTFLG6 : 1; + __IM uint32_t TERRFLG6 : 1; + __IM uint32_t GINTFLG7 : 1; + __IM uint32_t TCFLG7 : 1; + __IM uint32_t HTFLG7 : 1; + __IM uint32_t TERRFLG7 : 1; + __IM uint32_t RESERVED1 : 4; + } ISTS_B; + } ; + + /* DMA interrupt flag clear register */ + union + { + __OM uint32_t INTFCLR; + + struct + { + __OM uint32_t GINTCLR1 : 1; + __OM uint32_t TCCLR1 : 1; + __OM uint32_t HTCLR1 : 1; + __OM uint32_t TERRCLR1 : 1; + __OM uint32_t GINTCLR2 : 1; + __OM uint32_t TCCLR2 : 1; + __OM uint32_t HTCLR2 : 1; + __OM uint32_t TERRCLR2 : 1; + __OM uint32_t GINTCLR3 : 1; + __OM uint32_t TCCLR3 : 1; + __OM uint32_t HTCLR3 : 1; + __OM uint32_t TERRCLR3 : 1; + __OM uint32_t GINTCLR4 : 1; + __OM uint32_t TCCLR4 : 1; + __OM uint32_t HTCLR4 : 1; + __OM uint32_t TERRCLR4 : 1; + __OM uint32_t GINTCLR5 : 1; + __OM uint32_t TCCLR5 : 1; + __OM uint32_t HTCLR5 : 1; + __OM uint32_t TERRCLR5 : 1; + __OM uint32_t GINTCLR6 : 1; + __OM uint32_t TCCLR6 : 1; + __OM uint32_t HTCLR6 : 1; + __OM uint32_t TERRCLR6 : 1; + __OM uint32_t GINTCLR7 : 1; + __OM uint32_t TCCLR7 : 1; + __OM uint32_t HTCLR7 : 1; + __OM uint32_t TERRCLR7 : 1; + __IM uint32_t RESERVED1 : 4; + } INTFCLR_B; + } ; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG1; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG1_B; + } ; + + /* DMA channel 1 number of data register */ + union + { + __IOM uint32_t CHNDATA1; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA1_B; + } ; + + /* DMA channel 1 peripheral address register */ + union + { + __IOM uint32_t CHPADDR1; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR1_B; + } ; + + /* DMA channel 1 memory address register */ + union + { + __IOM uint32_t CHMADDR1; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR1_B; + } ; + __IM uint32_t RESERVED1; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG2; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG2_B; + } ; + + /* DMA channel 2 number of data register */ + union + { + __IOM uint32_t CHNDATA2; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA2_B; + } ; + + /* DMA channel 2 peripheral address register */ + union + { + __IOM uint32_t CHPADDR2; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR2_B; + } ; + + /* DMA channel 2 memory address register */ + union + { + __IOM uint32_t CHMADDR2; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR2_B; + } ; + __IM uint32_t RESERVED2; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG3; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG3_B; + } ; + + /* DMA channel 3 number of data register */ + union + { + __IOM uint32_t CHNDATA3; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA3_B; + } ; + + /* DMA channel 3 peripheral address register */ + union + { + __IOM uint32_t CHPADDR3; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR3_B; + } ; + + /* DMA channel 3 memory address register */ + union + { + __IOM uint32_t CHMADDR3; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR3_B; + } ; + __IM uint32_t RESERVED3; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG4; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG4_B; + } ; + + /* DMA channel 4 number of data register */ + union + { + __IOM uint32_t CHNDATA4; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA4_B; + } ; + + /* DMA channel 4 peripheral address register */ + union + { + __IOM uint32_t CHPADDR4; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR4_B; + } ; + + /* DMA channel 4 memory address register */ + union + { + __IOM uint32_t CHMADDR4; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR4_B; + } ; + __IM uint32_t RESERVED4; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG5; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG5_B; + } ; + + /* DMA channel 5 number of data register */ + union + { + __IOM uint32_t CHNDATA5; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA5_B; + } ; + + /* DMA channel 5 peripheral address register */ + union + { + __IOM uint32_t CHPADDR5; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR5_B; + } ; + + /* DMA channel 5 memory address register */ + union + { + __IOM uint32_t CHMADDR5; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR5_B; + } ; + __IM uint32_t RESERVED5; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG6; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG6_B; + } ; + + /* DMA channel 6 number of data register */ + union + { + __IOM uint32_t CHNDATA6; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA6_B; + } ; + + /* DMA channel 6 peripheral address register */ + union + { + __IOM uint32_t CHPADDR6; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR6_B; + } ; + + /* DMA channel 6 memory address register */ + union + { + __IOM uint32_t CHMADDR6; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR6_B; + } ; + __IM uint32_t RESERVED6; + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG7; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG7_B; + } ; + + /* DMA channel 7 number of data register */ + union + { + __IOM uint32_t CHNDATA7; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA7_B; + } ; + + /* DMA channel 7 peripheral address register */ + union + { + __IOM uint32_t CHPADDR7; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR7_B; + } ; + + /* DMA channel 7 memory address register */ + union + { + __IOM uint32_t CHMADDR7; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR7_B; + } ; + __IM uint32_t RESERVED7[6]; + + /* DMA channel remap selection register */ + union + { + __IOM uint32_t CHSEL; + + struct + { + __IOM uint32_t CHSEL1 : 4; + __IOM uint32_t CHSEL2 : 4; + __IOM uint32_t CHSEL3 : 4; + __IOM uint32_t CHSEL4 : 4; + __IOM uint32_t CHSEL5 : 4; + __IOM uint32_t CHSEL6 : 4; + __IOM uint32_t CHSEL7 : 4; + __IM uint32_t RESERVED1 : 4; + } CHSEL_B; + } ; +} DMA_T; + +/** + * @brief DMA CHANNEL register + */ + +typedef struct +{ + + /* DMA channel configuration register */ + union + { + __IOM uint32_t CHCFG; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED1 : 17; + } CHCFG_B; + } ; + + /* DMA channelx number of data register */ + union + { + __IOM uint32_t CHNDATA; + + struct + { + __IOM uint32_t NDATAT : 16; + __IM uint32_t RESERVED1 : 16; + } CHNDATA_B; + } ; + + /* DMA channelx peripheral address register */ + union + { + __IOM uint32_t CHPADDR; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR_B; + } ; + + /* DMA channelx memory address register */ + union + { + __IOM uint32_t CHMADDR; + + struct + { + __IOM uint32_t MEMADD : 32; + } CHMADDR_B; + } ; +} DMA_CHANNEL_T; + +/** + * @brief External interrupt/event controller (EINT) + */ + +typedef struct +{ + /* Interrupt mask register */ + union + { + __IOM uint32_t IMASK; + + struct + { + __IOM uint32_t IMASK0 : 1; + __IOM uint32_t IMASK1 : 1; + __IOM uint32_t IMASK2 : 1; + __IOM uint32_t IMASK3 : 1; + __IOM uint32_t IMASK4 : 1; + __IOM uint32_t IMASK5 : 1; + __IOM uint32_t IMASK6 : 1; + __IOM uint32_t IMASK7 : 1; + __IOM uint32_t IMASK8 : 1; + __IOM uint32_t IMASK9 : 1; + __IOM uint32_t IMASK10 : 1; + __IOM uint32_t IMASK11 : 1; + __IOM uint32_t IMASK12 : 1; + __IOM uint32_t IMASK13 : 1; + __IOM uint32_t IMASK14 : 1; + __IOM uint32_t IMASK15 : 1; + __IOM uint32_t IMASK16 : 1; + __IOM uint32_t IMASK17 : 1; + __IOM uint32_t IMASK18 : 1; + __IOM uint32_t IMASK19 : 1; + __IOM uint32_t IMASK20 : 1; + __IOM uint32_t IMASK21 : 1; + __IOM uint32_t IMASK22 : 1; + __IOM uint32_t IMASK23 : 1; + __IOM uint32_t IMASK24 : 1; + __IOM uint32_t IMASK25 : 1; + __IOM uint32_t IMASK26 : 1; + __IOM uint32_t IMASK27 : 1; + __IOM uint32_t IMASK28 : 1; + __IOM uint32_t IMASK29 : 1; + __IOM uint32_t IMASK30 : 1; + __IOM uint32_t IMASK31 : 1; + } IMASK_B; + } ; + + /* Event mask register (EINT_EVTMASK) */ + union + { + + __IOM uint32_t EMASK; + + struct + { + __IOM uint32_t EMASK0 : 1; + __IOM uint32_t EMASK1 : 1; + __IOM uint32_t EMASK2 : 1; + __IOM uint32_t EMASK3 : 1; + __IOM uint32_t EMASK4 : 1; + __IOM uint32_t EMASK5 : 1; + __IOM uint32_t EMASK6 : 1; + __IOM uint32_t EMASK7 : 1; + __IOM uint32_t EMASK8 : 1; + __IOM uint32_t EMASK9 : 1; + __IOM uint32_t EMASK10 : 1; + __IOM uint32_t EMASK11 : 1; + __IOM uint32_t EMASK12 : 1; + __IOM uint32_t EMASK13 : 1; + __IOM uint32_t EMASK14 : 1; + __IOM uint32_t EMASK15 : 1; + __IOM uint32_t EMASK16 : 1; + __IOM uint32_t EMASK17 : 1; + __IOM uint32_t EMASK18 : 1; + __IOM uint32_t EMASK19 : 1; + __IOM uint32_t EMASK20 : 1; + __IOM uint32_t EMASK21 : 1; + __IOM uint32_t EMASK22 : 1; + __IOM uint32_t EMASK23 : 1; + __IOM uint32_t EMASK24 : 1; + __IOM uint32_t EMASK25 : 1; + __IOM uint32_t EMASK26 : 1; + __IOM uint32_t EMASK27 : 1; + __IOM uint32_t EMASK28 : 1; + __IOM uint32_t EMASK29 : 1; + __IOM uint32_t EMASK30 : 1; + __IOM uint32_t EMASK31 : 1; + } EMASK_B; + } ; + + union + { + __IOM uint32_t RTEN; + + struct + { + __IOM uint32_t RTEN0 : 1; + __IOM uint32_t RTEN1 : 1; + __IOM uint32_t RTEN2 : 1; + __IOM uint32_t RTEN3 : 1; + __IOM uint32_t RTEN4 : 1; + __IOM uint32_t RTEN5 : 1; + __IOM uint32_t RTEN6 : 1; + __IOM uint32_t RTEN7 : 1; + __IOM uint32_t RTEN8 : 1; + __IOM uint32_t RTEN9 : 1; + __IOM uint32_t RTEN10 : 1; + __IOM uint32_t RTEN11 : 1; + __IOM uint32_t RTEN12 : 1; + __IOM uint32_t RTEN13 : 1; + __IOM uint32_t RTEN14 : 1; + __IOM uint32_t RTEN15 : 1; + __IOM uint32_t RTEN16 : 1; + __IOM uint32_t RTEN17 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t RTEN19 : 1; + __IOM uint32_t RTEN20 : 1; + __IOM uint32_t RTEN21 : 1; + __IOM uint32_t RTEN22 : 1; + __IM uint32_t RESERVED2 : 8; + __IOM uint32_t RTEN31 : 1; + } RTEN_B; + } ; + + /* Falling Trigger selection register */ + union + { + __IOM uint32_t FTEN; + + struct + { + __IOM uint32_t FTEN0 : 1; + __IOM uint32_t FTEN1 : 1; + __IOM uint32_t FTEN2 : 1; + __IOM uint32_t FTEN3 : 1; + __IOM uint32_t FTEN4 : 1; + __IOM uint32_t FTEN5 : 1; + __IOM uint32_t FTEN6 : 1; + __IOM uint32_t FTEN7 : 1; + __IOM uint32_t FTEN8 : 1; + __IOM uint32_t FTEN9 : 1; + __IOM uint32_t FTEN10 : 1; + __IOM uint32_t FTEN11 : 1; + __IOM uint32_t FTEN12 : 1; + __IOM uint32_t FTEN13 : 1; + __IOM uint32_t FTEN14 : 1; + __IOM uint32_t FTEN15 : 1; + __IOM uint32_t FTEN16 : 1; + __IOM uint32_t FTEN17 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t FTEN19 : 1; + __IOM uint32_t FTEN20 : 1; + __IOM uint32_t FTEN21 : 1; + __IOM uint32_t FTEN22 : 1; + __IM uint32_t RESERVED2 : 8; + __IOM uint32_t FTEN31 : 1; + } FTEN_B; + } ; + + /* Software interrupt event register */ + union + { + __IOM uint32_t SWINTE; + + struct + { + __IOM uint32_t SWINTE0 : 1; + __IOM uint32_t SWINTE1 : 1; + __IOM uint32_t SWINTE2 : 1; + __IOM uint32_t SWINTE3 : 1; + __IOM uint32_t SWINTE4 : 1; + __IOM uint32_t SWINTE5 : 1; + __IOM uint32_t SWINTE6 : 1; + __IOM uint32_t SWINTE7 : 1; + __IOM uint32_t SWINTE8 : 1; + __IOM uint32_t SWINTE9 : 1; + __IOM uint32_t SWINTE10 : 1; + __IOM uint32_t SWINTE11 : 1; + __IOM uint32_t SWINTE12 : 1; + __IOM uint32_t SWINTE13 : 1; + __IOM uint32_t SWINTE14 : 1; + __IOM uint32_t SWINTE15 : 1; + __IOM uint32_t SWINTE16 : 1; + __IOM uint32_t SWINTE17 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t SWINTE19 : 1; + __IOM uint32_t SWINTE20 : 1; + __IOM uint32_t SWINTE21 : 1; + __IOM uint32_t SWINTE22 : 1; + __IM uint32_t RESERVED2 : 8; + __IOM uint32_t SWINTE31 : 1; + } SWINTE_B; + } ; + + /* Pending register */ + union + { + __IOM uint32_t IPEND; + + struct + { + __IOM uint32_t IPEND0 : 1; + __IOM uint32_t IPEND1 : 1; + __IOM uint32_t IPEND2 : 1; + __IOM uint32_t IPEND3 : 1; + __IOM uint32_t IPEND4 : 1; + __IOM uint32_t IPEND5 : 1; + __IOM uint32_t IPEND6 : 1; + __IOM uint32_t IPEND7 : 1; + __IOM uint32_t IPEND8 : 1; + __IOM uint32_t IPEND9 : 1; + __IOM uint32_t IPEND10 : 1; + __IOM uint32_t IPEND11 : 1; + __IOM uint32_t IPEND12 : 1; + __IOM uint32_t IPEND13 : 1; + __IOM uint32_t IPEND14 : 1; + __IOM uint32_t IPEND15 : 1; + __IOM uint32_t IPEND16 : 1; + __IOM uint32_t IPEND17 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t IPEND19 : 1; + __IOM uint32_t IPEND20 : 1; + __IOM uint32_t IPEND21 : 1; + __IOM uint32_t IPEND22 : 1; + __IM uint32_t RESERVED2 : 8; + __IOM uint32_t IPEND31 : 1; + } IPEND_B; + } ; +} EINT_T; + +/** + * @brief FMC (FMC) + */ + +typedef struct +{ + + /* Flash access control register */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t WS : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PBEN : 1; + __IM uint32_t PBSF : 1; + __IM uint32_t RESERVED3 : 26; + } CTRL1_B; + } ; + + /* Flash key register */ + union + { + __OM uint32_t KEY; + + struct + { + __OM uint32_t KEY : 32; + } KEY_B; + } ; + + /* Flash option key register */ + union + { + __OM uint32_t OBKEY; + + struct + { + __OM uint32_t OBKEY : 32; + } OBKEY_B; + } ; + + /* Flash status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t BUSYF : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PEF : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WPEF : 1; + __IOM uint32_t OCF : 1; + __IM uint32_t RESERVED3 : 26; + } STS_B; + } ; + + /* Flash control register */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t PG : 1; + __IOM uint32_t PAGEERA : 1; + __IOM uint32_t MASSERA : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t OBP : 1; + __IOM uint32_t OBE : 1; + __IOM uint32_t STA : 1; + __IOM uint32_t LOCK : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t OBWEN : 1; + __IOM uint32_t ERRIE : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t OCIE : 1; + __IOM uint32_t OBLOAD : 1; + __IM uint32_t RESERVED4 : 18; + } CTRL2_B; + } ; + + /* Flash address register */ + union + { + __OM uint32_t ADDR; + + struct + { + __OM uint32_t ADDR : 32; + } ADDR_B; + } ; + __IM uint32_t RESERVED; + + /* Option byte register */ + union + { + __IM uint32_t OBCS; + + struct + { + __IM uint32_t OBE : 1; + __IM uint32_t READPROT : 2; + __IM uint32_t RESERVED1 : 5; + __IM uint32_t WDTSEL : 1; + __IM uint32_t RSTSTOP : 1; + __IM uint32_t RSTSTDB : 1; + __IM uint32_t RESERVED2 : 1; + __IM uint32_t nBOOT1 : 1; + __IM uint32_t VDDAMONI : 1; + __IM uint32_t SRAMPARITY : 1; + __IM uint32_t nBOOT0 : 1; + __IM uint32_t DATA0 : 8; + __IM uint32_t DATA1 : 8; + } OBCS_B; + } ; + + /* Write protection register */ + union + { + __IM uint32_t WRTPROT; + + struct + { + __IM uint32_t WRTPROT : 32; + } WRTPROT_B; + } ; +} FMC_T; + +/* + * @brief General-purpose I/Os (GPIO) + */ + +typedef struct +{ + /* GPIO port mode register*/ + union + { + __IOM uint32_t MODE; + + struct + { + __IOM uint32_t MODE0 : 2; + __IOM uint32_t MODE1 : 2; + __IOM uint32_t MODE2 : 2; + __IOM uint32_t MODE3 : 2; + __IOM uint32_t MODE4 : 2; + __IOM uint32_t MODE5 : 2; + __IOM uint32_t MODE6 : 2; + __IOM uint32_t MODE7 : 2; + __IOM uint32_t MODE8 : 2; + __IOM uint32_t MODE9 : 2; + __IOM uint32_t MODE10 : 2; + __IOM uint32_t MODE11 : 2; + __IOM uint32_t MODE12 : 2; + __IOM uint32_t MODE13 : 2; + __IOM uint32_t MODE14 : 2; + __IOM uint32_t MODE15 : 2; + } MODE_B; + } ; + + /* GPIO port output type register*/ + union + { + __IOM uint32_t OMODE; + + struct + { + __IOM uint32_t OMODE0 : 1; + __IOM uint32_t OMODE1 : 1; + __IOM uint32_t OMODE2 : 1; + __IOM uint32_t OMODE3 : 1; + __IOM uint32_t OMODE4 : 1; + __IOM uint32_t OMODE5 : 1; + __IOM uint32_t OMODE6 : 1; + __IOM uint32_t OMODE7 : 1; + __IOM uint32_t OMODE8 : 1; + __IOM uint32_t OMODE9 : 1; + __IOM uint32_t OMODE10 : 1; + __IOM uint32_t OMODE11 : 1; + __IOM uint32_t OMODE12 : 1; + __IOM uint32_t OMODE13 : 1; + __IOM uint32_t OMODE14 : 1; + __IOM uint32_t OMODE15 : 1; + __IOM uint32_t RESERVED1 : 16; + } OMODE_B; + } ; + + /* GPIO port output speed register*/ + union + { + __IOM uint32_t OSSEL; + + struct + { + __IOM uint32_t OSSEL0 : 2; + __IOM uint32_t OSSEL1 : 2; + __IOM uint32_t OSSEL2 : 2; + __IOM uint32_t OSSEL3 : 2; + __IOM uint32_t OSSEL4 : 2; + __IOM uint32_t OSSEL5 : 2; + __IOM uint32_t OSSEL6 : 2; + __IOM uint32_t OSSEL7 : 2; + __IOM uint32_t OSSEL8 : 2; + __IOM uint32_t OSSEL9 : 2; + __IOM uint32_t OSSEL10 : 2; + __IOM uint32_t OSSEL11 : 2; + __IOM uint32_t OSSEL12 : 2; + __IOM uint32_t OSSEL13 : 2; + __IOM uint32_t OSSEL14 : 2; + __IOM uint32_t OSSEL15 : 2; + } OSSEL_B; + } ; + + /* GPIO port pull-up/pull-down register*/ + union + { + __IOM uint32_t PUPD; + + struct + { + __IOM uint32_t PUPD0 : 2; + __IOM uint32_t PUPD1 : 2; + __IOM uint32_t PUPD2 : 2; + __IOM uint32_t PUPD3 : 2; + __IOM uint32_t PUPD4 : 2; + __IOM uint32_t PUPD5 : 2; + __IOM uint32_t PUPD6 : 2; + __IOM uint32_t PUPD7 : 2; + __IOM uint32_t PUPD8 : 2; + __IOM uint32_t PUPD9 : 2; + __IOM uint32_t PUPD10 : 2; + __IOM uint32_t PUPD11 : 2; + __IOM uint32_t PUPD12 : 2; + __IOM uint32_t PUPD13 : 2; + __IOM uint32_t PUPD14 : 2; + __IOM uint32_t PUPD15 : 2; + } PUPD_B; + } ; + + /* GPIO port input data register*/ + union + { + __IM uint32_t IDATA; + + struct + { + __IM uint32_t IDATA0 : 1; + __IM uint32_t IDATA1 : 1; + __IM uint32_t IDATA2 : 1; + __IM uint32_t IDATA3 : 1; + __IM uint32_t IDATA4 : 1; + __IM uint32_t IDATA5 : 1; + __IM uint32_t IDATA6 : 1; + __IM uint32_t IDATA7 : 1; + __IM uint32_t IDATA8 : 1; + __IM uint32_t IDATA9 : 1; + __IM uint32_t IDATA10 : 1; + __IM uint32_t IDATA11 : 1; + __IM uint32_t IDATA12 : 1; + __IM uint32_t IDATA13 : 1; + __IM uint32_t IDATA14 : 1; + __IM uint32_t IDATA15 : 1; + __IM uint32_t RESERVED1 : 16; + } IDATA_B; + } ; + + /* GPIO port output data register*/ + union + { + __IOM uint32_t ODATA; + + struct + { + __IOM uint32_t ODATA0 : 1; + __IOM uint32_t ODATA1 : 1; + __IOM uint32_t ODATA2 : 1; + __IOM uint32_t ODATA3 : 1; + __IOM uint32_t ODATA4 : 1; + __IOM uint32_t ODATA5 : 1; + __IOM uint32_t ODATA6 : 1; + __IOM uint32_t ODATA7 : 1; + __IOM uint32_t ODATA8 : 1; + __IOM uint32_t ODATA9 : 1; + __IOM uint32_t ODATA10 : 1; + __IOM uint32_t ODATA11 : 1; + __IOM uint32_t ODATA12 : 1; + __IOM uint32_t ODATA13 : 1; + __IOM uint32_t ODATA14 : 1; + __IOM uint32_t ODATA15 : 1; + __IOM uint32_t RESERVED1 : 16; + } ODATA_B; + } ; + + /* GPIO port bit set/clear register*/ + union + { + __OM uint32_t BSC; + + struct + { + __OM uint32_t BS0 : 1; + __OM uint32_t BS1 : 1; + __OM uint32_t BS2 : 1; + __OM uint32_t BS3 : 1; + __OM uint32_t BS4 : 1; + __OM uint32_t BS5 : 1; + __OM uint32_t BS6 : 1; + __OM uint32_t BS7 : 1; + __OM uint32_t BS8 : 1; + __OM uint32_t BS9 : 1; + __OM uint32_t BS10 : 1; + __OM uint32_t BS11 : 1; + __OM uint32_t BS12 : 1; + __OM uint32_t BS13 : 1; + __OM uint32_t BS14 : 1; + __OM uint32_t BS15 : 1; + __OM uint32_t BC0 : 1; + __OM uint32_t BC1 : 1; + __OM uint32_t BC2 : 1; + __OM uint32_t BC3 : 1; + __OM uint32_t BC4 : 1; + __OM uint32_t BC5 : 1; + __OM uint32_t BC6 : 1; + __OM uint32_t BC7 : 1; + __OM uint32_t BC8 : 1; + __OM uint32_t BC9 : 1; + __OM uint32_t BC10 : 1; + __OM uint32_t BC11 : 1; + __OM uint32_t BC12 : 1; + __OM uint32_t BC13 : 1; + __OM uint32_t BC14 : 1; + __OM uint32_t BC15 : 1; + } BSC_B; + } ; + + /* GPIO port configuration lock register*/ + union + { + __IOM uint32_t LOCK; + + struct + { + __IOM uint32_t LOCK0 : 1; + __IOM uint32_t LOCK1 : 1; + __IOM uint32_t LOCK2 : 1; + __IOM uint32_t LOCK3 : 1; + __IOM uint32_t LOCK4 : 1; + __IOM uint32_t LOCK5 : 1; + __IOM uint32_t LOCK6 : 1; + __IOM uint32_t LOCK7 : 1; + __IOM uint32_t LOCK8 : 1; + __IOM uint32_t LOCK9 : 1; + __IOM uint32_t LOCK10 : 1; + __IOM uint32_t LOCK11 : 1; + __IOM uint32_t LOCK12 : 1; + __IOM uint32_t LOCK13 : 1; + __IOM uint32_t LOCK14 : 1; + __IOM uint32_t LOCK15 : 1; + __IOM uint32_t LOCKKEY : 1; + __IOM uint32_t RESERVED1 : 15; + } LOCK_B; + } ; + + /* GPIO alternate function low register*/ + union + { + __IOM uint32_t ALFL; + + struct + { + __IOM uint32_t AF0 : 4; + __IOM uint32_t AF1 : 4; + __IOM uint32_t AF2 : 4; + __IOM uint32_t AF3 : 4; + __IOM uint32_t AF4 : 4; + __IOM uint32_t AF5 : 4; + __IOM uint32_t AF6 : 4; + __IOM uint32_t AF7 : 4; + } ALFL_B; + } ; + + /* GPIO alternate function high register*/ + union + { + __IOM uint32_t ALFH; + + struct + { + __IOM uint32_t AF0 : 4; + __IOM uint32_t AF1 : 4; + __IOM uint32_t AF2 : 4; + __IOM uint32_t AF3 : 4; + __IOM uint32_t AF4 : 4; + __IOM uint32_t AF5 : 4; + __IOM uint32_t AF6 : 4; + __IOM uint32_t AF7 : 4; + } ALFH_B; + } ; + + /* Port bit clear register*/ + union + { + __OM uint32_t BR; + + struct + { + __OM uint32_t BR0 : 1; + __OM uint32_t BR1 : 1; + __OM uint32_t BR2 : 1; + __OM uint32_t BR3 : 1; + __OM uint32_t BR4 : 1; + __OM uint32_t BR5 : 1; + __OM uint32_t BR6 : 1; + __OM uint32_t BR7 : 1; + __OM uint32_t BR8 : 1; + __OM uint32_t BR9 : 1; + __OM uint32_t BR10 : 1; + __OM uint32_t BR11 : 1; + __OM uint32_t BR12 : 1; + __OM uint32_t BR13 : 1; + __OM uint32_t BR14 : 1; + __OM uint32_t BR15 : 1; + __OM uint32_t RESERVED1 : 16; + } BR_B; + } ; +} GPIO_T; + + +/** + * @brief Inter-integrated circuit (I2C) + */ + +typedef struct +{ + /* Control register 1*/ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t I2CEN : 1; + __IOM uint32_t TXIEN : 1; + __IOM uint32_t RXIEN : 1; + __IOM uint32_t SADDRMIEN : 1; + __IOM uint32_t NACKRXIEN : 1; + __IOM uint32_t STOPIEN : 1; + __IOM uint32_t TXCIEN : 1; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t DNFCFG : 4; + __IOM uint32_t ANFD : 1; + __OM uint32_t SWRST : 1; + __IOM uint32_t DMATXEN : 1; + __IOM uint32_t DMARXEN : 1; + __IOM uint32_t SBCEN : 1; + __IOM uint32_t CLKSTRETCHD : 1; + __IOM uint32_t WUPEN : 1; + __IOM uint32_t RBEN : 1; + __IOM uint32_t HADDREN : 1; + __IOM uint32_t DEADDREN : 1; + __IOM uint32_t ALTEN : 1; + __IOM uint32_t PECEN : 1; + __IM uint32_t RESERVED2 : 8; + } CTRL1_B; + } ; + + /* Control register 2*/ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t SADDR0 : 1; + __IOM uint32_t SADDR1 : 7; + __IOM uint32_t SADDR8 : 2; + __IOM uint32_t TXDIR : 1; + __IOM uint32_t SADDRLEN : 1; + __IOM uint32_t ADDR10 : 1; + __IOM uint32_t START : 1; + __IOM uint32_t STOP : 1; + __IOM uint32_t NACKEN : 1; + __IOM uint32_t NUMBYT : 8; + __IOM uint32_t RELOADEN : 1; + __IOM uint32_t ENDCFG : 1; + __IOM uint32_t PEC : 1; + __IOM uint32_t RESERVED1 : 5; + } CTRL2_B; + } ; + + /* Own address register 1*/ + union + { + __IOM uint32_t ADDR1; + + struct + { + __IOM uint32_t ADDR0 : 1; + __IOM uint32_t ADDR1 : 7; + __IOM uint32_t ADDR8 : 2; + __IOM uint32_t ADDR1LEN : 1; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t ADDR1EN : 1; + __IM uint32_t RESERVED2 : 16; + } ADDR1_B; + } ; + + /* Own address register 2*/ + union + { + __IOM uint32_t ADDR2; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t ADDR2 : 7; + __IOM uint32_t ADDR2MSK : 3; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t ADDR2EN : 1; + __IM uint32_t RESERVED3 : 16; + } ADDR2_B; + } ; + + /* Timing register*/ + union + { + __IOM uint32_t TIMING; + + struct + { + __IOM uint32_t SCLL : 8; + __IOM uint32_t SCLH : 8; + __IOM uint32_t DATAHT : 4; + __IOM uint32_t DATAT : 4; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t TIMINGPSC : 4; + } TIMING_B; + } ; + + /* Status register 1*/ + union + { + __IOM uint32_t TIMEOUT; + + struct + { + __IOM uint32_t TIMEOUTA : 12; + __IOM uint32_t IDLECLKTO : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t CLKTOEN : 1; + __IOM uint32_t TIMEOUTB : 12; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t EXCLKTOEN : 1; + } TIMEOUT_B; + } ; + + /* Interrupt and Status register*/ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t TXBEFLG : 1; + __IOM uint32_t TXINTFLG : 1; + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t ADDRMFLG : 1; + __IM uint32_t NACKFLG : 1; + __IM uint32_t STOPFLG : 1; + __IM uint32_t TXCFLG : 1; + __IM uint32_t TXCRFLG : 1; + __IM uint32_t BERRFLG : 1; + __IM uint32_t ALFLG : 1; + __IM uint32_t OVRURFLG : 1; + __IM uint32_t PECEFLG : 1; + __IM uint32_t TTEFLG : 1; + __IM uint32_t SMBALTFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t BUSBSYFLG : 1; + __IM uint32_t TXDIRFLG : 1; + __IM uint32_t ADDRCMFLG : 7; + __IM uint32_t RESERVED2 : 8; + } STS_B; + } ; + + /* Interrupt clear register*/ + union + { + __OM uint32_t INTFCLR; + + struct + { + __IM uint32_t RESERVED1 : 3; + __OM uint32_t ADDRMCLR : 1; + __OM uint32_t NACKCLR : 1; + __OM uint32_t STOPCLR : 1; + __IM uint32_t RESERVED2 : 2; + __OM uint32_t BERRCLR : 1; + __OM uint32_t ALCLR : 1; + __OM uint32_t OVRURCLR : 1; + __OM uint32_t PECECLR : 1; + __OM uint32_t TTECLR : 1; + __OM uint32_t SMBALTCLR : 1; + __IM uint32_t RESERVED3 : 18; + } INTFCLR_B; + } ; + + /* PEC data register*/ + union + { + __IM uint32_t PEC; + + struct + { + __IM uint32_t PEC : 8; + __IM uint32_t RESERVED1 : 24; + } PEC_B; + } ; + + /* Receive data register*/ + union + { + __IM uint32_t RXDATA; + + struct + { + __IM uint32_t RXDATA : 8; + __IM uint32_t RESERVED1 : 24; + } RXDATA_B; + } ; + + /* Transmit data register*/ + union + { + __IOM uint32_t TXDATA; + + struct + { + __IOM uint32_t TXDATA : 8; + __IOM uint32_t RESERVED1 : 24; + } TXDATA_B; + } ; +} I2C_T; + +/** + * @brief Independent watchdog (IWDT) + */ + +typedef struct +{ + + /* Key register */ + union + { + __OM uint32_t KEY; + + struct + { + __OM uint32_t KEY : 16; + __IM uint32_t RESERVED1 : 16; + } KEY_B; + } ; + + /* Prescaler register */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t PSC : 3; + __IM uint32_t RESERVED1 : 29; + } PSC_B; + } ; + + /* Counter reload register */ + union + { + __IOM uint32_t CNTRLD; + + struct + { + __IOM uint32_t CNTRLD : 12; + __IM uint32_t RESERVED1 : 20; + } CNTRLD_B; + } ; + + /* Status register */ + union + { + __IM uint32_t STS; + + struct + { + __IM uint32_t PSCUFLG : 1; + __IM uint32_t CNTUFLG : 1; + __IM uint32_t WINUFLG : 1; + __IM uint32_t RESERVED1 : 29; + } STS_B; + } ; + + /* Window register */ + union + { + __IOM uint32_t WIN; + + struct + { + __IOM uint32_t WIN : 12; + __IM uint32_t RESERVED1 : 20; + } WIN_B; + } ; +} IWDT_T; + +/** + * @brief Option bytes (OB) + */ + +typedef struct +{ + + /* Read protection option byte */ + union + { + __IOM uint16_t READPROT; + + struct + { + __IOM uint16_t READPROT : 8; + __IOM uint16_t nREADPROT : 8; + } READPORT_B; + } ; + + /* User protection option byte */ + union + { + __IOM uint16_t USER; + + struct + { + __IOM uint16_t WDTSEL : 1; + __IOM uint16_t RSTSTOP : 1; + __IOM uint16_t RSTSTDBY : 1; + __IM uint16_t RESERVED1 : 1; + __IOM uint16_t BOT1 : 1; + __IOM uint16_t VDDAMON : 1; + __IOM uint16_t RPC : 1; + __IM uint16_t RESERVED2 : 1; + __IOM uint16_t nUSER : 8; + } USER_B; + } ; + + /* User data option byte */ + union + { + __IOM uint16_t DATA0; + + struct + { + __IOM uint16_t DATA0 : 8; + __IOM uint16_t nDATA0 : 8; + } DATA0_B; + } ; + + /* User data option byte */ + union + { + __IOM uint16_t DATA1; + + struct + { + __IOM uint16_t DATA1 : 8; + __IOM uint16_t nDATA1 : 8; + } DATA1_B; + } ; + + /* Write protection option byte */ + union + { + __IOM uint16_t WRTPROT0; + + struct + { + __IOM uint16_t WRTPROT0 : 8; + __IOM uint16_t nWRTPROT0 : 8; + } WRTPROT0_B; + } ; + + /* Write protection option byte */ + union + { + __IOM uint16_t WRTPROT1; + + struct + { + __IOM uint16_t WRTPROT1 : 8; + __IOM uint16_t nWRTPROT1 : 8; + } WRTPROT1_B; + } ; +} OB_T; + +/** + * @brief Power control (PMU) + */ + +typedef struct +{ + /* power control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t LPDSCFG : 1; + __IOM uint32_t PDDSCFG : 1; + __IOM uint32_t WUFLGCLR : 1; + __IOM uint32_t SBFLGCLR : 1; + __IOM uint32_t PVDEN : 1; + __IOM uint32_t PLSEL : 3; + __IOM uint32_t BPWEN : 1; + __IM uint32_t RESERVED1 : 23; + + } CTRL_B; + } ; + + /* power control/status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IM uint32_t WUEFLG : 1; + __IM uint32_t SBFLG : 1; + __IM uint32_t PVDOFLG : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t WKUPCFG1 : 1; + __IOM uint32_t WKUPCFG2 : 1; + __IOM uint32_t WKUPCFG3 : 1; + __IOM uint32_t WKUPCFG4 : 1; + __IOM uint32_t WKUPCFG5 : 1; + __IOM uint32_t WKUPCFG6 : 1; + __IOM uint32_t WKUPCFG7 : 1; + __IOM uint32_t WKUPCFG8 : 1; + __IM uint32_t RESERVED2 : 16; + } CSTS_B; + } ; +} PMU_T; + +/** + * @brief Reset and clock control (RCM) + */ + +typedef struct +{ + /*Clock control register 1 */ + union + { + /* Clock control register */ + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t HSIEN : 1; + __IM uint32_t HSIRDYFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t HSITRM : 5; + __IM uint32_t HSICAL : 8; + __IOM uint32_t HSEEN : 1; + __IM uint32_t HSERDYFLG : 1; + __IOM uint32_t HSEBCFG : 1; + __IOM uint32_t CSSEN : 1; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t PLLEN : 1; + __IM uint32_t PLLRDYFLG : 1; + __IM uint32_t RESERVED3 : 6; + } CTRL1_B; + } ; + + /* Clock configuration register 1 */ + union + { + __IOM uint32_t CFG1; + + struct + { + __IOM uint32_t SCLKSEL : 2; + __IM uint32_t SCLKSWSTS : 2; + __IOM uint32_t AHBPSC : 4; + __IOM uint32_t APB1PSC : 3; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ADCPSC : 1; + __IOM uint32_t PLLSRCSEL : 2; + __IOM uint32_t PLLHSEPSC : 1; + __IOM uint32_t PLLMULCFG : 4; + __IM uint32_t RESERVED3 : 2; + __IOM uint32_t MCOSEL : 4; + __IOM uint32_t MCOPSC : 3; + __IOM uint32_t MCOPLLPSC : 1; + } CFG1_B; + } ; + + /* Clock interrupt register */ + union + { + __IOM uint32_t INT; + + struct + { + __IM uint32_t LSIRDYFLG : 1; + __IM uint32_t LSERDYFLG : 1; + __IM uint32_t HSIRDYFLG : 1; + __IM uint32_t HSERDYFLG : 1; + __IM uint32_t PLLRDYFLG : 1; + __IM uint32_t HSI14RDYFLG : 1; + __IM uint32_t HSI48RDYFLG : 1; + __IM uint32_t CSSFLG : 1; + __IOM uint32_t LSIRDYEN : 1; + __IOM uint32_t LSERDYEN : 1; + __IOM uint32_t HSIRDYEN : 1; + __IOM uint32_t HSERDYEN : 1; + __IOM uint32_t PLLRDYEN : 1; + __IOM uint32_t HSI14RDYEN : 1; + __IOM uint32_t HSI48RDYEN : 1; + __IM uint32_t RESERVED1 : 1; + __OM uint32_t LSIRDYCLR : 1; + __OM uint32_t LSERDYCLR : 1; + __OM uint32_t HSIRDYCLR : 1; + __OM uint32_t HSERDYCLR : 1; + __OM uint32_t PLLRDYCLR : 1; + __OM uint32_t HSI14RDYCLR : 1; + __OM uint32_t HSI48RDYCLR : 1; + __OM uint32_t CSSCLR : 1; + __IM uint32_t RESERVED2 : 8; + } INT_B; + } ; + + /* APB2 peripheral reset register */ + union + { + __IOM uint32_t APBRST2; + + struct + { + __IOM uint32_t SYSCFGRST : 1; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t USART5RST : 1; + __IOM uint32_t USART6RST : 1; + __IOM uint32_t USART7RST : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t ADCRST : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t TMR1RST : 1; + __IOM uint32_t SPI1RST : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t USART1RST : 1; + __IM uint32_t RESERVED5 : 1; + __IOM uint32_t TMR15RST : 1; + __IOM uint32_t TMR16RST : 1; + __IOM uint32_t TMR17RST : 1; + __IM uint32_t RESERVED6 : 3; + __IOM uint32_t DBGRST : 1; + __IM uint32_t RESERVED7 : 9; + } APBRST2_B; + } ; + + /*APB1 peripheral reset register */ + union + { + __IOM uint32_t APBRST1; + + struct + { + __IOM uint32_t TMR2RST : 1; + __IOM uint32_t TMR3RST : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t TMR6RST : 1; + __IOM uint32_t TMR7RST : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t TMR14RST : 1; + __IM uint32_t RESERVED3 : 2; + __IOM uint32_t WWDTRST : 1; + __IM uint32_t RESERVED4 : 2; + __IOM uint32_t SPI2RST : 1; + __IM uint32_t RESERVED5 : 2; + __IOM uint32_t USART2RST : 1; + __IOM uint32_t USART3RST : 1; + __IOM uint32_t USART4RST : 1; + __IOM uint32_t USART5RST : 1; + __IOM uint32_t I2C1RST : 1; + __IOM uint32_t I2C2RST : 1; + __IOM uint32_t USBDRST : 1; + __IM uint32_t RESERVED6 : 1; + __IOM uint32_t CANRST : 1; + __IM uint32_t RESERVED7 : 1; + __IOM uint32_t CRSRST : 1; + __IOM uint32_t PMURST : 1; + __IOM uint32_t DACRST : 1; + __IOM uint32_t CECRST : 1; + __IM uint32_t RESERVED8 : 1; + } APBRST1_B; + } ; + + /* AHB Peripheral Clock enable register */ + union + { + __IOM uint32_t AHBCLKEN; + + struct + { + __IOM uint32_t DMA1EN : 1; + __IOM uint32_t DMA2EN : 1; + __IOM uint32_t SRAMEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t FMCEN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t CRCEN : 1; + __IM uint32_t RESERVED3 : 10; + __IOM uint32_t PAEN : 1; + __IOM uint32_t PBEN : 1; + __IOM uint32_t PCEN : 1; + __IOM uint32_t PDEN : 1; + __IOM uint32_t PEEN : 1; + __IOM uint32_t PFEN : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t TSCEN : 1; + __IM uint32_t RESERVED5 : 7; + } AHBCLKEN_B; + } ; + + union + { + __IOM uint32_t APBCLKEN2; + + struct + { + __IOM uint32_t SCFGCOMPEN : 1; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t USART6EN : 1; + __IOM uint32_t USART7EN : 1; + __IOM uint32_t USART8EN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t ADCEN : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t TMR1EN : 1; + __IOM uint32_t SPI1EN : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t USART1V : 1; + __IM uint32_t RESERVED5 : 1; + __IOM uint32_t TMR15EN : 1; + __IOM uint32_t TMR16EN : 1; + __IOM uint32_t TMR17EN : 1; + __IM uint32_t RESERVED6 : 3; + __IOM uint32_t DBGEN : 1; + __IM uint32_t RESERVED7 : 9; + } APBCLKEN2_B; + } ; + + /* APB1 peripheral clock enable register */ + union + { + __IOM uint32_t APBCLKEN1; + + struct + { + __IOM uint32_t TMR2EN : 1; + __IOM uint32_t TMR3EN : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t TMR6EN : 1; + __IOM uint32_t TMR7EN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t TMR14EN : 1; + __IM uint32_t RESERVED3 : 2; + __IOM uint32_t WWDTEN : 1; + __IM uint32_t RESERVED4 : 2; + __IOM uint32_t SPI2EN : 1; + __IM uint32_t RESERVED5 : 2; + __IOM uint32_t USART2EN : 1; + __IOM uint32_t USART3EN : 1; + __IOM uint32_t USART4EN : 1; + __IOM uint32_t USART5EN : 1; + __IOM uint32_t I2C1EN : 1; + __IOM uint32_t I2C2EN : 1; + __IOM uint32_t USBDEN : 1; + __IM uint32_t RESERVED6 : 1; + __IOM uint32_t CANEN : 1; + __IM uint32_t RESERVED7 : 1; + __IOM uint32_t CRSEN : 1; + __IOM uint32_t PMUEN : 1; + __IOM uint32_t DACEN : 1; + __IOM uint32_t CECEN : 1; + __IM uint32_t RESERVED8 : 1; + } APBCLKEN1_B; + } ; + + /* Backup domain control register */ + union + { + __IOM uint32_t BDCTRL; + + struct + { + __IOM uint32_t LSEEN : 1; + __IM uint32_t LSERDYFLG : 1; + __IOM uint32_t LSEBCFG : 1; + __IOM uint32_t LSEDRVCFG : 2; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t RTCSRCSEL : 2; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t RTCCLKEN : 1; + __IOM uint32_t BDRST : 1; + __IM uint32_t RESERVED3 : 15; + } BDCTRL_B; + } ; + + /* Control/status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IOM uint32_t LSIEN : 1; + __IM uint32_t LSIRDYFLG : 1; + __IM uint32_t RESERVED1 : 21; + __IM uint32_t PWRRSTFLG : 1; + __IOM uint32_t RSTFLGCLR : 1; + __IM uint32_t OBRSTFLG : 1; + __IM uint32_t PINRSTFLG : 1; + __IM uint32_t PODRSTFLG : 1; + __IM uint32_t SWRSTFLG : 1; + __IM uint32_t IWDTRSTFLG : 1; + __IM uint32_t WWDTRSTFLG : 1; + __IM uint32_t LPWRRSTFLG : 1; + } CSTS_B; + } ; + + /* AHB peripheral reset register */ + union + { + __IOM uint32_t AHBRST; + + struct + { + __IM uint32_t RESERVED1 : 17; + __IOM uint32_t PARST : 1; + __IOM uint32_t PBRST : 1; + __IOM uint32_t PCRST : 1; + __IOM uint32_t PDRST : 1; + __IOM uint32_t PERST : 1; + __IOM uint32_t PFRST : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t TSCRST : 1; + __IM uint32_t RESERVED3 : 7; + } AHBRST_B; + } ; + + /* Clock configuration register 2 */ + union + { + __IOM uint32_t CFG2; + + struct + { + __IOM uint32_t PLLDIVCFG : 4; + __IM uint32_t RESERVED1 : 28; + } CFG2_B; + } ; + + /*Clock configuration register 3 */ + union + { + __IOM uint32_t CFG3; + + struct + { + __IOM uint32_t USART1SEL : 2; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t I2C1SEL : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t CECSEL : 1; + __IOM uint32_t USBDSEL : 1; + __IOM uint32_t ADCSEL : 1; + __IM uint32_t RESERVED3 : 7; + __IOM uint32_t USART2SEL : 2; + __IOM uint32_t USART3SEL : 2; + __IM uint32_t RESERVED4 : 12; + } CFG3_B; + } ; + + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t HSI14EN : 1; + __IM uint32_t HSI14RDFLG : 1; + __IOM uint32_t HSI14TO : 1; + __IOM uint32_t HSI14TRM : 5; + __IM uint32_t HSI14CAL : 8; + __IOM uint32_t HSI48EN : 1; + __IM uint32_t HSI48RDFLG : 1; + __IM uint32_t RESERVED1 : 6; + __IM uint32_t HSI48CAL : 8; + } CTRL2_B; + } ; +} RCM_T; + +/** + * @brief Real-time clock (RTC) + */ + +typedef struct +{ + + /* time register */ + union + { + __IOM uint32_t TIME; + + struct + { + __IOM uint32_t SECU : 4; + __IOM uint32_t SECT : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t MINU : 4; + __IOM uint32_t MINT : 3; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t HRU : 4; + __IOM uint32_t HRT : 2; + __IOM uint32_t TIMEFCFG : 1; + __IM uint32_t RESERVED3 : 9; + } TIME_B; + } ; + + /* date register */ + union + { + __IOM uint32_t DATE; + + struct + { + __IOM uint32_t DAYU : 4; + __IOM uint32_t DAYT : 2; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t MONU : 4; + __IOM uint32_t MONT : 1; + __IOM uint32_t WEEKSEL : 3; + __IOM uint32_t YRU : 4; + __IOM uint32_t YRT : 4; + __IM uint32_t RESERVED2 : 8; + } DATE_B; + } ; + + /* control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t WUCLKSEL : 3; + __IOM uint32_t TSETECFG : 1; + __IOM uint32_t RCLKDEN : 1; + __IOM uint32_t RCMCFG : 1; + __IOM uint32_t TIMEFCFG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t ALREN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WUTEN : 1; + __IOM uint32_t TSEN : 1; + __IOM uint32_t ALRIEN : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t WUTIEN : 1; + __IOM uint32_t TSIEN : 1; + __OM uint32_t STCCFG : 1; + __OM uint32_t WTCCFG : 1; + __IOM uint32_t BAKP : 1; + __IOM uint32_t CALOSEL : 1; + __IOM uint32_t POLCFG : 1; + __IOM uint32_t OUTSEL : 2; + __IOM uint32_t CALOEN : 1; + __IM uint32_t RESERVED4 : 8; + } CTRL_B; + } ; + + /* initialization and status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t ALRWFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WUTWFLG : 1; + __IOM uint32_t SOPFLG : 1; + __IM uint32_t INITSFLG : 1; + __IOM uint32_t RSFLG : 1; + __IM uint32_t RINITFLG : 1; + __IOM uint32_t INITEN : 1; + __IOM uint32_t ALRAFLG : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WUTFLG : 1; + __IOM uint32_t TSFLG : 1; + __IOM uint32_t TSOVRFLG : 1; + __IOM uint32_t TP1FLG : 1; + __IOM uint32_t TP2FLG : 1; + __IM uint32_t TP3FLG : 1; + __IM uint32_t RCALPFLG : 1; + __IM uint32_t RESERVED3 : 15; + } STS_B; + } ; + + /* prescaler register */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t SPSC : 15; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t APSC : 7; + __IM uint32_t RESERVED2 : 9; + } PSC_B; + } ; + + /* auto-reload register */ + union + { + __OM uint32_t AUTORLD; + + struct + { + __OM uint32_t WUAUTORE : 15; + __IM uint32_t RESERVED1 : 17; + } AUTORLD_B; + } ; + __IM uint32_t RESERVED; + + /* alarm A register */ + union + { + __IOM uint32_t ALRMA; + + struct + { + __IOM uint32_t SECU : 4; + __IOM uint32_t SECT : 3; + __IOM uint32_t SECMEN : 1; + __IOM uint32_t MINU : 4; + __IOM uint32_t MINT : 3; + __IOM uint32_t MINMEN : 1; + __IOM uint32_t HRU : 4; + __IOM uint32_t HRT : 2; + __IOM uint32_t TIMEFCFG : 1; + __IOM uint32_t HRMEN : 1; + __IOM uint32_t DAYU : 4; + __IOM uint32_t DAYT : 2; + __IOM uint32_t WEEKSEL : 1; + __IOM uint32_t DATEMEN : 1; + } ALRMA_B; + } ; + + __IM uint32_t RESERVED1; + + /* write protection register */ + union + { + __OM uint32_t WRPROT; + + struct + { + __OM uint32_t KEY : 8; + __IM uint32_t RESERVED1 : 24; + } WRPROT_B; + } ; + + /* sub second register */ + union + { + __IM uint32_t SUBSEC; + + struct + { + __IM uint32_t SUBSEC : 16; + __IM uint32_t RESERVED1 : 16; + } SUBSEC_B; + } ; + + /* shift control register */ + union + { + __OM uint32_t SHIFT; + + struct + { + __OM uint32_t SFSEC : 15; + __IM uint32_t RESERVED1 : 16; + __OM uint32_t ADD1SECEN : 1; + } SHIFT_B; + } ; + + /* timestamp time register */ + union + { + __IM uint32_t TSTIME; + + struct + { + __IM uint32_t SECU : 4; + __IM uint32_t SECT : 3; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t MINU : 4; + __IM uint32_t MINT : 3; + __IM uint32_t RESERVED2 : 1; + __IM uint32_t HRU : 4; + __IM uint32_t HRT : 2; + __IM uint32_t TIMEFCFG : 1; + __IM uint32_t RESERVED3 : 9; + } TSTIME_B; + } ; + + /* timestamp date register */ + union + { + __IM uint32_t TSDATE; + + struct + { + __IM uint32_t DAYU : 4; + __IM uint32_t DAYT : 2; + __IM uint32_t RESERVED1 : 2; + __IM uint32_t MONU : 4; + __IM uint32_t MONT : 1; + __IM uint32_t WEEKSEL : 3; + __IM uint32_t RESERVED2 : 16; + } TSDATE_B; + } ; + + /* time-stamp sub second register */ + union + { + __IM uint32_t TSSUBSEC; + + struct + { + __IM uint32_t SUBSEC : 16; + __IM uint32_t RESERVED1 : 16; + } TSSUBSEC_B; + } ; + + /* calibration register */ + union + { + __IOM uint32_t CAL; + + struct + { + __IOM uint32_t RECALF : 9; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t CAL16CFG : 1; + __IOM uint32_t CAL8CFG : 1; + __IOM uint32_t ICALFEN : 1; + __IM uint32_t RESERVED2 : 16; + } CAL_B; + } ; + + /* tamper and alternate function configuration register */ + union + { + __IOM uint32_t TACFG; + + struct + { + __IOM uint32_t TP1EN : 1; + __IOM uint32_t TP1ALCFG : 1; + __IOM uint32_t TPIEN : 1; + __IOM uint32_t TP2EN : 1; + __IOM uint32_t TP2ALCFG : 1; + __IOM uint32_t TP3EN : 1; + __IOM uint32_t TP3ALCFG : 1; + __IOM uint32_t TPTSEN : 1; + __IOM uint32_t TPSFSEL : 3; + __IOM uint32_t TPFCSEL : 2; + __IOM uint32_t TPPRDUSEL : 2; + __IOM uint32_t TPPUDIS : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t PC13VAL : 1; + __IOM uint32_t PC13EN : 1; + __IOM uint32_t PC14VAL : 1; + __IOM uint32_t PC14EN : 1; + __IOM uint32_t PC15VAL : 1; + __IOM uint32_t PC15EN : 1; + __IM uint32_t RESERVED2 : 8; + } TACFG_B; + } ; + + /* alarm A sub second register */ + union + { + __IOM uint32_t ALRMASS; + + struct + { + __IOM uint32_t SUBSEC : 15; + __IM uint32_t RESERVED1 : 9; + __IOM uint32_t MASKSEL : 4; + __IM uint32_t RESERVED2 : 4; + } ALRMASS_B; + } ; + + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t BAKP0; + + struct + { + __IOM uint32_t BAKP : 32; + } BAKP0_B; + } ; + + union + { + __IOM uint32_t BAKP1; + + struct + { + __IOM uint32_t BAKP : 32; + } BAKP1_B; + } ; + union + { + __IOM uint32_t BAKP2; + + struct + { + __IOM uint32_t BAKP : 32; + } BAKP2_B; + } ; + union + { + __IOM uint32_t BAKP3; + + struct + { + __IOM uint32_t BAKP : 32; + } BAKP3_B; + } ; + union + { + __IOM uint32_t BAKP4; + + struct + { + __IOM uint32_t BAKP : 32; + } BAKP4_B; + } ; +} RTC_T; + +/** + * @brief Serial peripheral interface (SPI1) + */ + +typedef struct +{ + /* control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t MSMCFG : 1; + __IOM uint32_t BRSEL : 3; + __IOM uint32_t SPIEN : 1; + __IOM uint32_t LSBSEL : 1; + __IOM uint32_t ISSEL : 1; + __IOM uint32_t SSEN : 1; + __IOM uint32_t RXOMEN : 1; + __IOM uint32_t CRCLSEL : 1; + __IOM uint32_t CRCNXT : 1; + __IOM uint32_t CRCEN : 1; + __IOM uint32_t BMOEN : 1; + __IOM uint32_t BMEN : 1; + __IM uint32_t RESERVED1 : 16; + } CTRL1_B; + } ; + + /* control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t RXDEN : 1; + __IOM uint32_t TXDEN : 1; + __IOM uint32_t SSOEN : 1; + __IOM uint32_t NSSPEN : 1; + __IOM uint32_t FRFCFG : 1; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t RXBNEIEN : 1; + __IOM uint32_t TXBEIEN : 1; + __IOM uint32_t DSCFG : 4; + __IOM uint32_t FRTCFG : 1; + __IOM uint32_t LDRX : 1; + __IOM uint32_t LDTX : 1; + __IM uint32_t RESERVED1 : 17; + } CTRL2_B; + } ; + + /* status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IM uint32_t SCHDIR : 1; + __IM uint32_t UDRFLG : 1; + __IOM uint32_t CRCEFLG : 1; + __IM uint32_t MEFLG : 1; + __IM uint32_t OVRFLG : 1; + __IM uint32_t BSYFLG : 1; + __IM uint32_t FRECFG : 1; + __IM uint32_t FRLSEL : 2; + __IM uint32_t FTLSEL : 2; + __IM uint32_t RESERVED1 : 19; + } STS_B; + } ; + + /* data register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED1 : 16; + } DATA_B; + } ; + + /* CRC polynomial register */ + union + { + __IOM uint32_t CRCPOLY; + + struct + { + __IOM uint32_t CRCPOLY : 16; + __IM uint32_t RESERVED1 : 16; + } CRCPOLY_B; + } ; + + /*RX CRC register */ + union + { + + __IM uint32_t RXCRC; + + struct + { + __IM uint32_t RXCRC : 16; + __IM uint32_t RESERVED1 : 16; + } RXCRC_B; + } ; + + /* TX CRC register */ + union + { + + __IM uint32_t TXCRC; + + struct + { + __IM uint32_t TXCRC : 16; + __IM uint32_t RESERVED1 : 16; + } TXCRC_B; + } ; + + /* I2S CFG register */ + union + { + __IOM uint32_t I2SCFG; + + struct + { + __IOM uint32_t CHLEN : 1; + __IOM uint32_t DATALEN : 2; + __IOM uint32_t CPOL : 1; + __IOM uint32_t I2SSSEL : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PFSSEL : 1; + __IOM uint32_t I2SMOD : 2; + __IOM uint32_t I2SEN : 1; + __IOM uint32_t MODESEL : 1; + __IM uint32_t RESERVED2 : 20; + } I2SCFG_B; + } ; + + /* I2S Prescaler */ + union + { + __IOM uint32_t I2SPSC; + + struct + { + __IOM uint32_t I2SPSC : 8; + __IOM uint32_t ODDPSC : 1; + __IOM uint32_t MCOEN : 1; + __IM uint32_t RESERVED1 : 22; + } I2SPSC_B; + } ; +} SPI_T; + +/** + * @brief System configuration controller (SYSCFG) + */ + +typedef struct +{ + /* configuration register 1 */ + union + { + __IOM uint32_t CFG1; + + struct + { + __IOM uint32_t MMSEL : 2; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t IRSEL : 2; + __IOM uint32_t ADCDMARMP : 1; + __IOM uint32_t USART1TXRMP : 1; + __IOM uint32_t USART1RXRMP : 1; + __IOM uint32_t TMR16DMARMP : 1; + __IOM uint32_t TMR17DMARMP : 1; + __IOM uint32_t TMR16DMARMP2 : 1; + __IOM uint32_t TMR17DMARMP2 : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t I2CPB6FMP : 1; + __IOM uint32_t I2CPB7FMP : 1; + __IOM uint32_t I2CPB8FMP : 1; + __IOM uint32_t I2CPB9FMP : 1; + __IOM uint32_t I2C1FMP : 1; + __IOM uint32_t I2C2FMP : 1; + __IOM uint32_t I2CPA9FMP : 1; + __IOM uint32_t I2CPA10FMP : 1; + __IOM uint32_t SPI2DMARMP : 1; + __IOM uint32_t USART2DMARMP : 1; + __IOM uint32_t USART3DMARMP : 1; + __IOM uint32_t I2C1DMARMP : 1; + __IOM uint32_t TMR1DMARMP : 1; + __IOM uint32_t TMR2DMARMP : 1; + __IOM uint32_t TMR3DMARMP : 1; + __IM uint32_t RESERVED3 : 1; + } CFG1_B; + } ; + __IM uint32_t RESERVED; + + /* external interrupt configuration register 1 */ + union + { + + __IOM uint32_t EINTCFG1; + + struct + { + __IOM uint32_t EINT0 : 4; + __IOM uint32_t EINT1 : 4; + __IOM uint32_t EINT2 : 4; + __IOM uint32_t EINT3 : 4; + __IM uint32_t RESERVED1 : 16; + } EINTCFG1_B; + } ; + + /* external interrupt configuration register 2 */ + union + { + __IOM uint32_t EINTCFG2; + + struct + { + __IOM uint32_t EINT4 : 4; + __IOM uint32_t EINT5 : 4; + __IOM uint32_t EINT6 : 4; + __IOM uint32_t EINT7 : 4; + __IM uint32_t RESERVED1 : 16; + } EINTCFG2_B; + } ; + + /* external interrupt configuration register 3 */ + union + { + __IOM uint32_t EINTCFG3; + + struct + { + __IOM uint32_t EINT8 : 4; + __IOM uint32_t EINT9 : 4; + __IOM uint32_t EINT10 : 4; + __IOM uint32_t EINT11 : 4; + __IM uint32_t RESERVED1 : 16; + } EINTCFG3_B; + } ; + + /* external interrupt configuration register 4 */ + union + { + __IOM uint32_t EINTCFG4; + + struct + { + __IOM uint32_t EINT12 : 4; + __IOM uint32_t EINT13 : 4; + __IOM uint32_t EINT14 : 4; + __IOM uint32_t EINT15 : 4; + __IM uint32_t RESERVED1 : 16; + } EINTCFG4_B; + } ; + + /* configuration register 2 */ + union + { + __IOM uint32_t CFG2; + + struct + { + __IOM uint32_t LOCK : 1; + __IOM uint32_t SRAMLOCK : 1; + __IOM uint32_t PVDLOCK : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t SRAMEFLG : 1; + __IM uint32_t RESERVED2 : 23; + } CFG2_B; + } ; +} SYSCFG_T; + +/** + * @brief Touch sensing controller (TSC) + */ + +typedef struct +{ + /* I/O group 1~8 counter register */ + union + { + __IM uint32_t IOGCNT; + + struct + { + __IM uint32_t CNTVAL : 14; + __IM uint32_t RESERVED1 : 18; + } IOGCNT_B; + }; +} TSC_IOGroupRegister_T; + +typedef struct +{ + /* configuration register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t TSCEN : 1; + __IOM uint32_t STARTAFLG : 1; + __IOM uint32_t AMCFG : 1; + __IOM uint32_t SYNPPOL : 1; + __IOM uint32_t IODEFCFG : 1; + __IOM uint32_t MCNTVSEL : 3; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t PGCDFSEL : 3; + __IOM uint32_t SSCDFSEL : 1; + __IOM uint32_t SSEN : 1; + __IOM uint32_t SSERRVSEL : 7; + __IOM uint32_t CTPLSEL : 4; + __IOM uint32_t CTPHSEL : 4; + } CTRL_B; + } ; + + /* interrupt enable register */ + union + { + __IOM uint32_t INTEN; + + struct + { + __IOM uint32_t EOAIEN : 1; + __IOM uint32_t MCEIEN : 1; + __IM uint32_t RESERVED1 : 30; + } INTEN_B; + } ; + + /* interrupt clear register */ + union + { + __IOM uint32_t INTFCLR; + + struct + { + __IOM uint32_t EOAICLR : 1; + __IOM uint32_t MCEICLR : 1; + __IM uint32_t RESERVED1 : 30; + } INTFCLR_B; + } ; + + /* interrupt status register */ + union + { + __IOM uint32_t INTSTS; + + struct + { + __IOM uint32_t EOAFLG : 1; + __IOM uint32_t MCEFLG : 1; + __IM uint32_t RESERVED1 : 30; + } INTSTS_B; + } ; + + /* I/O hysteresis control register */ + union + { + __IOM uint32_t IOHCTRL; + + struct + { + __IOM uint32_t G1P1 : 1; + __IOM uint32_t G1P2 : 1; + __IOM uint32_t G1P3 : 1; + __IOM uint32_t G1P4 : 1; + __IOM uint32_t G2P1 : 1; + __IOM uint32_t G2P2 : 1; + __IOM uint32_t G2P3 : 1; + __IOM uint32_t G2P4 : 1; + __IOM uint32_t G3P1 : 1; + __IOM uint32_t G3P2 : 1; + __IOM uint32_t G3P3 : 1; + __IOM uint32_t G3P4 : 1; + __IOM uint32_t G4P1 : 1; + __IOM uint32_t G4P2 : 1; + __IOM uint32_t G4P3 : 1; + __IOM uint32_t G4P4 : 1; + __IOM uint32_t G5P1 : 1; + __IOM uint32_t G5P2 : 1; + __IOM uint32_t G5P3 : 1; + __IOM uint32_t G5P4 : 1; + __IOM uint32_t G6P1 : 1; + __IOM uint32_t G6P2 : 1; + __IOM uint32_t G6P3 : 1; + __IOM uint32_t G6P4 : 1; + __IM uint32_t RESERVED1 : 8; + } IOHCTRL_B; + } ; + __IM uint32_t RESERVED; + + /* I/O analog switch control register */ + union + { + __IOM uint32_t IOASWCTRL; + + struct + { + __IOM uint32_t G1P1 : 1; + __IOM uint32_t G1P2 : 1; + __IOM uint32_t G1P3 : 1; + __IOM uint32_t G1P4 : 1; + __IOM uint32_t G2P1 : 1; + __IOM uint32_t G2P2 : 1; + __IOM uint32_t G2P3 : 1; + __IOM uint32_t G2P4 : 1; + __IOM uint32_t G3P1 : 1; + __IOM uint32_t G3P2 : 1; + __IOM uint32_t G3P3 : 1; + __IOM uint32_t G3P4 : 1; + __IOM uint32_t G4P1 : 1; + __IOM uint32_t G4P2 : 1; + __IOM uint32_t G4P3 : 1; + __IOM uint32_t G4P4 : 1; + __IOM uint32_t G5P1 : 1; + __IOM uint32_t G5P2 : 1; + __IOM uint32_t G5P3 : 1; + __IOM uint32_t G5P4 : 1; + __IOM uint32_t G6P1 : 1; + __IOM uint32_t G6P2 : 1; + __IOM uint32_t G6P3 : 1; + __IOM uint32_t G6P4 : 1; + __IM uint32_t RESERVED1 : 8; + } IOASWCTRL_B; + } ; + __IM uint32_t RESERVED1; + + /* I/O sampling control register */ + union + { + __IOM uint32_t IOSMPCTRL; + + struct + { + __IOM uint32_t G1P1 : 1; + __IOM uint32_t G1P2 : 1; + __IOM uint32_t G1P3 : 1; + __IOM uint32_t G1P4 : 1; + __IOM uint32_t G2P1 : 1; + __IOM uint32_t G2P2 : 1; + __IOM uint32_t G2P3 : 1; + __IOM uint32_t G2P4 : 1; + __IOM uint32_t G3P1 : 1; + __IOM uint32_t G3P2 : 1; + __IOM uint32_t G3P3 : 1; + __IOM uint32_t G3P4 : 1; + __IOM uint32_t G4P1 : 1; + __IOM uint32_t G4P2 : 1; + __IOM uint32_t G4P3 : 1; + __IOM uint32_t G4P4 : 1; + __IOM uint32_t G5P1 : 1; + __IOM uint32_t G5P2 : 1; + __IOM uint32_t G5P3 : 1; + __IOM uint32_t G5P4 : 1; + __IOM uint32_t G6P1 : 1; + __IOM uint32_t G6P2 : 1; + __IOM uint32_t G6P3 : 1; + __IOM uint32_t G6P4 : 1; + __IM uint32_t RESERVED1 : 8; + } IOSMPCTRL_B; + } ; + __IM uint32_t RESERVED2; + + /* I/O channel control register */ + union + { + __IOM uint32_t IOCHCTRL; + + struct + { + __IOM uint32_t G1P1 : 1; + __IOM uint32_t G1P2 : 1; + __IOM uint32_t G1P3 : 1; + __IOM uint32_t G1P4 : 1; + __IOM uint32_t G2P1 : 1; + __IOM uint32_t G2P2 : 1; + __IOM uint32_t G2P3 : 1; + __IOM uint32_t G2P4 : 1; + __IOM uint32_t G3P1 : 1; + __IOM uint32_t G3P2 : 1; + __IOM uint32_t G3P3 : 1; + __IOM uint32_t G3P4 : 1; + __IOM uint32_t G4P1 : 1; + __IOM uint32_t G4P2 : 1; + __IOM uint32_t G4P3 : 1; + __IOM uint32_t G4P4 : 1; + __IOM uint32_t G5P1 : 1; + __IOM uint32_t G5P2 : 1; + __IOM uint32_t G5P3 : 1; + __IOM uint32_t G5P4 : 1; + __IOM uint32_t G6P1 : 1; + __IOM uint32_t G6P2 : 1; + __IOM uint32_t G6P3 : 1; + __IOM uint32_t G6P4 : 1; + __IM uint32_t RESERVED1 : 8; + } IOCHCTRL_B; + } ; + __IM uint32_t RESERVED3; + + /* I/O group control status register */ + union + { + __IOM uint32_t IOGCSTS; + + struct + { + __IOM uint32_t G1EN : 1; + __IOM uint32_t G2EN : 1; + __IOM uint32_t G3EN : 1; + __IOM uint32_t G4EN : 1; + __IOM uint32_t G5EN : 1; + __IOM uint32_t G6EN : 1; + __IOM uint32_t G7EN : 1; + __IOM uint32_t G8EN : 1; + __IM uint32_t RESERVED1 : 8; + __IM uint32_t G1STS : 1; + __IM uint32_t G2STS : 1; + __IM uint32_t G3STS : 1; + __IM uint32_t G4STS : 1; + __IM uint32_t G5STS : 1; + __IM uint32_t G6STS : 1; + __IM uint32_t G7STS : 1; + __IM uint32_t G8STS : 1; + __IM uint32_t RESERVED2 : 8; + } IOGCSTS_B; + } ; + + TSC_IOGroupRegister_T IOGxCNT[8]; +} TSC_T; + +/** + * @brief Advanced-timers (TMR1) + */ + +typedef struct +{ + /* control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t CNTEN : 1; + __IOM uint32_t UD : 1; + __IOM uint32_t URSSEL : 1; + __IOM uint32_t SPMEN : 1; + __IOM uint32_t CNTDIR : 1; + __IOM uint32_t CAMSEL : 2; + __IOM uint32_t ARPEN : 1; + __IOM uint32_t CLKDIV : 2; + __IM uint32_t RESERVED1 : 22; + } CTRL1_B; + } ; + + /* control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t CCPEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CCUSEL : 1; + __IOM uint32_t CCDSEL : 1; + __IOM uint32_t MMSEL : 3; + __IOM uint32_t TI1SEL : 1; + __IOM uint32_t OC1OIS : 1; + __IOM uint32_t OC1NOIS : 1; + __IOM uint32_t OC2OIS : 1; + __IOM uint32_t OC2NOIS : 1; + __IOM uint32_t OC3OIS : 1; + __IOM uint32_t OC3NOIS : 1; + __IOM uint32_t OC4OIS : 1; + __IM uint32_t RESERVED2 : 17; + } CTRL2_B; + } ; + + /* slave mode control register */ + union + { + __IOM uint32_t SMCTRL; + + struct + { + __IOM uint32_t SMFSEL : 3; + __IOM uint32_t OCCSEL : 1; + __IOM uint32_t TRGSEL : 3; + __IOM uint32_t MSMEN : 1; + __IOM uint32_t ETFCFG : 4; + __IOM uint32_t ETPCFG : 2; + __IOM uint32_t ECEN : 1; + __IOM uint32_t ETPOL : 1; + __IM uint32_t RESERVED1 : 16; + } SMCTRL_B; + } ; + + /* DMA/Interrupt enable register */ + union + { + __IOM uint32_t DIEN; + + struct + { + __IOM uint32_t UIEN : 1; + __IOM uint32_t CC1IEN : 1; + __IOM uint32_t CC2IEN : 1; + __IOM uint32_t CC3IEN : 1; + __IOM uint32_t CC4IEN : 1; + __IOM uint32_t COMIEN : 1; + __IOM uint32_t TRGIEN : 1; + __IOM uint32_t BRKIEN : 1; + __IOM uint32_t UDIEN : 1; + __IOM uint32_t CC1DEN : 1; + __IOM uint32_t CC2DEN : 1; + __IOM uint32_t CC3DEN : 1; + __IOM uint32_t CC4DEN : 1; + __IOM uint32_t COMDEN : 1; + __IOM uint32_t TRGDEN : 1; + __IM uint32_t RESERVED1 : 17; + } DIEN_B; + } ; + + /* status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t UIFLG : 1; + __IOM uint32_t CC1IFLG : 1; + __IOM uint32_t CC2IFLG : 1; + __IOM uint32_t CC3IFLG : 1; + __IOM uint32_t CC4IFLG : 1; + __IOM uint32_t COMIFLG : 1; + __IOM uint32_t TRGIFLG : 1; + __IOM uint32_t BRKIFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CC1RCFLG : 1; + __IOM uint32_t CC2RCFLG : 1; + __IOM uint32_t CC3RCFLG : 1; + __IOM uint32_t CC4RCFLG : 1; + __IM uint32_t RESERVED2 : 19; + } STS_B; + } ; + + /* event generation register */ + union + { + __OM uint32_t CEG; + + struct + { + __OM uint32_t UEG : 1; + __OM uint32_t CC1EG : 1; + __OM uint32_t CC2EG : 1; + __OM uint32_t CC3EG : 1; + __OM uint32_t CC4EG : 1; + __OM uint32_t COMG : 1; + __OM uint32_t TEG : 1; + __OM uint32_t BEG : 1; + __IM uint32_t RESERVED1 : 24; + } CEG_B; + } ; + + union + { + /* capture/compare mode register (output mode) */ + union + { + __IOM uint32_t CCM1_OUTPUT; + + struct + { + __IOM uint32_t CC1SEL : 2; + __IOM uint32_t OC1FEN : 1; + __IOM uint32_t OC1PEN : 1; + __IOM uint32_t OC1MOD : 3; + __IOM uint32_t OC1CEN : 1; + __IOM uint32_t CC2SEL : 2; + __IOM uint32_t OC2FEN : 1; + __IOM uint32_t OC2PEN : 1; + __IOM uint32_t OC2MOD : 3; + __IOM uint32_t OC2CEN : 1; + __IM uint32_t RESERVED1 : 16; + } CCM1_OUTPUT_B; + } ; + + /* capture/compare mode register 1 (input mode) */ + union + { + __IOM uint32_t CCM1_INPUT; + + struct + { + __IOM uint32_t CC1SEL : 2; + __IOM uint32_t IC1PSC : 2; + __IOM uint32_t IC1F : 4; + __IOM uint32_t CC2SEL : 2; + __IOM uint32_t IC2PSC : 2; + __IOM uint32_t IC2F : 4; + __IM uint32_t RESERVED1 : 16; + } CCM1_INPUT_B; + } ; + }; + + union + { + /* capture/compare mode register (output mode) */ + union + { + __IOM uint32_t CCM2_OUTPUT; + + struct + { + __IOM uint32_t CC3SEL : 2; + __IOM uint32_t OC3FEN : 1; + __IOM uint32_t OC3PEN : 1; + __IOM uint32_t OC3MOD : 3; + __IOM uint32_t OC3CEN : 1; + __IOM uint32_t CC4SEL : 2; + __IOM uint32_t OC4FEN : 1; + __IOM uint32_t OC4PEN : 1; + __IOM uint32_t OC4MOD : 3; + __IOM uint32_t OC4CEN : 1; + __IM uint32_t RESERVED1 : 16; + } CCM2_OUTPUT_B; + } ; + + /* capture/compare mode register 2 (input mode) */ + union + { + __IOM uint32_t CCM2_INPUT; + + struct + { + __IOM uint32_t CC3SEL : 2; + __IOM uint32_t IC3PSC : 2; + __IOM uint32_t IC3F : 4; + __IOM uint32_t CC4SEL : 2; + __IOM uint32_t IC4PSC : 2; + __IOM uint32_t IC4F : 4; + __IM uint32_t RESERVED1 : 16; + } CCM2_INPUT_B; + } ; + }; + + /* capture/compare enable register */ + union + { + __IOM uint32_t CCEN; + + struct + { + __IOM uint32_t CC1EN : 1; + __IOM uint32_t CC1POL : 1; + __IOM uint32_t CC1NEN : 1; + __IOM uint32_t CC1NPOL : 1; + __IOM uint32_t CC2EN : 1; + __IOM uint32_t CC2POL : 1; + __IOM uint32_t CC2NEN : 1; + __IOM uint32_t CC2NPOL : 1; + __IOM uint32_t CC3EN : 1; + __IOM uint32_t CC3POL : 1; + __IOM uint32_t CC3NEN : 1; + __IOM uint32_t CC3NPOL : 1; + __IOM uint32_t CC4EN : 1; + __IOM uint32_t CC4POL : 1; + __IM uint32_t RESERVED1 : 18; + } CCEN_B; + } ; + + /* counter */ + union + { + __IOM uint32_t CNT; + + struct + { + __IOM uint32_t CNT : 32; + } CNT_B; + } ; + + /* prescaler */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t PSC : 16; + __IM uint32_t RESERVED1 : 16; + } PSC_B; + } ; + + /* auto-reload register */ + union + { + __IOM uint32_t AUTORLD; + + struct + { + __IOM uint32_t AUTORLD : 32; + } AUTORLD_B; + } ; + + /* repetition counter register */ + union + { + __IOM uint32_t REPCNT; + + struct + { + __IOM uint32_t REPCNT : 8; + __IM uint32_t RESERVED1 : 24; + } REPCNT_B; + } ; + + /* capture/compare register 1 */ + union + { + __IOM uint32_t CC1; + + struct + { + __IOM uint32_t CC1 : 32; + } CC1_B; + } ; + + /* capture/compare register 2 */ + union + { + __IOM uint32_t CC2; + + struct + { + __IOM uint32_t CC2 : 32; + } CC2_B; + } ; + + /* capture/compare register 3 */ + union + { + __IOM uint32_t CC3; + + struct + { + __IOM uint32_t CC3 : 32; + } CC3_B; + } ; + + /* capture/compare register 4 */ + union + { + __IOM uint32_t CC4; + + struct + { + __IOM uint32_t CC4 : 32; + } CC4_B; + } ; + + /* break and dead-time register */ + union + { + __IOM uint32_t BDT; + + struct + { + __IOM uint32_t DTS : 8; + __IOM uint32_t LOCKCFG : 2; + __IOM uint32_t IMOS : 1; + __IOM uint32_t RMOS : 1; + __IOM uint32_t BRKEN : 1; + __IOM uint32_t BRKPOL : 1; + __IOM uint32_t AOEN : 1; + __IOM uint32_t MOEN : 1; + __IM uint32_t RESERVED1 : 16; + } BDT_B; + } ; + + /* DMA control register */ + union + { + __IOM uint32_t DCTRL; + + struct + { + __IOM uint32_t DBADDR : 5; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t DBLEN : 5; + __IM uint32_t RESERVED2 : 19; + } DCTRL_B; + } ; + + /* DMA address for full transfer */ + union + { + __IOM uint32_t DMADDR; + + struct + { + __IOM uint32_t DMADDR : 16; + __IM uint32_t RESERVED1 : 16; + } DMADDR_B; + } ; + + /* TMR14 Remap */ + union + { + __IOM uint32_t OPT; + + struct + { + __IOM uint32_t RMPSEL : 2; + __IM uint32_t RESERVED1 : 30; + } OPT_B; + } ; +} TMR_T; + +/** + * @brief Universal synchronous asynchronous receiver transmitter (USART) + */ + +typedef struct +{ + /* Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t UEN : 1; + __IOM uint32_t USWMEN : 1; + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + __IOM uint32_t IDLEIEN : 1; + __IOM uint32_t RXBNEIEN : 1; + __IOM uint32_t TXCIEN : 1; + __IOM uint32_t TXBEIEN : 1; + __IOM uint32_t PEIEN : 1; + __IOM uint32_t PCFG : 1; + __IOM uint32_t PCEN : 1; + __IOM uint32_t WUPMCFG : 1; + __IOM uint32_t DBLCFG0 : 1; + __IOM uint32_t RXMUTEEN : 1; + __IOM uint32_t CMIEN : 1; + __IOM uint32_t OSMCFG : 1; + __IOM uint32_t DDLTEN : 5; + __IOM uint32_t DLTEN : 5; + __IOM uint32_t RXTOIEN : 1; + __IOM uint32_t EOBIEN : 1; + __IOM uint32_t DBLCFG1 : 1; + __IM uint32_t RESERVED2 : 3; + } CTRL1_B; + } ; + + /* Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t ADDRLEN : 1; + __IOM uint32_t LBDLCFG : 1; + __IOM uint32_t LBDIEN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t LBCPOEN : 1; + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t CLKEN : 1; + __IOM uint32_t STOPCFG : 2; + __IOM uint32_t LINMEN : 1; + __IOM uint32_t SWAPEN : 1; + __IOM uint32_t RXINVEN : 1; + __IOM uint32_t TXINVEN : 1; + __IOM uint32_t BINVEN : 1; + __IOM uint32_t MSBFEN : 1; + __IOM uint32_t ABRDEN : 1; + __IOM uint32_t ABRDCFG : 2; + __IOM uint32_t RXTODEN : 1; + __IOM uint32_t ADDRL : 4; + __IOM uint32_t ADDRH : 4; + } CTRL2_B; + } ; + + /* Control register 3 */ + union + { + __IOM uint32_t CTRL3; + + struct + { + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t IREN : 1; + __IOM uint32_t IRLPEN : 1; + __IOM uint32_t HDEN : 1; + __IOM uint32_t SCNACKEN : 1; + __IOM uint32_t SCEN : 1; + __IOM uint32_t DMARXEN : 1; + __IOM uint32_t DMATXEN : 1; + __IOM uint32_t RTSEN : 1; + __IOM uint32_t CTSEN : 1; + __IOM uint32_t CTSIEN : 1; + __IOM uint32_t SAMCFG : 1; + __IOM uint32_t OVRDEDIS : 1; + __IOM uint32_t DDISRXEEN : 1; + __IOM uint32_t DEN : 1; + __IOM uint32_t DPCFG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t SCARCCFG : 3; + __IOM uint32_t WSIFLGSEL : 2; + __IOM uint32_t WSMIEN : 1; + __IM uint32_t RESERVED2 : 9; + } CTRL3_B; + } ; + + /* Baud rate register */ + union + { + __IOM uint32_t BR; + + struct + { + __IOM uint32_t FBR : 4; + __IOM uint32_t MBR : 12; + __IM uint32_t RESERVED1 : 16; + } BR_B; + } ; + + /* Guard time and prescaler */ + union + { + __IOM uint32_t GTPSC; + + struct + { + __IOM uint32_t PSC : 8; + __IOM uint32_t GRDT : 8; + __IM uint32_t RESERVED1 : 16; + } GTPSC_B; + } ; + + /* Receiver timeout register */ + union + { + __IOM uint32_t RXTO; + + struct + { + __IOM uint32_t RXTO : 24; + __IOM uint32_t BLEN : 8; + } RXTO_B; + } ; + + /* Request register */ + union + { + __IOM uint32_t REQUEST; + + struct + { + __IOM uint32_t ABRDQ : 1; + __IOM uint32_t TXBFQ : 1; + __IOM uint32_t MUTEQ : 1; + __IOM uint32_t RXDFQ : 1; + __IOM uint32_t TXDFQ : 1; + __IM uint32_t RESERVED1 : 27; + } REQUEST_B; + } ; + + /* Interrupt & status register */ + union + { + __IM uint32_t STS; + + struct + { + __IM uint32_t PEFLG : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t NEFLG : 1; + __IM uint32_t OVREFLG : 1; + __IM uint32_t IDLEFLG : 1; + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t TXCFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IM uint32_t LBDFLG : 1; + __IM uint32_t CTSFLG : 1; + __IM uint32_t CTSCFG : 1; + __IM uint32_t RXTOFLG : 1; + __IM uint32_t EOBFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t ABRDEFLG : 1; + __IM uint32_t ABRDFLG : 1; + __IM uint32_t BSYFLG : 1; + __IM uint32_t CMFLG : 1; + __IM uint32_t TXBFFLG : 1; + __IM uint32_t RXWFMUTE : 1; + __IM uint32_t WSMFLG : 1; + __IM uint32_t TXENACKFLG : 1; + __IM uint32_t RXENACKFLG : 1; + __IM uint32_t RESERVED2 : 9; + } STS_B; + } ; + + /* Interrupt flag clear register */ + union + { + __IOM uint32_t INTFCLR; + + struct + { + __IOM uint32_t PECLR : 1; + __IOM uint32_t FECLR : 1; + __IOM uint32_t NECLR : 1; + __IOM uint32_t OVRECLR : 1; + __IOM uint32_t IDLECLR : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t TXCCLR : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t LBDCLR : 1; + __IOM uint32_t CTSCLR : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t RXTOCLR : 1; + __IOM uint32_t EOBCLR : 1; + __IM uint32_t RESERVED4 : 4; + __IOM uint32_t CMCLR : 1; + __IM uint32_t RESERVED5 : 2; + __IOM uint32_t WSMCLR : 1; + __IM uint32_t RESERVED6 : 11; + } INTFCLR_B; + } ; + + /* Receive data register */ + union + { + __IM uint32_t RXDATA; + + struct + { + __IM uint32_t RXDATA : 9; + __IM uint32_t RESERVED1 : 23; + } RXDATA_B; + } ; + + /* Transmit data register */ + union + { + __IOM uint32_t TXDATA; + + struct + { + __IOM uint32_t TXDATA : 9; + __IM uint32_t RESERVED1 : 23; + } TXDATA_B; + } ; +} USART_T; + +/** + * @brief Window watchdog (WWDT) + */ + +typedef struct +{ + union + { + /* Control register */ + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t CNT : 7; + __IOM uint32_t WWDTEN : 1; + __IM uint32_t RESERVED1 : 24; + } CTRL_B; + } ; + + union + { + /* Configuration register */ + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t WIN : 7; + __IOM uint32_t TBPSC : 2; + __IOM uint32_t EWIEN : 1; + __IM uint32_t RESERVED1 : 22; + } CFG_B; + } ; + + union + { + /* Status register */ + __IOM uint32_t STS; + + struct + { + __IOM uint32_t EWIFLG : 1; + __IM uint32_t RESERVED1 : 31; + } STS_B; + } ; +} WWDT_T; + +/** + * @brief Universal Serial Bus Device (USB) + */ + +typedef union +{ + __IOM uint32_t EP; + + struct + { + __IOM uint32_t ADDR : 4; + __IOM uint32_t TXSTS : 2; + __IOM uint32_t TXDTOG : 1; + __IOM uint32_t CTFT : 1; + __IOM uint32_t KIND : 1; + __IOM uint32_t TYPE : 2; + __IOM uint32_t SETUP : 1; + __IOM uint32_t RXSTS : 2; + __IOM uint32_t RXDTOG : 1; + __IOM uint32_t CTFR : 1; + __IM uint32_t RESERVED : 16; + } EP_B; +} USB_EP_REG_T; + +typedef struct +{ + /* Endpoint */ + USB_EP_REG_T EP[8]; + + __IOM uint32_t RESERVED1[8]; + + /** + * @brief Control register + */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t FORRST : 1; + __IOM uint32_t PWRDOWN : 1; + __IOM uint32_t LPWREN : 1; + __IOM uint32_t FORSUS : 1; + __IOM uint32_t WKUPREQ : 1; + __IOM uint32_t L1WKUPREQ : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t L1STSREQIM : 1; + __IOM uint32_t ESOFIEN : 1; + __IOM uint32_t SOFIEN : 1; + __IOM uint32_t RSTIEN : 1; + __IOM uint32_t SUSIEN : 1; + __IOM uint32_t WKUPIEN : 1; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t PMAOUIEN : 1; + __IOM uint32_t CTRIEN : 1; + __IM uint32_t RESERVED2 : 16; + } CTRL_B; + }; + + /** + * @brief Interrupt status register + */ + union + { + __IOM uint32_t INTSTS; + + struct + { + __IOM uint32_t EPID : 4; + __IOM uint32_t DOT : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t L1STSREQ : 1; + __IOM uint32_t ESOFFLG : 1; + __IOM uint32_t SOFFLG : 1; + __IOM uint32_t RSTREQ : 1; + __IOM uint32_t SUSREQ : 1; + __IOM uint32_t WUPREQ : 1; + __IOM uint32_t ERRFLG : 1; + __IOM uint32_t PMOFLG : 1; + __IOM uint32_t CTFLG : 1; + __IM uint32_t RESERVED2 : 16; + } INTSTS_B; + }; + + /** + * @brief Frame number register + */ + union + { + __IOM uint32_t FRANUM; + + struct + { + __IOM uint32_t FRANUM : 11; + __IOM uint32_t LSOFNUM : 2; + __IOM uint32_t LOCK : 1; + __IOM uint32_t RXDMSTS : 1; + __IOM uint32_t RXDPSTS : 1; + __IM uint32_t RESERVED : 16; + } FRANUM_B; + }; + + /** + * @brief Device address register + */ + union + { + __IOM uint32_t ADDR; + + struct + { + __IOM uint32_t ADDR : 7; + __IOM uint32_t USBDEN : 1; + __IM uint32_t RESERVED : 24; + } ADDR_B; + }; + + /** + * @brief Buffer table address register + */ + union + { + __IOM uint32_t BUFFTB; + + struct + { + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t BUFFTB : 13; + __IM uint32_t RESERVED2 : 16; + } BUFFTB_B; + }; + + /** + * @brief LPM control and status regiter + */ + union + { + __IOM uint32_t LPMCTRLSTS; + + struct + { + __IOM uint32_t LPMEN : 1; + __IOM uint32_t LPMACKEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t REMWAKE : 1; + __IOM uint32_t BESL : 4; + __IM uint32_t RESERVED2 : 24; + } LPMCTRLSTS_B; + }; + + /** + * @brief Battery charging detector regiter + */ + union + { + __IOM uint32_t BCD; + + struct + { + __IOM uint32_t BCDEN : 1; + __IOM uint32_t DCDEN : 1; + __IOM uint32_t PDEN : 1; + __IOM uint32_t SDEN : 1; + __IOM uint32_t DCDFLG : 1; + __IOM uint32_t PDFLG : 1; + __IOM uint32_t SDFLG : 1; + __IOM uint32_t DMPUDFLG : 1; + __IM uint32_t RESERVED1 : 7; + __IOM uint32_t DPPUCTRL : 1; + __IM uint32_t RESERVED2 : 16; + } BCD_B; + }; +} USBD_T; + +/**@} end of group Peripheral_registers_structures*/ + +/** @defgroup Peripheral_memory_map + @{ +*/ + +/*@} end of group Device_Register*/ + +/* FMC base address in the alias region */ +#define FMC_BASE ((uint32_t)0x08000000) +/* SRAM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) +/* Peripheral base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) + +/* Peripheral memory map */ +#define APBPERIPH_BASE PERIPH_BASE +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) + +#define TMR2_BASE (APBPERIPH_BASE + 0x00000000) +#define TMR3_BASE (APBPERIPH_BASE + 0x00000400) +#define TMR6_BASE (APBPERIPH_BASE + 0x00001000) +#define TMR7_BASE (APBPERIPH_BASE + 0x00001400) +#define TMR14_BASE (APBPERIPH_BASE + 0x00002000) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800) +#define WWDT_BASE (APBPERIPH_BASE + 0x00002C00) +#define IWDT_BASE (APBPERIPH_BASE + 0x00003000) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00) +#define USART5_BASE (APBPERIPH_BASE + 0x00005000) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800) +#define USBD_BASE (APBPERIPH_BASE + 0x00005C00) +#define CAN_BASE (APBPERIPH_BASE + 0x00006400) +#define CRS_BASE (APBPERIPH_BASE + 0x00006C00) +#define PMU_BASE (APBPERIPH_BASE + 0x00007000) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400) +#define CEC_BASE (APBPERIPH_BASE + 0x00007800) + +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) +#define COMP_BASE (APBPERIPH_BASE + 0x0001001C) +#define EINT_BASE (APBPERIPH_BASE + 0x00010400) +#define USART6_BASE (APBPERIPH_BASE + 0x00011400) +#define USART7_BASE (APBPERIPH_BASE + 0x00011800) +#define USART8_BASE (APBPERIPH_BASE + 0x00011C00) +#define ADC_BASE (APBPERIPH_BASE + 0x00012400) +#define TMR1_BASE (APBPERIPH_BASE + 0x00012C00) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800) +#define TMR15_BASE (APBPERIPH_BASE + 0x00014000) +#define TMR16_BASE (APBPERIPH_BASE + 0x00014400) +#define TMR17_BASE (APBPERIPH_BASE + 0x00014800) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) +#define DMA1_CHANNEL_1_BASE (DMA1_BASE + 0x00000008) +#define DMA1_CHANNEL_2_BASE (DMA1_BASE + 0x0000001C) +#define DMA1_CHANNEL_3_BASE (DMA1_BASE + 0x00000030) +#define DMA1_CHANNEL_4_BASE (DMA1_BASE + 0x00000044) +#define DMA1_CHANNEL_5_BASE (DMA1_BASE + 0x00000058) +#define DMA1_CHANNEL_6_BASE (DMA1_BASE + 0x0000006C) +#define DMA1_CHANNEL_7_BASE (DMA1_BASE + 0x00000080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400) +#define DMA2_CHANNEL_1_BASE (DMA2_BASE + 0x00000008) +#define DMA2_CHANNEL_2_BASE (DMA2_BASE + 0x0000001C) +#define DMA2_CHANNEL_3_BASE (DMA2_BASE + 0x00000030) +#define DMA2_CHANNEL_4_BASE (DMA2_BASE + 0x00000044) +#define DMA2_CHANNEL_5_BASE (DMA2_BASE + 0x00000058) + +#define RCM_BASE (AHBPERIPH_BASE + 0x00001000) +#define FMC_R_BASE (AHBPERIPH_BASE + 0x00002000) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) +#define TSC_BASE (AHBPERIPH_BASE + 0x00004000) +#define OB_BASE ((uint32_t)0x1FFFF800) + +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400) + +/**@} end of group Peripheral_memory_map*/ + +/** @defgroup Peripheral_declaration + @{ +*/ + +#define ADC ((ADC_T*) ADC_BASE) +#define CAN ((CAN_T*) CAN_BASE) +#define CEC ((CEC_T*) CEC_BASE) +#define CRS ((CRS_T*) CRS_BASE) +#define CRC ((CRC_T*) CRC_BASE) +#define COMP ((COMP_T*) COMP_BASE) +#define DAC ((DAC_T*) DAC_BASE) +#define DBG ((DBG_T*) DBG_BASE) +#define EINT ((EINT_T*) EINT_BASE) +#define FMC ((FMC_T*) FMC_R_BASE) +#define I2C1 ((I2C_T*) I2C1_BASE) +#define I2C2 ((I2C_T*) I2C2_BASE) +#define IWDT ((IWDT_T*) IWDT_BASE) +#define OB ((OB_T*) OB_BASE) +#define PMU ((PMU_T*) PMU_BASE) +#define RCM ((RCM_T*) RCM_BASE) +#define RTC ((RTC_T*) RTC_BASE) +#define SPI1 ((SPI_T*) SPI1_BASE) +#define SPI2 ((SPI_T*) SPI2_BASE) +#define SYSCFG ((SYSCFG_T*) SYSCFG_BASE) +#define TSC ((TSC_T*) TSC_BASE) +#define USART1 ((USART_T*) USART1_BASE) +#define USART2 ((USART_T*) USART2_BASE) +#define USART3 ((USART_T*) USART3_BASE) +#define USART4 ((USART_T*) USART4_BASE) +#define USART5 ((USART_T*) USART5_BASE) +#define USART6 ((USART_T*) USART6_BASE) +#define USART7 ((USART_T*) USART7_BASE) +#define USART8 ((USART_T*) USART8_BASE) +#define USBD ((USBD_T*) USBD_BASE) +#define WWDT ((WWDT_T*) WWDT_BASE) + +#define DMA1 ((DMA_T*) DMA1_BASE) +#define DMA1_CHANNEL_1 ((DMA_CHANNEL_T*) DMA1_CHANNEL_1_BASE) +#define DMA1_CHANNEL_2 ((DMA_CHANNEL_T*) DMA1_CHANNEL_2_BASE) +#define DMA1_CHANNEL_3 ((DMA_CHANNEL_T*) DMA1_CHANNEL_3_BASE) +#define DMA1_CHANNEL_4 ((DMA_CHANNEL_T*) DMA1_CHANNEL_4_BASE) +#define DMA1_CHANNEL_5 ((DMA_CHANNEL_T*) DMA1_CHANNEL_5_BASE) +#define DMA1_CHANNEL_6 ((DMA_CHANNEL_T*) DMA1_CHANNEL_6_BASE) +#define DMA1_CHANNEL_7 ((DMA_CHANNEL_T*) DMA1_CHANNEL_7_BASE) +#define DMA2 ((DMA_T *) DMA2_BASE) +#define DMA2_CHANNEL_1 ((DMA_CHANNEL_T *) DMA2_CHANNEL_1_BASE) +#define DMA2_CHANNEL_2 ((DMA_CHANNEL_T *) DMA2_CHANNEL_2_BASE) +#define DMA2_CHANNEL_3 ((DMA_CHANNEL_T *) DMA2_CHANNEL_3_BASE) +#define DMA2_CHANNEL_4 ((DMA_CHANNEL_T *) DMA2_CHANNEL_4_BASE) +#define DMA2_CHANNEL_5 ((DMA_CHANNEL_T *) DMA2_CHANNEL_5_BASE) + +#define GPIOF ((GPIO_T*) GPIOF_BASE) +#define GPIOE ((GPIO_T*) GPIOE_BASE) +#define GPIOD ((GPIO_T*) GPIOD_BASE) +#define GPIOC ((GPIO_T*) GPIOC_BASE) +#define GPIOB ((GPIO_T*) GPIOB_BASE) +#define GPIOA ((GPIO_T*) GPIOA_BASE) + +#define TMR1 ((TMR_T*) TMR1_BASE) +#define TMR2 ((TMR_T*) TMR2_BASE) +#define TMR3 ((TMR_T*) TMR3_BASE) +#define TMR6 ((TMR_T*) TMR6_BASE) +#define TMR7 ((TMR_T*) TMR7_BASE) +#define TMR14 ((TMR_T*) TMR14_BASE) +#define TMR15 ((TMR_T*) TMR15_BASE) +#define TMR16 ((TMR_T*) TMR16_BASE) +#define TMR17 ((TMR_T*) TMR17_BASE) + +/**@} end of group Peripheral_declaration*/ + +/** @defgroup Exported_Macros + @{ +*/ + +/* Define one bit mask */ +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/**@} end of group Exported_Macros*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __APM32F0xx_H */ + +/**@} end of group APM32F0xx */ +/**@} end of group CMSIS */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Include/system_apm32f0xx.h b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Include/system_apm32f0xx.h new file mode 100644 index 0000000000..8547132b3b --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Include/system_apm32f0xx.h @@ -0,0 +1,86 @@ +/*! + * @file system_apm32f0xx.h + * + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File + * + * @details This file contains the system clock configuration for APM32F0xx devices. + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __SYSTEM_APM32F0XX_H +#define __SYSTEM_APM32F0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup CMSIS + @{ +*/ + +/** @addtogroup APM32F0xx_System + @{ +*/ + +/** @defgroup System_Macros Macros + @{ + */ + +/**@} end of group System_Macros */ + +/** @defgroup System_Enumerations Enumerations + @{ + */ + +/**@} end of group System_Enumerations */ + +/** @defgroup System_Structures Structures + @{ + */ + +/**@} end of group System_Structures */ + +/** @defgroup System_Variables Variables + @{ + */ + +/* System Clock Frequency (Core Clock) */ +extern uint32_t SystemCoreClock; + +/**@} end of group System_Variables */ + +/** @defgroup System_Functions Functions + @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_APM32F0XX_H */ + +/**@} end of group System_Functions */ +/**@} end of group APM32F0xx_System */ +/**@} end of group CMSIS */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f030.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f030.s new file mode 100644 index 0000000000..1398c772e6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f030.s @@ -0,0 +1,239 @@ +;/*! +; * @file startup_apm32f030.s +; * +; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f030 +; * +; * @version V1.0.2 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_IRQHandler ; RTC through EINT Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCM + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD 0 ; Reserved + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_6_IRQHandler ; USART3,USART4,USART5,USART6 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_1_IRQHandler [WEAK] + EXPORT EINT2_3_IRQHandler [WEAK] + EXPORT EINT4_15_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_3_IRQHandler [WEAK] + EXPORT DMA1_CH4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR6_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT TMR14_IRQHandler [WEAK] + EXPORT TMR15_IRQHandler [WEAK] + EXPORT TMR16_IRQHandler [WEAK] + EXPORT TMR17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_6_IRQHandler [WEAK] + + +WWDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_IRQHandler +EINT0_1_IRQHandler +EINT2_3_IRQHandler +EINT4_15_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_3_IRQHandler +DMA1_CH4_5_IRQHandler +ADC1_IRQHandler +TMR1_BRK_UP_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR3_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +TMR14_IRQHandler +TMR15_IRQHandler +TMR16_IRQHandler +TMR17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_6_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f051.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f051.s new file mode 100644 index 0000000000..f870c5fba1 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f051.s @@ -0,0 +1,246 @@ +;/*! +; * @file startup_apm32f051.s +; * +; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f030 +; * +; * @version V1.0.2 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD RTC_IRQHandler ; RTC through EINT Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCM + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD 0 ; Reserved + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_1_IRQHandler [WEAK] + EXPORT EINT2_3_IRQHandler [WEAK] + EXPORT EINT4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_3_IRQHandler [WEAK] + EXPORT DMA1_CH4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR6_DAC_IRQHandler [WEAK] + EXPORT TMR14_IRQHandler [WEAK] + EXPORT TMR15_IRQHandler [WEAK] + EXPORT TMR16_IRQHandler [WEAK] + EXPORT TMR17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDT_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_IRQHandler +EINT0_1_IRQHandler +EINT2_3_IRQHandler +EINT4_15_IRQHandler +TSC_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_3_IRQHandler +DMA1_CH4_5_IRQHandler +ADC1_COMP_IRQHandler +TMR1_BRK_UP_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR6_DAC_IRQHandler +TMR14_IRQHandler +TMR15_IRQHandler +TMR16_IRQHandler +TMR17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +>>>>>>> .r17560 diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f070.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f070.s new file mode 100644 index 0000000000..97c729bd2f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f070.s @@ -0,0 +1,243 @@ +;/*! +; * @file startup_apm32f070.s +; * +; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f070 +; * +; * @version V1.0.2 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_IRQHandler ; RTC through EINT Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCM + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4, Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD 0 ; Reserved + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD 0 ; Reserved + DCD USBD_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_1_IRQHandler [WEAK] + EXPORT EINT2_3_IRQHandler [WEAK] + EXPORT EINT4_15_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_3_IRQHandler [WEAK] + EXPORT DMA1_CH4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR6_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT TMR14_IRQHandler [WEAK] + EXPORT TMR15_IRQHandler [WEAK] + EXPORT TMR16_IRQHandler [WEAK] + EXPORT TMR17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + + +WWDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_IRQHandler +EINT0_1_IRQHandler +EINT2_3_IRQHandler +EINT4_15_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_3_IRQHandler +DMA1_CH4_5_IRQHandler +ADC1_IRQHandler +TMR1_BRK_UP_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR3_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +TMR14_IRQHandler +TMR15_IRQHandler +TMR16_IRQHandler +TMR17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_IRQHandler +USBD_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f071.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f071.s new file mode 100644 index 0000000000..246a28183f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f071.s @@ -0,0 +1,248 @@ +;/*! +; * @file startup_apm32f071.s +; * +; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f071 +; * +; * @version V1.0.2 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect + DCD RTC_IRQHandler ; RTC through EINT Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_CRS_IRQHandler ; RCM and CRS + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_CRS_IRQHandler [WEAK] + EXPORT EINT0_1_IRQHandler [WEAK] + EXPORT EINT2_3_IRQHandler [WEAK] + EXPORT EINT4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_3_IRQHandler [WEAK] + EXPORT DMA1_CH4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR6_DAC_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT TMR14_IRQHandler [WEAK] + EXPORT TMR15_IRQHandler [WEAK] + EXPORT TMR16_IRQHandler [WEAK] + EXPORT TMR17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDT_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_CRS_IRQHandler +EINT0_1_IRQHandler +EINT2_3_IRQHandler +EINT4_15_IRQHandler +TSC_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_3_IRQHandler +DMA1_CH4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +TMR1_BRK_UP_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR6_DAC_IRQHandler +TMR7_IRQHandler +TMR14_IRQHandler +TMR15_IRQHandler +TMR16_IRQHandler +TMR17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END \ No newline at end of file diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f072.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f072.s new file mode 100644 index 0000000000..b6bdfa2f26 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f072.s @@ -0,0 +1,251 @@ +;/*! +; * @file startup_apm32f072.s +; * +; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f072 +; * +; * @version V1.0.2 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect + DCD RTC_IRQHandler ; RTC through EINT Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_CRS_IRQHandler ; RCM and CRS + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USBD_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_CRS_IRQHandler [WEAK] + EXPORT EINT0_1_IRQHandler [WEAK] + EXPORT EINT2_3_IRQHandler [WEAK] + EXPORT EINT4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_3_IRQHandler [WEAK] + EXPORT DMA1_CH4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR6_DAC_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT TMR14_IRQHandler [WEAK] + EXPORT TMR15_IRQHandler [WEAK] + EXPORT TMR16_IRQHandler [WEAK] + EXPORT TMR17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + + +WWDT_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_CRS_IRQHandler +EINT0_1_IRQHandler +EINT2_3_IRQHandler +EINT4_15_IRQHandler +TSC_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_3_IRQHandler +DMA1_CH4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +TMR1_BRK_UP_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR6_DAC_IRQHandler +TMR7_IRQHandler +TMR14_IRQHandler +TMR15_IRQHandler +TMR16_IRQHandler +TMR17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_IRQHandler +CEC_CAN_IRQHandler +USBD_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END \ No newline at end of file diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f091.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f091.s new file mode 100644 index 0000000000..604d39f181 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/arm/startup_apm32f091.s @@ -0,0 +1,248 @@ +;/*! +; * @file startup_apm32f091.s +; * +; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f072 +; * +; * @version V1.0.2 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect + DCD RTC_IRQHandler ; RTC through EINT Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_CRS_IRQHandler ; RCM and CRS + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_DMA2_CH1_2_IRQHandler ; DMA1 Channel 2 and 3 DMA2 Channel 1 and 2 + DCD DMA1_CH4_7_DMA2_CH3_5_IRQHandler ; DMA1 Channel 4 to 7 DMA2 Channel 3 to 5 Interrupts + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8 + DCD CEC_CAN_IRQHandler ; CEC and CAN + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_CRS_IRQHandler [WEAK] + EXPORT EINT0_1_IRQHandler [WEAK] + EXPORT EINT2_3_IRQHandler [WEAK] + EXPORT EINT4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_3_DMA2_CH1_2_IRQHandler [WEAK] + EXPORT DMA1_CH4_7_DMA2_CH3_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR6_DAC_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT TMR14_IRQHandler [WEAK] + EXPORT TMR15_IRQHandler [WEAK] + EXPORT TMR16_IRQHandler [WEAK] + EXPORT TMR17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_8_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + + +WWDT_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_CRS_IRQHandler +EINT0_1_IRQHandler +EINT2_3_IRQHandler +EINT4_15_IRQHandler +TSC_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_3_DMA2_CH1_2_IRQHandler +DMA1_CH4_7_DMA2_CH3_5_IRQHandler +ADC1_COMP_IRQHandler +TMR1_BRK_UP_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR6_DAC_IRQHandler +TMR7_IRQHandler +TMR14_IRQHandler +TMR15_IRQHandler +TMR16_IRQHandler +TMR17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_8_IRQHandler +CEC_CAN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xx6.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xx6.ld new file mode 100644 index 0000000000..836289fb0b --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xx6.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F03xx6.ld + * + * @brief Linker script for APM32F03xx6 Device with + * 32KByte FLASH, 4KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0008000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00001000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20001000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xx8.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xx8.ld new file mode 100644 index 0000000000..f7fdf162c6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xx8.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F03xx8.ld + * + * @brief Linker script for APM32F03xx8 Device with + * 64KByte FLASH, 8KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0010000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00002000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20002000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xxC.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xxC.ld new file mode 100644 index 0000000000..11f5098091 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F03xxC.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F03xxC.ld.ld + * + * @brief Linker script for APM32F03xxC.ld Device with + * 256KByte FLASH, 32KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0040000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00008000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20008000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F05xx6.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F05xx6.ld new file mode 100644 index 0000000000..761320e139 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F05xx6.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F05xx6.ld + * + * @brief Linker script for APM32F05xx6 Device with + * 32KByte FLASH, 8KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0008000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00002000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20002000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F05xx8.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F05xx8.ld new file mode 100644 index 0000000000..6af71d5157 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F05xx8.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F05xx8.ld + * + * @brief Linker script for APM32F05xx8 Device with + * 64KByte FLASH, 8KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0010000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00002000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20002000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F07xx8.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F07xx8.ld new file mode 100644 index 0000000000..3a5be775ec --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F07xx8.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F07xx8.ld + * + * @brief Linker script for APM32F07xx8 Device with + * 64KByte FLASH, 16KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0010000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00004000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20004000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F07xxB.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F07xxB.ld new file mode 100644 index 0000000000..aa13a33e9c --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F07xxB.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F07xxB.ld + * + * @brief Linker script for APM32F07xxB Device with + * 128KByte FLASH, 32KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0020000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00004000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20004000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F09xxB.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F09xxB.ld new file mode 100644 index 0000000000..ffe63e368f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F09xxB.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F09xxB.ld + * + * @brief Linker script for APM32F09xxB Device with + * 128KByte FLASH, 32KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0020000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00008000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20008000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F09xxC.ld b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F09xxC.ld new file mode 100644 index 0000000000..947d8f33da --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/gcc_APM32F09xxC.ld @@ -0,0 +1,162 @@ +/*! + * @file gcc_APM32F09xxC.ld + * + * @brief Linker script for APM32F09xxC Device with + * 256KByte FLASH, 32KByte RAM + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0040000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00008000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20008000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size + RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f030.S b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f030.S new file mode 100644 index 0000000000..dbe06bca8d --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f030.S @@ -0,0 +1,247 @@ +/*! + * @file startup_apm32f030.S + * + * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f030 + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +// Reset handler routine +Reset_Handler: +// User Stack and Heap initialization + ldr r0, =_end_stack + mov sp, r0 + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + +L_loop3: + b L_loop3 + +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M0 Plus. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + .word _end_stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word 0 // Reserved + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word WWDT_IRQHandler // Window Watchdog + .word 0 // Reserved + .word RTC_IRQHandler // RTC through EINT Line + .word FLASH_IRQHandler // FLASH + .word RCM_IRQHandler // RCM + .word EINT0_1_IRQHandler // EINT Line 0 and 1 + .word EINT2_3_IRQHandler // EINT Line 2 and 3 + .word EINT4_15_IRQHandler // EINT Line 4 to 15 + .word 0 // Reserved + .word DMA1_CH1_IRQHandler // DMA1 Channel 1 + .word DMA1_CH2_3_IRQHandler // DMA1 Channel 2 and Channel 3 + .word DMA1_CH4_5_IRQHandler // DMA1 Channel 4 and Channel 5 + .word ADC1_IRQHandler // ADC1 + .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word 0 // Reserved + .word TMR3_IRQHandler // TMR3 + .word TMR6_IRQHandler // TMR6 + .word TMR7_IRQHandler // TMR7 + .word TMR14_IRQHandler // TMR14 + .word TMR15_IRQHandler // TMR15 + .word TMR16_IRQHandler // TMR16 + .word TMR17_IRQHandler // TMR17 + .word I2C1_IRQHandler // I2C1 + .word I2C2_IRQHandler // I2C2 + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_6_IRQHandler // USART3,USART4,USART5,USART6 + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_IRQHandler + .thumb_set RCM_IRQHandler,Default_Handler + + .weak EINT0_1_IRQHandler + .thumb_set EINT0_1_IRQHandler,Default_Handler + + .weak EINT2_3_IRQHandler + .thumb_set EINT2_3_IRQHandler,Default_Handler + + .weak EINT4_15_IRQHandler + .thumb_set EINT4_15_IRQHandler,Default_Handler + + .weak DMA1_CH1_IRQHandler + .thumb_set DMA1_CH1_IRQHandler,Default_Handler + + .weak DMA1_CH2_3_IRQHandler + .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler + + .weak DMA1_CH4_5_IRQHandler + .thumb_set DMA1_CH4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TMR1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR6_IRQHandler + .thumb_set TMR6_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak TMR14_IRQHandler + .thumb_set TMR14_IRQHandler,Default_Handler + + .weak TMR15_IRQHandler + .thumb_set TMR15_IRQHandler,Default_Handler + + .weak TMR16_IRQHandler + .thumb_set TMR16_IRQHandler,Default_Handler + + .weak TMR17_IRQHandler + .thumb_set TMR17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_6_IRQHandler + .thumb_set USART3_6_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f051.S b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f051.S new file mode 100644 index 0000000000..c3302e17d6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f051.S @@ -0,0 +1,254 @@ +/*! + * @file startup_apm32f051.S + * + * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f051 + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +// Reset handler routine +Reset_Handler: +// User Stack and Heap initialization + ldr r0, =_end_stack + mov sp, r0 + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + +L_loop3: + b L_loop3 + +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M0 Plus. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + .word _end_stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word 0 // Reserved + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word WWDT_IRQHandler // Window Watchdog + .word PVD_IRQHandler // PVD through EINT Line detect + .word RTC_IRQHandler // RTC through EINT Line + .word FLASH_IRQHandler // FLASH + .word RCM_IRQHandler // RCM + .word EINT0_1_IRQHandler // EINT Line 0 and 1 + .word EINT2_3_IRQHandler // EINT Line 2 and 3 + .word EINT4_15_IRQHandler // EINT Line 4 to 15 + .word TSC_IRQHandler // TSC + .word DMA1_CH1_IRQHandler // DMA1 Channel 1 + .word DMA1_CH2_3_IRQHandler // DMA1 Channel 2 and Channel 3 + .word DMA1_CH4_5_IRQHandler // DMA1 Channel 4 and Channel 5 + .word ADC1_IRQHandler // ADC1 + .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR6_DAC_IRQHandler // TMR6 and DAC + .word 0 // Reserved + .word TMR14_IRQHandler // TMR14 + .word TMR15_IRQHandler // TMR15 + .word TMR16_IRQHandler // TMR16 + .word TMR17_IRQHandler // TMR17 + .word I2C1_IRQHandler // I2C1 + .word I2C2_IRQHandler // I2C2 + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word 0 // Reserved + .word CEC_IRQHandler // CEC + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_IRQHandler + .thumb_set RCM_IRQHandler,Default_Handler + + .weak EINT0_1_IRQHandler + .thumb_set EINT0_1_IRQHandler,Default_Handler + + .weak EINT2_3_IRQHandler + .thumb_set EINT2_3_IRQHandler,Default_Handler + + .weak EINT4_15_IRQHandler + .thumb_set EINT4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_CH1_IRQHandler + .thumb_set DMA1_CH1_IRQHandler,Default_Handler + + .weak DMA1_CH2_3_IRQHandler + .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler + + .weak DMA1_CH4_5_IRQHandler + .thumb_set DMA1_CH4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TMR1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR6_DAC_IRQHandler + .thumb_set TMR6_DAC_IRQHandler,Default_Handler + + .weak TMR14_IRQHandler + .thumb_set TMR14_IRQHandler,Default_Handler + + .weak TMR15_IRQHandler + .thumb_set TMR15_IRQHandler,Default_Handler + + .weak TMR16_IRQHandler + .thumb_set TMR16_IRQHandler,Default_Handler + + .weak TMR17_IRQHandler + .thumb_set TMR17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f070.S b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f070.S new file mode 100644 index 0000000000..e2ab3ed3ab --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f070.S @@ -0,0 +1,252 @@ +/*! + * @file startup_apm32f070.S + * + * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f070 + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +// Reset handler routine +Reset_Handler: +// User Stack and Heap initialization + ldr r0, =_end_stack + mov sp, r0 + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + +L_loop3: + b L_loop3 + +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M0 Plus. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + .word _end_stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word 0 // Reserved + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word WWDT_IRQHandler // Window Watchdog + .word 0 // Reserved + .word RTC_IRQHandler // RTC through EINT Line + .word FLASH_IRQHandler // FLASH + .word RCM_IRQHandler // RCM + .word EINT0_1_IRQHandler // EINT Line 0 and 1 + .word EINT2_3_IRQHandler // EINT Line 2 and 3 + .word EINT4_15_IRQHandler // EINT Line 4 to 15 + .word 0 // Reserved + .word DMA1_CH1_IRQHandler // DMA1 Channel 1 + .word DMA1_CH2_3_IRQHandler // DMA1 Channel 2 and Channel 3 + .word DMA1_CH4_5_IRQHandler // DMA1 Channel 4 and Channel 5 + .word ADC1_IRQHandler // ADC1 + .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word 0 // Reserved + .word TMR3_IRQHandler // TMR3 + .word TMR6_IRQHandler // TMR6 + .word TMR7_IRQHandler // TMR7 + .word TMR14_IRQHandler // TMR14 + .word TMR15_IRQHandler // TMR15 + .word TMR16_IRQHandler // TMR16 + .word TMR17_IRQHandler // TMR17 + .word I2C1_IRQHandler // I2C1 + .word I2C2_IRQHandler // I2C2 + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_4_IRQHandler // USART3, USART4 + .word 0 // Reserved + word USBD_IRQHandler // USB + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_IRQHandler + .thumb_set RCM_IRQHandler,Default_Handler + + .weak EINT0_1_IRQHandler + .thumb_set EINT0_1_IRQHandler,Default_Handler + + .weak EINT2_3_IRQHandler + .thumb_set EINT2_3_IRQHandler,Default_Handler + + .weak EINT4_15_IRQHandler + .thumb_set EINT4_15_IRQHandler,Default_Handler + + .weak DMA1_CH1_IRQHandler + .thumb_set DMA1_CH1_IRQHandler,Default_Handler + + .weak DMA1_CH2_3_IRQHandler + .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler + + .weak DMA1_CH4_5_IRQHandler + .thumb_set DMA1_CH4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TMR1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR6_IRQHandler + .thumb_set TMR6_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak TMR14_IRQHandler + .thumb_set TMR14_IRQHandler,Default_Handler + + .weak TMR15_IRQHandler + .thumb_set TMR15_IRQHandler,Default_Handler + + .weak TMR16_IRQHandler + .thumb_set TMR16_IRQHandler,Default_Handler + + .weak TMR17_IRQHandler + .thumb_set TMR17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak USBD_IRQHandler + .thumb_set USBD_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f071.S b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f071.S new file mode 100644 index 0000000000..63483afbb6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f071.S @@ -0,0 +1,261 @@ +/*! + * @file startup_apm32f071.S + * + * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f071 + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +// Reset handler routine +Reset_Handler: +// User Stack and Heap initialization + ldr r0, =_end_stack + mov sp, r0 + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + +L_loop3: + b L_loop3 + +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M0 Plus. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + .word _end_stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word 0 // Reserved + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word WWDT_IRQHandler // Window Watchdog + .word PVD_VDDIO2_IRQHandler // PVD and VDDIO2 through EINT Line detect + .word RTC_IRQHandler // RTC through EINT Line + .word FLASH_IRQHandler // FLASH + .word RCM_CRS_IRQHandler // RCM and CRS + .word EINT0_1_IRQHandler // EINT Line 0 and 1 + .word EINT2_3_IRQHandler // EINT Line 2 and 3 + .word EINT4_15_IRQHandler // EINT Line 4 to 15 + .word TSC_IRQHandler // TSC + .word DMA1_CH1_IRQHandler // DMA1 Channel 1 + .word DMA1_CH2_3_IRQHandler // DMA1 Channel 2 and Channel 3 + .word DMA1_CH4_5_6_7_IRQHandler // DMA1 Channel 4 and Channel 5 + .word ADC1_COMP_IRQHandler // ADC1 , COMP1 and COMP2 + .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR6_DAC_IRQHandler // TMR6 and DAC + .word TMR7_IRQHandler // TMR7 + .word TMR14_IRQHandler // TMR14 + .word TMR15_IRQHandler // TMR15 + .word TMR16_IRQHandler // TMR16 + .word TMR17_IRQHandler // TMR17 + .word I2C1_IRQHandler // I2C1 + .word I2C2_IRQHandler // I2C2 + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_4_IRQHandler // USART3, USART4 + .word CEC_IRQHandler // CEC and CAN + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_CRS_IRQHandler + .thumb_set RCM_CRS_IRQHandler,Default_Handler + + .weak EINT0_1_IRQHandler + .thumb_set EINT0_1_IRQHandler,Default_Handler + + .weak EINT2_3_IRQHandler + .thumb_set EINT2_3_IRQHandler,Default_Handler + + .weak EINT4_15_IRQHandler + .thumb_set EINT4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_CH1_IRQHandler + .thumb_set DMA1_CH1_IRQHandler,Default_Handler + + .weak DMA1_CH2_3_IRQHandler + .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler + + .weak DMA1_CH4_5_6_7_IRQHandler + .thumb_set DMA1_CH4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TMR1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR6_DAC_IRQHandler + .thumb_set TMR6_DAC_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak TMR14_IRQHandler + .thumb_set TMR14_IRQHandler,Default_Handler + + .weak TMR15_IRQHandler + .thumb_set TMR15_IRQHandler,Default_Handler + + .weak TMR16_IRQHandler + .thumb_set TMR16_IRQHandler,Default_Handler + + .weak TMR17_IRQHandler + .thumb_set TMR17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f072.S b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f072.S new file mode 100644 index 0000000000..80b0a4275a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f072.S @@ -0,0 +1,264 @@ +/*! + * @file startup_apm32f072.S + * + * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f072 + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +// Reset handler routine +Reset_Handler: +// User Stack and Heap initialization + ldr r0, =_end_stack + mov sp, r0 + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + +L_loop3: + b L_loop3 + +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M0 Plus. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + .word _end_stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word 0 // Reserved + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word WWDT_IRQHandler // Window Watchdog + .word PVD_VDDIO2_IRQHandler // PVD and VDDIO2 through EINT Line detect + .word RTC_IRQHandler // RTC through EINT Line + .word FLASH_IRQHandler // FLASH + .word RCM_CRS_IRQHandler // RCM and CRS + .word EINT0_1_IRQHandler // EINT Line 0 and 1 + .word EINT2_3_IRQHandler // EINT Line 2 and 3 + .word EINT4_15_IRQHandler // EINT Line 4 to 15 + .word TSC_IRQHandler // TSC + .word DMA1_CH1_IRQHandler // DMA1 Channel 1 + .word DMA1_CH2_3_IRQHandler // DMA1 Channel 2 and Channel 3 + .word DMA1_CH4_5_6_7_IRQHandler // DMA1 Channel 4 and Channel 5 + .word ADC1_COMP_IRQHandler // ADC1 , COMP1 and COMP2 + .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR6_DAC_IRQHandler // TMR6 and DAC + .word TMR7_IRQHandler // TMR7 + .word TMR14_IRQHandler // TMR14 + .word TMR15_IRQHandler // TMR15 + .word TMR16_IRQHandler // TMR16 + .word TMR17_IRQHandler // TMR17 + .word I2C1_IRQHandler // I2C1 + .word I2C2_IRQHandler // I2C2 + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_4_IRQHandler // USART3, USART4 + .word CEC_CAN_IRQHandler // CEC and CAN + .word USBD_IRQHandler // USB + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_CRS_IRQHandler + .thumb_set RCM_CRS_IRQHandler,Default_Handler + + .weak EINT0_1_IRQHandler + .thumb_set EINT0_1_IRQHandler,Default_Handler + + .weak EINT2_3_IRQHandler + .thumb_set EINT2_3_IRQHandler,Default_Handler + + .weak EINT4_15_IRQHandler + .thumb_set EINT4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_CH1_IRQHandler + .thumb_set DMA1_CH1_IRQHandler,Default_Handler + + .weak DMA1_CH2_3_IRQHandler + .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler + + .weak DMA1_CH4_5_6_7_IRQHandler + .thumb_set DMA1_CH4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TMR1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR6_DAC_IRQHandler + .thumb_set TMR6_DAC_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak TMR14_IRQHandler + .thumb_set TMR14_IRQHandler,Default_Handler + + .weak TMR15_IRQHandler + .thumb_set TMR15_IRQHandler,Default_Handler + + .weak TMR16_IRQHandler + .thumb_set TMR16_IRQHandler,Default_Handler + + .weak TMR17_IRQHandler + .thumb_set TMR17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USBD_IRQHandler + .thumb_set USBD_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f091.S b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f091.S new file mode 100644 index 0000000000..fb650567e6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/startup_apm32f091.S @@ -0,0 +1,261 @@ +/*! + * @file startup_apm32f091.S + * + * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f091 + * + * @version V1.0.0 + * + * @date 2022-08-30 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +// Reset handler routine +Reset_Handler: +// User Stack and Heap initialization + ldr r0, =_end_stack + mov sp, r0 + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + +L_loop3: + b L_loop3 + +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M0 Plus. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + .word _end_stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word 0 // Reserved + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word WWDT_IRQHandler // Window Watchdog + .word PVD_VDDIO2_IRQHandler // PVD and VDDIO2 through EINT Line detect + .word RTC_IRQHandler // RTC through EINT Line + .word FLASH_IRQHandler // FLASH + .word RCM_CRS_IRQHandler // RCM and CRS + .word EINT0_1_IRQHandler // EINT Line 0 and 1 + .word EINT2_3_IRQHandler // EINT Line 2 and 3 + .word EINT4_15_IRQHandler // EINT Line 4 to 15 + .word TSC_IRQHandler // TSC + .word DMA1_CH1_IRQHandler // DMA1 Channel 1 + .word DMA1_CH2_3_DMA2_CH1_2_IRQHandler // DMA1 Channel 2 and 3 DMA2 Channel 1 and 2 + .word DMA1_CH4_7_DMA2_CH3_5_IRQHandler // DMA1 Channel 4 to 7 DMA2 Channel 3 to 5 Interrupts + .word ADC1_COMP_IRQHandler // ADC1 , COMP1 and COMP2 + .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR6_DAC_IRQHandler // TMR6 and DAC + .word TMR7_IRQHandler // TMR7 + .word TMR14_IRQHandler // TMR14 + .word TMR15_IRQHandler // TMR15 + .word TMR16_IRQHandler // TMR16 + .word TMR17_IRQHandler // TMR17 + .word I2C1_IRQHandler // I2C1 + .word I2C2_IRQHandler // I2C2 + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_8_IRQHandler // USART3, USART4, USART5, USART6, USART7, USART8 + .word CEC_CAN_IRQHandler // CEC and CAN + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_CRS_IRQHandler + .thumb_set RCM_CRS_IRQHandler,Default_Handler + + .weak EINT0_1_IRQHandler + .thumb_set EINT0_1_IRQHandler,Default_Handler + + .weak EINT2_3_IRQHandler + .thumb_set EINT2_3_IRQHandler,Default_Handler + + .weak EINT4_15_IRQHandler + .thumb_set EINT4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_CH1_IRQHandler + .thumb_set DMA1_CH1_IRQHandler,Default_Handler + + .weak DMA1_CH2_3_DMA2_CH1_2_IRQHandler + .thumb_set DMA1_CH2_3_DMA2_CH1_2_IRQHandler,Default_Handler + + .weak DMA1_CH4_7_DMA2_CH3_5_IRQHandler + .thumb_set DMA1_CH4_7_DMA2_CH3_5_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TMR1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR6_DAC_IRQHandler + .thumb_set TMR6_DAC_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak TMR14_IRQHandler + .thumb_set TMR14_IRQHandler,Default_Handler + + .weak TMR15_IRQHandler + .thumb_set TMR15_IRQHandler,Default_Handler + + .weak TMR16_IRQHandler + .thumb_set TMR16_IRQHandler,Default_Handler + + .weak TMR17_IRQHandler + .thumb_set TMR17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_8_IRQHandler + .thumb_set USART3_8_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f030.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f030.s new file mode 100644 index 0000000000..ca63f71cfa --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f030.s @@ -0,0 +1,278 @@ +;/*! +; * @file startup_apm32f030.s +; * +; * @brief APM32F030 devices vector table for EWARM toolchain. +; * +; * @version V1.0.0 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCC + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD 0 ; Reserved + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_6_IRQHandler ; USART3,USART4,USART5,USART6 + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT0_1_IRQHandler + B EINT0_1_IRQHandler + + PUBWEAK EINT2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT2_3_IRQHandler + B EINT2_3_IRQHandler + + PUBWEAK EINT4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT4_15_IRQHandler + B EINT4_15_IRQHandler + + PUBWEAK DMA1_CH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_IRQHandler + B DMA1_CH1_IRQHandler + + PUBWEAK DMA1_CH2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_3_IRQHandler + B DMA1_CH2_3_IRQHandler + + PUBWEAK DMA1_CH4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_5_IRQHandler + B DMA1_CH4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TMR1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_BRK_UP_TRG_COM_IRQHandler + B TMR1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR6_IRQHandler + B TMR6_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK TMR14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR14_IRQHandler + B TMR14_IRQHandler + + PUBWEAK TMR15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR15_IRQHandler + B TMR15_IRQHandler + + PUBWEAK TMR16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR16_IRQHandler + B TMR16_IRQHandler + + PUBWEAK TMR17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR17_IRQHandler + B TMR17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_6_IRQHandler + B USART3_6_IRQHandler + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f051.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f051.s new file mode 100644 index 0000000000..db1f59d4ae --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f051.s @@ -0,0 +1,289 @@ +;/*! +; * @file startup_apm32f051.s +; * +; * @brief APM32F051 devices vector table for EWARM toolchain. +; * +; * @version V1.0.0 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCC + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 + DCD 0 ; Reserved + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT0_1_IRQHandler + B EINT0_1_IRQHandler + + PUBWEAK EINT2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT2_3_IRQHandler + B EINT2_3_IRQHandler + + PUBWEAK EINT4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT4_15_IRQHandler + B EINT4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_CH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_IRQHandler + B DMA1_CH1_IRQHandler + + PUBWEAK DMA1_CH2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_3_IRQHandler + B DMA1_CH2_3_IRQHandler + + PUBWEAK DMA1_CH4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_5_IRQHandler + B DMA1_CH4_5_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TMR1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_BRK_UP_TRG_COM_IRQHandler + B TMR1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR6_DAC_IRQHandler + B TMR6_DAC_IRQHandler + + PUBWEAK TMR14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR14_IRQHandler + B TMR14_IRQHandler + + PUBWEAK TMR15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR15_IRQHandler + B TMR15_IRQHandler + + PUBWEAK TMR16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR16_IRQHandler + B TMR16_IRQHandler + + PUBWEAK TMR17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR17_IRQHandler + B TMR17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f070.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f070.s new file mode 100644 index 0000000000..d86ef74edc --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f070.s @@ -0,0 +1,285 @@ +;/*! +; * @file startup_apm32f070.s +; * +; * @brief APM32F070 devices vector table for EWARM toolchain. +; * +; * @version V1.0.0 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCC + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD 0 ; Reserved + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD 0 ; Reserved + DCD USBD_IRQHandler ; USB + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT0_1_IRQHandler + B EINT0_1_IRQHandler + + PUBWEAK EINT2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT2_3_IRQHandler + B EINT2_3_IRQHandler + + PUBWEAK EINT4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT4_15_IRQHandler + B EINT4_15_IRQHandler + + PUBWEAK DMA1_CH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_IRQHandler + B DMA1_CH1_IRQHandler + + PUBWEAK DMA1_CH2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_3_IRQHandler + B DMA1_CH2_3_IRQHandler + + PUBWEAK DMA1_CH4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_5_IRQHandler + B DMA1_CH4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TMR1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_BRK_UP_TRG_COM_IRQHandler + B TMR1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR6_IRQHandler + B TMR6_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK TMR14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR14_IRQHandler + B TMR14_IRQHandler + + PUBWEAK TMR15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR15_IRQHandler + B TMR15_IRQHandler + + PUBWEAK TMR16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR16_IRQHandler + B TMR16_IRQHandler + + PUBWEAK TMR17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR17_IRQHandler + B TMR17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_IRQHandler + B USART3_4_IRQHandler + + PUBWEAK USBD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_IRQHandler + B USBD_IRQHandler + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f071.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f071.s new file mode 100644 index 0000000000..7fc1ba995b --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f071.s @@ -0,0 +1,299 @@ +;/*! +; * @file startup_apm32f071.s +; * +; * @brief APM32F071 devices vector table for EWARM toolchain. +; * +; * @version V1.0.0 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_IRQHandler ; RCC + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_IRQHandler ; CEC + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT0_1_IRQHandler + B EINT0_1_IRQHandler + + PUBWEAK EINT2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT2_3_IRQHandler + B EINT2_3_IRQHandler + + PUBWEAK EINT4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT4_15_IRQHandler + B EINT4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_CH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_IRQHandler + B DMA1_CH1_IRQHandler + + PUBWEAK DMA1_CH2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_3_IRQHandler + B DMA1_CH2_3_IRQHandler + + PUBWEAK DMA1_CH4_5_6_7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_5_6_7_IRQHandler + B DMA1_CH4_5_6_7_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TMR1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_BRK_UP_TRG_COM_IRQHandler + B TMR1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR6_DAC_IRQHandler + B TMR6_DAC_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK TMR14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR14_IRQHandler + B TMR14_IRQHandler + + PUBWEAK TMR15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR15_IRQHandler + B TMR15_IRQHandler + + PUBWEAK TMR16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR16_IRQHandler + B TMR16_IRQHandler + + PUBWEAK TMR17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR17_IRQHandler + B TMR17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_IRQHandler + B USART3_4_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f072.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f072.s new file mode 100644 index 0000000000..d43ad8cff7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f072.s @@ -0,0 +1,305 @@ +;/*! +; * @file startup_apm32f072.s +; * +; * @brief APM32F072 devices vector table for EWARM toolchain. +; * +; * @version V1.0.0 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_CRS_IRQHandler ; RCM and CRS + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USBD_IRQHandler ; USB + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCM_CRS_IRQHandler + B RCM_CRS_IRQHandler + + PUBWEAK EINT0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT0_1_IRQHandler + B EINT0_1_IRQHandler + + PUBWEAK EINT2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT2_3_IRQHandler + B EINT2_3_IRQHandler + + PUBWEAK EINT4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT4_15_IRQHandler + B EINT4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_CH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_IRQHandler + B DMA1_CH1_IRQHandler + + PUBWEAK DMA1_CH2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_3_IRQHandler + B DMA1_CH2_3_IRQHandler + + PUBWEAK DMA1_CH4_5_6_7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_5_6_7_IRQHandler + B DMA1_CH4_5_6_7_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TMR1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_BRK_UP_TRG_COM_IRQHandler + B TMR1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR6_DAC_IRQHandler + B TMR6_DAC_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK TMR14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR14_IRQHandler + B TMR14_IRQHandler + + PUBWEAK TMR15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR15_IRQHandler + B TMR15_IRQHandler + + PUBWEAK TMR16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR16_IRQHandler + B TMR16_IRQHandler + + PUBWEAK TMR17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR17_IRQHandler + B TMR17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_IRQHandler + B USART3_4_IRQHandler + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + PUBWEAK USBD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBD_IRQHandler + B USBD_IRQHandler + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f091.s b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f091.s new file mode 100644 index 0000000000..8d1497a489 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/iar/startup_apm32f091.s @@ -0,0 +1,299 @@ +;/*! +; * @file startup_apm32f091.s +; * +; * @brief APM32F091 devices vector table for EWARM toolchain. +; * +; * @version V1.0.0 +; * +; * @date 2022-02-21 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCM_CRS_IRQHandler ; RCM and CRS + DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 + DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 + DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_CH2_3_DMA2_CH1_2_IRQHandler ; DMA1 Channel 2 and 3 DMA2 Channel 1 and 2 + DCD DMA1_CH4_7_DMA2_CH3_5_IRQHandler ; DMA1 Channel 4 to 7 DMA2 Channel 3 to 5 Interrupts + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR6_DAC_IRQHandler ; TMR6 and DAC + DCD TMR7_IRQHandler ; TMR7 + DCD TMR14_IRQHandler ; TMR14 + DCD TMR15_IRQHandler ; TMR15 + DCD TMR16_IRQHandler ; TMR16 + DCD TMR17_IRQHandler ; TMR17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_IRQHandler ; USART3 and USART4 + DCD CEC_CAN_IRQHandler ; CEC and CAN + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCM_CRS_IRQHandler + B RCM_CRS_IRQHandler + + PUBWEAK EINT0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT0_1_IRQHandler + B EINT0_1_IRQHandler + + PUBWEAK EINT2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT2_3_IRQHandler + B EINT2_3_IRQHandler + + PUBWEAK EINT4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EINT4_15_IRQHandler + B EINT4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_CH1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_IRQHandler + B DMA1_CH1_IRQHandler + + PUBWEAK DMA1_CH2_3_DMA2_CH1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_3_DMA2_CH1_2_IRQHandler + B DMA1_CH2_3_DMA2_CH1_2_IRQHandler + + PUBWEAK DMA1_CH4_7_DMA2_CH3_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_7_DMA2_CH3_5_IRQHandler + B DMA1_CH4_7_DMA2_CH3_5_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TMR1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_BRK_UP_TRG_COM_IRQHandler + B TMR1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR6_DAC_IRQHandler + B TMR6_DAC_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK TMR14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR14_IRQHandler + B TMR14_IRQHandler + + PUBWEAK TMR15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR15_IRQHandler + B TMR15_IRQHandler + + PUBWEAK TMR16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR16_IRQHandler + B TMR16_IRQHandler + + PUBWEAK TMR17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TMR17_IRQHandler + B TMR17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_IRQHandler + B USART3_4_IRQHandler + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + END diff --git a/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/system_apm32f0xx.c b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/system_apm32f0xx.c new file mode 100644 index 0000000000..d84a74de3c --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/system_apm32f0xx.c @@ -0,0 +1,444 @@ +/*! + * @file system_apm32f0xx.c + * + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * @version V1.0.3 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup CMSIS + @{ +*/ + +/** @addtogroup APM32F0xx_System + @{ +*/ + +/** @defgroup System_Macros Macros + @{ + */ + +/* HSE is used as system clock source */ +//#define SYSTEM_CLOCK_HSE HSE_VALUE + +/* HSE (8MHz) used to clock the PLL, and the PLL is used as system clock source */ +//#define SYSTEM_CLOCK_24MHz (24000000) +//#define SYSTEM_CLOCK_36MHz (36000000) +#define SYSTEM_CLOCK_48MHz (48000000) + +//#define VECT_TAB_SRAM +/* Vector Table base offset field. This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00 + +/**@} end of group System_Macros */ + +/** @defgroup System_Enumerations Enumerations + @{ + */ + +/**@} end of group System_Enumerations */ + +/** @defgroup System_Structures Structures + @{ + */ + +/**@} end of group System_Structures */ + +/** @defgroup System_Variables Variables + @{ + */ + +#ifdef SYSTEM_CLOCK_HSE + uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE; +#elif defined SYSTEM_CLOCK_24MHz + uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz; +#elif defined SYSTEM_CLOCK_36MHz + uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz; +#elif defined SYSTEM_CLOCK_48MHz + uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz; +#else + uint32_t SystemCoreClock = HSI_VALUE; +#endif + +static void SystemClockConfig(void); + +#ifdef SYSTEM_CLOCK_HSE + static void SystemClockHSE(void); +#elif defined SYSTEM_CLOCK_24MHz + static void SystemClock24M(void); +#elif defined SYSTEM_CLOCK_36MHz + static void SystemClock36M(void); +#elif defined SYSTEM_CLOCK_48MHz + static void SystemClock48M(void); + +#endif + +/**@} end of group System_Variables */ + +/** @defgroup System_Functions Functions + @{ + */ + +/*! + * @brief Setup the microcontroller system + * + * @param None + * + * @retval None + * + * @note + */ +void SystemInit(void) +{ + /* Set HSIEN bit */ + RCM->CTRL1_B.HSIEN = BIT_SET; + /* Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and COC bits */ + RCM->CFG1 &= (uint32_t)0x08FFB80CU; + /* Reset HSEEN, CSSEN and PLLEN bits */ + RCM->CTRL1 &= (uint32_t)0xFEF6FFFFU; + /* Reset HSEBCFG bit */ + RCM->CTRL1_B.HSEBCFG = BIT_RESET; + /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG bits */ + RCM->CFG1 &= (uint32_t)0xFFC0FFFFU; + /* Reset PREDIV[3:0] bits */ + RCM->CFG1 &= (uint32_t)0xFFFFFFF0U; + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCM->CFG3 &= (uint32_t)0xFFFFFEAC; + /* Reset HSI14 bit */ + RCM->CTRL2_B.HSI14EN = BIT_RESET; + /* Disable all interrupts */ + RCM->INT = 0x00000000U; + + SystemClockConfig(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; +#else + SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET; +#endif +} + +/*! + * @brief Update SystemCoreClock variable according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK) + * + * @param None + * + * @retval None + * + * @note + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysClock, pllMull, pllSource, Prescaler; + uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + /* Get SYSCLK source */ + sysClock = RCM->CFG1_B.SCLKSWSTS; + + switch (sysClock) + { + case 0: + SystemCoreClock = HSI_VALUE; + break; + + /* sys clock is HSE */ + case 1: + SystemCoreClock = HSE_VALUE; + break; + + /* sys clock is PLL */ + case 2: + pllMull = RCM->CFG1_B.PLLMULCFG + 2; + pllSource = RCM->CFG1_B.PLLSRCSEL; + + /* PLL entry clock source is HSE */ + if (pllSource == 2) + { + SystemCoreClock = HSE_VALUE * pllMull; + + /* HSE clock divided by 2 */ + if (pllSource == RCM->CFG1_B.PLLHSEPSC) + { + SystemCoreClock >>= 1; + } + } + /* PLL entry clock source is HSI/2 */ + else + { + SystemCoreClock = (HSI_VALUE >> 1) * pllMull; + } + + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + Prescaler = AHBPrescTable[(RCM->CFG1_B.AHBPSC)]; + SystemCoreClock >>= Prescaler; +} +/*! + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClockConfig(void) +{ +#ifdef SYSTEM_CLOCK_HSE + SystemClockHSE(); +#elif defined SYSTEM_CLOCK_24MHz + SystemClock24M(); +#elif defined SYSTEM_CLOCK_36MHz + SystemClock36M(); +#elif defined SYSTEM_CLOCK_48MHz + SystemClock48M(); +#endif +} + +#if defined SYSTEM_CLOCK_HSE + +/*! + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClockHSE(void) +{ + uint32_t i; + + RCM->CTRL1_B.HSEEN = BIT_SET; + + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if (RCM->CTRL1_B.HSERDYFLG) + { + break; + } + } + + if (RCM->CTRL1_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; + + /* HCLK = SYSCLK */ + RCM->CFG1_B.AHBPSC = 0X00; + + /* PCLK = HCLK */ + RCM->CFG1_B.APB1PSC = 0X00; + + /* Select HSE as system clock source */ + RCM->CFG1_B.SCLKSEL = 1; + + /* Wait till HSE is used as system clock source */ + while (RCM->CFG1_B.SCLKSWSTS != 0x01); + } +} + +#elif defined SYSTEM_CLOCK_24MHz + +/*! + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock24M(void) +{ + uint32_t i; + + RCM->CTRL1_B.HSEEN = BIT_SET; + + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if (RCM->CTRL1_B.HSERDYFLG) + { + break; + } + } + + if (RCM->CTRL1_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG1_B.AHBPSC = 0X00; + + /* PCLK = HCLK */ + RCM->CFG1_B.APB1PSC = 0X00; + + /* PLL: (HSE / 2) * 6 */ + RCM->CFG1_B.PLLSRCSEL = 2; + RCM->CFG1_B.PLLHSEPSC = 1; + RCM->CFG1_B.PLLMULCFG = 4; + + /* Enable PLL */ + RCM->CTRL1_B.PLLEN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL1_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG1_B.SCLKSEL = 2; + + /* Wait till PLL is used as system clock source */ + while (RCM->CFG1_B.SCLKSWSTS != 0x02); + } +} + +#elif defined SYSTEM_CLOCK_36MHz + +/*! + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock36M(void) +{ + uint32_t i; + + RCM->CTRL1_B.HSEEN = BIT_SET; + + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if (RCM->CTRL1_B.HSERDYFLG) + { + break; + } + } + + if (RCM->CTRL1_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG1_B.AHBPSC = 0X00; + + /* PCLK = HCLK */ + RCM->CFG1_B.APB1PSC = 0X00; + + /* PLL: (HSE / 2) * 9 */ + RCM->CFG1_B.PLLSRCSEL = 2; + RCM->CFG1_B.PLLHSEPSC = 1; + RCM->CFG1_B.PLLMULCFG = 7; + + /* Enable PLL */ + RCM->CTRL1_B.PLLEN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL1_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG1_B.SCLKSEL = 2; + + /* Wait till PLL is used as system clock source */ + while (RCM->CFG1_B.SCLKSWSTS != 0x02); + } +} + +#elif defined SYSTEM_CLOCK_48MHz + +/*! + * @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock48M(void) +{ + uint32_t i; + + RCM->CTRL1_B.HSEEN = BIT_SET; + + for (i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if (RCM->CTRL1_B.HSERDYFLG) + { + break; + } + } + + if (RCM->CTRL1_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG1_B.AHBPSC = 0X00; + + /* PCLK = HCLK */ + RCM->CFG1_B.APB1PSC = 0X00; + + /* PLL: HSE * 6 */ + RCM->CFG1_B.PLLSRCSEL = 2; + RCM->CFG1_B.PLLMULCFG = 4; + + /* Enable PLL */ + RCM->CTRL1_B.PLLEN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL1_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG1_B.SCLKSEL = 2; + + /* Wait till PLL is used as system clock source */ + while (RCM->CFG1_B.SCLKSWSTS != 0x02); + } +} + +#endif + +/**@} end of group System_Functions */ +/**@} end of group APM32F0xx_System */ +/**@} end of group CMSIS */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/SConscript b/bsp/apm32/libraries/APM32F0xx_Library/SConscript new file mode 100644 index 0000000000..fe845e860f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/SConscript @@ -0,0 +1,49 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +Device/Geehy/APM32F0xx/Source/system_apm32f0xx.c +APM32F0xx_StdPeriphDriver/src/apm32f0xx_gpio.c +APM32F0xx_StdPeriphDriver/src/apm32f0xx_syscfg.c +APM32F0xx_StdPeriphDriver/src/apm32f0xx_misc.c +APM32F0xx_StdPeriphDriver/src/apm32f0xx_rcm.c +APM32F0xx_StdPeriphDriver/src/apm32f0xx_usart.c +APM32F0xx_StdPeriphDriver/src/apm32f0xx_eint.c +""") + +if GetDepend(['RT_USING_ADC']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_dac.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_rtc.c'] + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_pmu.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_spi.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_tmr.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_wwdt.c'] + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_iwdt.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_can.c'] + +path = [cwd + '/Device/Geehy/APM32F0xx/Include', + cwd + '/APM32F0xx_StdPeriphDriver/inc', + cwd + '/CMSIS/Include'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc.h new file mode 100644 index 0000000000..e61692fa6b --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc.h @@ -0,0 +1,135 @@ +/*! + * @file tsc.h + * + * @brief This file contains external declarations of the tsc.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TSC_H +#define __TSC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_acq.h" +#include "tsc_time.h" +#include "tsc_touchkey.h" +#include "tsc_linrot.h" +#include "tsc_object.h" +#include "tsc_dxs.h" +#include "tsc_ecs.h" +#include "tsc_filter.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Driver TSC Driver + @{ +*/ + +/** @defgroup TSC_Macros Macros + @{ +*/ + +/**@} end of group TSC_Macros */ + +/** @defgroup TSC_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Enumerations */ + +/** @defgroup TSC_Structures Structures + @{ +*/ + +/** + * @brief Store all global variables shared between the Touch Driver and the Application. + */ +typedef struct +{ + TSC_tTick_ms_T Tick_ms; /*!< Incremented each 0.5ms by timing interrupt routine */ + TSC_tTick_sec_T Tick_sec; /*!< Incremented each second by timing interrupt routine */ + CONST TSC_Block_T* Block_Array; /*!< Pointer to the array containing all Blocks */ + TSC_tIndex_T For_Block; /*!< Pointer to the current Block */ + CONST TSC_Object_T* For_Obj; /*!< Pointer to the current Object */ +#if TOUCH_USE_ZONE > 0 + CONST TSC_Zone_T* For_Zone; /*!< Pointer to the current Zone */ + TSC_tIndex_T Index_For_Zone; /*!< Index in the current Zone */ +#endif +#if TOUCH_TOTAL_KEYS > 0 + CONST TSC_TouchKey_T* For_Key; /*!< Pointer to the current Touch Key */ +#endif +#if TOUCH_TOTAL_LNRTS > 0 + CONST TSC_LinRot_T* For_LinRot; /*!< Pointer to the current Linear or Rotary sensor */ +#endif +} TSC_Globals_T; + +/** + * @brief Store all global parametersshared between the Touch Driver and the Application. + * @warning Only one variable of this structure type must be created and be placed in RAM only. + */ +typedef struct +{ + TSC_tMeas_T AcqMin; /*!< Acquisition minimum limit */ + TSC_tMeas_T AcqMax; /*!< Acquisition maximum limit */ + TSC_tNum_T NumCalibSample; /*!< Number of Calibration samples */ + TSC_tTick_sec_T DTO; /*!< Detection Time Out */ +#if TOUCH_TOTAL_KEYS > 0 + CONST TSC_State_T* p_KeySta; /*!< Default state machine for TouchKey sensors */ + CONST TSC_TouchKeyMethods_T* p_KeyMet; /*!< Default methods for TouchKey sensors */ +#endif +#if TOUCH_TOTAL_LNRTS > 0 + CONST TSC_State_T* p_LinRotSta; /*!< Default state machine for Linear/Rotary sensors */ + CONST TSC_LinRotMethods_T* p_LinRotMet; /*!< Default methods for Linear/Rotary sensors */ +#endif +} TSC_Params_T; + +/**@} end of group TSC_Structures */ + +/** @defgroup TSC_Variables Variables + @{ +*/ + +extern TSC_Globals_T TSC_Globals; +extern TSC_Params_T TSC_Params; + +/**@} end of group TSC_Variables */ + +/** @defgroup TSC_Functions Functions + @{ +*/ + +TSC_STATUS_T TSC_Config(CONST TSC_Block_T* block); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_H */ + +/**@} end of group TSC_Functions */ +/**@} end of group TSC_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_acq.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_acq.h new file mode 100644 index 0000000000..8947832695 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_acq.h @@ -0,0 +1,253 @@ +/*! + * @file tsc_acq.h + * + * @brief This file contains external declarations of the tsc_acq.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TSC_ACQ_H +#define __TSC_ACQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" +#include "tsc_config.h" +#include "tsc_types.h" +#include "apm32f0xx_gpio.h" +#include "apm32f0xx_rcm.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Acquisition_Driver TSC Acquisition Driver + @{ +*/ + +#if !defined(APM32F051) && defined(APM32F071) && defined(APM32F072) && defined(APM32F091) +#error "Device family not declared in the toolchain compiler preprocessor." +#endif + +/** @defgroup TSC_Acquisition_Macros Macros + @{ + */ + +#ifndef CONST +#define CONST const +#endif + +/* SysTick enable/disable interrupt macros */ +#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;} +#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;} + +#define TSC_NB_GROUPS (8) + +#define TSC_GROUP1 (0x01) +#define TSC_GROUP2 (0x02) +#define TSC_GROUP3 (0x04) +#define TSC_GROUP4 (0x08) +#define TSC_GROUP5 (0x10) +#define TSC_GROUP6 (0x20) +#define TSC_GROUP7 (0x40) +#define TSC_GROUP8 (0x80) + +/* GxIOy masks */ +#define TSC_GROUP1_IO1 (0x00000001) +#define TSC_GROUP1_IO2 (0x00000002) +#define TSC_GROUP1_IO3 (0x00000004) +#define TSC_GROUP1_IO4 (0x00000008) +#define TSC_GROUP2_IO1 (0x00000010) +#define TSC_GROUP2_IO2 (0x00000020) +#define TSC_GROUP2_IO3 (0x00000040) +#define TSC_GROUP2_IO4 (0x00000080) +#define TSC_GROUP3_IO1 (0x00000100) +#define TSC_GROUP3_IO2 (0x00000200) +#define TSC_GROUP3_IO3 (0x00000400) +#define TSC_GROUP3_IO4 (0x00000800) +#define TSC_GROUP4_IO1 (0x00001000) +#define TSC_GROUP4_IO2 (0x00002000) +#define TSC_GROUP4_IO3 (0x00004000) +#define TSC_GROUP4_IO4 (0x00008000) +#define TSC_GROUP5_IO1 (0x00010000) +#define TSC_GROUP5_IO2 (0x00020000) +#define TSC_GROUP5_IO3 (0x00040000) +#define TSC_GROUP5_IO4 (0x00080000) +#define TSC_GROUP6_IO1 (0x00100000) +#define TSC_GROUP6_IO2 (0x00200000) +#define TSC_GROUP6_IO3 (0x00400000) +#define TSC_GROUP6_IO4 (0x00800000) +#define TSC_GROUP7_IO1 (0x01000000) +#define TSC_GROUP7_IO2 (0x02000000) +#define TSC_GROUP7_IO3 (0x04000000) +#define TSC_GROUP7_IO4 (0x08000000) +#define TSC_GROUP8_IO1 (0x10000000) +#define TSC_GROUP8_IO2 (0x20000000) +#define TSC_GROUP8_IO3 (0x40000000) +#define TSC_GROUP8_IO4 (0x80000000) + +/* Exported types, For all devices/acquisitions */ +typedef uint16_t TSC_tMeas_T; /*!< Measurement */ +typedef uint16_t TSC_tRefer_T; /*!< Reference */ +typedef int16_t TSC_tDelta_T; /*!< Delta */ + +typedef uint8_t TSC_tIndexSrc_T; /*!< Channel source index */ +typedef uint16_t TSC_tIndexDest_T; /*!< Channel destination index */ + +typedef uint8_t TSC_tRefRest_T; /*!< Reference Rest (ECS) */ +typedef uint16_t TSC_tKCoeff_T; /*!< K coefficient (ECS) */ + +typedef uint8_t TSC_tIndex_T; /*!< Generic index */ +typedef uint16_t TSC_tNum_T; /*!< Generic number */ +typedef uint8_t TSC_tCounter_T; /*!< Generic counter used for debounce */ + +typedef uint8_t TSC_tThreshold_T; /*!< Delta threshold */ + +typedef int16_t TSC_tPosition_T; /*!< Linear and Rotary sensors position */ +typedef uint8_t TSC_tsignPosition_T; /*!< Linear and Rotary sensors position */ + +typedef uint16_t TSC_tTick_ms_T; /*!< Time in ms */ +typedef uint8_t TSC_tTick_sec_T; /*!< Time in sec */ + +/**@} end of group TSC_Acquisition_Macros */ + +/** @defgroup TSC_Acquisition_Enumerations Enumerations + @{ + */ + +/**@} end of group TSC_Acquisition_Enumerations */ + +/** @defgroup TSC_Acquisition_Structures Structures + @{ + */ + +/* Pointer to the Measure filter function */ +typedef TSC_tMeas_T(* TSC_pMeasFilter_T)(TSC_tMeas_T, TSC_tMeas_T); +/* Pointer to the Delta filter function */ +typedef TSC_tDelta_T(* TSC_pDeltaFilter_T)(TSC_tDelta_T); + +/** + * @brief Channel destination index + */ +typedef struct +{ + TSC_tIndexDest_T IdxDest; /*!< Index in the Channel data array */ +} TSC_Channel_Dest_T; + +/** + * @brief Channel Source and Configuration + */ +typedef struct +{ + TSC_tIndexSrc_T IdxSrc; /*!< Index of TSC->IOGxCNT[] registers */ + /* For apm32f0xx only */ + uint32_t msk_IOCHCTRL_channel; /*!< Mask of the Channel IO (electrodes only) */ + uint32_t msk_IOGCSTS_group; /*!< Mask of the Group used (electrodes only) */ +} TSC_Channel_Src_T; + +/** + * @brief Channel flags + */ +typedef struct +{ + unsigned int DataReady : 1; /*!< To identify a new measurement (TSC_DATA_T) */ + unsigned int AcqStatus : 2; /*!< Acquisition status (TSC_ACQ_STATUS_T) */ + unsigned int ObjStatus : 2; /*!< Object status (TSC_OBJ_STATUS_T) */ +} TSC_Channel_Flag_T; + +/** + * @brief Channel Data + */ +typedef struct +{ + TSC_Channel_Flag_T Flag; /*!< Flag */ + TSC_tRefer_T Refer; /*!< Reference */ + TSC_tRefRest_T RefRest; /*!< Reference rest for ECS */ + TSC_tDelta_T Delta; /*!< Delta */ +#if TOUCH_USE_MEAS > 0 + TSC_tMeas_T Meas; /*!< Hold the last acquisition measure */ +#endif +} TSC_Channel_Data_T; + +/** + * @brief Block Configuration + */ +typedef struct +{ + /* Common to all acquisitions */ + CONST TSC_Channel_Src_T* p_chSrc; /*!< Pointer to the Channel Source and Configuration */ + CONST TSC_Channel_Dest_T* p_chDest; /*!< Pointer to the Channel Destination */ + TSC_Channel_Data_T* p_chData; /*!< Pointer to the Channel Data */ + TSC_tNum_T NumChannel; /*!< Number of channels in the block */ + /* For apm32f0xx only */ + uint32_t msk_IOCHCTRL_channels; /*!< Mask of all channel IOs (electrodes and shields) */ + uint32_t msk_IOGCSTS_groups; /*!< Mask of all groups used (electrodes only) */ +} TSC_Block_T; + +/** + * @brief Structure containing all data of a Zone. + * A Zone is a set of Blocks. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ + /* Common to all acquisitions */ + TSC_tIndex_T* indexBlock; /*!< Pointer to an array of block indexes */ + TSC_pDeltaFilter_T* daltaFilter; /*!< Pointer to a Delta filter function */ + TSC_tNum_T numBlock; /*!< Number of blocks in the zone */ +} TSC_Zone_T; + +/**@} end of group TSC_Acquisition_Structures */ + +/** @defgroup TSC_Acquisition_Functions Functions + @{ + */ + +TSC_STATUS_T TSC_Acq_Config(void); +void TSC_Acq_ConfigGPIO(void); +TSC_STATUS_T TSC_Acq_ConfigBlock(TSC_tIndex_T idxBlock); +TSC_BOOL_T TSC_Acq_UseFilter(TSC_Channel_Data_T* pCh); +TSC_BOOL_T TSC_Acq_TestReferenceRange(TSC_Channel_Data_T* pCh); +TSC_BOOL_T TSC_Acq_TestFirstReference(TSC_Channel_Data_T* pCh, TSC_tMeas_T newMeas); +void TSC_Acq_StartPerConfigBlock(void); +TSC_STATUS_T TSC_Acq_WaitBlockEOA(void); +TSC_ACQ_STATUS_T TSC_Acq_CheckNoise(void); +TSC_tMeas_T TSC_Acq_ReadMeasurVal(TSC_tIndexSrc_T index); +TSC_tDelta_T TSC_Acq_ComputeDelta(TSC_tRefer_T refVal, TSC_tMeas_T measVal); +TSC_tMeas_T TSC_Acq_ComputeMeas(TSC_tRefer_T refVal, TSC_tDelta_T deltaVal); + +TSC_STATUS_T TSC_Acq_ConfigZone(CONST TSC_Zone_T* zone, TSC_tIndex_T idxBlock); +TSC_STATUS_T TSC_Acq_ReadBlockResult(TSC_tIndex_T idxBlock, TSC_pMeasFilter_T mfilter, TSC_pDeltaFilter_T dfilter); +TSC_STATUS_T TSC_Acq_CalibrateBlock(TSC_tIndex_T block); +void TSC_acq_ClearBlockData(TSC_tIndex_T block); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_ACQ_H */ + +/**@} end of group TSC_Acquisition_Functions */ +/**@} end of group TSC_Acquisition_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_check.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_check.h new file mode 100644 index 0000000000..d0f78ebf71 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_check.h @@ -0,0 +1,578 @@ +/*! + * @file tsc_check.h + * + * @brief This file contains the check of all parameters defined in the + * common configuration file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_CHECK_H +#define __TOUCH_CHECK_H + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Check_Driver TSC Check Driver + @{ +*/ + +/* Local check */ +#if ((TOUCH_TOTAL_CHANNELS < 1) || (TOUCH_TOTAL_CHANNELS > 24)) + #error "TOUCH_TOTAL_CHANNELS can be (1 .. 24)." +#endif + +#if ((TOUCH_TOTAL_BLOCKS < 1) || (TOUCH_TOTAL_BLOCKS > 8)) + #error "TOUCH_TOTAL_BLOCKS can be (1 .. 8)." +#endif + +#if ((TOUCH_TOTAL_TOUCHKEYS < 0) || (TOUCH_TOTAL_TOUCHKEYS > 24)) + #error "TOUCH_TOTAL_TOUCHKEYS can be (0 .. 24)." +#endif + +#if ((TOUCH_TOTAL_TOUCHKEYS_B < 0) || (TOUCH_TOTAL_TOUCHKEYS_B > 24)) + #error "TOUCH_TOTAL_TOUCHKEYS_B can be (0 .. 24)." +#endif + +#if ((TOUCH_TOTAL_LINROTS < 0) || (TOUCH_TOTAL_LINROTS > 24)) + #error "TOUCH_TOTAL_LINROTS can be (0 .. 24)." +#endif + +#if ((TOUCH_TOTAL_LINROTS_B < 0) || (TOUCH_TOTAL_LINROTS_B > 24)) + #error "TOUCH_TOTAL_LINROTS_B can be (0 .. 24)." +#endif + +#if ((TOUCH_TOTAL_OBJECTS < 1) || (TOUCH_TOTAL_OBJECTS > 24)) + #error "TOUCH_TOTAL_OBJECTS can be (1 .. 24)." +#endif + +#if ((TOUCH_TOTAL_KEYS + TOUCH_TOTAL_LNRTS) > 24) + #error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24." +#endif + +#ifndef TOUCH_TSC_GPIO_CONFIG + #error "Please Config TOUCH_TSC_GPIO_CONFIG." +#endif + +#if ((TOUCH_TSC_GPIO_CONFIG < 0) || (TOUCH_TSC_GPIO_CONFIG > 1)) + #error "TOUCH_TSC_GPIO_CONFIG can be (0 .. 1)." +#endif + +#ifndef TOUCH_TSC_CTPHSEL + #error "Please Config TOUCH_TSC_CTPHSEL." +#endif + +#if ((TOUCH_TSC_CTPHSEL < 0) || (TOUCH_TSC_CTPHSEL > 15)) + #error "TOUCH_TSC_CTPHSEL can be (0 .. 15)." +#endif + +#ifndef TOUCH_TSC_CTPLSEL + #error "Please Config TOUCH_TSC_CTPLSEL." +#endif + +#if ((TOUCH_TSC_CTPLSEL < 0) || (TOUCH_TSC_CTPLSEL > 15)) + #error "TOUCH_TSC_CTPLSEL can be (0 .. 15)." +#endif + +#ifndef TOUCH_TSC_PGCDFSEL + #error "Please Config TOUCH_TSC_PGCDFSEL." +#endif + +#if ((TOUCH_TSC_PGCDFSEL < 0) || (TOUCH_TSC_PGCDFSEL > 7)) + #error "TOUCH_TSC_PGCDFSEL can be (0 .. 7)." +#endif + +#if (TOUCH_ACQ_MAX > 0) && (TOUCH_ACQ_MAX < 256) + #define TOUCH_TSC_MCNTVSEL 0 /*!< 255 */ +#endif + +#if (TOUCH_ACQ_MAX > 255) && (TOUCH_ACQ_MAX < 512) + #define TOUCH_TSC_MCNTVSEL 1 /*!< 511 */ +#endif + +#if (TOUCH_ACQ_MAX > 511) && (TOUCH_ACQ_MAX < 1024) + #define TOUCH_TSC_MCNTVSEL 2 /*!< 1023 */ +#endif + +#if (TOUCH_ACQ_MAX > 1023) && (TOUCH_ACQ_MAX < 2048) + #define TOUCH_TSC_MCNTVSEL 3 /*!< 2047 */ +#endif + +#if (TOUCH_ACQ_MAX > 2047) && (TOUCH_ACQ_MAX < 4096) + #define TOUCH_TSC_MCNTVSEL 4 /*!< 4095 */ +#endif + +#if (TOUCH_ACQ_MAX > 4095) && (TOUCH_ACQ_MAX < 8192) + #define TOUCH_TSC_MCNTVSEL 5 /*!< 8191 */ +#endif + +#if (TOUCH_ACQ_MAX > 8191) + #define TOUCH_TSC_MCNTVSEL 6 /*!< 16383 */ +#endif + +#ifndef TOUCH_TSC_MCNTVSEL + #error "Please Config TOUCH_TSC_MCNTVSEL." +#endif + +#if ((TOUCH_TSC_MCNTVSEL < 0) || (TOUCH_TSC_MCNTVSEL > 6)) + #error "TOUCH_TSC_MCNTVSEL can be (0 .. 6)." +#endif + +#ifndef TOUCH_TSC_IODEF + #error "Please Config TOUCH_TSC_IODEF." +#endif + +#if ((TOUCH_TSC_IODEF < 0) || (TOUCH_TSC_IODEF > 1)) + #error "TOUCH_TSC_IODEF can be (0 .. 1)." +#endif + +#ifndef TOUCH_TSC_AMCFG + #error "Please Config TOUCH_TSC_AMCFG." +#endif + +#if ((TOUCH_TSC_AMCFG < 0) || (TOUCH_TSC_AMCFG > 1)) + #error "TOUCH_TSC_AMCFG can be (0 .. 1)." +#endif + +#ifndef TOUCH_TSC_SYNC_PIN + #error "Please Config TOUCH_TSC_SYNC_PIN." +#endif + +#if ((TOUCH_TSC_SYNC_PIN < 0) || (TOUCH_TSC_SYNC_PIN > 1)) + #error "TOUCH_TSC_SYNC_PIN can be (0 .. 1)." +#endif + +#ifndef TOUCH_TSC_SYNC_POL + #error "Please Config TOUCH_TSC_SYNC_POL." +#endif + +#if ((TOUCH_TSC_SYNC_POL < 0) || (TOUCH_TSC_SYNC_POL > 1)) + #error "TOUCH_TSC_SYNC_POL can be (0 .. 1)." +#endif + +#ifndef TOUCH_TSC_USE_SSEN + #error "Please Config TOUCH_TSC_USE_SSEN." +#endif + +#if ((TOUCH_TSC_USE_SSEN < 0) || (TOUCH_TSC_USE_SSEN > 1)) + #error "TOUCH_TSC_USE_SSEN can be (0 .. 1)." +#endif + +#ifndef TOUCH_TSC_SSERRVSEL + #error "Please Config TOUCH_TSC_SSERRVSEL." +#endif + +#if ((TOUCH_TSC_SSERRVSEL < 0) || (TOUCH_TSC_SSERRVSEL > 127)) + #error "TOUCH_TSC_SSERRVSEL can be (0 .. 127)." +#endif + +#ifndef TOUCH_TSC_SSCDFSEL + #error "Please Config TOUCH_TSC_SSCDFSEL." +#endif + +#if ((TOUCH_TSC_SSCDFSEL < 0) || (TOUCH_TSC_SSCDFSEL > 1)) + #error "TOUCH_TSC_SSCDFSEL can be (0 .. 1)." +#endif + +#ifdef TSC_GROUP7_ENABLED + #undef TSC_GROUP7_ENABLED +#endif + +#if (TOUCH_TSC_GROUP7_IO1 != NU) || (TOUCH_TSC_GROUP7_IO2 != NU) || (TOUCH_TSC_GROUP7_IO3 != NU) || (TOUCH_TSC_GROUP7_IO4 != NU) + #define TSC_GROUP7_ENABLED (1) +#endif + +#ifdef TSC_GROUP8_ENABLED + #undef TSC_GROUP8_ENABLED +#endif + +#if (TOUCH_TSC_GROUP8_IO1 != NU) || (TOUCH_TSC_GROUP8_IO2 != NU) || (TOUCH_TSC_GROUP8_IO3 != NU) || (TOUCH_TSC_GROUP8_IO4 != NU) + #define TSC_GROUP8_ENABLED (1) +#endif + +#ifndef TOUCH_DELAY_DISCHARGE_ALL + #error "Please Config TOUCH_DELAY_DISCHARGE_ALL." +#endif + +#if ((TOUCH_DELAY_DISCHARGE_ALL < 0) || (TOUCH_DELAY_DISCHARGE_ALL > 65535)) + #error "TOUCH_DELAY_DISCHARGE_ALL can be (0 .. 65535)." +#endif + +/* Global check */ +#ifndef TOUCH_TOTAL_CHANNELS + #error "Please Config TOUCH_TOTAL_CHANNELS." +#endif + +#ifndef TOUCH_TOTAL_BLOCKS + #error "Please Config TOUCH_TOTAL_BLOCKS." +#endif + +#ifndef TOUCH_TOTAL_TOUCHKEYS + #error "Please Config TOUCH_TOTAL_TOUCHKEYS." +#endif + +#ifndef TOUCH_TOTAL_TOUCHKEYS_B + #error "Please Config TOUCH_TOTAL_TOUCHKEYS_B." +#endif + +#ifndef TOUCH_TOTAL_LINROTS + #error "Please Config TOUCH_TOTAL_LINROTS." +#endif + +#ifndef TOUCH_TOTAL_LINROTS_B + #error "Please Config TOUCH_TOTAL_LINROTS_B." +#endif + +#ifndef TOUCH_TOTAL_OBJECTS + #error "Please Config TOUCH_TOTAL_OBJECTS." +#endif + +#define TOUCH_TOTAL_KEYS (TOUCH_TOTAL_TOUCHKEYS + TOUCH_TOTAL_TOUCHKEYS_B) +#define TOUCH_TOTAL_LNRTS (TOUCH_TOTAL_LINROTS + TOUCH_TOTAL_LINROTS_B) + +#if ((TOUCH_TOTAL_KEYS == 0) && (TOUCH_TOTAL_LNRTS == 0)) + #error "Please Config TouchKey and Linear/Rotary sensors." +#endif + +#ifndef TOUCH_CALIB_SAMPLES + #error "Please Config TOUCH_CALIB_SAMPLES." +#endif + +#if ((TOUCH_CALIB_SAMPLES != 4) && (TOUCH_CALIB_SAMPLES != 8) && (TOUCH_CALIB_SAMPLES != 16)) + #error "TOUCH_CALIB_SAMPLES can be (4, 8, 16)." +#endif + +#ifndef TOUCH_CALIB_DELAY + #error "Please Config TOUCH_CALIB_DELAY." +#endif + +#if ((TOUCH_CALIB_DELAY < 0) || (TOUCH_CALIB_DELAY > 40)) + #error "TOUCH_CALIB_DELAY can be (0..40)." +#endif + +#ifndef TOUCH_ACQ_MIN + #error "Please Config TOUCH_ACQ_MIN." +#endif + +#ifndef TOUCH_ACQ_MAX + #error "Please Config TOUCH_ACQ_MAX." +#endif + +#if ((TOUCH_ACQ_MIN < 1) || (TOUCH_ACQ_MIN > (TOUCH_ACQ_MAX-1))) + #error "TOUCH_ACQ_MIN can be (1 .. ACQ_MAX-1)." +#endif + +#if ((TOUCH_ACQ_MAX < (TOUCH_ACQ_MIN+1)) || (TOUCH_ACQ_MAX > 50000)) + #error "TOUCH_ACQ_MAX can be (ACQ_MIN+1 .. 50000)." +#endif + +#ifndef TOUCH_KEY_PROX_IN_TH + #error "Please Config TOUCH_KEY_PROX_IN_TH." +#endif + +#ifndef TOUCH_KEY_PROX_OUT_TH + #error "Please Config TOUCH_KEY_PROX_OUT_TH." +#endif + +#if ((TOUCH_KEY_PROX_OUT_TH < 0) || (TOUCH_KEY_PROX_OUT_TH > (TOUCH_KEY_PROX_IN_TH-1))) + #error "TOUCH_KEY_PROX_OUT_TH can be (0 .. TOUCH_KEY_PROX_IN_TH-1)." +#endif + +#if TOUCH_COEFF_TH == 0 + #if ((TOUCH_KEY_PROX_IN_TH < (TOUCH_KEY_PROX_OUT_TH+1)) || (TOUCH_KEY_PROX_IN_TH > (TOUCH_KEY_DETECT_OUT_TH-1))) + #error "TOUCH_KEY_PROX_IN_TH can be (TOUCH_KEY_PROX_OUT_TH+1 .. TOUCH_KEY_DETECT_OUT_TH-1)." + #endif +#endif + +#ifndef TOUCH_LINROT_PROX_IN_TH + #error "Please Config TOUCH_LINROT_PROX_IN_TH." +#endif + +#ifndef TOUCH_LINROT_PROX_OUT_TH + #error "Please Config TOUCH_LINROT_PROX_OUT_TH." +#endif + +#if ((TOUCH_LINROT_PROX_OUT_TH < 0) || (TOUCH_LINROT_PROX_OUT_TH > (TOUCH_LINROT_PROX_IN_TH-1))) + #error "TOUCH_LINROT_PROX_OUT_TH can be (0 .. TOUCH_LINROT_PROX_IN_TH-1)." +#endif + +#if TOUCH_COEFF_TH == 0 + #if ((TOUCH_LINROT_PROX_IN_TH < (TOUCH_LINROT_PROX_OUT_TH+1)) || (TOUCH_LINROT_PROX_IN_TH > (TOUCH_LINROT_DETECT_OUT_TH-1))) + #error "TOUCH_LINROT_PROX_IN_TH can be (TOUCH_LINROT_PROX_OUT_TH+1 .. TOUCH_LINROT_DETECT_OUT_TH-1)." + #endif +#endif + +#ifndef TOUCH_KEY_DETECT_IN_TH + #error "Please Config TOUCH_KEY_DETECT_IN_TH." +#endif + +#ifndef TOUCH_KEY_DETECT_OUT_TH + #error "Please Config TOUCH_KEY_DETECT_OUT_TH." +#endif + +#if TOUCH_COEFF_TH == 0 + #if ((TOUCH_KEY_DETECT_OUT_TH < (TOUCH_KEY_PROX_IN_TH+1)) || (TOUCH_KEY_DETECT_OUT_TH > (TOUCH_KEY_DETECT_IN_TH-1))) + #error "TOUCH_KEY_DETECT_OUT_TH can be (TOUCH_KEY_PROX_IN_TH+1 .. TOUCH_KEY_DETECT_IN_TH-1)." + #endif +#endif + +#if ((TOUCH_KEY_DETECT_IN_TH < (TOUCH_KEY_DETECT_OUT_TH+1)) || (TOUCH_KEY_DETECT_IN_TH > 255)) + #error "TOUCH_KEY_DETECT_IN_TH can be (TOUCH_KEY_DETECT_OUT_TH+1 .. 255)." +#endif + +#ifndef TOUCH_LINROT_DETECT_IN_TH + #error "Please Config TOUCH_LINROT_DETECT_IN_TH." +#endif + +#ifndef TOUCH_LINROT_DETECT_OUT_TH + #error "Please Config TOUCH_LINROT_DETECT_OUT_TH." +#endif + +#if TOUCH_COEFF_TH == 0 + #if ((TOUCH_LINROT_DETECT_OUT_TH < (TOUCH_LINROT_PROX_IN_TH+1)) || (TOUCH_LINROT_DETECT_OUT_TH > (TOUCH_LINROT_DETECT_IN_TH-1))) + #error "TOUCH_LINROT_DETECT_OUT_TH can be (TOUCH_LINROT_PROX_IN_TH+1 .. TOUCH_LINROT_DETECT_IN_TH-1)." + #endif +#endif + +#if ((TOUCH_LINROT_DETECT_IN_TH < (TOUCH_LINROT_DETECT_OUT_TH+1)) || (TOUCH_LINROT_DETECT_IN_TH > 255)) + #error "TOUCH_LINROT_DETECT_IN_TH can be (TOUCH_LINROT_DETECT_OUT_TH+1 .. 255)." +#endif + +#ifndef TOUCH_KEY_CALIB_TH + #error "Please Config TOUCH_KEY_CALIB_TH." +#endif + +#if ((TOUCH_KEY_CALIB_TH < 0) || (TOUCH_KEY_CALIB_TH > 255)) + #error "TOUCH_KEY_CALIB_TH can be (0 .. 255)." +#endif + +#ifndef TOUCH_LINROT_CALIB_TH + #error "Please Config TOUCH_LINROT_CALIB_TH." +#endif + +#if ((TOUCH_LINROT_CALIB_TH < 0) || (TOUCH_LINROT_CALIB_TH > 255)) + #error "TOUCH_LINROT_CALIB_TH can be (0 .. 255)." +#endif + +#ifndef TOUCH_LINROT_USE_NORMDELTA + #error "Please Config TOUCH_LINROT_USE_NORMDELTA." +#endif + +#if ((TOUCH_LINROT_USE_NORMDELTA < 0) || (TOUCH_LINROT_USE_NORMDELTA > 1)) + #error "TOUCH_LINROT_USE_NORMDELTA can be (0 .. 1)." +#endif + +#ifndef TOUCH_COEFF_TH + #error "Please Config TOUCH_COEFF_TH." +#endif + +#if ((TOUCH_COEFF_TH < 0) || (TOUCH_COEFF_TH > 4)) + #error "TOUCH_COEFF_TH can be (0 .. 4)." +#endif + +#ifndef TOUCH_LINROT_DIR_CHG_POS + #error "Please Config TOUCH_LINROT_DIR_CHG_POS." +#endif + +#if ((TOUCH_LINROT_DIR_CHG_POS < 0) || (TOUCH_LINROT_DIR_CHG_POS > 255)) + #error "TOUCH_LINROT_DIR_CHG_POS can be (0 .. 255)." +#endif + +#ifndef TOUCH_LINROT_RESOLUTION + #error "Please Config TOUCH_LINROT_RESOLUTION." +#endif + +#if ((TOUCH_LINROT_RESOLUTION < 1) || (TOUCH_LINROT_RESOLUTION > 8)) + #error "TOUCH_LINROT_RESOLUTION can be (1 .. 8)." +#endif + +#ifndef TOUCH_DEBOUNCE_PROX + #error "Please Config TOUCH_DEBOUNCE_PROX." +#endif + +#if ((TOUCH_DEBOUNCE_PROX < 0) || (TOUCH_DEBOUNCE_PROX > 63)) + #error "TOUCH_DEBOUNCE_PROX can be (0 .. 63)." +#endif + +#ifndef TOUCH_DEBOUNCE_DETECT + #error "Please Config TOUCH_DEBOUNCE_DETECT." +#endif + +#if ((TOUCH_DEBOUNCE_DETECT < 0) || (TOUCH_DEBOUNCE_DETECT > 63)) + #error "TOUCH_DEBOUNCE_DETECT can be (0 .. 63)." +#endif + +#ifndef TOUCH_DEBOUNCE_RELEASE + #error "Please Config TOUCH_DEBOUNCE_RELEASE." +#endif + +#if ((TOUCH_DEBOUNCE_RELEASE < 0) || (TOUCH_DEBOUNCE_RELEASE > 63)) + #error "TOUCH_DEBOUNCE_RELEASE can be (0 .. 63)." +#endif + +#ifndef TOUCH_DEBOUNCE_CALIB + #error "Please Config TOUCH_DEBOUNCE_CALIB." +#endif + +#if ((TOUCH_DEBOUNCE_CALIB < 0) || (TOUCH_DEBOUNCE_CALIB > 63)) + #error "TOUCH_DEBOUNCE_CALIB can be (0 .. 63)." +#endif + +#ifndef TOUCH_DEBOUNCE_ERROR + #error "Please Config TOUCH_DEBOUNCE_ERROR." +#endif + +#if ((TOUCH_DEBOUNCE_ERROR < 0) || (TOUCH_DEBOUNCE_ERROR > 63)) + #error "TOUCH_DEBOUNCE_ERROR can be (0 .. 63)." +#endif + +#ifndef TOUCH_LINROT_DIR_CHG_DEB + #error "Please Config TOUCH_LINROT_DIR_CHG_DEB." +#endif + +#if ((TOUCH_LINROT_DIR_CHG_DEB < 0) || (TOUCH_LINROT_DIR_CHG_DEB > 63)) + #error "TOUCH_LINROT_DIR_CHG_DEB can be (0 .. 63)." +#endif + +#ifndef TOUCH_ECS_K_DIFFER + #error "Please Config TOUCH_ECS_K_DIFFER." +#endif + +#if ((TOUCH_ECS_K_DIFFER < 0) || (TOUCH_ECS_K_DIFFER > 255)) + #error "TOUCH_ECS_K_DIFFER can be (0 .. 255)." +#endif + +#ifndef TOUCH_ECS_K_SAME + #error "Please Config TOUCH_ECS_K_SAME." +#endif + +#if ((TOUCH_ECS_K_SAME < 0) || (TOUCH_ECS_K_SAME > 255)) + #error "TOUCH_ECS_K_SAME can be (0 .. 255)." +#endif + +#ifndef TOUCH_ECS_DELAY + #error "Please Config TOUCH_ECS_DELAY." +#endif + +#if ((TOUCH_ECS_DELAY < 0) || (TOUCH_ECS_DELAY > 5000)) + #error "TOUCH_ECS_DELAY can be (0 .. 5000)." +#endif + +#ifndef TOUCH_USE_MEAS + #error "Please Config TOUCH_USE_MEAS." +#endif + +#if ((TOUCH_USE_MEAS != 0) && (TOUCH_USE_MEAS != 1)) + #error "TOUCH_USE_MEAS can be (0 .. 1)." +#endif + +#ifndef TOUCH_USE_PROX + #error "Please Config TOUCH_USE_PROX." +#endif + +#if ((TOUCH_USE_PROX != 0) && (TOUCH_USE_PROX != 1)) + #error "TOUCH_USE_PROX can be (0 .. 1)." +#endif + +#ifndef TOUCH_USE_ZONE + #error "Please Config TOUCH_USE_ZONE." +#endif + +#if ((TOUCH_USE_ZONE != 0) && (TOUCH_USE_ZONE != 1)) + #error "TOUCH_USE_ZONE can be (0 .. 1)." +#endif + +#ifndef TOUCH_USE_ACQ_INTERRUPT + #error "Please Config TOUCH_USE_ACQ_INTERRUPT." +#endif + +#if ((TOUCH_USE_ACQ_INTERRUPT != 0) && (TOUCH_USE_ACQ_INTERRUPT != 1)) + #error "TOUCH_USE_ACQ_INTERRUPT can be (0 .. 1)." +#endif + +#ifndef TOUCH_DTO + #error "Please Config TOUCH_DTO." +#endif + +#if ((TOUCH_DTO < 0) || (TOUCH_DTO > 63)) + #error "TOUCH_DTO can be (0 .. 63)." +#endif + +#ifndef TOUCH_TICK_FREQ + #error "Please Config TOUCH_TICK_FREQ." +#endif + +#if ((TOUCH_TICK_FREQ != 125) && (TOUCH_TICK_FREQ != 250) && (TOUCH_TICK_FREQ != 500) &&\ + (TOUCH_TICK_FREQ != 1000) && (TOUCH_TICK_FREQ != 2000)) +#error "TOUCH_TICK_FREQ can be (125, 250, 500, 1000, 2000)." +#endif + +#ifndef TOUCH_USE_DXS + #error "Please Config TOUCH_USE_DXS." +#endif + +#if ((TOUCH_USE_DXS < 0) || (TOUCH_USE_DXS > 1)) + #error "TOUCH_USE_DXS can be (0 .. 1)." +#endif + +#ifndef TOUCH_USE_TIMER_CALLBACK + #error "Please Config TOUCH_USE_TIMER_CALLBACK." +#endif + +#if ((TOUCH_USE_TIMER_CALLBACK != 0) && (TOUCH_USE_TIMER_CALLBACK != 1)) + #error "TOUCH_USE_TIMER_CALLBACK can be (0 .. 1)." +#endif + +#endif /* __TOUCH_CHECK_H */ + +/** @defgroup TSC_Check_Macros Macros + @{ + */ + +/**@} end of group TSC_Check_Macros */ + +/** @defgroup TSC_Check_Enumerations Enumerations + @{ + */ + +/**@} end of group TSC_Check_Enumerations */ + +/** @defgroup TSC_Check_Structures Structures + @{ + */ + +/**@} end of group TSC_Check_Structures */ + +/** @defgroup TSC_Check_Variables Variables + @{ + */ + +/**@} end of group TSC_Check_Variables */ + +/** @defgroup TSC_Check_Functions Functions + @{ + */ + +/**@} end of group TSC_Check_Functions */ + +/**@} end of group TSC_Check_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_config.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_config.h new file mode 100644 index 0000000000..f0508b959d --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_config.h @@ -0,0 +1,583 @@ +/*! + * @file tsc_config.h + * + * @brief Acquisition parameters for APM32F0xx products. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TSC_CONFIG_H +#define __TSC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Config_Driver TSC Config Driver + @{ +*/ + +/** @defgroup TSC_Config_Macros Macros + @{ +*/ + +/** @defgroup Common_Parameters_Number_Of_Elements + @{ +*/ + +/* The number of channels (1..24) */ +#define TOUCH_TOTAL_CHANNELS (11) + +/* The number of blocks (1..8) */ +#define TOUCH_TOTAL_BLOCKS (3) + +/* The number of "Extended" TouchKeys (0..24) */ +#define TOUCH_TOTAL_TOUCHKEYS (5) + +/* The number of "Basic" TouchKeys (0..24) */ +#define TOUCH_TOTAL_TOUCHKEYS_B (0) + +/* The number of "Extended" Linear and Rotary sensors (0..24) */ +#define TOUCH_TOTAL_LINROTS (2) + +/* The number of "Basic" Linear and Rotary sensors (0..24) */ +#define TOUCH_TOTAL_LINROTS_B (0) + +/** The number of sensors/objects (1..24) + * - Count all TouchKeys, Linear and Rotary sensors + */ +#define TOUCH_TOTAL_OBJECTS (7) + +/**@} Common_Parameters_Number_Of_Elements */ + +/** @defgroup Common_Parameters_Optional_Features + @{ +*/ + +/** Record the last measure (0=No, 1=Yes) + * - If No the measure is recalculated using the Reference and Delta + */ +#define TOUCH_USE_MEAS (1) + +/* Zone management usage (0=No, 1=Yes) */ +#define TOUCH_USE_ZONE (0) + +/* Proximity detection usage (0=No, 1=Yes) */ +#define TOUCH_USE_PROX (1) + +/** Use the Timer tick callback (0=No, 1=Yes) + * - When equal to 1, the function TSC_CallBack_TimerTick + */ +#define TOUCH_USE_TIMER_CALLBACK (0) + +/** Acquisition interrupt mode (0=No, 1=Yes) + * - If No the TSC interrupt is not used. + * - If Yes the TSC interrupt is used. + */ +#define TOUCH_USE_ACQ_INTERRUPT (0) + +/**@} Common_Parameters_Optional_Features */ + +/** @defgroup Common_Parameters_Acquisition_limits + @{ +*/ + +/** Minimum acquisition measurement (0..65535) + * - This is the minimum acceptable value for the acquisition measure. + * - The acquisition will be in error if the measure is below this value. + */ +#define TOUCH_ACQ_MIN (10) + +/** Maximum acquisition measurement (255, 511, 1023, 2047, 8191, 16383) + * - This is the maximum acceptable value for the acquisition measure. + * - The acquisition will be in error if the measure is above this value. + */ +#define TOUCH_ACQ_MAX (8191) + +/**@} Common_Parameters_Acquisition_limits */ + +/** @defgroup Common_Parameters_Calibration + @{ +*/ +/** Number of calibration samples (4, 8, 16) + * - Low value = faster calibration but less precision. + * - High value = slower calibration but more precision. + */ +#define TOUCH_CALIB_SAMPLES (16) + +/** Delay in measurement samples before starting the calibration (0..40) + * - This is useful if a noise filter is used. + * - Write 0 to disable the delay. + */ +#define TOUCH_CALIB_DELAY (0) + +/**@} Common_Parameters_Calibration */ + +/** @defgroup Common_Parameters_Thresholds_for_TouchKey + @{ +*/ + +/** TouchKeys Proximity state input threshold (0..255) + * - Enter Proximity state if delta is above + */ +#define TOUCH_KEY_PROX_IN_TH (10) + +/** TouchKeys Proximity state output threshold (0..255) + * - Exit Proximity state if delta is below + */ +#define TOUCH_KEY_PROX_OUT_TH (5) + +/** TouchKeys Detect state input threshold (0..255) + * - Enter Detect state if delta is above + */ +#define TOUCH_KEY_DETECT_IN_TH (200) + +/** TouchKeys Detect state output threshold (0..255) + * - Exit Detect state if delta is below + */ +#define TOUCH_KEY_DETECT_OUT_TH (150) + +/** TouchKeys re-Calibration threshold (0..255) + * - @warning The value is inverted in the sensor state machine + * - Enter Calibration state if delta is below + */ +#define TOUCH_KEY_CALIB_TH (150) + +/** TouchKey, Linear and Rotary sensors thresholds coefficient (0..4) + * This multiplier coefficient is applied on Detect and Re-Calibration thresholds only. + * - 0: disabled + * - 1: thresholds x 2 + * - 2: thresholds x 4 + * - 3: thresholds x 8 + * - 4: thresholds x 16 + */ +#define TOUCH_COEFF_TH (0) + +/**@} Common_Parameters_Thresholds_for_TouchKey */ + +/** @defgroup Common_Parameters_Thresholds_For_Linear_Rotary + @{ +*/ + +/** Linear/Rotary Proximity state input threshold (0..255) + * - Enter Proximity state if delta is above + */ +#define TOUCH_LINROT_PROX_IN_TH (10) + +/** Linear/Rotary Proximity state output threshold (0..255) + * - Exit Proximity state if delta is below + */ +#define TOUCH_LINROT_PROX_OUT_TH (5) + +/** Linear/Rotary Detect state input threshold (0..255) + * - Enter Detect state if delta is above + */ +#define TOUCH_LINROT_DETECT_IN_TH (20) + +/** Linear/Rotary Detect state output threshold (0..255) + * - Exit Detect state if delta is below + */ +#define TOUCH_LINROT_DETECT_OUT_TH (15) + +/** Linear/Rotary Re-Calibration threshold (0..255) + * - @warning The value is inverted in the sensor state machine + * - Enter Calibration state if delta is below + */ +#define TOUCH_LINROT_CALIB_TH (30) + +/** Linear/Rotary Delta normalization (0=No, 1=Yes) + * - When this parameter is set, a coefficient is applied on all Delta of all sensors + * in order to normalize them and to improve the position calculation. + * - These coefficients must be defined in a constant table + * - The MSB is the coefficient integer part, the LSB is the coefficient real part. + * Examples: + * - To apply a factor 1.10: + * 0x01 to the MSB + * 0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A) + * - To apply a factor 0.90: + * 0x00 to the MSB + * 0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6) + */ +#define TOUCH_LINROT_USE_NORMDELTA (0) + +/**@} Common_Parameters_Thresholds_For_Linear_Rotary */ + +/** @defgroup Common_Parameters_Used_Linear_Rotary + @{ +*/ + +/** Select which Linear and Rotary sensors you use in your application. + * - 0 = Not Used + * - 1 = Used + * + * LIN = Linear sensor + * ROT = Rotary sensor + * M1 = Mono electrodes design with 0/255 position at extremities of the sensor + * M2 = Mono electrodes design + * H = Half-ended electrodes design + * D = Dual electrodes design + */ +#define TOUCH_USE_3CH_LIN_M1 (1) +#define TOUCH_USE_3CH_LIN_M2 (1) +#define TOUCH_USE_3CH_LIN_H (1) +#define TOUCH_USE_3CH_ROT_M (1) + +#define TOUCH_USE_4CH_LIN_M1 (1) +#define TOUCH_USE_4CH_LIN_M2 (1) +#define TOUCH_USE_4CH_LIN_H (1) +#define TOUCH_USE_4CH_ROT_M (1) + +#define TOUCH_USE_5CH_LIN_M1 (1) +#define TOUCH_USE_5CH_LIN_M2 (1) +#define TOUCH_USE_5CH_LIN_H (1) +#define TOUCH_USE_5CH_ROT_M (1) +#define TOUCH_USE_5CH_ROT_D (1) + +#define TOUCH_USE_6CH_LIN_M1 (1) +#define TOUCH_USE_6CH_LIN_M2 (1) +#define TOUCH_USE_6CH_LIN_H (1) +#define TOUCH_USE_6CH_ROT_M (1) + +/**@} Common_Parameters_Used_Linear_Rotary */ + +/** @defgroup Common_Parameters_Position_Linear_Rotary + @{ +*/ + +/** Position resolution in number of bits (1..8) + * - A Low value will result in a low resolution and will be less subject to noise. + * - A High value will result in a high resolution and will be more subject to noise. + */ +#define TOUCH_LINROT_RESOLUTION (7) + +/** Direction change threshold in position unit (0..255) + * - Defines the default threshold used during the change direction process. + * - A Low value will result in a faster direction change. + * - A High value will result in a slower direction change. + */ +#define TOUCH_LINROT_DIR_CHG_POS (10) + +/** Direction change debounce (0..63) + * - Defines the default integrator counter used during the change direction process. + * - This counter is decremented when the same change in the position is detected and the direction will + * change after this counter reaches zero. + * - A Low value will result in a faster direction change. + * - A High value will result in a slower direction change. + */ +#define TOUCH_LINROT_DIR_CHG_DEB (1) + +/**@} Common_Parameters_Position_Linear_Rotary */ + +/** @defgroup Common_Parameters_Debounce_Counters + @{ +*/ + +/** Proximity state debounce in samples unit (0..63) + * - A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering. + * - A High value will result in improving the system noise immunity but will increase the system response time. + */ +#define TOUCH_DEBOUNCE_PROX (3) + +/** Detect state debounce in samples unit (0..63) + * - A Low value will result in a higher sensitivity during the detection but with less noise filtering. + * - A High value will result in improving the system noise immunity but will increase the system response time. + */ +#define TOUCH_DEBOUNCE_DETECT (3) + +/** Release state debounce in samples unit (0..63) + * - A Low value will result in a higher sensitivity during the end-detection but with less noise filtering. + * - A High value will result in a lower sensitivity during the end-detection but with more noise filtering. + */ +#define TOUCH_DEBOUNCE_RELEASE (3) + +/** Re-calibration state debounce in samples unit (0..63) + * - A Low value will result in a higher sensitivity during the recalibration but with less noise filtering. + * - A High value will result in a lower sensitivity during the recalibration but with more noise filtering. + */ +#define TOUCH_DEBOUNCE_CALIB (3) + +/** Error state debounce in samples unit (0..63) + * - A Low value will result in a higher sensitivity to enter in error state. + * - A High value will result in a lower sensitivity to enter in error state. + */ +#define TOUCH_DEBOUNCE_ERROR (3) + +/**@} Common_Parameters_Debounce_Counters */ + +/** @defgroup Common_Parameters_Environment_Change_System (ECS) + @{ +*/ + +/** Environment Change System Different K factor (0..255) + * - The higher value is K, the faster is the response time. + */ +#define TOUCH_ECS_K_DIFFER (10) + +/** Environment Change System Same K factor (0..255) + * - The higher value is K, the faster is the response time. + */ +#define TOUCH_ECS_K_SAME (20) + +/** Environment Change System delay in msec (0..5000) + * - The ECS will be started after this delay and when all sensors are in Release state. + */ +#define TOUCH_ECS_DELAY (500) + +/**@} Common_Parameters_Environment_Change_System */ + +/** @defgroup Common_Parameters_Detection_Time_Out (DTO) + @{ +*/ + +/** Detection Time Out delay in seconds (0..63) + * - Value 0: DTO processing not compiled in the code (to gain size if not used). + * - Value 1: Default time out infinite. + * - Value between 2 and 63: Default time out between value n-1 and n. + * - Examples: + * - With a DTO equal to 2, the time out is between 1s and 2s. + * - With a DTO equal to 63, the time out is between 62s and 63s. + * + *@note The DTO can be changed in run-time by the application only if the + * default value is between 1 and 63. + */ +#define TOUCH_DTO (0) + +/**@} Common_Parameters_Detection_Time_Out */ + +/** @defgroup Common_Parameters_Detection_Exclusion_System (DXS) + @{ +*/ + +/** Detection Exclusion System (0=No, 1=Yes) */ +#define TOUCH_USE_DXS (0) + +/**@} Common_Parameters_Detection_Exclusion_System */ + +/** @defgroup Common_Parameters_Miscellaneous_Parameters + @{ +*/ + +/** Timing tick frequency in Hz (125, 250, 500, 1000, 2000) + * - Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms + */ +#define TOUCH_TICK_FREQ (1000) + +/** Delay for discharging Cx and Cs capacitors (0..65535) + * - The value corresponds to the Softdelay function parameter. + * - 500 gives around 53 delay whatever HCLK + * - 1000 gives around 106 delay whatever HCLK + * - 2000 gives around 210 delay whatever HCLK + */ +#define TOUCH_DELAY_DISCHARGE_ALL (1000) + +/**@} Common_Parameters_Miscellaneous_Parameters */ + +/** @defgroup APM32F0xx_Parameters_GPIOs_Configuration + @{ +*/ + +/** TSC GPIOs Configuration selection (0..1) + * - 0: Manual. The TSC GPIOs configuration must be done by the application code. + * - 1: Automatic. The TOUCH_TSC_GROUPx_IOy parameters below must be filled up. + * The TSC GPIOs configuration is automatically done by the Touch driver. + */ +#define TOUCH_TSC_GPIO_CONFIG (1) + +/* DO NOT CHANGE THESE VALUES */ +/* These defines must be applied to the TOUCH_TSC_GROUPx_IOy parameters below */ +#define NU (0) /*!< Not Used IO */ +#define CHANNEL (1) /*!< Channel IO */ +#define SHIELD (2) /*!< Shield IO (= Channel IO but not acquired) */ +#define SAMPCAP (3) /*!< Sampling Capacitor IO */ + +/* If TOUCH_TSC_GPIO_CONFIG=0 these parameters are ignored */ +/* If TOUCH_TSC_GPIO_CONFIG=1 assign each TOUCH_TSC_GROUPx_IOy parameters below */ + +#define TOUCH_TSC_GROUP1_IO1 SAMPCAP /*!< PA0 */ +#define TOUCH_TSC_GROUP1_IO2 CHANNEL /*!< PA1 */ +#define TOUCH_TSC_GROUP1_IO3 CHANNEL /*!< PA2 */ +#define TOUCH_TSC_GROUP1_IO4 NU /*!< PA3 */ + +#define TOUCH_TSC_GROUP2_IO1 SAMPCAP /*!< PA4 */ +#define TOUCH_TSC_GROUP2_IO2 CHANNEL /*!< PA5 */ +#define TOUCH_TSC_GROUP2_IO3 CHANNEL /*!< PA6 */ +#define TOUCH_TSC_GROUP2_IO4 CHANNEL /*!< PA7 */ + +#define TOUCH_TSC_GROUP3_IO1 SAMPCAP /*!< PC5 */ +#define TOUCH_TSC_GROUP3_IO2 NU /*!< PB0 */ +#define TOUCH_TSC_GROUP3_IO3 CHANNEL /*!< PB1 */ +#define TOUCH_TSC_GROUP3_IO4 CHANNEL /*!< PB2 */ + +#define TOUCH_TSC_GROUP4_IO1 SAMPCAP /*!< PA9 */ +#define TOUCH_TSC_GROUP4_IO2 NU /*!< PA10 */ +#define TOUCH_TSC_GROUP4_IO3 CHANNEL /*!< PA11 */ +#define TOUCH_TSC_GROUP4_IO4 CHANNEL /*!< PA12 */ + +#define TOUCH_TSC_GROUP5_IO1 NU /*!< PB3 */ +#define TOUCH_TSC_GROUP5_IO2 NU /*!< PB4 */ +#define TOUCH_TSC_GROUP5_IO3 NU /*!< PB6 */ +#define TOUCH_TSC_GROUP5_IO4 NU /*!< PB7 */ + +#define TOUCH_TSC_GROUP6_IO1 SAMPCAP /*!< PB11 */ +#define TOUCH_TSC_GROUP6_IO2 NU /*!< PB12 */ +#define TOUCH_TSC_GROUP6_IO3 CHANNEL /*!< PB13 */ +#define TOUCH_TSC_GROUP6_IO4 CHANNEL /*!< PB14 */ + +/* Warning: this group is available on some devices only */ +#define TOUCH_TSC_GROUP7_IO1 NU /*!< PE2 */ +#define TOUCH_TSC_GROUP7_IO2 NU /*!< PE3 */ +#define TOUCH_TSC_GROUP7_IO3 NU /*!< PE4 */ +#define TOUCH_TSC_GROUP7_IO4 NU /*!< PE5 */ + +/* Warning: this group is available on some devices only */ +#define TOUCH_TSC_GROUP8_IO1 NU /*!< PD12 */ +#define TOUCH_TSC_GROUP8_IO2 NU /*!< PD13 */ +#define TOUCH_TSC_GROUP8_IO3 NU /*!< PD14 */ +#define TOUCH_TSC_GROUP8_IO4 NU /*!< PD15 */ + +/**@} APM32F0xx_Parameters_GPIOs_Configuration */ + +/** @defgroup APM32F0xx_Parameters_Charge_Transfer_Pulses + @{ +*/ + +/** Charge Transfer Pulse High (0..15) + * - 0: 1 x tPGCLK + * - 1: 2 x tPGCLK + * - ... + * - 15: 16 x tPGCLK + */ +#define TOUCH_TSC_CTPHSEL (1) + +/** Charge Transfer Pulse Low (0..15) + * - 0: 1 x tPGCLK + * - 1: 2 x tPGCLK + * - ... + * - 15: 16 x tPGCLK + */ +#define TOUCH_TSC_CTPLSEL (1) + +/** Pulse Generator Clock Divide Factor Select (0..7) + * - 0: fPGCLK = fHCLK + * - 1: fPGCLK = fHCLK/2 + * - ... + * - 7: fPGCLK = fHCLK/128 + */ +#define TOUCH_TSC_PGCDFSEL (3) + +/**@} APM32F0xx_Parameters_Charge_Transfer_Pulses */ + +/** @defgroup APM32F0xx_Parameters_GPIOs + @{ +*/ + +/** TSC IOs default mode when no on-going acquisition (0..1) + * - 0: Output push-pull low + * - 1: Input floating + * @note To ensure a correct operation in noisy environment, this parameter should + * be configured to output push-pull low. + */ +#define TOUCH_TSC_IODEF (0) + +/** Acquisition Mode (0..1) + * - 0: Normal acquisition mode + * - 1: Synchronized acquisition mode + */ +#define TOUCH_TSC_AMCFG (0) + +/** Synchronization Pin (0..1) + * - 0: PB8 + * - 1: PB10 + */ +#define TOUCH_TSC_SYNC_PIN (0) + +/** Synchronization Polarity (0..1) + * - 0: Falling edge only + * - 1: Rising edge and high level + */ +#define TOUCH_TSC_SYNC_POL (0) + +/**@} APM32F0xx_Parameters_GPIOs */ + +/** @addtogroup APM32F0xx_Parameters_Spread_Spectrum + @{ +*/ + +/* Use Spread Spectrum (0=No, 1=Yes) */ +#define TOUCH_TSC_USE_SSEN (0) + +/** Spread Spectrum Error Value Select (0..127) + * - 0: 1 x tSSCLK + * - 1: 2 x tSSCLK + * - ... + * - 127: 128 x tSSCLK + */ +#define TOUCH_TSC_SSERRVSEL (0) + +/** Spread Spectrum Clock Divide Factor Select (0..1) + * - 0: fSSCLK = fHCLK + * - 1: fSSCLK = fHCLK/2 + */ +#define TOUCH_TSC_SSCDFSEL (0) + +/**@} APM32F0xx_Parameters_Spread_Spectrum */ + +/* Includes */ +/* Must be placed last */ +#include "tsc_check.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_CONFIG_H */ + +/**@} end of group TSC_Config_Macros */ + +/** @defgroup TSC_Config_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Config_Enumerations */ + +/** @defgroup TSC_Config_Structures Structures + @{ +*/ + +/**@} end of group TSC_Config_Structures */ + +/** @defgroup TSC_Config_Variables Variables + @{ +*/ + +/**@} end of group TSC_Config_Variables */ + +/** @defgroup TSC_Config_Functions Functions + @{ +*/ + +/**@} end of group TSC_Config_Functions */ +/**@} end of group TSC_Config_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_dxs.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_dxs.h new file mode 100644 index 0000000000..166a5c3691 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_dxs.h @@ -0,0 +1,95 @@ +/*! + * @file tsc_dxs.h + * + * @brief This file contains external declarations of the tsc_dxs.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_DXS_H +#define __TOUCH_DXS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_object.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_DXS_Driver TSC DXS Driver + @{ +*/ + +/** @defgroup TSC_DXS_Macros Macros + @{ +*/ + +#define FOR_OBJ_TYPE TSC_Globals.For_Obj->Type + +#define FOR_KEY TSC_Globals.For_Key +#define FOR_KEY_STATEID TSC_Globals.For_Key->p_Data->StateId +#define FOR_KEY_DXSLOCK TSC_Globals.For_Key->p_Data->DxsLock +#define FOR_KEY_CHANGE TSC_Globals.For_Key->p_Data->Change + +#define FOR_LINROT TSC_Globals.For_LinRot +#define FOR_LINROT_STATEID TSC_Globals.For_LinRot->p_Data->StateId +#define FOR_LINROT_DXSLOCK TSC_Globals.For_LinRot->p_Data->DxsLock +#define FOR_LINROT_CHANGE TSC_Globals.For_LinRot->p_Data->Change + +/**@} end of group TSC_DXS_Macros */ + +/** @defgroup TSC_DXS_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_DXS_Enumerations */ + +/** @defgroup TSC_DXS_Structures Structures + @{ +*/ + +/**@} end of group TSC_DXS_Structures */ + +/** @defgroup TSC_DXS_Variables Variables + @{ +*/ + +/**@} end of group TSC_DXS_Variables */ + +/** @defgroup TSC_DXS_Functions Functions + @{ +*/ + +void TSC_Dxs_FirstObj(CONST TSC_ObjectGroup_T* objgrp); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_DXS_H */ + +/**@} end of group TSC_DXS_Functions */ +/**@} end of group TSC_DXS_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_ecs.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_ecs.h new file mode 100644 index 0000000000..55b1f3ae13 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_ecs.h @@ -0,0 +1,94 @@ +/*! + * @file tsc_ecs.h + * + * @brief This file contains external declarations of the tsc_ecs.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_ECS_H +#define __TOUCH_ECS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_object.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_ECS_Driver TSC ECS Driver + @{ +*/ + +/** @defgroup TSC_ECS_Macros Macros + @{ +*/ + +#define FOR_OBJ_TYPE TSC_Globals.For_Obj->Type +#define FOR_KEY_REF TSC_Globals.For_Key->p_ChD->Refer +#define FOR_KEY_REFREST TSC_Globals.For_Key->p_ChD->RefRest +#define FOR_KEY_DELTA TSC_Globals.For_Key->p_ChD->Delta +#define FOR_KEY_STATEID TSC_Globals.For_Key->p_Data->StateId + +#define FOR_LINROT_STATEID TSC_Globals.For_LinRot->p_Data->StateId +#define FOR_LINROT_NB_CHANNELS TSC_Globals.For_LinRot->NumChannel + +/**@} end of group TSC_ECS_Macros */ + +/** @defgroup TSC_ECS_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_ECS_Enumerations */ + +/** @defgroup TSC_ECS_Structures Structures + @{ +*/ + +/**@} end of group TSC_ECS_Structures */ + +/** @defgroup TSC_ECS_Variables Variables + @{ +*/ + +/**@} end of group TSC_ECS_Variables */ + +/** @defgroup TSC_ECS_Functions Functions + @{ +*/ + +TSC_tKCoeff_T TSC_Ecs_CalculateK(TSC_ObjectGroup_T* objgrp, TSC_tKCoeff_T kDiffer, TSC_tKCoeff_T kSame); +void TSC_Ecs_ProcessK(TSC_ObjectGroup_T* objgrp, TSC_tKCoeff_T kCoeff); +TSC_STATUS_T TSC_Ecs_Process(TSC_ObjectGroup_T* objgrp); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_ECS_H */ + +/**@} end of group TSC_ECS_Functions*/ +/**@} end of group TSC_ECS_Driver */ +/**@} end of group TSC_Driver_Library*/ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_filter.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_filter.h new file mode 100644 index 0000000000..ec5a291042 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_filter.h @@ -0,0 +1,90 @@ +/*! + * @file tsc_filter.h + * + * @brief This file contains external declarations of the tsc_filter.c file. + * + * @version V1.0.0 + * + * @date 2022-02-21 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TSC_FILTER_H +#define __TSC_FILTER_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_acq.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Filter_Driver TSC Filter Driver + @{ +*/ + +/** @defgroup TSC_Filter_Macros Macros + @{ +*/ + +/* Can be[0..5] - Warning: all thresholds must be shifted if different from 0 */ +#define ACQ_FILTER_RANGE (0) + +/* Can be[1..255] - First order filter coefficient (k = ACQ_FILTER_COEFF/256) */ +#define ACQ_FILTER_COEFF (128) + +/**@} end of group TSC_Filter_Macros */ + +/** @defgroup TSC_Filter_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Filter_Enumerations */ + +/** @defgroup TSC_Filter_Structures Structures + @{ +*/ + +/**@} end of group TSC_Filter_Structures */ + +/** @defgroup TSC_Filter_Variables Variables + @{ +*/ + +/**@} end of group TSC_Filter_Variables */ + +/** @defgroup TSC_Filter_Functions Functions + @{ +*/ + +TSC_tMeas_T TSC_Filt_MeasFilter(TSC_tMeas_T preMeasn, TSC_tMeas_T curMeasn); +TSC_tDelta_T TSC_Filt_DeltaFilter(TSC_tDelta_T delta); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_FILTER_H */ + +/**@} end of group TSC_Filter_Functions */ +/**@} end of group TSC_Filter_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_linrot.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_linrot.h new file mode 100644 index 0000000000..58c05da738 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_linrot.h @@ -0,0 +1,273 @@ +/*! + * @file tsc_linrot.h + * + * @brief This file contains external declarations of the tsc_linrot.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_LINROT_H +#define __TOUCH_LINROT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_acq.h" +#include "tsc_time.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Linrot_Driver TSC Linrot Driver + @{ +*/ + +/** @defgroup TSC_Linrot_Macros Macros + @{ +*/ + +#define TSC_SCTCOMP_3CH_LIN_M1 ((TSC_tNum_T)(128)) +#define TSC_POSCORR_3CH_LIN_M1 ((TSC_tNum_T)( 64)) +#define TSC_SCTCOMP_3CH_LIN_M2 ((TSC_tNum_T)(256)) +#define TSC_POSCORR_3CH_LIN_M2 ((TSC_tNum_T)(256)) + +#define TSC_SCTCOMP_3CH_LIN_H ((TSC_tNum_T)(128)) +#define TSC_POSCORR_3CH_LIN_H ((TSC_tNum_T)(128)) + +#define TSC_SCTCOMP_3CH_ROT_M ((TSC_tNum_T)( 85)) + +#define TSC_SCTCOMP_4CH_LIN_M1 ((TSC_tNum_T)( 85)) +#define TSC_POSCORR_4CH_LIN_M1 ((TSC_tNum_T)( 43)) +#define TSC_SCTCOMP_4CH_LIN_M2 ((TSC_tNum_T)(128)) +#define TSC_POSCORR_4CH_LIN_M2 ((TSC_tNum_T)(128)) + +#define TSC_SCTCOMP_4CH_LIN_H ((TSC_tNum_T)( 85)) +#define TSC_POSCORR_4CH_LIN_H ((TSC_tNum_T)( 85)) + +#define TSC_SCTCOMP_4CH_ROT_M ((TSC_tNum_T)( 64)) + +#define TSC_SCTCOMP_5CH_LIN_M1 ((TSC_tNum_T)( 64)) +#define TSC_POSCORR_5CH_LIN_M1 ((TSC_tNum_T)( 32)) +#define TSC_SCTCOMP_5CH_LIN_M2 ((TSC_tNum_T)( 85)) +#define TSC_POSCORR_5CH_LIN_M2 ((TSC_tNum_T)( 85)) + +#define TSC_SCTCOMP_5CH_LIN_H ((TSC_tNum_T)( 64)) +#define TSC_POSCORR_5CH_LIN_H ((TSC_tNum_T)( 64)) + +#define TSC_SCTCOMP_5CH_ROT_M ((TSC_tNum_T)( 51)) + +#define TSC_SCTCOMP_5CH_ROT_D ((TSC_tNum_T)( 26)) + +#define TSC_SCTCOMP_6CH_LIN_M1 ((TSC_tNum_T)( 51)) +#define TSC_POSCORR_6CH_LIN_M1 ((TSC_tNum_T)( 25)) +#define TSC_SCTCOMP_6CH_LIN_M2 ((TSC_tNum_T)( 64)) +#define TSC_POSCORR_6CH_LIN_M2 ((TSC_tNum_T)( 64)) + +#define TSC_SCTCOMP_6CH_LIN_H ((TSC_tNum_T)( 51)) +#define TSC_POSCORR_6CH_LIN_H ((TSC_tNum_T)( 51)) + +#define TSC_SCTCOMP_6CH_ROT_M ((TSC_tNum_T)( 43)) + +/**@} end of group TSC_Linrot_Macros */ + +/** @defgroup TSC_Linrot_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Linrot_Enumerations */ + +/** @defgroup TSC_Linrot_Structures Structures + @{ +*/ + +/** + * @brief Contains all data related to Linear and Rotary sensor. + * Variables of this structure type must be placed in RAM only. + */ +typedef struct +{ + TSC_STATEID_T StateId; /*!< Current state identifier */ + TSC_tsignPosition_T RawPosition; /*!< Raw position */ + TSC_tsignPosition_T Position; /*!< Scaled position */ + TSC_tCounter_T CounterDebounce; /*!< Counter for debounce and calibration management */ + unsigned int CounterDTO : 6; /*!< Counter for DTO management (TSC_tCounter_T) */ + unsigned int Change : 1; /*!< The State is different from the previous one (TSC_STATE_T) */ + unsigned int PosChange : 1; /*!< The RawPosition/Position is different from the previous one (TSC_STATE_T) */ + unsigned int CounterDirection : 6; /*!< Counter for direction debounce management (TSC_tCounter_T) */ + unsigned int DxsLock : 1; /*!< The State is locked by the DxS (TSC_BOOL_T) */ + unsigned int Direction : 1; /*!< Movement direction (TSC_BOOL_T) */ +} TSC_LinRotData_T; + +/** + * @brief Contains all parameters related to Linear and Rotary sensor. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ + /* Thresholds */ +#if TOUCH_USE_PROX > 0 + TSC_tThreshold_T ProxInTh; /*!< Proximity state in threshold */ + TSC_tThreshold_T ProxOutTh; /*!< Proximity state out threshold */ +#endif + TSC_tThreshold_T DetectInTh; /*!< Detection state in threshold */ + TSC_tThreshold_T DetectOutTh; /*!< Detection state out threshold */ + TSC_tThreshold_T CalibTh; /*!< Calibration state threshold */ + + /* Debounce counters */ + TSC_tCounter_T CounterDebCalib; /*!< Debounce counter to enter in Calibration state */ +#if TOUCH_USE_PROX > 0 + TSC_tCounter_T CounterDebProx; /*!< Debounce counter to enter in Proximity state */ +#endif + TSC_tCounter_T CounterDebDetect; /*!< Debounce counter to enter in Detect state */ + TSC_tCounter_T CounterDebRelease; /*!< Debounce counter to enter in Release state */ + TSC_tCounter_T CounterDebError; /*!< Debounce counter to enter in Error state */ + TSC_tCounter_T CounterDebDirection; /*!< Debounce counter for the direction change */ + + /* Other parameters */ + TSC_tCounter_T Resolution; /*!< Position resolution */ + TSC_tsignPosition_T DirChangePos; /*!< Direction change position threshold */ +} TSC_LinRotParam_T; + +/** + * @brief Contains all parameters related to Linear and Rotary sensor. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ + TSC_LinRotData_T* p_Data; /*!< Data (state id, counter, flag, ...) */ + TSC_LinRotParam_T* p_Param; /*!< Parameters (thresholds, debounce, ...) */ + TSC_Channel_Data_T* p_ChD; /*!< First Channel Data (Meas, Refer, Delta, ...) */ + TSC_tNum_T NumChannel; /*!< Number of channels */ + CONST uint16_t* p_DeltaCoeff; /*!< Coefficient to apply on Delta */ + CONST TSC_tPosition_T* p_PosOff; /*!< Position offset table */ + TSC_tNum_T SctComp; /*!< Sector Computation */ + TSC_tNum_T PosCorr; /*!< Position Correction */ + CONST TSC_State_T* p_SM; /*!< State Machine */ + CONST TSC_LinRotMethods_T* p_Methods; /*!< Methods */ +} TSC_LinRot_T; + +/** + * @brief Contains all parameters related to Linear and Rotary sensor. + * Variables of this structure type can be placed in RAM or ROM. + * Basic sensor does not contain its own state machine and methods. + * It used default ones instead to gain memory space. + */ +typedef struct +{ + TSC_LinRotData_T* p_Data; /*!< Data (state id, counter, flag, ...) */ + TSC_LinRotParam_T* p_Param; /*!< Parameters (thresholds, debounce, ...) */ + TSC_Channel_Data_T* p_ChD; /*!< First Channel Data (Meas, Refer, Delta, ...) */ + TSC_tNum_T NumChannel; /*!< Number of channels */ + CONST uint16_t* p_DeltaCoeff; /*!< Coefficient to apply on Delta */ + CONST TSC_tPosition_T* p_PosOff; /*!< Position offset table */ + TSC_tNum_T SctComp; /*!< Sector Computation */ + TSC_tNum_T PosCorr; /*!< Position Correction */ +} TSC_LinRotB_T; + +/**@} end of group TSC_Linrot_Structures */ + +/** @defgroup TSC_Linrot_Variables Variables + @{ +*/ + +/* Position offset constant tables and corrections */ +extern CONST TSC_tPosition_T TSC_POSOFF_3CH_LIN_M1[3][3]; +extern CONST TSC_tPosition_T TSC_POSOFF_3CH_LIN_M2[3][3]; +extern CONST TSC_tPosition_T TSC_POSOFF_3CH_LIN_H[3][3]; +extern CONST TSC_tPosition_T TSC_POSOFF_3CH_ROT_M[3][3]; + +extern CONST TSC_tPosition_T TSC_POSOFF_4CH_LIN_M1[4][4]; +extern CONST TSC_tPosition_T TSC_POSOFF_4CH_LIN_M2[4][4]; +extern CONST TSC_tPosition_T TSC_POSOFF_4CH_LIN_H[4][4]; +extern CONST TSC_tPosition_T TSC_POSOFF_4CH_ROT_M[4][4]; + +extern CONST TSC_tPosition_T TSC_POSOFF_5CH_LIN_M1[5][5]; +extern CONST TSC_tPosition_T TSC_POSOFF_5CH_LIN_M2[5][5]; +extern CONST TSC_tPosition_T TSC_POSOFF_5CH_LIN_H[5][5]; +extern CONST TSC_tPosition_T TSC_POSOFF_5CH_ROT_M[5][5]; +extern CONST TSC_tPosition_T TSC_POSOFF_5CH_ROT_D[5][5]; + +extern CONST TSC_tPosition_T TSC_POSOFF_6CH_LIN_M1[6][6]; +extern CONST TSC_tPosition_T TSC_POSOFF_6CH_LIN_M2[6][6]; +extern CONST TSC_tPosition_T TSC_POSOFF_6CH_LIN_H[6][6]; +extern CONST TSC_tPosition_T TSC_POSOFF_6CH_ROT_M[6][6]; + +/**@} end of group TSC_Linrot_Variables */ + +/** @defgroup TSC_Linrot_Functions Functions + @{ +*/ + +/* "Object methods" functions */ +void TSC_Linrot_Config(void); +void TSC_Linrot_Process(void); +TSC_STATUS_T TSC_Linrot_CalcPos(void); + +/* Utility functions */ +void TSC_Linrot_ConfigCalibrationState(TSC_tCounter_T delay); +void TSC_Linrot_ConfigOffState(void); +void TSC_Linrot_ConfigBurstOnlyState(void); +TSC_STATEID_T TSC_Linrot_ReadStateId(void); +TSC_STATEMASK_T TSC_Linrot_ReadStateMask(void); +TSC_tNum_T TSC_Linrot_ReadChangeFlag(void); + +/* State machine functions */ +void TSC_Linrot_ProcessCalibrationState(void); +void TSC_Linrot_ProcessDebCalibrationState(void); +void TSC_Linrot_ProcessReleaseState(void); +void TSC_Linrot_ProcessDebReleaseProxState(void); +void TSC_Linrot_ProcessDebReleaseDetectState(void); +void TSC_Linrot_ProcessDebReleaseTouchState(void); +void TSC_Linrot_ProcessProxState(void); +void TSC_Linrot_ProcessDebProxState(void); +void TSC_Linrot_ProcessDebProxDetectState(void); +void TSC_Linrot_ProcessDebProxTouchState(void); +void TSC_Linrot_ProcessDetectState(void); +void TSC_Linrot_ProcessDebDetectState(void); +void TSC_Linrot_ProcessTouchState(void); +void TSC_Linrot_ProcessDebTouchState(void); +void TSC_Linrot_ProcessDebErrorState(void); + +/* Private functions */ +void TSC_Linrot_ReadTimeForDTO(void); +void TSC_Linrot_Process_AllChannel_Status(TSC_OBJ_STATUS_T status); +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DataReady(void); +TSC_STATUS_T TSC_Linrot_Process_AllChannel_AcqStatus(TSC_ACQ_STATUS_T status); +TSC_STATUS_T TSC_Linrot_Process_OneChannel_AcqStatusError(void); +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DeltaBelowEquMinus(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd); +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DeltaAboveEqu(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd); +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DeltaAbove(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd); +TSC_STATUS_T TSC_Linrot_Process_AllChannel_DeltaBelowEqu(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd); +void TSC_Linrot_Process_AllChannel_ClearRef(void); +TSC_tDelta_T TSC_Linrot_NormDelta(TSC_Channel_Data_T* channel, TSC_tIndex_T index); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_LINROT_H */ + +/**@} end of group TSC_Linrot_Functions */ +/**@} end of group TSC_Linrot_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_object.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_object.h new file mode 100644 index 0000000000..64def000a6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_object.h @@ -0,0 +1,126 @@ +/*! + * @file tsc_object.h + * + * @brief This file contains external declarations of the tsc_object.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_OBJECT_H +#define __TOUCH_OBJECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_touchkey.h" +#include "tsc_linrot.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Object_Driver TSC Object Driver + @{ +*/ + +/** @defgroup TSC_Object_Macros Macros + @{ +*/ + +#define TSC_OBJ_TYPE_KEY_MASK (0x10) /*!< TouchKey object mask */ +#define TSC_OBJ_TYPE_LINROT_MASK (0x20) /*!< Linear and Rotary objects mask */ +#define TSC_OBJ_TYPE_TRACKNAV_MASK (0x40) /*!< TrackPad and NaviPad objects mask */ + +/**@} end of group TSC_Object_Macros */ + +/** @defgroup TSC_Object_Enumerations Enumerations + @{ +*/ + +/** + * @brief Contains all different kinds of sensors + */ +typedef enum +{ + TSC_OBJ_TOUCHKEY = (TSC_OBJ_TYPE_KEY_MASK + 0), /*!< Normal TouchKey */ + TSC_OBJ_TOUCHKEYB = (TSC_OBJ_TYPE_KEY_MASK + 1), /*!< Basic TouchKey */ + TSC_OBJ_LINEAR = (TSC_OBJ_TYPE_LINROT_MASK + 0), /*!< Normal Linear sensor */ + TSC_OBJ_LINEARB = (TSC_OBJ_TYPE_LINROT_MASK + 1), /*!< Basic Linear sensor */ + TSC_OBJ_ROTARY = (TSC_OBJ_TYPE_LINROT_MASK + 2), /*!< Normal Rotary sensor */ + TSC_OBJ_ROTARYB = (TSC_OBJ_TYPE_LINROT_MASK + 3), /*!< Basic Rotary sensor */ + TSC_OBJ_TRACKPAD = (TSC_OBJ_TYPE_TRACKNAV_MASK + 0), /*!< TrackPad sensor */ + TSC_OBJ_NAVIPAD = (TSC_OBJ_TYPE_TRACKNAV_MASK + 1) /*!< NaviPad sensor */ +} TSC_OBJECT_T; + +/**@} end of group TSC_Object_Enumerations */ + +/** @defgroup TSC_Object_Structures Data Object Structures + @{ +*/ + +/** + * @brief Contains the definition of an Object. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ + TSC_OBJECT_T Type; /*!< Object type */ + void* MyObj; /*!< Pointer to the object */ +} TSC_Object_T; + +/** + * @brief Contains the definition of a Group of Objects. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ + CONST TSC_Object_T* p_Obj; /*!< Pointer to the first object */ + TSC_tNum_T NbObjects; /*!< Number of objects in the group */ + TSC_tNum_T StateMask; /*!< "OR" of all objects state mask */ + TSC_STATE_T Change; /*!< The State is different from the previous one */ + TSC_tIndex_T execution; /*!< Flag for the ECS execution */ +#if TOUCH_ECS_DELAY > 0 + TSC_tIndex_T wait; /*!< Flag for the ECS delay */ + TSC_tTick_ms_T time; /*!< Keep the time for the ECS delay */ +#endif +} TSC_ObjectGroup_T; + +/**@} end of group TSC_Object_Structures */ + +/** @defgroup TSC_Object_Functions Functions + @{ +*/ + +void TSC_Obj_ConfigGroup(TSC_ObjectGroup_T* objgrp); +void TSC_Obj_ProcessGroup(TSC_ObjectGroup_T* objgrp); +void TSC_Obj_ConfigGlobalObj(CONST TSC_Object_T* pObj); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_OBJECT_H */ + +/**@} end of group TSC_Object_Functions */ +/**@} end of group TSC_Object_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_time.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_time.h new file mode 100644 index 0000000000..806535aa5a --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_time.h @@ -0,0 +1,87 @@ +/*! + * @file tsc_time.h + * + * @brief This file contains external declarations of the tsc_time.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_TIME_H +#define __TOUCH_TIME_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f0xx.h" +#include "tsc_types.h" +#include "tsc_acq.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Time_Driver TSC Time Driver + @{ +*/ + +/** @defgroup TSC_Time_Macros Macros + @{ +*/ + +/**@} end of group TSC_Time_Macros */ + +/** @defgroup TSC_Time_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Time_Enumerations */ + +/** @defgroup TSC_Time_Structures Structures + @{ +*/ +/**@} end of group TSC_Time_Structures */ + +/** @defgroup TSC_Time_Variables Variables + @{ +*/ +/**@} end of group TSC_Time_Variables */ + +/** @defgroup TSC_Time_Functions Functions + @{ +*/ + +TSC_STATUS_T TSC_Time_Config(void); +void TSC_Time_ProcessInterrupt(void); +TSC_STATUS_T TSC_Time_Delay_ms(TSC_tTick_ms_T delay_ms, __IO TSC_tTick_ms_T* last_tick); +TSC_STATUS_T TSC_Time_Delay_sec(TSC_tTick_sec_T delay_sec, __IO TSC_tTick_sec_T* last_tick); +void TSC_CallBack_TimerTick(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_TIME_H */ + +/**@} end of group TSC_Time_Functions */ +/**@} end of group TSC_Time_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_touchkey.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_touchkey.h new file mode 100644 index 0000000000..284c7c81a2 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_touchkey.h @@ -0,0 +1,165 @@ +/*! + * @file tsc_touchkey.h + * + * @brief This file contains external declarations of the tsc_touchkey.c file. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TOUCH_TOUCHKEY_H +#define __TOUCH_TOUCHKEY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "tsc_acq.h" +#include "tsc_time.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_TouchKey_Driver TSC TouchKey Driver + @{ +*/ + +/** @defgroup TSC_TouchKey_Macros Macros + @{ +*/ + +/**@} end of group TSC_TouchKey_Macros */ + +/** @defgroup TSC_TouchKey_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_TouchKey_Enumerations */ + +/** @defgroup TSC_TouchKey_Structures Structures + @{ +*/ + +/** + * @brief Contains all data related to TouchKey sensor. + * Variables of this structure type must be placed in RAM only. + */ +typedef struct +{ + TSC_STATEID_T StateId; /*!< Current state identifier */ + TSC_tCounter_T CounterDebounce; /*!< Counter for debounce and calibration management */ + unsigned int CounterDTO : 6; /*!< Counter for DTO management (TSC_tCounter_T) */ + unsigned int Change : 1; /*!< The State is different from the previous one (TSC_STATE_T) */ + unsigned int DxsLock : 1; /*!< The State is locked by the DxS (TSC_BOOL_T) */ +} TSC_TouchKeyData_T; + +/** + * @brief Contains all data related to TouchKey sensor. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ +#if TOUCH_USE_PROX > 0 + TSC_tThreshold_T ProxInTh; /*!< Proximity in threshold */ + TSC_tThreshold_T ProxOutTh; /*!< Proximity out threshold */ +#endif + TSC_tThreshold_T DetectInTh; /*!< Detection in threshold */ + TSC_tThreshold_T DetectOutTh; /*!< Detection out threshold */ + TSC_tThreshold_T CalibTh; /*!< Calibration threshold */ + TSC_tCounter_T CounterDebCalib; /*!< Debounce counter to enter in Calibration state */ +#if TOUCH_USE_PROX > 0 + TSC_tCounter_T CounterDebProx; /*!< Debounce counter to enter in Proximity state */ +#endif + TSC_tCounter_T CounterDebDetect; /*!< Debounce counter to enter in Detect state */ + TSC_tCounter_T CounterDebRelease; /*!< Debounce counter to enter in Release state */ + TSC_tCounter_T CounterDebError; /*!< Debounce counter to enter in Error state */ +} TSC_TouchKeyParam_T; + +/** + * @brief Contains definition of a TouchKey sensor. + * Variables of this structure type can be placed in RAM or ROM. + */ +typedef struct +{ + TSC_TouchKeyData_T* p_Data; /*!< Data (state id, counter, flag, ...) */ + TSC_TouchKeyParam_T* p_Param; /*!< Parameters (thresholds, debounce, ...) */ + TSC_Channel_Data_T* p_ChD; /*!< Channel Data (Meas, Refer, Delta, ...) */ + CONST TSC_State_T* p_SM; /*!< State Machine */ + CONST TSC_TouchKeyMethods_T* p_Methods; /*!< Methods */ +} TSC_TouchKey_T; + +/** + * @brief Contains definition of a Basic TouchKey sensor. + * Variables of this structure type can be placed in RAM or ROM. + * Basic sensor does not contain its own state machine and methods. It used + * default ones instead to gain memory space. + */ +typedef struct +{ + TSC_TouchKeyData_T* p_Data; /*!< Data (state id, counters, flag, ...) */ + TSC_TouchKeyParam_T* p_Param; /*!< Parameters (thresholds, debounce, ...) */ + TSC_Channel_Data_T* p_ChD; /*!< Channel Data (Meas, Refer, Delta, ...) */ +} TSC_TouchKeyB_T; + +/**@} end of group TSC_TouchKey_Structures */ + +/** @defgroup TSC_TouchKey_Functions Functions + @{ +*/ + +/* "Object methods" functions */ +void TSC_TouchKey_Config(void); +void TSC_TouchKey_Process(void); + +/* Utility functions */ +void TSC_TouchKey_ConfigCalibrationState(TSC_tCounter_T delay); +void TSC_TouchKey_ConfigOffState(void); +void TSC_TouchKey_ConfigBurstOnlyState(void); +TSC_STATEID_T TSC_TouchKey_ReadStateId(void); +TSC_STATEMASK_T TSC_TouchKey_ReadStateMask(void); +TSC_tNum_T TSC_TouchKey_ReadChangeFlag(void); + +/* State machine functions */ +void TSC_TouchKey_ProcessCalibrationState(void); +void TSC_TouchKey_ProcessDebCalibrationState(void); +void TSC_TouchKey_ProcessReleaseState(void); +void TSC_TouchKey_ProcessDebReleaseProxState(void); +void TSC_TouchKey_ProcessDebReleaseDetectState(void); +void TSC_TouchKey_ProcessDebReleaseTouchState(void); +void TSC_TouchKey_ProcessProxState(void); +void TSC_TouchKey_ProcessDebProxState(void); +void TSC_TouchKey_ProcessDebProxDetectState(void); +void TSC_TouchKey_ProcessDebProxTouchState(void); +void TSC_TouchKey_ProcessDetectState(void); +void TSC_TouchKey_ProcessDebDetectState(void); +void TSC_TouchKey_ProcessTouchState(void); +void TSC_TouchKey_ProcessDebErrorState(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_TOUCHKEY_H */ + +/**@} end of group TSC_TouchKey_Functions */ +/**@} end of group TSC_TouchKey_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_types.h b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_types.h new file mode 100644 index 0000000000..42b2202e96 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/inc/tsc_types.h @@ -0,0 +1,271 @@ +/*! + * @file tsc_types.h + * + * @brief This file contains all general structures definition. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __TSC_TYPES_H +#define __TSC_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Types_Driver TSC Types Driver + @{ +*/ + +/** @defgroup TSC_Types_Macros Macros + @{ +*/ + +#define TSC_ACQ_STATUS_ERROR_MASK (0x02) /*!< Associated to TSC_ACQ_STATUS_T */ + +#define TSC_OBJ_STATUS_ACQ_MASK (0x01) /*!< Associated to TSC_OBJ_STATUS_T */ +#define TSC_OBJ_STATUS_BURST_MASK (0x02) /*!< Associated to TSC_OBJ_STATUS_T */ + + +#define TSC_STATE_ERROR_BIT_MASK (0x80) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_OFF_BIT_MASK (0x40) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_DEBOUNCE_BIT_MASK (0x20) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_CALIB_BIT_MASK (0x10) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_TOUCH_BIT_MASK (0x08) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_DETECT_BIT_MASK (0x04) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_PROX_BIT_MASK (0x02) /*!< Associated to TSC_STATEMASK_T */ +#define TSC_STATE_RELEASE_BIT_MASK (0x01) /*!< Associated to TSC_STATEMASK_T */ + +/**@} end of group TSC_Types_Macros */ + +/** @defgroup TSC_Types_Enumerations Enumerations + @{ +*/ + +/** + * @brief Generic Boolean status + */ +typedef enum +{ + TSC_FALSE = 0, /*!< A False value */ + TSC_TRUE = 1 /*!< A True value */ +} TSC_BOOL_T; + +/** + * @brief Generic status returned by functions + */ +typedef enum +{ + TSC_STATUS_OK = 0, /*!< The function has been executed correctly */ + TSC_STATUS_BUSY = 1, /*!< The function is in a Busy state */ + TSC_STATUS_ERROR = 2 /*!< The function has been executed not correctly */ +} TSC_STATUS_T; + +/** + * @brief DataReady status : 1 bit + * Used by acquisition to indicate if a new measurement is ready or not. + */ +typedef enum +{ + TSC_DATA_NOT_READY = 0, /*!< No new measurement or measurement treated */ + TSC_DATA_READY = 1 /*!< A new measurement is ready */ +} TSC_DATA_T; + +/** + * @brief State change status + */ +typedef enum +{ + TSC_STATE_NOT_CHANGED = 0, /*!< The object has the same state */ + TSC_STATE_CHANGED = 1 /*!< The object has changed of state */ +} TSC_STATE_T; + + +/** + * @brief Acquisition status + */ +typedef enum +{ + TSC_ACQ_STATUS_OK = 0, /*!< The acquisition is correct */ + TSC_ACQ_STATUS_NOISE = 1, /*!< Noise detected during the acquisition */ + TSC_ACQ_STATUS_ERROR_MIN = TSC_ACQ_STATUS_ERROR_MASK, /*!< The measure is below the minimum threshold */ + TSC_ACQ_STATUS_ERROR_MAX = (TSC_ACQ_STATUS_ERROR_MASK | 0x01) /*!< The measure is above the maximum threshold */ +} TSC_ACQ_STATUS_T; + +/** + * @brief Block status + */ +typedef enum +{ + TSC_BLOCK_STATUS_DISABLED = 0, /*!< The block is disabled */ + TSC_BLOCK_STATUS_ENABLED = 1 /*!< The block is enabled */ +} TSC_BLOCK_STATUS_T; + +/** + * @brief Zone status + */ +typedef enum +{ + TSC_ZONE_STATUS_DISABLED = 0, /*!< The zone is disabled */ + TSC_ZONE_STATUS_ENABLED = 1 /*!< The zone is enabled */ +} TSC_ZONE_STATUS_T; + +/** + * @brief Object status + */ +typedef enum +{ + TSC_OBJ_STATUS_OFF = 0, /*!< No burst and no acquisition */ + TSC_OBJ_STATUS_BURST_ONLY = TSC_OBJ_STATUS_BURST_MASK, /*!< Burst only */ + TSC_OBJ_STATUS_ON = (TSC_OBJ_STATUS_BURST_MASK | TSC_OBJ_STATUS_ACQ_MASK) /*!< Burst and acquisition */ +} TSC_OBJ_STATUS_T; + +/** + * @brief Object state masks + */ +typedef enum +{ + /* Calibration states */ + TSC_STATEMASK_CALIB = TSC_STATE_CALIB_BIT_MASK, /*!< 0x10 */ + TSC_STATEMASK_DEB_CALIB = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_CALIB_BIT_MASK), /*!< 0x30 */ + /* Release states */ + TSC_STATEMASK_RELEASE = TSC_STATE_RELEASE_BIT_MASK, /*!< 0x01 */ + TSC_STATEMASK_DEB_RELEASE_PROX = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_RELEASE_BIT_MASK | TSC_STATE_PROX_BIT_MASK), /*!< 0x23 */ + TSC_STATEMASK_DEB_RELEASE_DETECT = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_RELEASE_BIT_MASK | TSC_STATE_DETECT_BIT_MASK), /*!< 0x25 */ + TSC_STATEMASK_DEB_RELEASE_TOUCH = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_RELEASE_BIT_MASK | TSC_STATE_TOUCH_BIT_MASK), /*!< 0x29 */ + /* Proximity states */ + TSC_STATEMASK_PROX = TSC_STATE_PROX_BIT_MASK, /*!< 0x02 */ + TSC_STATEMASK_DEB_PROX = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_PROX_BIT_MASK), /*!< 0x22 */ + TSC_STATEMASK_DEB_PROX_DETECT = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_PROX_BIT_MASK | TSC_STATE_DETECT_BIT_MASK), /*!< 0x26 */ + TSC_STATEMASK_DEB_PROX_TOUCH = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_PROX_BIT_MASK | TSC_STATE_TOUCH_BIT_MASK), /*!< 0x2A */ + /* Detect states */ + TSC_STATEMASK_DETECT = TSC_STATE_DETECT_BIT_MASK, /*!< 0x04 */ + TSC_STATEMASK_DEB_DETECT = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_DETECT_BIT_MASK), /*!< 0x24 */ + /* Touch state */ + TSC_STATEMASK_TOUCH = TSC_STATE_TOUCH_BIT_MASK, /*!< 0x08 */ + /* Error states */ + TSC_STATEMASK_ERROR = TSC_STATE_ERROR_BIT_MASK, /*!< 0x80 */ + TSC_STATEMASK_DEB_ERROR_CALIB = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK | TSC_STATE_CALIB_BIT_MASK), /*!< 0xB0 */ + TSC_STATEMASK_DEB_ERROR_RELEASE = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK | TSC_STATE_RELEASE_BIT_MASK), /*!< 0xA1 */ + TSC_STATEMASK_DEB_ERROR_PROX = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK | TSC_STATE_PROX_BIT_MASK), /*!< 0xA2 */ + TSC_STATEMASK_DEB_ERROR_DETECT = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK | TSC_STATE_DETECT_BIT_MASK), /*!< 0xA4 */ + TSC_STATEMASK_DEB_ERROR_TOUCH = (TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK | TSC_STATE_TOUCH_BIT_MASK), /*!< 0xA8 */ + /* OFF state */ + TSC_STATEMASK_OFF = TSC_STATE_OFF_BIT_MASK, /*!< 0x40 */ + /* Other states not associated to a state id */ + TSC_STATEMASK_ACTIVE = (TSC_STATE_PROX_BIT_MASK | TSC_STATE_DETECT_BIT_MASK | TSC_STATE_TOUCH_BIT_MASK | TSC_STATE_CALIB_BIT_MASK | TSC_STATE_DEBOUNCE_BIT_MASK), /*!< 0x3E */ + TSC_STATEMASK_UNKNOWN = 0 /*!< 0x00 */ +} TSC_STATEMASK_T; + +/** + * @brief Object state identifiers + */ +typedef enum +{ + /* Calibration states */ + TSC_STATEID_CALIB = 0, /*!< 0 - Object is in Calibration */ + TSC_STATEID_DEB_CALIB = 1, /*!< 1 - Object is in Debounce Calibration */ + /* Release states */ + TSC_STATEID_RELEASE = 2, /*!< 2 - Object is released */ + TSC_STATEID_DEB_RELEASE_PROX = 3, /*!< 3 - Object is in Debounce Release from Proximity state */ + TSC_STATEID_DEB_RELEASE_DETECT = 4, /*!< 4 - Object is in Debounce Release from Detect state */ + TSC_STATEID_DEB_RELEASE_TOUCH = 5, /*!< 5 - Object is in Debounce Release from Touch state */ + /* Proximity states */ + TSC_STATEID_PROX = 6, /*!< 6 - Object is in Proximity */ + TSC_STATEID_DEB_PROX = 7, /*!< 7 - Object is in Debounce Proximity from Release state */ + TSC_STATEID_DEB_PROX_DETECT = 8, /*!< 8 - Object is in Debounce Proximity from Detect state */ + TSC_STATEID_DEB_PROX_TOUCH = 9, /*!< 9 - Object is in Debounce Proximity from Detect state */ + /* Detect states */ + TSC_STATEID_DETECT = 10, /*!< 10 - Object is in Detect */ + TSC_STATEID_DEB_DETECT = 11, /*!< 11 - Object is in Debounce Detect */ + /* Touch state */ + TSC_STATEID_TOUCH = 12, /*!< 12 - Object is in Touch */ + /* Error states */ + TSC_STATEID_ERROR = 13, /*!< 13 - Object is in Error */ + TSC_STATEID_DEB_ERROR_CALIB = 14, /*!< 14 - Object is in Debounce Error from Calibration */ + TSC_STATEID_DEB_ERROR_RELEASE = 15, /*!< 15 - Object is in Debounce Error from Release */ + TSC_STATEID_DEB_ERROR_PROX = 16, /*!< 16 - Object is in Debounce Error from Proximity */ + TSC_STATEID_DEB_ERROR_DETECT = 17, /*!< 17 - Object is in Debounce Error from Detect */ + TSC_STATEID_DEB_ERROR_TOUCH = 18, /*!< 18 - Object is in Debounce Error from Touch */ + /* Other states */ + TSC_STATEID_OFF = 19 /*!< 19 - Object is OFF (no burst, no acquisition) */ +} TSC_STATEID_T; + +/**@} end of group TSC_Types_Enumerations */ + +/** @defgroup TSC_Types_Structures Structures + @{ +*/ + +/** + * @brief Object state + */ +typedef struct +{ + TSC_STATEMASK_T StateMask; /*!< Current state mask */ + void(* StateFunc)(void); /*!< Function executed in the state */ +} TSC_State_T; + +/** + * @brief Touchkey methods + */ +typedef struct +{ + void(* Config)(void); /*!< Used to configure the TouchKey sensor */ + void(* Process)(void); /*!< Used to execute the TouchKey sensor state machine */ +} TSC_TouchKeyMethods_T; + +/** + * @brief Linear/Rotary methods + */ +typedef struct +{ + void(* Config)(void); /*!< Used to configure the Linear/Rotary sensor */ + void(* Process)(void); /*!< Used to execute the Linear/Rotary sensor state machine */ + TSC_STATUS_T(* CalcPosition)(void); /*!< Used to calculate the Linear/Rotary sensor position */ +} TSC_LinRotMethods_T; + +/**@} end of group TSC_Types_Structures */ + +/** @defgroup TSC_Types_Variables Variables + @{ +*/ + +/**@} end of group TSC_Types_Variables */ + +/** @defgroup TSC_Types_Functions Functions + @{ +*/ + +/**@} end of group TSC_Types_Functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TSC_TYPES_H */ + +/**@} end of group TSC_Types_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc.c new file mode 100644 index 0000000000..ffb11fbc77 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc.c @@ -0,0 +1,88 @@ +/*! + * @file tsc.c + * + * @brief This file contains the Touch Driver main functions. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Driver TSC Driver + @{ +*/ + +/** @defgroup TSC_Macros Macros + @{ +*/ + +/**@} end of group TSC_Macros */ + +/** @defgroup TSC_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Enumerations */ + +/** @defgroup TSC_Variables Variables + @{ +*/ + +/* Global variables used by main() and TSC modules */ +TSC_Globals_T TSC_Globals; + +/**@} end of group TSC_Variables */ + +/** @defgroup TSC_Functions Functions + @{ +*/ + +/*! + * @brief Config the TSC GPIO interface + * + * @param block: Array holding all the blocks + * + * @retval pointer to a TSC_STATUS_T structure + */ +TSC_STATUS_T TSC_Config(CONST TSC_Block_T* block) +{ + TSC_STATUS_T retval; + + /* Read blocks array */ + TSC_Globals.Block_Array = block; + + retval = TSC_Time_Config(); + + if (retval == TSC_STATUS_OK) + { + retval = TSC_Acq_Config(); + } + + return retval; +} + +/**@} end of group TSC_Functions */ +/**@} end of group TSC_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_acq.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_acq.c new file mode 100644 index 0000000000..df66a47f85 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_acq.c @@ -0,0 +1,1483 @@ +/*! + * @file tsc_acq.c + * + * @brief This file contains all functions to manage the acquisition in general. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" +#include "tsc_acq.h" +#include "apm32f0xx_int.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Acquisition_Driver TSC Acquisition Driver + @{ +*/ + +/** @defgroup TSC_Acquisition_Macros Macros + @{ +*/ + +/**@} end of group TSC_Acquisition_Macros */ + +/** @defgroup TSC_Acquisition_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Acquisition_Enumerations */ + +/** @defgroup TSC_Acquisition_Structures Structures + @{ +*/ + +/**@} end of group TSC_Acquisition_Structures */ + +/** @defgroup TSC_Acquisition_Variables Variables + @{ +*/ + +uint32_t DelayDischarge; + +/**@} end of group TSC_Acquisition_Variables */ + +/** @defgroup TSC_Acquisition_Functions Functions + @{ +*/ + +void SoftDelay(uint32_t val); + +/*! + * @brief Output Open-Drain for Sampling Capacitor in GPIOA + * + * @param None + * + * @retval pin value + */ +uint32_t TSC_Acq_GPIOA_SAMPCAP(void) +{ + uint32_t pin = 0; +#if TOUCH_TSC_GROUP1_IO1 == SAMPCAP + pin |= GPIO_PIN_0; +#endif +#if TOUCH_TSC_GROUP1_IO2 == SAMPCAP + pin |= GPIO_PIN_1; +#endif +#if TOUCH_TSC_GROUP1_IO3 == SAMPCAP + pin |= GPIO_PIN_2; +#endif +#if TOUCH_TSC_GROUP1_IO4 == SAMPCAP + pin |= GPIO_PIN_3; +#endif +#if TOUCH_TSC_GROUP2_IO1 == SAMPCAP + pin |= GPIO_PIN_4; +#endif +#if TOUCH_TSC_GROUP2_IO2 == SAMPCAP + pin |= GPIO_PIN_5; +#endif +#if TOUCH_TSC_GROUP2_IO3 == SAMPCAP + pin |= GPIO_PIN_6; +#endif +#if TOUCH_TSC_GROUP2_IO4 == SAMPCAP + pin |= GPIO_PIN_7; +#endif +#if TOUCH_TSC_GROUP4_IO1 == SAMPCAP + pin |= GPIO_PIN_9; +#endif +#if TOUCH_TSC_GROUP4_IO2 == SAMPCAP + pin |= GPIO_PIN_10; +#endif +#if TOUCH_TSC_GROUP4_IO3 == SAMPCAP + pin |= GPIO_PIN_11; +#endif +#if TOUCH_TSC_GROUP4_IO4 == SAMPCAP + pin |= GPIO_PIN_12; +#endif + return pin; +} + +/*! + * @brief Output Open-Drain for Sampling Capacitor in GPIOB + * + * @param None + * + * @retval pin value + */ +uint32_t TSC_Acq_GPIOB_SAMPCAP(void) +{ + uint32_t pin = 0; +#if TOUCH_TSC_GROUP3_IO2 == SAMPCAP + pin |= GPIO_PIN_0; +#endif +#if TOUCH_TSC_GROUP3_IO3 == SAMPCAP + pin |= GPIO_PIN_1; +#endif +#if TOUCH_TSC_GROUP3_IO4 == SAMPCAP + pin |= GPIO_PIN_2; +#endif +#if TOUCH_TSC_GROUP5_IO1 == SAMPCAP + pin |= GPIO_PIN_3; +#endif +#if TOUCH_TSC_GROUP5_IO2 == SAMPCAP + pin |= GPIO_PIN_4; +#endif +#if TOUCH_TSC_GROUP5_IO3 == SAMPCAP + pin |= GPIO_PIN_6; +#endif +#if TOUCH_TSC_GROUP5_IO4 == SAMPCAP + pin |= GPIO_PIN_7; +#endif +#if TOUCH_TSC_GROUP6_IO1 == SAMPCAP + pin |= GPIO_PIN_11; +#endif +#if TOUCH_TSC_GROUP6_IO2 == SAMPCAP + pin |= GPIO_PIN_12; +#endif +#if TOUCH_TSC_GROUP6_IO3 == SAMPCAP + pin |= GPIO_PIN_13; +#endif +#if TOUCH_TSC_GROUP6_IO4 == SAMPCAP + pin |= GPIO_PIN_14; +#endif + return pin; +} + +/*! + * @brief Output Open-Drain for Sampling Capacitor in GPIOC + * + * @param None + * + * @retval pin value + */ +uint32_t TSC_Acq_GPIOC_SAMPCAP(void) +{ + uint32_t pin = 0; +#if TOUCH_TSC_GROUP3_IO1 == SAMPCAP + pin |= GPIO_PIN_5; +#endif + return pin; +} + +/*! + * @brief Output Open-Drain for Sampling Capacitor in GPIOD + * + * @param None + * + * @retval pin value + */ +#if (TSC_GROUP8_ENABLED > 0) +uint32_t TSC_Acq_GPIOD_SAMPCAP(void) +{ + uint32_t pin = 0; +#if TOUCH_TSC_GROUP8_IO1 == SAMPCAP + pin |= GPIO_PIN_12; +#endif +#if TOUCH_TSC_GROUP8_IO2 == SAMPCAP + pin |= GPIO_PIN_13; +#endif +#if TOUCH_TSC_GROUP8_IO3 == SAMPCAP + pin |= GPIO_PIN_14; +#endif +#if TOUCH_TSC_GROUP8_IO4 == SAMPCAP + pin |= GPIO_PIN_15; +#endif + return pin; +} +#endif + +/*! + * @brief Output Open-Drain for Sampling Capacitor in GPIOE + * + * @param None + * + * @retval pin value + */ +#if (TSC_GROUP7_ENABLED > 0) +uint32_t TSC_Acq_GPIOE_SAMPCAP(void) +{ + pin = 0; +#if TOUCH_TSC_GROUP7_IO1 == SAMPCAP + pin |= GPIO_PIN_2; +#endif +#if TOUCH_TSC_GROUP7_IO2 == SAMPCAP + pin |= GPIO_PIN_3; +#endif +#if TOUCH_TSC_GROUP7_IO3 == SAMPCAP + pin |= GPIO_PIN_4; +#endif +#if TOUCH_TSC_GROUP7_IO4 == SAMPCAP + pin |= GPIO_PIN_5; +#endif + return pin; +} +#endif + +/*! + * @brief Output Push-Pull for Channel and Shield GPIOA + * + * @param None + * + * @retval pin value + */ +uint32_t TSC_Acq_GPIOA_CHANNEL_SHIELD(void) +{ + uint32_t pin = 0; +#if (TOUCH_TSC_GROUP1_IO1 == CHANNEL) || (TOUCH_TSC_GROUP1_IO1 == SHIELD) + pin |= GPIO_PIN_0; +#endif +#if (TOUCH_TSC_GROUP1_IO2 == CHANNEL) || (TOUCH_TSC_GROUP1_IO2 == SHIELD) + pin |= GPIO_PIN_1; +#endif +#if (TOUCH_TSC_GROUP1_IO3 == CHANNEL) || (TOUCH_TSC_GROUP1_IO3 == SHIELD) + pin |= GPIO_PIN_2; +#endif +#if (TOUCH_TSC_GROUP1_IO4 == CHANNEL) || (TOUCH_TSC_GROUP1_IO4 == SHIELD) + pin |= GPIO_PIN_3; +#endif +#if (TOUCH_TSC_GROUP2_IO1 == CHANNEL) || (TOUCH_TSC_GROUP2_IO1 == SHIELD) + pin |= GPIO_PIN_4; +#endif +#if (TOUCH_TSC_GROUP2_IO2 == CHANNEL) || (TOUCH_TSC_GROUP2_IO2 == SHIELD) + pin |= GPIO_PIN_5; +#endif +#if (TOUCH_TSC_GROUP2_IO3 == CHANNEL) || (TOUCH_TSC_GROUP2_IO3 == SHIELD) + pin |= GPIO_PIN_6; +#endif +#if (TOUCH_TSC_GROUP2_IO4 == CHANNEL) || (TOUCH_TSC_GROUP2_IO4 == SHIELD) + pin |= GPIO_PIN_7; +#endif +#if (TOUCH_TSC_GROUP4_IO1 == CHANNEL) || (TOUCH_TSC_GROUP4_IO1 == SHIELD) + pin |= GPIO_PIN_9; +#endif +#if (TOUCH_TSC_GROUP4_IO2 == CHANNEL) || (TOUCH_TSC_GROUP4_IO2 == SHIELD) + pin |= GPIO_PIN_10; +#endif +#if (TOUCH_TSC_GROUP4_IO3 == CHANNEL) || (TOUCH_TSC_GROUP4_IO3 == SHIELD) + pin |= GPIO_PIN_11; +#endif +#if (TOUCH_TSC_GROUP4_IO4 == CHANNEL) || (TOUCH_TSC_GROUP4_IO4 == SHIELD) + pin |= GPIO_PIN_12; +#endif + return pin; +} + +/*! + * @brief Output Push-Pull for Channel and Shield GPIOB + * + * @param None + * + * @retval pin value + */ +uint32_t TSC_Acq_GPIOB_CHANNEL_SHIELD(void) +{ + uint32_t pin = 0; +#if (TOUCH_TSC_GROUP3_IO2 == CHANNEL) || (TOUCH_TSC_GROUP3_IO2 == SHIELD) + pin |= GPIO_PIN_0; +#endif +#if (TOUCH_TSC_GROUP3_IO3 == CHANNEL) || (TOUCH_TSC_GROUP3_IO3 == SHIELD) + pin |= GPIO_PIN_1; +#endif +#if (TOUCH_TSC_GROUP3_IO4 == CHANNEL) || (TOUCH_TSC_GROUP3_IO4 == SHIELD) + pin |= GPIO_PIN_2; +#endif +#if (TOUCH_TSC_GROUP5_IO1 == CHANNEL) || (TOUCH_TSC_GROUP5_IO1 == SHIELD) + pin |= GPIO_PIN_3; +#endif +#if (TOUCH_TSC_GROUP5_IO2 == CHANNEL) || (TOUCH_TSC_GROUP5_IO2 == SHIELD) + pin |= GPIO_PIN_4; +#endif +#if (TOUCH_TSC_GROUP5_IO3 == CHANNEL) || (TOUCH_TSC_GROUP5_IO3 == SHIELD) + pin |= GPIO_PIN_6; +#endif +#if (TOUCH_TSC_GROUP5_IO4 == CHANNEL) || (TOUCH_TSC_GROUP5_IO4 == SHIELD) + pin |= GPIO_PIN_7; +#endif +#if (TOUCH_TSC_GROUP6_IO1 == CHANNEL) || (TOUCH_TSC_GROUP6_IO1 == SHIELD) + pin |= GPIO_PIN_11; +#endif +#if (TOUCH_TSC_GROUP6_IO2 == CHANNEL) || (TOUCH_TSC_GROUP6_IO2 == SHIELD) + pin |= GPIO_PIN_12; +#endif +#if (TOUCH_TSC_GROUP6_IO3 == CHANNEL) || (TOUCH_TSC_GROUP6_IO3 == SHIELD) + pin |= GPIO_PIN_13; +#endif +#if (TOUCH_TSC_GROUP6_IO4 == CHANNEL) || (TOUCH_TSC_GROUP6_IO4 == SHIELD) + pin |= GPIO_PIN_14; +#endif + return pin; +} + +/*! + * @brief Output Push-Pull for Channel and Shield GPIOC + * + * @param None + * + * @retval pin value + */ +uint32_t TSC_Acq_GPIOC_CHANNEL_SHIELD(void) +{ + uint32_t pin = 0; +#if (TOUCH_TSC_GROUP3_IO1 == CHANNEL) || (TOUCH_TSC_GROUP3_IO1 == SHIELD) + pin |= GPIO_PIN_5; +#endif + return pin; +} + +/*! + * @brief Output Push-Pull for Channel and Shield GPIOD + * + * @param None + * + * @retval pin value + */ +#if (TSC_GROUP8_ENABLED > 0) +uint32_t TSC_Acq_GPIOD_CHANNEL_SHIELD(void) +{ + uint32_t pin = 0; +#if (TOUCH_TSC_GROUP8_IO1 == CHANNEL) || (TOUCH_TSC_GROUP8_IO1 == SHIELD) + pin |= GPIO_PIN_12; +#endif +#if (TOUCH_TSC_GROUP8_IO2 == CHANNEL) || (TOUCH_TSC_GROUP8_IO2 == SHIELD) + pin |= GPIO_PIN_13; +#endif +#if (TOUCH_TSC_GROUP8_IO3 == CHANNEL) || (TOUCH_TSC_GROUP8_IO3 == SHIELD) + pin |= GPIO_PIN_14; +#endif +#if (TOUCH_TSC_GROUP8_IO4 == CHANNEL) || (TOUCH_TSC_GROUP8_IO4 == SHIELD) + pin |= GPIO_PIN_15; +#endif + return pin; +} +#endif + +/*! + * @brief Output Push-Pull for Channel and Shield GPIOE + * + * @param None + * + * @retval pin value + */ +#if (TSC_GROUP7_ENABLED > 0) +uint32_t TSC_Acq_GPIOE_CHANNEL_SHIELD(void) +{ + uint32_t pin = 0; +#if (TOUCH_TSC_GROUP7_IO1 == CHANNEL) || (TOUCH_TSC_GROUP7_IO1 == SHIELD) + pin |= GPIO_PIN_2; +#endif +#if (TOUCH_TSC_GROUP7_IO2 == CHANNEL) || (TOUCH_TSC_GROUP7_IO2 == SHIELD) + pin |= GPIO_PIN_3; +#endif +#if (TOUCH_TSC_GROUP7_IO3 == CHANNEL) || (TOUCH_TSC_GROUP7_IO3 == SHIELD) + pin |= GPIO_PIN_4; +#endif +#if (TOUCH_TSC_GROUP7_IO4 == CHANNEL) || (TOUCH_TSC_GROUP7_IO4 == SHIELD) + pin |= GPIO_PIN_5; +#endif + return pin; +#endif + + /*! + * @brief Alternate-Function AF3 for GPIOA in ALFL register + * + * @param None + * + * @retval ALFL value + */ + uint32_t TSC_Acq_GPIOA_AF3_L(void) + { + uint32_t val_ALFL = 0; +#if TOUCH_TSC_GROUP1_IO1 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (0 * 4)); +#endif +#if TOUCH_TSC_GROUP1_IO2 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (1 * 4)); +#endif +#if TOUCH_TSC_GROUP1_IO3 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (2 * 4)); +#endif +#if TOUCH_TSC_GROUP1_IO4 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (3 * 4)); +#endif +#if TOUCH_TSC_GROUP2_IO1 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (4 * 4)); +#endif +#if TOUCH_TSC_GROUP2_IO2 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (5 * 4)); +#endif +#if TOUCH_TSC_GROUP2_IO3 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (6 * 4)); +#endif +#if TOUCH_TSC_GROUP2_IO4 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (7 * 4)); +#endif + return val_ALFL; + } + + /*! + * @brief Alternate-Function AF3 for GPIOA in ALFH register + * + * @param None + * + * @retval ALFH value + */ + uint32_t TSC_Acq_GPIOA_AF3_H(void) + { + uint32_t val_ALFH = 0; +#if TOUCH_TSC_GROUP4_IO1 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (1 * 4)); +#endif +#if TOUCH_TSC_GROUP4_IO2 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (2 * 4)); +#endif +#if TOUCH_TSC_GROUP4_IO3 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (3 * 4)); +#endif +#if TOUCH_TSC_GROUP4_IO4 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (4 * 4)); +#endif + return val_ALFH; + } + + /*! + * @brief Alternate-Function AF3 for GPIOB in ALFL register + * + * @param None + * + * @retval ALFL value + */ + uint32_t TSC_Acq_GPIOB_AF3_L(void) + { + uint32_t val_ALFL = 0; +#if TOUCH_TSC_GROUP3_IO2 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (0 * 4)); +#endif +#if TOUCH_TSC_GROUP3_IO3 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (1 * 4)); +#endif +#if TOUCH_TSC_GROUP3_IO4 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (2 * 4)); +#endif +#if TOUCH_TSC_GROUP5_IO1 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (3 * 4)); +#endif +#if TOUCH_TSC_GROUP5_IO2 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (4 * 4)); +#endif +#if TOUCH_TSC_GROUP5_IO3 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (6 * 4)); +#endif +#if TOUCH_TSC_GROUP5_IO4 != NU + val_ALFL |= (uint32_t)((uint32_t)3 << (7 * 4)); +#endif + return val_ALFL; + } + + /*! + * @brief Alternate-Function AF3 for GPIOB in ALFH register + * + * @param None + * + * @retval ALFH value + */ + uint32_t TSC_Acq_GPIOB_AF3_H(void) + { + uint32_t val_ALFH = 0; +#if TOUCH_TSC_GROUP6_IO1 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (3 * 4)); +#endif +#if TOUCH_TSC_GROUP6_IO2 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (4 * 4)); +#endif +#if TOUCH_TSC_GROUP6_IO3 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (5 * 4)); +#endif +#if TOUCH_TSC_GROUP6_IO4 != NU + val_ALFH |= (uint32_t)((uint32_t)3 << (6 * 4)); +#endif + return val_ALFH; + } + + /*! + * @brief Alternate-Function AF1 for GPIOD in ALFH register + * + * @param None + * + * @retval ALFH value + */ +#if (TSC_GROUP8_ENABLED > 0) + uint32_t TSC_Acq_GPIOD_AF1_H(void) + { + uint32_t val_ALFH = 0; +#if TOUCH_TSC_GROUP8_IO1 != NU + val_ALFH |= (uint32_t)((uint32_t)1 << (4 * 4)); +#endif +#if TOUCH_TSC_GROUP8_IO2 != NU + val_ALFH |= (uint32_t)((uint32_t)1 << (5 * 4)); +#endif +#if TOUCH_TSC_GROUP8_IO3 != NU + val_ALFH |= (uint32_t)((uint32_t)1 << (6 * 4)); +#endif +#if TOUCH_TSC_GROUP8_IO4 != NU + val_ALFH |= (uint32_t)((uint32_t)1 << (7 * 4)); +#endif + return val_ALFH; + } +#endif + + /*! + * @brief Alternate-Function AF1 for GPIOE in ALFL register + * + * @param None + * + * @retval ALFL value + */ +#if (TSC_GROUP7_ENABLED > 0) + uint32_t TSC_Acq_GPIOE_AF1_L(void) + { + uint32_t val_ALFL = 0; +#if TOUCH_TSC_GROUP7_IO1 != NU + val_ALFL |= (uint32_t)((uint32_t)1 << (2 * 4)); +#endif +#if TOUCH_TSC_GROUP7_IO2 != NU + val_ALFL |= (uint32_t)((uint32_t)1 << (3 * 4)); +#endif +#if TOUCH_TSC_GROUP7_IO3 != NU + val_ALFL |= (uint32_t)((uint32_t)1 << (4 * 4)); +#endif +#if TOUCH_TSC_GROUP7_IO4 != NU + val_ALFL |= (uint32_t)((uint32_t)1 << (5 * 4)); +#endif + return val_ALFL; + } +#endif + + /*! + * @brief Disable Schmitt trigger hysteresis GPIO in IOHCTRL register + * + * @param None + * + * @retval IOHCTRL value + */ + uint32_t TSC_Acq_Schmitt_Trigger_Hysteresis(void) + { + uint32_t val_IOHCTRL = 0xFFFFFFFF; +#if TOUCH_TSC_GROUP1_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 0); +#endif +#if TOUCH_TSC_GROUP1_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 1); +#endif +#if TOUCH_TSC_GROUP1_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 2); +#endif +#if TOUCH_TSC_GROUP1_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 3); +#endif +#if TOUCH_TSC_GROUP2_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 4); +#endif +#if TOUCH_TSC_GROUP2_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 5); +#endif +#if TOUCH_TSC_GROUP2_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 6); +#endif +#if TOUCH_TSC_GROUP2_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 7); +#endif +#if TOUCH_TSC_GROUP3_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 8); +#endif +#if TOUCH_TSC_GROUP3_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 9); +#endif +#if TOUCH_TSC_GROUP3_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 10); +#endif +#if TOUCH_TSC_GROUP3_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 11); +#endif +#if TOUCH_TSC_GROUP4_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 12); +#endif +#if TOUCH_TSC_GROUP4_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 13); +#endif +#if TOUCH_TSC_GROUP4_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 14); +#endif +#if TOUCH_TSC_GROUP4_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 15); +#endif +#if TOUCH_TSC_GROUP5_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 16); +#endif +#if TOUCH_TSC_GROUP5_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 17); +#endif +#if TOUCH_TSC_GROUP5_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 18); +#endif +#if TOUCH_TSC_GROUP5_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 19); +#endif +#if TOUCH_TSC_GROUP6_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 20); +#endif +#if TOUCH_TSC_GROUP6_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 21); +#endif +#if TOUCH_TSC_GROUP6_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 22); +#endif +#if TOUCH_TSC_GROUP6_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 23); +#endif +#if (TSC_GROUP7_ENABLED > 0) +#if TOUCH_TSC_GROUP7_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 24); +#endif +#if TOUCH_TSC_GROUP7_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 25); +#endif +#if TOUCH_TSC_GROUP7_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 26); +#endif +#if TOUCH_TSC_GROUP7_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 27); +#endif +#endif /*!< TSC_GROUP7_ENABLED */ +#if (TSC_GROUP8_ENABLED > 0) +#if TOUCH_TSC_GROUP8_IO1 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 28); +#endif +#if TOUCH_TSC_GROUP8_IO2 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 29); +#endif +#if TOUCH_TSC_GROUP8_IO3 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 30); +#endif +#if TOUCH_TSC_GROUP8_IO4 != NU + val_IOHCTRL &= (uint32_t)~((uint32_t)1 << 31); +#endif +#endif /*!< TSC_GROUP8_ENABLED */ + return val_IOHCTRL; + } + + /*! + * @brief Sampling Capacitor GPIO in IOSMPCTRL register + * + * @param None + * + * @retval IOSMPCTRL value + */ + uint32_t TSC_Acq_Sampling_Capacitor(void) + { + uint32_t val_IOSMPCTRL = 0; +#if TOUCH_TSC_GROUP1_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 0); +#endif +#if TOUCH_TSC_GROUP1_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 1); +#endif +#if TOUCH_TSC_GROUP1_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 2); +#endif +#if TOUCH_TSC_GROUP1_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 3); +#endif +#if TOUCH_TSC_GROUP2_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 4); +#endif +#if TOUCH_TSC_GROUP2_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 5); +#endif +#if TOUCH_TSC_GROUP2_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 6); +#endif +#if TOUCH_TSC_GROUP2_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 7); +#endif +#if TOUCH_TSC_GROUP3_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 8); +#endif +#if TOUCH_TSC_GROUP3_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 9); +#endif +#if TOUCH_TSC_GROUP3_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 10); +#endif +#if TOUCH_TSC_GROUP3_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 11); +#endif +#if TOUCH_TSC_GROUP4_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 12); +#endif +#if TOUCH_TSC_GROUP4_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 13); +#endif +#if TOUCH_TSC_GROUP4_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 14); +#endif +#if TOUCH_TSC_GROUP4_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 15); +#endif +#if TOUCH_TSC_GROUP5_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 16); +#endif +#if TOUCH_TSC_GROUP5_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 17); +#endif +#if TOUCH_TSC_GROUP5_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 18); +#endif +#if TOUCH_TSC_GROUP5_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 19); +#endif +#if TOUCH_TSC_GROUP6_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 20); +#endif +#if TOUCH_TSC_GROUP6_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 21); +#endif +#if TOUCH_TSC_GROUP6_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 22); +#endif +#if TOUCH_TSC_GROUP6_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 23); +#endif +#if (TSC_GROUP7_ENABLED > 0) +#if TOUCH_TSC_GROUP7_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 24); +#endif +#if TOUCH_TSC_GROUP7_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 25); +#endif +#if TOUCH_TSC_GROUP7_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 26); +#endif +#if TOUCH_TSC_GROUP7_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 27); +#endif +#endif /*!< TSC_GROUP7_ENABLED */ +#if (TSC_GROUP8_ENABLED > 0) +#if TOUCH_TSC_GROUP8_IO1 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 28); +#endif +#if TOUCH_TSC_GROUP8_IO2 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 29); +#endif +#if TOUCH_TSC_GROUP8_IO3 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 30); +#endif +#if TOUCH_TSC_GROUP8_IO4 == SAMPCAP + val_IOSMPCTRL |= (uint32_t)((uint32_t)1 << 31); +#endif +#endif /*!< TSC_GROUP8_ENABLED */ + return val_IOSMPCTRL; + } + + /*! + * @brief Config the Touch Sensing GPIO + * + * @param None + * + * @retval None + * + * @note NU: Not Used IO + * CHANNEL: Channel IO + * SHIELD: Channel IO but not acquired + * SAMPCAP: Sampling Capacitor IO + */ + void TSC_Acq_ConfigGPIO(void) + { + GPIO_Config_T gpioConfig; + + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA | RCM_AHB_PERIPH_GPIOB | RCM_AHB_PERIPH_GPIOC); +#if (TSC_GROUP7_ENABLED > 0) || (TSC_GROUP8_ENABLED > 0) + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOD | RCM_AHB_PERIPH_GPIOE); +#endif + + /* Alternate function Output Open-Drain for Sampling Capacitor IOs */ + gpioConfig.mode = GPIO_MODE_AF; + gpioConfig.outtype = GPIO_OUT_TYPE_OD; + gpioConfig.speed = GPIO_SPEED_2MHz; + gpioConfig.pupd = GPIO_PUPD_NO; + + /* GPIOA */ + gpioConfig.pin = TSC_Acq_GPIOA_SAMPCAP(); + GPIO_Config(GPIOA, &gpioConfig); + + /* GPIOB */ + gpioConfig.pin = TSC_Acq_GPIOB_SAMPCAP(); + GPIO_Config(GPIOB, &gpioConfig); + + /* GPIOC */ + gpioConfig.pin = TSC_Acq_GPIOC_SAMPCAP(); + GPIO_Config(GPIOC, &gpioConfig); + + /* GPIOD */ +#if (TSC_GROUP8_ENABLED > 0) + gpioConfig.pin = TSC_Acq_GPIOD_SAMPCAP(); + GPIO_Config(GPIOD, &gpioConfig); +#endif + + /* GPIOE */ +#if (TSC_GROUP7_ENABLED > 0) + gpioConfig.pin = TSC_Acq_GPIOE_SAMPCAP(); + GPIO_Config(GPIOE, &gpioConfig); +#endif + + /* Alternate function Output Push-Pull for Channel and Shield IOs */ + gpioConfig.outtype = GPIO_OUT_TYPE_PP; + + /* GPIOA */ + gpioConfig.pin = TSC_Acq_GPIOA_CHANNEL_SHIELD(); + GPIO_Config(GPIOA, &gpioConfig); + + /* GPIOB */ + gpioConfig.pin = TSC_Acq_GPIOB_CHANNEL_SHIELD(); + GPIO_Config(GPIOB, &gpioConfig); + + /* GPIOC */ + gpioConfig.pin = TSC_Acq_GPIOC_CHANNEL_SHIELD(); + GPIO_Config(GPIOC, &gpioConfig); + + /* GPIOD */ +#if (TSC_GROUP8_ENABLED > 0) + gpioConfig.pin = TSC_Acq_GPIOD_CHANNEL_SHIELD(); + GPIO_Config(GPIOD, &gpioConfig); +#endif + + /* GPIOE */ +#if (TSC_GROUP7_ENABLED > 0) + gpioConfig.pin = TSC_Acq_GPIOE_CHANNEL_SHIELD(); + GPIO_Config(GPIOE, &gpioConfig); +#endif + + /* Config Alternate-Function AF3 for GPIOA and GPIOB */ + /* GPIOA */ + GPIOA->ALFL |= TSC_Acq_GPIOA_AF3_L(); + GPIOA->ALFH |= TSC_Acq_GPIOA_AF3_H(); + + /* GPIOB */ + GPIOB->ALFL |= TSC_Acq_GPIOB_AF3_L(); + GPIOB->ALFH |= TSC_Acq_GPIOB_AF3_H(); + + /* Config Alternate-Function AF1 for GPIOD and GPIOE */ + /* GPIOD */ +#if (TSC_GROUP8_ENABLED > 0) + GPIOD->ALFH |= TSC_Acq_GPIOD_AF1_H(); +#endif + + /* GPIOE */ +#if (TSC_GROUP7_ENABLED > 0) + GPIOE->ALFL |= TSC_Acq_GPIOE_AF1_L(); +#endif + + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_TSC); + + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ + TSC->IOHCTRL &= TSC_Acq_Schmitt_Trigger_Hysteresis(); + + /* Config Sampling Capacitor IOs */ + TSC->IOSMPCTRL |= TSC_Acq_Sampling_Capacitor(); + } + + /*! + * @brief Configurate the acquisition module + * + * @param None + * + * @retval pointer to a TSC_STATUS_T structure + */ + TSC_STATUS_T TSC_Acq_Config(void) + { +#if TOUCH_TSC_GPIO_CONFIG > 0 + TSC_Acq_ConfigGPIO(); +#endif + + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_TSC); + + /* TSC enabled */ + TSC->CTRL = 0x01; + + /* Config CTPHSEL */ +#if TOUCH_TSC_CTPHSEL > 0 + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_CTPHSEL << 28) & 0xF0000000; +#endif + + /* Config CTPLSEL */ +#if TOUCH_TSC_CTPLSEL > 0 + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_CTPLSEL << 24) & 0x0F000000; +#endif + + /* Config Spread Spectrum */ +#if TOUCH_TSC_USE_SSEN > 0 + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_USE_SSEN << 16) & 0x00010000; + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_SSERRVSEL << 17) & 0x00FE0000; + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_SSCDFSEL << 15) & 0x00008000; +#endif + + /* Config Prescaler */ +#if TOUCH_TSC_PGCDFSEL > 0 + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_PGCDFSEL << 12) & 0x00007000; +#endif + + /* Config Max Count */ +#if TOUCH_TSC_MCNTVSEL > 0 + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_MCNTVSEL << 5) & 0x000000E0; +#endif + + /* Config IO default in Output PP Low to discharge all capacitors */ + TSC->CTRL &= (uint32_t)(~(1 << 4)); + + /* Config Synchronization Mode */ +#if TOUCH_TSC_AMCFG > 0 + /* Config Synchronization Pin in Alternate-Function mode */ + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOB); + +#if TOUCH_TSC_SYNC_PIN == 0 /*!< PB8 */ + GPIOB->MODE &= 0xFFFCFFFF; + GPIOB->MODE |= 0x00020000; + GPIOB->ALFH |= 0x00000003; +#else /*!< PB10 */ + GPIOB->MODE &= 0xFFCFFFFF; + GPIOB->MODE |= 0x00200000; + GPIOB->ALFH |= 0x00000300; +#endif + + /* Config Synchronization Polarity */ + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_SYNC_POL << 3) & 0x00000008; + + /* Config acquisition mode */ + TSC->CTRL |= (uint32_t)((uint32_t)TOUCH_TSC_AMCFG << 2) & 0x00000004; +#endif + +#if TOUCH_USE_ACQ_INTERRUPT > 0 + /* Config both EOAIEN and MCEIEN interrupts */ + TSC->INTEN |= 0x03; + /* Configure NVIC */ + NVIC_EnableIRQRequest(TSC_IRQn, 0) +#endif + + /* Configure the delay that will be used to discharge the capacitors */ + DelayDischarge = (uint32_t)((TOUCH_DELAY_DISCHARGE_ALL * (uint32_t)(SystemCoreClock / 1000000)) / 48); + return TSC_STATUS_OK; + } + + /*! + * @brief Configures a Block + * + * @param idxBlock: Index of the Block + * + * @retval pointer to a TSC_STATUS_T structure + */ + TSC_STATUS_T TSC_Acq_ConfigBlock(TSC_tIndex_T idxBlock) + { + uint32_t idxChannel; + uint32_t objStatus; + uint32_t Gx, IOy; + CONST TSC_Block_T* block = &(TSC_Globals.Block_Array[idxBlock]); + CONST TSC_Channel_Src_T* pchSrc = block->p_chSrc; + CONST TSC_Channel_Dest_T* pchDest = block->p_chDest; + + /* Mark the current block processed */ + TSC_Globals.For_Block = idxBlock; + /* Enable the Gx_IOy used as channels (channels + shield) */ + TSC->IOCHCTRL = block->msk_IOCHCTRL_channels; + /* Enable acquisition on selected Groups */ + TSC->IOGCSTS = block->msk_IOGCSTS_groups; + + for (idxChannel = 0; idxChannel < block->NumChannel; idxChannel++) + { + /* Read Object status flag */ + objStatus = block->p_chData[pchDest->IdxDest].Flag.ObjStatus; + + if (objStatus != TSC_OBJ_STATUS_ON) + { + /* Read the Channel Group mask */ + Gx = pchSrc->msk_IOGCSTS_group; + /* Stop acquisition of the Group */ + TSC->IOGCSTS &= (uint32_t)~Gx; + + if (objStatus == TSC_OBJ_STATUS_OFF) + { + /* Read the Channel IO mask */ + IOy = pchSrc->msk_IOCHCTRL_channel; + /* Stop Burst of the Channel */ + TSC->IOCHCTRL &= (uint32_t)~IOy; + } + } + /* Next channel */ + pchSrc++; + pchDest++; + } + return TSC_STATUS_OK; + } + + /*! + * @brief Start acquisition on a previously configured block + * + * @param None + * + * @retval None + */ + void TSC_Acq_StartPerConfigBlock(void) + { + /* Clear both EOAIC and MCEIC flag */ + TSC->INTFCLR |= 0x03; + + /* Wait capacitors discharge */ + SoftDelay(DelayDischarge); + +#if TOUCH_TSC_IODEF > 0 + /* Config IO default in Input Floating */ + TSC->CTRL |= (1 << 4); +#endif + + /* Start acquisition */ + TSC->CTRL |= 0x02; + } + + /*! + * @brief Wait end of acquisition + * + * @param None + * + * @retval None + */ + TSC_STATUS_T TSC_Acq_WaitBlockEOA(void) + { + TSC_STATUS_T retval = TSC_STATUS_BUSY; + + /* Check EOAFLG flag */ + if (TSC->INTSTS & 0x01) + { +#if TOUCH_TSC_IODEF > 0 + /* Config IO default in Output PP Low to discharge all capacitors */ + TSC->CTRL &= (uint32_t)(~(1 << 4)); +#endif + + /* Check MCEFLG flag */ + if (TSC->INTSTS & 0x02) + { + retval = TSC_STATUS_ERROR; + } + else + { + retval = TSC_STATUS_OK; + } + } + return retval; + } + + /*! + * @brief Return the current measure + * + * @param index: Index of the measure source + * + * @retval Measure + */ + TSC_tMeas_T TSC_Acq_ReadMeasurVal(TSC_tIndex_T index) + { + return ((TSC_tMeas_T)(TSC->IOGxCNT[index].IOGCNT)); + } + + /*! + * @brief Compute the Delta value + * + * @param refVal: Reference value + * + * @param measVal: Measurement value + * + * @retval Delta value + */ + TSC_tDelta_T TSC_Acq_ComputeDelta(TSC_tRefer_T refVal, TSC_tMeas_T measVal) + { + return ((TSC_tDelta_T)(refVal - measVal)); + } + + /*! + * @brief Compute the Measurement value + * + * @param refVal: Reference value + * + * @param deltaVal: delta Delta value + * + * @retval Measurement value + */ + TSC_tMeas_T TSC_Acq_ComputeMeas(TSC_tRefer_T refVal, TSC_tDelta_T deltaVal) + { + return ((TSC_tMeas_T)(refVal - deltaVal)); + } + + /*! + * @brief Check noise (not used) + * + * @param None + * + * @retval pointer to a TSC_STATUS_T structure + */ + TSC_ACQ_STATUS_T TSC_Acq_CheckNoise(void) + { + return TSC_ACQ_STATUS_OK; + } + + /*! + * @brief Check if a filter must be used on the current channel (not used) + * + * @param pCh: Pointer on the channel data information + * + * @retval Result TRUE if a filter can be applied + */ + TSC_BOOL_T TSC_Acq_UseFilter(TSC_Channel_Data_T * pCh) + { + return TSC_TRUE; + } + + /*! + * @brief Test if the Reference is incorrect (not used) + * + * @param pCh: Pointer on the channel data information + * + * @retval Result TRUE if the Reference is out of range + */ + TSC_BOOL_T TSC_Acq_TestReferenceRange(TSC_Channel_Data_T * pCh) + { + return TSC_FALSE; + } + + /*! + * @brief Test if the measure has crossed the reference target (not used) + * + * @param pCh: Pointer on the channel data information + * + * @param newMeas: Measure of the last acquisition on this channel + * + * @retval Result TRUE if the Reference is valid + */ + TSC_BOOL_T TSC_Acq_TestFirstReference(TSC_Channel_Data_T * pCh, TSC_tMeas_T newMeas) + { + return TSC_TRUE; + } + + /*! + * @brief Software delay (private routine) + * + * @param val: Wait delay + * + * @retval None + * + * @note Measurements done with HCLK=48MHz and Keil/MDK-ARM compiler + * val = 500: ~ 53 + * val = 1000: ~106 + * val = 2000: ~210 + */ + void SoftDelay(uint32_t val) + { + uint32_t i; + for (i = val; i > 0; i--) + {} + } + + /*! + * @brief Read all channels measurement of a Block, calculate delta + * + * @param idxBlock: Index of the Block to access + * + * @param mfilter: Pointer to the measure filter + * + * @param dfilter: Pointer to the delta filter + * + * @retval Status + */ + TSC_STATUS_T TSC_Acq_ReadBlockResult(TSC_tIndex_T idxBlock, TSC_pMeasFilter_T mfilter, TSC_pDeltaFilter_T dfilter) + { + TSC_STATUS_T retval = TSC_STATUS_OK; + TSC_tIndex_T idxChannel; + TSC_tIndexDest_T idxDest; + TSC_tMeas_T oldMeas, newMeas; + TSC_tDelta_T newDelta; + CONST TSC_Block_T* block = &(TSC_Globals.Block_Array[idxBlock]); + CONST TSC_Channel_Dest_T* pchDest = block->p_chDest; + CONST TSC_Channel_Src_T* pchSrc = block->p_chSrc; + + /* For all channels in the block copy the measure + calculate delta and store them */ + for (idxChannel = 0; idxChannel < block->NumChannel; idxChannel++) + { + idxDest = pchDest->IdxDest; + + if (block->p_chData[idxDest].Flag.ObjStatus == TSC_OBJ_STATUS_ON) + { + block->p_chData[idxDest].Flag.DataReady = TSC_DATA_READY; + newMeas = TSC_Acq_ReadMeasurVal(pchSrc->IdxSrc); + +#if TOUCH_USE_MEAS > 0 + oldMeas = block->p_chData[idxDest].Meas; +#else + oldMeas = newMeas; +#endif + +#if TOUCH_USE_MEAS > 0 + block->p_chData[idxDest].Meas = newMeas; +#endif + + /* Check acquisition value min/max */ + if (newMeas > TSC_Params.AcqMax) + { + block->p_chData[idxDest].Flag.AcqStatus = TSC_ACQ_STATUS_ERROR_MAX; + block->p_chData[idxDest].Delta = 0; + retval = TSC_STATUS_ERROR; + } + else + { + if (newMeas < TSC_Params.AcqMin) + { + block->p_chData[idxDest].Flag.AcqStatus = TSC_ACQ_STATUS_ERROR_MIN; + block->p_chData[idxDest].Delta = 0; + retval = TSC_STATUS_ERROR; + } + else /*!< The measure is OK */ + { + if (TSC_Acq_UseFilter(&block->p_chData[idxDest]) == 0) + { + block->p_chData[idxDest].Delta = TSC_Acq_ComputeDelta(block->p_chData[idxDest].Refer, newMeas); + block->p_chData[idxDest].Flag.AcqStatus = TSC_Acq_CheckNoise(); + } + else + { + /* Measure filter*/ + if (mfilter) + { + newMeas = mfilter(oldMeas, newMeas); + /* Store the measure */ +#if TOUCH_USE_MEAS > 0 + block->p_chData[idxDest].Meas = newMeas; +#endif + } + + newDelta = TSC_Acq_ComputeDelta(block->p_chData[idxDest].Refer, newMeas); + block->p_chData[idxDest].Flag.AcqStatus = TSC_Acq_CheckNoise(); + + /* Delta filter */ + if (dfilter == 0) + { + block->p_chData[idxDest].Delta = newDelta; + } + else + { + block->p_chData[idxDest].Delta = dfilter(newDelta); + } + } + } + } + } + pchDest++; + pchSrc++; + } + return retval; + } + + /*! + * @brief Calibrate a Block + * + * @param idxBlock: Index of the Block + * + * @retval Status + */ + TSC_STATUS_T TSC_Acq_CalibrateBlock(TSC_tIndex_T idxBlock) + { + TSC_STATUS_T retval; + TSC_STATUS_T acqStatus; + TSC_tIndex_T idxChannel; + TSC_tIndexDest_T idxDest; + TSC_tMeas_T newMeas; + static TSC_tIndex_T goCalibration = 0; + static TSC_tNum_T doneCalibration = 0; + static TSC_tNum_T CalibDiv; + CONST TSC_Block_T* block; + CONST TSC_Channel_Dest_T* pchDest; + CONST TSC_Channel_Src_T* pchSrc; + + block = &(TSC_Globals.Block_Array[idxBlock]); + + if (goCalibration)/*!< Calibration is on-going */ + { + acqStatus = TSC_Acq_WaitBlockEOA(); + + switch (acqStatus) + { + case TSC_STATUS_OK: + pchDest = block->p_chDest; + pchSrc = block->p_chSrc; + + for (idxChannel = 0; idxChannel < block->NumChannel; idxChannel++) + { + idxDest = pchDest->IdxDest; + newMeas = TSC_Acq_ReadMeasurVal(pchSrc->IdxSrc); + + if ((newMeas < TSC_Params.AcqMin) || (newMeas > TSC_Params.AcqMax)) + { + TSC_acq_ClearBlockData(idxBlock); + goCalibration = 0; + return TSC_STATUS_ERROR; + } + else + { + block->p_chData[idxDest].Refer += newMeas; + } + pchDest++; + pchSrc++; + } + + doneCalibration--; + if (doneCalibration) + { + TSC_Acq_StartPerConfigBlock(); + retval = TSC_STATUS_BUSY; + } + else + { + pchDest = block->p_chDest; + + for (idxChannel = 0; idxChannel < block->NumChannel; idxChannel++) + { + idxDest = pchDest->IdxDest; + /* Divide the Reference by the number of samples */ + block->p_chData[idxDest].Refer >>= CalibDiv; + pchDest++; + } + goCalibration = 0; + retval = TSC_STATUS_OK; + } + break; + case TSC_STATUS_ERROR: + TSC_acq_ClearBlockData(idxBlock); + goCalibration = 0; + retval = TSC_STATUS_ERROR; + break; + default: + retval = TSC_STATUS_BUSY; + break; + } + } + else /*!< Calibration is done */ + { + if (TSC_Params.NumCalibSample == 4) + { + CalibDiv = 2; + } + else if (TSC_Params.NumCalibSample == 16) + { + CalibDiv = 4; + } + else + { + TSC_Params.NumCalibSample = 8; + CalibDiv = 3; + } + + TSC_acq_ClearBlockData(idxBlock); + + if (TSC_Acq_ConfigBlock(idxBlock)) + { + TSC_acq_ClearBlockData(idxBlock); + goCalibration = 0; + retval = TSC_STATUS_ERROR; + } + else + { + TSC_Acq_StartPerConfigBlock(); + goCalibration = 1; + doneCalibration = TSC_Params.NumCalibSample; + retval = TSC_STATUS_BUSY; + } + } + return retval; + } + + /*! + * @brief Clear Reference and delta on all channels of a Block + * + * @param idxBlock: Index of the Block + * + * @retval None + */ + void TSC_acq_ClearBlockData(TSC_tIndex_T idxBlock) + { + TSC_tIndex_T idxChannel; + TSC_tIndexDest_T idx_Dest; + CONST TSC_Block_T* block = &(TSC_Globals.Block_Array[idxBlock]); + CONST TSC_Channel_Dest_T* pchDest = block->p_chDest; + + for (idxChannel = 0; idxChannel < block->NumChannel; idxChannel++) + { + idx_Dest = pchDest->IdxDest; + block->p_chData[idx_Dest].Refer = 0; + block->p_chData[idx_Dest].Delta = 0; + pchDest++; + } + } + +#if TOUCH_USE_ZONE > 0 + + /*! + * @brief Configures a Zone + * + * @param zone: Zone to configure + * + * @param idxBlock: Index of the Block to access + * + * @retval Status + */ + TSC_STATUS_T TSC_Acq_ConfigZone(CONST TSC_Zone_T * zone, TSC_tIndex_T idxBlock) + { + TSC_STATUS_T retval; + TSC_Globals.For_Zone = zone; + + do + { + retval = TSC_Acq_ConfigBlock(zone->indexBlock[idxBlock]); + TSC_Globals.For_Block = zone->indexBlock[idxBlock]; + idxBlock++; + } + while ((idxBlock < zone->numBlock) && (retval == TSC_STATUS_ERROR)); + + TSC_Globals.Index_For_Zone = idxBlock; + +#if TOUCH_PXS_LOW_POWER_MODE > 0 + if (idxBlock < zone->numBlock) + { + resetPXSLowPower(); + } +#endif + + return (retval); + } +#endif + + /**@} end of group TSC_Acquisition_Functions */ + /**@} end of group TSC_Acquisition_Driver */ + /**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_dxs.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_dxs.c new file mode 100644 index 0000000000..0668f59ddc --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_dxs.c @@ -0,0 +1,202 @@ +/*! + * @file tsc_dxs.c + * + * @brief This file contains all functions to manage the + * Detection Exclusion System (Dxs) algorithm + + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" +#include "tsc_dxs.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_DXS_Driver TSC DXS Driver + @{ +*/ + +/** @defgroup TSC_DXS_Macros Macros + @{ +*/ + +/**@} end of group TSC_DXS_Macros */ + +/** @defgroup TSC_DXS_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_DXS_Enumerations */ + +/** @defgroup TSC_DXS_Structures Structures + @{ +*/ + +/**@} end of group TSC_DXS_Structures */ + +/** @defgroup TSC_DXS_Variables Variables + @{ +*/ + +/**@} end of group TSC_DXS_Variables */ + +/** @defgroup TSC_DXS_Functions Functions + @{ +*/ + +/*! + * @brief Detection Exclusion System on the first object in detect state + * + * @param objgrp: Pointer to the objects group to process + * + * @retval None + */ +void TSC_Dxs_FirstObj(CONST TSC_ObjectGroup_T* objgrp) +{ +#if TOUCH_USE_DXS > 0 + + TSC_tIndex_T idxObj; + TSC_tIndex_T objLock = 0; + CONST TSC_Object_T* pObj; + CONST TSC_Object_T* pObjadd = 0; + + /* Exit if no object are in DETECT state */ + if ((objgrp->StateMask & TSC_STATE_DETECT_BIT_MASK) == 0) + { + return; + } + + pObj = objgrp->p_Obj; + + /* Process all objects */ + for (idxObj = 0; idxObj < objgrp->NbObjects; idxObj++) + { + TSC_Obj_ConfigGlobalObj(pObj); + + switch (FOR_OBJ_TYPE) + { +#if TOUCH_TOTAL_KEYS > 0 + case TSC_OBJ_TOUCHKEY: + case TSC_OBJ_TOUCHKEYB: + if (FOR_KEY_STATEID == TSC_STATEID_DETECT) + { + if (FOR_KEY_DXSLOCK == TSC_FALSE) + { + FOR_KEY_STATEID = TSC_STATEID_TOUCH; + FOR_KEY_CHANGE = TSC_STATE_CHANGED; + if ((!pObjadd) && (!objLock)) + { + pObjadd = pObj; + } + } + else + { + if (objLock) + { + FOR_KEY_STATEID = TSC_STATEID_TOUCH; + FOR_KEY_CHANGE = TSC_STATE_CHANGED; + } + else + { + objLock = 1; + pObjadd = 0; + } + } + } + break; +#endif + +#if TOUCH_TOTAL_LNRTS > 0 + case TSC_OBJ_LINEAR: + case TSC_OBJ_LINEARB: + case TSC_OBJ_ROTARY: + case TSC_OBJ_ROTARYB: + if (FOR_LINROT_STATEID == TSC_STATEID_DETECT) + { + if (FOR_LINROT_DXSLOCK == TSC_FALSE) + { + FOR_LINROT_STATEID = TSC_STATEID_TOUCH; + FOR_LINROT_CHANGE = TSC_STATE_CHANGED; + if ((!pObjadd) && (!objLock)) + { + pObjadd = pObj; + } + } + else + { + if (objLock) + { + FOR_LINROT_STATEID = TSC_STATEID_TOUCH; + FOR_LINROT_CHANGE = TSC_STATE_CHANGED; + } + else + { + objLock = 1; + pObjadd = 0; + } + } + } + break; +#endif + default: + break; + } + pObj++; + } + + /* Change state from TOUCH to DETECT + DxsLock flag on the candidate object only */ + if (pObjadd) + { + TSC_Obj_ConfigGlobalObj(pObjadd); + + switch (FOR_OBJ_TYPE) + { +#if TOUCH_TOTAL_KEYS > 0 + case TSC_OBJ_TOUCHKEY: + case TSC_OBJ_TOUCHKEYB: + FOR_KEY_STATEID = TSC_STATEID_DETECT; + FOR_KEY_CHANGE = TSC_STATE_CHANGED; + FOR_KEY_DXSLOCK = TSC_TRUE; + break; +#endif + +#if TOUCH_TOTAL_LNRTS > 0 + case TSC_OBJ_LINEAR: + case TSC_OBJ_LINEARB: + case TSC_OBJ_ROTARY: + case TSC_OBJ_ROTARYB: + FOR_LINROT_STATEID = TSC_STATEID_DETECT; + FOR_LINROT_CHANGE = TSC_STATE_CHANGED; + FOR_LINROT_DXSLOCK = TSC_TRUE; + break; +#endif + default: + break; + } + } +#endif /*!< TOUCH_USE_DXS > 0 */ +} + +/**@} end of group TSC_DXS_Functions */ +/**@} end of group TSC_DXS_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_ecs.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_ecs.c new file mode 100644 index 0000000000..9927bb8b32 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_ecs.c @@ -0,0 +1,329 @@ +/*! + * @file tsc_ecs.c + * + * @brief This file contains all functions to manage the ECS + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" +#include "tsc_ecs.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_ECS_Driver TSC ECS Driver + @{ +*/ + +/** @defgroup TSC_ECS_Macros Macros + @{ +*/ + +/**@} end of group TSC_ECS_Macros */ + +/** @defgroup TSC_ECS_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_ECS_Enumerations */ + +/** @defgroup TSC_ECS_Structures Structures + @{ +*/ + +/**@} end of group TSC_ECS_Structures */ + +/** @defgroup TSC_ECS_Variables Variables + @{ +*/ + +/**@} end of group TSC_ECS_Variables */ + +/** @defgroup TSC_ECS_Functions Functions + @{ +*/ + +/*! + * @brief Calculate the K coefficient + * + * @param kDiffer: K coefficient when objects have different delta variation + * + * @param kSame: K coefficient when objects have the same delta variation + * + * @retval K coefficient (differ or same) + */ +TSC_tKCoeff_T TSC_Ecs_CalculateK(TSC_ObjectGroup_T* objgrp, TSC_tKCoeff_T kDiffer, TSC_tKCoeff_T kSame) +{ + TSC_tIndex_T idxObj; + TSC_tIndex_T idxChannel; + TSC_tDelta_T value = 0; + TSC_tDelta_T Cmd = 1; + TSC_tDelta_T Dir = 0; + TSC_tNum_T numChannel = 0; + TSC_tKCoeff_T retval = kDiffer; + TSC_Channel_Data_T* p_Ch = 0; + CONST TSC_Object_T* pObj; + + pObj = objgrp->p_Obj; + + /* Process all objects */ + for (idxObj = 0; idxObj < objgrp->NbObjects; idxObj++) + { + TSC_Obj_ConfigGlobalObj(pObj); + + switch (FOR_OBJ_TYPE) + { +#if TOUCH_TOTAL_KEYS > 0 + case TSC_OBJ_TOUCHKEY: + case TSC_OBJ_TOUCHKEYB: + if (FOR_KEY_STATEID != TSC_STATEID_RELEASE) + { + pObj++; + continue; + } + numChannel = 1; + p_Ch = TSC_Globals.For_Key->p_ChD; + break; +#endif + +#if TOUCH_TOTAL_LNRTS > 0 + case TSC_OBJ_LINEAR: + case TSC_OBJ_LINEARB: + case TSC_OBJ_ROTARY: + case TSC_OBJ_ROTARYB: + if (FOR_LINROT_STATEID != TSC_STATEID_RELEASE) + { + pObj++; + continue; + } + numChannel = FOR_LINROT_NB_CHANNELS; + p_Ch = TSC_Globals.For_LinRot->p_ChD; + break; +#endif + default: + break; + } + + /* Check all channels of current object */ + for (idxChannel = 0; idxChannel < numChannel; idxChannel++) + { + value = p_Ch->Delta; + + if (value) + { + if (value >= 0) + { + if (Dir > 0) + { + Dir = 1; + } + else + { + Cmd = 0; + } + } + else + { + if (Dir < 0) + { + Dir = -1; + } + else + { + Cmd = 0; + } + } + } + else + { + Cmd = 0; + } + p_Ch++; + } + pObj++; + } + + if (Cmd) + { + retval = kSame; + } + return retval; +} + +/*! + * @brief Calculate the new Reference on a group of objects + * + * @param objgrp: Pointer to the objects group to process + * + * @param kCoeff: K coefficient to apply + * + * @retval None + */ +void TSC_Ecs_ProcessK(TSC_ObjectGroup_T* objgrp, TSC_tKCoeff_T kCoeff) +{ + TSC_tIndex_T idxObj; + TSC_tIndex_T idxChannel; + CONST TSC_Object_T* pObj; + TSC_tKCoeff_T kCoeffComp; + uint32_t meas, refer; + TSC_tNum_T numChannel = 0; + TSC_Channel_Data_T* p_Ch = 0; + void(*pFunc_SetStateCalibration)(TSC_tCounter_T delay) = 0; + + pObj = objgrp->p_Obj; + + /* Calculate the K coefficient complement */ + kCoeffComp = (0xFF ^ kCoeff) + 1; + + /* Process all objects */ + for (idxObj = 0; idxObj < objgrp->NbObjects; idxObj++) + { + TSC_Obj_ConfigGlobalObj(pObj); + + switch (FOR_OBJ_TYPE) + { +#if TOUCH_TOTAL_KEYS > 0 + case TSC_OBJ_TOUCHKEY: + case TSC_OBJ_TOUCHKEYB: + if (FOR_KEY_STATEID != TSC_STATEID_RELEASE) + { + pObj++; + continue; + } + numChannel = 1; + p_Ch = TSC_Globals.For_Key->p_ChD; + pFunc_SetStateCalibration = &TSC_TouchKey_ConfigCalibrationState; + break; +#endif + +#if TOUCH_TOTAL_LNRTS > 0 + case TSC_OBJ_LINEAR: + case TSC_OBJ_LINEARB: + case TSC_OBJ_ROTARY: + case TSC_OBJ_ROTARYB: + if (FOR_LINROT_STATEID != TSC_STATEID_RELEASE) + { + pObj++; + continue; + } + numChannel = FOR_LINROT_NB_CHANNELS; + p_Ch = TSC_Globals.For_LinRot->p_ChD; + pFunc_SetStateCalibration = &TSC_Linrot_ConfigCalibrationState; + break; +#endif + default: + break; + } + + /* Calculate the new reference + rest for all channels */ + for (idxChannel = 0; idxChannel < numChannel; idxChannel++) + { + meas = TSC_Acq_ComputeMeas(p_Ch->Refer, p_Ch->Delta); + meas <<= 8; + + refer = (uint32_t)(p_Ch->Refer); + refer <<= 8; + refer += p_Ch->RefRest; + refer *= kCoeffComp; + refer += (kCoeff * meas); + + p_Ch->RefRest = (TSC_tRefRest_T)((refer >> 8) & 0xFF); + p_Ch->Refer = (TSC_tRefer_T)(refer >> 16); + + /* Go in Calibration state in the Reference is out of Range */ + if (TSC_Acq_TestReferenceRange(p_Ch) == TSC_TRUE) + { + pFunc_SetStateCalibration(0); + } + p_Ch++; + } + pObj++; + } +} + +/*! + * @brief ECS algorithm on a group of objects + * The ECS is only performed if at least an object is in Release state and + * if no objects are in active states (Prox, Detect or Touch) + * An optional delay is added after the ECS condition (all sensors in Release state) is reached. + * + * @param objgrp: Pointer to the objects group to process + * + * @retval Status + */ +TSC_STATUS_T TSC_Ecs_Process(TSC_ObjectGroup_T* objgrp) +{ + TSC_tKCoeff_T myKcoeff; + TSC_STATUS_T retval; + + if ((objgrp->StateMask & TSC_STATE_RELEASE_BIT_MASK) && !(objgrp->StateMask & TSC_STATEMASK_ACTIVE)) + { +#if TOUCH_ECS_DELAY > 0 + if (!objgrp->wait) + { + disableInterrupts(); + objgrp->time = TSC_Globals.Tick_ms; + enableInterrupts(); + objgrp->wait = 1; + objgrp->execution = 0; + } +#else + objgrp->execution = 1; +#endif + } + else + { +#if TOUCH_ECS_DELAY > 0 + objgrp->wait = 0; +#endif + objgrp->execution = 0; + } + +#if TOUCH_ECS_DELAY > 0 + if (objgrp->wait && (!objgrp->execution)) + { + if (TSC_Time_Delay_ms(TOUCH_ECS_DELAY, &objgrp->time) == TSC_STATUS_OK) + { + objgrp->execution = 1; + } + } +#endif + + if (objgrp->execution == 0) + { + retval = TSC_STATUS_BUSY; + } + else + { + /* Calculate the K coefficient */ + myKcoeff = TSC_Ecs_CalculateK(objgrp, TOUCH_ECS_K_DIFFER, TOUCH_ECS_K_SAME); + /* Process the objects */ + TSC_Ecs_ProcessK(objgrp, myKcoeff); + retval = TSC_STATUS_OK; + } + return retval; +} + +/**@} end of group TSC_ECS_Functions */ +/**@} end of group TSC_ECS_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_filter.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_filter.c new file mode 100644 index 0000000000..1bfa0bc371 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_filter.c @@ -0,0 +1,109 @@ +/*! + * @file tsc_filter.c + * + * @brief This file contains all functions to manage the signal or delta filters. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc_filter.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Filter_Driver TSC Filter Driver + @{ +*/ + +/** @defgroup TSC_Filter_Macros Macros + @{ +*/ + +/**@} end of group TSC_Filter_Macros */ + +/** @defgroup TSC_Filter_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Filter_Enumerations */ + +/** @defgroup TSC_Filter_Structures Structures + @{ +*/ + +/**@} end of group TSC_Filter_Structures */ + +/** @defgroup TSC_Filter_Variables Variables + @{ +*/ + +/**@} end of group TSC_Filter_Variables */ + +/** @defgroup TSC_Filter_Functions Functions + @{ +*/ + +/*! + * @brief Example of measure value filter + * + * @param preMeasn: Previous measure value + * + * @param curMeasn: Current measure value + * + * @retval Filtered measure + */ +TSC_tMeas_T TSC_Filt_MeasFilter(TSC_tMeas_T preMeasn, TSC_tMeas_T curMeasn) +{ + TSC_tMeas_T value; + + value = (TSC_tMeas_T)(curMeasn << ACQ_FILTER_RANGE); + + if (preMeasn) + { + if (value <= preMeasn) + { + value = preMeasn - ((ACQ_FILTER_COEFF * (preMeasn - value)) >> 8); + } + else + { + value = preMeasn + ((ACQ_FILTER_COEFF * (value - preMeasn)) >> 8); + } + } + return (value); +} + +/*! + * @brief Example of delta value filter + * + * @param delta: Delta value to modify + * + * @retval Filtered delta + */ +TSC_tDelta_T TSC_Filt_DeltaFilter(TSC_tDelta_T delta) +{ + return (delta); +} + +/**@} end of group TSC_Filter_Functions */ +/**@} end of group TSC_Filter_Driver */ +/**@} end of group TSC_Driver_Library */ + diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_linrot.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_linrot.c new file mode 100644 index 0000000000..ce0ab7918f --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_linrot.c @@ -0,0 +1,2073 @@ +/*! + * @file tsc_linrot.c + * + * @brief This file contains all functions to manage Linear and Rotary sensors. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" +#include "tsc_linrot.h" + +#if TOUCH_TOTAL_LNRTS > 0 + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Linrot_Driver TSC Linrot Driver + @{ +*/ + +/** @defgroup TSC_Linrot_Macros Macros + @{ +*/ + +#define FOR_OBJ_TYPE TSC_Globals.For_Obj->Type + +#define FOR_STATEID TSC_Globals.For_LinRot->p_Data->StateId +#define FOR_RAW_POSITION TSC_Globals.For_LinRot->p_Data->RawPosition +#define FOR_POSITION TSC_Globals.For_LinRot->p_Data->Position +#define FOR_CHANGE TSC_Globals.For_LinRot->p_Data->Change +#define FOR_POSCHANGE TSC_Globals.For_LinRot->p_Data->PosChange +#define FOR_COUNTER_DEB TSC_Globals.For_LinRot->p_Data->CounterDebounce +#define FOR_COUNTER_DIR TSC_Globals.For_LinRot->p_Data->CounterDirection +#define FOR_COUNTER_DTO TSC_Globals.For_LinRot->p_Data->CounterDTO +#define FOR_DXSLOCK TSC_Globals.For_LinRot->p_Data->DxsLock +#define FOR_DIRECTION TSC_Globals.For_LinRot->p_Data->Direction + +#define FOR_PROXIN_TH TSC_Globals.For_LinRot->p_Param->ProxInTh +#define FOR_PROXOUT_TH TSC_Globals.For_LinRot->p_Param->ProxOutTh +#define FOR_DETECTIN_TH TSC_Globals.For_LinRot->p_Param->DetectInTh +#define FOR_DETECTOUT_TH TSC_Globals.For_LinRot->p_Param->DetectOutTh +#define FOR_CALIB_TH TSC_Globals.For_LinRot->p_Param->CalibTh + +#define FOR_RESOLUTION TSC_Globals.For_LinRot->p_Param->Resolution +#define FOR_DIR_CHG_POS TSC_Globals.For_LinRot->p_Param->DirChangePos + +#define FOR_COUNTER_DEB_CALIB TSC_Globals.For_LinRot->p_Param->CounterDebCalib +#define FOR_COUNTER_DEB_PROX TSC_Globals.For_LinRot->p_Param->CounterDebProx +#define FOR_COUNTER_DEB_DETECT TSC_Globals.For_LinRot->p_Param->CounterDebDetect +#define FOR_COUNTER_DEB_RELEASE TSC_Globals.For_LinRot->p_Param->CounterDebRelease +#define FOR_COUNTER_DEB_ERROR TSC_Globals.For_LinRot->p_Param->CounterDebError +#define FOR_COUNTER_DEB_DIRECTION TSC_Globals.For_LinRot->p_Param->CounterDebDirection + +#define FOR_NB_CHANNELS TSC_Globals.For_LinRot->NumChannel +#define FOR_SCT_COMP TSC_Globals.For_LinRot->SctComp +#define FOR_POS_CORR TSC_Globals.For_LinRot->PosCorr + +#if TOUCH_DTO > 0 + #define DTO_READ_TIME {TSC_Linrot_ReadTimeForDTO();} +#else + #define DTO_READ_TIME +#endif + +#define DIRECTION_CHANGE_MAX_DISPLACEMENT (255) +#define DIRECTION_CHANGE_TOTAL_STEPS (256) +#define RESOLUTION_CALCULATION (8) + +/**@} end of group TSC_Linrot_Macros */ + +/** @defgroup TSC_Linrot_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Linrot_Enumerations */ + +/** @defgroup TSC_Linrot_Structures Structures + @{ +*/ + +/**@} end of group TSC_Linrot_Structures */ + +/** @defgroup TSC_Linrot_Variables Variables + @{ +*/ + +static TSC_tNum_T CalibDiv; + +/** + * @brief 3 CHANNELS - CH1 CH2 CH3 + * LINEAR - MONO - 0/255 at extremities + */ +#if TOUCH_USE_3CH_LIN_M1 > 0 +CONST TSC_tPosition_T TSC_POSOFF_3CH_LIN_M1[3][3] = +{ + { 0, -96, 0 }, + { 32, 0, -160 }, + { 0, 96, 0 } +}; +#endif + +/** + * @brief 3 CHANNELS - CH1 CH2 CH3 + * LINEAR - MONO + */ +#if TOUCH_USE_3CH_LIN_M2 > 0 +CONST TSC_tPosition_T TSC_POSOFF_3CH_LIN_M2[3][3] = +{ + { 0, -192, 0 }, + { 64, 0, -320 }, + { 0, 192, 0 } +}; +#endif + +/** + * @brief 3 CHANNELS - CH1 CH2 CH3 CH1 + * LINEAR - HALF-ENDED + */ +#if TOUCH_USE_3CH_LIN_H > 0 +CONST TSC_tPosition_T TSC_POSOFF_3CH_LIN_H[3][3] = +{ + { 0, -96, 160 }, + { 32, 0, -160 }, + { -224, 96, 0 } +}; +#endif + +/** + * @brief 3 CHANNELS - CH1 CH2 CH3 + * ROTARY - MONO + */ +#if TOUCH_USE_3CH_ROT_M > 0 +CONST TSC_tPosition_T TSC_POSOFF_3CH_ROT_M[3][3] = +{ + { 0, -64, 107 }, + { 21, 0, -107 }, + { -149, 64, 0 } +}; +#endif + +/** + * @brief 4 CHANNELS - CH1 CH2 CH3 CH4 + * LINEAR - MONO - 0/255 at extremities + */ +#if TOUCH_USE_4CH_LIN_M1 > 0 +CONST TSC_tPosition_T TSC_POSOFF_4CH_LIN_M1[4][4] = +{ + { 0, -64, 0, 0 }, + { 21, 0, -107, 0 }, + { 0, 64, 0, -149 }, + { 0, 0, 107, 0 } +}; +#endif + +/** + * @brief 4 CHANNELS - CH1 CH2 CH3 CH4 + * LINEAR - MONO + */ +#if TOUCH_USE_4CH_LIN_M2 > 0 +CONST TSC_tPosition_T TSC_POSOFF_4CH_LIN_M2[4][4] = +{ + { 0, -96, 0, 0 }, + { 32, 0, -160, 0 }, + { 0, 96, 0, -224 }, + { 0, 0, 160, 0 } +}; +#endif + +/** + * @brief 4 CHANNELS - CH1 CH2 CH3 CH4 CH1 + * LINEAR - MONO - HALF-ENDED + */ +#if TOUCH_USE_4CH_LIN_H > 0 +CONST TSC_tPosition_T TSC_POSOFF_4CH_LIN_H[4][4] = +{ + { 0, -64, 0, 149 }, + { 21, 0, -107, 0 }, + { 0, 64, 0, -149 }, + { -192, 0, 107, 0 } +}; +#endif + +/** + * @brief 4 CHANNELS - CH1 CH2 CH3 CH4 + * ROTARY - MONO + */ +#if TOUCH_USE_4CH_ROT_M > 0 +CONST TSC_tPosition_T TSC_POSOFF_4CH_ROT_M[4][4] = +{ + { 0, -48, 0, 112 }, + { 16, 0, -80, 0 }, + { 0, 48, 0, -112 }, + { -144, 0, 80, 0 } +}; +#endif + +/** + * @brief 5 CHANNELS - CH1 CH2 CH3 CH4 CH5 + * LINEAR - MONO - 0/255 at extremities + */ +#if TOUCH_USE_5CH_LIN_M1 > 0 +CONST TSC_tPosition_T TSC_POSOFF_5CH_LIN_M1[5][5] = +{ + { 0, -48, 0, 0, 0 }, + { 16, 0, -80, 0, 0 }, + { 0, 48, 0, -112, 0 }, + { 0, 0, 80, 0, -144 }, + { 0, 0, 0, 112, 0 } +}; +#endif + +/** + * @brief 5 CHANNELS - CH1 CH2 CH3 CH4 CH5 + * LINEAR - MONO + */ +#if TOUCH_USE_5CH_LIN_M2 > 0 +CONST TSC_tPosition_T TSC_POSOFF_5CH_LIN_M2[5][5] = +{ + { 0, -64, 0, 0, 0 }, + { 21, 0, -107, 0, 0 }, + { 0, 64, 0, -149, 0 }, + { 0, 0, 107, 0, -192 }, + { 0, 0, 0, 149, 0 } +}; +#endif + +/** + * @brief 5 CHANNELS - CH1 CH2 CH3 CH4 CH5 CH1 + * LINEAR - HALF-ENDED + */ +#if TOUCH_USE_5CH_LIN_H > 0 +CONST TSC_tPosition_T TSC_POSOFF_5CH_LIN_H[5][5] = +{ + { 0, -48, 0, 0, 144 }, + { 16, 0, -80, 0, 0 }, + { 0, 48, 0, -112, 0 }, + { 0, 0, 80, 0, -144 }, + { -176, 0, 0, 112, 0 } +}; +#endif + +/** + * @brief 5 CHANNELS - CH1 CH2 CH3 CH4 CH5 + * ROTARY - MONO + */ +#if TOUCH_USE_5CH_ROT_M > 0 +CONST TSC_tPosition_T TSC_POSOFF_5CH_ROT_M[5][5] = +{ + { 0, -38, 0, 0, 115 }, + { 13, 0, -64, 0, 0 }, + { 0, 38, 0, -90, 0 }, + { 0, 0, 64, 0, -115 }, + {-141, 0, 0, 90, 0 } +}; +#endif + +/** + * @brief 5 CHANNELS - CH1 CH2 CH3 CH4 CH5 CH1 CH3 CH5 CH2 CH4 + * ROTARY - DUAL + */ +#if TOUCH_USE_5CH_ROT_D > 0 +CONST TSC_tPosition_T TSC_POSOFF_5CH_ROT_D[5][5] = +{ + { 0, -19, -83, 122, 58 }, + { 6, 0, -32, -122, 96 }, + { 70, 19, 0, -45, -96 }, + {-134, 109, 32, 0, -58 }, + { -70, -109, 83, 45, 0 } +}; +#endif + +/** + * @brief 6 CHANNELS - CH1 CH2 CH3 CH4 CH5 CH6 + * LINEAR - MONO - 0/255 at extremities + */ +#if TOUCH_USE_6CH_LIN_M1 > 0 +CONST TSC_tPosition_T TSC_POSOFF_6CH_LIN_M1[6][6] = +{ + { 0, -38, 0, 0, 0, 0 }, + { 13, 0, -64, 0, 0, 0 }, + { 0, 38, 0, -90, 0, 0 }, + { 0, 0, 64, 0, -115, 0 }, + { 0, 0, 0, 90, 0, -141 }, + { 0, 0, 0, 0, 115, 0 } +}; +#endif + +/** + * @brief 6 CHANNELS - CH1 CH2 CH3 CH4 CH5 CH6 + * LINEAR - MONO + */ +#if TOUCH_USE_6CH_LIN_M2 > 0 +CONST TSC_tPosition_T TSC_POSOFF_6CH_LIN_M2[6][6] = +{ + { 0, -48, 0, 0, 0, 0 }, + { 16, 0, -80, 0, 0, 0 }, + { 0, 48, 0, -112, 0, 0 }, + { 0, 0, 80, 0, -144, 0 }, + { 0, 0, 0, 112, 0, -176 }, + { 0, 0, 0, 0, 144, 0 } +}; +#endif + +/** + * @brief 6 CHANNELS - CH1 CH2 CH3 CH4 CH5 CH6 CH1 + * LINEAR - HALF-ENDED + */ +#if TOUCH_USE_6CH_LIN_H > 0 +CONST TSC_tPosition_T TSC_POSOFF_6CH_LIN_H[6][6] = +{ + { 0, -38, 0, 0, 0, 141 }, + { 13, 0, -64, 0, 0, 0 }, + { 0, 38, 0, -90, 0, 0 }, + { 0, 0, 64, 0, -115, 0 }, + { 0, 0, 0, 90, 0, -141 }, + {-166, 0, 0, 0, 115, 0 } +}; +#endif + +/** + * @brief 6 CHANNELS - CH1 CH2 CH3 CH4 CH5 CH6 + * ROTARY - MONO + */ +#if TOUCH_USE_6CH_ROT_M > 0 +CONST TSC_tPosition_T TSC_POSOFF_6CH_ROT_M[6][6] = +{ + { 0, -32, 0, 0, 0, 117 }, + { 11, 0, -53, 0, 0, 0 }, + { 0, 32, 0, -75, 0, 0 }, + { 0, 0, 53, 0, -96, 0 }, + { 0, 0, 0, 75, 0, -117 }, + {-139, 0, 0, 0, 96, 0 } +}; +#endif + +/**@} end of group TSC_Linrot_Variables */ + +/** @defgroup TSC_Linrot_Functions Functions + @{ +*/ + +/** @defgroup "Object_methods" Functions + @{ +*/ + +/*! + * @brief The parameters with default values from configuration file + * + * @param None + * + * @retval None + */ +void TSC_Linrot_Config(void) +{ + /* Thresholds */ +#if TOUCH_USE_PROX > 0 + FOR_PROXIN_TH = TOUCH_LINROT_PROX_IN_TH; + FOR_PROXOUT_TH = TOUCH_LINROT_PROX_OUT_TH; +#endif + FOR_DETECTIN_TH = TOUCH_LINROT_DETECT_IN_TH; + FOR_DETECTOUT_TH = TOUCH_LINROT_DETECT_OUT_TH; + FOR_CALIB_TH = TOUCH_LINROT_CALIB_TH; + + /* Debounce counters */ + FOR_COUNTER_DEB_CALIB = TOUCH_DEBOUNCE_CALIB; +#if TOUCH_USE_PROX > 0 + FOR_COUNTER_DEB_PROX = TOUCH_DEBOUNCE_PROX; +#endif + FOR_COUNTER_DEB_DETECT = TOUCH_DEBOUNCE_DETECT; + FOR_COUNTER_DEB_RELEASE = TOUCH_DEBOUNCE_RELEASE; + FOR_COUNTER_DEB_ERROR = TOUCH_DEBOUNCE_ERROR; + + /* Other parameters for linear/rotary only */ + FOR_RESOLUTION = TOUCH_LINROT_RESOLUTION; + FOR_DIR_CHG_POS = TOUCH_LINROT_DIR_CHG_POS; + FOR_COUNTER_DEB_DIRECTION = TOUCH_LINROT_DIR_CHG_DEB; + + /* Config state */ + TSC_Linrot_ConfigCalibrationState(TOUCH_CALIB_DELAY); +} + +/*! + * @brief Process the State Machine + * + * @param None + * + * @retval None + */ +void TSC_Linrot_Process(void) +{ + TSC_STATEID_T stateID; + + /* Check if at least one channel has a data ready */ + if ((TSC_Linrot_Process_OneChannel_DataReady() == TSC_STATUS_OK) || (FOR_STATEID == TSC_STATEID_OFF)) + { + stateID = FOR_STATEID; + +#if TOUCH_TOTAL_LINROTS > 0 + if ((TSC_Globals.For_Obj->Type == TSC_OBJ_LINEAR) || + (TSC_Globals.For_Obj->Type == TSC_OBJ_ROTARY)) + { + TSC_Globals.For_LinRot->p_SM[FOR_STATEID].StateFunc(); + } +#endif + +#if TOUCH_TOTAL_LINROTS_B > 0 + if ((TSC_Globals.For_Obj->Type == TSC_OBJ_LINEARB) || + (TSC_Globals.For_Obj->Type == TSC_OBJ_ROTARYB)) + { + TSC_Params.p_LinRotSta[FOR_STATEID].StateFunc(); + } +#endif + + if (FOR_STATEID != stateID) + { + FOR_CHANGE = TSC_STATE_CHANGED; + } + else + { + FOR_CHANGE = TSC_STATE_NOT_CHANGED; + } + +#if TOUCH_USE_DXS > 0 + if (FOR_STATEID != TSC_STATEID_DETECT) + { + FOR_DXSLOCK = TSC_FALSE; + } + if (FOR_STATEID == TSC_STATEID_TOUCH) + { + FOR_STATEID = TSC_STATEID_DETECT; + } +#endif + } +} + +/*! + * @brief Calculate the position + * + * @param None + * + * @retval Status Return OK if position calculation is correct + * + * @note The position is calculated only if the number of channels is greater than 2 + */ +TSC_STATUS_T TSC_Linrot_CalcPos(void) +{ + TSC_tIndex_T index; + TSC_tDelta_T normDelta; + TSC_tNum_T minor, major; + TSC_tNum_T sector = 0; + TSC_tNum_T prePosition = 0; + TSC_tPosition_T curPosition = 0; + TSC_tsignPosition_T updatePosition = 0; + static TSC_tIndex_T index1, index2; + static TSC_tDelta_T delta1, delta2, delta3; + + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + + index1 = 0; + index2 = 0; + delta1 = 0; + delta2 = 0; + delta3 = 0; + + FOR_POSCHANGE = TSC_STATE_NOT_CHANGED; + + if (FOR_NB_CHANNELS < 3) + { + return TSC_STATUS_ERROR; + } + + /** + * Sort the channels' delta + * - delta1 and index1 = biggest + * - delta2 and index2 = middle + * - delta3 and index3 = lowest + */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { +#if TOUCH_LINROT_USE_NORMDELTA > 0 + normDelta = TSC_Linrot_NormDelta(p_Ch, index); +#else + normDelta = p_Ch->Delta; +#endif + + if (normDelta < 0) + { + normDelta = 0; + } + + if (normDelta <= delta1) + { + if (normDelta <= delta2) + { + if (normDelta > delta3) + { + delta3 = normDelta; + } + } + else + { + delta3 = delta2; + delta2 = normDelta; + index2 = index; + } + } + else + { + delta3 = delta2; + delta2 = delta1; + delta1 = normDelta; + index2 = index1; + index1 = index; + } + p_Ch++; + } + + if (delta2 < ((TSC_tThreshold_T)(FOR_DETECTOUT_TH >> 1) - 1)) + { + return TSC_STATUS_ERROR; + } + + /******************** Position calculation **********************/ + + /** + * B = Biggest signal measured (Delta1/Index1) + * M = Middle signal measured (Delta2/Index2) + * S = Smallest signal measured (Delta3/Index3) + * + * - The equation to find the position is: + * Position = Offset +/- [ Sector_Size x ( Major / (Major + Minor) ) ] + * + * - The Offset is the position of the middle of the Middle signal segment. + * All the Offset values are stored in the ROM table Table_POSITION_OFFSET. + * + * - Major = Biggest - Smallest signals + * Minor = Middle - Smallest signals + * + * - The Sector_Size depends of the number of channels used + */ + + /* Calculates the Major and Minor parameters */ + minor = (TSC_tNum_T)(delta2 - delta3); /*!p_PosOff + (index1 * FOR_NB_CHANNELS) + index2); + sector = FOR_SCT_COMP; + prePosition = FOR_POS_CORR; + + /* Calculates: [ Sector_Size x ( Major / (Major + Minor) ) ] */ + sector = major * sector; + sector = sector / (major + minor); + + /* Use the sign bit from position table to define the interpretation direction. + The NewPosition is multiplied by 2 because the Offset stored in the ROM + table is divided by 2... */ + if (curPosition <= 0) /*! 0 in the position table */ + { + curPosition = (TSC_tPosition_T)(curPosition << 1); + curPosition += sector; + } + + /* Position is calculated differently if LINEAR or ROTARY sensor */ + if ((FOR_OBJ_TYPE == TSC_OBJ_LINEAR) || (FOR_OBJ_TYPE == TSC_OBJ_LINEARB)) + { + /* First adjustment used to shift all the values to obtain the "zero" */ + if (curPosition <= 0) + { + curPosition = curPosition + (256 - prePosition); + } + else + { + curPosition -= prePosition; + } + /*! 255) + { + curPosition = 255; + } + if (curPosition < 0) + { + curPosition = 0; + } + } + else /*! (uint16_t)(FOR_RAW_POSITION + DIRECTION_CHANGE_MAX_DISPLACEMENT)) + { + if ((curPosition + FOR_DIR_CHG_POS) <= (uint16_t)(FOR_RAW_POSITION + DIRECTION_CHANGE_TOTAL_STEPS)) + { + FOR_COUNTER_DIR--; + if (FOR_COUNTER_DIR) + { + return TSC_STATUS_ERROR; + } + else + { + FOR_COUNTER_DIR = FOR_COUNTER_DEB_DIRECTION; + FOR_DIRECTION = TSC_TRUE; /*! FOR_RAW_POSITION) && (((TSC_tsignPosition_T)curPosition - FOR_RAW_POSITION) < DIRECTION_CHANGE_MAX_DISPLACEMENT)) + { + if (curPosition >= (uint16_t)(FOR_RAW_POSITION + FOR_DIR_CHG_POS)) + { + FOR_COUNTER_DIR--; + if (FOR_COUNTER_DIR) + { + return TSC_STATUS_ERROR; + } + else + { + FOR_COUNTER_DIR = FOR_COUNTER_DEB_DIRECTION; + FOR_DIRECTION = TSC_FALSE; /*!= (uint16_t)(FOR_RAW_POSITION + FOR_DIR_CHG_POS)) + { + FOR_COUNTER_DIR--; + if (FOR_COUNTER_DIR) + { + return TSC_STATUS_ERROR; + } + else + { + FOR_COUNTER_DIR = FOR_COUNTER_DEB_DIRECTION; + FOR_DIRECTION = TSC_FALSE; /*!> (RESOLUTION_CALCULATION - FOR_RESOLUTION)); + + if (FOR_POSITION != updatePosition) + { + FOR_POSITION = updatePosition; + FOR_POSCHANGE = TSC_STATE_CHANGED; + return TSC_STATUS_OK; + } + else + { + return TSC_STATUS_ERROR; + } +} + +/**@} "Object_methods" Functions */ + +/** @defgroup Utility Functions + @{ +*/ + +/*! + * @brief Go in Calibration state + * + * @param delay Delay before calibration starts (stabilization of noise filter) + * + * @retval None + */ +void TSC_Linrot_ConfigCalibrationState(TSC_tCounter_T delay) +{ + FOR_STATEID = TSC_STATEID_CALIB; + FOR_CHANGE = TSC_STATE_CHANGED; + TSC_Linrot_Process_AllChannel_Status(TSC_OBJ_STATUS_ON); + + if (TSC_Params.NumCalibSample == 4) + { + CalibDiv = 2; + } + else if (TSC_Params.NumCalibSample == 16) + { + CalibDiv = 4; + } + else + { + TSC_Params.NumCalibSample = 8; + CalibDiv = 3; + } + + /* If a noise filter is used, the counter must be initialized to a value + different from 0 in order to stabilize the filter */ + FOR_COUNTER_DEB = (TSC_tCounter_T)(delay + (TSC_tCounter_T)TSC_Params.NumCalibSample); + TSC_Linrot_Process_AllChannel_ClearRef(); +} + +/*! + * @brief Go in Off state with sensor "off" + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ConfigOffState(void) +{ + FOR_STATEID = TSC_STATEID_OFF; + FOR_CHANGE = TSC_STATE_CHANGED; + TSC_Linrot_Process_AllChannel_Status(TSC_OBJ_STATUS_OFF); +} + +/*! + * @brief Go in Off state with sensor in "Burst mode only" + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ConfigBurstOnlyState(void) +{ + FOR_STATEID = TSC_STATEID_OFF; + FOR_CHANGE = TSC_STATE_CHANGED; + TSC_Linrot_Process_AllChannel_Status(TSC_OBJ_STATUS_BURST_ONLY); +} + +/*! + * @brief Return the current state identifier + * + * @param None + * + * @retval State id + */ +TSC_STATEID_T TSC_Linrot_ReadStateId(void) +{ + return (FOR_STATEID); +} + +/*! + * @brief Return the current state mask + * + * @param None + * + * @retval State mask + */ +TSC_STATEMASK_T TSC_Linrot_ReadStateMask(void) +{ + TSC_STATEMASK_T state_mask = TSC_STATEMASK_UNKNOWN; + + switch (TSC_Globals.For_Obj->Type) + { +#if TOUCH_TOTAL_LINROTS > 0 + case TSC_OBJ_LINEAR: + case TSC_OBJ_ROTARY: + state_mask = TSC_Globals.For_LinRot->p_SM[FOR_STATEID].StateMask; + break; +#endif + +#if TOUCH_TOTAL_LINROTS_B > 0 + case TSC_OBJ_LINEARB: + case TSC_OBJ_ROTARYB: + state_mask = TSC_Params.p_LinRotSta[FOR_STATEID].StateMask; + break; +#endif + default: + break; + } + return state_mask; +} + +/*! + * @brief Return the Change flag + * + * @param None + * + * @retval Change flag status + */ +TSC_tNum_T TSC_Linrot_ReadChangeFlag(void) +{ + return (FOR_CHANGE); +} + +/**@} Utility Functions */ + +/** @defgroup State_machine Functions + @{ +*/ + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Release processing (previous state = Proximity) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebReleaseProxState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0)) + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + } + } + else + { + /* Go back to the previous state */ + FOR_STATEID = TSC_STATEID_PROX; + } +} +#endif /*! 0 */ + +/*! + * @brief Debounce Release processing (previous state = Detect) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebReleaseDetectState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_DETECTOUT_TH, 1)) + { +#if TOUCH_USE_PROX > 0 + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0) == TSC_STATUS_OK) + { + FOR_STATEID = TSC_STATEID_PROX; + return; + } +#endif + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + } + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + } +} + +/*! + * @brief Debounce Release processing (previous state = Touch) + * Same as Debounce Release Detect processing + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebReleaseTouchState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_DETECTOUT_TH, 1)) + { +#if TOUCH_USE_PROX > 0 + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0) == TSC_STATUS_OK) + { + FOR_STATEID = TSC_STATEID_PROX; + return; + } +#endif + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_STATEID = TSC_STATEID_TOUCH; + } + } + else + { + FOR_STATEID = TSC_STATEID_TOUCH; + } +} + +/*! + * @brief Release state processing + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessReleaseState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_DETECTIN_TH, 1) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_DETECT; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + return; + } + +#if TOUCH_USE_PROX > 0 + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_PROXIN_TH, 0) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + return; + } +#endif + + /* Check delta for re-calibration */ + if (TSC_Linrot_Process_OneChannel_DeltaBelowEquMinus(FOR_CALIB_TH, 1) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_CALIB; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_CALIB; + } + else + { + TSC_Linrot_ConfigCalibrationState(0); + } + } + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_RELEASE; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } +} + +/*! + * @brief Debounce Calibration processing (previous state = Release) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebCalibrationState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaBelowEquMinus(FOR_CALIB_TH, 1)) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + TSC_Linrot_ConfigCalibrationState(0); + } + } + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } +} + +/*! + * @brief Calibration state processing + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessCalibrationState(void) +{ + TSC_tMeas_T newMeas; + TSC_tIndex_T index; + TSC_Channel_Data_T* p_Ch; + +#if TOUCH_CALIB_DELAY > 0 + /* Noise filter stabilization time */ + if (FOR_COUNTER_DEB > (TSC_tCounter_T)TSC_Params.NumCalibSample) + { + FOR_COUNTER_DEB--; + return; + } +#endif + + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + /* Process all channels */ + p_Ch = TSC_Globals.For_LinRot->p_ChD; + + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + /* Read the new measure or Calculate it */ +#if TOUCH_USE_MEAS > 0 + newMeas = p_Ch->Meas; +#else + newMeas = TSC_Acq_ComputeMeas(p_Ch->Refer, p_Ch->Delta); +#endif + + /* Verify the first Reference value */ + if (FOR_COUNTER_DEB != (TSC_tCounter_T)TSC_Params.NumCalibSample) + { + p_Ch->Refer += newMeas; + + if (p_Ch->Refer < newMeas) + { + p_Ch->Refer = 0; + FOR_STATEID = TSC_STATEID_ERROR; + return; + } + } + else + { + if (TSC_Acq_TestFirstReference(p_Ch, newMeas)) + { + p_Ch->Refer = newMeas; + } + else + { + p_Ch->Refer = 0; + return; + } + } + p_Ch++; + } + + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + /* Process all channels */ + p_Ch = TSC_Globals.For_LinRot->p_ChD; + + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + p_Ch->Refer >>= CalibDiv; + p_Ch->RefRest = 0; + p_Ch->Delta = 0; + p_Ch++; + } + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_CALIB; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } +} + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Proximity processing (previous state = Release) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebProxState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_DETECTIN_TH, 1) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_DETECT; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + return; + } + + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_PROXIN_TH, 0)) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } +} +#endif + + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Proximity processing (previous state = Detect) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebProxDetectState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_DETECTOUT_TH, 1) == TSC_STATUS_OK) + { + FOR_STATEID = TSC_STATEID_DETECT; + return; + } + + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0)) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + } +} +#endif + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Proximity processing (previous state = Touch) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebProxTouchState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_DETECTOUT_TH, 1) == TSC_STATUS_OK) + { + FOR_STATEID = TSC_STATEID_TOUCH; + return; + } + + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0)) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } + } + else + { + FOR_STATEID = TSC_STATEID_TOUCH; + } +} +#endif + +#if TOUCH_USE_PROX > 0 +/*! + * @brief roximity state processing + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessProxState(void) +{ +#if TOUCH_DTO > 0 + TSC_tTick_sec_T tick_detected; +#endif + + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_DETECTIN_TH, 1) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_DETECT; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + return; + } + + if (TSC_Linrot_Process_AllChannel_DeltaBelowEqu(FOR_PROXOUT_TH, 0) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + return; + } + + /* Stay in Proximity state */ +#if TOUCH_DTO > 0 + /* Detection Time Out (DTO) processing */ + if ((TSC_Params.DTO > 1) && (TSC_Params.DTO < 64)) + { + tick_detected = FOR_COUNTER_DTO; + /* Enter in calibration state if the DTO duration has elapsed */ + if (TSC_Time_Delay_sec(TSC_Params.DTO, &tick_detected) == TSC_STATUS_OK) + { + TSC_Linrot_ConfigCalibrationState(0); + } + } +#endif + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } +} +#endif + +/*! + * @brief Debounce Detect processing (previous state = Release or Proximity) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebDetectState(void) +{ + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_DETECTIN_TH, 1)) + { +#if TOUCH_USE_PROX > 0 + if (TSC_Linrot_Process_OneChannel_DeltaAboveEqu(FOR_PROXIN_TH, 0)) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } +#else + FOR_STATEID = TSC_STATEID_RELEASE; +#endif + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + } + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } +} + +/*! + * @brief Detect state processing + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDetectState(void) +{ +#if TOUCH_DTO > 0 + TSC_STATUS_T pos_sts; + TSC_tTick_sec_T tick_detected; +#endif + + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_DETECTOUT_TH, 1) == TSC_STATUS_OK) + { + /* Calculate position */ + if ((FOR_OBJ_TYPE == TSC_OBJ_LINEAR) || (FOR_OBJ_TYPE == TSC_OBJ_ROTARY)) + { +#if TOUCH_DTO > 0 + pos_sts = TSC_Globals.For_LinRot->p_Methods->CalcPosition(); +#else + TSC_Globals.For_LinRot->p_Methods->CalcPosition(); +#endif + } + else /*! 0 + pos_sts = TSC_Params.p_LinRotMet->CalcPosition(); +#else + TSC_Params.p_LinRotMet->CalcPosition(); +#endif + } +#if TOUCH_DTO > 0 + /* Detection Time Out (DTO) processing, Only if the Position has NOT changed */ + if (pos_sts) + { + if ((TSC_Params.DTO > 1) && (TSC_Params.DTO < 64)) + { + tick_detected = FOR_COUNTER_DTO; + /* Enter in calibration state if the DTO duration has elapsed */ + if (TSC_Time_Delay_sec(TSC_Params.DTO, &tick_detected) == TSC_STATUS_OK) + { + TSC_Linrot_ConfigCalibrationState(0); + } + } + } + else + { + DTO_READ_TIME; + } +#endif + return; + } + +#if TOUCH_USE_PROX > 0 + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + return; + } +#endif + + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } +} + +/*! + * @brief Touch state processing, Same as Detect state + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessTouchState(void) +{ +#if TOUCH_DTO > 0 + TSC_STATUS_T pos_sts; + TSC_tTick_sec_T tick_detected; +#endif + + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_DETECTOUT_TH, 1) == TSC_STATUS_OK) + { + /* Calculate position */ + if ((FOR_OBJ_TYPE == TSC_OBJ_LINEAR) || (FOR_OBJ_TYPE == TSC_OBJ_ROTARY)) + { +#if TOUCH_DTO > 0 + pos_sts = TSC_Globals.For_LinRot->p_Methods->CalcPosition(); +#else + TSC_Globals.For_LinRot->p_Methods->CalcPosition(); +#endif + } + else /* TSC_OBJ_LINEARB or TSC_OBJ_ROTARYB */ + { +#if TOUCH_DTO > 0 + pos_sts = TSC_Params.p_LinRotMet->CalcPosition(); +#else + TSC_Params.p_LinRotMet->CalcPosition(); +#endif + } +#if TOUCH_DTO > 0 + /* Detection Time Out (DTO) processing, Only if the Position has NOT changed */ + if (pos_sts) + { + if ((TSC_Params.DTO > 1) && (TSC_Params.DTO < 64)) + { + tick_detected = FOR_COUNTER_DTO; + /* Enter in calibration state if the DTO duration has elapsed */ + if (TSC_Time_Delay_sec(TSC_Params.DTO, &tick_detected) == TSC_STATUS_OK) + { + TSC_Linrot_ConfigCalibrationState(0); + } + } + } + else + { + DTO_READ_TIME; + } +#endif + return; + } + +#if TOUCH_USE_PROX > 0 + if (TSC_Linrot_Process_OneChannel_DeltaAbove(FOR_PROXOUT_TH, 0) == TSC_STATUS_OK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + return; + } +#endif + + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } +} + +/*! + * @brief Debounce error state processing + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ProcessDebErrorState(void) +{ + volatile TSC_STATEMASK_T mask; + + if (TSC_Linrot_Process_OneChannel_AcqStatusError()) + { + mask = TSC_Linrot_ReadStateMask(); + mask &= (TSC_STATEMASK_T)(~(TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK)); + + if (mask == TSC_STATEMASK_RELEASE) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else if (mask == TSC_STATEMASK_PROX) + { + FOR_STATEID = TSC_STATEID_PROX; + } + else if (mask == TSC_STATEMASK_DETECT) + { + FOR_STATEID = TSC_STATEID_DETECT; + } + else if (mask == TSC_STATEMASK_TOUCH) + { + FOR_STATEID = TSC_STATEID_TOUCH; + } + else + { + TSC_Linrot_ConfigCalibrationState(0); + } + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } +} + +/**@} State_machine Functions */ + +/** @defgroup Private Functions + @{ +*/ + +/*! + * @brief Read the current time in second and affect it to the DTO counter (Private) + * + * @param None + * + * @retval None + */ +void TSC_Linrot_ReadTimeForDTO(void) +{ + disableInterrupts(); + FOR_COUNTER_DTO = (TSC_tCounter_T)TSC_Globals.Tick_sec; + enableInterrupts(); +} + +/*! + * @brief Set all channels status to ON, OFF or BURST only + * + * @param status: Channel status + * + * @retval None + */ +void TSC_Linrot_Process_AllChannel_Status(TSC_OBJ_STATUS_T status) +{ + TSC_tIndex_T index; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + /* Config channels status */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + p_Ch->Flag.ObjStatus = status; + p_Ch++; + } +} + +/*! + * @brief Check if at least one channel has a data ready + * + * @param None + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DataReady(void) +{ + TSC_tIndex_T index; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + TSC_STATUS_T retval = TSC_STATUS_ERROR; + /* Return OK if at least one channel has a data ready */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + if (p_Ch->Flag.DataReady == TSC_DATA_READY) + { + p_Ch->Flag.DataReady = TSC_DATA_NOT_READY; + retval = TSC_STATUS_OK; + } + p_Ch++; + } + return retval; +} + +/*! + * @brief Check if all channels are equal to the status passed + * + * @param status: Channel status + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_AllChannel_AcqStatus(TSC_ACQ_STATUS_T status) +{ + TSC_tIndex_T index; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + /* Return OK if ALL channels have the correct acq status */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + if (p_Ch->Flag.AcqStatus != status) + { + return TSC_STATUS_ERROR; + } + p_Ch++; + } + return TSC_STATUS_OK; +} + +/*! + * @brief Check if at least one channel is in error + * + * @param None + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_OneChannel_AcqStatusError(void) +{ + TSC_tIndex_T index; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + /* Return OK if at least one channel is in acquisition error min or max */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + if (p_Ch->Flag.AcqStatus & TSC_ACQ_STATUS_ERROR_MASK) + { + return TSC_STATUS_OK; + } + p_Ch++; + } + return TSC_STATUS_ERROR; +} + +/*! + * @brief Check if at least one channel is below or equal a threshold (inverted) + * + * @param threshold: Threshold + * + * @param Cmd: Enable or Disable the multiplier coefficient on threshold + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DeltaBelowEquMinus(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd) +{ + TSC_tIndex_T index; + TSC_tDelta_T normDelta; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + +#if TOUCH_COEFF_TH > 0 + uint16_t nowThreshold; + if (Cmd != ENABLE) + { + nowThreshold = threshold; + } + else + { + nowThreshold = (uint16_t)((uint16_t)threshold << TOUCH_COEFF_TH); + } +#endif + + /* Return OK if at least one channel is below or equal the threshold */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { +#if TOUCH_LINROT_USE_NORMDELTA > 0 + normDelta = TSC_Linrot_NormDelta(p_Ch, index); +#else + normDelta = p_Ch->Delta; +#endif + +#if TOUCH_COEFF_TH > 0 + if (normDelta <= -nowThreshold) +#else + if (normDelta <= -threshold) +#endif + { + return TSC_STATUS_OK; + } + p_Ch++; + } + return TSC_STATUS_ERROR; +} + +/*! + * @brief Check if at least one channel is above or equal a threshold + * + * @param threshold: Threshold + * + * @param Cmd: Enable or Disable the multiplier coefficient on threshold + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DeltaAboveEqu(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd) +{ + TSC_tIndex_T index; + TSC_tDelta_T normDelta; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + +#if TOUCH_COEFF_TH > 0 + uint16_t nowThreshold; + if (Cmd != ENABLE) + { + nowThreshold = threshold; + } + else + { + nowThreshold = (uint16_t)((uint16_t)threshold << TOUCH_COEFF_TH); + } +#endif + + /* Return OK if at least one channel is above or equal the threshold */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { +#if TOUCH_LINROT_USE_NORMDELTA > 0 + normDelta = TSC_Linrot_NormDelta(p_Ch, index); +#else + normDelta = p_Ch->Delta; +#endif + +#if TOUCH_COEFF_TH > 0 + if (normDelta >= nowThreshold) +#else + if (normDelta >= threshold) +#endif + { +#if TOUCH_COEFF_TH > 0 + if (normDelta < 0) + { + p_Ch++; + continue; + } +#endif + return TSC_STATUS_OK; + } + p_Ch++; + } + return TSC_STATUS_ERROR; +} + +/*! + * @brief Check if at least one channel is stricly above a threshold + * + * @param threshold: Threshold + * + * @param Cmd: Enable or Disable the multiplier coefficient on threshold + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_OneChannel_DeltaAbove(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd) +{ + TSC_tIndex_T index; + TSC_tDelta_T normDelta; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + +#if TOUCH_COEFF_TH > 0 + uint16_t nowThreshold; + if (Cmd != ENABLE) + { + nowThreshold = threshold; + } + else + { + nowThreshold = (uint16_t)((uint16_t)threshold << TOUCH_COEFF_TH); + } +#endif + + /* Return OK if at least one channel is above the threshold */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { +#if TOUCH_LINROT_USE_NORMDELTA > 0 + normDelta = TSC_Linrot_NormDelta(p_Ch, index); +#else + normDelta = p_Ch->Delta; +#endif + +#if TOUCH_COEFF_TH > 0 + if (normDelta > nowThreshold) +#else + if (normDelta > threshold) +#endif + { +#if TOUCH_COEFF_TH > 0 + if (normDelta < 0) + { + p_Ch++; + continue; + } +#endif + return TSC_STATUS_OK; + } + p_Ch++; + } + return TSC_STATUS_ERROR; +} + +/*! + * @brief Check if all channels are below or equal a threshold + * + * @param threshold: Threshold + * + * @param Cmd: Enable or Disable the multiplier coefficient on threshold + * + * @retval Status + */ +TSC_STATUS_T TSC_Linrot_Process_AllChannel_DeltaBelowEqu(TSC_tThreshold_T threshold, TSC_tIndex_T Cmd) +{ + TSC_tIndex_T index; + TSC_tDelta_T normDelta; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + +#if TOUCH_COEFF_TH > 0 + uint16_t nowThreshold; + if (Cmd != ENABLE) + { + nowThreshold = threshold; + } + else + { + nowThreshold = (uint16_t)((uint16_t)threshold << TOUCH_COEFF_TH); + } +#endif + + /* Return OK if ALL channels are below or equal the threshold */ + for (index = 0; index < FOR_NB_CHANNELS; index++) + { +#if TOUCH_LINROT_USE_NORMDELTA > 0 + normDelta = TSC_Linrot_NormDelta(p_Ch, index); +#else + normDelta = p_Ch->Delta; +#endif + +#if TOUCH_COEFF_TH > 0 + if (normDelta > nowThreshold) +#else + if (normDelta > threshold) +#endif + { +#if TOUCH_COEFF_TH > 0 + if (normDelta < 0) + { + p_Ch++; + continue; + } +#endif + return TSC_STATUS_ERROR; + } + p_Ch++; + } + return TSC_STATUS_OK; +} + +/*! + * @brief Clear the Reference and ReferenceRest for all channels + * + * @param None + * + * @retval None + */ +void TSC_Linrot_Process_AllChannel_ClearRef(void) +{ + TSC_tIndex_T index; + TSC_Channel_Data_T* p_Ch = TSC_Globals.For_LinRot->p_ChD; + for (index = 0; index < FOR_NB_CHANNELS; index++) + { + p_Ch->Refer = 0; + p_Ch->RefRest = 0; + p_Ch++; + } +} + +/*! + * @brief Normalize a Delta value + * + * @param channel: Pointer to the current channel + * + * @param index: Index of the channel + * + * @retval Normalized Delta value + */ +TSC_tDelta_T TSC_Linrot_NormDelta(TSC_Channel_Data_T* channel, TSC_tIndex_T index) +{ + uint32_t tmpdelta = channel->Delta; + + if (TSC_Globals.For_LinRot->p_DeltaCoeff[index] != 0x0100) + { + tmpdelta = (uint32_t)(tmpdelta * TSC_Globals.For_LinRot->p_DeltaCoeff[index]); + tmpdelta = tmpdelta >> (uint8_t)8; + } + return (TSC_tDelta_T)tmpdelta; +} +#endif /*!<#if TOUCH_TOTAL_LNRTS > 0 */ + +/**@} Private Functions */ + +/**@} end of group TSC_Linrot_Functions */ +/**@} end of group TSC_Linrot_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_object.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_object.c new file mode 100644 index 0000000000..cf91a3f455 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_object.c @@ -0,0 +1,250 @@ +/*! + * @file tsc_object.c + * + * @brief This file contains all functions to manage the sensors in general. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" +#include "tsc_object.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Object_Driver TSC Driver + @{ +*/ + +/** @defgroup TSC_Object_Macros Macros + @{ +*/ + +/**@} end of group TSC_Object_Macros */ + +/** @defgroup TSC_Object_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Object_Enumerations */ + +/** @defgroup TSC_Object_Structures Structures + @{ +*/ + +/**@} end of group TSC_Object_Structures */ + +/** @defgroup TSC_Object_Variables Variables + @{ +*/ + +/**@} end of group TSC_Object_Variables */ + +/** @defgroup TSC_Object_Functions Functions + @{ +*/ + +/*! + * @brief Config a group of Objects + * + * @param objgrp: Pointer to the group of objects + * + * @retval None + */ +void TSC_Obj_ConfigGroup(TSC_ObjectGroup_T* objgrp) +{ + TSC_tIndex_T idxObj; + CONST TSC_Object_T* pObj; + TSC_tNum_T stateMask = 0; + + pObj = objgrp->p_Obj; + objgrp->Change = TSC_STATE_NOT_CHANGED; + + /* Process all objects */ + for (idxObj = 0; idxObj < objgrp->NbObjects; idxObj++) + { + TSC_Obj_ConfigGlobalObj(pObj); + + if (pObj->Type == TSC_OBJ_TOUCHKEY) + { +#if TOUCH_TOTAL_TOUCHKEYS > 0 + TSC_Globals.For_Key->p_Methods->Config(); + + if (TSC_Globals.For_Key->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + stateMask |= TSC_Globals.For_Key->p_SM[TSC_Globals.For_Key->p_Data->StateId].StateMask; +#endif + } + else if (pObj->Type == TSC_OBJ_TOUCHKEYB) + { +#if TOUCH_TOTAL_TOUCHKEYS_B > 0 + TSC_Params.p_KeyMet->Config(); + + if (TSC_Globals.For_Key->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + + stateMask |= TSC_Params.p_KeySta[TSC_Globals.For_Key->p_Data->StateId].StateMask; +#endif + } + else if ((pObj->Type == TSC_OBJ_LINEAR) || (pObj->Type == TSC_OBJ_ROTARY)) + { +#if TOUCH_TOTAL_LINROTS > 0 + TSC_Globals.For_LinRot->p_Methods->Config(); + + if (TSC_Globals.For_LinRot->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + + stateMask |= TSC_Globals.For_LinRot->p_SM[TSC_Globals.For_LinRot->p_Data->StateId].StateMask; +#endif + } + else if ((pObj->Type == TSC_OBJ_LINEARB) || (pObj->Type == TSC_OBJ_ROTARYB)) + { +#if TOUCH_TOTAL_LINROTS_B > 0 + TSC_Params.p_LinRotMet->Config(); + + if (TSC_Globals.For_LinRot->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + stateMask |= TSC_Params.p_LinRotSta[TSC_Globals.For_LinRot->p_Data->StateId].StateMask; +#endif + } + pObj++; + } + /* Update the object group state mask */ + objgrp->StateMask = stateMask; +} + +/*! + * @brief Process the state machine on a group of Objects + * + * @param objgrp: Pointer to the group of objects to process + * + * @retval None + */ +void TSC_Obj_ProcessGroup(TSC_ObjectGroup_T* objgrp) +{ + TSC_tIndex_T idxObj; + CONST TSC_Object_T* pObj; + TSC_tNum_T stateMask = 0; + + pObj = objgrp->p_Obj; + objgrp->Change = TSC_STATE_NOT_CHANGED; + + /* Process all objects */ + for (idxObj = 0; idxObj < objgrp->NbObjects; idxObj++) + { + TSC_Obj_ConfigGlobalObj(pObj); + + if (pObj->Type == TSC_OBJ_TOUCHKEY) + { +#if TOUCH_TOTAL_TOUCHKEYS > 0 + TSC_Globals.For_Key->p_Methods->Process(); + + if (TSC_Globals.For_Key->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + + stateMask |= TSC_Globals.For_Key->p_SM[TSC_Globals.For_Key->p_Data->StateId].StateMask; +#endif + } + else if (pObj->Type == TSC_OBJ_TOUCHKEYB) + { +#if TOUCH_TOTAL_TOUCHKEYS_B > 0 + TSC_Params.p_KeyMet->Process(); + + if (TSC_Globals.For_Key->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + + stateMask |= TSC_Params.p_KeySta[TSC_Globals.For_Key->p_Data->StateId].StateMask; +#endif + } + else if ((pObj->Type == TSC_OBJ_LINEAR) || (pObj->Type == TSC_OBJ_ROTARY)) + { +#if TOUCH_TOTAL_LINROTS > 0 + TSC_Globals.For_LinRot->p_Methods->Process(); + + if (TSC_Globals.For_LinRot->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + + stateMask |= TSC_Globals.For_LinRot->p_SM[TSC_Globals.For_LinRot->p_Data->StateId].StateMask; +#endif + } + else if ((pObj->Type == TSC_OBJ_LINEARB) || (pObj->Type == TSC_OBJ_ROTARYB)) + { +#if TOUCH_TOTAL_LINROTS_B > 0 + TSC_Params.p_LinRotMet->Process(); + + if (TSC_Globals.For_LinRot->p_Data->Change) + { + objgrp->Change = TSC_STATE_CHANGED; + } + + stateMask |= TSC_Params.p_LinRotSta[TSC_Globals.For_LinRot->p_Data->StateId].StateMask; +#endif + } + pObj++; + } + /* Update the object group state mask */ + objgrp->StateMask = stateMask; +} + +/*! + * @brief Set the global object variable + * + * @param pObj: Pointer to the object to process + * + * @retval None + */ +void TSC_Obj_ConfigGlobalObj(CONST TSC_Object_T* pObj) +{ + TSC_Globals.For_Obj = pObj; + + if ((pObj->Type == TSC_OBJ_TOUCHKEY) || (pObj->Type == TSC_OBJ_TOUCHKEYB)) + { +#if TOUCH_TOTAL_KEYS > 0 + TSC_Globals.For_Key = (TSC_TouchKey_T*)pObj->MyObj; +#endif + } + else if ((pObj->Type == TSC_OBJ_LINEAR) || (pObj->Type == TSC_OBJ_LINEARB) || + (pObj->Type == TSC_OBJ_ROTARY) || (pObj->Type == TSC_OBJ_ROTARYB)) + { +#if TOUCH_TOTAL_LNRTS > 0 + TSC_Globals.For_LinRot = (TSC_LinRot_T*)pObj->MyObj; +#endif + } +} + +/**@} end of group TSC_Object_Functions */ +/**@} end of group TSC_Object_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_time.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_time.c new file mode 100644 index 0000000000..aa88141e18 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_time.c @@ -0,0 +1,224 @@ +/*! + * @file tsc_time.c + * + * @brief This file contains all functions to manage the timings in general. + * + * @version V1.0.0 + * + * @date 2022-02-21 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "tsc.h" +#include "tsc_time.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_Time_Driver TSC Time Driver + @{ +*/ + +/** @defgroup TSC_Time_Macros Macros + @{ +*/ + +/**@} end of group TSC_Time_Macros */ + +/** @defgroup TSC_Time_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_Time_Enumerations */ + +/** @defgroup TSC_Time_Structures Structures + @{ +*/ + +/**@} end of group TSC_Time_Structures */ + +/** @defgroup TSC_Time_Variables Variables + @{ +*/ + +/**@} end of group TSC_Time_Variables */ + +/** @defgroup TSC_Time_Functions Functions + @{ +*/ + +/*! + * @brief Configurate of the timing module + * + * @param None + * + * @retval pointer to a TSC_STATUS_T structure + */ +TSC_STATUS_T TSC_Time_Config(void) +{ + /* Program one systick interrupt every (1 / TOUCH_TICK_FREQ) ms */ + if (SysTick_Config(SystemCoreClock / TOUCH_TICK_FREQ)) + { + return TSC_STATUS_ERROR; + } + else + { + return TSC_STATUS_OK; + } +} + +/*! + * @brief Management of the timing module interrupt service routine. + * + * @param None + * + * @retval None + */ +void TSC_Time_ProcessInterrupt(void) +{ + static TSC_tTick_ms_T val_1s = 0; + + /* Count 1 global tick every xxx ms (defined by TOUCH_TICK_FREQ parameter) */ + TSC_Globals.Tick_ms++; + + /* Check if 1 second has elapsed */ + val_1s++; + if (val_1s > (TOUCH_TICK_FREQ - 1)) + { + TSC_Globals.Tick_sec++; + if (TSC_Globals.Tick_sec > 63) + { + TSC_Globals.Tick_sec = 0; + } + val_1s = 0; + } + + /* Callback function */ +#if TOUCH_USE_TIMER_CALLBACK > 0 + TSC_CallBack_TimerTick(); +#endif +} + +/*! + * @brief Check if a delay (in ms) has elapsed + * This function must be called regularly due to counter Roll-over only managed one time + * + * @param delay_ms: Delay in ms + * + * @param last_tick: Variable holding the last tick value + * + * @retval Status + */ +TSC_STATUS_T TSC_Time_Delay_ms(TSC_tTick_ms_T delay_ms, __IO TSC_tTick_ms_T* last_tick) +{ + TSC_tTick_ms_T count1, count2; + + disableInterrupts(); + + count1 = TSC_Globals.Tick_ms; + + if (delay_ms == 0) + { + enableInterrupts(); + return TSC_STATUS_ERROR; + } + + /* Counter Roll-over management */ + if (count1 < *last_tick) + { + count2 = (0xFFFF - *last_tick) + count1 + 1; + + } + else + { + count2 = count1 - *last_tick; + } + +#if (TOUCH_TICK_FREQ == 125) + if (count2 >= (TSC_tTick_ms_T)(delay_ms >> 3)) //!< Divide by 8 for 8ms tick +#endif +#if (TOUCH_TICK_FREQ == 250) + if (count2 >= (TSC_tTick_ms_T)(delay_ms >> 2)) //!< Divide by 4 for 4ms tick +#endif +#if (TOUCH_TICK_FREQ == 500) + if (count2 >= (TSC_tTick_ms_T)(delay_ms >> 1)) //!< Divide by 2 for 2ms tick +#endif +#if (TOUCH_TICK_FREQ == 1000) + if (count2 >= (TSC_tTick_ms_T)delay_ms) //!< Direct value for 1ms tick +#endif +#if (TOUCH_TICK_FREQ == 2000) + if (count2 >= (TSC_tTick_ms_T)(delay_ms << 1)) //!< Multiply by 2 for 0.5ms tick +#endif + { + /* Save current time */ + *last_tick = count1; + enableInterrupts(); + return TSC_STATUS_OK; + } + enableInterrupts(); + return TSC_STATUS_BUSY; +} + +/*! + * @brief Check if a delay has elapsed. + * + * @param delay_sec: Delay in seconds + * + * @param last_tick: Variable holding the last tick value + * + * @retval Status + */ +TSC_STATUS_T TSC_Time_Delay_sec(TSC_tTick_sec_T delay_sec, __IO TSC_tTick_sec_T* last_tick) +{ + TSC_tTick_sec_T count1, count2; + + disableInterrupts(); + + count1 = TSC_Globals.Tick_sec; + + if (delay_sec == 0) + { + enableInterrupts(); + return TSC_STATUS_ERROR; + } + + /* Counter Roll-over management */ + if (count1 < *last_tick) + { + count2 = (TSC_tTick_sec_T)((63 - *last_tick) + count1 + 1); + + } + else + { + count2 = (TSC_tTick_sec_T)(count1 - *last_tick); + } + + if (count2 >= delay_sec) + { + /* Save current time */ + *last_tick = count1; + enableInterrupts(); + return TSC_STATUS_OK; + } + enableInterrupts(); + return TSC_STATUS_BUSY; +} + +/**@} end of group TSC_Time_Functions */ +/**@} end of group TSC_Time_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_touchkey.c b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_touchkey.c new file mode 100644 index 0000000000..22b44f9905 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/TSC_Device_Lib/src/tsc_touchkey.c @@ -0,0 +1,1131 @@ +/*! + * @file tsc_touchkey.c + * + * @brief This file contains all functions to manage TouchKey sensors. + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "tsc.h" +#include "tsc_touchkey.h" + +/** @addtogroup TSC_Driver_Library TSC Driver Library + @{ +*/ + +/** @addtogroup TSC_TouchKey_Driver TSC TouchKey Driver + @{ +*/ + +/** @defgroup TSC_TouchKey_Macros Macros + @{ +*/ + +#if TOUCH_TOTAL_KEYS > 0 + +#define FOR_MEAS TSC_Globals.For_Key->p_ChD->Meas +#define FOR_DELTA TSC_Globals.For_Key->p_ChD->Delta +#define FOR_REFER TSC_Globals.For_Key->p_ChD->Refer +#define FOR_REFREST TSC_Globals.For_Key->p_ChD->RefRest +#define FOR_CHANNEL_DATA TSC_Globals.For_Key->p_ChD +#define FOR_ACQ_STATUS TSC_Globals.For_Key->p_ChD->Flag.AcqStatus +#define FOR_OBJ_STATUS TSC_Globals.For_Key->p_ChD->Flag.ObjStatus +#define FOR_DATA_READY TSC_Globals.For_Key->p_ChD->Flag.DataReady + +#define FOR_STATEID TSC_Globals.For_Key->p_Data->StateId +#define FOR_CHANGE TSC_Globals.For_Key->p_Data->Change +#define FOR_COUNTER_DEB TSC_Globals.For_Key->p_Data->CounterDebounce +#define FOR_COUNTER_DTO TSC_Globals.For_Key->p_Data->CounterDTO +#define FOR_DXSLOCK TSC_Globals.For_Key->p_Data->DxsLock + +#define FOR_PROXIN_TH TSC_Globals.For_Key->p_Param->ProxInTh +#define FOR_PROXOUT_TH TSC_Globals.For_Key->p_Param->ProxOutTh +#define FOR_DETECTIN_TH TSC_Globals.For_Key->p_Param->DetectInTh +#define FOR_DETECTOUT_TH TSC_Globals.For_Key->p_Param->DetectOutTh +#define FOR_CALIB_TH TSC_Globals.For_Key->p_Param->CalibTh + +#define FOR_COUNTER_DEB_CALIB TSC_Globals.For_Key->p_Param->CounterDebCalib +#define FOR_COUNTER_DEB_PROX TSC_Globals.For_Key->p_Param->CounterDebProx +#define FOR_COUNTER_DEB_DETECT TSC_Globals.For_Key->p_Param->CounterDebDetect +#define FOR_COUNTER_DEB_RELEASE TSC_Globals.For_Key->p_Param->CounterDebRelease +#define FOR_COUNTER_DEB_ERROR TSC_Globals.For_Key->p_Param->CounterDebError + +#if TOUCH_DTO > 0 + #define DTO_READ_TIME {TSC_TouchKey_DTOGetTime();} +#else + #define DTO_READ_TIME +#endif + +#if TOUCH_COEFF_TH > 0 + #define TEST_DELTA(OPER,TH) (FOR_DELTA OPER (uint16_t)((uint16_t)TH << TOUCH_COEFF_TH)) + #define TEST_DELTA_N(OPER,TH) (FOR_DELTA OPER -((uint16_t)((uint16_t)TH << TOUCH_COEFF_TH))) + #define TEST_DELTA_NEGATIVE {if (FOR_DELTA < 0) {return;}} +#else + #define TEST_DELTA(OPER,TH) (FOR_DELTA OPER TH) + #define TEST_DELTA_N(OPER,TH) (FOR_DELTA OPER -(TH)) + #define TEST_DELTA_NEGATIVE +#endif + +/**@} end of group TSC_TouchKey_Macros */ + +/** @defgroup TSC_TouchKey_Enumerations Enumerations + @{ +*/ + +/**@} end of group TSC_TouchKey_Enumerations */ + +/** @defgroup TSC_TouchKey_Structures Structures + @{ +*/ + +/**@} end of group TSC_TouchKey_Structures */ + +/** @defgroup TSC_TouchKey_Variables Variables + @{ +*/ + +static TSC_tNum_T CalibDiv; + +/**@} end of group TSC_TouchKey_Variables */ + +/** @defgroup TSC_TouchKey_Functions Functions + @{ +*/ + +void TSC_TouchKey_DTOGetTime(void); + +/*! + * @brief Config parameters with default values from configuration file + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_Config(void) +{ + /* Debounce counters */ + FOR_COUNTER_DEB_CALIB = TOUCH_DEBOUNCE_CALIB; +#if TOUCH_USE_PROX > 0 + FOR_COUNTER_DEB_PROX = TOUCH_DEBOUNCE_PROX; +#endif + FOR_COUNTER_DEB_DETECT = TOUCH_DEBOUNCE_DETECT; + FOR_COUNTER_DEB_RELEASE = TOUCH_DEBOUNCE_RELEASE; + FOR_COUNTER_DEB_ERROR = TOUCH_DEBOUNCE_ERROR; + + /* Thresholds */ +#if TOUCH_USE_PROX > 0 + FOR_PROXIN_TH = TOUCH_KEY_PROX_IN_TH; + FOR_PROXOUT_TH = TOUCH_KEY_PROX_OUT_TH; +#endif + FOR_DETECTIN_TH = TOUCH_KEY_DETECT_IN_TH; + FOR_DETECTOUT_TH = TOUCH_KEY_DETECT_OUT_TH; + FOR_CALIB_TH = TOUCH_KEY_CALIB_TH; + + /* Config state */ + TSC_TouchKey_ConfigCalibrationState(TOUCH_CALIB_DELAY); +} + +/*! + * @brief Process the State Machine + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_Process(void) +{ + TSC_STATEID_T stateID; + + if ((FOR_STATEID == TSC_STATEID_OFF) || (FOR_DATA_READY != 0)) + { + FOR_DATA_READY = TSC_DATA_NOT_READY; + stateID = FOR_STATEID; + +#if TOUCH_TOTAL_TOUCHKEYS > 0 + if (TSC_Globals.For_Obj->Type == TSC_OBJ_TOUCHKEY) + { + TSC_Globals.For_Key->p_SM[FOR_STATEID].StateFunc(); + } +#endif + +#if TOUCH_TOTAL_TOUCHKEYS_B > 0 + if (TSC_Globals.For_Obj->Type == TSC_OBJ_TOUCHKEYB) + { + TSC_Params.p_KeySta[FOR_STATEID].StateFunc(); + } +#endif + + /* Check if the new state has changed */ + if (FOR_STATEID != stateID) + { + FOR_CHANGE = TSC_STATE_CHANGED; + } + else + { + FOR_CHANGE = TSC_STATE_NOT_CHANGED; + } + +#if TOUCH_USE_DXS > 0 + if (FOR_STATEID == TSC_STATEID_TOUCH) + { + FOR_STATEID = TSC_STATEID_DETECT; + } + if (FOR_STATEID != TSC_STATEID_DETECT) + { + FOR_DXSLOCK = TSC_FALSE; + } +#endif + } +} + +/*! + * @brief Go in Calibration state + * + * @param delay: Delay before calibration starts (stabilization of noise filter) + * + * @retval None + */ +void TSC_TouchKey_ConfigCalibrationState(TSC_tCounter_T delay) +{ + FOR_STATEID = TSC_STATEID_CALIB; + FOR_CHANGE = TSC_STATE_CHANGED; + FOR_OBJ_STATUS = TSC_OBJ_STATUS_ON; + + if (TSC_Params.NumCalibSample == 4) + { + CalibDiv = 2; + } + else if (TSC_Params.NumCalibSample == 16) + { + CalibDiv = 4; + } + else + { + TSC_Params.NumCalibSample = 8; + CalibDiv = 3; + } + /* If a noise filter is used, the counter must be initialized to a value + * different from 0 in order to stabilize the filter. */ + FOR_COUNTER_DEB = (TSC_tCounter_T)(delay + (TSC_tCounter_T)TSC_Params.NumCalibSample); + FOR_REFER = 0; +} + +/*! + * @brief Go in Off state with sensor "off" + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ConfigOffState(void) +{ + FOR_STATEID = TSC_STATEID_OFF; + FOR_CHANGE = TSC_STATE_CHANGED; + FOR_OBJ_STATUS = TSC_OBJ_STATUS_OFF; +} + +/*! + * @brief Go in Off state with sensor in "Burst mode only" + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ConfigBurstOnlyState(void) +{ + FOR_STATEID = TSC_STATEID_OFF; + FOR_CHANGE = TSC_STATE_CHANGED; + FOR_OBJ_STATUS = TSC_OBJ_STATUS_BURST_ONLY; +} + +/*! + * @brief Return the current state identifier + * + * @param None + * + * @retval State id + */ +TSC_STATEID_T TSC_TouchKey_ReadStateId(void) +{ + return (FOR_STATEID); +} + +/*! + * @brief Return the current state mask + * + * @param None + * + * @retval State mask + */ +TSC_STATEMASK_T TSC_TouchKey_ReadStateMask(void) +{ + TSC_STATEMASK_T state_mask = TSC_STATEMASK_UNKNOWN; + +#if TOUCH_TOTAL_TOUCHKEYS > 0 + if (TSC_Globals.For_Obj->Type == TSC_OBJ_TOUCHKEY) + { + state_mask = TSC_Globals.For_Key->p_SM[FOR_STATEID].StateMask; + } +#endif + +#if TOUCH_TOTAL_TOUCHKEYS_B > 0 + if (TSC_Globals.For_Obj->Type == TSC_OBJ_TOUCHKEYB) + { + state_mask = TSC_Params.p_KeySta[FOR_STATEID].StateMask; + } +#endif + + return state_mask; +} + +/*! + * @brief Return the Change flag + * + * @param None + * + * @retval Change flag status + */ +TSC_tNum_T TSC_TouchKey_ReadChangeFlag(void) +{ + return (FOR_CHANGE); +} + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Release processing (previous state = Proximity) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebReleaseProxState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_PROX; + } + else /*!< Acquisition is OK or has NOISE */ + { + if (FOR_DELTA <= FOR_PROXOUT_TH) + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + } + } +} +#endif /*!< if TOUCH_USE_PROX > 0 */ + +/*! + * @brief Debounce Release processing (previous state = Detect) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebReleaseDetectState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_DETECT; + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( <=, FOR_DETECTOUT_TH) + { +#if TOUCH_USE_PROX > 0 + if (FOR_DELTA > FOR_PROXOUT_TH) + { + FOR_STATEID = TSC_STATEID_PROX; + return; + } +#endif + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + TEST_DELTA_NEGATIVE; + FOR_STATEID = TSC_STATEID_DETECT; + } + } +} + +/*! + * @brief Debounce Release processing (previous state = Touch) + * Same as Debounce Release Detect processing + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebReleaseTouchState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_TOUCH; + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( <=, FOR_DETECTOUT_TH) + { +#if TOUCH_USE_PROX > 0 + if (FOR_DELTA > FOR_PROXOUT_TH) + { + FOR_STATEID = TSC_STATEID_PROX; + return; + } +#endif + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + TEST_DELTA_NEGATIVE; + FOR_STATEID = TSC_STATEID_TOUCH; + } + } +} + +/*! + * @brief Release state processing + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessReleaseState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_RELEASE; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( >=, FOR_DETECTIN_TH) + { + TEST_DELTA_NEGATIVE; + FOR_COUNTER_DEB = FOR_COUNTER_DEB_DETECT; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + return; + } + +#if TOUCH_USE_PROX > 0 + if (FOR_DELTA >= FOR_PROXIN_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + return; + } +#endif + + /* Check delta for re-calibration + Warning: the threshold value is inverted in the macro */ + if TEST_DELTA_N( <=, FOR_CALIB_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_CALIB; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_CALIB; + } + else + { + TSC_TouchKey_ConfigCalibrationState(0); + } + } + } +} + +/*! + * @brief Debounce Calibration processing (previous state = Release) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebCalibrationState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else /*!< Acquisition is OK or has NOISE */ + { + /* Still below recalibration threshold + Warning: the threshold value is inverted in the macro */ + if TEST_DELTA_N( >, FOR_CALIB_TH) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + TSC_TouchKey_ConfigCalibrationState(0); + } + } + } +} + +/*! + * @brief Calibration state processing + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessCalibrationState(void) +{ + TSC_tMeas_T newMeas; + +#if TOUCH_CALIB_DELAY > 0 + /* Noise filter stabilization time */ + if (FOR_COUNTER_DEB > (TSC_tCounter_T)TSC_Params.NumCalibSample) + { + FOR_COUNTER_DEB--; + return; + } +#endif + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_CALIB; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } + else /*!< Acquisition is OK or has NOISE */ + { + /* Read the new measure or Calculate it */ +#if TOUCH_USE_MEAS > 0 + newMeas = FOR_MEAS; +#else + newMeas = TSC_Acq_ComputeMeas(FOR_REFER, FOR_DELTA); +#endif + + /* Verify the first Reference value */ + if (FOR_COUNTER_DEB != (TSC_tCounter_T)TSC_Params.NumCalibSample) + { + FOR_REFER += newMeas; + + /* Check reference overflow */ + if (FOR_REFER < newMeas) + { + FOR_REFER = 0; + FOR_STATEID = TSC_STATEID_ERROR; + return; + } + } + else + { + if (TSC_Acq_TestFirstReference(FOR_CHANNEL_DATA, newMeas)) + { + FOR_REFER = newMeas; + } + else + { + FOR_REFER = 0; + return; + } + } + + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_REFER >>= CalibDiv; + FOR_REFREST = 0; + FOR_DELTA = 0; + FOR_STATEID = TSC_STATEID_RELEASE; + } + } +} + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Proximity processing (previous state = Release) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebProxState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( >=, FOR_DETECTIN_TH) + { + TEST_DELTA_NEGATIVE; + FOR_COUNTER_DEB = FOR_COUNTER_DEB_DETECT; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + return; + } + + if (FOR_DELTA < FOR_PROXIN_TH) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } + } +} +#endif + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Proximity processing (previous state = Detect) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebProxDetectState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_DETECT; + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( >, FOR_DETECTOUT_TH) + { + TEST_DELTA_NEGATIVE; + FOR_STATEID = TSC_STATEID_DETECT; + return; + } + + if (FOR_DELTA <= FOR_PROXOUT_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } + } +} +#endif + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Debounce Proximity processing (previous state = Touch) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebProxTouchState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_TOUCH; + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( >, FOR_DETECTOUT_TH) + { + TEST_DELTA_NEGATIVE; + FOR_STATEID = TSC_STATEID_TOUCH; + return; + } + + if (FOR_DELTA <= FOR_PROXOUT_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } + else + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } + } +} +#endif + +#if TOUCH_USE_PROX > 0 +/*! + * @brief Proximity state processing + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessProxState(void) +{ +#if TOUCH_DTO > 0 + TSC_tTick_sec_T tick_detected; +#endif + + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } + else /*!< Acquisition is OK or has NOISE */ + { + if (FOR_DELTA <= FOR_PROXOUT_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + return; + } + + if TEST_DELTA( >=, FOR_DETECTIN_TH) + { + TEST_DELTA_NEGATIVE; + FOR_COUNTER_DEB = FOR_COUNTER_DEB_DETECT; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + return; + } + + /* Stay in Proximity state */ +#if TOUCH_DTO > 0 + /* Detection Time Out (DTO) processing */ + if ((TSC_Params.DTO > 1) && (TSC_Params.DTO < 64)) + { + /* Read the detected time previously saved */ + tick_detected = FOR_COUNTER_DTO; + /* Enter in calibration state if the DTO duration has elapsed */ + if (TSC_Time_Delay_sec(TSC_Params.DTO, &tick_detected) == TSC_STATUS_OK) + { + TSC_TouchKey_ConfigCalibrationState(0); + } + } +#endif + } +} +#endif + +/*! + * @brief Debounce Detect processing (previous state = Release or Proximity) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebDetectState(void) +{ + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( <, FOR_DETECTIN_TH) + { +#if TOUCH_USE_PROX > 0 + if (FOR_DELTA < FOR_PROXIN_TH) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + } +#else + FOR_STATEID = TSC_STATEID_RELEASE; +#endif + } + else + { + TEST_DELTA_NEGATIVE; + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_DETECT; + DTO_READ_TIME; + } + } + } +} + +/*! + * @brief Detect state processing + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDetectState(void) +{ +#if TOUCH_DTO > 0 + TSC_tTick_sec_T tick_detected; +#endif + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( >, FOR_DETECTOUT_TH) + { + TEST_DELTA_NEGATIVE; +#if TOUCH_DTO > 0 + /* Detection Time Out (DTO) processing */ + if ((TSC_Params.DTO > 1) && (TSC_Params.DTO < 64)) + { + /* Read the detected time previously saved */ + tick_detected = FOR_COUNTER_DTO; + /* Enter in calibration state if the DTO duration has elapsed */ + if (TSC_Time_Delay_sec(TSC_Params.DTO, &tick_detected) == TSC_STATUS_OK) + { + TSC_TouchKey_ConfigCalibrationState(0); + } + } +#endif + return; + } + +#if TOUCH_USE_PROX > 0 + if (FOR_DELTA > FOR_PROXOUT_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + return; + } +#endif + + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_DETECT; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } +} + +/*! + * @brief Touch state processing, Same as Detect state + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessTouchState(void) +{ +#if TOUCH_DTO > 0 + TSC_tTick_sec_T tick_detected; +#endif + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_ERROR; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_ERROR_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } + else /*!< Acquisition is OK or has NOISE */ + { + if TEST_DELTA( >, FOR_DETECTOUT_TH) + { + TEST_DELTA_NEGATIVE; +#if TOUCH_DTO > 0 + /* Detection Time Out (DTO) processing */ + if ((TSC_Params.DTO > 1) && (TSC_Params.DTO < 64)) + { + /* Read the detected time previously saved */ + tick_detected = FOR_COUNTER_DTO; + /* Enter in calibration state if the DTO duration has elapsed */ + if (TSC_Time_Delay_sec(TSC_Params.DTO, &tick_detected) == TSC_STATUS_OK) + { + TSC_TouchKey_ConfigCalibrationState(0); + } + } +#endif + return; + } + +#if TOUCH_USE_PROX > 0 + if (FOR_DELTA > FOR_PROXOUT_TH) + { + FOR_COUNTER_DEB = FOR_COUNTER_DEB_PROX; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_PROX_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_PROX; + DTO_READ_TIME; + } + return; + } +#endif + + FOR_COUNTER_DEB = FOR_COUNTER_DEB_RELEASE; + if (FOR_COUNTER_DEB) + { + FOR_STATEID = TSC_STATEID_DEB_RELEASE_TOUCH; + } + else + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + } +} + +/*! + * @brief Debounce error state processing + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_ProcessDebErrorState(void) +{ + volatile TSC_STATEMASK_T mask; + + /* Acquisition error (min or max) */ + if (FOR_ACQ_STATUS & TSC_ACQ_STATUS_ERROR_MASK) + { + if (FOR_COUNTER_DEB > 0) + { + FOR_COUNTER_DEB--; + } + if (FOR_COUNTER_DEB == 0) + { + FOR_STATEID = TSC_STATEID_ERROR; + } + } + else /*!< Acquisition is OK or has NOISE */ + { + mask = TSC_TouchKey_ReadStateMask(); + mask &= (TSC_STATEMASK_T)(~(TSC_STATE_DEBOUNCE_BIT_MASK | TSC_STATE_ERROR_BIT_MASK)); + + if (mask == TSC_STATEMASK_RELEASE) + { + FOR_STATEID = TSC_STATEID_RELEASE; + } + else if (mask == TSC_STATEMASK_PROX) + { + FOR_STATEID = TSC_STATEID_PROX; + } + else if (mask == TSC_STATEMASK_DETECT) + { + FOR_STATEID = TSC_STATEID_DETECT; + } + else if (mask == TSC_STATEMASK_TOUCH) + { + FOR_STATEID = TSC_STATEID_TOUCH; + } + else + { + TSC_TouchKey_ConfigCalibrationState(0); + } + } +} + +/*! + * @brief Read the current time in second and affect it to the DTO counter (Private) + * + * @param None + * + * @retval None + */ +void TSC_TouchKey_DTOGetTime(void) +{ + disableInterrupts(); + FOR_COUNTER_DTO = (TSC_tCounter_T)TSC_Globals.Tick_sec; + enableInterrupts(); +} +#endif /*!< #if TOUCH_TOTAL_KEYS > 0 */ + +/**@} end of group TSC_TouchKey_Functions */ +/**@} end of group TSC_TouchKey_Driver */ +/**@} end of group TSC_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h new file mode 100644 index 0000000000..1cf4cc4694 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h @@ -0,0 +1,85 @@ +/*! + * @file usbd_class_cdc.h + * + * @brief CDC Class handler file head file + * + * @version V1.0.0 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_CDC_CLASS_ +#define __USBD_CDC_CLASS_ + +/* Includes */ +#include "usbd_core.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup CDC + @{ +*/ + +/** @defgroup CDC_Macros Macros + @{ +*/ + +/**@} end of group CDC_Macros */ + +/** @defgroup CDC_Enumerations Enumerations + @{ +*/ + +/**@} end of group CDC_Enumerations */ + +/** @defgroup CDC_Structures Structures + @{ +*/ + +/**@} end of group CDC_Structures */ + +/** @defgroup CDC_Variables Variables + @{ +*/ + +/**@} end of group CDC_Variables */ + +/** @defgroup CDC_Functions Functions + @{ +*/ + +void USBD_ClassHandler(USBD_DevReqData_T* reqData); + +#endif + +/**@} end of group CDC_Functions */ +/**@} end of group CDC */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c new file mode 100644 index 0000000000..05c0f71371 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c @@ -0,0 +1,122 @@ +/*! + * @file usbd_class_cdc.c + * + * @brief CDC Class handler file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_class_cdc.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup CDC + @{ +*/ + +/** @defgroup CDC_Macros Macros + @{ +*/ + +/**@} end of group CDC_Macros */ + +/** @defgroup CDC_Enumerations Enumerations + @{ +*/ + +/**@} end of group CDC_Enumerations */ + +/** @defgroup CDC_Structures Structures + @{ +*/ + +/**@} end of group CDC_Structures */ + +/** @defgroup CDC_Variables Variables + @{ +*/ + +static uint8_t cmdBuf[8] = {0}; + +/**@} end of group CDC_Variables */ + +/** @defgroup CDC_Functions Functions + @{ +*/ + +/*! + * @brief USB CDC Class request handler + * + * @param reqData : point to USBD_DevReqData_T structure + * + * @retval None + */ +void USBD_ClassHandler(USBD_DevReqData_T* reqData) +{ + uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \ + reqData->byte.wLength[0] ; + + if (!length) + { + if (!reqData->byte.bmRequestType.bit.dir) + { + USBD_CtrlTxStatus(); + } + else + { + USBD_CtrlRxStatus(); + } + } + else + { + switch (reqData->byte.bRequest) + { + + case 0x20: + USBD_CtrlOutData(cmdBuf, length); + break; + case 0x21: + USBD_CtrlInData(cmdBuf, length); + break; + case 0x22: + USBD_CtrlOutData(cmdBuf, length); + break; + default: + break; + } + } +} + +/**@} end of group CDC_Functions */ +/**@} end of group CDC */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h new file mode 100644 index 0000000000..9a7278b6c6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h @@ -0,0 +1,94 @@ +/*! + * @file usbd_class_hid.h + * + * @brief HID Class handler file head file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_HID_CLASS_ +#define __USBD_HID_CLASS_ + +/* Includes */ +#include "usbd_core.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup HID + @{ +*/ + +/** @defgroup HID_Macros Macros + @{ +*/ + +#define HID_CLASS_REQ_SET_PROTOCOL 0x0B +#define HID_CLASS_REQ_GET_PROTOCOL 0x03 + +#define HID_CLASS_REQ_SET_IDLE 0x0A +#define HID_CLASS_REQ_GET_IDLE 0x02 + +#define HID_CLASS_REQ_SET_REPORT 0x09 +#define HID_CLASS_REQ_GET_REPORT 0x01 + +/**@} end of group HID_Macros */ + +/** @defgroup HID_Enumerations Enumerations + @{ +*/ + +/**@} end of group HID_Enumerations */ + +/** @defgroup HID_Structures Structures + @{ +*/ + +/**@} end of group HID_Structures */ + +/** @defgroup HID_Variables Variables + @{ +*/ + +/**@} end of group HID_Variables */ + +/** @defgroup HID_Functions Functions + @{ +*/ + +void USBD_ClassHandler(USBD_DevReqData_T* reqData); + +#endif + +/**@} end of group HID_Functions */ +/**@} end of group HID */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c new file mode 100644 index 0000000000..0a2d0c2384 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c @@ -0,0 +1,114 @@ +/*! + * @file usbd_class_hid.c + * + * @brief HID Class handler file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_class_hid.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup HID + @{ +*/ + +/** @defgroup HID_Macros Macros + @{ +*/ + +/**@} end of group HID_Macros */ + +/** @defgroup HID_Enumerations Enumerations + @{ +*/ + +/**@} end of group HID_Enumerations */ + +/** @defgroup HID_Structures Structures + @{ +*/ + +/**@} end of group HID_Structures */ + +/** @defgroup HID_Variables Variables + @{ +*/ + +static uint8_t s_hidIdleState; +static uint8_t s_hidProtocol; + +/**@} end of group HID_Variables */ + +/** @defgroup HID_Functions Functions + @{ +*/ + +/*! + * @brief USB HID Class request handler + * + * @param reqData : point to USBD_DevReqData_T structure + * + * @retval None + */ +void USBD_ClassHandler(USBD_DevReqData_T* reqData) +{ + switch (reqData->byte.bRequest) + { + case HID_CLASS_REQ_SET_IDLE: + s_hidIdleState = reqData->byte.wValue[1]; + USBD_CtrlInData(NULL, 0); + break; + + case HID_CLASS_REQ_GET_IDLE: + USBD_CtrlInData(&s_hidIdleState, 1); + break; + + case HID_CLASS_REQ_SET_PROTOCOL: + s_hidProtocol = reqData->byte.wValue[0]; + USBD_CtrlInData(NULL, 0); + break; + + case HID_CLASS_REQ_GET_PROTOCOL: + USBD_CtrlInData(&s_hidProtocol, 1); + break; + + default: + break; + } +} + +/**@} end of group HID_Functions */ +/**@} end of group HID */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h new file mode 100644 index 0000000000..12425200c5 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h @@ -0,0 +1,88 @@ +/*! + * @file usbd_class_msc.h + * + * @brief MSC Class handler file head file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __CLASS_MSC_ +#define __CLASS_MSC_ + +/* Includes */ +#include "usbd_core.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup MSC + @{ +*/ + +/** @defgroup MSC_Macros Macros + @{ +*/ + +#define BOT_GET_MAX_LUN 0xFE +#define BOT_RESET 0xFF + +/**@} end of group MSC_Macros */ + +/** @defgroup MSC_Enumerations Enumerations + @{ +*/ + +/**@} end of group MSC_Enumerations */ + +/** @defgroup MSC_Structures Structures + @{ +*/ + +/**@} end of group MSC_Structures */ + +/** @defgroup MSC_Variables Variables + @{ +*/ + +/**@} end of group MSC_Variables */ + +/** @defgroup MSC_Functions Functions + @{ +*/ + +void USBD_MSC_ClassHandler(USBD_DevReqData_T* reqData); + +#endif + +/**@} end of group MSC_Functions */ +/**@} end of group MSC */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h new file mode 100644 index 0000000000..0f82d7fe6d --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h @@ -0,0 +1,156 @@ +/*! + * @file usbd_msc_bot.h + * + * @brief MSC BOT protocol core functions + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_MSC_BOT_H +#define __USBD_MSC_BOT_H + +/* Includes */ +#include "usbd_core.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup MSC_BOT + @{ +*/ + +/** @defgroup MSC_BOT_Macros Macros + @{ +*/ + +#define MSC_BOT_CBW_SIGNATURE (uint32_t)(0x43425355) +#define MSC_BOT_CBW_LENGTH 31 + +#define MSC_BOT_CSW_SIGNATURE (uint32_t)(0x53425355) +#define MSC_BOT_CSW_LENGTH 13 + +/**@} end of group MSC_BOT_Macros */ + +/** @defgroup MSC_BOT_Enumerations Enumerations + @{ +*/ + +typedef enum +{ + BOT_STATE_IDLE, /*!< Idle state */ + BOT_STATE_DATA_OUT, /*!< Data Out state */ + BOT_STATE_DATA_IN, /*!< Data In state */ + BOT_STATE_LAST_DATA_IN, /*!< Last Data In Last */ + BOT_STATE_SEND_DATA /*!< Send Immediate data */ +} BOT_STATE_T; + +typedef enum +{ + BOT_STATUS_NORMAL, + BOT_STATUS_RECOVERY, + BOT_STATUS_ERROR +} BOT_STATUS_T; + +typedef enum +{ + BOT_CSW_STATUS_CMD_OK, + BOT_CSW_STATUS_CMD_FAIL, + BOT_CSW_STATUS_PHASE_ERROR +} BOT_CSW_STATUS_T; + +/**@} end of group MSC_BOT_Enumerations */ + +/** @defgroup MSC_BOT_Structures Structures + @{ +*/ + +/** + * @brief Command Block Wrapper + */ +typedef struct +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataXferLen; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLen; + uint8_t CB[16]; +} BOT_CBW_T; + +/** + * @brief Command Status Wrapper + */ +typedef struct +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} BOT_CSW_T; + +typedef struct +{ + uint8_t state; + uint8_t status; + uint16_t dataLen; + BOT_CBW_T CBW; + BOT_CSW_T CSW; + uint8_t data[MSC_MEDIA_PACKET]; +} BOT_Info_T; + +/**@} end of group MSC_BOT_Structures */ + +/** @defgroup MSC_BOT_Variables Variables + @{ +*/ + +extern BOT_Info_T g_BOTInfo; + +/**@} end of group MSC_BOT_Variables */ + +/** @defgroup MSC_BOT_Functions Functions + @{ +*/ + +void USBD_MSC_BOT_Reset(void); +void USBD_MSC_BOT_Init(void); +void USBD_MSC_BOT_OutData(uint8_t ep); +void USBD_MSC_BOT_InData(uint8_t ep); +void USBD_MSC_BOT_TxCSW(uint8_t cswStatus); +void USBD_MSV_BOT_ClearFeatureHandler(void); + +#endif /*__USBD_MSC_BOT_H */ + +/**@} end of group MSC_BOT_Functions */ +/**@} end of group MSC_BOT_ */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h new file mode 100644 index 0000000000..92140d4c85 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h @@ -0,0 +1,183 @@ +/*! + * @file usbd_msc_scsi.h + * + * @brief MSC scsi + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_MSC_SCSI_H_ +#define __USBD_MSC_SCSI_H_ + +/* Includes */ +#include "usbd_core.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup MSC_SCSI + @{ +*/ + +/** @defgroup MSC_SCSI_Macros Macros + @{ +*/ + +#define SCSI_SENSE_LIST_NUMBER 4 +#define SCSI_INQUIRY_LENGTH 36 + +/* SCSI Commands */ +#define SCSI_CMD_FORMAT_UNIT ((uint8_t)0x04) +#define SCSI_CMD_INQUIRY ((uint8_t)0x12) +#define SCSI_CMD_MODE_SELECT_6 ((uint8_t)0x15) +#define SCSI_CMD_MODE_SELECT_10 ((uint8_t)0x55) +#define SCSI_CMD_MODE_SENSE_6 ((uint8_t)0x1A) +#define SCSI_CMD_MODE_SENSE_10 ((uint8_t)0x5A) +#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL ((uint8_t)0x1E) +#define SCSI_CMD_READ_6 ((uint8_t)0x08) +#define SCSI_CMD_READ_10 ((uint8_t)0x28) +#define SCSI_CMD_READ_12 ((uint8_t)0xA8) +#define SCSI_CMD_READ_16 ((uint8_t)0x88) + +#define SCSI_CMD_READ_CAPACITY_10 ((uint8_t)0x25) +#define SCSI_CMD_READ_CAPACITY_16 ((uint8_t)0x9E) + +#define SCSI_CMD_REQUEST_SENSE ((uint8_t)0x03) +#define SCSI_CMD_START_STOP_UNIT ((uint8_t)0x1B) +#define SCSI_CMD_TEST_UNIT_READY ((uint8_t)0x00) +#define SCSI_CMD_WRITE6 ((uint8_t)0x0A) +#define SCSI_CMD_WRITE10 ((uint8_t)0x2A) +#define SCSI_CMD_WRITE12 ((uint8_t)0xAA) +#define SCSI_CMD_WRITE16 ((uint8_t)0x8A) + +#define SCSI_CMD_VERIFY_10 ((uint8_t)0x2F) +#define SCSI_CMD_VERIFY_12 ((uint8_t)0xAF) +#define SCSI_CMD_VERIFY_16 ((uint8_t)0x8F) + +#define SCSI_CMD_SEND_DIAGNOSTIC ((uint8_t)0x1D) +#define SCSI_CMD_READ_FORMAT_CAPACITIES ((uint8_t)0x23) + +#define SCSI_ASC_INVALID_CDB 0x20 +#define SCSI_ASC_INVALID_FIELED_IN_COMMAND 0x24 +#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR 0x1A +#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST 0x26 +#define SCSI_ASC_ADDRESS_OUT_OF_RANGE 0x21 +#define SCSI_ASC_MEDIUM_NOT_PRESENT 0x3A +#define SCSI_ASC_MEDIUM_HAVE_CHANGED 0x28 +#define SCSI_ASC_WRITE_PROTECTED 0x27 +#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 +#define SCSI_ASC_WRITE_FAULT 0x03 + +#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN 0x0C +#define SCSI_READ_CAPACITY10_DATA_LEN 0x08 +#define SCSI_MODE_SENSE10_DATA_LEN 0x08 +#define SCSI_MODE_SENSE6_DATA_LEN 0x04 +#define SCSI_REQUEST_SENSE_DATA_LEN 0x12 +#define SCSI_STANDARD_INQUIRY_DATA_LEN 0x24 +#define SCSI_BLKVFY 0x04 + +/**@} end of group MSC_SCSI_Macros */ + +/** @defgroup MSC_SCSI_Enumerations Enumerations + @{ +*/ + +/** + * @brief SCSI function status + */ +typedef enum +{ + SCSI_FAIL, + SCSI_OK, +} SCSI_STATUS_T; + +/** + * @brief SCSI Sense Key + */ +typedef enum +{ + SCSI_SKEY_NO_SENSE, + SCSI_SKEY_RECOVERED_ERROR, + SCSI_SKEY_NOT_READY, + SCSI_SKEY_MEDIUM_ERROR, + SCSI_SKEY_HARDWARE_ERROR, + SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_SKEY_UNIT_ATTENTION, + SCSI_SKEY_DATA_PROTECT, + SCSI_SKEY_BLANK_CHECK, + SCSI_SKEY_VENDOR_SPECIFIC, + SCSI_SKEY_COPY_ABORTED, + SCSI_SKEY_ABORTED_COMMAND, + SCSI_SKEY_VOLUME_OVERFLOW = 13, + SCSI_SKEY_MISCOMPARE = 14 +} SCSI_SKEY_T; + +/**@} end of group MSC_SCSI_Enumerations */ + +/** @defgroup MSC_SCSI_Structures Structures + @{ +*/ + +/** + * @brief SCSI Sense + */ +typedef struct +{ + uint8_t sensekey; + uint8_t ASC; + uint8_t ASCQ; +} SCSI_Sense_T; + +/**@} end of group MSC_SCSI_Structures */ + +/** @defgroup MSC_SCSI_Variables Variables + @{ +*/ + +extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER]; +extern uint8_t g_senseTxCnt; +extern uint8_t g_sensePutCnt; + +/**@} end of group MSC_SCSI_Variables */ + +/** @defgroup MSC_SCSI_Functions Functions + @{ +*/ + +uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t* cmd); +void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ); + +#endif + +/**@} end of group MSC_SCSI_Functions */ +/**@} end of group MSC_SCSI */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c new file mode 100644 index 0000000000..4df2621207 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c @@ -0,0 +1,130 @@ +/*! + * @file usbd_class_msc.c + * + * @brief MSC Class file + * + * @version V1.0.0 + * + * @date 2021-12-06 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_class_msc.h" +#include "usbd_msc_bot.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup MSC + @{ +*/ + +/** @defgroup MSC_Macros Macros + @{ +*/ + +/**@} end of group MSC_Macros */ + +/** @defgroup MSC_Enumerations Enumerations + @{ +*/ + +/**@} end of group MSC_Enumerations */ + +/** @defgroup MSC_Structures Structures + @{ +*/ + +/**@} end of group MSC_Structures */ + +/** @defgroup MSC_Variables Variables + @{ +*/ + +static uint8_t s_mscMaxLen = 0; + +/**@} end of group MSC_Variables */ + +/** @defgroup MSC_Functions Functions + @{ +*/ + +/*! + * @brief USB MSC Class request handler + * + * @param reqData : point to USBD_DevReqData_T structure + * + * @retval None + */ +void USBD_MSC_ClassHandler(USBD_DevReqData_T* reqData) +{ + uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \ + reqData->byte.wValue[0]; + uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \ + reqData->byte.wLength[0]; + + switch (reqData->byte.bRequest) + { + case BOT_GET_MAX_LUN : + if ((wValue == 0) && (wLength == 1) && \ + (reqData->byte.bmRequestType.bit.dir == 1)) + { + s_mscMaxLen = STORAGE_MAX_LUN - 1; + + USBD_CtrlInData(&s_mscMaxLen, 1); + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + break; + case BOT_RESET : + if ((wValue == 0) && (wLength == 0) && \ + (reqData->byte.bmRequestType.bit.dir == 0)) + { + USBD_CtrlInData(NULL, 0); + /* Reset */ + USBD_MSC_BOT_Reset(); + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + + break; + + default: + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + break; + } +} + +/**@} end of group MSC_Functions */ +/**@} end of group MSC */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c new file mode 100644 index 0000000000..254a0a8884 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c @@ -0,0 +1,292 @@ +/*! + * @file usbd_msv_bot.c + * + * @brief MSC BOT protocol core functions + * + * @version V1.0.0 + * + * @date 2021-12-25 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_msc_bot.h" +#include "usbd_core.h" +#include "usbd_storage_disk.h" +#include "usbd_msc_scsi.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup MSC_BOT + @{ +*/ + +/** @defgroup MSC_BOT_Macros Macros + @{ +*/ + +/**@} end of group MSC_BOT_Macros */ + +/** @defgroup MSC_BOT_Enumerations Enumerations + @{ +*/ + +/**@} end of group MSC_BOT_Enumerations */ + +/** @defgroup MSC_BOT_Structures Structures + @{ +*/ + +/**@} end of group MSC_BOT_Structures */ + +/** @defgroup MSC_BOT_Variables Variables + @{ +*/ + +BOT_Info_T g_BOTInfo; + +/**@} end of group MSC_BOT_Variables */ + +/** @defgroup MSC_BOT_Functions Functions + @{ +*/ + +static void USBD_MSC_BOT_DecodeCBW(void); +static void USBD_MSC_BOT_TxData(uint8_t* txBuf, uint16_t len); +static void USBD_MSC_BOT_Stall(void); + +/*! + * @brief BOT Process Reset. + * + * @param None + * + * @retval None + */ +void USBD_MSC_BOT_Reset(void) +{ + g_BOTInfo.state = BOT_STATE_IDLE; + g_BOTInfo.status = BOT_STATUS_RECOVERY; + + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t*)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH); +} + +/*! + * @brief BOT Process initialization. + * + * @param None + * + * @retval None + */ +void USBD_MSC_BOT_Init(void) +{ + g_BOTInfo.state = BOT_STATE_IDLE; + g_BOTInfo.status = BOT_STATUS_NORMAL; + + g_storageCallBack.Init(0); + + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t*)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH); +} + +/*! + * @brief Bulk OUT data handler. + * + * @param ep : OUT endpoint + * + * @retval None + */ +void USBD_MSC_BOT_OutData(uint8_t ep) +{ + if (g_BOTInfo.state == BOT_STATE_IDLE) + { + USBD_MSC_BOT_DecodeCBW(); + } + else if (g_BOTInfo.state == BOT_STATE_DATA_OUT) + { + if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL); + } + } +} + +/*! + * @brief Bulk IN data handler. + * + * @param ep : IN endpoint + * + * @retval None + */ +void USBD_MSC_BOT_InData(uint8_t ep) +{ + if (g_BOTInfo.state == BOT_STATE_DATA_IN) + { + if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL); + } + } + else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \ + (g_BOTInfo.state == BOT_STATE_LAST_DATA_IN)) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK); + } +} + +/*! + * @brief Decode CBW. + * + * @param None + * + * @retval None + */ +static void USBD_MSC_BOT_DecodeCBW(void) +{ + uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt; + + g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag; + g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen; + + if ((xferCnt != MSC_BOT_CBW_LENGTH) || \ + (g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \ + (g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \ + (g_BOTInfo.CBW.bCBLen > 16)) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + g_BOTInfo.status = BOT_STATUS_ERROR; + } + else + { + if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK) + { + USBD_MSC_BOT_Stall(); + } + else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \ + (g_BOTInfo.state == BOT_STATE_SEND_DATA)) + { + if (g_BOTInfo.dataLen) + { + USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen); + } + else + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK); + } + } + } +} + +/*! + * @brief MSC send data. + * + * @param txBuf : buffer to send + * + * @param len : buffer length + * + * @retval None + */ +static void USBD_MSC_BOT_TxData(uint8_t* txBuf, uint16_t len) +{ + len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen); + + g_BOTInfo.CSW.dDataResidue -= len; + g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK; + g_BOTInfo.state = BOT_STATE_SEND_DATA; + + USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len); +} + +/*! + * @brief Send CSW. + * + * @param cswStatus : status of CSW + * + * @retval None + */ +void USBD_MSC_BOT_TxCSW(uint8_t cswStatus) +{ + g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE; + g_BOTInfo.CSW.bStatus = cswStatus; + g_BOTInfo.state = BOT_STATE_IDLE; + + USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t*)&g_BOTInfo.CSW, + MSC_BOT_CSW_LENGTH); + + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t*)&g_BOTInfo.CBW, + MSC_BOT_CBW_LENGTH); +} + +/*! + * @brief handler clearFeature in standard request. + * + * @param None + * + * @retval None + */ +void USBD_MSV_BOT_ClearFeatureHandler(void) +{ + if (g_BOTInfo.status == BOT_STATUS_ERROR) + { + USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK); + g_BOTInfo.status = BOT_STATUS_NORMAL; + } + else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \ + g_BOTInfo.status != BOT_STATUS_RECOVERY) + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL); + } +} + +/*! + * @brief Stall MSC. + * + * @param None + * + * @retval None + */ +static void USBD_MSC_BOT_Stall(void) +{ + if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \ + (g_BOTInfo.status == BOT_STATUS_NORMAL)) + { + USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL); + } + + USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL); + + if (g_BOTInfo.status == BOT_STATUS_ERROR) + { + USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t*)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH); + } +} + +/**@} end of group MSC_BOT_Functions */ +/**@} end of group MSC_BOT_ */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c new file mode 100644 index 0000000000..d896602681 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c @@ -0,0 +1,752 @@ +/*! + * @file usbd_msc_scsi.c + * + * @brief MSC scsi + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_storage_disk.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Class + @{ +*/ + +/** @addtogroup MSC_SCSI + @{ +*/ + +/** @defgroup MSC_SCSI_Macros Macros + @{ +*/ + +/**@} end of group MSC_SCSI_Macros */ + +/** @defgroup MSC_SCSI_Enumerations Enumerations + @{ +*/ + +/**@} end of group MSC_SCSI_Enumerations */ + +/** @defgroup MSC_SCSI_Structures Structures + @{ +*/ + +/**@} end of group MSC_SCSI_Structures */ + +/** @defgroup MSC_SCSI_Variables Variables + @{ +*/ + +SCSI_Sense_T g_scsiSenseCode[SCSI_SENSE_LIST_NUMBER]; +uint8_t g_senseTxCnt; +uint8_t g_sensePutCnt; + +static uint32_t s_blkSize; +static uint32_t s_blkNbr; + +static uint32_t s_blkAddr; +static uint32_t s_blkLen; + +/* USB Mass storage Page 0 Inquiry Data */ +static const uint8_t s_page00InquiryData[] = +{ + 0x00, + 0x00, + 0x00, + (7 - 4), + 0x00, + 0x80, + 0x83 +}; +/* USB Mass storage sense 6 Data */ +static const uint8_t s_modeSense6Data[] = +{ + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/* USB Mass storage sense 10 Data */ +static const uint8_t s_modeSense10Data[] = +{ + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; + +/**@} end of group MSC_SCSI_Variables */ + +/** @defgroup MSC_SCSI_Functions Functions + @{ +*/ + +static uint8_t SCSI_TestUnitReady(uint8_t lun); +static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t* command); +static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t* command); + +static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t* command); +static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t* command); +static uint8_t SCSI_Read10(uint8_t lun, uint8_t* command); +static uint8_t SCSI_Write10(uint8_t lun, uint8_t* command); +static uint8_t SCSI_Verify10(uint8_t lun, uint8_t* command); + +static uint8_t SCSI_StartStopUnit(void); +static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t* command); +static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t* command); + +static uint8_t SCSI_Read(uint8_t lun); +static uint8_t SCSI_Write(uint8_t lun); +static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr); + +/*! + * @brief SCSI command handler. + * + * @param lun: Logical unit number + * + * @param command: Command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t* command) +{ + uint8_t ret = SCSI_OK; + + switch (command[0]) + { + case SCSI_CMD_TEST_UNIT_READY: + ret = SCSI_TestUnitReady(lun); + break; + + case SCSI_CMD_INQUIRY: + ret = SCSI_Inquiry(lun, command); + break; + + case SCSI_CMD_REQUEST_SENSE: + ret = SCSI_RequestSense(lun, command); + break; + + case SCSI_CMD_READ_FORMAT_CAPACITIES: + ret = SCSI_ReadFormatCapacity(lun, command); + break; + + case SCSI_CMD_READ_CAPACITY_10: + ret = SCSI_ReadCapacity10(lun, command); + break; + + case SCSI_CMD_READ_10: + ret = SCSI_Read10(lun, command); + break; + + case SCSI_CMD_WRITE10: + ret = SCSI_Write10(lun, command); + break; + + case SCSI_CMD_VERIFY_10: + ret = SCSI_Verify10(lun, command); + break; + case SCSI_CMD_ALLOW_MEDIUM_REMOVAL: + case SCSI_CMD_START_STOP_UNIT: + ret = SCSI_StartStopUnit(); + break; + + case SCSI_CMD_MODE_SENSE_6: + ret = SCSI_ModeSense6(lun, command); + break; + + case SCSI_CMD_MODE_SENSE_10: + ret = SCSI_ModeSense10(lun, command); + break; + + default: + SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + ret = SCSI_FAIL; + } + + return ret; +} + +/*! + * @brief Put the sense code to array. + * + * @param sKey: sense Key + * + * @param ASC: Additional Sense Code + * + * @param ASCQ: Additional Sense Code Qualifier + * + * @retval None + */ +void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ) +{ + g_scsiSenseCode[g_sensePutCnt].sensekey = sKey; + g_scsiSenseCode[g_sensePutCnt].ASC = ASC; + g_scsiSenseCode[g_sensePutCnt].ASCQ = ASCQ; + + if ((++g_sensePutCnt) == SCSI_SENSE_LIST_NUMBER) + { + g_sensePutCnt = 0; + } +} + +/*! + * @brief SCSI Test Unit Ready handler. + * + * @param lun: Logical unit number + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_TestUnitReady(uint8_t lun) +{ + if (g_BOTInfo.CBW.dDataXferLen) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + else if (g_storageCallBack.CheckReady(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + else + { + g_BOTInfo.dataLen = 0; + return SCSI_OK; + } +} + +/*! + * @brief SCSI Inquiry handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t* command) +{ + uint16_t i; + uint8_t* pInquiryData; + + if (command[1] & 0x01) + { + pInquiryData = (uint8_t*)s_page00InquiryData; + g_BOTInfo.dataLen = s_page00InquiryData[3] + 4; + } + else + { + pInquiryData = &g_storageCallBack.pInquiryData[lun * SCSI_INQUIRY_LENGTH]; + + g_BOTInfo.dataLen = USB_MIN((pInquiryData[4] + 5), command[4]); + } + + for (i = 0; i < g_BOTInfo.dataLen; i++) + { + g_BOTInfo.data[i] = pInquiryData[i]; + } + + return SCSI_OK; +} + +/*! + * @brief SCSI Request Sense handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t* command) +{ + uint8_t i = 0; + + while (i < SCSI_REQUEST_SENSE_DATA_LEN) + { + g_BOTInfo.data[i++] = 0; + } + + g_BOTInfo.data[0] = 0x70; + g_BOTInfo.data[7] = SCSI_REQUEST_SENSE_DATA_LEN - 6; + + if (g_senseTxCnt != g_sensePutCnt) + { + g_BOTInfo.data[2] = g_scsiSenseCode[g_senseTxCnt].sensekey; + g_BOTInfo.data[12] = g_scsiSenseCode[g_senseTxCnt].ASC; + g_BOTInfo.data[13] = g_scsiSenseCode[g_senseTxCnt].ASCQ; + + if ((++g_senseTxCnt) == SCSI_SENSE_LIST_NUMBER) + { + g_senseTxCnt = 0; + } + } + + g_BOTInfo.dataLen = (SCSI_REQUEST_SENSE_DATA_LEN < command[4]) ? \ + SCSI_REQUEST_SENSE_DATA_LEN : command[4]; + + return SCSI_OK; +} + +/*! + * @brief SCSI Read Format Capacity handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t* command) +{ + uint16_t i = 0; + uint32_t blkSize; + uint32_t blkNbr; + + while (i < 12) + { + g_BOTInfo.data[i++] = 0; + } + + if (g_storageCallBack.ReadCapacity(lun, &blkNbr, &blkSize) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + else + { + blkNbr--; + + g_BOTInfo.data[3] = 0x08; + g_BOTInfo.data[4] = (uint8_t)(blkNbr >> 24); + g_BOTInfo.data[5] = (uint8_t)(blkNbr >> 16); + g_BOTInfo.data[6] = (uint8_t)(blkNbr >> 8); + g_BOTInfo.data[7] = (uint8_t)(blkNbr); + g_BOTInfo.data[8] = 0x02; + g_BOTInfo.data[9] = (uint8_t)(blkSize >> 16); + g_BOTInfo.data[10] = (uint8_t)(blkSize >> 8); + g_BOTInfo.data[11] = (uint8_t)blkSize; + + g_BOTInfo.dataLen = 12; + + return SCSI_OK; + } +} + +/*! + * @brief SCSI Read Capacity10 handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t* command) +{ + if (g_storageCallBack.ReadCapacity(lun, &s_blkNbr, &s_blkSize) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + else + { + g_BOTInfo.data[0] = (uint8_t)((s_blkNbr - 1) >> 24); + g_BOTInfo.data[1] = (uint8_t)((s_blkNbr - 1) >> 16); + g_BOTInfo.data[2] = (uint8_t)((s_blkNbr - 1) >> 8); + g_BOTInfo.data[3] = (uint8_t)(s_blkNbr - 1); + g_BOTInfo.data[4] = (uint8_t)(s_blkSize >> 24); + g_BOTInfo.data[5] = (uint8_t)(s_blkSize >> 16); + g_BOTInfo.data[6] = (uint8_t)(s_blkSize >> 8); + g_BOTInfo.data[7] = (uint8_t)(s_blkSize); + + g_BOTInfo.dataLen = 8; + + return SCSI_OK; + } +} + +/*! + * @brief SCSI Read10 handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Read10(uint8_t lun, uint8_t* command) +{ + uint8_t ret = SCSI_OK; + + if (g_BOTInfo.state == BOT_STATE_IDLE) + { + if ((g_BOTInfo.CBW.bmFlags & 0x80) != 0x80) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + if (g_storageCallBack.CheckReady(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + + s_blkAddr = ((uint32_t)command[2] << 24) | \ + ((uint32_t)command[3] << 16) | \ + ((uint32_t)command[4] << 8) | \ + (uint32_t)command[5]; + + s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]); + + if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK) + { + return SCSI_FAIL; + } + + g_BOTInfo.state = BOT_STATE_DATA_IN; + s_blkAddr *= s_blkSize; + s_blkLen *= s_blkSize; + + if (g_BOTInfo.CBW.dDataXferLen != s_blkLen) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + } + + g_BOTInfo.dataLen = MSC_MEDIA_PACKET; + + ret = SCSI_Read(lun); + + return ret; +} + +/*! + * @brief SCSI write10 handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Write10(uint8_t lun, uint8_t* command) +{ + uint8_t ret = SCSI_OK; + uint32_t len; + + if (g_BOTInfo.state == BOT_STATE_IDLE) + { + if (g_BOTInfo.CBW.bmFlags & 0x80) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + if (g_storageCallBack.CheckReady(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_MEDIUM_NOT_PRESENT, 0); + + return SCSI_FAIL; + } + + if (g_storageCallBack.CheckWPR(lun) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY, + SCSI_ASC_WRITE_PROTECTED, 0); + + return SCSI_FAIL; + } + + s_blkAddr = ((uint32_t)command[2] << 24) | \ + ((uint32_t)command[3] << 16) | \ + ((uint32_t)command[4] << 8) | \ + (uint32_t)command[5]; + + s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]); + + if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK) + { + return SCSI_FAIL; + } + + s_blkAddr *= s_blkSize; + s_blkLen *= s_blkSize; + + if (g_BOTInfo.CBW.dDataXferLen != s_blkLen) + { + SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_CDB, 0); + + return SCSI_FAIL; + } + + g_BOTInfo.state = BOT_STATE_DATA_OUT; + len = USB_MIN(s_blkLen, MSC_MEDIA_PACKET); + + USBD_RxData(MSC_OUT_EP & 0x7F, g_BOTInfo.data, len); + + } + else + { + ret = SCSI_Write(lun); + } + + return ret; +} + +/*! + * @brief SCSI Verify10 Handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Verify10(uint8_t lun, uint8_t* command) +{ + if (command[1] & 0x02) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_INVALID_FIELED_IN_COMMAND, 0); + + return SCSI_FAIL; + } + + s_blkAddr = ((uint32_t)command[2] << 24) | \ + ((uint32_t)command[3] << 16) | \ + ((uint32_t)command[4] << 8) | \ + (uint32_t)command[5]; + + s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]); + + if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK) + { + return SCSI_FAIL; + } + + g_BOTInfo.dataLen = 0; + + return SCSI_OK; +} + +/*! + * @brief SCSI Start Stop Unit Handler. + * + * @param None + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_StartStopUnit(void) +{ + g_BOTInfo.dataLen = 0; + return SCSI_OK; +} + +/*! + * @brief SCSI Mode Sense6 Handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t* command) +{ + for (uint16_t i = 0; i < 8; i++) + { + g_BOTInfo.data[i] = s_modeSense6Data[i]; + } + + g_BOTInfo.dataLen = 8; + + return SCSI_OK; +} + +/*! + * @brief SCSI Mode Sense10 Handler. + * + * @param lun: Logical unit number + * + * @param command: command pointer + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t* command) +{ + for (uint16_t i = 0; i < 8; i++) + { + g_BOTInfo.data[i] = s_modeSense10Data[i]; + } + + g_BOTInfo.dataLen = 8; + + return SCSI_OK; +} + +/*! + * @brief SCSI Read Process. + * + * @param lun: Logical unit number + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Read(uint8_t lun) +{ + uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen); + + if (g_storageCallBack.ReadData(len, g_BOTInfo.data, (s_blkAddr / s_blkSize), + (len / s_blkSize)) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, + SCSI_ASC_UNRECOVERED_READ_ERROR, 0); + + return SCSI_FAIL; + } + + USBD_TxData(MSC_IN_EP & 0x7F, g_BOTInfo.data, len); + + s_blkAddr += len; + s_blkLen -= len; + + g_BOTInfo.CSW.dDataResidue -= len; + + if (s_blkLen == 0) + { + g_BOTInfo.state = BOT_STATE_LAST_DATA_IN; + } + + return SCSI_OK; +} + +/*! + * @brief SCSI Write Process. + * + * @param lun: Logical unit number + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_Write(uint8_t lun) +{ + uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen); + + if (s_blkLen - len) + { + __NOP(); + } + if (g_storageCallBack.WriteData(lun, g_BOTInfo.data, s_blkAddr / s_blkSize, + len / s_blkSize) != SCSI_OK) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT, 0); + + return SCSI_FAIL; + } + + s_blkAddr += len; + s_blkLen -= len; + + g_BOTInfo.CSW.dDataResidue -= len; + + if (s_blkLen) + { + len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen); + + USBD_RxData(MSC_OUT_EP & 0x7f, g_BOTInfo.data, len); + } + else + { + USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK); + } + + return SCSI_OK; +} + +/*! + * @brief SCSI Check Address Range. + * + * @param lun: Logical unit number + * + * @param blkOffset: first block address + * + * @param blkNbr: number of block to be processed + * + * @retval SCSI_OK or SCSI_FAILL + */ +static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr) +{ + if (s_blkNbr < (blkNbr + blkOffset)) + { + SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST, + SCSI_ASC_ADDRESS_OUT_OF_RANGE, 0); + + return SCSI_FAIL; + } + + return SCSI_OK; +} + +/**@} end of group MSC_SCSI_Functions */ +/**@} end of group MSC_SCSI */ +/**@} end of group Class */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h new file mode 100644 index 0000000000..0bb68804e0 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h @@ -0,0 +1,366 @@ +/*! + * @file usbd_core.h + * + * @brief USB protocol core handler head file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_CORE_H_ +#define __USBD_CORE_H_ + +/* Includes */ +#include "drv_usb_device.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup Core + @{ +*/ + +/** @defgroup Core_Macros Macros + @{ +*/ + +/* Get minimum value */ +#define USB_MIN(a, b) (a >= b ? b : a) + +/* Get maximum value */ +#define USB_MAX(a, b) (a >= b ? a : b) + +/* control status function */ +#define USBD_CtrlTxStatus() USBD_CtrlInData(NULL, 0) +#define USBD_CtrlRxStatus() USBD_CtrlOutData(NULL, 0) + +/**@} end of group Core_Macros */ + +/** @defgroup Core_Enumerations Enumerations + @{ +*/ + +/** + * @brief USB request type + */ +enum +{ + USBD_REQ_TYPE_STANDARD = 0, + USBD_REQ_TYPE_CLASS = 1, + USBD_REQ_TYPE_VENDOR = 2, + USBD_REQ_TYPE_RESERVED = 3 +}; + +/** + * @brief USB recipient + */ +enum +{ + USBD_RECIPIENT_DEVICE = 0, + USBD_RECIPIENT_INTERFACE = 1, + USBD_RECIPIENT_ENDPOINT = 2, + USBD_RECIPIENT_OTHER = 3, +}; + +/** + * @brief USB standard device requests + */ +enum +{ + USBD_GET_STATUS = 0, + USBD_CLEAR_FEATURE = 1, + USBD_SET_FEATURE = 3, + USBD_SET_ADDRESS = 5, + USBD_GET_DESCRIPTOR = 6, + USBD_SET_DESCRIPTOR = 7, + USBD_GET_CONFIGURATION = 8, + USBD_SET_CONFIGURATION = 9, + USBD_GET_INTERFACE = 10, + USBD_SET_INTERFACE = 11, + USBD_SYNCH_FRAME = 12, +}; + +/** + * @brief USB descriptor types + */ +enum +{ + USBD_DESC_DEVICE = 1, + USBD_DESC_CONFIGURATION = 2, + USBD_DESC_STRING = 3, + USBD_DESC_INTERFACE = 4, + USBD_DESC_ENDPOINT = 5, + USBD_DESC_DEVICE_QUALIFIER = 6, + USBD_DESC_OTHER_SPEED = 7, + USBD_INTERFACE_POWER = 8, +}; + +/** + * @brief USB standard feature + */ +enum +{ + USBD_FEATURE_ENDPOINT_HALT = 0, + USBD_FEATURE_REMOTE_WAKEUP = 1, + USBD_FEATURE_TEST_MODE = 2 +}; + +/** + * @brief USB internal state machine + */ +typedef enum +{ + USBD_CTRL_STATE_WAIT_SETUP, + USBD_CTRL_STATE_DATA_IN, + USBD_CTRL_STATE_DATA_OUT, + USBD_CTRL_STATE_WAIT_STATUS_IN, + USBD_CTRL_STATE_WAIT_STATUS_OUT, + USBD_CTRL_STATE_STALLED, +} USBD_CTRL_STATE_T; + +/** + * @brief USBD Endpoint type for USB protocol + */ +typedef enum +{ + USBD_EP_TYPE_CONTROL, + USBD_EP_TYPE_ISO, + USBD_EP_TYPE_BULK, + USBD_EP_TYPE_INTERRUPT +} USBD_EP_TYPE_T; + +/**@} end of group Core_Enumerations */ + +/** @defgroup Core_Structures Structures + @{ +*/ + +/** + * @brief USB request type + */ +typedef union +{ + uint8_t byte; + + struct + { + uint8_t recipient : 5; + uint8_t type : 2; + uint8_t dir : 1; + } bit; +} USBD_REQ_TYPE_T; + +/** + * @brief USB device request data + */ +typedef struct +{ + union + { + uint8_t pack[8]; + + struct + { + USBD_REQ_TYPE_T bmRequestType; + uint8_t bRequest; + uint8_t wValue[2]; + uint8_t wIndex[2]; + uint8_t wLength[2]; + } byte; + }; +} USBD_DevReqData_T; + + +/* USB standard request callback handler */ +typedef void (*USBD_StdReqHandler_T)(void); + +/* USB request handler */ +typedef void (*USBD_ReqHandler_T)(USBD_DevReqData_T*); + +/* Ctrl Tx Status handler function define */ +typedef void (*USBD_CtrlTxStatusHandler_T)(void); + +/* Ctrl Rx Status handler function define */ +typedef void (*USBD_CtrlRxStatusHandler_T)(void); + +/* Endpoint handler */ +typedef void (*USBD_EPHandler_T)(uint8_t ep); + +/* Reset handler */ +typedef void (*USBD_ResetHandler_T)(void); + +/* Interrupt handler function define */ +typedef void (*USBD_InterruptHandler_T)(void); + +/** + * @brief Descriptor structure + */ +typedef struct +{ + const uint8_t* pDesc; + uint8_t size; +} USBD_Descriptor_T; + +/** + * @brief USB Class Request handler + */ +typedef struct +{ + USBD_StdReqHandler_T getConfigurationHandler; + USBD_StdReqHandler_T getDescriptorHandler; + USBD_StdReqHandler_T getInterfaceHandler; + USBD_StdReqHandler_T getStatusHandler; + USBD_StdReqHandler_T setAddressHandler; + + USBD_StdReqHandler_T setConfigurationHandler; + USBD_StdReqHandler_T setDescriptorHandler; + USBD_StdReqHandler_T setFeatureHandler; + USBD_StdReqHandler_T setInterfaceHandler; + USBD_StdReqHandler_T clearFeatureHandler; +} USBD_StdReqCallback_T; + +/** + * @brief Control transfer buffer + */ +typedef struct +{ + uint8_t* pBuf; /*!< Data buffer */ + uint32_t bufLen; /*!< Length of the data buffer */ + uint8_t packNum; /*!< Packet number of the data */ + uint8_t zeroPackFill; /*!< Fill a zero pack for IN transfer or not */ + uint16_t maxPackSize; /*!< Max pack size of this endpoint */ + uint32_t xferCnt; /*!< Data count of one pack on from tansfer */ +} USBD_CtrlBuf_T; + +/** + * @brief USB init parameter + */ +typedef struct +{ + USBD_Descriptor_T* pDeviceDesc; /*!< Device descriptor pointer */ + USBD_Descriptor_T* pConfigurationDesc; /*!< Configuration descriptor pointer */ + USBD_Descriptor_T* pStringDesc; /*!< String descriptor pointer */ + USBD_Descriptor_T* pQualifierDesc; /*!< Device Qualifier descriptor pointer */ + USBD_Descriptor_T* pHidReportDesc; /*!< HID report descriptor pointer */ + + + USBD_StdReqCallback_T* pStdReqCallback; + USBD_ReqHandler_T stdReqExceptionHandler; /*!< Standard request exception handler */ + USBD_ReqHandler_T classReqHandler; /*!< Class request handler */ + USBD_ReqHandler_T vendorReqHandler; /*!< vendor request handler */ + + USBD_CtrlTxStatusHandler_T txStatusHandler; /*!< Send IN status early handler */ + USBD_CtrlRxStatusHandler_T rxStatusHandler; /*!< Receive OUT status early handler */ + + USBD_EPHandler_T outEpHandler; /*!< OUT EP transfer done handler except EP0 */ + USBD_EPHandler_T inEpHandler; /*!< IN EP transfer done handler except EP0 */ + USBD_ResetHandler_T resetHandler; /*!< Reset handler */ + USBD_InterruptHandler_T intHandler; /*!< Hadler the rest of interrupt. */ +} USBD_InitParam_T; + +/** + * @brief USB infomation + */ +typedef struct +{ + USBD_CTRL_STATE_T ctrlState; + + uint8_t curFeature; + uint8_t curInterface; + uint8_t curAlternateSetting; + uint8_t curConfiguration; + uint8_t configurationNum; + + /* Setup request data buffer */ + USBD_DevReqData_T reqData; + + /* Endpoint buffer management */ + USBD_CtrlBuf_T inBuf[USB_EP_MAX_NUM]; + USBD_CtrlBuf_T outBuf[USB_EP_MAX_NUM]; + + /* Descriptor pointer */ + USBD_Descriptor_T* pDeviceDesc; + USBD_Descriptor_T* pConfigurationDesc; + USBD_Descriptor_T* pStringDesc; + USBD_Descriptor_T* pQualifierDesc; + USBD_Descriptor_T* pHidReportDesc; + + /* Setup request callback handler */ + USBD_StdReqCallback_T* pStdReqCallback; + USBD_ReqHandler_T stdReqExceptionHandler; + USBD_ReqHandler_T classReqHandler; + USBD_ReqHandler_T vendorReqHandler; + + /* Control transfer status stage handler */ + USBD_CtrlTxStatusHandler_T txStatusHandler; + USBD_CtrlRxStatusHandler_T rxStatusHandler; + + /* Endpoint transfer done handler */ + USBD_EPHandler_T outEpHandler; + USBD_EPHandler_T inEpHandler; + + USBD_ResetHandler_T resetHandler; + USBD_InterruptHandler_T intHandler; +} USBD_Info_T; + +/**@} end of group Core_Structures */ + +/** @defgroup Core_Variables Variables + @{ +*/ + + +extern USBD_Info_T g_usbDev; + +/**@} end of group Core_Variables */ + +/** @defgroup Core_Functions Functions + @{ +*/ + +/* Handler Endpoint 0 control transfer */ +void USBD_SetupProcess(void); +void USBD_CtrlInProcess(void); +void USBD_CtrlOutProcess(void); +void USBD_CtrlOutData(uint8_t* buf, uint32_t len); +void USBD_CtrlInData(uint8_t* buf, uint32_t len); + +/* Handler other Endpoint data transfer */ +void USBD_DataInProcess(USBD_EP_T ep); +void USBD_DataOutProcess(USBD_EP_T ep); +void USBD_TxData(uint8_t ep, uint8_t* buf, uint32_t len); +void USBD_RxData(uint8_t ep, uint8_t* buf, uint32_t len); + +#endif + +/**@} end of group Core_Functions */ +/**@} end of group Core */ +/**@} end of group Standard */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h new file mode 100644 index 0000000000..d6c5ef4180 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h @@ -0,0 +1,116 @@ +/*! + * @file usbd_init.h + * + * @brief USB initialization management head file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef USBD_INIT_H_ +#define USBD_INIT_H_ + +/* Includes */ +#include "usbd_core.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup Init + @{ +*/ + +/** @defgroup Init_Macros Macros + @{ +*/ + +/**@} end of group Init_Macros */ + +/** @defgroup Init_Enumerations Enumerations + @{ +*/ + +/**@} end of group Init_Enumerations */ + +/** @defgroup Init_Structures Structures + @{ +*/ + +/** + * @brief Endpoint Configuration Info + */ +typedef struct +{ + USBD_EP_T epNum; /*!< endpoint number */ + USBD_EP_TYPE_T epType; /*!< endpoint type */ + uint8_t epKind; /** + * Which could be ENABLE or DISABLE, it is valid only for + * control and bulk Endpoint. The mean of ENABLE for them like : + * 1. Control endpoint : Only for OUT status which is zero data. + * 2. Bulk endpoint : Enable the double-buffer feature + */ + USBD_EP_STATUS_T epStatus; /*!< Endpoint status */ + uint16_t epBufAddr; /*!< buffer address for the endpoint */ + uint16_t maxPackSize; /*!< max packet size for the endpoint */ +} USBD_EPConfig_T; + +/**@} end of group Init_Structures */ + +/** @defgroup Init_Variables Variables + @{ +*/ + +/**@} end of group Init_Variables */ + +/** @defgroup Init_Functions Functions + @{ +*/ + +/* USB init */ +void USBD_Init(USBD_InitParam_T* param); +void USBD_InitParamStructInit(USBD_InitParam_T* param); + +/* power */ +void USBD_PowerOn(void); +void USBD_PowerOff(void); + +/* Endpoint init */ +void USBD_OpenOutEP(USBD_EPConfig_T* epConfig); +void USBD_OpenInEP(USBD_EPConfig_T* epConfig); + +void USBD_CloseOutEP(USBD_EP_T ep); +void USBD_CloseInEP(USBD_EP_T ep); + +#endif + +/**@} end of group Init_Functions */ +/**@} end of group Init */ +/**@} end of group Standard */ +/**@} end of groupInit_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h new file mode 100644 index 0000000000..1606ffb818 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h @@ -0,0 +1,83 @@ +/*! + * @file usbd_interrupt.h + * + * @brief USB interrupt service routine header file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_INTERRUPT_H_ +#define __USBD_INTERRUPT_H_ + +/* Includes */ +#include "apm32f0xx.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup Interrupt + @{ +*/ + +/** @defgroup Interrupt_Macros Macros + @{ +*/ + +/**@} end of group Interrupt_Macros */ + +/** @defgroup Interrupt_Enumerations Enumerations + @{ +*/ + +/**@} end of group Interrupt_Enumerations */ + +/** @defgroup Interrupt_Structures Structures + @{ +*/ + +/**@} end of group Interrupt_Structures */ + +/** @defgroup Interrupt_Variables Variables + @{ +*/ + +/**@} end of group Interrupt_Variables */ + +/** @defgroup Interrupt_Functions Functions + @{ +*/ + +#endif + +/**@} end of group Interrupt_Functions */ +/**@} end of group Interrupt */ +/**@} end of group Standard */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h new file mode 100644 index 0000000000..04b06e27f8 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h @@ -0,0 +1,82 @@ +/*! + * @file usbd_stdReq.h + * + * @brief USB standard request process head file + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __USBD_STDREQ_H_ +#define __USBD_STDREQ_H_ + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup StdReq + @{ +*/ + +/** @defgroup StdReq_Macros Macros + @{ +*/ + +/**@} end of group StdReq_Macros */ + +/** @defgroup StdReq_Enumerations Enumerations + @{ +*/ + +/**@} end of group StdReq_Enumerations */ + +/** @defgroup StdReq_Structures Structures + @{ +*/ + +/**@} end of group StdReq_Structures */ + +/** @defgroup StdReq_Variables Variables + @{ +*/ + +/**@} end of group StdReq_Variables */ + +/** @defgroup StdReq_Functions Functions + @{ +*/ + +void USBD_StandardReqeust(void); + +#endif + +/**@} end of group StdReq_Functions */ +/**@} end of group Interrupt */ +/**@} end of group Standard */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c new file mode 100644 index 0000000000..9b62af7212 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c @@ -0,0 +1,456 @@ +/*! + * @file usbd_core.c + * + * @brief USB protocol core handler + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_core.h" +#include "usbd_stdReq.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup Core + @{ +*/ + +/** @defgroup Core_Macros Macros + @{ +*/ + +/**@} end of group Core_Macros */ + +/** @defgroup Core_Enumerations Enumerations + @{ +*/ + +/**@} end of group Core_Enumerations */ + +/** @defgroup Core_Structures Structures + @{ +*/ + +/**@} end of group Core_Structures */ + +/** @defgroup Core_Variables Variables + @{ +*/ + +/* USB information */ +USBD_Info_T g_usbDev; + +/**@} end of group Core_Variables */ + +/** @defgroup Core_Functions Functions + @{ +*/ + +/*! + * @brief Endpoint 0 Setup process + * + * @param None + * + * @retval None + */ +void USBD_SetupProcess(void) +{ + uint8_t reqType; + uint8_t dataBuf[8]; + USBD_DevReqData_T* pReqData = &g_usbDev.reqData; + uint16_t xferLen = USBD_ReadEPRxCnt(USBD_EP_0); + + if (xferLen) + { + USBD_ReadDataFromEP(USBD_EP_0, (uint8_t*)dataBuf, xferLen); + } + else + { + return; + } + + pReqData->byte.bmRequestType.byte = dataBuf[0]; + pReqData->byte.bRequest = dataBuf[1]; + pReqData->byte.wValue[0] = dataBuf[2]; + pReqData->byte.wValue[1] = dataBuf[3]; + pReqData->byte.wIndex[0] = dataBuf[4]; + pReqData->byte.wIndex[1] = dataBuf[5]; + pReqData->byte.wLength[0] = dataBuf[6]; + pReqData->byte.wLength[1] = dataBuf[7]; + + reqType = pReqData->byte.bmRequestType.bit.type; + + if (reqType == USBD_REQ_TYPE_STANDARD) + { + USBD_StandardReqeust(); + } + else if (reqType == USBD_REQ_TYPE_CLASS) + { + if (g_usbDev.classReqHandler) + { + g_usbDev.classReqHandler(pReqData); + } + } + else if (reqType == USBD_REQ_TYPE_VENDOR) + { + if (g_usbDev.vendorReqHandler) + { + g_usbDev.vendorReqHandler(pReqData); + } + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } +} + + +/*! + * @brief Endpoint 0 USB Control in process + * + * @param None + * + * @retval None + */ +void USBD_CtrlInProcess(void) +{ + uint32_t tmp; + + if (g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_IN) + { + if (g_usbDev.inBuf[0].packNum) + { + tmp = USB_MIN(g_usbDev.inBuf[0].bufLen, g_usbDev.inBuf[0].maxPackSize); + + USBD_WriteDataToEP(USBD_EP_0, g_usbDev.inBuf[0].pBuf, tmp); + USBD_SetEPTxCnt(USBD_EP_0, tmp); + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK); + + g_usbDev.inBuf[0].pBuf += tmp; + g_usbDev.inBuf[0].bufLen -= tmp; + g_usbDev.inBuf[0].packNum--; + } + else + { + if (g_usbDev.inBuf[USBD_EP_0].zeroPackFill) + { + USBD_SetEPTxCnt(USBD_EP_0, 0); + USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID); + g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 0; + } + else + { + if (g_usbDev.rxStatusHandler) + { + g_usbDev.rxStatusHandler(); + } + + g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT; + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID); + } + + } + } + else if (g_usbDev.ctrlState == USBD_CTRL_STATE_WAIT_STATUS_IN) + { + if (g_usbDev.reqData.byte.bRequest == USBD_SET_ADDRESS) + { + USBD_SetDeviceAddr(g_usbDev.reqData.byte.wValue[0]); + } + } +} + +/*! + * @brief Endpoint 0 USB Control out process + * + * @param None + * + * @retval None + */ +void USBD_CtrlOutProcess(void) +{ + uint32_t len; + + if (g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_OUT) + { + if (g_usbDev.outBuf[0].packNum) + { + len = USB_MIN(g_usbDev.outBuf[0].bufLen, g_usbDev.outBuf[0].maxPackSize); + + USBD_ReadDataFromEP(USBD_EP_0, g_usbDev.outBuf[0].pBuf, len); + + g_usbDev.outBuf[0].bufLen -= len; + g_usbDev.outBuf[0].pBuf += len; + g_usbDev.outBuf[0].packNum--; + + if (g_usbDev.outBuf[0].packNum) + { + USBD_CtrlOutData(g_usbDev.outBuf[0].pBuf, g_usbDev.outBuf[0].bufLen); + } + else + { + USBD_CtrlTxStatus(); + } + } + else + { + if (g_usbDev.txStatusHandler) + { + g_usbDev.txStatusHandler(); + } + + USBD_CtrlTxStatus(); + } + } +} + +/*! + * @brief Send data or status in control in transation + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_CtrlInData(uint8_t* buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.inBuf[0].maxPackSize; + uint16_t reqLen = *(uint16_t*)g_usbDev.reqData.byte.wLength; + + if (len) + { + if ((len < reqLen) && ((len % maxPackSize) == 0)) + { + g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 1; + } + + if (len >= g_usbDev.inBuf[0].maxPackSize) + { + /* Send a packet */ + USBD_WriteDataToEP(USBD_EP_0, buf, g_usbDev.inBuf[0].maxPackSize); + USBD_SetEPTxCnt(USBD_EP_0, g_usbDev.inBuf[0].maxPackSize); + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK); + + /* deal with buffer */ + g_usbDev.inBuf[0].bufLen = len - g_usbDev.inBuf[0].maxPackSize; + g_usbDev.inBuf[0].pBuf = buf + g_usbDev.inBuf[0].maxPackSize; + g_usbDev.inBuf[0].packNum = (g_usbDev.inBuf[0].bufLen + (maxPackSize - 1)) / maxPackSize; + + g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_IN; + } + else + { + USBD_WriteDataToEP(USBD_EP_0, buf, len); + USBD_SetEPTxCnt(USBD_EP_0, len); + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK); + + g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \ + USBD_CTRL_STATE_DATA_IN : \ + USBD_CTRL_STATE_WAIT_STATUS_IN; + } + } + else + { + USBD_SetEPTxCnt(USBD_EP_0, 0); + USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID); + + g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \ + USBD_CTRL_STATE_DATA_IN : \ + USBD_CTRL_STATE_WAIT_STATUS_IN; + } +} + +/*! + * @brief Read data or status in control out transation + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_CtrlOutData(uint8_t* buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize; + + if (len) + { + g_usbDev.outBuf[USBD_EP_0].pBuf = buf; + g_usbDev.outBuf[USBD_EP_0].bufLen = len; + g_usbDev.outBuf[USBD_EP_0].packNum = (len + (maxPackSize - 1)) / maxPackSize; + + len = USB_MIN(g_usbDev.outBuf[0].bufLen, maxPackSize); + + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID); + + g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_OUT; + } + else + { + g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT; + } + + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID); +} + +/*! + * @brief USB Data in process except endpoint 0 + * + * @param ep : endpoint Number except endpoint 0 + * + * @retval None + */ +void USBD_DataInProcess(USBD_EP_T ep) +{ + uint16_t len; + + if (g_usbDev.inBuf[ep].packNum) + { + len = g_usbDev.inBuf[ep].bufLen > g_usbDev.inBuf[ep].maxPackSize ? \ + g_usbDev.inBuf[ep].maxPackSize : g_usbDev.inBuf[ep].bufLen; + + + USBD_WriteDataToEP(ep, g_usbDev.inBuf[ep].pBuf, len); + USBD_SetEPTxCnt(ep, len); + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID); + + g_usbDev.inBuf[ep].pBuf += len; + g_usbDev.inBuf[ep].bufLen -= len; + g_usbDev.inBuf[ep].packNum--; + } + else + { + if (g_usbDev.inEpHandler) + { + g_usbDev.inEpHandler(ep); + } + } +} + +/*! + * @brief USB Data out process except endpoint 0 + * + * @param ep : endpoint Number except endpoint 0 + * + * @retval None + */ +void USBD_DataOutProcess(USBD_EP_T ep) +{ + if (g_usbDev.outBuf[ep].packNum) + { + g_usbDev.outBuf[ep].xferCnt = USBD_ReadEPRxCnt(ep); + + if ((g_usbDev.outBuf[ep].xferCnt != 0) && (g_usbDev.outBuf[ep].pBuf != NULL)) + { + USBD_ReadDataFromEP(ep, g_usbDev.outBuf[ep].pBuf, g_usbDev.outBuf[ep].xferCnt); + + g_usbDev.outBuf[ep].bufLen -= g_usbDev.outBuf[ep].xferCnt; + g_usbDev.outBuf[ep].pBuf += g_usbDev.outBuf[ep].xferCnt; + g_usbDev.outBuf[ep].packNum--; + } + if (g_usbDev.outBuf[ep].packNum) + { + USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID); + } + } + + if (g_usbDev.outEpHandler && !g_usbDev.outBuf[ep].packNum) + { + g_usbDev.outEpHandler(ep); + } +} + +/*! + * @brief Transfer data to host(except endpoint 0) + * + * @param ep: Endpoint number except endpoint 0 + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_TxData(uint8_t ep, uint8_t* buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.inBuf[ep].maxPackSize; + + if (len >= maxPackSize) + { + USBD_WriteDataToEP(ep, buf, maxPackSize); + USBD_SetEPTxCnt(ep, maxPackSize); + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID); + + g_usbDev.inBuf[ep].pBuf = buf + maxPackSize; + g_usbDev.inBuf[ep].bufLen = len - maxPackSize; + g_usbDev.inBuf[ep].packNum = (g_usbDev.inBuf[ep].bufLen + (maxPackSize - 1)) / maxPackSize; + } + else + { + USBD_WriteDataToEP(ep, buf, len); + USBD_SetEPTxCnt(ep, len); + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID); + + g_usbDev.inBuf[ep].packNum = 0; + g_usbDev.inBuf[ep].bufLen = 0; + } +} + +/*! + * @brief Receive data from host(except endpoint 0) + * + * @param ep: Endpoint number except endpoint 0 + * + * @param buf: Buffer pointer + * + * @param len: Buffer length + * + * @retval None + */ +void USBD_RxData(uint8_t ep, uint8_t* buf, uint32_t len) +{ + uint16_t maxPackSize = g_usbDev.outBuf[ep].maxPackSize; + + g_usbDev.outBuf[ep].pBuf = buf; + g_usbDev.outBuf[ep].bufLen = len; + g_usbDev.outBuf[ep].packNum = (len + (maxPackSize - 1)) / maxPackSize; + + USBD_SetEPRxCnt(ep, USB_MIN(len, maxPackSize)); + + USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID); +} + +/**@} end of group Core_Functions */ +/**@} end of group Core */ +/**@} end of group Standard */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c new file mode 100644 index 0000000000..d1548f9a15 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c @@ -0,0 +1,288 @@ +/*! + * @file usbd_init.c + * + * @brief USB initialization management + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_init.h" +#include "usb_bsp.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup Init + @{ +*/ + +/** @defgroup Init_Macros Macros + @{ +*/ + +/**@} end of group Init_Macros */ + +/** @defgroup Init_Enumerations Enumerations + @{ +*/ + +/**@} end of group Init_Enumerations */ + +/** @defgroup Init_Structures Structures + @{ +*/ + +/**@} end of group Init_Structures */ + +/** @defgroup Init_Variables Variables + @{ +*/ + +/**@} end of group Init_Variables */ + +/** @defgroup Init_Functions Functions + @{ +*/ + +static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType); + +/*! + * @brief USB initialization + * + * @param param: Initialization parameter + * + * @retval None + */ +void USBD_Init(USBD_InitParam_T* param) +{ + g_usbDev.pDeviceDesc = param->pDeviceDesc; + g_usbDev.pConfigurationDesc = param->pConfigurationDesc; + g_usbDev.pStringDesc = param->pStringDesc; + g_usbDev.pQualifierDesc = param->pQualifierDesc; + g_usbDev.pHidReportDesc = param->pHidReportDesc; + + g_usbDev.pStdReqCallback = param->pStdReqCallback; + g_usbDev.classReqHandler = param->classReqHandler; + g_usbDev.vendorReqHandler = param->vendorReqHandler; + g_usbDev.stdReqExceptionHandler = param->stdReqExceptionHandler; + + g_usbDev.txStatusHandler = param->txStatusHandler; + g_usbDev.rxStatusHandler = param->rxStatusHandler; + + g_usbDev.inEpHandler = param->inEpHandler; + g_usbDev.outEpHandler = param->outEpHandler; + + g_usbDev.resetHandler = param->resetHandler; + g_usbDev.intHandler = param->intHandler; + + USBD_HardWareInit(); + +#ifndef APM32F0xx_USB +#if USB_SELECT == USB1 + USBD2_Disable(); +#else + USB2_Enable(); +#endif +#endif + + USBD_PowerOn(); +} + +/*! + * @brief Init parameter in param + * + * @param param: Initialization parameter + * + * @retval None + */ +void USBD_InitParamStructInit(USBD_InitParam_T* param) +{ + param->pStdReqCallback = NULL; + param->stdReqExceptionHandler = NULL; + param->classReqHandler = NULL; + param->vendorReqHandler = NULL; + + param->txStatusHandler = NULL; + param->rxStatusHandler = NULL; + + param->outEpHandler = NULL; + param->inEpHandler = NULL; + + param->resetHandler = NULL; + param->intHandler = NULL; +} + +/*! + * @brief USB Power on + * + * @param None + * + * @retval None + */ +void USBD_PowerOn(void) +{ + USBD_ResetPowerDown(); + + USBD_SetForceReset(); + USBD_ResetForceReset(); + + USBD_DisableInterrupt(USBD_INT_ALL); + USBD_ClearIntFlag(USBD_INT_ALL); + + USBD_EnableInterrupt(USB_INT_SOURCE); +} + +/*! + * @brief USB Power off + * + * @param None + * + * @retval None + */ +void USBD_PowerOff(void) +{ + USBD_DisableInterrupt(USBD_INT_ALL); + USBD_ClearIntFlag(USBD_INT_ALL); + + /* Power down and Force USB Reset */ + USBD_SetRegCTRL(0X03); +} + + +/*! + * @brief Open OUT endpoint. + * + * @param epConfig: Point to USBD_EPConfig_T structure + * + * @retval None + */ +void USBD_OpenOutEP(USBD_EPConfig_T* epConfig) +{ + g_usbDev.outBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize; + + USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType)); + + if (epConfig->epKind) + { + USBD_SetEPKind(epConfig->epNum); + } + else + { + USBD_ResetEPKind(epConfig->epNum); + } + + USBD_SetEPRxAddr(epConfig->epNum, epConfig->epBufAddr); + USBD_SetEPRxCnt(epConfig->epNum, epConfig->maxPackSize); + USBD_SetEPRxStatus(epConfig->epNum, epConfig->epStatus); +} + +/*! + * @brief Open IN endpoint. + * + * @param epConfig: Point to USBD_EPConfig_T structure + * + * @retval None + */ +void USBD_OpenInEP(USBD_EPConfig_T* epConfig) +{ + g_usbDev.inBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize; + + USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType)); + + if (epConfig->epKind) + { + USBD_SetEPKind(epConfig->epNum); + } + else + { + USBD_ResetEPKind(epConfig->epNum); + } + + USBD_SetEPTxAddr(epConfig->epNum, epConfig->epBufAddr); + USBD_SetEPTxStatus(epConfig->epNum, epConfig->epStatus); +} + +/*! + * @brief Close OUT endpoint. + * + * @param ep: OUT endpoint Number + * + * @retval None + */ +void USBD_CloseOutEP(USBD_EP_T ep) +{ + g_usbDev.outBuf[ep].maxPackSize = 0; + + USBD_SetEPRxStatus(ep, USBD_EP_STATUS_DISABLE); +} + +/*! + * @brief Close IN endpoint. + * + * @param ep: IN endpoint Number + * + * @retval None + */ +void USBD_CloseInEP(USBD_EP_T ep) +{ + g_usbDev.inBuf[ep].maxPackSize = 0; + + USBD_SetEPTxStatus(ep, USBD_EP_STATUS_DISABLE); +} + +/*! + * @brief Convert endpoint Type. + * + * @param epType: endpoint type + * + * @retval Value of USBD_REG_EP_TYPE_T + */ +static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType) +{ + switch (epType) + { + case USBD_EP_TYPE_CONTROL : + return USBD_REG_EP_TYPE_CONTROL; + case USBD_EP_TYPE_ISO : + return USBD_REG_EP_TYPE_ISO; + case USBD_EP_TYPE_BULK : + return USBD_REG_EP_TYPE_BULK; + case USBD_EP_TYPE_INTERRUPT : + return USBD_REG_EP_TYPE_INTERRUPT; + default : + return USBD_REG_EP_TYPE_CONTROL; + } +} + +/**@} end of group Init_Functions */ +/**@} end of group Init */ +/**@} end of group Standard */ +/**@} end of groupInit_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c new file mode 100644 index 0000000000..6a750c5b0c --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c @@ -0,0 +1,384 @@ +/*! + * @file usbd_interrupt.c + * + * @brief USB interrupt service routine + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "usbd_init.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup Core_Device Core Device + @{ +*/ + +/** @addtogroup Standrad + @{ +*/ + +/** @addtogroup Interrupt + @{ +*/ + +/** @defgroup Interrupt_Macros Macros + @{ +*/ + +/**@} end of group Interrupt_Macros */ + +/** @defgroup Interrupt_Enumerations Enumerations + @{ +*/ + +/**@} end of group Interrupt_Enumerations */ + +/** @defgroup Interrupt_Structures Structures + @{ +*/ + +/**@} end of group Interrupt_Structures */ + +/** @defgroup Interrupt_Variables Variables + @{ +*/ + +/**@} end of group Interrupt_Variables */ + +/** @defgroup Interrupt_Functions Functions + @{ +*/ + +static void USBD_LowPriorityProc(void); + +static void USBD_ResetIsrHandler(void); +static void USBD_SuspendIsrHandler(void); +static void USBD_ResumeIsrHandler(void); + +/*! + * @brief USB interrupt service routine + * + * @param None + * + * @retval None + */ +#ifdef APM32F0xx_USB /*!< APM32F0xx_USB */ +void USBD_IRQHandler(void) +{ +#if (USB_INT_SOURCE & USBD_INT_CTR) + if (USBD_ReadIntFlag(USBD_INT_CTR)) + { + USBD_LowPriorityProc(); + } +#endif + +#if (USB_INT_SOURCE & USBD_INT_RST) + if (USBD_ReadIntFlag(USBD_INT_RST)) + { + USBD_ClearIntFlag(USBD_INT_RST); + USBD_ResetIsrHandler(); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_PMAOU + if (USBD_ReadIntFlag(USBD_INT_PMAOU)) + { + USBD_ClearIntFlag(USBD_INT_PMAOU); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_ERR + + if (USBD_ReadIntFlag(USBD_INT_ERR)) + { + USBD_ClearIntFlag(USBD_INT_ERR); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_WKUP + if (USBD_ReadIntFlag(USBD_INT_WKUP)) + { + USBD_ResumeIsrHandler(); + USBD_ClearIntFlag(USBD_INT_WKUP); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_SUS + if (USBD_ReadIntFlag(USBD_INT_SUS)) + { + USBD_SuspendIsrHandler(); + USBD_ClearIntFlag(USBD_INT_SUS); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_SOF + if (USBD_ReadIntFlag(USBD_INT_SOF)) + { + USBD_ClearIntFlag(USBD_INT_SOF); + } +#endif + +#if USB_INT_SOURCE & USBD_INT_ESOF + if (USBD_ReadIntFlag(USBD_INT_ESOF)) + { + USBD_ClearIntFlag(USBD_INT_ESOF); + } +#endif +} +#endif + +/*! + * @brief USB low priority process + * + * @param None + * + * @retval None + */ +static void USBD_LowPriorityProc(void) +{ + USBD_EP_T ep; + + while (USBD_ReadIntFlag(USBD_INT_CTR)) + { + ep = (USBD_EP_T)USBD_ReadEP(); + + /* Endpoint 0 */ + if (ep == 0) + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_NAK); + + /* Control in */ + if (USBD_ReadDir() == 0) + { + USBD_ResetEPTxFlag(USBD_EP_0); + USBD_CtrlInProcess(); + } + else + { + /* Setup */ + if (USBD_ReadEPSetup(USBD_EP_0) == SET) + { + USBD_ResetEPRxFlag(USBD_EP_0); + USBD_SetupProcess(); + } + /* Control out */ + else + { + USBD_ResetEPRxFlag(USBD_EP_0); + USBD_CtrlOutProcess(); + } + } + } + /* Transfer Handler Except endpoint 0 */ + else + { + if (USBD_ReadEPRxFlag(ep)) + { + USBD_ResetEPRxFlag(ep); + USBD_DataOutProcess(ep); + } + + if (USBD_ReadEPTxFlag(ep)) + { + USBD_ResetEPTxFlag(ep); + USBD_DataInProcess(ep); + } + } + } +} + + +/*! + * @brief USB Device Reset + * + * @param None + * + * @retval None + */ +static void USBD_ResetIsrHandler(void) +{ + uint8_t i; + USBD_EPConfig_T epConfig; + + g_usbDev.configurationNum = USB_CONFIGURATION_NUM; + g_usbDev.curConfiguration = 0; + g_usbDev.curInterface = 0; + g_usbDev.curAlternateSetting = 0; + g_usbDev.curFeature = 0; + g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_SETUP; + + g_usbDev.inBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE; + g_usbDev.outBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE; + + USBD_SetBufferTable(USB_BUFFER_TABLE_ADDR); + + /* Endpoint 0 IN */ + epConfig.epNum = USBD_EP_0; + epConfig.epType = USBD_EP_TYPE_CONTROL; + epConfig.epKind = DISABLE; + epConfig.epBufAddr = USB_EP0_TX_ADDR; + epConfig.maxPackSize = g_usbDev.inBuf[USBD_EP_0].maxPackSize; + epConfig.epStatus = USBD_EP_STATUS_NAK; + USBD_OpenInEP(&epConfig); + + /* Endpoint 0 OUT */ + epConfig.epBufAddr = USB_EP0_RX_ADDR; + epConfig.maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize; + epConfig.epStatus = USBD_EP_STATUS_VALID; + USBD_OpenOutEP(&epConfig); + + if (g_usbDev.resetHandler) + { + g_usbDev.resetHandler(); + } + + for (i = 0; i < USB_EP_MAX_NUM; i++) + { + USBD_SetEpAddr((USBD_EP_T)i, i); + } + + USBD_SetDeviceAddr(0); + USBD_Enable(); +} + +/*! + * @brief USB Suspend + * + * @param None + * + * @retval None + */ +static void USBD_SuspendIsrHandler(void) +{ + uint8_t i; + uint16_t bakEP[8]; +#if USB_LOW_POWER_SWITCH + uint32_t bakPwrCR; + uint32_t tmp; +#endif + + for (i = 0; i < 8; i++) + { + bakEP[i] = (uint16_t)USBD->EP[i].EP; + } + + USBD_EnableInterrupt(USBD_INT_RST); + + USBD_SetForceReset(); + USBD_ResetForceReset(); + + while (USBD_ReadIntFlag(USBD_INT_RST) == RESET); + + for (i = 0; i < 8; i++) + { + USBD->EP[i].EP = bakEP[i]; + } + + USBD_SetForceSuspend(); + +#if USB_LOW_POWER_SWITCH + USBD_SetLowerPowerMode(); + + bakPwrCR = PMU->CTRL; + tmp = PMU->CTRL; + tmp &= (uint32_t)0xfffffffc; + tmp |= PMU_REGULATOR_LOWPOWER; + PMU->CTRL = tmp; + + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + if (USBD_ReadIntFlag(USBD_INT_WKUP) == RESET) + { + __WFI(); + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + } + else + { + USBD_ClearIntFlag(USBD_INT_WKUP); + USBD_ResetForceSuspend(); + PMU->CTRL = bakPwrCR; + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + } +#endif +} + +/*! + * @brief Resume + * + * @param None + * + * @retval None + */ +static void USBD_ResumeIsrHandler(void) +{ +#if USB_LOW_POWER_SWITCH + USBD_ResetLowerPowerMode(); +#endif + + SystemInit(); + + USBD_SetRegCTRL(USB_INT_SOURCE); +} + +#ifndef APM32F0xx_USB +/*! + * @brief USB High priority process + * + * @param None + * + * @retval None + */ +static void USBD_HighPriorityProc(void) +{ + USBD_EP_T ep; + + while (USBD_ReadIntFlag(USBD_INT_CTR)) + { + USBD_ClearIntFlag(USBD_INT_CTR); + + ep = USBD_ReadEP(); + + if (USBD_ReadEPRxFlag(ep)) + { + USBD_ResetEPRxFlag(ep); + + g_usbDev.outEpHandler(ep); + } + + if (USBD_ReadEPTxFlag(ep)) + { + USBD_ResetEPTxFlag(ep); + + g_usbDev.inEpHandler(ep); + } + } +} + +#endif + +/**@} end of group Interrupt_Functions */ +/**@} end of group Interrupt */ +/**@} end of group Standard */ +/**@} end of group Core_Device */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c new file mode 100644 index 0000000000..a9f737b538 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c @@ -0,0 +1,371 @@ +/*! + * @file usbd_stdReq.c + * + * @brief USB standard request process + * + * @version V1.0.0 + * + * @date 2021-12-30 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "usbd_stdReq.h" +#include "usbd_core.h" +#include "usbd_descriptor.h" + +static uint8_t USBD_StandardGetConfiguration(void); +static uint8_t USBD_StandardGetDescriptor(void); +static uint8_t USBD_StandardGetInterface(void); +static uint8_t USBD_StandardGetStatus(void); + +static uint8_t USBD_StandardSetAddress(void); +static uint8_t USBD_StandardSetConfiguration(void); +static uint8_t USBD_StandardSetDescriptor(void); +static uint8_t USBD_StandardSetFeature(void); +static uint8_t USBD_StandardSetInterface(void); + +static uint8_t USBD_StandardClearFeature(void); + + +/*! + * @brief USB request standard request + * + * @param None + * + * @retval None + */ +void USBD_StandardReqeust(void) +{ + uint8_t result = 1; + + uint8_t bRequest = g_usbDev.reqData.byte.bRequest; + + switch(bRequest) + { + case USBD_GET_CONFIGURATION: + result = USBD_StandardGetConfiguration(); + break; + + case USBD_GET_DESCRIPTOR: + result = USBD_StandardGetDescriptor(); + break; + + case USBD_GET_INTERFACE: + result = USBD_StandardGetInterface(); + break; + + case USBD_GET_STATUS: + result = USBD_StandardGetStatus(); + break; + + case USBD_SET_ADDRESS: + result = USBD_StandardSetAddress(); + break; + + case USBD_SET_CONFIGURATION: + result = USBD_StandardSetConfiguration(); + break; + + case USBD_SET_DESCRIPTOR: + result = USBD_StandardSetDescriptor(); + break; + + case USBD_SET_FEATURE: + result = USBD_StandardSetFeature(); + break; + + case USBD_SET_INTERFACE: + result = USBD_StandardSetInterface(); + + break; + + case USBD_CLEAR_FEATURE: + result = USBD_StandardClearFeature(); + break; + + default: + + break; + } + + if(!result) + { + if(g_usbDev.stdReqExceptionHandler != NULL) + { + g_usbDev.stdReqExceptionHandler(&g_usbDev.reqData); + } + else + { + USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL); + } + } +} + +/*! + * @brief Standard request get configuration + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetConfiguration(void) +{ + uint8_t recipient = g_usbDev.reqData.byte.bmRequestType.bit.recipient; + + if(recipient == USBD_RECIPIENT_DEVICE) + { + USBD_CtrlInData(&g_usbDev.curConfiguration, 1); + + if (g_usbDev.pStdReqCallback->getConfigurationHandler) + { + g_usbDev.pStdReqCallback->getConfigurationHandler(); + } + + + return SUCCESS; + } + + return ERROR; +} + +/*! + * @brief Standard request get descriptor + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetDescriptor(void) +{ + uint8_t ret = SUCCESS; + uint32_t len = 0; + uint8_t wValue0 = g_usbDev.reqData.byte.wValue[0]; + uint8_t wValue1 = g_usbDev.reqData.byte.wValue[1]; + + if(wValue1 == USBD_DESC_DEVICE) + { + len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pDeviceDesc->size); + USBD_CtrlInData((uint8_t *)g_usbDev.pDeviceDesc->pDesc, len); + } + else if(wValue1 == USBD_DESC_CONFIGURATION) + { + len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pConfigurationDesc->size); + USBD_CtrlInData((uint8_t *)g_usbDev.pConfigurationDesc->pDesc, len); + } + else if(wValue1 == USBD_DESC_STRING) + { + if (wValue0 < SRTING_DESC_NUM) + { + len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pStringDesc[wValue0].size); + USBD_CtrlInData((uint8_t *)g_usbDev.pStringDesc[wValue0].pDesc, len); + } + else + { + ret = ERROR; + } + + } + else + { + ret = ERROR; + } + + return ret; +} + +/*! + * @brief Standard request get interface + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetInterface(void) +{ + + return ERROR; +} + +/*! + * @brief Standard request get status + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardGetStatus(void) +{ + uint8_t ret = 1; + + + uint8_t status[2] = {0, 0}; + + if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_DEVICE) + { + if(g_usbDev.curFeature & (1 << 5)) + { + status[0] |= 0x02; + } + + if(g_usbDev.curFeature & (1 << 6)) + { + status[0] |= 0x01; + } + + USBD_CtrlInData(status, 2); + + + } + + else if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_INTERFACE) + { + USBD_CtrlInData(status, 2); + + + } + + else if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_ENDPOINT) + { + + if(g_usbDev.reqData.byte.wIndex[0] & 0x80) + { + if(USBD_ReadEPTxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL) + { + status[0] |= 0x01; + } + } + else + { + if(USBD_ReadEPRxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL) + { + status[0] |= 0x01; + } + + } + USBD_CtrlInData(status, 2); + + } + else + { + ret = 0; + } + + return ret; +} + +/*! + * @brief Standard request set address + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardSetAddress(void) +{ + USBD_DevReqData_T *reqData = &g_usbDev.reqData; + + if((reqData->byte.wValue[0] < 127) && (reqData->byte.wValue[1] == 0) && + (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE)) + { + USBD_CtrlInData((void *)0, 0); + + return 1; + } + + return 0; +} + +/*! + * @brief Standard request set configuration + * + * @param None + * + * @retval ERROR: 0; SUCCESS : 1 + */ +static uint8_t USBD_StandardSetConfiguration(void) +{ + USBD_DevReqData_T *reqData = &g_usbDev.reqData; + + if((reqData->byte.wValue[0] <= g_usbDev.configurationNum) && \ + (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE)) + { + g_usbDev.curConfiguration = reqData->byte.wValue[0]; + + if (g_usbDev.pStdReqCallback->setConfigurationHandler) + { + g_usbDev.pStdReqCallback->setConfigurationHandler(); + } + + USBD_CtrlInData((void *)0, 0); + + return 1; + } + + return 0; +} + +/*! + * @brief Standard request set descriptor + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardSetDescriptor(void) +{ + + return ERROR; +} + +/*! + * @brief Standard request set feature + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardSetFeature(void) +{ + uint8_t ret = 1; + + return ret; +} + +/*! + * @brief Standard request set interface + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardSetInterface(void) +{ + + return 0; +} + +/*! + * @brief Standard request clear feature + * + * @param None + * + * @retval 0: Failed; 1: Success + */ +static uint8_t USBD_StandardClearFeature(void) +{ + return 0; +} diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h new file mode 100644 index 0000000000..a768c2b5ae --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h @@ -0,0 +1,939 @@ +/*! + * @file drv_usb_device.h + * + * @brief This file contains all the prototypes,enumeration and macros for USBD peripheral + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __DRV_USB_DEVICE_H_ +#define __DRV_USB_DEVICE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(APM32F070xB) || defined(APM32F072x8) || defined(APM32F072xB) +#define APM32F0xx_USB +#endif + +/* Includes */ +#ifdef APM32F0xx_USB +#include "apm32f0xx.h" +#include "apm32f0xx_pmu.h" +#include "apm32f0xx_eint.h" +#include "apm32f0xx_gpio.h" +#include "apm32f0xx_rcm.h" +#include "apm32f0xx_misc.h" +#include "usb_config.h" +#endif + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup USBD_Driver + @{ +*/ + +/** @defgroup Driver_Macros Macros + @{ +*/ + +/* USBD packet memory area base address */ +#define USBD_PMA_ADDR (0x40006000L) + +/* Endpoint register mask value default */ +#define USBD_EP_MASK_DEFAULT (USBD_EP_BIT_CTFR | USBD_EP_BIT_SETUP | USBD_EP_BIT_TYPE | USBD_EP_BIT_KIND | USBD_EP_BIT_CTFT |USBD_EP_BIT_ADDR) + +/** + * @brief USBD interrupt source + */ +#define USBD_INT_ESOF 0X100 +#define USBD_INT_SOF 0X200 +#define USBD_INT_RST 0X400 +#define USBD_INT_SUS 0x800 +#define USBD_INT_WKUP 0X1000 +#define USBD_INT_ERR 0X2000 +#define USBD_INT_PMAOU 0X4000 +#define USBD_INT_CTR 0X8000 +#define USBD_INT_ALL 0XFF00 + +/**@} end of group Driver_Macros */ + +/** @defgroup Driver_Macros_Functions Macros Functions + @{ +*/ + +/*! + * @brief Set CTRL register + * + * @param val: Register value + * + * @retval None + * + */ +#define USBD_SetRegCTRL(val) (USBD->CTRL = val) + +/*! + * @brief Set INTSTS register + * + * @param val: Register value + * + * @retval None + */ +#define USBD_SetRegINTSTS(val) (USBD->INTSTS = val) + +/*! + * @brief Set force reset + * + * @param None + * + * @retval None + */ +#define USBD_SetForceReset() (USBD->CTRL_B.FORRST = BIT_SET) + +/*! + * @brief Reset force reset + * + * @param None + * + * @retval None + */ +#define USBD_ResetForceReset() (USBD->CTRL_B.FORRST = BIT_RESET) + +/*! + * @brief Set power down + * + * @param None + * + * @retval None + */ +#define USBD_SetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_SET) + +/*! + * @brief Reset power down + * + * @param None + * + * @retval None + */ +#define USBD_ResetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_RESET) + +/*! + * @brief Set low power mode + * + * @param None + * + * @retval None + */ +#define USBD_SetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_SET) + +/*! + * @brief Ret low power mode + * + * @param None + * + * @retval None + */ +#define USBD_ResetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_RESET) + +/*! + * @brief Set force suspend + * + * @param None + * + * @retval None + */ +#define USBD_SetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_SET) + +/*! + * @brief Reset force suspend + * + * @param None + * + * @retval None + */ +#define USBD_ResetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_RESET) + +/*! + * @brief Read force suspend status + * + * @param None + * + * @retval None + */ +#define USBD_ReadForceSuspend() (USBD->CTRL_B.FORSUS) + +/*! + * @brief Set resume + * + * @param None + * + * @retval None + */ +#define USBD_SetResume() (USBD->CTRL_B.WUPREQ = BIT_SET) + +/*! + * @brief Reset resume + * + * @param None + * + * @retval None + */ +#define USBD_ResetResume() (USBD->CTRL_B.WUPREQ = BIT_RESET) + +/*! + * @brief Enable interrupt + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_EnableInterrupt(int) (USBD->CTRL |= int) + +/*! + * @brief Disable interrupt + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_DisableInterrupt(int) (USBD->CTRL &= (uint32_t)~int) + +/*! + * @brief Read the specified interrupt flag status + * + * @param int: Interrupt source + * + * @retval Flag status.0 or not 0 + */ +#define USBD_ReadIntFlag(int) (USBD->INTSTS & int) + +/*! + * @brief Clear the specified interrupt flag status + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_ClearIntFlag(int) (USBD->INTSTS &= (uint32_t)~int) + +/*! + * @brief Read DOT field value in INTSTS rigister + * + * @param None + * + * @retval DOT field value + */ +#define USBD_ReadDir() (USBD->INTSTS_B.DOT) + +/*! + * @brief Read EPID field value in INTSTS rigister + * + * @param None + * + * @retval EPIDfield value + */ +#define USBD_ReadEP() ((USBD_EP_T)(USBD->INTSTS_B.EPID)) + +/*! + * @brief Read EP type + * + * @param ep: EP number + * + * @retval EP type + */ +#define USBD_ReadEPType(ep) (USBD->EP[ep].EP_B.TYPE) + +/*! + * @brief Read EP Tx status + * + * @param ep: EP number + * + * @retval EP Tx status + */ +#define USBD_ReadEPTxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.TXSTS)) + +/*! + * @brief Read EP Rx status + * + * @param ep: EP number + * + * @retval EP Rx status + */ +#define USBD_ReadEPRxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS)) + +/*! + * @brief Read SETUP field value in EP register + * + * @param ep: EP number + * + * @retval SETUP field value + */ +#define USBD_ReadEPSetup(ep) (USBD->EP[ep].EP_B.SETUP) + +/*! + * @brief Set buffer table value + * + * @param tab: Buffer table value + * + * @retval None + */ +#define USBD_SetBufferTable(tab) (USBD->BUFFTB_B.BUFFTB = tab) + +/*! + * @brief Set device address + * + * @param addr: Device address + * + * @retval None + */ +#define USBD_SetDeviceAddr(addr) (USBD->ADDR_B.ADDR = addr) + +/*! + * @brief Read CTFR field value in EP register + * + * @param ep: Endpoint number + * + * @retval CTFR field value + */ +#define USBD_ReadEPRxFlag(ep) (USBD->EP[ep].EP_B.CTFR) + +/*! + * @brief Read CTFT field value in EP register + * + * @param ep: Endpoint number + * + * @retval CTFT field value + */ +#define USBD_ReadEPTxFlag(ep) (USBD->EP[ep].EP_B.CTFT) + +/*! + * @brief Enable USBD peripheral + * + * @param None + * + * @retval None + */ +#define USBD_Enable() (USBD->ADDR_B.USBDEN = BIT_SET) + +/*! + * @brief Disable USBD peripheral + * + * @param None + * + * @retval None + */ +#define USBD_Disable() (USBD->ADDR_B.USBDEN = BIT_RESET) + +/*! + * @brief Enable USBD2 peripheral + * + * @param None + * + * @retval None + */ +#define USBD2_Enable() (USBD->SWITCH = BIT_SET) + +/*! + * @brief Disable USBD2 peripheral + * + * @param None + * + * @retval None + */ +#define USBD2_Disable() (USBD->SWITCH = BIT_RESET) + +/*! + * @brief Read RXDPSTS field value in FRANUM register + * + * @param None + * + * @retval RXDPSTS field value + */ +#define USBD_ReadRDPS() (USBD->FRANUM_B.RXDPSTS) + +/*! + * @brief Read RXDMSTS field value in FRANUM register + * + * @param None + * + * @retval RXDMSTS field value + */ +#define USBD_ReadRDMS() (USBD->FRANUM_B.RXDMSTS) + +/*! + * @brief Read LOCK field value in FRANUM register + * + * @param None + * + * @retval LOCK field value + */ +#define USBD_ReadLOCK() (USBD->FRANUM_B.LOCK) + +/*! + * @brief Read LSOFNUM field value in FRANUM register + * + * @param None + * + * @retval LSOFNUM field value + */ +#define USBD_ReadLSOF() (USBD->FRANUM_B.LSOFNUM) + +/*! + * @brief Read FRANUM field value in FRANUM register + * + * @param None + * + * @retval FRANUM field value + */ +#define USBD_ReadFRANUM() (USBD->FRANUM_B.FRANUM) + +#ifdef APM32F0xx_USB +/*! + * @brief Read EP Tx address pointer + * + * @param ep: EP number + * + * @retval EP Tx address pointer + */ +#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Tx count pointer + * + * @param ep: EP number + * + * @retval EP Tx count pointer + */ +#define USBD_ReadEPTxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx address pointer + * + * @param ep: EP number + * + * @retval EP Rx address pointer + */ +#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx count pointer + * + * @param ep: EP number + * + * @retval EP Rx count pointer + */ +#define USBD_ReadEPRxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx addr + * + * @param ep: EP number + * + * @param addr: Tx addr + * + * @retval None + */ +#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Set EP Rx addr + * + * @param ep: EP number + * + * @param addr: Rx addr + * + * @retval None + */ +#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Read EP Tx addr + * + * @param ep: EP number + * + * @retval EP Tx addr + */ +#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) + +/*! + * @brief Read EP Rx addr + * + * @param ep: EP number + * + * @retval EP Rx addr + */ +#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) + +/*! + * @brief Read EP Tx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Tx Buffer Pointer + */ +#define USBD_ReadEPTxBufferPointer(ep) (uint16_t *)(USBD_ReadEPTxAddr(ep) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Rx Buffer Pointer + */ +#define USBD_ReadEPRxBufferPointer(ep) (uint16_t *)(USBD_ReadEPRxAddr(ep) + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx Count + * + * @param ep: EP number + * + * @param cnt: Tx count + * + * @retval None + */ +#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) + +/*! + * @brief Read EP Tx count + * + * @param ep: EP number + * + * @retval EP Tx count + */ +#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read EP Rx count + * + * @param ep: EP number + * + * @retval EP Rx count + */ +#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) + +/*! + * @brief Set BESL Value + * + * @param val: 4-bits BESL Value to be set + * + * @retval None + */ +#define USBD_SetBESL(val) (USBD->LPMCTRLSTS_B.BESL = val) + +/*! + * @brief Set bRemoteWakew Value + * + * @param val: 1-bit bRemoteWakew Value to be set + * + * @retval None + */ +#define USBD_SetRemoteWakeVal(val) (USBD->LPMCTRLSTS_B.REMWAKE = val) + +/*! + * @brief Enable LPM ACK + * + * @param None + * + * @retval None + */ +#define USBD_EnableAckLPM() (USBD->LPMCTRLSTS_B.LPMACKEN = 1) + +/*! + * @brief Disable LPM ACK + * + * @param None + * + * @retval None + */ +#define USBD_DisableAckLPM() (USBD->LPMCTRLSTS_B.LPMACKEN = 0) + +/*! + * @brief Disable LPM + * + * @param None + * + * @retval None + */ +#define USBD_EnableLPM() (USBD->LPMCTRLSTS_B.LPMEN = 1) + +/*! + * @brief Disable LPM + * + * @param None + * + * @retval None + */ +#define USBD_DisableLPM() (USBD->LPMCTRLSTS_B.LPMEN = 0) + +/*! + * @brief Enable Pull-up of DP line + * + * @param None + * + * @retval None + */ +#define USBD_EnablePullUpDP() (USBD->BCD_B.DPPUCTRL = 1) + +/*! + * @brief Disable Pull-up of DP line + * + * @param None + * + * @retval None + */ +#define USBD_DisablePullUpDP() (USBD->BCD_B.DPPUCTRL = 0) + +/*! + * @brief Read DM Pull-up Detection Status Flag + * + * @param None + * + * @retval DM Pull-up Detection Status Flag + */ +#define USBD_DMPullUpStatus() (USBD->BCD_B.DMPUDFLG) + +/*! + * @brief Read Secondary Detection Status Flag + * + * @param None + * + * @retval Secondary Detection Status Flag + */ +#define USBD_SDStatus() (USBD->BCD_B.SDFLG) + +/*! + * @brief Read Primary Detection Status Flag + * + * @param None + * + * @retval Primary Detection Status Flag + */ +#define USBD_PDStatus() (USBD->BCD_B.PDFLG) + +/*! + * @brief Read Data Contact Detection Status Flag + * + * @param None + * + * @retval Data Contact Detection Status Flag + */ +#define USBD_DCDStatus() (USBD->BCD_B.DCDFLG) + +/*! + * @brief Enable Secondary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_EnableSDMode() (USBD->BCD_B.SDEN = 1) + +/*! + * @brief Disable Secondary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_DisableSDMode() (USBD->BCD_B.SDEN = 0) + +/*! + * @brief Enable Primary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_EnablePDMode() (USBD->BCD_B.PDEN = 1) + +/*! + * @brief Disable Primary Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_DisablePDMode() (USBD->BCD_B.PDEN = 0) + +/*! + * @brief Enable Data Contact Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_EnableDCDMode() (USBD->BCD_B.DCDEN = 1) + +/*! + * @brief Disable Data Contact Detection Mode + * + * @param None + * + * @retval None + */ +#define USBD_DisableDCDMode() (USBD->BCD_B.DCDEN = 0) + +/*! + * @brief Enable Battery Charging Detector + * + * @param None + * + * @retval None + */ +#define USBD_EnableBCD() (USBD->BCD_B.BCDEN = 1) + +/*! + * @brief Disable Battery Charging Detector + * + * @param None + * + * @retval None + */ +#define USBD_DisableBCD() (USBD->BCD_B.BCDEN = 0) + +#else //!< APM32F10x_USB +/*! + * @brief Read EP Tx address pointer + * + * @param ep: EP number + * + * @retval EP Tx address pointer + */ +#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Tx count pointer + * + * @param ep: EP number + * + * @retval EP Tx count pointer + */ +#define USBD_ReadEPTxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx address pointer + * + * @param ep: EP number + * + * @retval EP Rx address pointer + */ +#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx count pointer + * + * @param ep: EP number + * + * @retval EP Rx count pointer + */ +#define USBD_ReadEPRxCntPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx addr + * + * @param ep: EP number + * + * @param addr: Tx addr + * + * @retval None + */ +#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Set EP Rx addr + * + * @param ep: EP number + * + * @param addr: Rx addr + * + * @retval None + */ +#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Read EP Tx addr + * + * @param ep: EP number + * + * @retval EP Tx addr + */ +#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) + +/*! + * @brief Read EP Rx addr + * + * @param ep: EP number + * + * @retval EP Rx addr + */ +#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) + +/*! + * @brief Read EP Tx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Tx Buffer Pointer + */ +#define USBD_ReadEPTxBufferPointer(ep) (uint32_t *)(((uint32_t)USBD_ReadEPTxAddr(ep) << 1) + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx Buffer Pointer + * + * @param ep: EP number + * + * @retval EP Rx Buffer Pointer + */ +#define USBD_ReadEPRxBufferPointer(ep) (uint32_t *)(((uint32_t)USBD_ReadEPRxAddr(ep) << 1) + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx Count + * + * @param ep: EP number + * + * @param cnt: Tx count + * + * @retval None + */ +#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) + +/*! + * @brief Read EP Tx count + * + * @param ep: EP number + * + * @retval EP Tx count + */ +#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read EP Rx count + * + * @param ep: EP number + * + * @retval EP Rx count + */ +#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) + +#endif + +/**@} end of group Driver_Macros_Functions */ + +/** @defgroup Driver_Enumerations Enumerations + @{ +*/ + +/** + * @brief USBD Endpoint register bit definition + */ +typedef enum +{ + USBD_EP_BIT_ADDR = (uint32_t)(BIT0 | BIT1 | BIT2 | BIT3), + USBD_EP_BIT_TXSTS = (uint32_t)(BIT4 | BIT5), + USBD_EP_BIT_TXDTOG = (uint32_t)(BIT6), + USBD_EP_BIT_CTFT = (uint32_t)(BIT7), + USBD_EP_BIT_KIND = (uint32_t)(BIT8), + USBD_EP_BIT_TYPE = (uint32_t)(BIT9 | BIT10), + USBD_EP_BIT_SETUP = (uint32_t)(BIT11), + USBD_EP_BIT_RXSTS = (uint32_t)(BIT12 | BIT13), + USBD_EP_BIT_RXDTOG = (uint32_t)(BIT14), + USBD_EP_BIT_CTFR = (uint32_t)(BIT15) +} USBD_EP_BIT_T; + +/** + * @brief Endpoint id + */ +typedef enum +{ + USBD_EP_0, + USBD_EP_1, + USBD_EP_2, + USBD_EP_3, + USBD_EP_4, + USBD_EP_5, + USBD_EP_6, + USBD_EP_7, +} USBD_EP_T; + +/** + * @brief Endpoint status + */ +typedef enum +{ + USBD_EP_STATUS_DISABLE = ((uint32_t)0), + USBD_EP_STATUS_STALL = ((uint32_t)1), + USBD_EP_STATUS_NAK = ((uint32_t)2), + USBD_EP_STATUS_VALID = ((uint32_t)3), +} USBD_EP_STATUS_T; + +/** + * @brief USBD Endpoint type for register + */ +typedef enum +{ + USBD_REG_EP_TYPE_BULK, + USBD_REG_EP_TYPE_CONTROL, + USBD_REG_EP_TYPE_ISO, + USBD_REG_EP_TYPE_INTERRUPT +} USBD_REG_EP_TYPE_T; + +/**@} end of group Driver_Enumerations */ + +/** @defgroup Driver_Functions Functions + @{ +*/ + +void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type); + +void USBD_SetEPKind(uint8_t ep); +void USBD_ResetEPKind(uint8_t ep); + +void USBD_ResetEPRxFlag(uint8_t ep); +void USBD_ResetEPTxFlag(uint8_t ep); + +void USBD_ToggleTx(uint8_t ep); +void USBD_ToggleRx(uint8_t ep); +void USBD_ResetTxToggle(uint8_t ep); +void USBD_ResetRxToggle(uint8_t ep); + +void USBD_SetEpAddr(uint8_t ep, uint8_t addr); + +void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status); +void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status); +void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus); + +void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt); + +void USBD_WriteDataToEP(uint8_t ep, uint8_t* wBuf, uint32_t wLen); +void USBD_ReadDataFromEP(uint8_t ep, uint8_t* rBuf, uint32_t rLen); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USB_DEVICE_H */ + +/**@} end of group Driver_Functions */ +/**@} end of group USBD_Driver */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Driver/src/drv_usb_device.c b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Driver/src/drv_usb_device.c new file mode 100644 index 0000000000..6d84210ae7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F0xx_Library/USB_Device_Lib/Driver/src/drv_usb_device.c @@ -0,0 +1,432 @@ +/*! + * @file drv_usb_device.c + * + * @brief This file contains all the functions for the USBD peripheral + * + * @version V1.0.1 + * + * @date 2022-09-20 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Includes */ +#include "drv_usb_device.h" + +/** @addtogroup USB_Driver_Library USB Driver Library + @{ +*/ + +/** @addtogroup USBD_Driver + @{ +*/ + +/** @defgroup Driver_Macros Macros + @{ +*/ + +/**@} end of group Driver_Macros */ + +/** @defgroup Driver_Enumerations Enumerations + @{ +*/ + +/**@} end of group Driver_Enumerations */ + +/** @defgroup Driver_Functions Functions + @{ +*/ + +/*! + * @brief Set Endpoint type + * + * @param ep: Endpoint number + * + * @param type: Endpoint type + * + * @retval None + */ +void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_TYPE; + reg |= type << 9; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP kind + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_SetEPKind(uint8_t ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_KIND; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset EP kind + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPKind(uint8_t ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_KIND; + + USBD->EP[ep].EP = reg; +} + + +/*! + * @brief Reset EP CTFR bit + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPRxFlag(uint8_t ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_CTFR; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset EP CTFT bit + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPTxFlag(uint8_t ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_CTFT; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Toggle Tx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ToggleTx(uint8_t ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_TXDTOG; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Toggle Rx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ToggleRx(uint8_t ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_RXDTOG; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset Toggle Tx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetTxToggle(uint8_t ep) +{ + if (USBD->EP[ep].EP_B.TXDTOG) + { + USBD_ToggleTx(ep); + } +} + +/*! + * @brief Reset Toggle Rx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetRxToggle(uint8_t ep) +{ + if (USBD->EP[ep].EP_B.RXDTOG) + { + USBD_ToggleRx(ep); + } +} + +/*! + * @brief Set EP address + * + * @param ep: Endpoint number + * + * @param addr: Address + * + * @retval None + */ +void USBD_SetEpAddr(uint8_t ep, uint8_t addr) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_ADDR; + reg |= addr; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Tx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status) +{ + __IOM uint32_t reg; + + status <<= 4; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS); + reg ^= ((uint32_t)status & (uint32_t)USBD_EP_BIT_TXSTS); + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Rx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status) +{ + __IOM uint32_t reg; + uint32_t tmp; + + tmp = status << 12; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS); + reg ^= (tmp & USBD_EP_BIT_RXSTS); + + USBD->EP[ep].EP = reg; +} + + +/*! + * @brief Set EP Tx and Rx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus) +{ + __IOM uint32_t reg; + uint32_t tmp; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS | USBD_EP_BIT_TXSTS); + + tmp = rxStatus << 12; + reg ^= (tmp & USBD_EP_BIT_RXSTS); + + tmp = txStatus << 4; + reg ^= (tmp & USBD_EP_BIT_TXSTS); + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Rx Count + * + * @param ep: Endpoint number + * + * @param cnt: Rx count + * + * @retval None + */ +void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt) +{ + __IOM uint16_t* p; + __IOM uint16_t block = 0; + + p = USBD_ReadEPRxCntPointer(ep); + + if (cnt > 62) + { + block = cnt >> 5; + + if (!(cnt & 0x1f)) + { + block -= 1; + } + + *p = (block << 10) | 0x8000; + } + else + { + block = cnt >> 1; + + if (cnt & 0x01) + { + block += 1; + } + + *p = (block << 10); + } +} + +/*! + * @brief Write a buffer of data to a selected endpoint + * + * @param ep: Endpoint number + * + * @retval wBuf: The pointer to the buffer of data to be written to the endpoint + * + * @param wLen: Number of data to be written (in bytes) + * + * @retval None + */ +void USBD_WriteDataToEP(uint8_t ep, uint8_t* wBuf, uint32_t wLen) +{ + uint32_t i; +#ifdef APM32F0xx_USB + uint16_t* epAddr; + uint16_t tmp; +#else + uint32_t* epAddr; + uint32_t tmp; +#endif + + wLen = (wLen + 1) >> 1; + + epAddr = USBD_ReadEPTxBufferPointer(ep); + + for (i = 0; i < wLen; i++) + { + tmp = *wBuf++; + tmp = ((*wBuf++) << 8) | tmp; + + *epAddr++ = tmp; + } +} + +/*! + * @brief Read a buffer of data to a selected endpoint + * + * @param ep: Endpoint number + * + * @retval wBuf: The pointer to the buffer of data to be read to the endpoint + * + * @param wLen: Number of data to be read (in bytes) + * + * @retval None + */ +void USBD_ReadDataFromEP(uint8_t ep, uint8_t* rBuf, uint32_t rLen) +{ +#ifdef APM32F0xx_USB + uint16_t* epAddr; +#else + uint32_t* epAddr; +#endif + uint32_t i, tmp, cnt; + + cnt = rLen >> 1; + + epAddr = USBD_ReadEPRxBufferPointer(ep); + + for (i = 0; i < cnt; i++) + { + tmp = *epAddr++; + *rBuf++ = tmp & 0xFF; + *rBuf++ = (tmp >> 8) & 0xFF; + } + + if (rLen & 1) + { + tmp = *epAddr; + *rBuf = tmp & 0xFF; + } +} + +/**@} end of group Driver_Functions */ +/**@} end of group USBD_Driver */ +/**@} end of group USB_Driver_Library */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/inc/apm32f10x_eth.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/inc/apm32f10x_eth.h new file mode 100644 index 0000000000..4694e2ffcc --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/inc/apm32f10x_eth.h @@ -0,0 +1,1406 @@ +/*! + * @file apm32f10x_eth.c + * + * @brief This file provides all the ETH firmware functions + * + * @version V1.0.3 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2021-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F10x_ETH_H +#define __APM32F10x_ETH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes */ +#include "apm32f10x.h" + +/** @addtogroup APM32F10x_ETHDriver + @{ +*/ + +/** @addtogroup ETH_Driver + @{ +*/ + +/** @defgroup ETH_Enumerations + @{ +*/ + +/** + * @brief ETH AutoNegotiation + */ +typedef enum +{ + ETH_AUTONEGOTIATION_DISABLE, /*!< Disable negotiation */ + ETH_AUTONEGOTIATION_ENABLE /*!< Enable negotiation */ +} ETH_AUTONEGOTIATION_T; + +/** + * @brief ETH Watchdog + */ +typedef enum +{ + ETH_WATCHDOG_ENABLE, /*!< Enable watch dog */ + ETH_WATCHDOG_DISABLE /*!< Disable watch dog */ +} ETH_WATCHDOG_T; + +/** + * @brief ETH Jabber + */ +typedef enum +{ + ETH_JABBER_ENABLE, /*!< Enable jabber */ + ETH_JABBER_DISABLE /*!< Disable jabber */ +} ETH_JABBER_T; + +/** + * @brief ETH Inter Frame Gap + */ +typedef enum +{ + ETH_INTERFRAMEGAP_96BIT = 0x00, /*!< Inter-Frame gap = 96-bit */ + ETH_INTERFRAMEGAP_88BIT = 0x01, /*!< Inter-Frame gap = 88-bit */ + ETH_INTERFRAMEGAP_80BIT = 0x02, /*!< Inter-Frame gap = 80-bit */ + ETH_INTERFRAMEGAP_72BIT = 0x03, /*!< Inter-Frame gap = 72-bit */ + ETH_INTERFRAMEGAP_64BIT = 0x04, /*!< Inter-Frame gap = 64-bit */ + ETH_INTERFRAMEGAP_56BIT = 0x05, /*!< Inter-Frame gap = 56-bit */ + ETH_INTERFRAMEGAP_48BIT = 0x06, /*!< Inter-Frame gap = 48-bit */ + ETH_INTERFRAMEGAP_40BIT = 0x07 /*!< Inter-Frame gap = 40-bit */ +} ETH_INTERFRAMEGAP_T; + +/** + * @brief ETH Carrier Sense + */ +typedef enum +{ + ETH_CARRIERSENCE_ENABLE, /*!< Disable carrier sense during transmission */ + ETH_CARRIERSENCE_DISABLE /*!< Ignore MII CRS signal */ +} ETH_CARRIERSENCE_T; + +/** + * @brief ETH Speed + */ +typedef enum +{ + ETH_SPEED_10M, /*!< 10M speed */ + ETH_SPEED_100M /*!< 100M speed */ +} ETH_SPEED_T; + +/** + * @brief ETH Receive Own + */ +typedef enum +{ + ETH_RECEIVEOWN_ENABLE, /*!< Enable receive own */ + ETH_RECEIVEOWN_DISABLE /*!< Disable receive own */ +} ETH_RECEIVEOWN_T; + +/** + * @brief ETH Loop Back Mode + */ +typedef enum +{ + ETH_LOOPBACKMODE_DISABLE, /*!< Disable loopback mode */ + ETH_LOOPBACKMODE_ENABLE /*!< Enable loopback mode */ +} ETH_LOOPBACKMODE_T; + +/** + * @brief ETH Duplex Mode + */ +typedef enum +{ + ETH_MODE_HALFDUPLEX, /*!< Half-Duplex */ + ETH_MODE_FULLDUPLEX /*!< Full-Duplex */ +} ETH_MODE_T; + +/** + * @brief ETH Checksum Offload + */ +typedef enum +{ + ETH_CHECKSUMOFFLAOD_DISABLE, /*!< Disable IPv4 checksum offload */ + ETH_CHECKSUMOFFLAOD_ENABLE /*!< Enable Ipv4 checksum offload */ +} ETH_CHECKSUMOFFLAOD_T; + +/** + * @brief ETH Retry Transmission + */ +typedef enum +{ + ETH_RETRYTRANSMISSION_ENABLE, /*!< Enable retry */ + ETH_RETRYTRANSMISSION_DISABLE /*!< Disable retry */ +} ETH_RETRYTRANSMISSION_T; + +/** + * @brief ETH Automatic Pad CRC Strip + */ +typedef enum +{ + ETH_AUTOMATICPADCRCSTRIP_DISABLE, /*!< Disable automatic pad or CRC stripping */ + ETH_AUTOMATICPADCRCSTRIP_ENABLE /*!< Enable automatic pad or CRC stripping */ +} ETH_AUTOMATICPADCRCSTRIP_T; + +/** + * @brief ETH Back Off Limit + */ +typedef enum +{ + ETH_BACKOFFLIMIT_10, /*!< Set back off limit to 10 */ + ETH_BACKOFFLIMIT_8, /*!< Set back off limit to 18 */ + ETH_BACKOFFLIMIT_4, /*!< Set back off limit to 4 */ + ETH_BACKOFFLIMIT_1 /*!< Set back off limit to 1 */ +} ETH_BACKOFFLIMIT_T; + +/** + * @brief ETH Deferral Check + */ +typedef enum +{ + ETH_DEFFERRALCHECK_DISABLE, /*!< Disable deferral check */ + ETH_DEFFERRALCHECK_ENABLE /*!< Enable deferral check */ +} ETH_DEFFERRALCHECK_T; + +/** + * @brief ETH Receive All + */ +typedef enum +{ + ETH_RECEIVEAll_DISABLE, /*!< Disable receive all */ + ETH_RECEIVEALL_ENABLE /*!< Enable receive all */ +} ETH_RECEIVEAll_T; + +/** + * @brief ETH Source Addr Filter + */ +typedef enum +{ + ETH_SOURCEADDRFILTER_DISABLE, /*!< Disable source address filter */ + ETH_SOURCEADDRFILTER_NORMAL_ENABLE = BIT9, /*!< Enable normal source address filter */ + ETH_SOURCEADDRFILTER_INVERSE_ENABLE = BIT8 | BIT9, /*!< Enable inverse source address filter */ +} ETH_SOURCEADDRFILTER_T; + +/** + * @brief ETH Pass Control Frames + */ +typedef enum +{ + ETH_PASSCONTROLFRAMES_BLOCKALL = 1, /*!< Even if all control frames except pause frames fail the + address filter, MAC forwards them to the application */ + ETH_PASSCONTROLFRAMES_FORWARDALL, /*!< MAC forwards control frames to the application even if + they do not pass the address filter */ + ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER /*!< MAC forwards control frames that pass through the address filter */ +} ETH_PASSCONTROLFRAMES_T; + +/** + * @brief ETH Broadcast Frames Reception + */ +typedef enum +{ + ETH_BROADCASTFRAMESRECEPTION_ENABLE, /*!< Enable broadcast frames */ + ETH_BROADCASTFRAMESRECEPTION_DISABLE /*!< Disable broadcast frames */ +} ETH_BROADCASTFRAMESRECEPTION_T; + +/** + * @brief ETH Destination Addr Filter + */ +typedef enum +{ + ETH_DESTINATIONADDRFILTER_NORMAL, /*!< Normal destination address filter */ + ETH_DESTINATIONADDRFILTER_INVERSE /*!< Inverse destination address filter */ +} ETH_DESTINATIONADDRFILTER_T; + +/** + * @brief ETH Destination Addr Filter + */ +typedef enum +{ + ETH_PROMISCUOUS_MODE_DISABLE, /*!< Disable promiscuous mode */ + ETH_PROMISCUOUS_MODE_ENABLE /*!< Enable promiscuous mode */ +} ETH_PROMISCUOUS_MODE_T; + +/** + * @brief ETH Multicast Frames Filter + */ +typedef enum +{ + ETH_MULTICASTFRAMESFILTER_PERFECT, /*!< Multicast perfect filter */ + ETH_MULTICASTFRAMESFILTER_NONE = BIT4, /*!< Multicast pass all multicast */ + ETH_MULTICASTFRAMESFILTER_HASHTABLE = BIT2, /*!< Multicast hash multicast */ + ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE = BIT2 | BIT10 /*!< Multicast perfect hash table */ +} ETH_MULTICASTFRAMESFILTER_T; + +/** + * @brief ETH Unicast Frames Filter + */ +typedef enum +{ + ETH_UNICASTFRAMESFILTER_PERFECT, /*!< Unicast perfect filter */ + ETH_UNICASTFRAMESFILTER_HASHTABLE = BIT1, /*!< Unicast hash table */ + ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE = BIT1 | BIT10 /*!< Unicast perfect hash table */ +} ETH_UNICASTFRAMESFILTER_T; + +/** + * @brief ETH Zero Quanta Pause + */ +typedef enum +{ + ETH_ZEROQUANTAPAUSE_ENABLE, /*!< Enable zero-quanta pause */ + ETH_ZEROQUANTAPAUSE_DISABLE /*!< Disable zero-quanta pause */ +} ETH_ZEROQUANTAPAUSE_T; + +/** + * @brief ETH Pause Low Threshold + */ +typedef enum +{ + ETH_PAUSELOWTHRESHOLD_MINUS4, /*!< Minus 4 slot-time */ + ETH_PAUSELOWTHRESHOLD_MINUS28, /*!< Minus 28 slot-time */ + ETH_PAUSELOWTHRESHOLD_MINUS144, /*!< Minus 144 slot-time */ + ETH_PAUSELOWTHRESHOLD_MINUS256 /*!< Minus 256 slot-time */ +} ETH_PAUSELOWTHRESHOLD_T; + +/** + * @brief ETH Unicast Pause Frame Detect + */ +typedef enum +{ + ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, /*!< Disable unicast pause frame detect */ + ETH_UNICASTPAUSEFRAMEDETECT_ENABLE /*!< Enable unicast pause frame detect */ +} ETH_UNICASTPAUSEFRAMEDETECT_T; + +/** + * @brief ETH Receive Flow Control + */ +typedef enum +{ + ETH_RECEIVEFLOWCONTROL_DISABLE, /*!< Disable receive flow control */ + ETH_RECEIVEFLOWCONTROL_ENABLE /*!< Enable receive flow control */ +} ETH_RECEIVEFLOWCONTROL_T; + +/** + * @brief ETH Transmit Flow Control + */ +typedef enum +{ + ETH_TRANSMITFLOWCONTROL_DISABLE, /*!< Disable transmit flow control */ + ETH_TRANSMITFLOWCONTROL_ENABLE /*!< Enable transmit flow control */ +} ETH_TRANSMITFLOWCONTROL_T; + +/** + * @brief ETH VLAN Tag Comparison + */ +typedef enum +{ + ETH_VLANTAGCOMPARISON_16BIT, /*!< 16-bit VLAN tag comparison */ + ETH_VLANTAGCOMPARISON_12BIT /*!< 12-bit VLAN tag comparison */ +} ETH_VLANTAGCOMPARISON_T; + +/** + * @brief ETH MAC Flags + */ +typedef enum +{ + ETH_MAC_FLAG_TST = 0x00000200, /*!< Time stamp trigger flag */ + ETH_MAC_FLAG_MMCT = 0x00000040, /*!< MMC transmit flag */ + ETH_MAC_FLAG_MMCR = 0x00000020, /*!< MMC receive flag */ + ETH_MAC_FLAG_MMC = 0x00000010, /*!< MMC flag */ + ETH_MAC_FLAG_PMT = 0x00000008 /*!< PMT flag */ +} ETH_MAC_FLAG_T; + +/** + * @brief ETH MAC Interrupts + */ +typedef enum +{ + ETH_MAC_INT_TST = 0x00000200, /*!< Time stamp trigger interrupt */ + ETH_MAC_INT_MMCT = 0x00000040, /*!< MMC transmit interrupt */ + ETH_MAC_INT_MMCR = 0x00000020, /*!< MMC receive interrupt */ + ETH_MAC_INT_MMC = 0x00000010, /*!< MMC interrupt */ + ETH_MAC_INT_PMT = 0x00000008 /*!< PMT interrupt */ +} ETH_MAC_INT_T; + +/** + * @brief ETH MAC Interrupts + */ +typedef enum +{ + ETH_MAC_ADDRESS0 = 0x00000000, /*!< MAC Address0 */ + ETH_MAC_ADDRESS1 = 0x00000008, /*!< MAC Address1 */ + ETH_MAC_ADDRESS2 = 0x00000010, /*!< MAC Address2 */ + ETH_MAC_ADDRESS3 = 0x00000018 /*!< MAC Address3 */ +} ETH_MAC_ADDRESS_T; + +/** + * @brief ETH MAC addresses filter SA/DA + */ +typedef enum +{ + ETH_MAC_ADDRESSFILTER_SA, /*!< MAC Address is used to compare with the + SA fields of the received frame */ + ETH_MAC_ADDRESSFILTER_DA = BIT30 /*!< MAC Address is used to compare with the + DA fields of the received frame */ +} ETH_MAC_ADDRESSFILTER_T; + +/** + * @brief ETH MAC addresses filter Mask bytes + */ +typedef enum +{ + ETH_MAC_ADDRESSMASK_BYTE6 = 0x20000000, /*!< Mask MAC Address high reg bits [15:8] */ + ETH_MAC_ADDRESSMASK_BYTE5 = 0x10000000, /*!< Mask MAC Address high reg bits [7:0] */ + ETH_MAC_ADDRESSMASK_BYTE4 = 0x08000000, /*!< Mask MAC Address low reg bits [31:24] */ + ETH_MAC_ADDRESSMASK_BYTE3 = 0x04000000, /*!< Mask MAC Address low reg bits [23:16] */ + ETH_MAC_ADDRESSMASK_BYTE2 = 0x02000000, /*!< Mask MAC Address low reg bits [15:8] */ + ETH_MAC_ADDRESSMASK_BYTE1 = 0x01000000 /*!< Mask MAC Address low reg bits [70] */ +} ETH_MAC_ADDRESSMASK_T; + +/** + * @brief DMA Tx descriptor flags + */ +typedef enum +{ + ETH_DMATXDESC_OWN = (int)0x80000000, /*!< Descriptor is owned by DMA engine */ + ETH_DMATXDESC_INTC = 0x40000000, /*!< Interrupt on completion */ + ETH_DMATXDESC_LS = 0x20000000, /*!< Last Segment */ + ETH_DMATXDESC_FS = 0x10000000, /*!< First Segment */ + ETH_DMATXDESC_DISC = 0x08000000, /*!< Disable CRC */ + ETH_DMATXDESC_DISP = 0x04000000, /*!< Disable Pad */ + ETH_DMATXDESC_TXTSEN = 0x02000000, /*!< Transmit Time Stamp Enable */ + ETH_DMATXDESC_TXENDR = 0x00200000, /*!< Transmit End of Ring */ + ETH_DMATXDESC_TXCH = 0x00100000, /*!< Second Address Chained */ + ETH_DMATXDESC_TXTSS = 0x00020000, /*!< Tx Time Stamp Status */ + ETH_DMATXDESC_IHERR = 0x00010000, /*!< IP Header Error */ + ETH_DMATXDESC_ERRS = 0x00008000, /*!< Error summary */ + ETH_DMATXDESC_JTO = 0x00004000, /*!< Jabber Timeout */ + ETH_DMATXDESC_FF = 0x00002000, /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ + ETH_DMATXDESC_IPERR = 0x00001000, /*!< Payload Checksum Error */ + ETH_DMATXDESC_LSC = 0x00000800, /*!< Loss of Carrier: carrier lost during transmission */ + ETH_DMATXDESC_NC = 0x00000400, /*!< No Carrier: no carrier signal from the transceiver */ + ETH_DMATXDESC_LC = 0x00000200, /*!< Late Collision: transmission aborted due to collision */ + ETH_DMATXDESC_EC = 0x00000100, /*!< Excessive Collision: transmission aborted after 16 collisions */ + ETH_DMATXDESC_VLANF = 0x00000080, /*!< VLAN Frame */ + ETH_DMATXDESC_CCNT = 0x00000078, /*!< Collision Count */ + ETH_DMATXDESC_EDEF = 0x00000004, /*!< Excessive Deferral */ + ETH_DMATXDESC_UFERR = 0x00000002, /*!< Underflow Error: late data arrival from the memory */ + ETH_DMATXDESC_DEF = 0x00000001 /*!< Deferred Bit */ +} ETH_DMATXDESC_FLAG_T; + +/** + * @brief ETH DMA Tx descriptor segment + */ +typedef enum +{ + ETH_DMATXDESC_LASTSEGMENTS = BIT30, /*!< Actual Tx desc contain last segment */ + ETH_DMATXDESC_FIRSTSEGMENT = BIT29 /*!< Actual Tx desc contain first segment */ +} ETH_DMATXDESC_SEGMENTS_T; + +/** + * @brief ETH DMA Tx descriptor Checksum Insertion Control + */ +typedef enum +{ + ETH_DMATXDESC_CHECKSUMBYPASS, /*!< Checksum bypass */ + ETH_DMATXDESC_CHECKSUMIPV4HEADER = BIT22, /*!< IPv4 header checksum */ + ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT = BIT23, /*!< TCP/UDP/ICMP checksum. Pseudo header + checksum is assumed to be present */ + ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL = BIT22 | BIT23 /*!< TCP/UDP/ICMP checksum fully in hardware + including pseudo header */ +} ETH_DMATXDESC_CHECKSUMB_T; + +/** + * @brief DMA Rx descriptor status + */ +typedef enum +{ + ETH_DMARXDESC_OWN = (int)0x80000000U, /*!< Descriptor is owned by DMA engine */ + ETH_DMARXDESC_ADDRF = 0x40000000, /*!< DA Filter Fail for the rx frame */ + ETH_DMARXDESC_ERRS = 0x00008000, /*!< Error summary */ + ETH_DMARXDESC_DESERR = 0x00004000, /*!< Descriptor error: no more descriptors for receive frame */ + ETH_DMARXDESC_SADDRF = 0x00002000, /*!< SA Filter Fail for the received frame */ + ETH_DMARXDESC_LERR = 0x00001000, /*!< Frame size not matching with length field */ + ETH_DMARXDESC_OFERR = 0x00000800, /*!< Overflow Error: Frame was damaged due to buffer overflow */ + ETH_DMARXDESC_VLANF = 0x00000400, /*!< VLAN Tag: received frame is a VLAN frame */ + ETH_DMARXDESC_FDES = 0x00000200, /*!< First descriptor of the frame */ + ETH_DMARXDESC_LDES = 0x00000100, /*!< Last descriptor of the frame */ + ETH_DMARXDESC_IPV4HCE = 0x00000080, /*!< IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */ + ETH_DMARXDESC_LC = 0x00000040, /*!< Late collision occurred during reception */ + ETH_DMARXDESC_FT = 0x00000020, /*!< Frame type - Ethernet, otherwise 802.3 */ + ETH_DMARXDESC_RXWDTTO = 0x00000010, /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ + ETH_DMARXDESC_RERR = 0x00000008, /*!< Receive error: error reported by MII interface */ + ETH_DMARXDESC_DERR = 0x00000004, /*!< Dribble bit error: frame contains non int multiple of 8 bits */ + ETH_DMARXDESC_CERR = 0x00000002, /*!< CRC error */ + ETH_DMARXDESC_MAMPCE = 0x00000001 /*!< Rx MAC Address/Payload Checksum Error: + Rx MAC address matched/ Rx Payload Checksum Error */ +} ETH_DMARXDESC_FLAG_T; + +/** + * @brief DMA Rx descriptor extended flags + */ +typedef enum +{ + ETH_DMAPTPRXDESC_PTPV = 0x00002000, /*!< PTP version */ + ETH_DMAPTPRXDESC_PTPFT = 0x00001000, /*!< PTP frame type */ + ETH_DMAPTPRXDESC_PTPMT = 0x00000F00, /*!< PTP message type */ + ETH_DMAPTPRXDESC_IPV6P = 0x00000080, /*!< IPv6 packet received */ + ETH_DMAPTPRXDESC_IPV4P = 0x00000040, /*!< IPv4 packet received */ + ETH_DMAPTPRXDESC_IPCBP = 0x00000020, /*!< IP checksum bypassed */ + ETH_DMAPTPRXDESC_IPPERR = 0x00000010, /*!< IP payload error */ + ETH_DMAPTPRXDESC_IPHERR = 0x00000008, /*!< IP header error */ + ETH_DMAPTPRXDESC_IPPT = 0x00000007 /*!< IP payload type */ +} ETH_DMAPTPRXDESC_FLAG_T; + +/** + * @brief ETH DMA Rx descriptor buffers + */ +typedef enum +{ + ETH_DMARXDESC_BUFFER1, /*!< DMA Rx Desc Buffer1 */ + ETH_DMARXDESC_BUFFER2 /*!< DMA Rx Desc Buffer2 */ +} ETH_DMARXDESC_BUFFER_T; + +/** + * @brief ETH Drop TCP IP Checksum Error Frame + */ +typedef enum +{ + ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE, /*!< Enable dropping of TCP/IP checksum error frame */ + ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE /*!< Disable dropping of TCP/IP checksum error frame */ +} ETH_DROPTCPIPCHECKSUMERRORFRAME_T; + +/** + * @brief ETH Receive Store Forward + */ +typedef enum +{ + ETH_RECEIVESTOREFORWARD_DISABLE, /*!< Disable receive store and forward */ + ETH_RECEIVESTOREFORWARD_ENABLE /*!< Enable receive store and forward */ +} ETH_RECEIVESTOREFORWARD_T; + +/** + * @brief ETH Flush Received Frame + */ +typedef enum +{ + ETH_FLUSHRECEIVEDFRAME_ENABLE, /*!< Enable flushing of received frames */ + ETH_FLUSHRECEIVEDFRAME_DISABLE /*!< Disable flushing of received frames */ +} ETH_FLUSHRECEIVEDFRAME_T; + +/** + * @brief ETH Transmit Store Forward + */ +typedef enum +{ + ETH_TRANSMITSTOREFORWARD_DISABLE, /*!< Disable transmit store and forward */ + ETH_TRANSMITSTOREFORWARD_ENABLE /*!< Enable transmit store and forward */ +} ETH_TRANSMITSTOREFORWARD_T; + +/** + * @brief ETH Transmit Threshold Control + */ +typedef enum +{ + ETH_TRANSMITTHRESHOLDCONTROL_64BYTES, /*!< Select 64 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_128BYTES, /*!< Select 128 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_192BYTES, /*!< Select 192 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_256BYTES, /*!< Select 256 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_40BYTES, /*!< Select 40 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_32BYTES, /*!< Select 32 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_24BYTES, /*!< Select 24 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_16BYTES /*!< Select 16 bytes transmit threshild level */ +} ETH_TRANSMITTHRESHOLDCONTROL_T; + +/** + * @brief ETH Forward Error Frames + */ +typedef enum +{ + ETH_FORWARDERRORFRAMES_DISABLE, /*!< Disable forward error frames */ + ETH_FORWARDERRORFRAMES_ENABLE /*!< Enable forward error frames */ +} ETH_FORWARDERRORFRAMES_T; + +/** + * @brief ETH Forward Undersized Good Frames + */ +typedef enum +{ + ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE, /*!< Disable forward undersized good frames */ + ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE /*!< Enable forward undersized good frames */ +} ETH_FORWARDUNDERSIZEDGOODFRAMES_T; + +/** + * @brief ETH Receive Threshold Control + */ +typedef enum +{ + ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES, /*!< Select 64 bytes receive threshold level */ + ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES, /*!< Select 32 bytes receive threshold level */ + ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES, /*!< Select 96 bytes receive threshold level */ + ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES /*!< Select 128 bytes receive threshold level */ +} ETH_RECEIVEDTHRESHOLDCONTROL_T; + +/** + * @brief ETH Second Frame Operate + */ +typedef enum +{ + ETH_SECONDFRAMEOPERARTE_DISABLE, /*!< Disable second frame operate */ + ETH_SECONDFRAMEOPERARTE_ENABLE /*!< Enable second frame operate */ +} ETH_SECONDFRAMEOPERARTE_T; + +/** + * @brief ETH Address Aligned Beats + */ +typedef enum +{ + ETH_ADDRESSALIGNEDBEATS_DISABLE, /*!< Disable address aligned beats */ + ETH_ADDRESSALIGNEDBEATS_ENABLE /*!< Enable address aligned beats */ +} ETH_ADDRESSALIGNEDBEATS_T; + +/** + * @brief ETH Fixed Burst + */ +typedef enum +{ + ETH_FIXEDBURST_DISABLE, /*!< Disable fixed burst */ + ETH_FIXEDBURST_ENABLE /*!< Enable fixed burst */ +} ETH_FIXEDBURST_T; + +/** + * @brief ETH Rx DMA Burst Length + */ +typedef enum +{ + ETH_RXDMABURSTLENGTH_1BEAT = BIT17, /*!< Maxnum number of Rx DMA transaction = 1 beat */ + ETH_RXDMABURSTLENGTH_2BEAT = BIT18, /*!< Maxnum number of Rx DMA transaction = 2 beat */ + ETH_RXDMABURSTLENGTH_4BEAT = BIT19, /*!< Maxnum number of Rx DMA transaction = 4 beat */ + ETH_RXDMABURSTLENGTH_8BEAT = BIT20, /*!< Maxnum number of Rx DMA transaction = 8 beat */ + ETH_RXDMABURSTLENGTH_16BEAT = BIT21, /*!< Maxnum number of Rx DMA transaction = 16 beat */ + ETH_RXDMABURSTLENGTH_32BEAT = BIT22, /*!< Maxnum number of Rx DMA transaction = 32 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_4BEAT = BIT17 | BIT24, /*!< Maxnum number of Rx DMA transaction = 4 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_8BEAT = BIT18 | BIT24, /*!< Maxnum number of Rx DMA transaction = 8 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_16BEAT = BIT19 | BIT24, /*!< Maxnum number of Rx DMA transaction = 16 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_32BEAT = BIT20 | BIT24, /*!< Maxnum number of Rx DMA transaction = 32 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_64BEAT = BIT21 | BIT24, /*!< Maxnum number of Rx DMA transaction = 64 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_128BEAT = BIT22 | BIT24 /*!< Maxnum number of Rx DMA transaction = 128 beat */ +} ETH_RXDMABURSTLENGTH_T; + +/** + * @brief ETH Tx DMA Burst Length + */ +typedef enum +{ + ETH_TXDMABURSTLENGTH_1BEAT = BIT8, /*!< Maxnum number of Tx DMA transaction = 1 beat */ + ETH_TXDMABURSTLENGTH_2BEAT = BIT9, /*!< Maxnum number of Tx DMA transaction = 2 beat */ + ETH_TXDMABURSTLENGTH_4BEAT = BIT10, /*!< Maxnum number of Tx DMA transaction = 4 beat */ + ETH_TXDMABURSTLENGTH_8BEAT = BIT11, /*!< Maxnum number of Tx DMA transaction = 8 beat */ + ETH_TXDMABURSTLENGTH_16BEAT = BIT12, /*!< Maxnum number of Tx DMA transaction = 16 beat */ + ETH_TXDMABURSTLENGTH_32BEAT = BIT13, /*!< Maxnum number of Tx DMA transaction = 32 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_4BEAT = BIT8 | BIT24, /*!< Maxnum number of Tx DMA transaction = 4 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_8BEAT = BIT9 | BIT24, /*!< Maxnum number of Tx DMA transaction = 8 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_16BEAT = BIT10 | BIT24, /*!< Maxnum number of Tx DMA transaction = 16 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_32BEAT = BIT11 | BIT24, /*!< Maxnum number of Tx DMA transaction = 32 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_64BEAT = BIT12 | BIT24, /*!< Maxnum number of Tx DMA transaction = 64 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_128BEAT = BIT13 | BIT24 /*!< Maxnum number of Tx DMA transaction = 128 beat */ +} ETH_TXDMABURSTLENGTH_T; + +/** + * @brief ETH DMA Arbitration + */ +typedef enum +{ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1, /*!< Priority ratio RX : TX = 1 : 1 */ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 = BIT14, /*!< Priority ratio RX : TX = 2 : 1 */ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 = BIT15, /*!< Priority ratio RX : TX = 3 : 1 */ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 = BIT14 | BIT15, /*!< Priority ratio RX : TX = 4 : 1 */ + ETH_DMAARBITRATION_RXPRIORTX = BIT1 /*!< Rx priority ratio higher than Tx */ +} ETH_DMAARBITRATION_T; + +/** + * @brief ETH DMA Flags + */ +typedef enum +{ + ETH_DMA_FLAG_TST = 0x20000000, /*!< Time-stamp trigger interrupt (on DMA) */ + ETH_DMA_FLAG_PMT = 0x10000000, /*!< PMT interrupt (on DMA) */ + ETH_DMA_FLAG_MMC = 0x08000000, /*!< MMC interrupt (on DMA) */ + ETH_DMA_FLAG_DATATRANSFERERROR = 0x00800000, /*!< Error bits 0-Rx DMA, 1-Tx DMA */ + ETH_DMA_FLAG_READWRITEERROR = 0x01000000, /*!< Error bits 0-write transfer, 1-read transfer */ + ETH_DMA_FLAG_ACCESSERROR = 0x02000000, /*!< Error bits 0-data buffer, 1-desc. access */ + ETH_DMA_FLAG_NIS = 0x00010000, /*!< Normal interrupt summary flag */ + ETH_DMA_FLAG_AIS = 0x00008000, /*!< Abnormal interrupt summary flag */ + ETH_DMA_FLAG_ER = 0x00004000, /*!< Early receive flag */ + ETH_DMA_FLAG_FBE = 0x00002000, /*!< Fatal bus error flag */ + ETH_DMA_FLAG_ET = 0x00000400, /*!< Early transmit flag */ + ETH_DMA_FLAG_RWT = 0x00000200, /*!< Receive watchdog timeout flag */ + ETH_DMA_FLAG_RPS = 0x00000100, /*!< Receive process stopped flag */ + ETH_DMA_FLAG_RBU = 0x00000080, /*!< Receive buffer unavailable flag */ + ETH_DMA_FLAG_RX = 0x00000040, /*!< Receive flag */ + ETH_DMA_FLAG_TU = 0x00000020, /*!< Underflow flag */ + ETH_DMA_FLAG_RO = 0x00000010, /*!< Overflow flag */ + ETH_DMA_FLAG_TJT = 0x00000008, /*!< Transmit jabber timeout flag */ + ETH_DMA_FLAG_TBU = 0x00000004, /*!< Transmit buffer unavailable flag */ + ETH_DMA_FLAG_TPS = 0x00000002, /*!< Transmit process stopped flag */ + ETH_DMA_FLAG_TX = 0x00000001 /*!< Transmit flag */ +} ETH_DMA_FLAG_T; + +/** + * @brief ETH DMA Interrupts + */ +typedef enum +{ + ETH_DMA_INT_TST = 0x20000000, /*!< Time-stamp trigger interrupt (on DMA) */ + ETH_DMA_INT_PMT = 0x10000000, /*!< PMT interrupt (on DMA) */ + ETH_DMA_INT_MMC = 0x08000000, /*!< MMC interrupt (on DMA) */ + ETH_DMA_INT_NIS = 0x00010000, /*!< Normal interrupt summary */ + ETH_DMA_INT_AIS = 0x00008000, /*!< Abnormal interrupt summary */ + ETH_DMA_INT_ER = 0x00004000, /*!< Early receive interrupt */ + ETH_DMA_INT_FBE = 0x00002000, /*!< Fatal bus error interrupt */ + ETH_DMA_INT_ET = 0x00000400, /*!< Early transmit interrupt */ + ETH_DMA_INT_RWT = 0x00000200, /*!< Receive watchdog timeout interrupt */ + ETH_DMA_INT_RPS = 0x00000100, /*!< Receive process stopped interrupt */ + ETH_DMA_INT_RBU = 0x00000080, /*!< Receive buffer unavailable interrupt */ + ETH_DMA_INT_RX = 0x00000040, /*!< Receive interrupt */ + ETH_DMA_INT_TU = 0x00000020, /*!< Underflow interrupt */ + ETH_DMA_INT_RO = 0x00000010, /*!< Overflow interrupt */ + ETH_DMA_INT_TJT = 0x00000008, /*!< Transmit jabber timeout interrupt */ + ETH_DMA_INT_TBU = 0x00000004, /*!< Transmit buffer unavailable interrupt */ + ETH_DMA_INT_TPS = 0x00000002, /*!< Transmit process stopped interrupt */ + ETH_DMA_INT_TX = 0x00000001 /*!< Transmit interrupt */ +} ETH_DMA_INT_T; + +/** + * @brief ETH DMA transmit process state + */ +typedef enum +{ + ETH_DMA_TRANSMITPROCESS_STOPPED, /*!< Stopped - Reset or Stop Tx Command issued */ + ETH_DMA_TRANSMITPROCESS_FETCHING, /*!< Running - fetching the Tx descriptor */ + ETH_DMA_TRANSMITPROCESS_WAITING, /*!< Running - waiting for status */ + ETH_DMA_TRANSMITPROCESS_READING, /*!< Running - reading the data from host memory */ + ETH_DMA_TRANSMITPROCESS_SUSPENDED = 0x06, /*!< Suspended - Tx Descriptor unavailable */ + ETH_DMA_TRANSMITPROCESS_CLOSING = 0x07, /*!< Running - closing Rx descriptor */ +} ETH_DMA_TRANSMITPROCESS_T; + +/** + * @brief ETH DMA receive process state + */ +typedef enum +{ + ETH_DMA_RECEIVEPROCESS_STOPPED, /*!< Stopped - Reset or Stop Rx Command issued */ + ETH_DMA_RECEIVEPROCESS_FETCHING = 0x02, /*!< Running - fetching the Rx descriptor */ + ETH_DMA_RECEIVEPROCESS_WAITING = 0x06, /*!< Running - waiting for packet */ + ETH_DMA_RECEIVEPROCESS_SUSPENDED = 0x08, /*!< Suspended - Rx Descriptor unavailable */ + ETH_DMA_RECEIVEPROCESS_CLOSING = 0x0A, /*!< Running - closing descriptor */ + ETH_DMA_RECEIVEPROCESS_QUEUING = 0x0E /*!< Running - queuing the receive frame into host memory */ +} ETH_DMA_RECEIVEPROCESS_T; + +/** + * @brief ETH DMA overflow + */ +typedef enum +{ + ETH_DMA_OVERFLOW_RXFIFOCOUNTER = BIT28, /*!< Overflow for FIFO Overflows Counter */ + ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER = BIT16 /*!< Overflow for Buffer Unavailable Missed Frame Counter */ +} ETH_DMA_OVERFLOW_T; + +/** + * @brief ETH PMT Flags + */ +typedef enum +{ + ETH_PMT_FLAG_WUFFRPR = (int)BIT31, /*!< Wake-Up Frame Filter Register Pointer Reset */ + ETH_PMT_FLAG_WUFR = BIT6, /*!< Wake-Up Frame Received */ + ETH_PMT_FLAG_MPR = BIT5 /*!< Magic Packet Received */ +} ETH_PMT_FLAG_T; + +/** + * @brief ETH MMC Tx/RX Interrupts + */ +typedef enum +{ + ETH_MMC_INT_TGF = BIT21, /*!< When Tx good frame counter reaches half the maximum value */ + ETH_MMC_INT_TGFMSC = BIT15, /*!< When Tx good multi col counter reaches half the maximum value */ + ETH_MMC_INT_TGFSC = BIT14, /*!< When Tx good single col counter reaches half the maximum value */ + ETH_MMC_INT_RGUF = BIT21 | BIT30, /*!< When Rx good unicast frames counter reaches half the maximum value */ + ETH_MMC_INT_RFAE = BIT6 | BIT30, /*!< When Rx alignment error counter reaches half the maximum value */ + ETH_MMC_INT_RFCE = BIT5 | BIT30 /*!< When Rx crc error counter reaches half the maximum value */ +} ETH_MMC_INT_T; + +/** + * @brief ETH MMC Registers + */ +typedef enum +{ + ETH_MMC_CTRL = 0x00000100, /*!< MMC CTRL register */ + ETH_MMC_RXINT = 0x00000104, /*!< MMC RXINT register */ + ETH_MMC_TXINT = 0x00000108, /*!< MMC TXINT register */ + ETH_MMC_RXINTMASK = 0x0000010C, /*!< MMC RXINTMASK register */ + ETH_MMC_TXINTMASK = 0x00000110, /*!< MMC TXINTMASK register */ + ETH_MMC_TXGFSCCNT = 0x0000014C, /*!< MMC TXGFSCCNT register */ + ETH_MMC_TXGFMCCNT = 0x00000150, /*!< MMC TXGFMCCNT register */ + ETH_MMC_TXGFCNT = 0x00000168, /*!< MMC TXGFCNT register */ + ETH_MMC_RXFCECNT = 0x00000194, /*!< MMC RXFCECNT register */ + ETH_MMC_RXFAECNT = 0x00000198, /*!< MMC RXFAECNT register */ + ETH_MMC_RXGUNCNT = 0x000001C4 /*!< MMC RXGUNCNT register */ +} ETH_MMC_REG_T; + +/**@} end of group ETH_Enumerations*/ + + +/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + * @{ + */ + +/** +* DMA Tx Descriptor +* ----------------------------------------------------------------------------------------------- +* TXDES0 | OWN(31) | CTRL[30:25] | Reserved(24) | CTRL[23:20] | Reserved[19:18] | Status[17:0] | +* ----------------------------------------------------------------------------------------------- +* TXDES1 | Reserved[31:29] | Buffer2 Size[28:16] | Reserved[15:13] | Buffer1 Size[12:0] | +* ----------------------------------------------------------------------------------------------- +* TXDES2 | Buffer1 Address [31:0] | +* ----------------------------------------------------------------------------------------------- +* TXDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | +* ----------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of TXDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_INTC 0x40000000U /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ +#define ETH_DMATXDESC_DISC 0x08000000U /*!< Disable CRC */ +#define ETH_DMATXDESC_DISP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXDESC_TXTSEN 0x02000000U /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TXENDR 0x00200000U /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TXCH 0x00100000U /*!< Second Address Chained */ +#define ETH_DMATXDESC_TXTSS 0x00020000U /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHERR 0x00010000U /*!< IP Header Error */ +#define ETH_DMATXDESC_ERRS 0x00008000U /*!< Error summary: OR of the following bits: UFERR || EDEF || EC || LC || NC || LSC || FF || JTO */ +#define ETH_DMATXDESC_JTO 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_IPERR 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LSC 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LC 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VLANF 0x00000080U /*!< VLAN Frame */ +#define ETH_DMATXDESC_CCNT 0x00000078U /*!< Collision Count */ +#define ETH_DMATXDESC_EDEF 0x00000004U /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UFERR 0x00000002U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DEF 0x00000001U /*!< Deferred Bit */ + +/** + * @brief Bit definition of TXDES1 register + */ +#define ETH_DMATXDESC_TXBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TXBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TXDES2 register + */ +#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TXDES3 register + */ +#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + +/** +* --------------------------------------------------------------------------------------------- +* TXDES6 | Transmit Time Stamp Low [31:0] | +* --------------------------------------------------------------------------------------------- +* TXDES7 | Transmit Time Stamp High [31:0] | +* ---------------------------------------------------------------------------------------------- +*/ + +/* Bit definition of TXDES6 register */ +#define ETH_DMAPTPTXDESC_TXTSL 0xFFFFFFFFU /*!< Transmit Time Stamp Low */ + +/* Bit definition of TXDES7 register */ +#define ETH_DMAPTPTXDESC_TXTSH 0xFFFFFFFFU /*!< Transmit Time Stamp High */ + +/** + * @} + */ +/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + * @{ + */ + +/** + *DMA Rx Descriptor + *-------------------------------------------------------------------------------------------------------------------- + *RXDES0 | OWN(31) | Status [30:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES1 | CTRL(31) | Reserved[30:29] | Buffer2 Size[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 Size[12:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES2 | Buffer1 Address [31:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + *--------------------------------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RXDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_ADDRF 0x40000000U /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ERRS 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DESERR 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SADDRF 0x00002000U /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LERR 0x00001000U /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OFERR 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLANF 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FDES 0x00000200U /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LDES 0x00000100U /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RXWWTTO 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RERR 0x00000008U /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DERR 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CERR 0x00000002U /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RXDES1 register + */ +#define ETH_DMARXDESC_DINTC 0x80000000U /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RXBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RXER 0x00008000U /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RXCH 0x00004000U /*!< Second Address Chained */ +#define ETH_DMARXDESC_RXBS1 0x00001FFFU /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RXDES2 register + */ +#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RXDES3 register + */ +#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + +/** + *--------------------------------------------------------------------------------------------------------------------- + *RXDES4 | Reserved[31:14] | Extended Status [13:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES5 | Reserved[31:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES6 | Receive Time Stamp Low [31:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES7 | Receive Time Stamp High [31:0] | + *--------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit definition of RXDES4 register */ +#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /*!< PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /*!< PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /*!< PTP Message Type */ +#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /*!< SYNC message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /*!< FollowUp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /*!< DelayReq message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /*!< DelayResp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /*!< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /*!< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /*!< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6P 0x00000080U /*!< IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4P 0x00000040U /*!< IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCBP 0x00000020U /*!< IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPERR 0x00000010U /*!< IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHERR 0x00000008U /*!< IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /*!< IP Payload Type */ +#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /*!< UDP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /*!< TCP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /*!< ICMP payload encapsulated in the IP datagram */ + +/* Bit definition of RXDES6 register */ +#define ETH_DMAPTPRXDESC_RXTSL 0xFFFFFFFFU /*!< Receive Time Stamp Low */ + +/* Bit definition of RXDES7 register */ +#define ETH_DMAPTPRXDESC_RXTSH 0xFFFFFFFFU /*!< Receive Time Stamp High */ +/** + * @} + */ + + +/** @addtogroup ETH_Macros Macros + *@{ + */ + +/* ETH Frames defines */ + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /*!< buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /*!< buffer size for transmit */ +#define ETH_RXBUFNB (5U) /*!< 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB (5U) /*!< 5 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* ETH_Buffers_setting ETH Buffers setting */ +#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ + +/** +* Ethernet driver receive buffers are organized in a chained linked-list, when +* an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO +* to the driver receive buffers memory. +* +* Depending on the size of the received ethernet packet and the size of +* each ethernet driver receive buffer, the received packet can take one or more +* ethernet driver receive buffer. +* +* In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE +* and the total count of the driver receive buffers ETH_RXBUFNB. +* +* The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as +* example, they can be reconfigured in the application layer to fit the application +* needs +*/ + +/** Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet +* packet +*/ +#ifndef ETH_RX_BUF_SIZE +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ +#ifndef ETH_RXBUFNB +#define ETH_RXBUFNB 5U /*!< 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +/** +* Ethernet driver transmit buffers are organized in a chained linked-list, when +* an ethernet packet is transmitted, Tx-DMA will transfer the packet from the +* driver transmit buffers memory to the TxFIFO. +* +* Depending on the size of the Ethernet packet to be transmitted and the size of +* each ethernet driver transmit buffer, the packet to be transmitted can take +* one or more ethernet driver transmit buffer. +* +* In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE +* and the total count of the driver transmit buffers ETH_TXBUFNB. +* +* The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as +* example, they can be reconfigured in the application layer to fit the application +* needs +*/ + +/** Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet +* packet +*/ +#ifndef ETH_TX_BUF_SIZE +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ +#ifndef ETH_TXBUFNB +#define ETH_TXBUFNB 5U /*!< 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#endif + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /*!< ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /*!< ETHERNET MAC address low offset */ + +/* ETHERNET Errors */ +#define ETH_SUCCESS 1U +#define ETH_ERROR 0U + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U + +/* ETHERNET DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U + +/* ETHERNET MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U + +/* ETHERNET MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK 0xFF20010FU + +/* ETHERNET MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U + +/* ETHERNET DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U + +/* PHY registers defines */ + +/* PHY Read write Timeouts */ +#define PHY_READ_TIMEOUT ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TIMEOUT ((uint32_t)0x0004FFFF) + +/* PHY Register address */ +#define PHY_BCR 0 /*!< Transceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Transceiver Basic Status Register */ +#define PHY_SR 16 /*!< Transceiver Status Register for dp83848 */ + +/* PHY Status Register (PHYSTS), address 0x10 */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< for dp83848 ((uint16_t)0x0010) */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< for dp83848 ((uint16_t)0x0004) */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* PHY basic Control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTAET_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +/* PHY Delay */ +#define PHY_RESET_DELAY ((uint32_t)0x000FFFFF) /*!< PHY reset delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF) /*!< PHY configuration delay */ +/* Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY ((uint32_t)0x0000FFFF) + +/* Ethernet MAC MII Address Clock Range*/ +#define ETH_MACMIIAR_CR_DIV42 ((uint8_t)0x00) /*!< HCLK:60-100 MHz; MDC clock = HCLK/42 */ +#define ETH_MACMIIAR_CR_DIV62 ((uint8_t)0x01) /*!< HCLK:100-150 MHz; MDC clock = HCLK/62 */ +#define ETH_MACMIIAR_CR_DIV16 ((uint8_t)0x02) /*!< HCLK:20-35 MHz; MDC clock = HCLK/16 */ +#define ETH_MACMIIAR_CR_DIV26 ((uint8_t)0x03) /*!< HCLK:35-60 MHz; MDC clock = HCLK/26 */ +#define ETH_MACMIIAR_CR_DIV102 ((uint8_t)0x04) /*!< HCLK:150-168 MHz; MDC clock = HCLK/102 */ + +/**@} end of group ETH_Macros */ + + +/** @addtogroup ETH_Structure Data Structure + @{ +*/ + +/** + * @brief ETH MAC Config structure types + */ +typedef struct +{ + /* MAC Configuration */ + ETH_AUTONEGOTIATION_T autoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex) */ + + ETH_WATCHDOG_T watchDog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. */ + + ETH_JABBER_T jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. */ + ETH_INTERFRAMEGAP_T interFrameGap; /*!< Selects the minimum IFG between frames during transmission */ + + ETH_CARRIERSENCE_T carrierSense; /*!< Selects or not the Carrier Sense */ + + ETH_SPEED_T speed; /*!< Sets the Ethernet speed: 10/100 Mbps */ + + ETH_RECEIVEOWN_T receiveOwn; /*!< Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode */ + + ETH_LOOPBACKMODE_T loopbackMode; /*!< Selects or not the internal MAC MII Loopback mode */ + + ETH_MODE_T mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + + ETH_CHECKSUMOFFLAOD_T checksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. */ + + ETH_RETRYTRANSMISSION_T retryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a collision occurs (Half-Duplex mode) */ + + ETH_AUTOMATICPADCRCSTRIP_T automaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping */ + + ETH_BACKOFFLIMIT_T backOffLimit; /*!< Selects the BackOff limit value */ + + ETH_DEFFERRALCHECK_T deferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) */ + + ETH_RECEIVEAll_T receiveAll; /*!< Selects or not all frames reception by the MAC (No filtering) */ + + ETH_SOURCEADDRFILTER_T sourceAddrFilter; /*!< Selects the Source Address Filter mode */ + + ETH_PASSCONTROLFRAMES_T passControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) */ + + ETH_BROADCASTFRAMESRECEPTION_T broadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames */ + + ETH_DESTINATIONADDRFILTER_T destinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames */ + + ETH_PROMISCUOUS_MODE_T promiscuousMode; /*!< Selects or not the Promiscuous Mode */ + + ETH_MULTICASTFRAMESFILTER_T multicastFramesFilter; /*!< Selects the Multicast Frames filter mode */ + + ETH_UNICASTFRAMESFILTER_T unicastFramesFilter; /*!< Selects the Unicast Frames filter mode */ + + + uint32_t hashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ + + uint32_t hashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ + + uint32_t pauseTime; /*!< This field holds the (value<=0xFFFF) to be used in the Pause Time */ + + ETH_ZEROQUANTAPAUSE_T zeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames */ + + ETH_PAUSELOWTHRESHOLD_T pauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame */ + + ETH_UNICASTPAUSEFRAMEDETECT_T unicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) */ + + ETH_RECEIVEFLOWCONTROL_T receiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) */ + + ETH_TRANSMITFLOWCONTROL_T transmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) */ + + ETH_VLANTAGCOMPARISON_T VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering */ + + uint32_t VLANTagIdentifier; /*!< Holds the (value <=0xFFFF) VLAN tag identifier for receive frames */ + + /* DMA Configuration */ + ETH_DROPTCPIPCHECKSUMERRORFRAME_T dropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */ + + ETH_RECEIVESTOREFORWARD_T receiveStoreForward; /*!< Enables or disables the Receive store and forward mode */ + + ETH_FLUSHRECEIVEDFRAME_T flushReceivedFrame; /*!< Enables or disables the flushing of received frames */ + + ETH_TRANSMITSTOREFORWARD_T transmitStoreForward; /*!< Enables or disables Transmit store and forward mode */ + + ETH_TRANSMITTHRESHOLDCONTROL_T transmitThresholdControl; /*!< Selects or not the Transmit Threshold Control */ + + ETH_FORWARDERRORFRAMES_T forwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames */ + + ETH_FORWARDUNDERSIZEDGOODFRAMES_T forwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) */ + + ETH_RECEIVEDTHRESHOLDCONTROL_T receiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ + + ETH_SECONDFRAMEOPERARTE_T secondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. */ + + ETH_ADDRESSALIGNEDBEATS_T addressAlignedBeats; /*!< Enables or disables the Address Aligned Beats */ + + ETH_FIXEDBURST_T fixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers */ + + ETH_RXDMABURSTLENGTH_T rxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction */ + + ETH_TXDMABURSTLENGTH_T txDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction */ + + uint32_t descriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) (value <= 0x1F) */ + + ETH_DMAARBITRATION_T DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration */ +} ETH_Config_T; + +/** + * @brief ETH DMA Descriptors data structure types + */ +typedef struct +{ + __IO uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + /* Enhanced ETHERNET DMA PTP Descriptors */ +} ETH_DMADescConfig_T; + +/** + * @brief ETH DMA Descriptors data structure types + */ +typedef struct +{ + uint32_t length; /*!< Data length */ + uint32_t buffer; /*!< Data buffer */ + __IO ETH_DMADescConfig_T* descriptor; /*!< DMA descriptor */ +} ETH_Frame_T; + +/** + * @brief ETH DMA Descriptors Received Frame Informations structure types + */ +typedef struct +{ + __IO ETH_DMADescConfig_T* FS_RxDesc; /*!< First Segment Rx Desc */ + __IO ETH_DMADescConfig_T* LS_RxDesc; /*!< Last Segment Rx Desc */ + __IO uint32_t segCount; /*!< Segment count */ +} ETH_DMARxFrameInformations; + +/**@} end of group ETH_Structure*/ + +/** @defgroup ETH_Functions + @{ +*/ + +/* ETH Configuration */ +void ETH_Reset(void); +void ETH_ConfigStructInit(ETH_Config_T* ethConfig); +uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr); +void ETH_SoftwareReset(void); +uint8_t ETH_ReadSoftwareReset(void); +void ETH_Start(void); +void ETH_Stop(void); +uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T* DMARxDesc); + +/* PHY */ +uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg); +uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data); +uint32_t ETH_EnablePHYLoopBack(uint16_t addr); +uint32_t ETH_DisablePHYLoopBack(uint16_t addr); + +/* MAC */ +void ETH_EnableMACTransmission(void); +void ETH_DisableMACTransmission(void); +void ETH_EnableMACReceiver(void); +void ETH_DisableMACReceiver(void); +uint8_t ETH_ReadFlowControlBusyStatus(void); +void ETH_SetPauseControlFrame(void); +void ETH_EnableBackPressureActivation(void); +void ETH_DisableBackPressureActivation(void); +uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag); +void ETH_EnableMACInterrupt(uint32_t interrupt); +void ETH_DisableMACInterrupt(uint32_t interrupt); +void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr); +void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr); +void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr); +void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr); +void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter); +void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte); + +/* DMA descriptors */ +void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T* DMARxDescTab, uint8_t* rxBuff, uint32_t rxBuffcount); +void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T* DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount); +uint32_t ETH_CheckReceivedFrame(void); +uint32_t ETH_Transmit_Descriptors(u16 frameLength); +ETH_Frame_T ETH_ReadReceivedFrame(void); +uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_FLAG_T flag); +uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T* DMATxDesc); +void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T* DMATxDesc); +void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc); +void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc); +void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment); +void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum); +void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc); +void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc); +void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc); +void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc); +void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc); +void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc); +void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T* DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2); +uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_FLAG_T flag); + +void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T* DMARxDesc); +uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T* DMARxDesc); +void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMARxDesc); +void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMATxDesc); +uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer); +ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void); + +/* DMA */ +uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag); +void ETH_ClearDMAFlag(uint32_t flag); +uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag); +void ETH_ClearDMAIntFlag(uint32_t flag); +uint32_t ETH_ReadTransmitProcessState(void); +uint32_t ETH_ReadReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +uint8_t ETH_ReadFlushTransmitFIFOStatus(void); +void ETH_EnableDMATransmission(void); +void ETH_DisableDMATransmission(void); +void ETH_EnableDMAReceiver(void); +void ETH_DisableDMAReceiver(void); +void ETH_EnableDMAInterrupt(uint32_t interrupt); +void ETH_DisableDMAInterrupt(uint32_t interrupt); +uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow); +uint32_t ETH_ReadRxOverflowMissedFrameCounter(void); +uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_ReadCurrentTxDescStartAddress(void); +uint32_t ETH_ReadCurrentRxDescStartAddress(void); +uint32_t ETH_ReadCurrentTxBufferAddress(void); +uint32_t ETH_ReadCurrentRxBufferAddress(void); +void ETH_ResetDMATransmission(void); +void ETH_ResetDMAReception(void); + +/* PMT */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_EnableGlobalUnicastWakeUp(void); +void ETH_DisableGlobalUnicastWakeUp(void); +uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag); +void ETH_EnableWakeUpFrameDetection(void); +void ETH_DisableWakeUpFrameDetection(void); +void ETH_EnableMagicPacketDetection(void); +void ETH_DisableMagicPacketDetection(void); +void ETH_EnablePowerDown(void); +void ETH_DisablePowerDown(void); + +/* MMC */ +void ETH_EnableMMCCounterFreeze(void); +void ETH_DisableMMCCounterFreeze(void); +void ETH_EnableMMCResetOnRead(void); +void ETH_DisableMMCResetOnRead(void); +void ETH_EnableMMCCounterRollover(void); +void ETH_DisableMMCCounterRollover(void); +void ETH_ResetMMCCounters(void); +void ETH_EnableMMCInterrupt(uint32_t interrupt); +void ETH_DisableMMCInterrupt(uint32_t interrupt); +uint8_t ETH_ReadMMCIntFlag(uint32_t flag); +uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg); + +/**@} end of group ETH_Functions */ +/**@} end of group ETH_Driver */ +/**@} end of group APM32F10x_ETHDriver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10x_ETH_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/src/apm32f10x_eth.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/src/apm32f10x_eth.c new file mode 100644 index 0000000000..46842e2a0a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/src/apm32f10x_eth.c @@ -0,0 +1,2203 @@ +/*! + * @file apm32f10x_eth.c + * + * @brief This file provides all the ETH firmware functions + * + * @version V1.0.3 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2021-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#if defined(APM32F10X_CL) + +#include "apm32f10x_eth.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup APM32F10x_ETHDriver + @{ +*/ + +/** @defgroup ETH_Driver + * @brief ETH driver modules + @{ +*/ + +#if defined (__CC_ARM) /*!< ARM Compiler */ + __align(4) + ETH_DMADescConfig_T DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */ + __align(4) + ETH_DMADescConfig_T DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */ + __align(4) + uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /*!< Ethernet Receive Buffer */ + __align(4) + uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /*!< Ethernet Transmit Buffer */ + +#elif defined ( __ICCARM__ ) + + ETH_DMADescConfig_T DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */ + ETH_DMADescConfig_T DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */ + uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /*!< Ethernet Receive Buffer */ + uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /*!< Ethernet Transmit Buffer */ + +#elif defined (__GNUC__) /*!< GNU Compiler */ +ETH_DMADescConfig_T DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /*!< Ethernet Rx MA Descriptor */ +ETH_DMADescConfig_T DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /*!< Ethernet Tx DMA Descriptor */ +uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4))); /*!< Ethernet Receive Buffer */ +uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4))); /*!< Ethernet Transmit Buffer */ + +#endif + +/** @defgroup Global_Definition + @{ +*/ + +/* Global pointers on Tx and Rx descriptor used to transmit and receive descriptors */ +__IO ETH_DMADescConfig_T* DMATxDescToSet; +__IO ETH_DMADescConfig_T* DMARxDescToGet; + +/* Structure used to hold the last received packet descriptors info */ +ETH_DMARxFrameInformations RxFrameDescriptor; +__IO ETH_DMARxFrameInformations* DMARxFraminfos; +__IO uint32_t FrameRxindex; + +/** + * @} + */ + +/** @defgroup ETH_Functions + @{ +*/ + +/*! + * @brief Inserts a delay time. + * + * @param count: specifies the delay time length. + * + * @retval None + */ +static void ETH_Delay(__IO uint32_t count) +{ + __IO uint32_t i = 0; + for (i = count; i != 0; i--) + { + } +} + +/* ETH Configuration */ + +/*! + * @brief Reset ETH peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void ETH_Reset(void) +{ + RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_ETH_MAC); + + RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_ETH_MAC); +} + +/*! + * @brief Config ETH_Config_T member with its default value. + * + * @param ethConfig: pointer to a ETH_Config_T structure which will be initialized. + * + * @retval None + */ +void ETH_ConfigStructInit(ETH_Config_T* ethConfig) +{ + /* MAC Configuration */ + ethConfig->autoNegotiation = ETH_AUTONEGOTIATION_ENABLE; + ethConfig->watchDog = ETH_WATCHDOG_ENABLE; + ethConfig->jabber = ETH_JABBER_ENABLE; + ethConfig->interFrameGap = ETH_INTERFRAMEGAP_96BIT; + ethConfig->carrierSense = ETH_CARRIERSENCE_ENABLE; + ethConfig->speed = ETH_SPEED_100M; + ethConfig->receiveOwn = ETH_RECEIVEOWN_ENABLE; + ethConfig->loopbackMode = ETH_LOOPBACKMODE_DISABLE; + ethConfig->mode = ETH_MODE_FULLDUPLEX; + ethConfig->checksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + ethConfig->retryTransmission = ETH_RETRYTRANSMISSION_ENABLE; + ethConfig->automaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + ethConfig->backOffLimit = ETH_BACKOFFLIMIT_10; + ethConfig->deferralCheck = ETH_DEFFERRALCHECK_DISABLE; + ethConfig->receiveAll = ETH_RECEIVEAll_DISABLE; + ethConfig->sourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; + ethConfig->passControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; + ethConfig->broadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_DISABLE; + ethConfig->destinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; + ethConfig->promiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + ethConfig->multicastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + ethConfig->unicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; + ethConfig->hashTableHigh = 0x0000; + ethConfig->hashTableLow = 0x0000; + ethConfig->pauseTime = 0x0000; + ethConfig->zeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; + ethConfig->pauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + ethConfig->unicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; + ethConfig->receiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; + ethConfig->transmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; + ethConfig->VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; + ethConfig->VLANTagIdentifier = 0x0000; + /* DMA Configuration */ + ethConfig->dropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE; + ethConfig->receiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + ethConfig->flushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; + ethConfig->transmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + ethConfig->transmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + ethConfig->forwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + ethConfig->forwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + ethConfig->receiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + ethConfig->secondFrameOperate = ETH_SECONDFRAMEOPERARTE_DISABLE; + ethConfig->addressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + ethConfig->fixedBurst = ETH_FIXEDBURST_ENABLE; + ethConfig->rxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + ethConfig->txDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + ethConfig->descriptorSkipLength = 0x00; + ethConfig->DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; +} + +/*! + * @brief Config the ETH peripheral parameters in the ethConfig. + * + * @param ethConfig: pointer to a ETH_Config_T structure. + * + * @param addr: external PHY address + * + * @retval ETH_ERROR: Ethernet initialization error + * ETH_SUCCESS: Ethernet initialization success + */ +uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr) +{ + uint32_t regValue = 0; + uint32_t hclk = 60000000; + __IO uint32_t timeout = 0, err = ETH_SUCCESS; + + hclk = RCM_ReadHCLKFreq(); + + if ((hclk >= 20000000) && (hclk <= 35000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV16; + } + else if ((hclk >= 35000000) && (hclk < 60000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV26; + } + else if ((hclk >= 60000000) && (hclk < 100000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV42; + } + else if ((hclk >= 100000000) && (hclk < 150000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV62; + } + else + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV102; + } + + /* PHY initialization and configuration */ + if (!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_RESET))) + { + /* Return ERROR in case of write timeout */ + err = ETH_ERROR; + goto error; + } + + ETH_Delay(PHY_RESET_DELAY); + + if (ethConfig->autoNegotiation == ETH_AUTONEGOTIATION_ENABLE) + { + /* Wait for linked status */ + do + { + timeout++ ; + } + while (!(ETH_ReadPHYRegister(addr, PHY_BSR) & PHY_LINKED_STATUS) && (timeout < PHY_READ_TIMEOUT)); + + /* Return ERROR in case of timeout */ + if (timeout == PHY_READ_TIMEOUT) + { + err = ETH_ERROR; + goto error; + } + + timeout = 0; + /* Enable Auto-Negotiation */ + if (!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_AUTONEGOTIATION))) + { + /* Return ERROR in case of write timeout */ + err = ETH_ERROR; + } + + /* Wait until the auto-negotiation will be completed */ + do + { + timeout++; + } + while (!(ETH_ReadPHYRegister(addr, PHY_BSR) & PHY_AUTONEGO_COMPLETE) && (timeout < (uint32_t)PHY_READ_TIMEOUT)); + + /* Return ERROR in case of timeout */ + if (timeout == PHY_READ_TIMEOUT) + { + err = ETH_ERROR; + goto error; + } + + timeout = 0; + /* Read the result of the auto-negotiation */ + regValue = ETH_ReadPHYRegister(addr, PHY_SR); + + if ((regValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) + { + ethConfig->mode = ETH_MODE_FULLDUPLEX; + } + else + { + ethConfig->mode = ETH_MODE_HALFDUPLEX; + } + if (regValue & PHY_SPEED_STATUS) + { + ethConfig->speed = ETH_SPEED_10M; + } + else + { + ethConfig->speed = ETH_SPEED_100M; + } + } + else + { + if (!ETH_WritePHYRegister(addr, PHY_BCR, ((uint16_t)(ethConfig->speed << 8) | + (uint16_t)(ethConfig->mode << 13)))) + { + err = ETH_ERROR; + } + + ETH_Delay(PHY_CONFIG_DELAY); + } +error: + if (err == ETH_ERROR) + { + ethConfig->speed = ETH_SPEED_100M; + ethConfig->mode = ETH_MODE_FULLDUPLEX; + } + + /* ETHERNET MAC_CFG Configuration */ + ETH->CFG_B.WDTDIS = ethConfig->watchDog; + ETH->CFG_B.JDIS = ethConfig->jabber; + ETH->CFG_B.IFG = ethConfig->interFrameGap; + ETH->CFG_B.DISCRS = ethConfig->carrierSense; + ETH->CFG_B.SSEL = ethConfig->speed; + ETH->CFG_B.DISRXO = ethConfig->receiveOwn; + ETH->CFG_B.LBM = ethConfig->loopbackMode; + ETH->CFG_B.DM = ethConfig->mode; + ETH->CFG_B.IPC = ethConfig->checksumOffload; + ETH->CFG_B.DISR = ethConfig->retryTransmission; + ETH->CFG_B.ACS = ethConfig->automaticPadCRCStrip; + ETH->CFG_B.BL = ethConfig->backOffLimit; + ETH->CFG_B.DC = ethConfig->deferralCheck; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET MAC_FRAF Configuration */ + ETH->FRAF_B.RXA = ethConfig->receiveAll; + ETH->FRAF |= ethConfig->sourceAddrFilter; + ETH->FRAF_B.PCTRLF = ethConfig->passControlFrames; + ETH->FRAF_B.DISBF = ethConfig->broadcastFramesReception; + ETH->FRAF_B.DAIF = ethConfig->destinationAddrFilter; + ETH->FRAF_B.PR = ethConfig->promiscuousMode; + ETH->FRAF |= ethConfig->multicastFramesFilter; + ETH->FRAF |= ethConfig->unicastFramesFilter; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET MAC_HTH/HTL Configuration */ + ETH->HTH = ethConfig->hashTableHigh; + ETH->HTL = ethConfig->hashTableLow; + + /* ETHERNET MAC_FCTRL Configuration */ + ETH->FCTRL_B.PT = ethConfig->pauseTime; + ETH->FCTRL_B.ZQPDIS = ethConfig->zeroQuantaPause; + ETH->FCTRL_B.PTSEL = ethConfig->pauseLowThreshold; + ETH->FCTRL_B.UNPFDETE = ethConfig->unicastPauseFrameDetect; + ETH->FCTRL_B.RXFCTRLEN = ethConfig->receiveFlowControl; + ETH->FCTRL_B.TXFCTRLEN = ethConfig->transmitFlowControl; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET MAC_VLANT Configuration */ + ETH->VLANT_B.VLANTCOMP = ethConfig->VLANTagComparison; + ETH->VLANT_B.VLANTID = ethConfig->VLANTagIdentifier; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET DMA_OPMOD Configuration */ + ETH->DMAOPMOD_B.DISDT = ethConfig->dropTCPIPChecksumErrorFrame; + ETH->DMAOPMOD_B.RXSF = ethConfig->receiveStoreForward; + ETH->DMAOPMOD_B.DISFRXF = ethConfig->flushReceivedFrame; + ETH->DMAOPMOD_B.TXSF = ethConfig->transmitStoreForward; + ETH->DMAOPMOD_B.TXTHCTRL = ethConfig->transmitThresholdControl; + ETH->DMAOPMOD_B.FERRF = ethConfig->forwardErrorFrames; + ETH->DMAOPMOD_B.FUF = ethConfig->forwardUndersizedGoodFrames; + ETH->DMAOPMOD_B.RXTHCTRL = ethConfig->receiveThresholdControl; + ETH->DMAOPMOD_B.OSECF = ethConfig->secondFrameOperate; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET DMA_BMOD Configuration */ + ETH->DMABMOD = RESET; + ETH->DMABMOD_B.AAL = ethConfig->addressAlignedBeats; + ETH->DMABMOD_B.FB = ethConfig->fixedBurst; + ETH->DMABMOD |= ethConfig->rxDMABurstLength; + ETH->DMABMOD |= ethConfig->txDMABurstLength; + ETH->DMABMOD_B.DSL = ethConfig->descriptorSkipLength; + ETH->DMABMOD |= ethConfig->DMAArbitration; + ETH->DMABMOD_B.USP = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); + + if (err == ETH_SUCCESS) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/*! + * @brief Resets all MAC subsystem internal registers and logic. + * + * @param None + * + * @retval None + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMOD_B.SWR = SET; +} + +/*! + * @brief Read the ETH software reset bit. + * + * @param None + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadSoftwareReset(void) +{ + return ETH->DMABMOD_B.SWR; +} + +/*! + * @brief Enables ETH MAC and DMA reception/transmission + * + * @param None + * + * @retval None + */ +void ETH_Start(void) +{ + ETH_EnableMACTransmission(); + ETH_EnableMACReceiver(); + ETH_FlushTransmitFIFO(); + ETH_EnableDMATransmission(); + ETH_EnableDMAReceiver(); +} + +/*! + * @brief Disables ETH MAC and DMA reception/transmission + * + * @param None + * + * @retval None + */ +void ETH_Stop(void) +{ + ETH_DisableDMATransmission(); + ETH_DisableDMAReceiver(); + ETH_DisableMACReceiver(); + ETH_FlushTransmitFIFO(); + ETH_DisableMACTransmission(); +} + +/*! + * @brief Read the size of the received packet. + * + * @param None + * + * @retval frameLength: received packet size + */ +uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T* DMARxDesc) +{ + uint32_t frameLength = 0; + if (((DMARxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) && + ((DMARxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET)) + { + frameLength = ETH_ReadDMARxDescFrameLength(DMARxDesc); + } + return frameLength; +} + +/* PHY functions */ + +/*! + * @brief Read a PHY register + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + * + * @param reg: PHY register + * This parameter can be one of the following values: + * @arg PHY_BCR : Transceiver Basic Control Register + * @arg PHY_BSR : Transceiver Basic Status Register + * @arg PHY_SR : Transceiver Status Register + * + * @retval ETH_ERROR: in case of timeout + * MAC DATA register value: Data read from the selected PHY register + */ +uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg) +{ + __IO uint32_t timeout = 0; + + ETH->ADDR_B.PA = addr; + ETH->ADDR_B.MR = reg; + ETH->ADDR_B.MW = RESET; + ETH->ADDR_B.MB = SET; + /* Check for the Busy flag */ + do + { + timeout++ ; + } + while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_READ_TIMEOUT)); + /* Return ERROR in case of timeout */ + if (timeout == PHY_READ_TIMEOUT) + { + return ETH_ERROR; + } + /* Return data register value */ + return (uint16_t)(ETH->DATA); +} + +/*! + * @brief Write to a PHY register + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + + * @param reg: PHY register + * This parameter can be one of the following values: + * @arg PHY_BCR : Transceiver Basic Control Register + + * @param data: the data to write + * + * @retval ETH_ERROR: write timeout + * ETH_SUCCESS: write success + */ +uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data) +{ + __IO uint32_t timeout = 0; + + ETH->DATA = data; + ETH->ADDR_B.PA = addr; + ETH->ADDR_B.MR = reg; + ETH->ADDR_B.MW = SET; + ETH->ADDR_B.MB = SET; + + /* Check for the Busy flag */ + do + { + timeout++ ; + } + while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_WRITE_TIMEOUT)); + /* Return ERROR in case of timeout */ + if (timeout == PHY_WRITE_TIMEOUT) + { + return ETH_ERROR; + } + /* Return data register value */ + return ETH_SUCCESS; +} + +/*! + * @brief Enable the PHY loopBack mode. + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + * + * @retval ETH_ERROR or ETH_SUCCESS + */ +uint32_t ETH_EnablePHYLoopBack(uint16_t addr) +{ + uint16_t temp = 0; + + temp = ETH_ReadPHYRegister(addr, PHY_BCR); + temp |= PHY_LOOPBACK; + + if (ETH_WritePHYRegister(addr, PHY_BCR, temp) == SET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/*! + * @brief Disable the PHY loopBack mode. + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + * + * @retval ETH_ERROR or ETH_SUCCESS + */ +uint32_t ETH_DisablePHYLoopBack(uint16_t addr) +{ + uint16_t temp = 0; + + temp = ETH_ReadPHYRegister(addr, PHY_BCR); + temp &= ((uint16_t)~PHY_LOOPBACK); + + if (ETH_WritePHYRegister(addr, PHY_BCR, temp) == SET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/* MAC functions */ + +/*! + * @brief Enable the MAC transmission. + * + * @param None + * + * @retval None + */ +void ETH_EnableMACTransmission(void) +{ + ETH->CFG_B.TXEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC transmission. + * + * @param None + * + * @retval None + */ +void ETH_DisableMACTransmission(void) +{ + ETH->CFG_B.TXEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC receiver. + * + * @param None + * + * @retval None + */ +void ETH_EnableMACReceiver(void) +{ + ETH->CFG_B.RXEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC receiver. + * + * @param None + * + * @retval None + */ +void ETH_DisableMACReceiver(void) +{ + ETH->CFG_B.RXEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the ETH flow control busy status + * + * @param None + * + * @retval SET or RESET + */ +uint8_t ETH_ReadFlowControlBusyStatus(void) +{ + return ETH->FCTRL_B.FCTRLB; +} + +/*! + * @brief Set a Pause Control Frame (Full-duplex only). + * + * @param None + * + * @retval None + */ +void ETH_SetPauseControlFrame(void) +{ + ETH->FCTRL_B.FCTRLB = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC Back Pressure operation activation (Half-duplex only). + * + * @param None + * + * @retval None + */ +void ETH_EnableBackPressureActivation(void) +{ + ETH->FCTRL_B.FCTRLB = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Back Pressure operation activation (Half-duplex only). + * + * @param None + * + * @retval None + */ +void ETH_DisableBackPressureActivation(void) +{ + ETH->FCTRL_B.FCTRLB = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the specified ETH MAC flag + * + * @param flag: Ethernet MAC flag: + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag) +{ + return (ETH->ISTS & flag) ? SET : RESET; +} + +/*! + * @brief Enable the specified ETH MAC interrupts. + * + * @param interrupt: Ethernet MAC interrupt flag: + * This parameter can be any combination of the following values: + * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_INT_PMT : PMT interrupt + * + * @retval None + */ +void ETH_EnableMACInterrupt(uint32_t interrupt) +{ + ETH->IMASK |= interrupt; +} + +/*! + * @brief Disable the specified ETH MAC interrupts. + * + * @param interrupt: Ethernet MAC interrupt flag: + * This parameter can be any combination of the following values: + * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_INT_PMT : PMT interrupt + * + * @retval None + */ +void ETH_DisableMACInterrupt(uint32_t interrupt) +{ + ETH->IMASK &= (~(uint32_t)interrupt); +} + +/*! + * @brief Config the MAC address. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0 : MAC Address0 + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param addr: Pointer on MAC address buffer data (6 bytes). + * + * @retval None + */ +void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr) +{ + uint32_t temp; + + temp = ((uint32_t)addr[5] << 8) | (uint32_t)addr[4]; + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp; + + temp = ((uint32_t)addr[3] << 24) | ((uint32_t)addr[2] << 16) | ((uint32_t)addr[1] << 8) | addr[0]; + (*(__IO uint32_t*)(ETH_MAC_ADDR_LBASE + macAddr)) = temp; +} + +/*! + * @brief Read the MAC address. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0 : MAC Address0 + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param addr: Pointer on MAC address buffer data (6 bytes). + * + * @retval None + */ +void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr) +{ + uint32_t temp; + + temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)); + + addr[5] = ((temp >> 8) & 0xFF); + addr[4] = (temp & 0xFF); + + temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_LBASE + macAddr)); + addr[3] = ((temp >> 24) & 0xFF); + addr[2] = ((temp >> 16) & 0xFF); + addr[1] = ((temp >> 8) & 0xFF); + addr[0] = (temp & 0xFF); +} + +/*! + * @brief Enable address filters module uses the MAC address for perfect filtering. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @retval None + */ +void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr) +{ + __IO uint32_t temp = 0; + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= BIT31; + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp; +} + +/*! + * @brief Disable address filters module uses the MAC address for perfect filtering. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @retval None + */ +void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr) +{ + __IO uint32_t temp = 0; + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) &= (~BIT31); + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp; +} + +/*! + * @brief Config the filter type for the MAC address + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param filter: Comparison with the SA/DA fields of the received frame. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESSFILTER_SA : MAC Address is used to compare with the + * SA fields of the received frame. + * @arg ETH_MAC_ADDRESSFILTER_DA : MAC Address is used to compare with the + * DA fields of the received frame. + * @retval None + */ +void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter) +{ + if (filter == ETH_MAC_ADDRESSFILTER_SA) + { + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_SA; + } + else + { + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_DA; + } + +} + +/*! + * @brief Config the filter type for the ETH MAC address. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param MaskByte: specifies the used address bytes for comparison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_ADDRESSMASK_BYTE6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_ADDRESSMASK_BYTE5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_ADDRESSMASK_BYTE4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_ADDRESSMASK_BYTE3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_ADDRESSMASK_BYTE2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_ADDRESSMASK_BYTE1 : Mask MAC Address low reg bits [7:0]. + * + * @retval None + */ +void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte) +{ + __IO uint32_t temp = 0; + + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) &= (~(uint32_t)0x3F000000); + + temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)); + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp; + + /* Set the selected Filter mask bytes */ + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= maskByte; + + temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)); + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp; +} + +/* DMA Descriptors functions */ + +/*! + * @brief Config the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab: Pointer on the first Rx desc list + * + * @param rxBuff: Pointer on the first RxBuffer list + * + * @param rxBuffcount: Number of the used Rx desc in the list + * + * @retval None + */ +void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T* DMARxDescTab, uint8_t* rxBuff, uint32_t rxBuffcount) +{ + uint32_t i = 0; + ETH_DMADescConfig_T* DMARxDesc; + DMARxDescToGet = DMARxDescTab; + + for (i = 0; i < rxBuffcount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARXDESC_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RXCH | ETH_RX_BUF_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&rxBuff[i * ETH_RX_BUF_SIZE]); + if (i < (rxBuffcount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + + ETH->DMARXDLADDR = (uint32_t) DMARxDescTab; + DMARxFraminfos = &RxFrameDescriptor; +} + +/*! + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab: Pointer on the first Tx desc list + * + * @param txBuff: Pointer on the first TxBuffer list + * + * @param txBuffcount: Number of the used Tx desc in the list + * + * @retval None + */ +void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T* DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount) +{ + uint32_t i = 0; + ETH_DMADescConfig_T* DMATxDesc; + DMATxDescToSet = DMATxDescTab; + + for (i = 0; i < txBuffcount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATXDESC_TXCH; + DMATxDesc->Buffer1Addr = (uint32_t)(&txBuff[i * ETH_TX_BUF_SIZE]); + if (i < (txBuffcount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab); + } + } + + ETH->DMATXDLADDR = (uint32_t) DMATxDescTab; +} + +/*! + * @brief This function polls for a frame receiver + * + * @param None + * + * @retval Returns 1 when a frame is received, 0 if none. + */ +uint32_t ETH_CheckReceivedFrame(void) +{ + if (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET)) + { + DMARxFraminfos->segCount++; + if (DMARxFraminfos->segCount == 1) + { + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + } + DMARxFraminfos->LS_RxDesc = DMARxDescToGet; + return 1; + } + else if (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + DMARxFraminfos->LS_RxDesc = NULL; + DMARxFraminfos->segCount = 1; + DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr); + } + else if (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + (DMARxFraminfos->segCount) ++; + DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr); + } + return 0; +} + +/*! + * @brief Prepares DMA Tx descriptors to transmit an ethernet frame + * + * @param FrameLength : length of the frame to send + * + * @retval ETH_ERROR or ETH_SUCCESS + */ +uint32_t ETH_Transmit_Descriptors(u16 frameLength) +{ + uint32_t count = 0, size = 0, i = 0; + __IO ETH_DMADescConfig_T* DMATxDesc; + + if ((DMATxDescToSet->Status & ETH_DMATXDESC_OWN) == SET) + { + return ETH_ERROR; + } + + DMATxDesc = DMATxDescToSet; + + if (frameLength > ETH_TX_BUF_SIZE) + { + count = frameLength / ETH_TX_BUF_SIZE; + if (frameLength % ETH_TX_BUF_SIZE) count++; + } + else count = 1; + + if (count == 1) + { + DMATxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; + DMATxDesc->ControlBufferSize = (frameLength & ETH_DMATXDESC_TXBS1); + DMATxDesc->Status |= ETH_DMATXDESC_OWN; + DMATxDesc = (ETH_DMADescConfig_T*)(DMATxDesc->Buffer2NextDescAddr); + } + else + { + for (i = 0; i < count; i++) + { + DMATxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + + if (i == 0) + { + DMATxDesc->Status |= ETH_DMATXDESC_FS; + } + DMATxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TXBS1); + + if (i == (count - 1)) + { + DMATxDesc->Status |= ETH_DMATXDESC_LS; + size = frameLength - (count - 1) * ETH_TX_BUF_SIZE; + DMATxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TXBS1); + } + + DMATxDesc->Status |= ETH_DMATXDESC_OWN; + DMATxDesc = (ETH_DMADescConfig_T*)(DMATxDesc->Buffer2NextDescAddr); + } + } + DMATxDescToSet = DMATxDesc; + + if (ETH->DMASTS_B.TXBU == SET) + { + ETH->DMASTS = BIT2; + ETH->DMATXPD = 0; + } + + return ETH_SUCCESS; +} + +/*! + * @brief Read the received frame. + * + * @param none + * + * @retval Structure of type ETH_Frame_T + */ +ETH_Frame_T ETH_ReadReceivedFrame(void) +{ + uint32_t frameLength = 0; + ETH_Frame_T frame = {0, 0, 0}; + + frameLength = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; + frame.length = frameLength; + + frame.descriptor = DMARxFraminfos->FS_RxDesc; + frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr; + DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr); + + return (frame); +} + +/*! + * @brief Read ETH DMA Tx Descriptor flag. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param flag: Specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_OWN : Descriptor is owned by DMA engine + * @arg ETH_DMATXDESC_INTC : Interrupt on completion + * @arg ETH_DMATXDESC_LS : Last Segment + * @arg ETH_DMATXDESC_FS : First Segment + * @arg ETH_DMATXDESC_DISC : Disable CRC + * @arg ETH_DMATXDESC_DISP : Disable Pad + * @arg ETH_DMATXDESC_TXTSEN: Transmit Time Stamp Enable + * @arg ETH_DMATXDESC_TXENDR: Transmit End of Ring + * @arg ETH_DMATXDESC_TXCH : Second Address Chained + * @arg ETH_DMATXDESC_TXTSS : Tx Time Stamp Status + * @arg ETH_DMATXDESC_IHERR : IP Header Error + * @arg ETH_DMATXDESC_ERRS : Error summary + * @arg ETH_DMATXDESC_JTO : Jabber Timeout + * @arg ETH_DMATXDESC_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATXDESC_IPERR : Payload Checksum Error + * @arg ETH_DMATXDESC_LSC : Loss of Carrier: carrier lost during transmission + * @arg ETH_DMATXDESC_NC : No Carrier: no carrier signal from the transceiver + * @arg ETH_DMATXDESC_LC : Late Collision: transmission aborted due to collision + * @arg ETH_DMATXDESC_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATXDESC_VLANF : VLAN Frame + * @arg ETH_DMATXDESC_CCNT : Collision Count + * @arg ETH_DMATXDESC_EDEF : Excessive Deferral + * @arg ETH_DMATXDESC_UFERR : Underflow Error: late data arrival from the memory + * @arg ETH_DMATXDESC_DEF : Deferred Bit + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_FLAG_T flag) +{ + return (DMATxDesc->Status & flag) ? SET : RESET; +} + +/*! + * @brief Returns ETH DMA Tx Descriptor collision count. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval The Transmit descriptor collision counter value. + */ +uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T* DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATXDESC_CCNT) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/*! + * @brief Config the ETH DMA Tx Descriptor Own bit. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_OWN; +} + +/*! + * @brief Enable the ETH DMA Tx Descriptor Transmit interrupt. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_INTC; +} + +/*! + * @brief Disable the ETH DMA Tx Descriptor Transmit interrupt. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_INTC); +} + +/*! + * @brief Config Tx descriptor as last or first segment + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param frameSegment: Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_LASTSEGMENTS : Actual Tx desc contain last segment + * @arg ETH_DMATXDESC_FIRSTSEGMENT : Actual Tx desc contain first segment + * + * @retval None + */ +void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment) +{ + DMATxDesc->Status |= frameSegment; +} +/*! + * @brief Config ETH DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass + * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * + * @retval None + */ +void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum) +{ + DMATxDesc->Status |= checksum; +} + +/*! + * @brief Enable the DMA Tx Desc CRC. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISC); +} + +/*! + * @brief Disable the DMA Tx Desc CRC. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_DISC; +} + +/*! + * @brief Enable the DMA Tx Desc second address chained. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_TXCH; +} + +/*! + * @brief Disable the DMA Tx Desc second address chained. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TXCH); +} + +/*! + * @brief Enable the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISP); +} + +/*! + * @brief Disable the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_DISP; +} + +/*! + * @brief Config the ETH DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param bufferSize1: specifies the Tx desc buffer1 size. + * + * @param bufferSize2: specifies the Tx desc buffer2 size. + * + * @retval None + */ +void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T* DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2) +{ + DMATxDesc->ControlBufferSize |= (bufferSize1 | (bufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/*! + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARXDESC_OWN : Descriptor is owned by DMA engine + * @arg ETH_DMARXDESC_ADDRF : DA Filter Fail for the rx frame + * @arg ETH_DMARXDESC_ERRS : Error summary + * @arg ETH_DMARXDESC_DESERR : Descriptor error: no more descriptors for receive frame + * @arg ETH_DMARXDESC_SADDRF : SA Filter Fail for the received frame + * @arg ETH_DMARXDESC_LERR : Frame size not matching with length field + * @arg ETH_DMARXDESC_OFERR : Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARXDESC_VLANF : VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARXDESC_FDES : First descriptor of the frame + * @arg ETH_DMARXDESC_LDES : Last descriptor of the frame + * @arg ETH_DMARXDESC_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARXDESC_LC : Late collision occurred during reception + * @arg ETH_DMARXDESC_FT : Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARXDESC_RXWDTTO: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARXDESC_RERR : Receive error: error reported by MII interface + * @arg ETH_DMARXDESC_DERR : Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARXDESC_CERR : CRC error + * @arg ETH_DMARXDESC_MAMPCE : Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_FLAG_T flag) +{ + return (DMARxDesc->Status & flag) ? SET : RESET; +} + +/*! + * @brief Config the ETH DMA Rx Desc Own bit. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval None + */ +void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T* DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARXDESC_OWN; +} + +/*! + * @brief Returns the ETH DMA Rx descriptor frame length. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval The Rx descriptor received frame length. + */ +uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T* DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/*! + * @brief Enable the ETH DMA Rx Desc receive interrupt. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval None + */ +void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMARxDesc) +{ + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_DINTC); +} + +/*! + * @brief Disable the ETH DMA Rx Desc receive interrupt. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval None + */ +void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMARxDesc) +{ + DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_DINTC; +} + +/*! + * @brief Returns the ETH DMA Rx Desc buffer size. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @param buffer: specifies the DMA Rx Desc buffer. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * + * @retval The Receive descriptor frame length. + */ +uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer) +{ + if (buffer == ETH_DMARXDESC_BUFFER1) + { + return (DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS1); + } + else + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } +} + +/*! + * @brief Read frame using DMA Receive interrupt. + * it allows scanning of Rx descriptors to get the the receive frame + * + * @param None + * + * @retval Structure of type ETH_Frame_T + */ +ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void) +{ + __IO uint32_t count = 0; + ETH_Frame_T frame = {0, 0, 0}; + + while (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (count < ETH_RXBUFNB)) + { + count ++; + + if (((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + DMARxFraminfos->segCount = 1; + DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr); + } + else if (((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + (DMARxFraminfos->segCount) ++; + DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + DMARxFraminfos->LS_RxDesc = DMARxDescToGet; + (DMARxFraminfos->segCount)++; + + if ((DMARxFraminfos->segCount) == 1) + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + + frame.length = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; + + if (DMARxFraminfos->segCount > 1) + { + frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr; + } + else + { + frame.buffer = DMARxDescToGet->Buffer1Addr; + } + + frame.descriptor = DMARxFraminfos->FS_RxDesc; + DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr); + + return (frame); + } + } + return (frame); +} + +/* DMA functions */ + +/*! + * @brief Read the ETH DMA flag. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DATATRANSFERERROR : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_READWRITEERROR : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_ACCESSERROR : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RX : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_TX : Transmit flag + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag) +{ + return (ETH->DMASTS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the ETH DMA flag. + * + * @param flag: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RX : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_TX : Transmit flag + * + * @retval None + */ +void ETH_ClearDMAFlag(uint32_t flag) +{ + ETH->DMASTS = flag; +} + +/*! + * @brief Read the ETH DMA interrupt flag. + * + * @param flag: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_INT_PMT : PMT interrupt + * @arg ETH_DMA_INT_MMC : MMC interrupt + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Underflow interrupt + * @arg ETH_DMA_INT_RO : Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag) +{ + return (ETH->DMASTS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the ETH DMA interrupt flag. + * + * @param flag: specifies the interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_INT_RO : Receive Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval None + */ +void ETH_ClearDMAIntFlag(uint32_t flag) +{ + ETH->DMASTS = flag; +} + +/*! + * @brief Returns the ETH DMA Transmit Process State. + * + * @param None + + * @retval The new ETH DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TRANSMITPROCESS_STOPPED : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TRANSMITPROCESS_FETCHING : Running - fetching the Tx descriptor + * - ETH_DMA_TRANSMITPROCESS_WAITING : Running - waiting for status + * - ETH_DMA_TRANSMITPROCESS_READING : Running - reading the data from host memory + * - ETH_DMA_TRANSMITPROCESS_SUSPENDED : Suspended - Tx Descriptor unavailable + * - ETH_DMA_TRANSMITPROCESS_CLOSING : Running - closing Rx descriptor + */ +uint32_t ETH_ReadTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASTS & BIT0) ? SET : RESET); +} + +/*! + * @brief Returns the ETH DMA Receive Process State. + * + * @param None + * + * @retval The new ETH DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_RECEIVEPROCESS_STOPPED : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_RECEIVEPROCESS_FETCHING : Running - fetching the Rx descriptor + * - ETH_DMA_RECEIVEPROCESS_WAITING : Running - waiting for packet + * - ETH_DMA_RECEIVEPROCESS_SUSPENDED : Suspended - Rx Descriptor unavailable + * - ETH_DMA_RECEIVEPROCESS_CLOSING : Running - closing descriptor + * - ETH_DMA_RECEIVEPROCESS_QUEUING : Running - queuing the receive frame into host memory + */ +uint32_t ETH_ReadReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASTS & BIT6) ? SET : RESET); +} + +/*! + * @brief Flush the ETH transmit FIFO. + * + * @param None + * + * @retval None + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOPMOD_B.FTXF = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the ETH flush transmit FIFO status. + * + * @param None + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadFlushTransmitFIFOStatus(void) +{ + return ETH->DMAOPMOD_B.FTXF; +} + +/*! + * @brief Enable the DMA transmission. + * + * @param None + * + * @retval None + */ +void ETH_EnableDMATransmission(void) +{ + ETH->DMAOPMOD_B.STTX = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the DMA transmission. + * + * @param None + * + * @retval None + */ +void ETH_DisableDMATransmission(void) +{ + ETH->DMAOPMOD_B.STTX = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the DMA receiver. + * + * @param None + * + * @retval None + */ +void ETH_EnableDMAReceiver(void) +{ + ETH->DMAOPMOD_B.STRX = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the DMA receiver. + * + * @param None + * + * @retval None + */ +void ETH_DisableDMAReceiver(void) +{ + ETH->DMAOPMOD_B.STRX = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the ETH DMA interrupts. + * + * @param interrupt: specifies the ETH DMA interrupt sources. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Underflow interrupt + * @arg ETH_DMA_INT_RO : Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval None + */ +void ETH_EnableDMAInterrupt(uint32_t interrupt) +{ + ETH->DMAINTEN |= interrupt; +} + +/*! + * @brief Disable the ETH DMA interrupts. + * + * @param interrupt: specifies the ETH DMA interrupt sources. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Underflow interrupt + * @arg ETH_DMA_INT_RO : Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval None + */ +void ETH_DisableDMAInterrupt(uint32_t interrupt) +{ + ETH->DMAINTEN &= ((uint32_t)~interrupt); +} + +/*! + * @brief Read the ETH DMA overflow flag. + * + * @param overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter + * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow) +{ + return (ETH->DMAMFABOCNT & overflow) ? SET : RESET; +} + +/*! + * @brief Read the ETH DMA Rx Overflow Missed Frame Counter value. + * + * @param None + * + * @retval The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_ReadRxOverflowMissedFrameCounter(void) +{ + return (uint32_t)(ETH->DMAMFABOCNT_B.AMISFCNT); +} + +/*! + * @brief Read the ETH DMA Buffer Unavailable Missed Frame Counter value. + * + * @param None + * + * @retval The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void) +{ + return (uint32_t)(ETH->DMAMFABOCNT_B.MISFCNT); +} + +/*! + * @brief Read the ETH DMA DMAHTXD register value. + * + * @param None + * + * @retval The value of the current Tx desc start address. + */ +uint32_t ETH_ReadCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMAHTXD)); +} + +/*! + * @brief Read the ETHERNET DMA DMAHRXD register value. + * + * @param None + * + * @retval The value of the current Rx desc start address. + */ +uint32_t ETH_ReadCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMAHRXD)); +} + +/*! + * @brief Read the ETH DMA DMAHTXBADDR register value. + * + * @param None + * + * @retval The value of the current transmit descriptor data buffer address. + */ +uint32_t ETH_ReadCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMAHTXBADDR)); +} + +/*! + * @brief Read the ETH DMA DMAHRXBADDR register value. + * + * @param None + * + * @retval The value of the current receive descriptor data buffer address. + */ +uint32_t ETH_ReadCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMAHRXBADDR)); +} + +/*! + * @brief Reset the DMA Transmission by writing to the DmaTxPollDemand register + * + * @param None + + * @retval None. + */ +void ETH_ResetDMATransmission(void) +{ + ETH->DMATXPD = 0; +} + +/*! + * @brief Reset the DMA Transmission by writing to the DmaRxPollDemand register + * + * @param None + * + * @retval None. + */ +void ETH_ResetDMAReception(void) +{ + ETH->DMARXPD = 0; +} + +/** Power Management(PMT) functions */ + +/*! + * @brief Reset Wakeup frame filter register pointer. + * + * @param None + * + * @retval None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->PMTCTRLSTS_B.WKUPFRST = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * + * @retval None + */ +void ETH_EnableGlobalUnicastWakeUp(void) +{ + ETH->PMTCTRLSTS_B.GUN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * + * @retval None + */ +void ETH_DisableGlobalUnicastWakeUp(void) +{ + ETH->PMTCTRLSTS_B.GUN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the ETH PMT flag. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag) +{ + return (ETH->PMTCTRLSTS & flag) ? SET : RESET; +} + +/*! + * @brief Enable the MAC Wake-Up Frame Detection. + * + * @param None + * + * @retval None + */ +void ETH_EnableWakeUpFrameDetection(void) +{ + ETH->PMTCTRLSTS_B.WKUPFEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Wake-Up Frame Detection. + * + * @param None + * + * @retval None + */ +void ETH_DisableWakeUpFrameDetection(void) +{ + ETH->PMTCTRLSTS_B.WKUPFEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC Magic Packet Detection. + * + * @param None + * + * @retval None + */ +void ETH_EnableMagicPacketDetection(void) +{ + ETH->PMTCTRLSTS_B.MPEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Magic Packet Detection. + * + * @param None + * + * @retval None + */ +void ETH_DisableMagicPacketDetection(void) +{ + ETH->PMTCTRLSTS_B.MPEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC Power Down. + * + * @param None + * + * @retval None + */ +void ETH_EnablePowerDown(void) +{ + ETH->PMTCTRLSTS_B.PD = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Power Down. + * + * @param None + * + * @retval None + */ +void ETH_DisablePowerDown(void) +{ + ETH->PMTCTRLSTS_B.PD = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MMC Counter Freeze. + * + * @param None + * + * @retval None + */ +void ETH_EnableMMCCounterFreeze(void) +{ + ETH->CTRL_B.MCNTF = SET; +} + +/*! + * @brief Disable the MMC Counter Freeze. + * + * @param None + * + * @retval None + */ +void ETH_DisableMMCCounterFreeze(void) +{ + ETH->CTRL_B.MCNTF = RESET; +} + +/*! + * @brief Enable the MMC Reset On Read. + * + * @param None + * + * @retval None + */ +void ETH_EnableMMCResetOnRead(void) +{ + ETH->CTRL_B.RSTOR = SET; +} + +/*! + * @brief Disable the MMC Reset On Read. + * + * @param None + * + * @retval None + */ +void ETH_DisableMMCResetOnRead(void) +{ + ETH->CTRL_B.RSTOR = RESET; +} + +/*! + * @brief Enble the MMC Counter Stop Rollover. + * + * @param None + * + * @retval None + */ +void ETH_EnableMMCCounterRollover(void) +{ + ETH->CTRL_B.CNTSTOPRO = RESET; +} + +/*! + * @brief Disable the MMC Counter Stop Rollover. + * + * @param None + * + * @retval None + */ +void ETH_DisableMMCCounterRollover(void) +{ + ETH->CTRL_B.CNTSTOPRO = SET; +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval None + */ +void ETH_ResetMMCCounters(void) +{ + ETH->CTRL_B.CNTRST = SET; +} + +/*! + * @brief Enable the ETH MMC interrupts. + * + * @param interrupt: specifies the ETH MMC interrupt sources. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_INT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RFCE : When Rx crc error counter reaches half the maximum value + * + * @retval None + */ +void ETH_EnableMMCInterrupt(uint32_t interrupt) +{ + if ((interrupt & 0x10000000) == SET) + { + ETH->RXINTMASK &= (~(uint32_t)interrupt); + } + else + { + ETH->TXINTMASK &= (~(uint32_t)interrupt); + } +} + +/*! + * @brief Disable the ETH MMC interrupts. + * + * @param interrupt: specifies the ETH MMC interrupt sources. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_INT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RFCE : When Rx crc error counter reaches half the maximum value + * + * @retval None + */ +void ETH_DisableMMCInterrupt(uint32_t interrupt) +{ + if ((interrupt & 0x10000000) == SET) + { + ETH->RXINTMASK |= interrupt; + } + else + { + ETH->TXINTMASK |= interrupt; + } +} + +/*! + * @brief Read the ETH MMC interrupt flag. + * + * @param flag: specifies the ETH MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_INT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RFCE : When Rx crc error counter reaches half the maximum value + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadMMCIntFlag(uint32_t flag) +{ + if ((flag & 0x10000000) == SET) + { + return ((((ETH->RXINT & flag) != RESET)) && ((ETH->RXINTMASK & flag) == RESET)); + } + else + { + return ((((ETH->TXINT & flag) != RESET)) && ((ETH->TXINTMASK & flag) == RESET)); + } +} + +/*! + * @brief Read the ETH MMC register value. + * + * @param MMCReg: specifies the ETH MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMC_CTRL : MMC CTRL register + * @arg ETH_MMC_RXINT : MMC RXINT register + * @arg ETH_MMC_TXINT : MMC TXINT register + * @arg ETH_MMC_RXINTMASK : MMC RXINTMASK register + * @arg ETH_MMC_TXINTMASK : MMC TXINTMASK register + * @arg ETH_MMC_TXGFSCCNT : MMC TXGFSCCNT register + * @arg ETH_MMC_TXGFMCCNT : MMC TXGFMCCNT register + * @arg ETH_MMC_TXGFCNT : MMC TXGFCNT register + * @arg ETH_MMC_RXFCECNT : MMC RXFCECNT register + * @arg ETH_MMC_RXFAECNT : MMC RXFAECNT register + * @arg ETH_MMC_RXGUNCNT : MMC RXGUNCNT register + * + * @retval Return ETH MMC Register value. + */ +uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg) +{ + return (*(__IO uint32_t*)(ETH_MAC_BASE + MMCReg)); +} + +#endif + +/**@} end of group ETH_Functions */ +/**@} end of group ETH_Driver */ +/**@} end of group APM32F10x_ETHDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h index da04b17db9..ff8ab89da6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the ADC firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,17 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_ADC_H #define __APM32F10X_ADC_H +/* Includes */ +#include "apm32f10x.h" #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#include "apm32f10x.h" - -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +41,33 @@ @{ */ -/** @addtogroup ADC_Enumerations Enumerations + +/** @defgroup ADC_Macros + @{ +*/ + +/* ADC_IJD Offset */ +#define INJDATA_OFFSET ((uint8_t)0x28) + +/* ADC_RDG register address */ +#define RDG_ADDRESS ((uint32_t)0x4001244C) + +/* INJSEQ register config */ +#define INJSEQ_SET_INJSEQC ((uint32_t)0x0000001F) +#define INJSEQ_SET_INJSEQLEN ((uint32_t)0x00300000) + +/* SMPTIM register SET */ +#define SMPCYCCFG_SET_SMPTIM1 ((uint32_t)0x00000007) +#define SMPCYCCFG_SET_SMPTIM2 ((uint32_t)0x00000007) + +/* REGSEQ register SET */ +#define REGSEQC_SET_REGSEQ3 ((uint32_t)0x0000001F) +#define REGSEQC_SET_REGSEQ2 ((uint32_t)0x0000001F) +#define REGSEQC_SET_REGSEQ1 ((uint32_t)0x0000001F) + +/**@} end of group ADC_Macros*/ + +/** @defgroup ADC_Enumerations @{ */ @@ -49,16 +76,16 @@ */ typedef enum { - ADC_MODE_INDEPENDENT = ((uint32_t)0x00000000), //!< Independent mode - ADC_MODE_REG_INJEC_SIMULT = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode - ADC_MODE_REG_SIMULT_ALTER_TRIG = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode - ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode - ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode - ADC_MODE_INJEC_SIMULT = ((uint32_t)0x00050000), //!< Injected simultaneous mode - ADC_MODE_REG_SIMULT = ((uint32_t)0x00060000), //!< Regular simultaneous mode - ADC_MODE_FAST_INTERL = ((uint32_t)0x00070000), //!< Fast interleaved mode - ADC_MODE_SLOW_INTERL = ((uint32_t)0x00080000), //!< Slow interleaved mode - ADC_MODE_ALTER_TRIG = ((uint32_t)0x00090000) //!< Alternate trigger mode + ADC_MODE_INDEPENDENT = ((uint32_t)0x00000000), /*!< Independent mode */ + ADC_MODE_REG_INJEC_SIMULT = ((uint32_t)0x00010000), /*!< Combined regular simultaneous and injected simultaneous mode */ + ADC_MODE_REG_SIMULT_ALTER_TRIG = ((uint32_t)0x00020000), /*!< Combined regular simultaneous and alternate trigger mode */ + ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), /*!< Combined injected simultaneous and fast interleaved mode */ + ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), /*!< Combined injected simultaneous and slow interleaved mode */ + ADC_MODE_INJEC_SIMULT = ((uint32_t)0x00050000), /*!< Injected simultaneous mode */ + ADC_MODE_REG_SIMULT = ((uint32_t)0x00060000), /*!< Regular simultaneous mode */ + ADC_MODE_FAST_INTERL = ((uint32_t)0x00070000), /*!< Fast interleaved mode */ + ADC_MODE_SLOW_INTERL = ((uint32_t)0x00080000), /*!< Slow interleaved mode */ + ADC_MODE_ALTER_TRIG = ((uint32_t)0x00090000) /*!< Alternate trigger mode */ } ADC_MODE_T; /** @@ -139,19 +166,19 @@ typedef enum */ typedef enum { - /** for ADC1 and ADC2 */ + /* for ADC1 and ADC2 */ ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO = ((uint8_t)0x02), ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 = ((uint8_t)0x03), ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 = ((uint8_t)0x04), ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO = ((uint8_t)0x05), ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4 = ((uint8_t)0x06), - /** for ADC1, ADC2 and ADC3 */ + /* for ADC1, ADC2 and ADC3 */ ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO = ((uint8_t)0x00), ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 = ((uint8_t)0x01), ADC_EXT_TRIG_INJEC_CONV_NONE = ((uint8_t)0x07), - /** for ADC3 only */ + /* for ADC3 only */ ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 = ((uint8_t)0x02), ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 = ((uint8_t)0x03), ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 = ((uint8_t)0x04), @@ -189,9 +216,9 @@ typedef enum */ typedef enum { - ADC_INT_AWD = ((uint16_t)0x0140), //!< Analog Watchdog interrupt - ADC_INT_EOC = ((uint16_t)0x0220), //!< End Of Conversion interrupt - ADC_INT_INJEOC = ((uint16_t)0x0480) //!< Injected Channel End Of Conversion interrupt + ADC_INT_AWD = ((uint16_t)0x0140), /*!< Analog Watchdog interrupt */ + ADC_INT_EOC = ((uint16_t)0x0220), /*!< End Of Conversion interrupt */ + ADC_INT_INJEOC = ((uint16_t)0x0480) /*!< Injected Channel End Of Conversion interrupt */ } ADC_INT_T; /** @@ -199,43 +226,16 @@ typedef enum */ typedef enum { - ADC_FLAG_AWD = ((uint8_t)0x01), //!< Analog Watchdog event occur flag - ADC_FLAG_EOC = ((uint8_t)0x02), //!< End Of Conversion flag - ADC_FLAG_INJEOC = ((uint8_t)0x04), //!< Injected Channel End Of Conversion flag - ADC_FLAG_INJCS = ((uint8_t)0x08), //!< Injected Channel Conversion Start flag - ADC_FLAG_REGCS = ((uint8_t)0x10) //!< Regular Channel Conversion Start flag + ADC_FLAG_AWD = ((uint8_t)0x01), /*!< Analog Watchdog event occur flag */ + ADC_FLAG_EOC = ((uint8_t)0x02), /*!< End Of Conversion flag */ + ADC_FLAG_INJEOC = ((uint8_t)0x04), /*!< Injected Channel End Of Conversion flag */ + ADC_FLAG_INJCS = ((uint8_t)0x08), /*!< Injected Channel Conversion Start flag */ + ADC_FLAG_REGCS = ((uint8_t)0x10) /*!< Regular Channel Conversion Start flag */ } ADC_FLAG_T; /**@} end of group ADC_Enumerations*/ - -/** @addtogroup ADC_Macros Macros - @{ -*/ - -/** ADC_IJD Offset */ -#define INJDATA_OFFSET ((uint8_t)0x28) - -/** ADC_RDG register address */ -#define RDG_ADDRESS ((uint32_t)0x4001244C) - -/** INJSEQ register config */ -#define INJSEQ_SET_INJSEQC ((uint32_t)0x0000001F) -#define INJSEQ_SET_INJSEQLEN ((uint32_t)0x00300000) - -/** SMPTIM register SET */ -#define SMPCYCCFG_SET_SMPTIM1 ((uint32_t)0x00000007) -#define SMPCYCCFG_SET_SMPTIM2 ((uint32_t)0x00000007) - -/** REGSEQ register SET */ -#define REGSEQC_SET_REGSEQ3 ((uint32_t)0x0000001F) -#define REGSEQC_SET_REGSEQ2 ((uint32_t)0x0000001F) -#define REGSEQC_SET_REGSEQ1 ((uint32_t)0x0000001F) - -/**@} end of group ADC_Macros*/ - - -/** @addtogroup ADC_Structure Data Structure +/** @defgroup ADC_Structures Structures @{ */ @@ -245,89 +245,89 @@ typedef enum typedef struct { ADC_MODE_T mode; - uint8_t scanConvMode; //!< This parameter can be ENABLE or DISABLE. - uint8_t continuosConvMode; //!< This parameter can be ENABLE or DISABLE. + uint8_t scanConvMode; /*!< This parameter can be ENABLE or DISABLE. */ + uint8_t continuosConvMode; /*!< This parameter can be ENABLE or DISABLE. */ ADC_EXT_TRIG_CONV_T externalTrigConv; ADC_DATA_ALIGN_T dataAlign; - uint8_t nbrOfChannel; //!< This parameter must range from 1 to 16. + uint8_t nbrOfChannel; /*!< This parameter must range from 1 to 16. */ } ADC_Config_T; -/**@} end of group ADC_Structure*/ +/**@} end of group ADC_Structures*/ -/** @addtogroup ADC_Fuctions Fuctions +/** @defgroup ADC_Functions Functions @{ */ -/** ADC reset and common configuration */ +/* ADC reset and common configuration */ void ADC_Reset(ADC_T* adc); void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig); void ADC_ConfigStructInit(ADC_Config_T* adcConfig); -void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime); +void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); void ADC_Enable(ADC_T* adc); void ADC_Disable(ADC_T* adc); -/** ADC for DMA */ +/* ADC for DMA */ void ADC_EnableDMA(ADC_T* adc); void ADC_DisableDMA(ADC_T* adc); -/** ADC Calibration */ +/* ADC Calibration */ void ADC_ResetCalibration(ADC_T* adc); uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc); void ADC_StartCalibration(ADC_T* adc); uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc); -/** ADC software start conversion */ +/* ADC software start conversion */ void ADC_EnableSoftwareStartConv(ADC_T* adc); void ADC_DisableSoftwareStartConv(ADC_T* adc); uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc); -/** ADC Discontinuous mode */ +/* ADC Discontinuous mode */ void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number); void ADC_EnableDiscMode(ADC_T* adc); void ADC_DisableDiscMode(ADC_T* adc); -/** ADC External trigger conversion */ +/* ADC External trigger conversion */ void ADC_EnableExternalTrigConv(ADC_T* adc); void ADC_DisableExternalTrigConv(ADC_T* adc); -/** ADC Conversion result */ +/* ADC Conversion result */ uint16_t ADC_ReadConversionValue(ADC_T* adc); uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc); -/** ADC Automatic injected group */ +/* ADC Automatic injected group */ void ADC_EnableAutoInjectedConv(ADC_T* adc); void ADC_DisableAutoInjectedConv(ADC_T* adc); void ADC_EnableInjectedDiscMode(ADC_T* adc); void ADC_DisableInjectedDiscMode(ADC_T* adc); -/** ADC External trigger for injected channels conversion */ +/* ADC External trigger for injected channels conversion */ void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv); void ADC_EnableExternalTrigInjectedConv(ADC_T* adc); void ADC_DisableExternalTrigInjectedConv(ADC_T* adc); -/** ADC Start of the injected channels conversion */ +/* ADC Start of the injected channels conversion */ void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc); void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc); uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc); -/** ADC injected channel */ +/* ADC injected channel */ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length); void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet); uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel); -/** ADC analog watchdog */ +/* ADC analog watchdog */ void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog); void ADC_DisableAnalogWatchdog(ADC_T* adc); void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold); void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel); -/** ADC temperature sensor */ +/* ADC temperature sensor */ void ADC_EnableTempSensorVrefint(ADC_T* adc); void ADC_DisableTempSensorVrefint(ADC_T* adc); -/** Interrupt and flag */ +/* Interrupt and flag */ void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt); void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt); uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag); @@ -335,12 +335,14 @@ void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag); uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag); void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag); -/**@} end of group ADC_Fuctions*/ -/**@} end of group ADC_Driver*/ -/**@} end of group Peripherals_Library*/ + #ifdef __cplusplus } + +/**@} end of group ADC_Functions*/ +/**@} end of group ADC_Driver*/ +/**@} end of group APM32F10x_StdPeriphDriver */ #endif -#endif /** __APM32F10X_ADC_H */ +#endif /* __APM32F10X_ADC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h index 874d621682..3b72519388 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the BAKPR firmware library. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,13 +26,14 @@ #ifndef __APM32F10X_BAKPR_H #define __APM32F10X_BAKPR_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +41,7 @@ @{ */ -/** @addtogroup BAKPR_Enumerations Enumerations +/** @defgroup BAKPR_Enumerations Enumerations @{ */ @@ -116,11 +117,11 @@ typedef enum /**@} end of group BAKPR_Enumerations*/ -/** @addtogroup BAKPR_Fuctions Fuctions +/** @defgroup BAKPR_Functions Functions @{ */ -/** BAKPR reset and configuration */ +/* BAKPR reset and configuration */ void BAKPR_Reset(void); void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value); void BAKPR_EnableTamperPin(void); @@ -130,7 +131,7 @@ void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue); void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data); uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData); -/** Interrupts and flags */ +/* Interrupts and flags */ void BAKPR_EnableInterrupt(void); void BAKPR_DisableInterrupt(void); uint8_t BAKPR_ReadStatusFlag(void); @@ -138,9 +139,9 @@ void BAKPR_ClearStatusFlag(void); uint8_t BAKPR_ReadIntFlag(void); void BAKPR_ClearIntFlag(void); -/**@} end of group BAKPR_Fuctions*/ -/**@} end of group BAKPR_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group BAKPR_Functions*/ +/**@} end of group BAKPR_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h index cd676d4817..47d4973c2a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the CAN firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_CAN_H #define __APM32F10X_CAN_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup CAN_Enumerations Enumerations +/** @defgroup CAN_Enumerations Enumerations @{ */ @@ -49,10 +51,10 @@ */ typedef enum { - CAN_MODE_NORMAL = ((uint8_t)0x00), //!< normal mode - CAN_MODE_LOOPBACK = ((uint8_t)0x01), //!< loopback mode - CAN_MODE_SILENT = ((uint8_t)0x02), //!< silent mode - CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03) //!< loopback combined with silent mode + CAN_MODE_NORMAL = ((uint8_t)0x00), /*!< normal mode */ + CAN_MODE_LOOPBACK = ((uint8_t)0x01), /*!< loopback mode */ + CAN_MODE_SILENT = ((uint8_t)0x02), /*!< silent mode */ + CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03) /*!< loopback combined with silent mode */ } CAN_MODE_T; /** @@ -60,10 +62,10 @@ typedef enum */ typedef enum { - CAN_SJW_1 = ((uint8_t)0x00), //!< 1 time quantum - CAN_SJW_2 = ((uint8_t)0x01), //!< 2 time quantum - CAN_SJW_3 = ((uint8_t)0x02), //!< 3 time quantum - CAN_SJW_4 = ((uint8_t)0x03) //!< 4 time quantum + CAN_SJW_1 = ((uint8_t)0x00), /*!< 1 time quantum */ + CAN_SJW_2 = ((uint8_t)0x01), /*!< 2 time quantum */ + CAN_SJW_3 = ((uint8_t)0x02), /*!< 3 time quantum */ + CAN_SJW_4 = ((uint8_t)0x03) /*!< 4 time quantum */ } CAN_SJW_T; /** @@ -71,22 +73,22 @@ typedef enum */ typedef enum { - CAN_TIME_SEGMENT1_1 = ((uint8_t)0x00), //!< 1 time quanta - CAN_TIME_SEGMENT1_2 = ((uint8_t)0x01), //!< 2 time quanta - CAN_TIME_SEGMENT1_3 = ((uint8_t)0x02), //!< 3 time quanta - CAN_TIME_SEGMENT1_4 = ((uint8_t)0x03), //!< 4 time quanta - CAN_TIME_SEGMENT1_5 = ((uint8_t)0x04), //!< 5 time quanta - CAN_TIME_SEGMENT1_6 = ((uint8_t)0x05), //!< 6 time quanta - CAN_TIME_SEGMENT1_7 = ((uint8_t)0x06), //!< 7 time quanta - CAN_TIME_SEGMENT1_8 = ((uint8_t)0x07), //!< 8 time quanta - CAN_TIME_SEGMENT1_9 = ((uint8_t)0x08), //!< 9 time quanta - CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09), //!< 10 time quanta - CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A), //!< 11 time quanta - CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B), //!< 12 time quanta - CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C), //!< 13 time quanta - CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D), //!< 14 time quanta - CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E), //!< 15 time quanta - CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F) //!< 16 time quanta + CAN_TIME_SEGMENT1_1 = ((uint8_t)0x00), /*!< 1 time quanta */ + CAN_TIME_SEGMENT1_2 = ((uint8_t)0x01), /*!< 2 time quanta */ + CAN_TIME_SEGMENT1_3 = ((uint8_t)0x02), /*!< 3 time quanta */ + CAN_TIME_SEGMENT1_4 = ((uint8_t)0x03), /*!< 4 time quanta */ + CAN_TIME_SEGMENT1_5 = ((uint8_t)0x04), /*!< 5 time quanta */ + CAN_TIME_SEGMENT1_6 = ((uint8_t)0x05), /*!< 6 time quanta */ + CAN_TIME_SEGMENT1_7 = ((uint8_t)0x06), /*!< 7 time quanta */ + CAN_TIME_SEGMENT1_8 = ((uint8_t)0x07), /*!< 8 time quanta */ + CAN_TIME_SEGMENT1_9 = ((uint8_t)0x08), /*!< 9 time quanta */ + CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09), /*!< 10 time quanta */ + CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A), /*!< 11 time quanta */ + CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B), /*!< 12 time quanta */ + CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C), /*!< 13 time quanta */ + CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D), /*!< 14 time quanta */ + CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E), /*!< 15 time quanta */ + CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F) /*!< 16 time quanta */ } CAN_TIME_SEGMENT1_T; /** @@ -94,14 +96,14 @@ typedef enum */ typedef enum { - CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, //!< 1 time quanta - CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, //!< 2 time quanta - CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, //!< 3 time quanta - CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, //!< 4 time quanta - CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta - CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta - CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta - CAN_TIME_SEGMENT2_8 = (uint8_t)0x07 //!< 8 time quanta + CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, /*!< 1 time quanta */ + CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, /*!< 2 time quanta */ + CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, /*!< 3 time quanta */ + CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, /*!< 4 time quanta */ + CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, /*!< 5 time quanta */ + CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, /*!< 6 time quanta */ + CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, /*!< 7 time quanta */ + CAN_TIME_SEGMENT2_8 = (uint8_t)0x07 /*!< 8 time quanta */ } CAN_TIME_SEGMENT2_T; /** @@ -109,8 +111,8 @@ typedef enum */ typedef enum { - CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0 - CAN_FILTER_FIFO_1 = ((uint8_t)0x01) //!< filter FIFO 1 + CAN_FILTER_FIFO_0 = ((uint8_t)0x00), /*!< filter FIFO 0 */ + CAN_FILTER_FIFO_1 = ((uint8_t)0x01) /*!< filter FIFO 1 */ } CAN_FILTER_FIFO_T; /** @@ -118,8 +120,8 @@ typedef enum */ typedef enum { - CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode - CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode + CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),/*!< identifier/mask mode */ + CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) /*!< identifier list mode */ } CAN_FILTER_MODE_T; /** @@ -127,8 +129,8 @@ typedef enum */ typedef enum { - CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters - CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01) //!< One 32-bit filter + CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), /*!< Two 16-bit filters */ + CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01) /*!< One 32-bit filter */ } CAN_FILTER_SCALE_T; /** @@ -136,8 +138,8 @@ typedef enum */ typedef enum { - CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id - CAN_TYPEID_EXT = ((uint32_t)0x00000004) //!< Extended Id + CAN_TYPEID_STD = ((uint32_t)0x00000000), /*!< Standard Id */ + CAN_TYPEID_EXT = ((uint32_t)0x00000004) /*!< Extended Id */ } CAN_TYPEID_T; /** @@ -145,8 +147,8 @@ typedef enum */ typedef enum { - CAN_RTXR_DATA = ((uint32_t)0x00000000), //!< Data frame - CAN_RTXR_REMOTE = ((uint32_t)0x00000002) //!< Remote frame + CAN_RTXR_DATA = ((uint32_t)0x00000000), /*!< Data frame */ + CAN_RTXR_REMOTE = ((uint32_t)0x00000002) /*!< Remote frame */ } CAN_RTXR_T; /** @@ -154,9 +156,9 @@ typedef enum */ typedef enum { - CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0 - CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1 - CAN_TX_MAILBIX_2 = ((uint8_t)0x02) //!< Tx mailbox2 + CAN_TX_MAILBIX_0 = ((uint8_t)0x00), /*!< Tx mailbox0 */ + CAN_TX_MAILBIX_1 = ((uint8_t)0x01), /*!< Tx mailbox1 */ + CAN_TX_MAILBIX_2 = ((uint8_t)0x02) /*!< Tx mailbox2 */ } CAN_TX_MAILBIX_T; /** @@ -164,8 +166,8 @@ typedef enum */ typedef enum { - CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0 - CAN_RX_FIFO_1 = ((uint8_t)0x01) //!< receive FIFO 1 + CAN_RX_FIFO_0 = ((uint8_t)0x00), /*!< receive FIFO 0 */ + CAN_RX_FIFO_1 = ((uint8_t)0x01) /*!< receive FIFO 1 */ } CAN_RX_FIFO_T; /** @@ -173,9 +175,9 @@ typedef enum */ typedef enum { - CAN_OPERATING_MODE_INIT = ((uint8_t)0x00), //!< Initialization mode - CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode - CAN_OPERATING_MODE_SLEEP = ((uint8_t)0x02) //!< sleep mode + CAN_OPERATING_MODE_INIT = ((uint8_t)0x00), /*!< Initialization mode */ + CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), /*!< Normal mode */ + CAN_OPERATING_MODE_SLEEP = ((uint8_t)0x02) /*!< sleep mode */ } CAN_OPERATING_MODE_T; /** @@ -183,20 +185,20 @@ typedef enum */ typedef enum { - CAN_INT_TXME = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt - CAN_INT_F0MP = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt - CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt - CAN_INT_F0OVR = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt - CAN_INT_F1MP = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt - CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt - CAN_INT_F1OVR = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt - CAN_INT_ERRW = ((uint32_t)0x00000100), //!< Error warning Interrupt - CAN_INT_ERRP = ((uint32_t)0x00000200), //!< Error passive Interrupt - CAN_INT_BOF = ((uint32_t)0x00000400), //!< Bus-off Interrupt - CAN_INT_LEC = ((uint32_t)0x00000800), //!< Last error record code Interrupt - CAN_INT_ERR = ((uint32_t)0x00008000), //!< Error Interrupt - CAN_INT_WUP = ((uint32_t)0x00010000), //!< Wake-up Interrupt - CAN_INT_SLEEP = ((uint32_t)0x00020000) //!< Sleep acknowledge Interrupt + CAN_INT_TXME = ((uint32_t)0x00000001), /*!< Transmit mailbox empty Interrupt */ + CAN_INT_F0MP = ((uint32_t)0x00000002), /*!< FIFO 0 message pending Interrupt */ + CAN_INT_F0FULL = ((uint32_t)0x00000004), /*!< FIFO 0 full Interrupt */ + CAN_INT_F0OVR = ((uint32_t)0x00000008), /*!< FIFO 0 overrun Interrupt */ + CAN_INT_F1MP = ((uint32_t)0x00000010), /*!< FIFO 1 message pending Interrupt */ + CAN_INT_F1FULL = ((uint32_t)0x00000020), /*!< FIFO 1 full Interrupt */ + CAN_INT_F1OVR = ((uint32_t)0x00000040), /*!< FIFO 1 overrun Interrupt */ + CAN_INT_ERRW = ((uint32_t)0x00000100), /*!< Error warning Interrupt */ + CAN_INT_ERRP = ((uint32_t)0x00000200), /*!< Error passive Interrupt */ + CAN_INT_BOF = ((uint32_t)0x00000400), /*!< Bus-off Interrupt */ + CAN_INT_LEC = ((uint32_t)0x00000800), /*!< Last error record code Interrupt */ + CAN_INT_ERR = ((uint32_t)0x00008000), /*!< Error Interrupt */ + CAN_INT_WUP = ((uint32_t)0x00010000), /*!< Wake-up Interrupt */ + CAN_INT_SLEEP = ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt */ } CAN_INT_T; /** @@ -205,28 +207,31 @@ typedef enum typedef enum { /** Error flag*/ - CAN_FLAG_ERRW = ((uint32_t)0x10F00001), //!< Error Warning Flag - CAN_FLAG_ERRP = ((uint32_t)0x10F00002), //!< Error Passive Flag - CAN_FLAG_BOF = ((uint32_t)0x10F00004), //!< Bus-Off Flag - CAN_FLAG_LERRC = ((uint32_t)0x30F00070), //!< Last error record code Flag + CAN_FLAG_ERRW = ((uint32_t)0x10F00001), /*!< Error Warning Flag */ + CAN_FLAG_ERRP = ((uint32_t)0x10F00002), /*!< Error Passive Flag */ + CAN_FLAG_BOF = ((uint32_t)0x10F00004), /*!< Bus-Off Flag */ + CAN_FLAG_LERRC = ((uint32_t)0x30F00070), /*!< Last error record code Flag */ /** Operating Mode Flags */ - CAN_FLAG_WUPI = ((uint32_t)0x31000008), //!< Wake up Flag - CAN_FLAG_SLEEP = ((uint32_t)0x31000012), //!< Sleep acknowledge Flag + CAN_FLAG_WUPI = ((uint32_t)0x31000008), /*!< Wake up Flag */ + CAN_FLAG_SLEEP = ((uint32_t)0x31000012), /*!< Sleep acknowledge Flag */ /** Receive Flags */ - CAN_FLAG_F0MP = ((uint32_t)0x12000003), //!< FIFO 0 Message Pending Flag - CAN_FLAG_F0FULL = ((uint32_t)0x32000008), //!< FIFO 0 Full Flag - CAN_FLAG_F0OVR = ((uint32_t)0x32000010), //!< FIFO 0 Overrun Flag - CAN_FLAG_F1MP = ((uint32_t)0x14000003), //!< FIFO 1 Message Pending Flag - CAN_FLAG_F1FULL = ((uint32_t)0x34000008), //!< FIFO 1 Full Flag - CAN_FLAG_F1OVR = ((uint32_t)0x34000010), //!< FIFO 1 Overrun Flag + CAN_FLAG_F0MP = ((uint32_t)0x12000003), /*!< FIFO 0 Message Pending Flag */ + CAN_FLAG_F0FULL = ((uint32_t)0x32000008), /*!< FIFO 0 Full Flag */ + CAN_FLAG_F0OVR = ((uint32_t)0x32000010), /*!< FIFO 0 Overrun Flag */ + CAN_FLAG_F1MP = ((uint32_t)0x14000003), /*!< FIFO 1 Message Pending Flag */ + CAN_FLAG_F1FULL = ((uint32_t)0x34000008), /*!< FIFO 1 Full Flag */ + CAN_FLAG_F1OVR = ((uint32_t)0x34000010), /*!< FIFO 1 Overrun Flag */ /** Transmit Flags */ - CAN_FLAG_REQC0 = ((uint32_t)0x38000001), //!< Request MailBox0 Flag - CAN_FLAG_REQC1 = ((uint32_t)0x38000100), //!< Request MailBox1 Flag - CAN_FLAG_REQC2 = ((uint32_t)0x38010000) //!< Request MailBox2 Flag + CAN_FLAG_REQC0 = ((uint32_t)0x38000001), /*!< Request MailBox0 Flag */ + CAN_FLAG_REQC1 = ((uint32_t)0x38000100), /*!< Request MailBox1 Flag */ + CAN_FLAG_REQC2 = ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ } CAN_FLAG_T; /**@} end of group CAN_Enumerations*/ +/** @defgroup CAN_Structures Structures + @{ +*/ /** * @brief CAN Config structure definition @@ -237,18 +242,18 @@ typedef enum */ typedef struct { - uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management. - uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode. - uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode. - uint8_t rxFIFOLockMode; //!< Enable or disable the Receive FIFO Locked mode. - uint8_t txFIFOPriority; //!< Enable or disable the transmit FIFO priority. - CAN_MODE_T mode; //!< Specifies the CAN operating mode. - CAN_SJW_T syncJumpWidth; /** Specifies the maximum number of time quanta the CAN hardware - * is allowed to lengthen or shorten a bit to perform resynchronization. - */ - CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1. - CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2. - uint16_t prescaler; //!< Specifies the length of a time quantum. It can be 1 to 1024. + uint8_t autoBusOffManage; /*!< Enable or disable the automatic bus-off management. */ + uint8_t autoWakeUpMode; /*!< Enable or disable the automatic wake-up mode. */ + uint8_t nonAutoRetran; /*!< Enable or disable the non-automatic retransmission mode. */ + uint8_t rxFIFOLockMode; /*!< Enable or disable the Receive FIFO Locked mode. */ + uint8_t txFIFOPriority; /*!< Enable or disable the transmit FIFO priority. */ + CAN_MODE_T mode; /*!< Specifies the CAN operating mode. */ + CAN_SJW_T syncJumpWidth; /* Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + */ + CAN_TIME_SEGMENT1_T timeSegment1; /*!< Specifies the number of time quanta in Bit Segment 1. */ + CAN_TIME_SEGMENT2_T timeSegment2; /*!< Specifies the number of time quanta in Bit Segment 2. */ + uint16_t prescaler; /*!< Specifies the length of a time quantum. It can be 1 to 1024. */ } CAN_Config_T; /** @@ -256,12 +261,12 @@ typedef struct */ typedef struct { - uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF. - uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. + uint32_t stdID; /*!< Specifies the standard identifier. It can be 0 to 0x7FF. */ + uint32_t extID; /*!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. */ CAN_TYPEID_T typeID; CAN_RTXR_T remoteTxReq; - uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8. - uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. + uint8_t dataLengthCode;/*!< Specifies the data length code. It can be 0 to 8. */ + uint8_t data[8]; /*!< Specifies the data to be transmitted. It can be 0 to 0xFF. */ } CAN_TxMessage_T; /** @@ -269,13 +274,13 @@ typedef struct */ typedef struct { - uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF. - uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. + uint32_t stdID; /*!< Specifies the standard identifier. It can be 0 to 0x7FF. */ + uint32_t extID; /*!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. */ uint32_t typeID; uint32_t remoteTxReq; - uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8. - uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. - uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF. + uint8_t dataLengthCode; /*!< Specifies the data length code. It can be 0 to 8. */ + uint8_t data[8]; /*!< Specifies the data to be transmitted. It can be 0 to 0xFF. */ + uint8_t filterMatchIndex;/*!< Specifies the filter match index. It can be 0 to 0xFF. */ } CAN_RxMessage_T; /** @@ -283,54 +288,58 @@ typedef struct */ typedef struct { - uint8_t filterNumber; //!< Specifies the filter number. It can be 0 to 13. - uint16_t filterIdHigh; //!< Specifies the filter identification number.It can be 0 to 0xFFFF. - uint16_t filterIdLow; //!< Specifies the filter identification number.It can be 0 to 0xFFFF. - uint16_t filterMaskIdHigh; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF. - uint16_t filterMaskIdLow; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF. - uint16_t filterActivation; //!< Specifies the filter Activation. It can be ENABLE or DISABLE. + uint8_t filterNumber; /*!< Specifies the filter number. It can be 0 to 13. */ + uint16_t filterIdHigh; /*!< Specifies the filter identification number.It can be 0 to 0xFFFF. */ + uint16_t filterIdLow; /*!< Specifies the filter identification number.It can be 0 to 0xFFFF. */ + uint16_t filterMaskIdHigh; /*!< Specifies the filter mask identification. It can be 0 to 0xFFFF. */ + uint16_t filterMaskIdLow; /*!< Specifies the filter mask identification. It can be 0 to 0xFFFF. */ + uint16_t filterActivation; /*!< Specifies the filter Activation. It can be ENABLE or DISABLE. */ CAN_FILTER_FIFO_T filterFIFO; CAN_FILTER_MODE_T filterMode; CAN_FILTER_SCALE_T filterScale; } CAN_FilterConfig_T; -/**@} end of group CAN_Structure*/ +/**@} end of group CAN_Structures*/ -/** @addtogroup CAN_Fuctions Fuctions +/** @defgroup CAN_Functions Functions @{ */ -/** CAN reset and configuration */ +/* CAN reset and configuration */ void CAN_Reset(CAN_T* can); uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig); +#if defined(APM32F10X_CL) +void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig); +void CAN_SlaveStartBank(uint8_t bankNum); +#else void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig); +#endif void CAN_ConfigStructInit(CAN_Config_T* canConfig); void CAN_EnableDBGFreeze(CAN_T* can); void CAN_DisableDBGFreeze(CAN_T* can); -void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum); -/** CAN frames transmit */ +/* CAN frames transmit */ uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage); uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); -/** CAN frames receive */ +/* CAN frames receive */ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage); void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber); uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber); -/** CAN operation modes */ +/* CAN operation modes */ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode); uint8_t CAN_SleepMode(CAN_T* can); uint8_t CAN_WakeUpMode(CAN_T* can); -/** CAN bus error management */ +/* CAN bus error management */ uint8_t CAN_ReadLastErrorCode(CAN_T* can); uint8_t CAN_ReadRxErrorCounter(CAN_T* can); uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can); -/** CAN interrupt and flag */ +/* CAN interrupt and flag */ void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt); void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt); uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag); @@ -338,9 +347,9 @@ void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag); uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag); void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag); -/**@} end of group CAN_Fuctions*/ -/**@} end of group CAN_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group CAN_Functions*/ +/**@} end of group CAN_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h index 27a9ab64e0..58b2750719 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the CRC firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,13 +26,14 @@ #ifndef __APM32F10X_CRC_H #define __APM32F10X_CRC_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,27 +41,26 @@ @{ */ -/** @addtogroup CRC_Fuctions Fuctions +/** @defgroup CRC_Functions Functions @{ */ -/** Reset DATA */ +/* Reset DATA */ void CRC_ResetDATA(void); -/** Operation functions */ +/* Operation functions */ uint32_t CRC_CalculateCRC(uint32_t data); -uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen); +uint32_t CRC_CalculateBlockCRC(uint32_t* buf, uint32_t bufLen); uint32_t CRC_ReadCRC(void); void CRC_WriteIDRegister(uint8_t inData); uint8_t CRC_ReadIDRegister(void); -/**@} end of group CRC_Fuctions*/ -/**@} end of group CRC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group CRC_Functions*/ +/**@} end of group CRC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } #endif #endif /* __APM32F10X_CRC_H */ - diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h index 74df98d0bf..a73e219e2e 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the DAC firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,13 +26,14 @@ #ifndef __APM32F10X_DAC_H #define __APM32F10X_DAC_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +41,7 @@ @{ */ -/** @addtogroup DAC_Enumerations Enumerations +/** @defgroup DAC_Enumerations Enumerations @{ */ @@ -51,7 +52,7 @@ typedef enum { DAC_CHANNEL_1 = 0x00000000, DAC_CHANNEL_2 = 0x00000010 -}DAC_CHANNEL_T; +} DAC_CHANNEL_T; /** * @brief DAC trigger selection @@ -67,7 +68,7 @@ typedef enum DAC_TRIGGER_TMR4_TRGO = 0x0000002C, DAC_TRIGGER_EINT9 = 0x00000034, DAC_TRIGGER_SOFT = 0x0000003C -}DAC_TRIGGER_T; +} DAC_TRIGGER_T; /** * @brief DAC wave generation @@ -77,39 +78,39 @@ typedef enum DAC_WAVE_GENERATION_NONE = 0x00000000, DAC_WAVE_GENERATION_NOISE = 0x00000040, DAC_WAVE_GENERATION_TRIANGLE = 0x00000080 -}DAC_WAVE_GENERATION_T; +} DAC_WAVE_GENERATION_T; /** * @brief DAC channelx mask/amplitude selector */ typedef enum { - DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_2 = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_3 = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_4 = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_5 = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_6 = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_7 = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_8 = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_9 = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation - DAC_LFSR_MASK_BIT11 = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation - DAC_LFSR_MASK_NONE = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_1 = 0x00000000, /*!< Mask bit[11:1] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_2 = 0x00000100, /*!< Mask bit[11:2] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_3 = 0x00000200, /*!< Mask bit[11:3] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_4 = 0x00000300, /*!< Mask bit[11:4] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_5 = 0x00000400, /*!< Mask bit[11:5] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_6 = 0x00000500, /*!< Mask bit[11:6] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_7 = 0x00000600, /*!< Mask bit[11:7] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_8 = 0x00000700, /*!< Mask bit[11:8] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_9 = 0x00000800, /*!< Mask bit[11:9] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11_10 = 0x00000900, /*!< Mask bit[11:10] of LFSR for noise wave generation */ + DAC_LFSR_MASK_BIT11 = 0x00000A00, /*!< Mask bit11 of LFSR for noise wave generation */ + DAC_LFSR_MASK_NONE = 0x00000B00, /*!< Mask none bit of LFSR for noise wave generation */ - DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1 - DAC_TRIANGLE_AMPLITUDE_3 = 0x00000100, //!< Triangle amplitude equal to 3 - DAC_TRIANGLE_AMPLITUDE_7 = 0x00000200, //!< Triangle amplitude equal to 7 - DAC_TRIANGLE_AMPLITUDE_15 = 0x00000300, //!< Triangle amplitude equal to 15 - DAC_TRIANGLE_AMPLITUDE_31 = 0x00000400, //!< Triangle amplitude equal to 31 - DAC_TRIANGLE_AMPLITUDE_63 = 0x00000500, //!< Triangle amplitude equal to 63 - DAC_TRIANGLE_AMPLITUDE_127 = 0x00000600, //!< Triangle amplitude equal to 127 - DAC_TRIANGLE_AMPLITUDE_255 = 0x00000700, //!< Triangle amplitude equal to 255 - DAC_TRIANGLE_AMPLITUDE_511 = 0x00000800, //!< Triangle amplitude equal to 511 - DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023 - DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047 - DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 //!< Triangle amplitude equal to 4095 -}DAC_MASK_AMPLITUDE_SEL_T; + DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, /*!< Triangle amplitude equal to 1 */ + DAC_TRIANGLE_AMPLITUDE_3 = 0x00000100, /*!< Triangle amplitude equal to 3 */ + DAC_TRIANGLE_AMPLITUDE_7 = 0x00000200, /*!< Triangle amplitude equal to 7 */ + DAC_TRIANGLE_AMPLITUDE_15 = 0x00000300, /*!< Triangle amplitude equal to 15 */ + DAC_TRIANGLE_AMPLITUDE_31 = 0x00000400, /*!< Triangle amplitude equal to 31 */ + DAC_TRIANGLE_AMPLITUDE_63 = 0x00000500, /*!< Triangle amplitude equal to 63 */ + DAC_TRIANGLE_AMPLITUDE_127 = 0x00000600, /*!< Triangle amplitude equal to 127 */ + DAC_TRIANGLE_AMPLITUDE_255 = 0x00000700, /*!< Triangle amplitude equal to 255 */ + DAC_TRIANGLE_AMPLITUDE_511 = 0x00000800, /*!< Triangle amplitude equal to 511 */ + DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, /*!< Triangle amplitude equal to 1023 */ + DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, /*!< Triangle amplitude equal to 2047 */ + DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00 /*!< Triangle amplitude equal to 4095 */ +} DAC_MASK_AMPLITUDE_SEL_T; /** * @brief DAC output buffer @@ -118,7 +119,7 @@ typedef enum { DAC_OUTPUT_BUFFER_ENBALE = 0x00000000, DAC_OUTPUT_BUFFER_DISABLE = 0x00000002 -}DAC_OUTPUT_BUFFER_T; +} DAC_OUTPUT_BUFFER_T; /** * @brief DAC data align @@ -128,12 +129,12 @@ typedef enum DAC_ALIGN_12BIT_R = 0x00000000, DAC_ALIGN_12BIT_L = 0x00000004, DAC_ALIGN_8BIT_R = 0x00000008 -}DAC_ALIGN_T; +} DAC_ALIGN_T; /**@} end of group DAC_Enumerations*/ -/** @addtogroup DAC_Structure Data Structure +/** @defgroup DAC_Structures Structures @{ */ @@ -146,47 +147,47 @@ typedef struct DAC_OUTPUT_BUFFER_T outputBuffer; DAC_WAVE_GENERATION_T waveGeneration; DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect; -}DAC_Config_T; +} DAC_Config_T; -/**@} end of group DAC_Structure*/ +/**@} end of group DAC_Structures*/ -/** @addtogroup DAC_Fuctions Fuctions +/** @defgroup DAC_Functions Functions @{ */ -/** DAC Reset and Configuration */ +/* DAC Reset and Configuration */ void DAC_Reset(void); void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig); void DAC_ConfigStructInit(DAC_Config_T* dacConfig); void DAC_Enable(DAC_CHANNEL_T channel); void DAC_Disable(DAC_CHANNEL_T channel); -/** DAC channel for DAM */ +/* DAC channel for DAM */ void DAC_DMA_Enable(DAC_CHANNEL_T channel); void DAC_DMA_Disable(DAC_CHANNEL_T channel); -/** DAC channel software trigger */ +/* DAC channel software trigger */ void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel); void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel); void DAC_EnableDualSoftwareTrigger(void); void DAC_DisableDualSoftwareTrigger(void); -/** DAC channel wave generation */ +/* DAC channel wave generation */ void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); -/** DAC set channel data */ +/* DAC set channel data */ void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data); void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data); void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1); -/** DAC read data output value */ +/* DAC read data output value */ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel); -/**@} end of group DAC_Fuctions*/ -/**@} end of group DAC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group DAC_Functions*/ +/**@} end of group DAC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h index aaf8365958..68dee4171a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the DBUGMCU firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_DBGMCU_H #define __APM32F10X_DBGMCU_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,10 +42,13 @@ @{ */ -/** @addtogroup DBGMCU_Enumerations Enumerations +/** @defgroup DBGMCU_Enumerations Enumerations @{ */ +/** + * @brief DBGMCU_STOP description + */ enum { DBGMCU_SLEEP = ((uint32_t)0x00000001), @@ -77,7 +82,7 @@ enum /**@} end of group DBGMCU_Enumerations*/ -/** @addtogroup DBGMCU_Fuctions Fuctions +/** @defgroup DBGMCU_Functions Functions @{ */ @@ -86,9 +91,9 @@ uint32_t DBGMCU_ReadREVID(void); void DBGMCU_Enable(uint32_t periph); void DBGMCU_Disable(uint32_t periph); -/**@} end of group DBGMCU_Fuctions*/ -/**@} end of group DBGMCU_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group DBGMCU_Functions*/ +/**@} end of group DBGMCU_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h index 02d0be4c54..8dae060314 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the DMA firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,13 +26,14 @@ #ifndef __APM32F10X_DMA_H #define __APM32F10X_DMA_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +41,7 @@ @{ */ -/** @addtogroup DMA_Enumerations Enumerations +/** @defgroup DMA_Enumerations Enumerations @{ */ @@ -245,7 +246,7 @@ typedef enum /**@} end of group DMA_Enumerations*/ -/** @addtogroup DMA_Structure Data Structure +/** @defgroup DMA_Structures Structures @{ */ @@ -267,35 +268,35 @@ typedef struct DMA_M2MEN_T M2M; } DMA_Config_T; -/**@} end of group DMA_Structure*/ +/**@} end of group DMA_Structures*/ -/** @addtogroup DMA_Fuctions Fuctions +/** @defgroup DMA_Functions Functions @{ */ -/** Reset and configuration */ -void DMA_Reset(DMA_Channel_T *channel); +/* Reset and configuration */ +void DMA_Reset(DMA_Channel_T* channel); void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig); -void DMA_ConfigStructInit( DMA_Config_T* dmaConfig); -void DMA_Enable(DMA_Channel_T *channel); -void DMA_Disable(DMA_Channel_T *channel); +void DMA_ConfigStructInit(DMA_Config_T* dmaConfig); +void DMA_Enable(DMA_Channel_T* channel); +void DMA_Disable(DMA_Channel_T* channel); -/** Data number */ -void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber); -uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel); +/* Data number */ +void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber); +uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel); -/** Interrupt and flag */ -void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt); -void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt); +/* Interrupt and flag */ +void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt); +void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt); uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag); void DMA_ClearStatusFlag(uint32_t flag); uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag); void DMA_ClearIntFlag(uint32_t flag); -/**@} end of group DMA_Fuctions*/ -/**@} end of group DMA_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group DMA_Functions*/ +/**@} end of group DMA_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h index f6b2b70e5a..fcc44a5532 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h @@ -3,9 +3,9 @@ * * @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,13 +26,14 @@ #ifndef __APM32F10X_DMC_H #define __APM32F10X_DMC_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,11 +41,10 @@ @{ */ -/** @addtogroup DMC_Enumerations Enumerations +/** @defgroup DMC_Enumerations Enumerations @{ */ - /** * @brief Bank Address Width */ @@ -52,7 +52,7 @@ typedef enum { DMC_BANK_WIDTH_1, DMC_BANK_WIDTH_2 -}DMC_BANK_WIDTH_T; +} DMC_BANK_WIDTH_T; /** * @brief Row Address Width @@ -65,7 +65,7 @@ typedef enum DMC_ROW_WIDTH_14, DMC_ROW_WIDTH_15, DMC_ROW_WIDTH_16 -}DMC_ROW_WIDTH_T; +} DMC_ROW_WIDTH_T; /** * @brief Column Address Width @@ -80,7 +80,7 @@ typedef enum DMC_COL_WIDTH_13, DMC_COL_WIDTH_14, DMC_COL_WIDTH_15 -}DMC_COL_WIDTH_T; +} DMC_COL_WIDTH_T; /** * @brief CAS Latency Select @@ -91,7 +91,7 @@ typedef enum DMC_CAS_LATENCY_2, DMC_CAS_LATENCY_3, DMC_CAS_LATENCY_4 -}DMC_CAS_LATENCY_T; +} DMC_CAS_LATENCY_T; /** * @brief RAS Minimun Time Select @@ -114,7 +114,7 @@ typedef enum DMC_RAS_MINIMUM_14, DMC_RAS_MINIMUM_15, DMC_RAS_MINIMUM_16 -}DMC_RAS_MINIMUM_T; +} DMC_RAS_MINIMUM_T; /** * @brief RAS To CAS Delay Time Select @@ -129,7 +129,7 @@ typedef enum DMC_DELAY_TIME_6, DMC_DELAY_TIME_7, DMC_DELAY_TIME_8 -}DMC_DELAY_TIME_T; +} DMC_DELAY_TIME_T; /** * @brief Precharge Period Select @@ -144,7 +144,7 @@ typedef enum DMC_PRECHARGE_6, DMC_PRECHARGE_7, DMC_PRECHARGE_8 -}DMC_PRECHARGE_T; +} DMC_PRECHARGE_T; /** * @brief Last Data Next Precharge For Write Time Select @@ -155,7 +155,7 @@ typedef enum DMC_NEXT_PRECHARGE_2, DMC_NEXT_PRECHARGE_3, DMC_NEXT_PRECHARGE_4 -}DMC_NEXT_PRECHARGE_T; +} DMC_NEXT_PRECHARGE_T; /** * @brief Auto-Refresh Period Select @@ -178,7 +178,7 @@ typedef enum DMC_AUTO_REFRESH_14, DMC_AUTO_REFRESH_15, DMC_AUTO_REFRESH_16, -}DMC_AUTO_REFRESH_T; +} DMC_AUTO_REFRESH_T; /** * @brief Active-to-active Command Period Select @@ -201,7 +201,7 @@ typedef enum DMC_ATA_CMD_14, DMC_ATA_CMD_15, DMC_ATA_CMD_16, -}DMC_ATA_CMD_T; +} DMC_ATA_CMD_T; /** * @brief Clock PHASE @@ -210,7 +210,7 @@ typedef enum { DMC_CLK_PHASE_NORMAL, DMC_CLK_PHASE_REVERSE -}DMC_CLK_PHASE_T; +} DMC_CLK_PHASE_T; /** * @brief DMC Memory Size @@ -231,7 +231,7 @@ typedef enum DMC_MEMORY_SIZE_64MB, DMC_MEMORY_SIZE_128MB, DMC_MEMORY_SIZE_256MB, -}DMC_MEMORY_SIZE_T; +} DMC_MEMORY_SIZE_T; /** * @brief Open Banks Of Number @@ -254,25 +254,25 @@ typedef enum DMC_BANK_NUMBER_14, DMC_BANK_NUMBER_15, DMC_BANK_NUMBER_16, -}DMC_BANK_NUMBER_T; +} DMC_BANK_NUMBER_T; /** * @brief Full refresh type */ typedef enum { - DMC_REFRESH_ROW_ONE, //!< Refresh one row - DMC_REFRESH_ROW_ALL, //!< Refresh all row -}DMC_REFRESH_T; + DMC_REFRESH_ROW_ONE, /*!< Refresh one row */ + DMC_REFRESH_ROW_ALL, /*!< Refresh all row */ +} DMC_REFRESH_T; /** * @brief Precharge type */ typedef enum { - DMC_PRECHARGE_IM, //!< Immediate precharge - DMC_PRECHARGE_DELAY, //!< Delayed precharge -}DMC_PRECHARE_T; + DMC_PRECHARGE_IM, /*!< Immediate precharge */ + DMC_PRECHARGE_DELAY, /*!< Delayed precharge */ +} DMC_PRECHARE_T; /** * @brief WRAP Burst Type @@ -281,12 +281,12 @@ typedef enum { DMC_WRAPB_4, DMC_WRAPB_8, -}DMC_WRPB_T; +} DMC_WRPB_T; /**@} end of group DMC_Enumerations*/ -/** @addtogroup DMC_Structure Data Structure +/** @defgroup DMC_Structures Structures @{ */ @@ -295,66 +295,66 @@ typedef enum */ typedef struct { - uint32_t latencyCAS : 2; //!< DMC_CAS_LATENCY_T - uint32_t tRAS : 4; //!< DMC_RAS_MINIMUM_T - uint32_t tRCD : 3; //!< DMC_DELAY_TIME_T - uint32_t tRP : 3; //!< DMC_PRECHARGE_T - uint32_t tWR : 2; //!< DMC_NEXT_PRECHARGE_T - uint32_t tARP : 4; //!< DMC_AUTO_REFRESH_T - uint32_t tCMD : 4; //!< DMC_ATA_CMD_T - uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF - uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF -}DMC_TimingConfig_T; + uint32_t latencyCAS : 2; /*!< DMC_CAS_LATENCY_T */ + uint32_t tRAS : 4; /*!< DMC_RAS_MINIMUM_T */ + uint32_t tRCD : 3; /*!< DMC_DELAY_TIME_T */ + uint32_t tRP : 3; /*!< DMC_PRECHARGE_T */ + uint32_t tWR : 2; /*!< DMC_NEXT_PRECHARGE_T */ + uint32_t tARP : 4; /*!< DMC_AUTO_REFRESH_T */ + uint32_t tCMD : 4; /*!< DMC_ATA_CMD_T */ + uint32_t tXSR : 9; /*!< auto-refresh commands, can be 0x000 to 0x1FF */ + uint16_t tRFP : 16; /*!< Refresh period, can be 0x0000 to 0xFFFF */ +} DMC_TimingConfig_T; /** * @brief Config struct definition */ typedef struct { - DMC_MEMORY_SIZE_T memorySize; //!< Memory size(byte) - DMC_BANK_WIDTH_T bankWidth; //!< Number of bank bits - DMC_ROW_WIDTH_T rowWidth; //!< Number of row address bits - DMC_COL_WIDTH_T colWidth; //!< Number of col address bits - DMC_CLK_PHASE_T clkPhase; //!< Clock phase - DMC_TimingConfig_T timing; //!< Timing -}DMC_Config_T; + DMC_MEMORY_SIZE_T memorySize; /*!< Memory size(byte) */ + DMC_BANK_WIDTH_T bankWidth; /*!< Number of bank bits */ + DMC_ROW_WIDTH_T rowWidth; /*!< Number of row address bits */ + DMC_COL_WIDTH_T colWidth; /*!< Number of col address bits */ + DMC_CLK_PHASE_T clkPhase; /*!< Clock phase */ + DMC_TimingConfig_T timing; /*!< Timing */ +} DMC_Config_T; -/**@} end of group DMC_Structure*/ +/**@} end of group DMC_Structures*/ -/** @addtogroup DMC_Fuctions Fuctions +/** @defgroup DMC_Functions Functions @{ */ - /** Enable / Disable */ +/* Enable / Disable */ void DMC_Enable(void); void DMC_Disable(void); void DMC_EnableInit(void); -/** Global config */ +/* Global config */ void DMC_Config(DMC_Config_T* dmcConfig); void DMC_ConfigStructInit(DMC_Config_T* dmcConfig); -/** Address */ +/* Address */ void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth); void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth); -/** Timing */ +/* Timing */ void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig); void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig); void DMC_ConfigStableTimePowerup(uint16_t stableTime); void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num); void DMC_ConfigRefreshPeriod(uint16_t period); -/** Refresh mode */ +/* Refresh mode */ void DMC_EixtSlefRefreshMode(void); void DMC_EnterSlefRefreshMode(void); -/** Accelerate Module */ +/* Accelerate Module */ void DMC_EnableAccelerateModule(void); void DMC_DisableAccelerateModule(void); -/** Config */ +/* Config */ void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num); void DMC_EnableUpdateMode(void); void DMC_EnterPowerdownMode(void); @@ -365,12 +365,12 @@ void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize); void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase); void DMC_ConfigWRAPB(DMC_WRPB_T burst); -/** read flag */ +/* read flag */ uint8_t DMC_ReadSelfRefreshStatus(void); -/**@} end of group DMC_Fuctions*/ +/**@} end of group DMC_Functions*/ /**@} end of group DMC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h index 7cf3cb1454..74e8ac8573 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the EINT firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_EINT_H #define __APM32F10X_EINT_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup EINT_Enumerations Enumerations +/** @defgroup EINT_Enumerations Enumerations @{ */ @@ -65,32 +67,32 @@ typedef enum typedef enum { - EINT_LINENONE = 0x00000, //! - EINT_LINE_0 = 0x00001, //!< External interrupt line 0 - EINT_LINE_1 = 0x00002, //!< External interrupt line 1 - EINT_LINE_2 = 0x00004, //!< External interrupt line 2 - EINT_LINE_3 = 0x00008, //!< External interrupt line 3 - EINT_LINE_4 = 0x00010, //!< External interrupt line 4 - EINT_LINE_5 = 0x00020, //!< External interrupt line 5 - EINT_LINE_6 = 0x00040, //!< External interrupt line 6 - EINT_LINE_7 = 0x00080, //!< External interrupt line 7 - EINT_LINE_8 = 0x00100, //!< External interrupt line 8 - EINT_LINE_9 = 0x00200, //!< External interrupt line 9 - EINT_LINE_10 = 0x00400, //!< External interrupt line 10 - EINT_LINE_11 = 0x00800, //!< External interrupt line 11 - EINT_LINE_12 = 0x01000, //!< External interrupt line 12 - EINT_LINE_13 = 0x02000, //!< External interrupt line 13 - EINT_LINE_14 = 0x04000, //!< External interrupt line 14 - EINT_LINE_15 = 0x08000, //!< External interrupt line 15 - EINT_LINE_16 = 0x10000, //!< External interrupt line 16 Connected to the PVD Output - EINT_LINE_17 = 0x20000, //!< External interrupt line 17 Connected to the RTC Alarm event - EINT_LINE_18 = 0x40000, //!< External interrupt line 18 Connected to the USB Device + EINT_LINENONE = 0x00000, /*! */ + EINT_LINE_0 = 0x00001, /*!< External interrupt line 0 */ + EINT_LINE_1 = 0x00002, /*!< External interrupt line 1 */ + EINT_LINE_2 = 0x00004, /*!< External interrupt line 2 */ + EINT_LINE_3 = 0x00008, /*!< External interrupt line 3 */ + EINT_LINE_4 = 0x00010, /*!< External interrupt line 4 */ + EINT_LINE_5 = 0x00020, /*!< External interrupt line 5 */ + EINT_LINE_6 = 0x00040, /*!< External interrupt line 6 */ + EINT_LINE_7 = 0x00080, /*!< External interrupt line 7 */ + EINT_LINE_8 = 0x00100, /*!< External interrupt line 8 */ + EINT_LINE_9 = 0x00200, /*!< External interrupt line 9 */ + EINT_LINE_10 = 0x00400, /*!< External interrupt line 10 */ + EINT_LINE_11 = 0x00800, /*!< External interrupt line 11 */ + EINT_LINE_12 = 0x01000, /*!< External interrupt line 12 */ + EINT_LINE_13 = 0x02000, /*!< External interrupt line 13 */ + EINT_LINE_14 = 0x04000, /*!< External interrupt line 14 */ + EINT_LINE_15 = 0x08000, /*!< External interrupt line 15 */ + EINT_LINE_16 = 0x10000, /*!< External interrupt line 16 Connected to the PVD Output */ + EINT_LINE_17 = 0x20000, /*!< External interrupt line 17 Connected to the RTC Alarm event */ + EINT_LINE_18 = 0x40000, /*!< External interrupt line 18 Connected to the USB Device */ } EINT_LINE_T; /**@} end of group EINT_Enumerations*/ -/** @addtogroup EINT_Structure Data Structure +/** @defgroup EINT_Structures Structures @{ */ @@ -105,31 +107,31 @@ typedef struct uint8_t lineCmd; } EINT_Config_T; -/**@} end of group EINT_Structure*/ +/**@} end of group EINT_Structures*/ -/** @addtogroup EINT_Fuctions Fuctions +/** @defgroup EINT_Functions Functions @{ */ -/** Reset and configuration */ +/* Reset and configuration */ void EINT_Reset(void); -void EINT_Config( EINT_Config_T* eintConfig); +void EINT_Config(EINT_Config_T* eintConfig); void EINT_ConfigStructInit(EINT_Config_T* eintConfig); -/** Interrupt and flag */ +/* Interrupt and flag */ void EINT_SelectSWInterrupt(uint32_t line); uint8_t EINT_ReadStatusFlag(EINT_LINE_T line); void EINT_ClearStatusFlag(uint32_t line); uint8_t EINT_ReadIntFlag(EINT_LINE_T line); void EINT_ClearIntFlag(uint32_t line); -/**@} end of group EINT_Fuctions*/ -/**@} end of group EINT_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group EINT_Functions*/ +/**@} end of group EINT_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ -#ifdef __cplusplus +#ifdef __APM32F10X_cplusplus } #endif -#endif /* __APM32F10XEINT_H */ +#endif /* __EINT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h index d8b56e2bf2..240e23efde 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the FMC firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_FMC_H #define __APM32F10X_FMC_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,86 @@ @{ */ -/** @addtogroup FMC_Enumerations Enumerations +/** @defgroup FMC_Macros Macros + @{ +*/ + +/* Macros description */ + +/* Values for APM32 Low and Medium density devices */ +#define FLASH_WRP_PAGE_0_3 ((uint32_t)BIT0) /*!< Write protection of page 0 to 3 */ +#define FLASH_WRP_PAGE_4_7 ((uint32_t)BIT1) /*!< Write protection of page 4 to 7 */ +#define FLASH_WRP_PAGE_8_11 ((uint32_t)BIT2) /*!< Write protection of page 8 to 11 */ +#define FLASH_WRP_PAGE_12_15 ((uint32_t)BIT3) /*!< Write protection of page 12 to 15 */ +#define FLASH_WRP_PAGE_16_19 ((uint32_t)BIT4) /*!< Write protection of page 16 to 19 */ +#define FLASH_WRP_PAGE_20_23 ((uint32_t)BIT5) /*!< Write protection of page 20 to 23 */ +#define FLASH_WRP_PAGE_24_27 ((uint32_t)BIT6) /*!< Write protection of page 24 to 27 */ +#define FLASH_WRP_PAGE_28_31 ((uint32_t)BIT7) /*!< Write protection of page 28 to 31 */ + +/* Values for APM32 Medium-density devices */ +#define FLASH_WRP_PAGE_32_35 ((uint32_t)BIT8) /*!< Write protection of page 32 to 35 */ +#define FLASH_WRP_PAGE_36_39 ((uint32_t)BIT9) /*!< Write protection of page 36 to 39 */ +#define FLASH_WRP_PAGE_40_43 ((uint32_t)BIT10) /*!< Write protection of page 40 to 43 */ +#define FLASH_WRP_PAGE_44_47 ((uint32_t)BIT11) /*!< Write protection of page 44 to 47 */ +#define FLASH_WRP_PAGE_48_51 ((uint32_t)BIT12) /*!< Write protection of page 48 to 51 */ +#define FLASH_WRP_PAGE_52_55 ((uint32_t)BIT13) /*!< Write protection of page 52 to 55 */ +#define FLASH_WRP_PAGE_56_59 ((uint32_t)BIT14) /*!< Write protection of page 56 to 59 */ +#define FLASH_WRP_PAGE_60_63 ((uint32_t)BIT15) /*!< Write protection of page 60 to 63 */ +#define FLASH_WRP_PAGE_64_67 ((uint32_t)BIT16) /*!< Write protection of page 64 to 67 */ +#define FLASH_WRP_PAGE_68_71 ((uint32_t)BIT17) /*!< Write protection of page 68 to 71 */ +#define FLASH_WRP_PAGE_72_75 ((uint32_t)BIT18) /*!< Write protection of page 72 to 75 */ +#define FLASH_WRP_PAGE_76_79 ((uint32_t)BIT19) /*!< Write protection of page 76 to 79 */ +#define FLASH_WRP_PAGE_80_83 ((uint32_t)BIT20) /*!< Write protection of page 80 to 83 */ +#define FLASH_WRP_PAGE_84_87 ((uint32_t)BIT21) /*!< Write protection of page 84 to 87 */ +#define FLASH_WRP_PAGE_88_91 ((uint32_t)BIT22) /*!< Write protection of page 88 to 91 */ +#define FLASH_WRP_PAGE_92_95 ((uint32_t)BIT23) /*!< Write protection of page 92 to 95 */ +#define FLASH_WRP_PAGE_96_99 ((uint32_t)BIT24) /*!< Write protection of page 96 to 99 */ +#define FLASH_WRP_PAGE_100_103 ((uint32_t)BIT25) /*!< Write protection of page 100 to 103 */ +#define FLASH_WRP_PAGE_104_107 ((uint32_t)BIT26) /*!< Write protection of page 104 to 107 */ +#define FLASH_WRP_PAGE_108_111 ((uint32_t)BIT27) /*!< Write protection of page 108 to 111 */ +#define FLASH_WRP_PAGE_112_115 ((uint32_t)BIT28) /*!< Write protection of page 112 to 115 */ +#define FLASH_WRP_PAGE_116_119 ((uint32_t)BIT29) /*!< Write protection of page 116 to 119 */ +#define FLASH_WRP_PAGE_120_123 ((uint32_t)BIT30) /*!< Write protection of page 120 to 123 */ +#define FLASH_WRP_PAGE_124_127 ((uint32_t)BIT31) /*!< Write protection of page 124 to 127 */ + +/* Values only for APM32 High-density devices */ +#define FLASH_WRP_PAGE_0_1 ((uint32_t)BIT0) /*!< Write protection of page 0 to 1 */ +#define FLASH_WRP_PAGE_2_3 ((uint32_t)BIT1) /*!< Write protection of page 2 to 3 */ +#define FLASH_WRP_PAGE_4_5 ((uint32_t)BIT2) /*!< Write protection of page 4 to 5 */ +#define FLASH_WRP_PAGE_6_7 ((uint32_t)BIT3) /*!< Write protection of page 6 to 7 */ +#define FLASH_WRP_PAGE_8_9 ((uint32_t)BIT4) /*!< Write protection of page 8 to 9 */ +#define FLASH_WRP_PAGE_10_11 ((uint32_t)BIT5) /*!< Write protection of page 10 to 11 */ +#define FLASH_WRP_PAGE_12_13 ((uint32_t)BIT6) /*!< Write protection of page 12 to 13 */ +#define FLASH_WRP_PAGE_14_15 ((uint32_t)BIT7) /*!< Write protection of page 14 to 15 */ +#define FLASH_WRP_PAGE_16_17 ((uint32_t)BIT8) /*!< Write protection of page 16 to 17 */ +#define FLASH_WRP_PAGE_18_19 ((uint32_t)BIT9) /*!< Write protection of page 18 to 19 */ +#define FLASH_WRP_PAGE_20_21 ((uint32_t)BIT10) /*!< Write protection of page 20 to 21 */ +#define FLASH_WRP_PAGE_22_23 ((uint32_t)BIT11) /*!< Write protection of page 22 to 23 */ +#define FLASH_WRP_PAGE_24_25 ((uint32_t)BIT12) /*!< Write protection of page 24 to 25 */ +#define FLASH_WRP_PAGE_26_27 ((uint32_t)BIT13) /*!< Write protection of page 26 to 27 */ +#define FLASH_WRP_PAGE_28_29 ((uint32_t)BIT14) /*!< Write protection of page 28 to 29 */ +#define FLASH_WRP_PAGE_30_31 ((uint32_t)BIT15) /*!< Write protection of page 30 to 31 */ +#define FLASH_WRP_PAGE_32_33 ((uint32_t)BIT16) /*!< Write protection of page 32 to 33 */ +#define FLASH_WRP_PAGE_34_35 ((uint32_t)BIT17) /*!< Write protection of page 34 to 35 */ +#define FLASH_WRP_PAGE_36_37 ((uint32_t)BIT18) /*!< Write protection of page 36 to 37 */ +#define FLASH_WRP_PAGE_38_39 ((uint32_t)BIT19) /*!< Write protection of page 38 to 39 */ +#define FLASH_WRP_PAGE_40_41 ((uint32_t)BIT20) /*!< Write protection of page 40 to 41 */ +#define FLASH_WRP_PAGE_42_43 ((uint32_t)BIT21) /*!< Write protection of page 42 to 43 */ +#define FLASH_WRP_PAGE_44_45 ((uint32_t)BIT22) /*!< Write protection of page 44 to 45 */ +#define FLASH_WRP_PAGE_46_47 ((uint32_t)BIT23) /*!< Write protection of page 46 to 47 */ +#define FLASH_WRP_PAGE_48_49 ((uint32_t)BIT24) /*!< Write protection of page 48 to 49 */ +#define FLASH_WRP_PAGE_50_51 ((uint32_t)BIT25) /*!< Write protection of page 50 to 51 */ +#define FLASH_WRP_PAGE_52_53 ((uint32_t)BIT26) /*!< Write protection of page 52 to 53 */ +#define FLASH_WRP_PAGE_54_55 ((uint32_t)BIT27) /*!< Write protection of page 54 to 55 */ +#define FLASH_WRP_PAGE_56_57 ((uint32_t)BIT28) /*!< Write protection of page 56 to 57 */ +#define FLASH_WRP_PAGE_58_59 ((uint32_t)BIT29) /*!< Write protection of page 58 to 59 */ +#define FLASH_WRP_PAGE_60_61 ((uint32_t)BIT30) /*!< Write protection of page 60 to 61 */ +#define FLASH_WRP_PAGE_62_127 ((uint32_t)BIT31) /*!< Write protection of page 62 to 127 */ +#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) /*!< Write protection of page all */ + +/**@} end of group FMC_Macros*/ + +/** @defgroup FMC_Enumerations Enumerations @{ */ @@ -59,11 +140,11 @@ typedef enum */ typedef enum { - FMC_STATUS_BUSY = 1, //!< flash busy - FMC_STATUS_ERROR_PG, //!< flash programming error - FMC_STATUS_ERROR_WRP, //!< flash write protection error - FMC_STATUS_COMPLETE, //!< flash operation complete - FMC_STATUS_TIMEOUT //!< flash time out + FMC_STATUS_BUSY = 1, /*!< flash busy */ + FMC_STATUS_ERROR_PG, /*!< flash programming error */ + FMC_STATUS_ERROR_WRP, /*!< flash write protection error */ + FMC_STATUS_COMPLETE, /*!< flash operation complete */ + FMC_STATUS_TIMEOUT /*!< flash time out */ } FMC_STATUS_T; /** @@ -107,95 +188,16 @@ typedef enum */ typedef enum { - FMC_FLAG_BUSY = 0x00000001, //!< FMC Busy flag - FMC_FLAG_OC = 0x00000020, //!< FMC End of Operation flag - FMC_FLAG_PE = 0x00000004, //!< FMC Program error flag - FMC_FLAG_WPE = 0x00000010, //!< FMC Write protected error flag - FMC_FLAG_OBE = 0x10000001, //!< FMC Option Byte error flag + FMC_FLAG_BUSY = 0x00000001, /*!< FMC Busy flag */ + FMC_FLAG_OC = 0x00000020, /*!< FMC End of Operation flag */ + FMC_FLAG_PE = 0x00000004, /*!< FMC Program error flag */ + FMC_FLAG_WPE = 0x00000010, /*!< FMC Write protected error flag */ + FMC_FLAG_OBE = 0x10000001, /*!< FMC Option Byte error flag */ } FMC_FLAG_T; /**@} end of group FMC_Enumerations*/ -/** @addtogroup FMC_Macros Macros - @{ -*/ - -/** Macros description */ - -/** Values for APM32 Low and Medium density devices */ -#define FLASH_WRP_PAGE_0_3 ((uint32_t)BIT0) //!< Write protection of page 0 to 3 -#define FLASH_WRP_PAGE_4_7 ((uint32_t)BIT1) //!< Write protection of page 4 to 7 -#define FLASH_WRP_PAGE_8_11 ((uint32_t)BIT2) //!< Write protection of page 8 to 11 -#define FLASH_WRP_PAGE_12_15 ((uint32_t)BIT3) //!< Write protection of page 12 to 15 -#define FLASH_WRP_PAGE_16_19 ((uint32_t)BIT4) //!< Write protection of page 16 to 19 -#define FLASH_WRP_PAGE_20_23 ((uint32_t)BIT5) //!< Write protection of page 20 to 23 -#define FLASH_WRP_PAGE_24_27 ((uint32_t)BIT6) //!< Write protection of page 24 to 27 -#define FLASH_WRP_PAGE_28_31 ((uint32_t)BIT7) //!< Write protection of page 28 to 31 - -/** Values for APM32 Medium-density devices */ -#define FLASH_WRP_PAGE_32_35 ((uint32_t)BIT8) //!< Write protection of page 32 to 35 -#define FLASH_WRP_PAGE_36_39 ((uint32_t)BIT9) //!< Write protection of page 36 to 39 -#define FLASH_WRP_PAGE_40_43 ((uint32_t)BIT10) //!< Write protection of page 40 to 43 -#define FLASH_WRP_PAGE_44_47 ((uint32_t)BIT11) //!< Write protection of page 44 to 47 -#define FLASH_WRP_PAGE_48_51 ((uint32_t)BIT12) //!< Write protection of page 48 to 51 -#define FLASH_WRP_PAGE_52_55 ((uint32_t)BIT13) //!< Write protection of page 52 to 55 -#define FLASH_WRP_PAGE_56_59 ((uint32_t)BIT14) //!< Write protection of page 56 to 59 -#define FLASH_WRP_PAGE_60_63 ((uint32_t)BIT15) //!< Write protection of page 60 to 63 -#define FLASH_WRP_PAGE_64_67 ((uint32_t)BIT16) //!< Write protection of page 64 to 67 -#define FLASH_WRP_PAGE_68_71 ((uint32_t)BIT17) //!< Write protection of page 68 to 71 -#define FLASH_WRP_PAGE_72_75 ((uint32_t)BIT18) //!< Write protection of page 72 to 75 -#define FLASH_WRP_PAGE_76_79 ((uint32_t)BIT19) //!< Write protection of page 76 to 79 -#define FLASH_WRP_PAGE_80_83 ((uint32_t)BIT20) //!< Write protection of page 80 to 83 -#define FLASH_WRP_PAGE_84_87 ((uint32_t)BIT21) //!< Write protection of page 84 to 87 -#define FLASH_WRP_PAGE_88_91 ((uint32_t)BIT22) //!< Write protection of page 88 to 91 -#define FLASH_WRP_PAGE_92_95 ((uint32_t)BIT23) //!< Write protection of page 92 to 95 -#define FLASH_WRP_PAGE_96_99 ((uint32_t)BIT24) //!< Write protection of page 96 to 99 -#define FLASH_WRP_PAGE_100_103 ((uint32_t)BIT25) //!< Write protection of page 100 to 103 -#define FLASH_WRP_PAGE_104_107 ((uint32_t)BIT26) //!< Write protection of page 104 to 107 -#define FLASH_WRP_PAGE_108_111 ((uint32_t)BIT27) //!< Write protection of page 108 to 111 -#define FLASH_WRP_PAGE_112_115 ((uint32_t)BIT28) //!< Write protection of page 112 to 115 -#define FLASH_WRP_PAGE_116_119 ((uint32_t)BIT29) //!< Write protection of page 116 to 119 -#define FLASH_WRP_PAGE_120_123 ((uint32_t)BIT30) //!< Write protection of page 120 to 123 -#define FLASH_WRP_PAGE_124_127 ((uint32_t)BIT31) //!< Write protection of page 124 to 127 - -/** Values only for APM32 High-density devices */ -#define FLASH_WRP_PAGE_0_1 ((uint32_t)BIT0) //!< Write protection of page 0 to 1 -#define FLASH_WRP_PAGE_2_3 ((uint32_t)BIT1) //!< Write protection of page 2 to 3 -#define FLASH_WRP_PAGE_4_5 ((uint32_t)BIT2) //!< Write protection of page 4 to 5 -#define FLASH_WRP_PAGE_6_7 ((uint32_t)BIT3) //!< Write protection of page 6 to 7 -#define FLASH_WRP_PAGE_8_9 ((uint32_t)BIT4) //!< Write protection of page 8 to 9 -#define FLASH_WRP_PAGE_10_11 ((uint32_t)BIT5) //!< Write protection of page 10 to 11 -#define FLASH_WRP_PAGE_12_13 ((uint32_t)BIT6) //!< Write protection of page 12 to 13 -#define FLASH_WRP_PAGE_14_15 ((uint32_t)BIT7) //!< Write protection of page 14 to 15 -#define FLASH_WRP_PAGE_16_17 ((uint32_t)BIT8) //!< Write protection of page 16 to 17 -#define FLASH_WRP_PAGE_18_19 ((uint32_t)BIT9) //!< Write protection of page 18 to 19 -#define FLASH_WRP_PAGE_20_21 ((uint32_t)BIT10) //!< Write protection of page 20 to 21 -#define FLASH_WRP_PAGE_22_23 ((uint32_t)BIT11) //!< Write protection of page 22 to 23 -#define FLASH_WRP_PAGE_24_25 ((uint32_t)BIT12) //!< Write protection of page 24 to 25 -#define FLASH_WRP_PAGE_26_27 ((uint32_t)BIT13) //!< Write protection of page 26 to 27 -#define FLASH_WRP_PAGE_28_29 ((uint32_t)BIT14) //!< Write protection of page 28 to 29 -#define FLASH_WRP_PAGE_30_31 ((uint32_t)BIT15) //!< Write protection of page 30 to 31 -#define FLASH_WRP_PAGE_32_33 ((uint32_t)BIT16) //!< Write protection of page 32 to 33 -#define FLASH_WRP_PAGE_34_35 ((uint32_t)BIT17) //!< Write protection of page 34 to 35 -#define FLASH_WRP_PAGE_36_37 ((uint32_t)BIT18) //!< Write protection of page 36 to 37 -#define FLASH_WRP_PAGE_38_39 ((uint32_t)BIT19) //!< Write protection of page 38 to 39 -#define FLASH_WRP_PAGE_40_41 ((uint32_t)BIT20) //!< Write protection of page 40 to 41 -#define FLASH_WRP_PAGE_42_43 ((uint32_t)BIT21) //!< Write protection of page 42 to 43 -#define FLASH_WRP_PAGE_44_45 ((uint32_t)BIT22) //!< Write protection of page 44 to 45 -#define FLASH_WRP_PAGE_46_47 ((uint32_t)BIT23) //!< Write protection of page 46 to 47 -#define FLASH_WRP_PAGE_48_49 ((uint32_t)BIT24) //!< Write protection of page 48 to 49 -#define FLASH_WRP_PAGE_50_51 ((uint32_t)BIT25) //!< Write protection of page 50 to 51 -#define FLASH_WRP_PAGE_52_53 ((uint32_t)BIT26) //!< Write protection of page 52 to 53 -#define FLASH_WRP_PAGE_54_55 ((uint32_t)BIT27) //!< Write protection of page 54 to 55 -#define FLASH_WRP_PAGE_56_57 ((uint32_t)BIT28) //!< Write protection of page 56 to 57 -#define FLASH_WRP_PAGE_58_59 ((uint32_t)BIT29) //!< Write protection of page 58 to 59 -#define FLASH_WRP_PAGE_60_61 ((uint32_t)BIT30) //!< Write protection of page 60 to 61 -#define FLASH_WRP_PAGE_62_127 ((uint32_t)BIT31) //!< Write protection of page 62 to 127 -#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */ - -/**@} end of group FMC_Macros*/ - -/** @addtogroup FMC_Structure Data Structure +/** @defgroup FMC_Structures Structures @{ */ @@ -211,27 +213,27 @@ typedef struct /**@} end of group FMC_Structure*/ -/** @addtogroup FMC_Fuctions Fuctions +/** @defgroup FMC_Functions Functions @{ */ -/** Initialization and Configuration */ +/* Initialization and Configuration */ void FMC_ConfigLatency(FMC_LATENCY_T latency); void FMC_EnableHalfCycleAccess(void); void FMC_DisableHalfCycleAccess(void); void FMC_EnablePrefetchBuffer(void); void FMC_DisablePrefetchBuffer(void); -/** Lock management */ +/* Lock management */ void FMC_Unlock(void); void FMC_Lock(void); -/** Erase management */ +/* Erase management */ FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr); FMC_STATUS_T FMC_EraseAllPage(void); FMC_STATUS_T FMC_EraseOptionBytes(void); -/** Read Write management */ +/* Read Write management */ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data); FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data); FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data); @@ -244,19 +246,19 @@ uint32_t FMC_ReadOptionByteWriteProtection(void); uint8_t FMC_GetReadProtectionStatus(void); uint8_t FMC_ReadPrefetchBufferStatus(void); -/** Interrupts and flags */ +/* Interrupts and flags */ void FMC_EnableInterrupt(FMC_INT_T interrupt); void FMC_DisableInterrupt(FMC_INT_T interrupt); uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag); void FMC_ClearStatusFlag(uint32_t flag); -/** Status management */ +/* Status management */ FMC_STATUS_T FMC_ReadStatus(void); FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut); -/**@} end of group FMC_Fuctions*/ +/**@} end of group FMC_Functions*/ /**@} end of group FMC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h index b462ba55c5..9ca3b350f9 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the GPIO firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_GPIO_H #define __APM32F10X_GPIO_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup GPIO_Enumerations Enumerations +/** @defgroup GPIO_Enumerations Enumerations @{ */ @@ -49,25 +51,25 @@ */ typedef enum { - GPIO_SPEED_10MHz = 1, - GPIO_SPEED_20MHz, - GPIO_SPEED_50MHz -}GPIO_SPEED_T; + GPIO_SPEED_10MHz = 1, + GPIO_SPEED_2MHz, + GPIO_SPEED_50MHz +} GPIO_SPEED_T; /** * @brief Configuration Mode enumeration */ typedef enum { - GPIO_MODE_ANALOG = 0x0, //!< Analog mode - GPIO_MODE_IN_FLOATING = 0x04, //!< Floating input - GPIO_MODE_IN_PD = 0x28, //!< Input with pull-down - GPIO_MODE_IN_PU = 0x48, //!< Input with pull-up - GPIO_MODE_OUT_PP = 0x80, //!< General purpose output push-pull - GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain - GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull - GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain -}GPIO_MODE_T; + GPIO_MODE_ANALOG = 0x0, /*!< Analog mode */ + GPIO_MODE_IN_FLOATING = 0x04, /*!< Floating input */ + GPIO_MODE_IN_PD = 0x28, /*!< Input with pull-down */ + GPIO_MODE_IN_PU = 0x48, /*!< Input with pull-up */ + GPIO_MODE_OUT_PP = 0x80, /*!< General purpose output push-pull */ + GPIO_MODE_OUT_OD = 0x84, /*!< General purpose output Open-drain */ + GPIO_MODE_AF_PP = 0x88, /*!< Alternate function output Push-pull */ + GPIO_MODE_AF_OD = 0x8C, /*!< Alternate function output Open-drain */ +} GPIO_MODE_T; /** * @brief Definition of the GPIO pins @@ -98,113 +100,145 @@ typedef enum */ typedef enum { - GPIO_NO_REMAP_SPI1 = 0x00000010, - GPIO_REMAP_SPI1 = 0x00000011, + GPIO_NO_REMAP_SPI1 = 0x00000010, + GPIO_REMAP_SPI1 = 0x00000011, - GPIO_NO_REMAP_I2C1 = 0x00000110, - GPIO_REMAP_I2C1 = 0x00000111, + GPIO_NO_REMAP_I2C1 = 0x00000110, + GPIO_REMAP_I2C1 = 0x00000111, - GPIO_NO_REMAP_USART1 = 0x00000210, - GPIO_REMAP_USART1 = 0x00000211, + GPIO_NO_REMAP_USART1 = 0x00000210, + GPIO_REMAP_USART1 = 0x00000211, - GPIO_NO_REMAP_USART2 = 0x00000310, - GPIO_REMAP_USART2 = 0x00000311, + GPIO_NO_REMAP_USART2 = 0x00000310, + GPIO_REMAP_USART2 = 0x00000311, - GPIO_NO_REMAP_USART3 = 0x00000430, - GPIO_PARTIAL_REMAP_USART3 = 0x00000431, - GPIO_FULL_REMAP_USART3 = 0x00000433, + GPIO_NO_REMAP_USART3 = 0x00000430, + GPIO_PARTIAL_REMAP_USART3 = 0x00000431, + GPIO_FULL_REMAP_USART3 = 0x00000433, - GPIO_NO_REMAP_TMR1 = 0x00000630, - GPIO_PARTIAL_REMAP_TMR1 = 0x00000631, - GPIO_FULL_REMAP_TMR1 = 0x00000633, + GPIO_NO_REMAP_TMR1 = 0x00000630, + GPIO_PARTIAL_REMAP_TMR1 = 0x00000631, + GPIO_FULL_REMAP_TMR1 = 0x00000633, - GPIO_NO_REMAP_TMR2 = 0x00000830, - GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831, - GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832, - GPIO_FULL_REMAP_TMR2 = 0x00000833, + GPIO_NO_REMAP_TMR2 = 0x00000830, + GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831, + GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832, + GPIO_FULL_REMAP_TMR2 = 0x00000833, - GPIO_NO_REMAP_TMR3 = 0x00000A30, - GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32, - GPIO_FULL_REMAP_TMR3 = 0x00000A33, + GPIO_NO_REMAP_TMR3 = 0x00000A30, + GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32, + GPIO_FULL_REMAP_TMR3 = 0x00000A33, - GPIO_NO_REMAP_TMR4 = 0x00000C10, - GPIO_REMAP_TMR4 = 0x00000C11, + GPIO_NO_REMAP_TMR4 = 0x00000C10, + GPIO_REMAP_TMR4 = 0x00000C11, - GPIO_NO_REMAP_CAN1 = 0x00000D30, - GPIO_REMAP1_CAN1 = 0x00000D32, - GPIO_REMAP2_CAN1 = 0x00000D33, + GPIO_NO_REMAP_CAN1 = 0x00000D30, + GPIO_REMAP1_CAN1 = 0x00000D32, + GPIO_REMAP2_CAN1 = 0x00000D33, - GPIO_NO_REMAP_PD01 = 0x00000F10, - GPIO_REMAP_PD01 = 0x00000F11, + GPIO_NO_REMAP_PD01 = 0x00000F10, + GPIO_REMAP_PD01 = 0x00000F11, - GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010, - GPIO_REMAP_TMR5CH4_LSI = 0x00001011, + GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010, + GPIO_REMAP_TMR5CH4_LSI = 0x00001011, - GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110, - GPIO_REMAP_ADC1_ETRGINJ = 0x00001111, +#if !defined(APM32F10X_CL) + GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110, + GPIO_REMAP_ADC1_ETRGINJ = 0x00001111, - GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210, - GPIO_REMAP_ADC1_ETRGREG = 0x00001211, + GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210, + GPIO_REMAP_ADC1_ETRGREG = 0x00001211, - GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310, - GPIO_REMAP_ADC2_ETRGINJ = 0x00001311, + GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310, + GPIO_REMAP_ADC2_ETRGINJ = 0x00001311, - GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410, - GPIO_REMAP_ADC2_ETRGREG = 0x00001411, + GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410, + GPIO_REMAP_ADC2_ETRGREG = 0x00001411, - GPIO_NO_REMAP_CAN2 = 0x00001610, - GPIO_REMAP_CAN2 = 0x00001611, + GPIO_NO_REMAP_ETH = 0x00001510, + GPIO_REMAP_ETH = 0x00001511, - GPIO_NO_REMAP_SWJ = 0x00001870, - GPIO_REMAP_SWJ_NOJTRST = 0x00001871, - GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, - GPIO_REMAP_SWJ_DISABLE = 0x00001874, + GPIO_NO_REMAP_CAN2 = 0x00001610, + GPIO_REMAP_CAN2 = 0x00001611, - GPIO_NO_REMAP_EMMC_NADV = 0x00010A10, - GPIO_REMAP_EMMC_NADV = 0x00010A11, -}GPIO_REMAP_T; + GPIO_REMAP_MII = 0x00001710, + GPIO_REMAP_RMII = 0x00001711, + + GPIO_NO_REMAP_SWJ = 0x00001870, + GPIO_REMAP_SWJ_NOJTRST = 0x00001871, + GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, + GPIO_REMAP_SWJ_DISABLE = 0x00001874, + + GPIO_NO_REMAP_EMMC_NADV = 0x00010A10, + GPIO_REMAP_EMMC_NADV = 0x00010A11, + +#else /* APM32F10X_CL */ + GPIO_NO_REMAP_ETH_MAC = 0x00001510, + GPIO_REMAP_ETH_MAC = 0x00001511, + + GPIO_NO_REMAP_CAN2 = 0x00001610, + GPIO_REMAP_CAN2 = 0x00001611, + + GPIO_REMAP_MACEISEL_MII = 0x00001710, + GPIO_REMAP_MACEISEL_RMII = 0x00001711, + + GPIO_NO_REMAP_SWJ = 0x00001870, + GPIO_REMAP_SWJ_NOJTRST = 0x00001871, + GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, + GPIO_REMAP_SWJ_DISABLE = 0x00001874, + + GPIO_NO_REMAP_SPI3 = 0x00001C10, + GPIO_REMAP_SPI3 = 0x00001C11, + + GPIO_NO_REMAP_TMR2ITR1 = 0x00001D10, + GPIO_REMAP_TMR2ITR1 = 0x00001D11, + + GPIO_NO_REMAP_PTP_PPS = 0x00001E10, + GPIO_REMAP_PTP_PPS = 0x00001E11, +#endif +} GPIO_REMAP_T; /** * @brief gpio port source define */ typedef enum { - GPIO_PORT_SOURCE_A, - GPIO_PORT_SOURCE_B, - GPIO_PORT_SOURCE_C, - GPIO_PORT_SOURCE_D, - GPIO_PORT_SOURCE_E, - GPIO_PORT_SOURCE_F, - GPIO_PORT_SOURCE_G, -}GPIO_PORT_SOURCE_T; + GPIO_PORT_SOURCE_A, + GPIO_PORT_SOURCE_B, + GPIO_PORT_SOURCE_C, + GPIO_PORT_SOURCE_D, + GPIO_PORT_SOURCE_E, + GPIO_PORT_SOURCE_F, + GPIO_PORT_SOURCE_G, +} GPIO_PORT_SOURCE_T; /** * @brief gpio pin source define */ typedef enum { - GPIO_PIN_SOURCE_0, - GPIO_PIN_SOURCE_1, - GPIO_PIN_SOURCE_2, - GPIO_PIN_SOURCE_3, - GPIO_PIN_SOURCE_4, - GPIO_PIN_SOURCE_5, - GPIO_PIN_SOURCE_6, - GPIO_PIN_SOURCE_7, - GPIO_PIN_SOURCE_8, - GPIO_PIN_SOURCE_9, - GPIO_PIN_SOURCE_10, - GPIO_PIN_SOURCE_11, - GPIO_PIN_SOURCE_12, - GPIO_PIN_SOURCE_13, - GPIO_PIN_SOURCE_14, - GPIO_PIN_SOURCE_15, -}GPIO_PIN_SOURCE_T; + GPIO_PIN_SOURCE_0, + GPIO_PIN_SOURCE_1, + GPIO_PIN_SOURCE_2, + GPIO_PIN_SOURCE_3, + GPIO_PIN_SOURCE_4, + GPIO_PIN_SOURCE_5, + GPIO_PIN_SOURCE_6, + GPIO_PIN_SOURCE_7, + GPIO_PIN_SOURCE_8, + GPIO_PIN_SOURCE_9, + GPIO_PIN_SOURCE_10, + GPIO_PIN_SOURCE_11, + GPIO_PIN_SOURCE_12, + GPIO_PIN_SOURCE_13, + GPIO_PIN_SOURCE_14, + GPIO_PIN_SOURCE_15, +} GPIO_PIN_SOURCE_T; /**@} end of group GPIO_Enumerations*/ -/** @addtogroup GPIO_Structure Data Structure +/** @defgroup GPIO_Structures Structures @{ */ @@ -213,36 +247,36 @@ typedef enum */ typedef struct { - uint16_t pin; - GPIO_SPEED_T speed; - GPIO_MODE_T mode; -}GPIO_Config_T; + uint16_t pin; + GPIO_SPEED_T speed; + GPIO_MODE_T mode; +} GPIO_Config_T; -/**@} end of group GPIO_Structure*/ +/**@} end of group GPIO_Structures*/ -/** @addtogroup GPIO_Fuctions Fuctions +/** @defgroup GPIO_Functions Functions @{ */ -/** Reset and common Configuration */ +/* Reset and common Configuration */ void GPIO_Reset(GPIO_T* port); void GPIO_AFIOReset(void); void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig); void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig); -/** Read */ +/* Read */ uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin); uint16_t GPIO_ReadInputPort(GPIO_T* port); uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin); uint16_t GPIO_ReadOutputPort(GPIO_T* port); -/** Write */ +/* Write */ void GPIO_SetBit(GPIO_T* port, uint16_t pin); void GPIO_ResetBit(GPIO_T* port, uint16_t pin); void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue); void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal); -/** GPIO Configuration */ +/* GPIO Configuration */ void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin); void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); void GPIO_EnableEventOutput(void); @@ -250,9 +284,9 @@ void GPIO_DisableEventOutput(void); void GPIO_ConfigPinRemap(GPIO_REMAP_T remap); void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); -/**@} end of group GPIO_Fuctions*/ -/**@} end of group GPIO_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group GPIO_Functions*/ +/**@} end of group GPIO_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h index ee2cfc71d3..7a4e4da2ea 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the I2C firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_I2C_H #define __APM32F10X_I2C_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup I2C_Enumerations Enumerations +/** @defgroup I2C_Enumerations Enumerations @{ */ @@ -150,58 +152,56 @@ typedef enum */ typedef enum { - /** I2C Master Events */ - /** Event 5: Communication start event */ - I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, //!< BUSBSYFLG, MSFLG and STARTFLG flag + /* I2C Master Events */ + /* Event 5: Communication start event */ + I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, /*!< BUSBSYFLG, MSFLG and STARTFLG flag */ - /** - * Event 6: 7-bit Address Acknowledge - * in case of master receiver - */ - I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, //!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */ - I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, //!< BUSBSYFLG, MSFLG and ADDRFLG flags */ - /** - * Event 9: Master has sent the first byte - * in 10-bit address mode - */ - I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, //!< BUSBSYFLG, MSFLG and ADDR10FLG flags */ + /* Event 6: 7-bit Address Acknowledge + in case of master receiver + */ + I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, /*!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */ + I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, /*!< BUSBSYFLG, MSFLG and ADDRFLG flags */ + /* Event 9: Master has sent the first byte + in 10-bit address mode + */ + I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, /*!< BUSBSYFLG, MSFLG and ADDR10FLG flags */ - /** Master RECEIVER mode */ - /** Event 7 */ - I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, //!< BUSBSYFLG, MSFLG and RXBNEFLG flags */ + /* Master RECEIVER mode */ + /* Event 7 */ + I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, /*!< BUSBSYFLG, MSFLG and RXBNEFLG flags */ - /** Master TRANSMITTER mode */ - /** Event 8 */ - I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */ - /** Event 8_2 */ - I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */ + /* Master TRANSMITTER mode */ + /* Event 8 */ + I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, /*!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */ + /* Event 8_2 */ + I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, /*!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */ - /** EV1 (all the events below are variants of EV1) */ - /** 1, Case of One Single Address managed by the slave */ - I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, //!< BUSBSYFLG and ADDRFLG flags */ - I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, //!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */ + /* EV1 (all the events below are variants of EV1) */ + /* 1, Case of One Single Address managed by the slave */ + I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, /*!< BUSBSYFLG and ADDRFLG flags */ + I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, /*!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */ - /** 2, Case of Dual address managed by the slave */ - I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, //!< DUALF and BUSBSYFLG flags */ - I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, //!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */ + /* 2, Case of Dual address managed by the slave */ + I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, /*!< DUALF and BUSBSYFLG flags */ + I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, /*!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */ - /** 3, Case of General Call enabled for the slave */ - I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, //!< GENCALL and BUSBSYFLG flags */ + /* 3, Case of General Call enabled for the slave */ + I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, /*!< GENCALL and BUSBSYFLG flags */ - /** Slave RECEIVER mode */ - /** EV2 */ - I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, //!< BUSBSYFLG and RXBNEFLG flags */ - /** EV4 */ - I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, //!< STOPFLG flag */ + /* Slave RECEIVER mode */ + /* EV2 */ + I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, /*!< BUSBSYFLG and RXBNEFLG flags */ + /* EV4 */ + I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, /*!< STOPFLG flag */ - /** Slave TRANSMITTER mode */ - /** EV3 */ - I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, //!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */ - I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, //!< TRFLG, BUSBSYFLG and TXBEFLG flags */ - /** EV3_2 */ - I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, //!< AEFLG flag */ + /* Slave TRANSMITTER mode */ + /* EV3 */ + I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, /*!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */ + I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, /*!< TRFLG, BUSBSYFLG and TXBEFLG flags */ + /* EV3_2 */ + I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, /*!< AEFLG flag */ } I2C_EVENT_T; /** @@ -209,7 +209,7 @@ typedef enum */ typedef enum { - /** STS2 register flags */ + /* STS2 register flags */ I2C_FLAG_DUALADDR, I2C_FLAG_SMMHADDR, I2C_FLAG_SMBDADDR, @@ -218,7 +218,7 @@ typedef enum I2C_FLAG_BUSBSY, I2C_FLAG_MS, - /** STS1 register flags */ + /* STS1 register flags */ I2C_FLAG_SMBALT, I2C_FLAG_TTE, I2C_FLAG_PECE, @@ -258,7 +258,7 @@ typedef enum /**@} end of group I2C_Enumerations*/ -/** @addtogroup I2C_Structure Data Structure +/** @defgroup I2C_Structures Structures @{ */ @@ -275,14 +275,14 @@ typedef struct I2C_ACK_ADDRESS_T ackAddress; } I2C_Config_T; -/**@} end of group I2C_Structure*/ +/**@} end of group I2C_Structures*/ -/** @addtogroup I2C_Fuctions Fuctions +/** @defgroup I2C_Functions Functions @{ */ -/** I2C reset and configuration */ +/* I2C reset and configuration */ void I2C_Reset(I2C_T* i2c); void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig); void I2C_ConfigStructInit(I2C_Config_T* i2cConfig); @@ -300,7 +300,7 @@ void I2C_DisableDualAddress(I2C_T* i2c); void I2C_EnableGeneralCall(I2C_T* i2c); void I2C_DisableGeneralCall(I2C_T* i2c); -/** Transmit Configuration */ +/* Transmit Configuration */ void I2C_TxData(I2C_T* i2c, uint8_t data); uint8_t I2C_RxData(I2C_T* i2c); void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction); @@ -321,13 +321,13 @@ void I2C_EnableStretchClock(I2C_T* i2c); void I2C_DisableStretchClock(I2C_T* i2c); void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle); -/** DMA */ +/* DMA */ void I2C_EnableDMA(I2C_T* i2c); void I2C_DisableDMA(I2C_T* i2c); void I2C_EnableDMALastTransfer(I2C_T* i2c); void I2C_DisableDMALastTransfer(I2C_T* i2c); -/** Interrupts and flags */ +/* Interrupts and flags */ void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt); void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt); uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent); @@ -337,9 +337,9 @@ void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag); -/**@} end of group I2C_Fuctions*/ +/**@} end of group I2C_Functions*/ /**@} end of group I2C_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h index 962f8a1a54..f0965ab896 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the IWDT firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_IWDT_H #define __APM32F10X_IWDT_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup IWDT_Enumerations Enumerations +/** @defgroup IWDT_Enumerations Enumerations @{ */ @@ -51,7 +53,7 @@ typedef enum { IWDT_KEYWORD_RELOAD = 0xAAAA, IWDT_KEYWORD_ENABLE = 0xCCCC -}IWDT_KEYWORD_T; +} IWDT_KEYWORD_T; /** * @brief IWDT Write Access define @@ -60,7 +62,7 @@ typedef enum { IWDT_WRITEACCESS_ENABLE = 0x5555, IWDT_WRITEACCESS_DISABLE = 0x0000 -}IWDT_WRITEACCESS_T; +} IWDT_WRITEACCESS_T; /** * @brief IWDT Divider @@ -74,7 +76,7 @@ typedef enum IWDT_DIVIDER_64 = 0x04, IWDT_DIVIDER_128 = 0x05, IWDT_DIVIDER_256 = 0x06 -}IWDT_DIVIDER_T; +} IWDT_DIVIDER_T; /** * @brief IWDT Flag @@ -83,37 +85,37 @@ typedef enum { IWDT_FLAG_PSCU = BIT0, IWDT_FLAG_CNTU = BIT1 -}IWDT_FLAG_T; +} IWDT_FLAG_T; /**@} end of group IWDT_Enumerations*/ -/** @addtogroup IWDT_Fuctions Fuctions +/** @defgroup IWDT_Functions Functions @{ */ -/** Enable IWDT */ +/* Enable IWDT */ void IWDT_Enable(void); -/** Refresh IWDT */ +/* Refresh IWDT */ void IWDT_Refresh(void); -/** Counter reload */ +/* Counter reload */ void IWDT_ConfigReload(uint16_t reload); -/** Divider */ +/* Divider */ void IWDT_ConfigDivider(uint8_t div); -/** Write Access */ +/* Write Access */ void IWDT_EnableWriteAccess(void); void IWDT_DisableWriteAccess(void); -/** flag */ +/* flag */ uint8_t IWDT_ReadStatusFlag(uint16_t flag); -/**@} end of group IWDT_Fuctions*/ -/**@} end of group IWDT_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group IWDT_Functions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h index 7448aebe11..82cc03ac8f 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h @@ -4,9 +4,9 @@ * @brief This file provides all the miscellaneous firmware functions. * Include NVIC,SystemTick and Power management. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -16,7 +16,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -24,16 +24,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_MISC_H #define __APM32F10X_MISC_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -41,7 +43,7 @@ @{ */ -/** @addtogroup MISC_Enumerations Enumerations +/** @defgroup MISC_Enumerations Enumerations @{ */ @@ -50,66 +52,66 @@ */ typedef enum { - NVIC_VECT_TAB_RAM = 0x20000000, - NVIC_VECT_TAB_FLASH = 0x08000000, -}NVIC_VECT_TAB_T; + NVIC_VECT_TAB_RAM = 0x20000000, + NVIC_VECT_TAB_FLASH = 0x08000000, +} NVIC_VECT_TAB_T; /** * @brief system low power mode */ typedef enum { - NVIC_LOWPOWER_SEVONPEND = 0x10, - NVIC_LOWPOWER_SLEEPDEEP = 0x04, - NVIC_LOWPOWER_SLEEPONEXIT = 0x02 -}NVIC_LOWPOWER_T; + NVIC_LOWPOWER_SEVONPEND = 0x10, + NVIC_LOWPOWER_SLEEPDEEP = 0x04, + NVIC_LOWPOWER_SLEEPONEXIT = 0x02 +} NVIC_LOWPOWER_T; /** * @brief nvic priority group */ typedef enum { - NVIC_PRIORITY_GROUP_0 = 0x700, //!< 0 bits for pre-emption priority,4 bits for subpriority - NVIC_PRIORITY_GROUP_1 = 0x600, //!< 1 bits for pre-emption priority,3 bits for subpriority - NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority - NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority - NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority -}NVIC_PRIORITY_GROUP_T; + NVIC_PRIORITY_GROUP_0 = 0x700, /*!< 0 bits for pre-emption priority,4 bits for subpriority */ + NVIC_PRIORITY_GROUP_1 = 0x600, /*!< 1 bits for pre-emption priority,3 bits for subpriority */ + NVIC_PRIORITY_GROUP_2 = 0x500, /*!< 2 bits for pre-emption priority,2 bits for subpriority */ + NVIC_PRIORITY_GROUP_3 = 0x400, /*!< 3 bits for pre-emption priority,1 bits for subpriority */ + NVIC_PRIORITY_GROUP_4 = 0x300 /*!< 4 bits for pre-emption priority,0 bits for subpriority */ +} NVIC_PRIORITY_GROUP_T; /** * @brief SysTick Clock source */ typedef enum { - SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00, - SYSTICK_CLK_SOURCE_HCLK = 0x01 -}SYSTICK_CLK_SOURCE_T; + SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00, + SYSTICK_CLK_SOURCE_HCLK = 0x01 +} SYSTICK_CLK_SOURCE_T; /**@} end of group MISC_Enumerations*/ -/** @addtogroup MISC_Fuctions Fuctions +/** @defgroup MISC_Functions Functions @{ */ -/** NVIC */ +/* NVIC */ void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup); void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority); void NVIC_DisableIRQRequest(IRQn_Type irq); -/** Vector Table */ +/* Vector Table */ void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset); -/** Power */ +/* Power */ void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode); void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode); -/** Systick */ +/* Systick */ void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource); -/**@} end of group MISC_Fuctions*/ +/**@} end of group MISC_Functions*/ /**@} end of group MISC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h index 3c7797a863..05dfe7b0a2 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the PMU firmware library. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_PMU_H #define __APM32F10X_PMU_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup PMU_Enumerations Enumerations +/** @defgroup PMU_Enumerations Enumerations @{ */ @@ -49,14 +51,14 @@ */ typedef enum { - PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V - PMU_PVD_LEVEL_2V3 = 0x01, //!< PVD detection level set to 2.3V - PMU_PVD_LEVEL_2V4 = 0x02, //!< PVD detection level set to 2.4V - PMU_PVD_LEVEL_2V5 = 0x03, //!< PVD detection level set to 2.5V - PMU_PVD_LEVEL_2V6 = 0x04, //!< PVD detection level set to 2.6V - PMU_PVD_LEVEL_2V7 = 0x05, //!< PVD detection level set to 2.7V - PMU_PVD_LEVEL_2V8 = 0x06, //!< PVD detection level set to 2.8V - PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V + PMU_PVD_LEVEL_2V2 = 0x00, /*!< PVD detection level set to 2.2V */ + PMU_PVD_LEVEL_2V3 = 0x01, /*!< PVD detection level set to 2.3V */ + PMU_PVD_LEVEL_2V4 = 0x02, /*!< PVD detection level set to 2.4V */ + PMU_PVD_LEVEL_2V5 = 0x03, /*!< PVD detection level set to 2.5V */ + PMU_PVD_LEVEL_2V6 = 0x04, /*!< PVD detection level set to 2.6V */ + PMU_PVD_LEVEL_2V7 = 0x05, /*!< PVD detection level set to 2.7V */ + PMU_PVD_LEVEL_2V8 = 0x06, /*!< PVD detection level set to 2.8V */ + PMU_PVD_LEVEL_2V9 = 0x07, /*!< PVD detection level set to 2.9V */ } PMU_PVD_LEVEL_T; /** @@ -90,14 +92,14 @@ typedef enum /**@} end of group PMU_Enumerations*/ -/** @addtogroup PMU_Fuctions Fuctions +/** @addtogroup PMU_Functions Functions @{ */ -/** PMU Reset */ +/* PMU Reset */ void PMU_Reset(void); -/** Configuration and Operation modes */ +/* Configuration and Operation modes */ void PMU_EnableBackupAccess(void); void PMU_DisableBackupAccess(void); void PMU_EnablePVD(void); @@ -108,13 +110,13 @@ void PMU_DisableWakeUpPin(void); void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry); void PMU_EnterSTANDBYMode(void); -/** flags */ +/* flags */ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag); void PMU_ClearStatusFlag(PMU_FLAG_T flag); -/**@} end of group PMU_Fuctions*/ -/**@} end of group PMU_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group PMU_Functions*/ +/**@} end of group PMU_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h index 7035b6ce38..446b2ebaa0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h @@ -3,9 +3,9 @@ * * @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_QSPI_H #define __APM32F10X_QSPI_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,42 @@ @{ */ -/** @addtogroup QSPI_Enumerations Enumerations +/** @defgroup QSPI_Macros Macros + @{ +*/ + +/* CTRL1 register reset value */ +#define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007) +/* CTRL2 register reset value */ +#define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00) +/* SSIEN register reset value */ +#define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00) +/* SLAEN register reset value */ +#define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00) +/* BR register reset value */ +#define QSPI_BR_RESET_VALUE ((uint32_t)0x00) +/* TFTL register reset value */ +#define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00) +/* RFTL register reset value */ +#define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00) +/* TFL register reset value */ +#define QSPI_TFL_RESET_VALUE ((uint32_t)0x00) +/* RFL register reset value */ +#define QSPI_RFL_RESET_VALUE ((uint32_t)0x00) +/* STS register reset value */ +#define QSPI_STS_RESET_VALUE ((uint32_t)0x06) +/* INTEN register reset value */ +#define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F) +/* RSD register reset value */ +#define QSPI_RSD_RESET_VALUE ((uint32_t)0x00) +/* CTRL3 register reset value */ +#define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200) +/* IOSW register reset value */ +#define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00) + +/**@} end of group QSPI_Macros*/ + +/** @defgroup QSPI_Enumerations Enumerations @{ */ @@ -49,21 +86,21 @@ */ typedef enum { - QSPI_FRF_STANDARD, //!< Standard mode - QSPI_FRF_DUAL, //!< Dual SPI - QSPI_FRF_QUAD //!< QUAD SPI -}QSPI_FRF_T; + QSPI_FRF_STANDARD, /*!< Standard mode */ + QSPI_FRF_DUAL, /*!< Dual SPI */ + QSPI_FRF_QUAD /*!< QUAD SPI */ +} QSPI_FRF_T; /** * @brief Transmission mode */ typedef enum { - QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode - QSPI_TRANS_MODE_TX, //!< TX mode only - QSPI_TRANS_MODE_RX, //!< RX mode only - QSPI_TRANS_MODE_EEPROM_READ //!< EEPROM read mode -}QSPI_TRANS_MODE_T; + QSPI_TRANS_MODE_TX_RX, /*!< TX and RX mode */ + QSPI_TRANS_MODE_TX, /*!< TX mode only */ + QSPI_TRANS_MODE_RX, /*!< RX mode only */ + QSPI_TRANS_MODE_EEPROM_READ /*!< EEPROM read mode */ +} QSPI_TRANS_MODE_T; /** * @brief Clock polarity @@ -72,7 +109,7 @@ typedef enum { QSPI_CLKPOL_LOW, QSPI_CLKPOL_HIGH -}QSPI_CLKPOL_T; +} QSPI_CLKPOL_T; /** * @brief Clock phase @@ -81,7 +118,7 @@ typedef enum { QSPI_CLKPHA_1EDGE, QSPI_CLKPHA_2EDGE -}QSPI_CLKPHA_T; +} QSPI_CLKPHA_T; /** * @brief Data format size @@ -117,46 +154,46 @@ typedef enum QSPI_DFS_30BIT, QSPI_DFS_31BIT, QSPI_DFS_32BIT -}QSPI_DFS_T; +} QSPI_DFS_T; /** * @brief QSPI flag */ typedef enum { - QSPI_FLAG_BUSY = BIT0, //!< Busy flag - QSPI_FLAG_TFNF = BIT1, //!< TX FIFO not full flag - QSPI_FLAG_TFE = BIT2, //!< TX FIFO empty flag - QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag - QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag - QSPI_FLAG_DCE = BIT6 //!< Data collision error -}QSPI_FLAG_T; + QSPI_FLAG_BUSY = BIT0, /*!< Busy flag */ + QSPI_FLAG_TFNF = BIT1, /*!< TX FIFO not full flag */ + QSPI_FLAG_TFE = BIT2, /*!< TX FIFO empty flag */ + QSPI_FLAG_RFNE = BIT3, /*!< RX FIFO not empty flag */ + QSPI_FLAG_RFF = BIT4, /*!< RX FIFO full flag */ + QSPI_FLAG_DCE = BIT6 /*!< Data collision error */ +} QSPI_FLAG_T; /** * @brief QSPI interrupt source */ typedef enum { - QSPI_INT_TFE = BIT0, //!< TX FIFO empty interrupt - QSPI_INT_TFO = BIT1, //!< TX FIFO overflow interrupt - QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt - QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt - QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt - QSPI_INT_MST = BIT5 //!< Master interrupt -}QSPI_INT_T; + QSPI_INT_TFE = BIT0, /*!< TX FIFO empty interrupt */ + QSPI_INT_TFO = BIT1, /*!< TX FIFO overflow interrupt */ + QSPI_INT_RFU = BIT2, /*!< RX FIFO underflow interrupt */ + QSPI_INT_RFO = BIT3, /*!< RX FIFO overflow interrupt */ + QSPI_INT_RFF = BIT4, /*!< RX FIFO full interrupt */ + QSPI_INT_MST = BIT5 /*!< Master interrupt */ +} QSPI_INT_T; /** * @brief QSPI interrupt flag */ typedef enum { - QSPI_INT_FLAG_TFE = BIT0, //!< TX FIFO empty interrupt flag - QSPI_INT_FLAG_TFO = BIT1, //!< TX FIFO overflow interrupt flag - QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag - QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag - QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag - QSPI_INT_FLAG_MST = BIT5 //!< Master interrupt flag -}QSPI_INT_FLAG_T; + QSPI_INT_FLAG_TFE = BIT0, /*!< TX FIFO empty interrupt flag */ + QSPI_INT_FLAG_TFO = BIT1, /*!< TX FIFO overflow interrupt flag */ + QSPI_INT_FLAG_RFU = BIT2, /*!< RX FIFO underflow interrupt flag */ + QSPI_INT_FLAG_RFO = BIT3, /*!< RX FIFO overflow interrupt flag */ + QSPI_INT_FLAG_RFF = BIT4, /*!< RX FIFO full interrupt flag */ + QSPI_INT_FLAG_MST = BIT5 /*!< Master interrupt flag */ +} QSPI_INT_FLAG_T; /** * @brief Reception sample edge @@ -165,7 +202,7 @@ typedef enum { QSPI_RSE_RISING, QSPI_RSE_FALLING -}QSPI_RSE_T; +} QSPI_RSE_T; /** * @brief Instruction length @@ -176,7 +213,7 @@ typedef enum QSPI_INST_LEN_4BIT, QSPI_INST_LEN_8BIT, QSPI_INST_LEN_16BIT -}QSPI_INST_LEN_T; +} QSPI_INST_LEN_T; /** * @brief QSPI address length @@ -199,7 +236,7 @@ typedef enum QSPI_ADDR_LEN_52BIT, QSPI_ADDR_LEN_56BIT, QSPI_ADDR_LEN_60BIT -}QSPI_ADDR_LEN_T; +} QSPI_ADDR_LEN_T; /** * @brief Instruction and address transmission mode @@ -209,7 +246,7 @@ typedef enum QSPI_INST_ADDR_TYPE_STANDARD, QSPI_INST_TYPE_STANDARD, QSPI_INST_ADDR_TYPE_FRF -}QSPI_INST_ADDR_TYPE_T; +} QSPI_INST_ADDR_TYPE_T; /** * @brief Slave Select Toggle @@ -218,134 +255,97 @@ typedef enum { QSPI_SST_DISABLE, QSPI_SST_ENABLE -}QSPI_SST_T; +} QSPI_SST_T; /**@} end of group QSPI_Enumerations*/ -/** @addtogroup QSPI_Macros Macros - @{ -*/ - -/** CTRL1 register reset value */ -#define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007) -/** CTRL2 register reset value */ -#define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00) -/** SSIEN register reset value */ -#define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00) -/** SLAEN register reset value */ -#define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00) -/** BR register reset value */ -#define QSPI_BR_RESET_VALUE ((uint32_t)0x00) -/** TFTL register reset value */ -#define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00) -/** RFTL register reset value */ -#define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00) -/** TFL register reset value */ -#define QSPI_TFL_RESET_VALUE ((uint32_t)0x00) -/** RFL register reset value */ -#define QSPI_RFL_RESET_VALUE ((uint32_t)0x00) -/** STS register reset value */ -#define QSPI_STS_RESET_VALUE ((uint32_t)0x06) -/** INTEN register reset value */ -#define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F) -/** RSD register reset value */ -#define QSPI_RSD_RESET_VALUE ((uint32_t)0x00) -/** CTRL3 register reset value */ -#define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200) -/** IOSW register reset value */ -#define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00) - -/**@} end of group QSPI_Macros*/ - - -/** @addtogroup QSPI_Structure Data Structure +/** @defgroup QSPI_Structure Data Structure @{ */ typedef struct { - QSPI_SST_T selectSlaveToggle; //!< Slave Select Toggle - QSPI_FRF_T frameFormat; //!< Frame format - uint16_t clockDiv; //!< Clock divider - QSPI_CLKPOL_T clockPolarity; //!< Clock polarity - QSPI_CLKPHA_T clockPhase; //!< Clock phase - QSPI_DFS_T dataFrameSize; //!< Data frame size -}QSPI_Config_T; + QSPI_SST_T selectSlaveToggle; /*!< Slave Select Toggle */ + QSPI_FRF_T frameFormat; /*!< Frame format */ + uint16_t clockDiv; /*!< Clock divider */ + QSPI_CLKPOL_T clockPolarity; /*!< Clock polarity */ + QSPI_CLKPHA_T clockPhase; /*!< Clock phase */ + QSPI_DFS_T dataFrameSize; /*!< Data frame size */ +} QSPI_Config_T; /**@} end of group QSPI_Structure*/ - -/** @addtogroup QSPI_Fuctions Fuctions +/** @defgroup QSPI_Functions Functions @{ */ -/** Reset */ +/* Reset */ void QSPI_Reset(void); -/** Configuration */ -void QSPI_Config(QSPI_Config_T *qspiConfig); -void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig); +/* Configuration */ +void QSPI_Config(QSPI_Config_T* qspiConfig); +void QSPI_ConfigStructInit(QSPI_Config_T* qspiConfig); -/** Data frame size, frame number, frame format */ +/* Data frame size, frame number, frame format */ void QSPI_ConfigFrameNum(uint16_t num); void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs); void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat); -/** Disable or Enable */ +/* Disable or Enable */ void QSPI_Enable(void); void QSPI_Disable(void); -/** TX and RX FIFO */ +/* TX and RX FIFO */ uint8_t QSPI_ReadTxFifoDataNum(void); uint8_t QSPI_ReadRxFifoDataNum(void); void QSPI_ConfigRxFifoThreshold(uint8_t threshold); void QSPI_ConfigTxFifoThreshold(uint8_t threshold); void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold); -/** RX Sample */ +/* RX Sample */ void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse); void QSPI_ConfigRxSampleDelay(uint8_t delay); -/** Clock stretch */ +/* Clock stretch */ void QSPI_EnableClockStretch(void); void QSPI_DisableClockStretch(void); -/** Instruction, address, Wait cycle */ +/* Instruction, address, Wait cycle */ void QSPI_ConfigInstLen(QSPI_INST_LEN_T len); void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len); void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type); void QSPI_ConfigWaitCycle(uint8_t cycle); -/** IO */ +/* IO */ void QSPI_OpenIO(void); void QSPI_CloseIO(void); -/** Transmission mode */ +/* Transmission mode */ void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode); -/** Rx and Tx data */ +/* Rx and Tx data */ uint32_t QSPI_RxData(void); void QSPI_TxData(uint32_t data); -/** Slave */ +/* Slave */ void QSPI_EnableSlave(void); void QSPI_DisableSlave(void); -/** Interrupt */ +/* Interrupt */ void QSPI_EnableInterrupt(uint32_t interrupt); void QSPI_DisableInterrupt(uint32_t interrupt); -/** Flag */ +/* Flag */ uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag); void QSPI_ClearStatusFlag(void); uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag); void QSPI_ClearIntFlag(uint32_t flag); -/**@} end of group QSPI_Fuctions*/ +/**@} end of group QSPI_Functions*/ /**@} end of group QSPI_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ #ifdef __cplusplus } #endif -#endif /* __APM32F10X_QSPI_H_ */ +#endif /* __APM32F10X_QSPI_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h index 2e58e7c7e1..42e9f6df2c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the RCM firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_RCM_H #define __APM32F10X_RCM_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup RCM_Enumerations Enumerations +/** @defgroup RCM_Enumerations Enumerations @{ */ @@ -59,6 +61,15 @@ typedef enum */ typedef enum { +#if defined(APM32F10X_CL) + RCM_PLLMF_4 = 2, + RCM_PLLMF_5, + RCM_PLLMF_6, + RCM_PLLMF_7, + RCM_PLLMF_8, + RCM_PLLMF_9, + RCM_PLLMF_6_5 = 13, +#else RCM_PLLMF_2, RCM_PLLMF_3, RCM_PLLMF_4, @@ -74,8 +85,41 @@ typedef enum RCM_PLLMF_14, RCM_PLLMF_15, RCM_PLLMF_16 +#endif } RCM_PLLMF_T; +/** + * @brief PLL2 multiplication factor + */ +typedef enum +{ + RCM_PLL2MF_8 = 6, + RCM_PLL2MF_9 = 7, + RCM_PLL2MF_10 = 8, + RCM_PLL2MF_11 = 9, + RCM_PLL2MF_12 = 10, + RCM_PLL2MF_13 = 11, + RCM_PLL2MF_14 = 12, + RCM_PLL2MF_16 = 14, + RCM_PLL2MF_20 = 15 +} RCM_PLL2MF_T; + +/** + * @brief PLL3 multiplication factor + */ +typedef enum +{ + RCM_PLL3MF_8 = 6, + RCM_PLL3MF_9 = 7, + RCM_PLL3MF_10 = 8, + RCM_PLL3MF_11 = 9, + RCM_PLL3MF_12 = 10, + RCM_PLL3MF_13 = 11, + RCM_PLL3MF_14 = 12, + RCM_PLL3MF_16 = 14, + RCM_PLL3MF_20 = 15 +} RCM_PLL3MF_T; + /** * @brief System clock select */ @@ -86,6 +130,64 @@ typedef enum RCM_SYSCLK_SEL_PLL } RCM_SYSCLK_SEL_T; +#if defined(APM32F10X_CL) +/** + * @brief PLLPSC1 Source + */ +typedef enum +{ + RCM_PLLPSC1_SRC_HSE, + RCM_PLLPSC1_SRC_PLL2 +} RCM_PLLPSC1_SRC_T; + +/** + * @brief PLLPSC1 divider Number + */ +typedef enum +{ + RCM_PLLPSC1_DIV_1, + RCM_PLLPSC1_DIV_2, + RCM_PLLPSC1_DIV_3, + RCM_PLLPSC1_DIV_4, + RCM_PLLPSC1_DIV_5, + RCM_PLLPSC1_DIV_6, + RCM_PLLPSC1_DIV_7, + RCM_PLLPSC1_DIV_8, + RCM_PLLPSC1_DIV_9, + RCM_PLLPSC1_DIV_10, + RCM_PLLPSC1_DIV_11, + RCM_PLLPSC1_DIV_12, + RCM_PLLPSC1_DIV_13, + RCM_PLLPSC1_DIV_14, + RCM_PLLPSC1_DIV_15, + RCM_PLLPSC1_DIV_16 +} RCM_PLLPSC1_DIV_T; + +/** + * @brief PLLPSC2 divider Number + */ +typedef enum +{ + RCM_PLLPSC2_DIV_1, + RCM_PLLPSC2_DIV_2, + RCM_PLLPSC2_DIV_3, + RCM_PLLPSC2_DIV_4, + RCM_PLLPSC2_DIV_5, + RCM_PLLPSC2_DIV_6, + RCM_PLLPSC2_DIV_7, + RCM_PLLPSC2_DIV_8, + RCM_PLLPSC2_DIV_9, + RCM_PLLPSC2_DIV_10, + RCM_PLLPSC2_DIV_11, + RCM_PLLPSC2_DIV_12, + RCM_PLLPSC2_DIV_13, + RCM_PLLPSC2_DIV_14, + RCM_PLLPSC2_DIV_15, + RCM_PLLPSC2_DIV_16 +} RCM_PLLPSC2_DIV_T; + +#endif + /** * @brief AHB divider Number */ @@ -122,9 +224,18 @@ typedef enum RCM_USB_DIV_1_5, RCM_USB_DIV_1, RCM_USB_DIV_2, - RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx) + RCM_USB_DIV_2_5 /*!< (Only for High-density devices for APM32F103xx) */ } RCM_USB_DIV_T; +/** + * @brief OTG FS divider Number + */ +typedef enum +{ + RCM_OTGFS_DIV_1_5, + RCM_OTGFS_DIV_1 +} RCM_OTGFS_DIV_T; + /** * @brief FPU divider Number */ @@ -155,6 +266,24 @@ typedef enum RCM_LSE_BYPASS } RCM_LSE_T; +/** + * @brief I2S2 clock select + */ +typedef enum +{ + RCM_I2S2CLK_SYSCLK, + RCM_I2S2CLK_DOUBLE_PLL3 +} RCM_I2S2CLK_T; + +/** + * @brief I2S3 clock select + */ +typedef enum +{ + RCM_I2S3CLK_SYSCLK, + RCM_I2S3CLK_DOUBLE_PLL3 +} RCM_I2S3CLK_T; + /** * @brief RTC clock select */ @@ -174,7 +303,13 @@ typedef enum RCM_MCOCLK_SYSCLK, RCM_MCOCLK_HSI, RCM_MCOCLK_HSE, - RCM_MCOCLK_PLLCLK_DIV_2 + RCM_MCOCLK_PLLCLK_DIV_2, +#if defined(APM32F10X_CL) + RCM_MCOCLK_PLL2CLK = 8, + RCM_MCOCLK_PLL3CLK_DIV_2, + RCM_MCOCLK_OSCCLK, + RCM_MCOCLK_PLL3CLK +#endif } RCM_MCOCLK_T; /** @@ -183,8 +318,12 @@ typedef enum typedef enum { RCM_PLLSEL_HSI_DIV_2 = 0, +#if defined(APM32F10X_CL) + RCM_PLLSEL_PREDIV1 = 1, +#else RCM_PLLSEL_HSE = 1, RCM_PLLSEL_HSE_DIV2 = 3, +#endif /* APM32F10X_CL */ } RCM_PLLSEL_T; /** @@ -192,12 +331,14 @@ typedef enum */ typedef enum { - RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt - RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt - RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt - RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt - RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt - RCM_INT_CSS = BIT7 //!< Clock security system interrupt + RCM_INT_LSIRDY = BIT0, /*!< LSI ready interrupt */ + RCM_INT_LSERDY = BIT1, /*!< LSE ready interrupt */ + RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */ + RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */ + RCM_INT_PLLRDY = BIT4, /*!< PLL ready interrupt */ + RCM_INT_PLL2RDY = BIT5, /*!< PLL2 ready interrupt */ + RCM_INT_PLL3RDY = BIT6, /*!< PLL3 ready interrupt */ + RCM_INT_CSS = BIT7 /*!< Clock security system interrupt */ } RCM_INT_T; /** @@ -205,15 +346,19 @@ typedef enum */ typedef enum { - RCM_AHB_PERIPH_DMA1 = BIT0, - RCM_AHB_PERIPH_DMA2 = BIT1, - RCM_AHB_PERIPH_SRAM = BIT2, - RCM_AHB_PERIPH_FPU = BIT3, - RCM_AHB_PERIPH_FMC = BIT4, - RCM_AHB_PERIPH_QSPI = BIT5, - RCM_AHB_PERIPH_CRC = BIT6, - RCM_AHB_PERIPH_EMMC = BIT8, - RCM_AHB_PERIPH_SDIO = BIT10 + RCM_AHB_PERIPH_DMA1 = BIT0, + RCM_AHB_PERIPH_DMA2 = BIT1, + RCM_AHB_PERIPH_SRAM = BIT2, + RCM_AHB_PERIPH_FPU = BIT3, + RCM_AHB_PERIPH_FMC = BIT4, + RCM_AHB_PERIPH_QSPI = BIT5, + RCM_AHB_PERIPH_CRC = BIT6, + RCM_AHB_PERIPH_EMMC = BIT8, + RCM_AHB_PERIPH_SDIO = BIT10, + RCM_AHB_PERIPH_OTG_FS = BIT12, + RCM_AHB_PERIPH_ETH_MAC = BIT14, + RCM_AHB_PERIPH_ETH_MAC_TX = BIT15, + RCM_AHB_PERIPH_ETH_MAC_RX = BIT16 } RCM_AHB_PERIPH_T; /** @@ -271,51 +416,63 @@ typedef enum */ typedef enum { - RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag - RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag - RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag - RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag - RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag - RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag - RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag - RCM_FLAG_SWRST = 0x21C, //!< Software reset flag - RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag - RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag - RCM_FLAG_LPRRST = 0x21F //!< Low-power reset flag + RCM_FLAG_HSIRDY = 0x001, /*!< HSI Ready Flag */ + RCM_FLAG_HSERDY = 0x011, /*!< HSE Ready Flag */ + RCM_FLAG_PLLRDY = 0x019, /*!< PLL Ready Flag */ + RCM_FLAG_PLL2RDY = 0x01B, /*!< PLL2 Ready Flag */ + RCM_FLAG_PLL3RDY = 0x01D, /*!< PLL3 Ready Flag */ + RCM_FLAG_LSERDY = 0x101, /*!< LSE Ready Flag */ + RCM_FLAG_LSIRDY = 0x201, /*!< LSI Ready Flag */ + RCM_FLAG_PINRST = 0x21A, /*!< PIN reset flag */ + RCM_FLAG_PORRST = 0x21B, /*!< POR/PDR reset flag */ + RCM_FLAG_SWRST = 0x21C, /*!< Software reset flag */ + RCM_FLAG_IWDTRST = 0x21D, /*!< Independent watchdog reset flag */ + RCM_FLAG_WWDTRST = 0x21E, /*!< Window watchdog reset flag */ + RCM_FLAG_LPRRST = 0x21F /*!< Low-power reset flag */ } RCM_FLAG_T; -/**@} end of group RCM_Enumerations*/ +/**@} end of group RCM_Enumerations */ -/** @addtogroup RCM_Fuctions Fuctions +/** @defgroup RCM_Functions Functions @{ */ -/** Function description */ +/* Function description */ -/** RCM Reset */ +/* RCM Reset */ void RCM_Reset(void); -/** HSE clock */ +/* HSE clock */ void RCM_ConfigHSE(RCM_HSE_T state); uint8_t RCM_WaitHSEReady(void); -/** HSI clock */ +/* HSI clock */ void RCM_ConfigHSITrim(uint8_t HSITrim); void RCM_EnableHSI(void); void RCM_DisableHSI(void); -/** LSE and LSI clock */ +/* LSE and LSI clock */ void RCM_ConfigLSE(RCM_LSE_T state); void RCM_EnableLSI(void); void RCM_DisableLSI(void); -/** PLL clock */ +/* PLL clock */ void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf); void RCM_EnablePLL(void); void RCM_DisablePLL(void); +#if defined(APM32F10X_CL) +void RCM_EnablePLL2(void); +void RCM_DisablePLL2(void); +void RCM_EnablePLL3(void); +void RCM_DisablePLL3(void); +void RCM_ConfigPLLPSC1(RCM_PLLPSC1_SRC_T pllPsc1Src, RCM_PLLPSC1_DIV_T pllPsc1); +void RCM_ConfigPLLPSC2(RCM_PLLPSC2_DIV_T pllpsc2); +void RCM_ConfigPLL2(RCM_PLL2MF_T pll2Mf); +void RCM_ConfigPLL3(RCM_PLL3MF_T pll3Mf); +#endif -/** Clock Security System */ +/* Clock Security System */ void RCM_EnableCSS(void); void RCM_DisableCSS(void); @@ -323,26 +480,32 @@ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock); void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); -/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */ +/* Config clock prescaler of AHB, APB1, APB2, USB and ADC */ void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv); void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div); void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div); +#if defined(APM32F10X_CL) +void RCM_ConfigI2S2CLK(RCM_I2S2CLK_T i2s2ClkSelect); +void RCM_ConfigI2S3CLK(RCM_I2S2CLK_T i2s3ClkSelect); +void RCM_ConfigOTGFSCLK(RCM_OTGFS_DIV_T OTGDiv); +#else void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv); void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv); +#endif void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv); -/** RTC clock */ +/* RTC clock */ void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect); void RCM_EnableRTCCLK(void); void RCM_DisableRTCCLK(void); -/** Reads the clock frequency */ +/* Reads the clock frequency */ uint32_t RCM_ReadSYSCLKFreq(void); uint32_t RCM_ReadHCLKFreq(void); void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); uint32_t RCM_ReadADCCLKFreq(void); -/** Enable or disable Periph Clock */ +/* Enable or disable Periph Clock */ void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph); void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph); void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); @@ -350,17 +513,21 @@ void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); -/** Enable or disable Periph Reset */ +/* Enable or disable Periph Reset */ +#if defined(APM32F10X_CL) +void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph); +void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph); +#endif void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); -/** Backup domain reset */ +/* Backup domain reset */ void RCM_EnableBackupReset(void); void RCM_DisableBackupReset(void); -/** Interrupts and flags */ +/* Interrupts and flags */ void RCM_EnableInterrupt(uint32_t interrupt); void RCM_DisableInterrupt(uint32_t interrupt); uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag); @@ -368,9 +535,9 @@ void RCM_ClearStatusFlag(void); uint8_t RCM_ReadIntFlag(RCM_INT_T flag); void RCM_ClearIntFlag(uint32_t flag); -/**@} end of group RCM_Fuctions*/ -/**@} end of group RCM_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group RCM_Functions */ +/**@} end of group RCM_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h index b6eb995ce2..5b7008f280 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the RTC firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_RTC_H #define __APM32F10X_RTC_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,38 +42,37 @@ @{ */ -/** @addtogroup RTC_Enumerations Enumerations +/** @defgroup RTC_Enumerations Enumerations @{ */ typedef enum { - RTC_FLAG_OC = 0x0020, //!< RTC Operation Complete flag - RTC_FLAG_RSYNC = 0x0008, //!< Registers Synchronized flag - RTC_FLAG_OVR = 0x0004, //!< Overflow flag - RTC_FLAG_ALR = 0x0002, //!< Alarm flag - RTC_FLAG_SEC = 0x0001 //!< Second flag + RTC_FLAG_OC = 0x0020, /*!< RTC Operation Complete flag */ + RTC_FLAG_RSYNC = 0x0008, /*!< Registers Synchronized flag */ + RTC_FLAG_OVR = 0x0004, /*!< Overflow flag */ + RTC_FLAG_ALR = 0x0002, /*!< Alarm flag */ + RTC_FLAG_SEC = 0x0001 /*!< Second flag */ } RTC_FLAG_T; typedef enum { - RTC_INT_OVR = 0x0004, //!< Overflow interrupt - RTC_INT_ALR = 0x0002, //!< Alarm interrupt - RTC_INT_SEC = 0x0001 //!< Second interrupt + RTC_INT_OVR = 0x0004, /*!< Overflow interrupt */ + RTC_INT_ALR = 0x0002, /*!< Alarm interrupt */ + RTC_INT_SEC = 0x0001 /*!< Second interrupt */ } RTC_INT_T; -/**@} end of group RTC_Enumerations*/ +/**@} end of group RTC_Enumerations */ - -/** @addtogroup RTC_Fuctions Fuctions +/** @defgroup RTC_Functions Functions @{ */ -/** Operation modes */ +/* Operation modes */ void RTC_EnableConfigMode(void); void RTC_DisableConfigMode(void); -/** Configuration */ +/* Configuration */ uint32_t RTC_ReadCounter(void); void RTC_ConfigCounter(uint32_t value); void RTC_ConfigPrescaler(uint32_t value); @@ -80,7 +81,7 @@ uint32_t RTC_ReadDivider(void); void RTC_WaitForLastTask(void); void RTC_WaitForSynchro(void); -/** Interrupts and flags */ +/* Interrupts and flags */ void RTC_EnableInterrupt(uint16_t interrupt); void RTC_DisableInterrupt(uint16_t interrupt); uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag); @@ -88,9 +89,9 @@ void RTC_ClearStatusFlag(uint16_t flag); uint8_t RTC_ReadIntFlag(RTC_INT_T flag); void RTC_ClearIntFlag(uint16_t flag); -/**@} end of group RTC_Fuctions*/ -/**@} end of group RTC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group RTC_Functions */ +/**@} end of group RTC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h index 11f4b0707f..48b51fe4eb 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h @@ -3,9 +3,9 @@ * * @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_SCI2C_H #define __APM32F10X_SCI2C_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup SCI2C_Enumerations Enumerations +/** @defgroup SCI2C_Enumerations Enumerations @{ */ @@ -52,7 +54,7 @@ typedef enum SCI2C_SPEED_STANDARD = 1, SCI2C_SPEED_FAST, SCI2C_SPEED_HIGH -}SCI2C_SPEED_T; +} SCI2C_SPEED_T; /** * @brief Address mode @@ -61,7 +63,7 @@ typedef enum { SCI2C_ADDR_MODE_7BIT, SCI2C_ADDR_MODE_10BIT -}SCI2C_ADDR_MODE_T; +} SCI2C_ADDR_MODE_T; /** * @brief SCI2C mode enumeration @@ -70,7 +72,7 @@ typedef enum { SCI2C_MODE_MASTER, SCI2C_MODE_SLAVE -}SCI2C_MODE_T; +} SCI2C_MODE_T; /** * @brief Restart enable or disable @@ -79,7 +81,7 @@ typedef enum { SCI2C_RESTART_DISABLE, SCI2C_RESTART_ENABLE -}SCI2C_RESTART_T; +} SCI2C_RESTART_T; /** * @brief Enable or disable generate stop condition @@ -88,7 +90,7 @@ typedef enum { SCI2C_STOP_DISABLE, SCI2C_STOP_ENABLE -}SCI2C_STOP_T; +} SCI2C_STOP_T; /** * @brief Data direction */ @@ -96,69 +98,69 @@ typedef enum { SCI2C_DATA_DIR_WRITE, SCI2C_DATA_DIR_READ, -}SCI2C_DATA_DIR_T; +} SCI2C_DATA_DIR_T; /** * @brief SCI2C interrupt */ typedef enum { - SCI2C_INT_RFU = BIT0, //!< Rx FIFO underflow interrupt - SCI2C_INT_RFO = BIT1, //!< Rx FIFO onverflow interrupt - SCI2C_INT_RFF = BIT2, //!< Rx FIFO full interrupt - SCI2C_INT_TFO = BIT3, //!< Tx FIFO onverflow interrupt - SCI2C_INT_TFE = BIT4, //!< Tx FIFO empty interrupt - SCI2C_INT_RR = BIT5, //!< Read request interrupt - SCI2C_INT_TA = BIT6, //!< Tx abort interrupt - SCI2C_INT_RD = BIT7, //!< Read done interrupt - SCI2C_INT_ACT = BIT8, //!< Activity interrupt - SCI2C_INT_STPD = BIT9, //!< Stop detect interrupt - SCI2C_INT_STAD = BIT10, //!< Start detect interrupt - SCI2C_INT_GC = BIT11, //!< Gernal call interrupt - SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt - SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt - SCI2C_INT_ALL = BIT15 //!< All interrupt -}SCI2C_INT_T; + SCI2C_INT_RFU = BIT0, /*!< Rx FIFO underflow interrupt */ + SCI2C_INT_RFO = BIT1, /*!< Rx FIFO onverflow interrupt */ + SCI2C_INT_RFF = BIT2, /*!< Rx FIFO full interrupt */ + SCI2C_INT_TFO = BIT3, /*!< Tx FIFO onverflow interrupt */ + SCI2C_INT_TFE = BIT4, /*!< Tx FIFO empty interrupt */ + SCI2C_INT_RR = BIT5, /*!< Read request interrupt */ + SCI2C_INT_TA = BIT6, /*!< Tx abort interrupt */ + SCI2C_INT_RD = BIT7, /*!< Read done interrupt */ + SCI2C_INT_ACT = BIT8, /*!< Activity interrupt */ + SCI2C_INT_STPD = BIT9, /*!< Stop detect interrupt */ + SCI2C_INT_STAD = BIT10, /*!< Start detect interrupt */ + SCI2C_INT_GC = BIT11, /*!< Gernal call interrupt */ + SCI2C_INT_RSTAD = BIT12, /*!< Restart detect interrupt */ + SCI2C_INT_MOH = BIT13, /*!< Master on hold interrupt */ + SCI2C_INT_ALL = BIT15 /*!< All interrupt */ +} SCI2C_INT_T; /** * @brief Flag enumeration */ typedef enum { - SCI2C_FLAG_ACT = BIT0, //!< Activity flag - SCI2C_FLAG_TFNF = BIT1, //!< Tx FIFO not full flag - SCI2C_FLAG_TFE = BIT2, //!< Tx FIFO empty flag - SCI2C_FLAG_RFNE = BIT3, //!< Rx FIFO not empty flag - SCI2C_FLAG_RFF = BIT4, //!< Rx FIFO full flag - SCI2C_FLAG_MA = BIT5, //!< Master activity flag - SCI2C_FLAG_SA = BIT6, //!< Slave activity flag - SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag - SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag - SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag -}SCI2C_FLAG_T; + SCI2C_FLAG_ACT = BIT0, /*!< Activity flag */ + SCI2C_FLAG_TFNF = BIT1, /*!< Tx FIFO not full flag */ + SCI2C_FLAG_TFE = BIT2, /*!< Tx FIFO empty flag */ + SCI2C_FLAG_RFNE = BIT3, /*!< Rx FIFO not empty flag */ + SCI2C_FLAG_RFF = BIT4, /*!< Rx FIFO full flag */ + SCI2C_FLAG_MA = BIT5, /*!< Master activity flag */ + SCI2C_FLAG_SA = BIT6, /*!< Slave activity flag */ + SCI2C_FLAG_I2CEN = BIT8 | BIT0, /*!< I2C enable flag */ + SCI2C_FLAG_SDWB = BIT8 | BIT1, /*!< Slave disable while busy flag */ + SCI2C_FLAG_SRDL = BIT8 | BIT2 /*!< Slave receive data lost flag */ +} SCI2C_FLAG_T; /** * @brief Tx abort source */ typedef enum { - SCI2C_TAS_AD7NA = BIT0, //!< 7 bit address mode NACK - SCI2C_TAS_AD10FBNA = BIT1, //!< 10 bit address mode first byte NACK - SCI2C_TAS_AD10SBNA = BIT2, //!< 10 bit address mode second byte NACK - SCI2C_TAS_TDNA = BIT3, //!< Tx data NACK - SCI2C_TAS_GCNA = BIT4, //!< Gernal call NACK - SCI2C_TAS_GCR = BIT5, //!< Gernal call read - SCI2C_TAS_HSAD = BIT6, //!< High speed ack detected - SCI2C_TAS_SNR = BIT7, //!< Start byte no restart - SCI2C_TAS_RNR10B = BIT8, //!< Read 10bit address mode when restart disable - SCI2C_TAS_MSTDIS = BIT9, //!< Master disable - SCI2C_TAS_ARBLOST = BIT10, //!< Arbitration lost - SCI2C_TAS_LFTF = BIT11, //!< Slave flush tx FIFO - SCI2C_TAS_SAL = BIT12, //!< Slave arbitration lost - SCI2C_TAS_SRI = BIT13, //!< Slave read done - SCI2C_TAS_USRARB = BIT14, //!< User abort - SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter -}SCI2C_TAS_T; + SCI2C_TAS_AD7NA = BIT0, /*!< 7 bit address mode NACK */ + SCI2C_TAS_AD10FBNA = BIT1, /*!< 10 bit address mode first byte NACK */ + SCI2C_TAS_AD10SBNA = BIT2, /*!< 10 bit address mode second byte NACK */ + SCI2C_TAS_TDNA = BIT3, /*!< Tx data NACK */ + SCI2C_TAS_GCNA = BIT4, /*!< Gernal call NACK */ + SCI2C_TAS_GCR = BIT5, /*!< Gernal call read */ + SCI2C_TAS_HSAD = BIT6, /*!< High speed ack detected */ + SCI2C_TAS_SNR = BIT7, /*!< Start byte no restart */ + SCI2C_TAS_RNR10B = BIT8, /*!< Read 10bit address mode when restart disable */ + SCI2C_TAS_MSTDIS = BIT9, /*!< Master disable */ + SCI2C_TAS_ARBLOST = BIT10, /*!< Arbitration lost */ + SCI2C_TAS_LFTF = BIT11, /*!< Slave flush tx FIFO */ + SCI2C_TAS_SAL = BIT12, /*!< Slave arbitration lost */ + SCI2C_TAS_SRI = BIT13, /*!< Slave read done */ + SCI2C_TAS_USRARB = BIT14, /*!< User abort */ + SCI2C_TAS_FLUCNT = BIT15 /*!< Tx flush counter */ +} SCI2C_TAS_T; /** * @brief DMA Enable @@ -167,17 +169,15 @@ typedef enum { SCI2C_DMA_RX = BIT0, SCI2C_DMA_TX = BIT1, -}SCI2C_DMA_T; +} SCI2C_DMA_T; -/**@} end of group SCI2C_Enumerations*/ +/**@} end of group SCI2C_Enumerations */ - -/** @addtogroup SCI2C_Macros Macros +/** @defgroup SCI2C_Macros Macros @{ */ -/** Macros description */ - +/* Macros description */ #define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E) #define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055) #define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55) @@ -206,117 +206,116 @@ typedef enum #define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01) #define SCI2C_FIFO_DEPTH (0X08) -/**@} end of group SCI2C_Macros*/ +/**@} end of group SCI2C_Macros */ -/** @addtogroup SCI2C_Structure Data Structure +/** @defgroup SCI2C_Structures Structures @{ */ /** - * @brief Struct description + * @brief Structure description */ typedef struct { - uint16_t slaveAddr; //!< Slave address. - SCI2C_MODE_T mode; //!< Specifies mode, master mode or slave mode - SCI2C_SPEED_T speed; //!< Specifies speed. Standard speed, fast speed or high speed. - uint16_t clkLowPeriod; //!< SCL high period - uint16_t clkHighPeriod; //!< SCL low period - uint8_t rxFifoThreshold; //!< Rx FIFO threshold - uint8_t txFifoThreshold; //!< Tx FIFO threshold - SCI2C_RESTART_T restart; //!< Enable or disable restart - SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode. -}SCI2C_Config_T; + uint16_t slaveAddr; /*!< Slave address. */ + SCI2C_MODE_T mode; /*!< Specifies mode, master mode or slave mode */ + SCI2C_SPEED_T speed; /*!< Specifies speed. Standard speed, fast speed or high speed. */ + uint16_t clkLowPeriod; /*!< SCL high period */ + uint16_t clkHighPeriod; /*!< SCL low period */ + uint8_t rxFifoThreshold; /*!< Rx FIFO threshold */ + uint8_t txFifoThreshold; /*!< Tx FIFO threshold */ + SCI2C_RESTART_T restart; /*!< Enable or disable restart */ + SCI2C_ADDR_MODE_T addrMode; /*!< Address mode. 7-bit or 10-bit mode. */ +} SCI2C_Config_T; -/**@} end of group SCI2C_Structure*/ +/**@} end of group SCI2C_Structure */ - -/** @addtogroup SCI2C_Fuctions Fuctions +/** @defgroup SCI2C_Functions Functions @{ */ -/** Reset */ -void SCI2C_Reset(SCI2C_T *i2c); +/* Reset */ +void SCI2C_Reset(SCI2C_T* i2c); -/** Configuration */ -void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig); -void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig); +/* Configuration */ +void SCI2C_Config(SCI2C_T* i2c, SCI2C_Config_T* sci2cConfig); +void SCI2C_ConfigStructInit(SCI2C_Config_T* sci2cConfig); -/** Stop detect */ -void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c); -void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c); -void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c); -void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c); +/* Stop detect */ +void SCI2C_EnableStopDetectAddressed(SCI2C_T* i2c); +void SCI2C_DisableStopDetectAddressed(SCI2C_T* i2c); +void SCI2C_EnableStopDetectMasterActivity(SCI2C_T* i2c); +void SCI2C_DisableStopDetectMasterActivity(SCI2C_T* i2c); -/** Restart */ -void SCI2C_EnableRestart(SCI2C_T *i2c); -void SCI2C_DisableRestart(SCI2C_T *i2c); +/* Restart */ +void SCI2C_EnableRestart(SCI2C_T* i2c); +void SCI2C_DisableRestart(SCI2C_T* i2c); -/** Speed */ -void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed); +/* Speed */ +void SCI2C_ConfigSpeed(SCI2C_T* i2c, SCI2C_SPEED_T speed); -/** Address */ -void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); -void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); +/* Address */ +void SCI2C_ConfigMasterAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); +void SCI2C_ConfigSlaveAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); -/** Master mode and slave mode */ -void SCI2C_EnableMasterMode(SCI2C_T *i2c); -void SCI2C_DisableMasterMode(SCI2C_T *i2c); -void SCI2C_EnableSlaveMode(SCI2C_T *i2c); -void SCI2C_DisableSlaveMode(SCI2C_T *i2c); -void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code); +/* Master mode and slave mode */ +void SCI2C_EnableMasterMode(SCI2C_T* i2c); +void SCI2C_DisableMasterMode(SCI2C_T* i2c); +void SCI2C_EnableSlaveMode(SCI2C_T* i2c); +void SCI2C_DisableSlaveMode(SCI2C_T* i2c); +void SCI2C_ConfigMasterCode(SCI2C_T* i2c, uint8_t code); -/** Data */ -void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir); -void SCI2C_TxData(SCI2C_T *i2c, uint8_t data); -uint8_t SCI2C_RxData(SCI2C_T *i2c); -void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data); +/* Data */ +void SCI2C_ConfigDataDir(SCI2C_T* i2c, SCI2C_DATA_DIR_T dir); +void SCI2C_TxData(SCI2C_T* i2c, uint8_t data); +uint8_t SCI2C_RxData(SCI2C_T* i2c); +void SCI2C_ConfigDataRegister(SCI2C_T* i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data); -/** Rx and Tx FIFO */ -uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c); -uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c); -void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); -void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); +/* Rx and Tx FIFO */ +uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T* i2c); +uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T* i2c); +void SCI2C_ConfigRxFifoThreshold(SCI2C_T* i2c, uint8_t threshold); +void SCI2C_ConfigTxFifoThreshold(SCI2C_T* i2c, uint8_t threshold); -/** I2C Enable, disable, abort, block */ -void SCI2C_Enable(SCI2C_T *i2c); -void SCI2C_Disable(SCI2C_T *i2c); -void SCI2C_Abort(SCI2C_T *i2c); -void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable); +/* I2C Enable, disable, abort, block */ +void SCI2C_Enable(SCI2C_T* i2c); +void SCI2C_Disable(SCI2C_T* i2c); +void SCI2C_Abort(SCI2C_T* i2c); +void SCI2C_BlockTxCmd(SCI2C_T* i2c, uint8_t enable); -/** SCL and SDA */ -void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod); -void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold); -void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay); +/* SCL and SDA */ +void SCI2C_ConfigClkPeriod(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod); +void SCI2C_ConfigSDAHoldTime(SCI2C_T* i2c, uint16_t txHold, uint8_t rxHold); +void SCI2C_ConfigSDADelayTime(SCI2C_T* i2c, uint8_t delay); -/** ACK and NACK */ -void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable); -void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable); +/* ACK and NACK */ +void SCI2C_GernalCallAck(SCI2C_T* i2c, uint8_t enable); +void SCI2C_SlaveDataNackOnly(SCI2C_T* i2c, uint8_t enable); -/** Abort */ -uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c); +/* Abort */ +uint32_t SCI2C_ReadTxAbortSource(SCI2C_T* i2c); -/** DMA */ -void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); -void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); -void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt); -void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt); +/* DMA */ +void SCI2C_EnableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma); +void SCI2C_DisableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma); +void SCI2C_ConfigDMATxDataLevel(SCI2C_T* i2c, uint8_t cnt); +void SCI2C_ConfigDMARxDataLevel(SCI2C_T* i2c, uint8_t cnt); -/** Spike suppression limit */ -void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit); +/* Spike suppression limit */ +void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint8_t limit); -/** Ingerrupt and flag */ -uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag); -void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); -uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); -uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); -void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt); -void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt); +/* Ingerrupt and flag */ +uint8_t SCI2C_ReadStatusFlag(SCI2C_T* i2c, SCI2C_FLAG_T flag); +void SCI2C_ClearIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag); +uint8_t SCI2C_ReadIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag); +uint8_t SCI2C_ReadRawIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag); +void SCI2C_EnableInterrupt(SCI2C_T* i2c, uint16_t interrupt); +void SCI2C_DisableInterrupt(SCI2C_T* i2c, uint16_t interrupt); -/**@} end of group SCI2C_Fuctions*/ -/**@} end of group SCI2C_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group SCI2C_Functions */ +/**@} end of group SCI2C_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h index 7f63a65dd2..0c63633767 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the SDIO firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_SDIO_H #define __APM32F10X_SDIO_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup SDIO_Enumerations Enumerations +/** @defgroup SDIO_Enumerations Enumerations @{ */ @@ -51,7 +53,7 @@ typedef enum { SDIO_CLOCK_EDGE_RISING = 0x00000000, SDIO_CLOCK_EDGE_FALLING = 0x00002000 -}SDIO_CLOCK_EDGE_T; +} SDIO_CLOCK_EDGE_T; /** * @brief SDIO clock bypass @@ -60,7 +62,7 @@ typedef enum { SDIO_CLOCK_BYPASS_DISABLE = 0x00000000, SDIO_CLOCK_BYPASS_ENABLE = 0x00000400 -}SDIO_CLOCK_BYPASS_T; +} SDIO_CLOCK_BYPASS_T; /** * @brief SDIO clock power save @@ -69,7 +71,7 @@ typedef enum { SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000, SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200 -}SDIO_CLOCK_POWER_SAVE_T; +} SDIO_CLOCK_POWER_SAVE_T; /** * @brief SDIO bus wide @@ -79,7 +81,7 @@ typedef enum SDIO_BUS_WIDE_1B = 0x00000000, SDIO_BUS_WIDE_4B = 0x00000800, SDIO_BUS_WIDE_8B = 0x00001000 -}SDIO_BUS_WIDE_T; +} SDIO_BUS_WIDE_T; /** * @brief SDIO hardware flow control @@ -88,7 +90,7 @@ typedef enum { SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000, SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000 -}SDIO_HARDWARE_FLOW_CONTROL_T; +} SDIO_HARDWARE_FLOW_CONTROL_T; /** * @brief SDIO power state @@ -97,7 +99,7 @@ typedef enum { SDIO_POWER_STATE_OFF = 0x00000000, SDIO_POWER_STATE_ON = 0x00000003 -}SDIO_POWER_STATE_T; +} SDIO_POWER_STATE_T; /** * @brief SDIO interrupt sources @@ -128,7 +130,7 @@ typedef enum SDIO_INT_RXDA = 0x00200000, SDIO_INT_SDIOINT = 0x00400000, SDIO_INT_ATAEND = 0x00800000 -}SDIO_INT_T; +} SDIO_INT_T; /** * @brief SDIO response @@ -138,7 +140,7 @@ typedef enum SDIO_RESPONSE_NO = 0x00000000, SDIO_RESPONSE_SHORT = 0x00000040, SDIO_RESPONSE_LONG = 0x000000C0 -}SDIO_RESPONSE_T; +} SDIO_RESPONSE_T; /** * @brief SDIO wait interrupt state @@ -148,7 +150,7 @@ typedef enum SDIO_WAIT_NO = 0x00000000, SDIO_WAIT_INT = 0x00000100, SDIO_WAIT_PEND = 0x00000200 -}SDIO_WAIT_T; +} SDIO_WAIT_T; /** * @brief SDIO CPSM state @@ -157,7 +159,7 @@ typedef enum { SDIO_CPSM_DISABLE = 0x00000000, SDIO_CPSM_ENABLE = 0x00000400 -}SDIO_CPSM_T; +} SDIO_CPSM_T; /** * @brief SDIO response registers @@ -168,7 +170,7 @@ typedef enum SDIO_RES2 = 0x00000004, SDIO_RES3 = 0x00000008, SDIO_RES4 = 0x0000000C -}SDIO_RES_T; +} SDIO_RES_T; /** * @brief SDIO data block size @@ -190,7 +192,7 @@ typedef enum SDIO_DATA_BLOCKSIZE_496B = 0x000000C0, SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0, SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0 -}SDIO_DATA_BLOCKSIZE_T; +} SDIO_DATA_BLOCKSIZE_T; /** * @brief SDIO transfer direction @@ -199,7 +201,7 @@ typedef enum { SDIO_TRANSFER_DIR_TO_CARD = 0x00000000, SDIO_TRANSFER_DIR_TO_SDIO = 0x00000002 -}SDIO_TRANSFER_DIR_T; +} SDIO_TRANSFER_DIR_T; /** * @brief SDIO transfer type @@ -208,7 +210,7 @@ typedef enum { SDIO_TRANSFER_MODE_BLOCK = 0x00000000, SDIO_TRANSFER_MODE_STREAM = 0x00000004 -}SDIO_TRANSFER_MODE_T; +} SDIO_TRANSFER_MODE_T; /** * @brief SDIO DPSM state @@ -217,7 +219,7 @@ typedef enum { SDIO_DPSM_DISABLE = 0x00000000, SDIO_DPSM_ENABLE = 0x00000001 -}SDIO_DPSM_T; +} SDIO_DPSM_T; /** * @brief SDIO flag @@ -248,7 +250,7 @@ typedef enum SDIO_FLAG_RXDA = 0x00200000, SDIO_FLAG_SDIOINT = 0x00400000, SDIO_FLAG_ATAEND = 0x00800000 -}SDIO_FLAG_T; +} SDIO_FLAG_T; /** * @brief SDIO read wait mode @@ -257,75 +259,75 @@ typedef enum { SDIO_READ_WAIT_MODE_CLK = 0x00000001, SDIO_READ_WAIT_MODE_DATA2 = 0x00000000 -}SDIO_READ_WAIT_MODE_T; +} SDIO_READ_WAIT_MODE_T; -/**@} end of group SDIO_Enumerations*/ +/**@} end of group SDIO_Enumerations */ -/** @addtogroup SDIO_Macros Macros +/** @defgroup SDIO_Macros Macros @{ */ -/** ------------ SDIO registers bit address in the alias region ----------- */ +/* ------------ SDIO registers bit address in the alias region ----------- */ #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) -/** --- CLKCTRL Register ---*/ +/* --- CLKCTRL Register --- */ -/** Alias word address of CLKEN bit */ +/* Alias word address of CLKEN bit */ #define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04) #define CLKEN_BitNumber 0x08 #define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4)) -/** --- CMD Register ---*/ +/* --- CMD Register --- */ -/** Alias word address of SDIOSC bit */ +/* Alias word address of SDIOSC bit */ #define CMD_OFFSET (SDIO_OFFSET + 0x0C) #define SDIOSC_BitNumber 0x0B #define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4)) -/** Alias word address of CMDCPEN bit */ +/* Alias word address of CMDCPEN bit */ #define CMDCPEN_BitNumber 0x0C #define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4)) -/** Alias word address of INTEN bit */ +/* Alias word address of INTEN bit */ #define INTEN_BitNumber 0x0D #define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4)) -/** Alias word address of ATACMD bit */ +/* Alias word address of ATACMD bit */ #define ATACMD_BitNumber 0x0E #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) -/** --- DCTRL Register ---*/ +/* --- DCTRL Register --- */ -/** Alias word address of DMAEN bit */ +/* Alias word address of DMAEN bit */ #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) #define DMAEN_BitNumber 0x03 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) -/** Alias word address of RWSTR bit */ +/* Alias word address of RWSTR bit */ #define RWSTR_BitNumber 0x08 #define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4)) -/** Alias word address of RWSTOP bit */ +/* Alias word address of RWSTOP bit */ #define RWSTOP_BitNumber 0x09 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) -/** Alias word address of RDWAIT bit */ +/* Alias word address of RDWAIT bit */ #define RDWAIT_BitNumber 0x0A #define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4)) -/** Alias word address of SDIOF bit */ +/* Alias word address of SDIOF bit */ #define SDIOF_BitNumber 0x0B #define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4)) -/**@} end of group SDIO_Macros*/ +/**@} end of group SDIO_Macros */ -/** @addtogroup SDIO_Structure Data Structure +/** @defgroup SDIO_Structures Structures @{ */ /** - * @brief SDIO Config structure definition + * @brief SDIO Configure structure definition */ typedef struct { @@ -335,10 +337,10 @@ typedef struct SDIO_BUS_WIDE_T busWide; SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl; uint8_t clockDiv; -}SDIO_Config_T; +} SDIO_Config_T; /** - * @brief SDIO CMD Config structure definition + * @brief SDIO CMD Configure structure definition */ typedef struct { @@ -347,10 +349,10 @@ typedef struct SDIO_RESPONSE_T response; SDIO_WAIT_T wait; SDIO_CPSM_T CPSM; -}SDIO_CmdConfig_T; +} SDIO_CmdConfig_T; /** - * @brief SDIO Data Config structure definition + * @brief SDIO Data Configure structure definition */ typedef struct { @@ -360,16 +362,15 @@ typedef struct SDIO_TRANSFER_DIR_T transferDir; SDIO_TRANSFER_MODE_T transferMode; SDIO_DPSM_T DPSM; -}SDIO_DataConfig_T; +} SDIO_DataConfig_T; -/**@} end of group SDIO_Structure*/ +/**@} end of group SDIO_Structures */ - -/** @addtogroup SDIO_Fuctions Fuctions +/** @defgroup SDIO_Functions Functions @{ */ -/** SDIO reset and configuration */ +/* SDIO reset and configuration */ void SDIO_Reset(void); void SDIO_Config(SDIO_Config_T* sdioConfig); void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig); @@ -378,17 +379,17 @@ void SDIO_DisableClock(void); void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState); uint32_t SDIO_ReadPowerState(void); -/** DMA */ +/* DMA */ void SDIO_EnableDMA(void); void SDIO_DisableDMA(void); -/** Command */ -void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig); +/* Command */ +void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig); void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdconfig); uint8_t SDIO_ReadCommandResponse(void); uint32_t SDIO_ReadResponse(SDIO_RES_T res); -/** SDIO data configuration */ +/* SDIO data configuration */ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig); void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig); uint32_t SDIO_ReadDataCounter(void); @@ -396,7 +397,7 @@ void SDIO_WriteData(uint32_t data); uint32_t SDIO_ReadData(void); uint32_t SDIO_ReadFIFOCount(void); -/** SDIO mode */ +/* SDIO mode */ void SDIO_EnableStartReadWait(void); void SDIO_DisableStartReadWait(void); void SDIO_EnableStopReadWait(void); @@ -413,7 +414,7 @@ void SDIO_DisableCEATAInterrupt(void); void SDIO_EnableTxCEATA(void); void SDIO_DisableTxCEATA(void); -/** Interrupt and flags */ +/* Interrupt and flags */ void SDIO_EnableInterrupt(uint32_t interrupt); void SDIO_DisableInterrupt(uint32_t interrupt); uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag); @@ -421,12 +422,12 @@ void SDIO_ClearStatusFlag(uint32_t flag); uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag); void SDIO_ClearIntFlag(uint32_t flag); -/**@} end of group SDIO_Fuctions*/ -/**@} end of group SDIO_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group SDIO_Functions */ +/**@} end of group SDIO_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } #endif -#endif /* __APM32F10X_SDIO_H */ +#endif /*__APM32F10X_SDIO_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_smc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_smc.h new file mode 100644 index 0000000000..77be32fe0c --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_smc.h @@ -0,0 +1,370 @@ +/*! + * @file apm32f10x_smc.h + * + * @brief This file contains all the functions prototypes for the SMC firmware library + * + * @version V1.0.4 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F10X_SMC_H +#define __APM32F10X_SMC_H + +/* Includes */ +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver + @{ +*/ + +/** @addtogroup SMC_Driver SMC Driver + @{ +*/ + +/** @defgroup SMC_Enumerations Enumerations + @{ +*/ + +/** + * @brief SMC NORSRAM_Bank + */ +typedef enum +{ + SMC_BANK1_NORSRAM_1 = 0x00000000, + SMC_BANK1_NORSRAM_2 = 0x00000002, + SMC_BANK1_NORSRAM_3 = 0x00000004, + SMC_BANK1_NORSRAM_4 = 0x00000006 +} SMC_BANK1_NORSRAM_T; + +/** + * @brief SMC NAND and PC Card Bank + */ +typedef enum +{ + SMC_BANK2_NAND = 0x00000010, + SMC_BANK3_NAND = 0x00000100, + SMC_BANK4_PCCARD = 0x00001000 +} SMC_BANK_NAND_T; + +/** + * @brief SMC_Data_Address_Bus_Multiplexing + */ +typedef enum +{ + SMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000, + SMC_DATA_ADDRESS_MUX_ENABLE = 0x00000002 +} SMC_DATA_ADDRESS_MUX_T; + +/** + * @brief SMC_Memory_Type + */ +typedef enum +{ + SMC_MEMORY_TYPE_SRAM = 0x00000000, + SMC_MEMORY_TYPE_PSRAM = 0x00000004, + SMC_MEMORY_TYPE_NOR = 0x00000008 +} SMC_MEMORY_TYPE_T; + +/** + * @brief SMC_Data_Width + */ +typedef enum +{ + SMC_MEMORY_DATA_WIDTH_8BIT = 0x00000000, + SMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010 +} SMC_MEMORY_DATA_WIDTH_T; + +/** + * @brief SMC_Burst_Access_Mode + */ +typedef enum +{ + SMC_BURST_ACCESS_MODE_DISABLE = 0x00000000, + SMC_BURST_ACCESS_MODE_ENABLE = 0x00000100 +} SMC_BURST_ACCESS_MODE_T; + +/** + * @brief SMC_AsynchronousWait + */ +typedef enum +{ + SMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000, + SMC_ASYNCHRONOUS_WAIT_ENABLE = 0x00008000 +} SMC_ASYNCHRONOUS_WAIT_T; + +/** + * @brief SMC_Wait_Signal_Polarity + */ +typedef enum +{ + SMC_WAIT_SIGNAL_POLARITY_LOW = 0x00000000, + SMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200 +} SMC_WAIT_SIGNAL_POLARITY_T; + +/** + * @brief SMC_Wrap_Mode + */ +typedef enum +{ + SMC_WRAP_MODE_DISABLE = 0x00000000, + SMC_WRAP_MODE_ENABLE = 0x00000400 +} SMC_WRAP_MODE_T; + +/** + * @brief SMC_Wait_Timing + */ +typedef enum +{ + SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000, + SMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800 +} SMC_WAIT_SIGNAL_ACTIVE_T; + +/** + * @brief SMC_Write_Operation + */ +typedef enum +{ + SMC_WRITE_OPERATION_DISABLE = 0x00000000, + SMC_WRITE_OPERATION_ENABLE = 0x00001000 +} SMC_WRITE_OPERATION_T; + +/** + * @brief SMC_Wait_Signal + */ +typedef enum +{ + SMC_WAITE_SIGNAL_DISABLE = 0x00000000, + SMC_WAITE_SIGNAL_ENABLE = 0x00002000 +} SMC_WAITE_SIGNAL_T; + +/** + * @brief SMC_Extended_Mode + */ +typedef enum +{ + SMC_EXTENDEN_MODE_DISABLE = 0x00000000, + SMC_EXTENDEN_MODE_ENABLE = 0x00004000 +} SMC_EXTENDEN_MODE_T; + +/** + * @brief SMC_Write_Burst + */ +typedef enum +{ + SMC_WRITE_BURST_DISABLE = 0x00000000, + SMC_WRITE_BURST_ENABLE = 0x00080000 +} SMC_WRITE_BURST_T; + +/** + * @brief SMC_WAIT_FEATURE + */ +typedef enum +{ + SMC_WAIT_FEATURE_DISABLE = 0x00000000, + SMC_WAIT_FEATURE_ENABLE = 0x00000002 +} SMC_WAIT_FEATURE_T; + +/** + * @brief SMC_ECC + */ +typedef enum +{ + SMC_ECC_DISABLE = 0x00000000, + SMC_ECC_ENABLE = 0x00000040 +} SMC_ECC_T; + +/** + * @brief SMC_ECC_Page_Size + */ +typedef enum +{ + SMC_ECC_PAGE_SIZE_BYTE_256 = 0x00000000, + SMC_ECC_PAGE_SIZE_BYTE_512 = 0x00020000, + SMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000, + SMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000, + SMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000, + SMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000 +} SMC_ECC_PAGE_SIZE_BYTE_T; + +/** + * @brief SMC_Access_Mode + */ +typedef enum +{ + SMC_ACCESS_MODE_A = 0x00000000, + SMC_ACCESS_MODE_B = 0x10000000, + SMC_ACCESS_MODE_C = 0x20000000, + SMC_ACCESS_MODE_D = 0x30000000 +} SMC_ACCESS_MODE_T; + +/** + * @brief SMC_Interrupt_sources + */ +typedef enum +{ + SMC_INT_EDGE_RISING = 0x00000008, + SMC_INT_LEVEL_HIGH = 0x00000010, + SMC_INT_EDGE_FALLING = 0x00000020 +} SMC_INT_T; + +/** + * @brief SMC_Flags + */ +typedef enum +{ + SMC_FLAG_EDGE_RISING = 0x00000001, + SMC_FLAG_LEVEL_HIGH = 0x00000002, + SMC_FLAG_EDGE_FALLING = 0x00000004, + SMC_FLAG_FIFO_EMPTY = 0x00000040 +} SMC_FLAG_T; + +/**@} end of group SMC_Enumerations */ + +/** @defgroup SMC_Structures Structures + @{ +*/ + +/** + * @brief Timing parameters for NOR/SRAM Banks + */ +typedef struct +{ + uint32_t addressSetupTime; + uint32_t addressHodeTime; + uint32_t dataSetupTime; + uint32_t busTurnaroundTime; + uint32_t clockDivision; + uint32_t dataLatency; + SMC_ACCESS_MODE_T accessMode; +} SMC_NORSRAMTimingConfig_T; + +/** + * @brief SMC NOR/SRAM Configure structure + */ +typedef struct +{ + SMC_BANK1_NORSRAM_T bank; + SMC_DATA_ADDRESS_MUX_T dataAddressMux; + SMC_MEMORY_TYPE_T memoryType; + SMC_MEMORY_DATA_WIDTH_T memoryDataWidth; + SMC_BURST_ACCESS_MODE_T burstAcceesMode; + SMC_ASYNCHRONOUS_WAIT_T asynchronousWait; + SMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity; + SMC_WRAP_MODE_T wrapMode; + SMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive; + SMC_WRITE_OPERATION_T writeOperation; + SMC_WAITE_SIGNAL_T waiteSignal; + SMC_EXTENDEN_MODE_T extendedMode; + SMC_WRITE_BURST_T writeBurst; + SMC_NORSRAMTimingConfig_T* readWriteTimingStruct; + SMC_NORSRAMTimingConfig_T* writeTimingStruct; +} SMC_NORSRAMConfig_T; + +/** + * @brief Timing parameters for NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t setupTime; + uint32_t waitSetupTime; + uint32_t holdSetupTime; + uint32_t HiZSetupTime; +} SMC_NAND_PCCARDTimingConfig_T; + +/** + * @brief SMC NAND Configure structure + */ +typedef struct +{ + SMC_BANK_NAND_T bank; + SMC_WAIT_FEATURE_T waitFeature; + SMC_MEMORY_DATA_WIDTH_T memoryDataWidth; + SMC_ECC_T ECC; + SMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize; + uint32_t TCLRSetupTime; + uint32_t TARSetupTime; + SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; + SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; +} SMC_NANDConfig_T; + +/** + * @brief SMC PCCARD Configure structure + */ +typedef struct +{ + SMC_WAIT_FEATURE_T waitFeature; + uint32_t TCLRSetupTime; + uint32_t TARSetupTime; + SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; + SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; + SMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct; +} SMC_PCCARDConfig_T; + +/**@} end of group SMC_Structures */ + +/** @defgroup SMC_Functions Functions + @{ +*/ + +/* SMC reset */ +void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank); +void SMC_ResetNAND(SMC_BANK_NAND_T bank); +void SMC_ResetPCCard(void); + +/* SMC Configuration */ +void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig); +void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig); +void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig); +void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig); +void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig); +void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig); + +/* SMC bank control */ +void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank); +void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank); +void SMC_EnableNAND(SMC_BANK_NAND_T bank); +void SMC_DisableNAND(SMC_BANK_NAND_T bank); +void SMC_EnablePCCARD(void); +void SMC_DisablePCCARD(void); +void SMC_EnableNANDECC(SMC_BANK_NAND_T bank); +void SMC_DisableNANDECC(SMC_BANK_NAND_T bank); +uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank); + +/* Interrupt and flag */ +void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt); +void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt); +uint8_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag); +void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag); +uint8_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag); +void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag); + +/**@} end of group SMC_Functions */ +/**@} end of group SMC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h index 6e6d8e3338..c7609be840 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the SPI firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_SPI_H #define __APM32F10X_SPI_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,7 +42,7 @@ @{ */ -/** @addtogroup SPI_Enumerations Enumerations +/** @defgroup SPI_Enumerations Enumerations @{ */ @@ -53,7 +55,7 @@ typedef enum SPI_DIRECTION_2LINES_RXONLY = 0x0400, SPI_DIRECTION_1LINE_RX = 0x8000, SPI_DIRECTION_1LINE_TX = 0xC000 -}SPI_DIRECTION_T; +} SPI_DIRECTION_T; /** * @brief SPI mode @@ -62,7 +64,7 @@ typedef enum { SPI_MODE_MASTER = 0x0104, SPI_MODE_SLAVE = 0x0000 -}SPI_MODE_T; +} SPI_MODE_T; /** * @brief SPI Data length @@ -71,7 +73,7 @@ typedef enum { SPI_DATA_LENGTH_16B = 0x0800, SPI_DATA_LENGTH_8B = 0x0000 -}SPI_DATA_LENGTH_T; +} SPI_DATA_LENGTH_T; /** * @brief SPI Clock Polarity @@ -80,7 +82,7 @@ typedef enum { SPI_CLKPOL_LOW = 0x0000, SPI_CLKPOL_HIGH = 0x0002 -}SPI_CLKPOL_T; +} SPI_CLKPOL_T; /** * @brief SPI Clock Phase @@ -89,7 +91,7 @@ typedef enum { SPI_CLKPHA_1EDGE = 0x0000, SPI_CLKPHA_2EDGE = 0x0001 -}SPI_CLKPHA_T; +} SPI_CLKPHA_T; /** * @brief SPI Slave Select management @@ -98,7 +100,7 @@ typedef enum { SPI_NSS_SOFT = 0x0200, SPI_NSS_HARD = 0x0000 -}SPI_NSS_T; +} SPI_NSS_T; /** * @brief SPI BaudRate Prescaler @@ -113,7 +115,7 @@ typedef enum SPI_BAUDRATE_DIV_64 = 0x0028, SPI_BAUDRATE_DIV_128 = 0x0030, SPI_BAUDRATE_DIV_256 = 0x0038, -}SPI_BAUDRATE_DIV_T; +} SPI_BAUDRATE_DIV_T; /** * @brief SPI MSB LSB transmission @@ -122,7 +124,7 @@ typedef enum { SPI_FIRSTBIT_MSB = 0x0000, SPI_FIRSTBIT_LSB = 0x0080 -}SPI_FIRSTBIT_T; +} SPI_FIRSTBIT_T; /** * @brief I2S Mode @@ -133,7 +135,7 @@ typedef enum I2S_MODE_SLAVE_RX = 0x0100, I2S_MODE_MASTER_TX = 0x0200, I2S_MODE_MASTER_RX = 0x0300 -}I2S_MODE_T; +} I2S_MODE_T; /** * @brief I2S Standard @@ -145,7 +147,7 @@ typedef enum I2S_STANDARD_LSB = 0x0020, I2S_STANDARD_PCMSHORT = 0x0030, I2S_STANDARD_PCMLONG = 0x00B0 -}I2S_STANDARD_T; +} I2S_STANDARD_T; /** * @brief I2S data length @@ -165,7 +167,7 @@ typedef enum { I2S_MCLK_OUTPUT_DISABLE = 0x0000, I2S_MCLK_OUTPUT_ENABLE = 0x0200, -}I2S_MCLK_OUTPUT_T; +} I2S_MCLK_OUTPUT_T; /** * @brief I2S Audio divider @@ -182,7 +184,7 @@ typedef enum I2S_AUDIO_DIV_11K = 11025, I2S_AUDIO_DIV_8K = 8000, I2S_AUDIO_DIV_DEFAULT = 2 -}I2S_AUDIO_DIV_T; +} I2S_AUDIO_DIV_T; /** * @brief I2S Clock Polarity @@ -191,7 +193,7 @@ typedef enum { I2S_CLKPOL_LOW = 0x0000, I2S_CLKPOL_HIGH = 0x0008 -}I2S_CLKPOL_T; +} I2S_CLKPOL_T; /** * @brief SPI Direction select @@ -200,7 +202,7 @@ typedef enum { SPI_DIRECTION_RX = 0xBFFF, SPI_DIRECTION_TX = 0x4000 -}SPI_DIRECTION_SELECT_T; +} SPI_DIRECTION_SELECT_T; /** * @brief SPI interrupts definition @@ -214,7 +216,7 @@ typedef enum SPI_INT_CRCE = 0x2010, SPI_INT_ME = 0x2020, I2S_INT_UDR = 0x2008 -}SPI_I2S_INT_T; +} SPI_I2S_INT_T; /** * @brief SPI flags definition @@ -229,7 +231,7 @@ typedef enum SPI_FLAG_ME = 0x0020, SPI_FLAG_OVR = 0x0040, SPI_FLAG_BSY = 0x0080 -}SPI_FLAG_T; +} SPI_FLAG_T; /** * @brief SPI I2S DMA requests @@ -238,12 +240,12 @@ typedef enum { SPI_I2S_DMA_REQ_TX = 0x0002, SPI_I2S_DMA_REQ_RX = 0x0001 -}SPI_I2S_DMA_REQ_T; +} SPI_I2S_DMA_REQ_T; /**@} end of group SPI_Enumerations*/ -/** @addtogroup SPI_Structure Data Structure +/** @addtogroup SPI_Structures Structures @{ */ @@ -261,7 +263,7 @@ typedef struct SPI_DIRECTION_T direction; SPI_BAUDRATE_DIV_T baudrateDiv; uint16_t crcPolynomial; -}SPI_Config_T; +} SPI_Config_T; /** * @brief I2S Config structure definition @@ -274,15 +276,15 @@ typedef struct I2S_MCLK_OUTPUT_T MCLKOutput; I2S_AUDIO_DIV_T audioDiv; I2S_CLKPOL_T polarity; -}I2S_Config_T; +} I2S_Config_T; -/**@} end of group SPI_Structure*/ +/**@} end of group SPI_Structures */ -/** @addtogroup SPI_Fuctions Fuctions +/** @defgroup SPI_Functions Functions @{ */ -/** Reset and Configuration */ +/* Reset and Configuration */ void SPI_I2S_Reset(SPI_T* spi); void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig); void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig); @@ -301,11 +303,11 @@ void SPI_EnableSSOutput(SPI_T* spi); void SPI_DisableSSOutput(SPI_T* spi); void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length); -/** DMA */ +/* DMA */ void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); -/** CRC */ +/* CRC */ void SPI_TxCRC(SPI_T* spi); void SPI_EnableCRC(SPI_T* spi); void SPI_DisableCRC(SPI_T* spi); @@ -314,7 +316,7 @@ uint16_t SPI_ReadRxCRC(SPI_T* spi); uint16_t SPI_ReadCRCPolynomial(SPI_T* spi); void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction); -/** Interrupts and flag */ +/* Interrupts and flag */ void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag); @@ -322,9 +324,9 @@ void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag); uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); -/**@} end of group SPI_Fuctions*/ -/**@} end of group SPI_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group SPI_Functions */ +/**@} end of group SPI_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h index 62069152fe..9a71cc1016 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the TMR firmware library. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,31 +15,33 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_TMR_H #define __APM32F10X_TMR_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup TMR_Driver TMR Driver +/** @addtogroup TMR_Driver TMR Driver @{ */ -/** @addtogroup TMR_Enumerations Enumerations +/** @defgroup TMR_Enumerations Enumerations @{ */ @@ -480,26 +482,26 @@ typedef enum TMR_FLAG_CC4RC = 0x1000 } TMR_FLAG_T; -/**@} end of group TMR_Enumerations*/ +/**@} end of group TMR_Enumerations */ -/** @addtogroup TMR_Structure Data Structure +/** @defgroup TMR_Structures Structures @{ */ /** - * @brief TMR Config struct definition + * @brief TMR Base Configure structure definition */ typedef struct { TMR_COUNTER_MODE_T countMode; TMR_CLOCK_DIV_T clockDivision; - uint16_t period; //!< This must between 0x0000 and 0xFFFF - uint16_t division; //!< This must between 0x0000 and 0xFFFF - uint8_t repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. + uint16_t period; /*!< This must between 0x0000 and 0xFFFF */ + uint16_t division; /*!< This must between 0x0000 and 0xFFFF */ + uint8_t repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */ } TMR_BaseConfig_T; ; /** - * @brief TMR Config struct definition + * @brief TMR Output Compare Configure structure definition */ typedef struct { @@ -510,7 +512,7 @@ typedef struct TMR_OC_NPOLARITY_T nPolarity; TMR_OC_IDLE_STATE_T idleState; TMR_OC_NIDLE_STATE_T nIdleState; - uint16_t pulse; //!< This must between 0x0000 and 0xFFFF + uint16_t pulse; /*!< This must between 0x0000 and 0xFFFF */ } TMR_OCConfig_T; /** @@ -528,7 +530,7 @@ typedef struct } TMR_BDTConfig_T; /** - * @brief TMR Input Capture Config struct definition + * @brief TMR Input Capture Configure structure definition */ typedef struct { @@ -536,48 +538,48 @@ typedef struct TMR_IC_POLARITY_T polarity; TMR_IC_SELECTION_T selection; TMR_IC_PSC_T prescaler; - uint16_t filter; //!< This must between 0x00 and 0x0F + uint16_t filter; /*!< This must between 0x00 and 0x0F */ } TMR_ICConfig_T; -/**@} end of group TMR_Structure*/ +/**@} end of group TMR_Structures */ -/** @addtogroup TMR_Fuctions Fuctions +/** @defgroup TMR_Functions Functions @{ */ -/** Reset and Configuration */ +/* Reset and Configuration */ void TMR_Reset(TMR_T* tmr); -void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig); -void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OCConfig); -void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OCConfig); -void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OCConfig); -void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OCConfig); -void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig); -void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig); -void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig); -void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig); -void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig); -void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig); +void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig); +void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig); +void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig); +void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig); +void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig); +void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig); +void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig); +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig); +void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig); +void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig); +void TMR_ConfigBDTStructInit(TMR_BDTConfig_T* BDTConfig); void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode); void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision); void TMR_Enable(TMR_T* tmr); void TMR_Disable(TMR_T* tmr); -/** PWM Configuration */ -void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig); +/* PWM Configuration */ +void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig); void TMR_EnablePWMOutputs(TMR_T* tmr); void TMR_DisablePWMOutputs(TMR_T* tmr); -/** DMA */ +/* DMA */ void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength); void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource); void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource); -/** Configuration */ +/* Configuration */ void TMR_ConfigInternalClock(TMR_T* tmr); void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource); void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, - TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter); void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, @@ -589,10 +591,10 @@ void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode); void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce); void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, TMR_IC_POLARITY_T IC2Polarity); -void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); -void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); void TMR_EnableAutoReload(TMR_T* tmr); void TMR_DisableAutoReload(TMR_T* tmr); void TMR_EnableSelectCOM(TMR_T* tmr); @@ -620,16 +622,17 @@ void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); -void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); -void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel); +void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel); +void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel); +void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel); void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode); void TMR_EnableUpdate(TMR_T* tmr); void TMR_DisableUpdate(TMR_T* tmr); void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource); void TMR_EnableHallSensor(TMR_T* tmr); void TMR_DisableHallSensor(TMR_T* tmr); + void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource); void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode); void TMR_EnableMasterSlaveMode(TMR_T* tmr); @@ -644,6 +647,7 @@ void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); + uint16_t TMR_ReadCaputer1(TMR_T* tmr); uint16_t TMR_ReadCaputer2(TMR_T* tmr); uint16_t TMR_ReadCaputer3(TMR_T* tmr); @@ -651,20 +655,20 @@ uint16_t TMR_ReadCaputer4(TMR_T* tmr); uint16_t TMR_ReadCounter(TMR_T* tmr); uint16_t TMR_ReadPrescaler(TMR_T* tmr); -/** Interrupts and Event */ +/* Interrupts and Event */ void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt); void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt); -void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources); +void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources); -/** flags */ +/* flags */ uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag); void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag); uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag); void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag); -/**@} end of group TMR_Fuctions*/ -/**@} end of group TMR_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group TMR_Functions */ +/**@} end of group TMR_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h index d18418d839..7d4434320c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the USART firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,16 +23,18 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_USART_H #define __APM32F10X_USART_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -40,12 +42,12 @@ @{ */ -/** @addtogroup USART_Enumerations Enumerations +/** @defgroup USART_Enumerations Enumerations @{ */ /** - * @brief USART Word Length define + * @brief USART Word Length definition */ typedef enum { @@ -54,7 +56,7 @@ typedef enum } USART_WORD_LEN_T; /** - * @brief USART Stop bits define + * @brief USART Stop bits definition */ typedef enum { @@ -65,7 +67,7 @@ typedef enum } USART_STOP_BIT_T; /** - * @brief USART Parity define + * @brief USART Parity definition */ typedef enum { @@ -75,7 +77,7 @@ typedef enum } USART_PARITY_T; /** - * @brief USART mode define + * @brief USART mode definition */ typedef enum { @@ -85,7 +87,7 @@ typedef enum } USART_MODE_T; /** - * @brief USART hardware flow control define + * @brief USART hardware flow control definition */ typedef enum { @@ -105,7 +107,7 @@ typedef enum } USART_CLKEN_T; /** - * @brief USART Clock polarity define + * @brief USART Clock polarity definition */ typedef enum { @@ -114,7 +116,7 @@ typedef enum } USART_CLKPOL_T; /** - * @brief USART Clock phase define + * @brief USART Clock phase definition */ typedef enum { @@ -123,7 +125,7 @@ typedef enum } USART_CLKPHA_T; /** - * @brief USART Last bit clock pulse enable + * @brief USART Last bit clock pulse definition */ typedef enum { @@ -187,7 +189,7 @@ typedef enum } USART_IRDALP_T; /** - * @brief USART flag define + * @brief USART flag definition */ typedef enum { @@ -203,43 +205,43 @@ typedef enum USART_FLAG_PE = 0x0001 } USART_FLAG_T; -/**@} end of group USART_Enumerations*/ +/**@} end of group USART_Enumerations */ -/** @addtogroup USART_Structure Data Structure +/** @defgroup USART_Structures Structures @{ */ /** - * @brief USART Config struct definition + * @brief USART Configure structure definition */ typedef struct { - uint32_t baudRate; //!< Specifies the baud rate - USART_WORD_LEN_T wordLength; //!< Specifies the word length - USART_STOP_BIT_T stopBits; //!< Specifies the stop bits - USART_PARITY_T parity; //!< Specifies the parity - USART_MODE_T mode; //!< Specifies the mode - USART_HARDWARE_FLOW_T hardwareFlow; //!< Specifies the hardware flow control + uint32_t baudRate; /*!< Specifies the baud rate */ + USART_WORD_LEN_T wordLength; /*!< Specifies the word length */ + USART_STOP_BIT_T stopBits; /*!< Specifies the stop bits */ + USART_PARITY_T parity; /*!< Specifies the parity */ + USART_MODE_T mode; /*!< Specifies the mode */ + USART_HARDWARE_FLOW_T hardwareFlow; /*!< Specifies the hardware flow control */ } USART_Config_T; /** - * @brief USART synchronous communication clock config struct definition + * @brief USART synchronous communication clock configure structure definition */ typedef struct { - USART_CLKEN_T clock; //!< Enable or Disable Clock - USART_CLKPOL_T polarity; //!< Specifies the clock polarity - USART_CLKPHA_T phase; //!< Specifies the clock phase - USART_LBCP_T lastBit; //!< Enable or Disable last bit clock + USART_CLKEN_T clock; /*!< Enable or Disable Clock */ + USART_CLKPOL_T polarity; /*!< Specifies the clock polarity */ + USART_CLKPHA_T phase; /*!< Specifies the clock phase */ + USART_LBCP_T lastBit; /*!< Enable or Disable last bit clock */ } USART_ClockConfig_T; -/**@} end of group USART_Structure*/ +/**@} end of group USART_Structures */ -/** @addtogroup USART_Fuctions Fuctions +/** @defgroup USART_Functions Functions @{ */ -/** USART Reset and Configuration */ +/* USART Reset and Configuration */ void USART_Reset(USART_T* usart); void USART_Config(USART_T* uart, USART_Config_T* usartConfig); void USART_ConfigStructInit(USART_Config_T* usartConfig); @@ -247,25 +249,25 @@ void USART_Address(USART_T* usart, uint8_t address); void USART_Enable(USART_T* usart); void USART_Disable(USART_T* usart); -/** Clock communication */ +/* Clock communication */ void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig); void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig); -/** DMA mode */ +/* DMA mode */ void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq); void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq); -/** Mute mode */ +/* Mute mode */ void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup); void USART_EnableMuteMode(USART_T* usart); void USART_DisableMuteMode(USART_T* usart); -/** LIN mode */ +/* LIN mode */ void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length); void USART_EnableLIN(USART_T* usart); void USART_DisableLIN(USART_T* usart); -/** Transmit and receive */ +/* Transmit and receive */ void USART_EnableTx(USART_T* usart); void USART_DisableTx(USART_T* usart); void USART_EnableRx(USART_T* usart); @@ -274,7 +276,7 @@ void USART_TxData(USART_T* usart, uint16_t data); uint16_t USART_RxData(USART_T* usart); void USART_TxBreak(USART_T* usart); -/** Smartcard mode */ +/* Smartcard mode */ void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime); void USART_ConfigPrescaler(USART_T* usart, uint8_t div); void USART_EnableSmartCard(USART_T* usart); @@ -282,16 +284,16 @@ void USART_DisableSmartCard(USART_T* usart); void USART_EnableSmartCardNACK(USART_T* usart); void USART_DisableSmartCardNACK(USART_T* usart); -/** Half-duplex mode */ +/* Half-duplex mode */ void USART_EnableHalfDuplex(USART_T* usart); void USART_DisableHalfDuplex(USART_T* usart); -/** IrDA mode */ +/* IrDA mode */ void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode); void USART_EnableIrDA(USART_T* usart); void USART_DisableIrDA(USART_T* usart); -/** Interrupt and flag */ +/* Interrupt and flag */ void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt); void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt); uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag); @@ -299,9 +301,9 @@ void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag); uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag); void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag); -/**@} end of group USART_Fuctions*/ -/**@} end of group USART_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group USART_Functions */ +/**@} end of group USART_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h index 1acc761036..b30c098738 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h @@ -3,9 +3,9 @@ * * @brief This file contains all the functions prototypes for the WWDT firmware library * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,29 +23,31 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_WWDT_H #define __APM32F10X_WWDT_H -#ifdef __cplusplus - extern "C" { -#endif - +/* Includes */ #include "apm32f10x.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup WWDT_Driver WWDT Driver +/** @addtogroup WWDT_Driver WWDT Driver @{ */ -/** @addtogroup WWDT_Enumerations Enumerations +/** @defgroup WWDT_Enumerations Enumerations @{ */ /** - * @brief WWDT Timebase(Prescaler) define + * @brief WWDT Timebase(Prescaler) definition */ typedef enum { @@ -53,37 +55,37 @@ typedef enum WWDT_TIME_BASE_2 = 0x00000080, WWDT_TIME_BASE_4 = 0x00000100, WWDT_TIME_BASE_8 = 0x00000180 -}WWDT_TIME_BASE_T; +} WWDT_TIME_BASE_T; -/**@} end of group WWDT_Enumerations*/ +/**@} end of group WWDT_Enumerations */ -/** @addtogroup WWDT_Fuctions Fuctions +/** @defgroup WWDT_Functions Functions @{ */ -/** WWDT reset */ +/* WWDT reset */ void WWDT_Reset(void); -/** Config WWDT Timebase */ +/* Configure WWDT Timebase */ void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase); -/** Config Window Data */ +/* Configure Window Data */ void WWDT_ConfigWindowData(uint8_t windowData); -/** Config Couter */ +/* Configure Couter */ void WWDT_ConfigCounter(uint8_t counter); -/** Enable WWDT and Early Wakeup interrupt */ +/* Enable WWDT and Early Wakeup interrupt */ void WWDT_EnableEWI(void); void WWDT_Enable(uint8_t count); -/** Read Flag and Clear Flag */ +/* Read Flag and Clear Flag */ uint8_t WWDT_ReadFlag(void); void WWDT_ClearFlag(void); -/**@} end of group WWDT_Fuctions*/ -/**@} end of group WWDT_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group WWDT_Functions */ +/**@} end of group WWDT_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ #ifdef __cplusplus } diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c index 0f7ef97b8b..36d591de55 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c @@ -3,9 +3,9 @@ * * @brief This file provides all the ADC firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #include "apm32f10x_adc.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup ADC_Driver ADC Driver + * @brief ADC driver modules @{ */ -/** @addtogroup ADC_Fuctions Fuctions +/** @defgroup ADC_Functions Functions @{ */ @@ -47,7 +48,7 @@ * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Reset(ADC_T *adc) +void ADC_Reset(ADC_T* adc) { if (adc == ADC1) { @@ -77,7 +78,7 @@ void ADC_Reset(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig) +void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig) { uint32_t reg; @@ -107,7 +108,7 @@ void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig) * * @retval None */ -void ADC_ConfigStructInit(ADC_Config_T *adcConfig) +void ADC_ConfigStructInit(ADC_Config_T* adcConfig) { adcConfig->mode = ADC_MODE_INDEPENDENT; adcConfig->scanConvMode = DISABLE; @@ -126,7 +127,7 @@ void ADC_ConfigStructInit(ADC_Config_T *adcConfig) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Enable(ADC_T *adc) +void ADC_Enable(ADC_T* adc) { adc->CTRL2_B.ADCEN = BIT_SET; } @@ -140,7 +141,7 @@ void ADC_Enable(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_Disable(ADC_T *adc) +void ADC_Disable(ADC_T* adc) { adc->CTRL2_B.ADCEN = BIT_RESET; } @@ -154,7 +155,7 @@ void ADC_Disable(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableDMA(ADC_T *adc) +void ADC_EnableDMA(ADC_T* adc) { adc->CTRL2_B.DMAEN = BIT_SET; } @@ -168,7 +169,7 @@ void ADC_EnableDMA(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableDMA(ADC_T *adc) +void ADC_DisableDMA(ADC_T* adc) { adc->CTRL2_B.DMAEN = BIT_RESET; } @@ -182,7 +183,7 @@ void ADC_DisableDMA(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ResetCalibration(ADC_T *adc) +void ADC_ResetCalibration(ADC_T* adc) { adc->CTRL2_B.CALRST = BIT_SET; } @@ -196,7 +197,7 @@ void ADC_ResetCalibration(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc) +uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc) { uint8_t ret; ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET; @@ -212,7 +213,7 @@ uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_StartCalibration(ADC_T *adc) +void ADC_StartCalibration(ADC_T* adc) { adc->CTRL2_B.CAL = BIT_SET; } @@ -226,7 +227,7 @@ void ADC_StartCalibration(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc) +uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc) { uint8_t ret; ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET; @@ -242,7 +243,7 @@ uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableSoftwareStartConv(ADC_T *adc) +void ADC_EnableSoftwareStartConv(ADC_T* adc) { adc->CTRL2 |= 0x00500000; } @@ -256,7 +257,7 @@ void ADC_EnableSoftwareStartConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableSoftwareStartConv(ADC_T *adc) +void ADC_DisableSoftwareStartConv(ADC_T* adc) { adc->CTRL2 &= 0xFFAFFFFF; } @@ -270,7 +271,7 @@ void ADC_DisableSoftwareStartConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc) +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc) { uint8_t ret; ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET; @@ -289,7 +290,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number) +void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number) { adc->CTRL1_B.DISCNUMCFG |= number - 1; } @@ -303,7 +304,7 @@ void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableDiscMode(ADC_T *adc) +void ADC_EnableDiscMode(ADC_T* adc) { adc->CTRL1_B.REGDISCEN = BIT_SET; } @@ -317,7 +318,7 @@ void ADC_EnableDiscMode(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableDiscMode(ADC_T *adc) +void ADC_DisableDiscMode(ADC_T* adc) { adc->CTRL1_B.REGDISCEN = BIT_RESET; } @@ -366,7 +367,7 @@ void ADC_DisableDiscMode(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) +void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) { uint32_t temp1 = 0; uint32_t temp2 = 0; @@ -427,7 +428,7 @@ void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableExternalTrigConv(ADC_T *adc) +void ADC_EnableExternalTrigConv(ADC_T* adc) { adc->CTRL2_B.REGEXTTRGEN = BIT_SET; } @@ -441,7 +442,7 @@ void ADC_EnableExternalTrigConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableExternalTrigConv(ADC_T *adc) +void ADC_DisableExternalTrigConv(ADC_T* adc) { adc->CTRL2_B.REGEXTTRGEN = BIT_RESET; } @@ -455,7 +456,7 @@ void ADC_DisableExternalTrigConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint16_t ADC_ReadConversionValue(ADC_T *adc) +uint16_t ADC_ReadConversionValue(ADC_T* adc) { return (uint16_t) adc->REGDATA; } @@ -469,9 +470,9 @@ uint16_t ADC_ReadConversionValue(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc) +uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc) { - return (*(__IOM uint32_t *) RDG_ADDRESS); + return (*(__IOM uint32_t*) RDG_ADDRESS); } /*! @@ -483,7 +484,7 @@ uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableAutoInjectedConv(ADC_T *adc) +void ADC_EnableAutoInjectedConv(ADC_T* adc) { adc->CTRL1_B.INJGACEN = BIT_SET; } @@ -497,7 +498,7 @@ void ADC_EnableAutoInjectedConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableAutoInjectedConv(ADC_T *adc) +void ADC_DisableAutoInjectedConv(ADC_T* adc) { adc->CTRL1_B.INJGACEN = BIT_RESET; } @@ -511,7 +512,7 @@ void ADC_DisableAutoInjectedConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableInjectedDiscMode(ADC_T *adc) +void ADC_EnableInjectedDiscMode(ADC_T* adc) { adc->CTRL1_B.INJDISCEN = BIT_SET; } @@ -525,7 +526,7 @@ void ADC_EnableInjectedDiscMode(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableInjectedDiscMode(ADC_T *adc) +void ADC_DisableInjectedDiscMode(ADC_T* adc) { adc->CTRL1_B.INJDISCEN = BIT_RESET; } @@ -558,7 +559,7 @@ void ADC_DisableInjectedDiscMode(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv) +void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv) { adc->CTRL2_B.INJGEXTTRGSEL = RESET; adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv; @@ -573,7 +574,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T ex * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableExternalTrigInjectedConv(ADC_T *adc) +void ADC_EnableExternalTrigInjectedConv(ADC_T* adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_SET; } @@ -587,7 +588,7 @@ void ADC_EnableExternalTrigInjectedConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableExternalTrigInjectedConv(ADC_T *adc) +void ADC_DisableExternalTrigInjectedConv(ADC_T* adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; } @@ -601,7 +602,7 @@ void ADC_DisableExternalTrigInjectedConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc) +void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_SET; adc->CTRL2_B.INJSWSC = BIT_SET; @@ -616,7 +617,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc) +void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc) { adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; adc->CTRL2_B.INJSWSC = BIT_RESET; @@ -631,7 +632,7 @@ void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc) +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc) { uint8_t ret; ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET; @@ -682,7 +683,7 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) +void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) { uint32_t temp1 = 0; uint32_t temp2 = 0; @@ -726,7 +727,7 @@ void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_ * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length) +void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length) { adc->INJSEQ_B.INJSEQLEN = RESET; adc->INJSEQ_B.INJSEQLEN |= length - 1; @@ -751,14 +752,14 @@ void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet) +void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet) { __IOM uint32_t tmp = 0; tmp = (uint32_t)adc; tmp += channel; - *(__IOM uint32_t *) tmp = (uint32_t)offSet; + *(__IOM uint32_t*) tmp = (uint32_t)offSet; } /*! @@ -777,14 +778,14 @@ void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t * * @note adc can be ADC1, ADC2 or ADC3. */ -uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel) +uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel) { __IOM uint32_t temp = 0; temp = (uint32_t)adc; temp += channel + INJDATA_OFFSET; - return (uint16_t)(*(__IOM uint32_t *) temp); + return (uint16_t)(*(__IOM uint32_t*) temp); } /*! @@ -806,7 +807,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog) +void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog) { adc->CTRL1 &= 0xFF3FFDFF; adc->CTRL1 |= analogWatchdog; @@ -821,7 +822,7 @@ void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableAnalogWatchdog(ADC_T *adc) +void ADC_DisableAnalogWatchdog(ADC_T* adc) { adc->CTRL1 &= 0xFF3FFDFF; } @@ -841,7 +842,7 @@ void ADC_DisableAnalogWatchdog(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold) +void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold) { adc->AWDHT = highThreshold; adc->AWDLT = lowThreshold; @@ -877,7 +878,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel) +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel) { adc->CTRL1_B.AWDCHSEL = BIT_RESET; adc->CTRL1 |= channel; @@ -892,7 +893,7 @@ void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableTempSensorVrefint(ADC_T *adc) +void ADC_EnableTempSensorVrefint(ADC_T* adc) { adc->CTRL2_B.TSVREFEN = BIT_SET; } @@ -906,7 +907,7 @@ void ADC_EnableTempSensorVrefint(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableTempSensorVrefint(ADC_T *adc) +void ADC_DisableTempSensorVrefint(ADC_T* adc) { adc->CTRL2_B.TSVREFEN = BIT_RESET; } @@ -926,7 +927,7 @@ void ADC_DisableTempSensorVrefint(ADC_T *adc) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt) +void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt) { uint8_t mask; @@ -949,7 +950,7 @@ void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt) +void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt) { uint8_t mask; @@ -974,7 +975,7 @@ void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag) +uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag) { return (adc->STS & flag) ? SET : RESET; } @@ -996,7 +997,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag) +void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag) { adc->STS = ~(uint32_t)flag; } @@ -1016,7 +1017,7 @@ void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag) * * @note adc can be ADC1, ADC2 or ADC3. */ -uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag) +uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag) { uint8_t bitStatus = RESET; uint32_t itmask = 0; @@ -1051,7 +1052,7 @@ uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag) * * @note adc can be ADC1, ADC2 or ADC3. */ -void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag) +void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag) { uint8_t mask = 0; @@ -1059,6 +1060,6 @@ void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag) adc->STS = ~(uint32_t)mask; } -/**@} end of group ADC_Fuctions*/ -/**@} end of group ADC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group ADC_Functions */ +/**@} end of group ADC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c index d5c19a0e08..627eb37525 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c @@ -3,9 +3,9 @@ * * @brief This file provides all the BAKPR firmware functions. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #include "apm32f10x_bakpr.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup BAKPR_Driver ADC Driver +/** @addtogroup BAKPR_Driver BAKPR Driver + * @brief BAKPR driver modules @{ */ -/** @addtogroup BAKPR_Fuctions Fuctions +/** @defgroup BAKPR_Functions Functions @{ */ @@ -177,7 +178,7 @@ void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data) tmp = (uint32_t)BAKPR_BASE; tmp += bakrData; - *(__IOM uint32_t *) tmp = data; + *(__IOM uint32_t*) tmp = data; } /*! @@ -195,7 +196,7 @@ uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData) tmp = (uint32_t)BAKPR_BASE; tmp += bakrData; - return (*(__IOM uint32_t *) tmp); + return (*(__IOM uint32_t*) tmp); } /*! @@ -246,6 +247,6 @@ void BAKPR_ClearIntFlag(void) BAKPR->CSTS_B.TICLR = BIT_SET; } -/**@} end of group BAKPR_Fuctions*/ +/**@} end of group BAKPR_Functions*/ /**@} end of group BAKPR_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c index ed0ef63b81..2573ef328f 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c @@ -3,9 +3,9 @@ * * @brief This file provides all the CAN firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #include "apm32f10x_can.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup CAN_Driver CAN Driver + * @brief CAN driver modules @{ */ -/** @addtogroup CAN_Fuctions Fuctions +/** @defgroup CAN_Functions Functions @{ */ @@ -47,7 +48,7 @@ * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_Reset(CAN_T *can) +void CAN_Reset(CAN_T* can) { if (can == CAN1) { @@ -72,22 +73,22 @@ void CAN_Reset(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig) +uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) { uint8_t initStatus = ERROR; uint32_t wait_ack = 0x00000000; - /** Exit from sleep mode */ + /* Exit from sleep mode */ can->MCTRL_B.SLEEPREQ = BIT_RESET; - /** Request initialisation */ + /* Request initialisation */ can->MCTRL_B.INITREQ = BIT_SET; - /** Wait the acknowledge */ + /* Wait the acknowledge */ while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF)) { wait_ack++; } - /** Check acknowledge */ + /* Check acknowledge */ if (((can->MSTS_B.INITFLG) != BIT_SET)) { initStatus = ERROR; @@ -139,7 +140,7 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig) can->MCTRL_B.TXFPCFG = BIT_RESET; } - /** Set the bit timing register */ + /* Set the bit timing register */ can->BITTIM &= (uint32_t)0x3fffffff; can->BITTIM |= (uint32_t)canConfig->mode << 30; can->BITTIM_B.RSYNJW = canConfig->syncJumpWidth; @@ -147,16 +148,16 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig) can->BITTIM_B.TIMSEG2 = canConfig->timeSegment2; can->BITTIM_B.BRPSC = canConfig->prescaler - 1; - /** Request leave initialisation */ + /* Request leave initialisation */ can->MCTRL_B.INITREQ = BIT_RESET; wait_ack = 0; - /** Wait the acknowledge */ + /* Wait the acknowledge */ while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF)) { wait_ack++; } - /** Check acknowledge */ + /* Check acknowledge */ if (((can->MSTS_B.INITFLG) != BIT_RESET)) { initStatus = ERROR; @@ -169,6 +170,92 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig) return initStatus; } +#if defined(APM32F10X_CL) +/*! + * @brief Congig the CAN peripheral according to the specified parameters in the filterConfig. + * + * @param filterConfig :Point to a CAN_FilterConfig_T structure. + * + * @retval None + * + * @note This function is for CAN1 and CAN2. + */ +void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig) +{ + CAN1->FCTRL_B.FINITEN = BIT_SET; + + CAN1->FACT &= ~(1 << filterConfig->filterNumber); + + /* Filter Scale */ + if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) + { + /* 16-bit scale for the filter */ + CAN1->FSCFG &= ~(1 << filterConfig->filterNumber); + + CAN1->sFilterRegister[filterConfig->filterNumber].FBANK1 = + ((0x0000FFFF & filterConfig->filterMaskIdLow) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + CAN1->sFilterRegister[filterConfig->filterNumber].FBANK2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdHigh); + } + + if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT) + { + CAN1->FSCFG |= (1 << filterConfig->filterNumber); + + CAN1->sFilterRegister[filterConfig->filterNumber].FBANK1 = + ((0x0000FFFF & filterConfig->filterIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + CAN1->sFilterRegister[filterConfig->filterNumber].FBANK2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterMaskIdLow); + } + + /* Filter Mode */ + if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) + { + CAN1->FMCFG &= ~(1 << filterConfig->filterNumber); + } + else + { + CAN1->FMCFG |= (1 << filterConfig->filterNumber); + } + + /* Filter FIFO assignment */ + if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0) + { + CAN1->FFASS &= ~(1 << filterConfig->filterNumber); + } + if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1) + { + CAN1->FFASS |= (1 << filterConfig->filterNumber); + } + + /* Filter activation */ + if (filterConfig->filterActivation == ENABLE) + { + CAN1->FACT |= (1 << filterConfig->filterNumber); + } + CAN1->FCTRL_B.FINITEN = BIT_RESET; +} + +/*! + * @brief Select the start bank filter for slave CAN. + * + * @param bankNum: the start slave bank filter from 1..27. + * + * @retval None + */ +void CAN_SlaveStartBank(uint8_t bankNum) +{ + CAN1->FCTRL_B.FINITEN = SET; + CAN1->FCTRL_B.CAN2BN = bankNum; + CAN1->FCTRL_B.FINITEN = RESET; +} +#else /*! * @brief Congig the CAN peripheral according to the specified parameters in the filterConfig. * @@ -180,16 +267,16 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig) +void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig) { can->FCTRL_B.FINITEN = BIT_SET; can->FACT &= ~(1 << filterConfig->filterNumber); - /** Filter Scale */ + /* Filter Scale */ if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) { - /** 16-bit scale for the filter */ + /* 16-bit scale for the filter */ can->FSCFG &= ~(1 << filterConfig->filterNumber); can->sFilterRegister[filterConfig->filterNumber].FBANK1 = @@ -214,7 +301,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig) (0x0000FFFF & filterConfig->filterMaskIdLow); } - /** Filter Mode */ + /* Filter Mode */ if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) { can->FMCFG &= ~(1 << filterConfig->filterNumber); @@ -224,7 +311,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig) can->FMCFG |= (1 << filterConfig->filterNumber); } - /** Filter FIFO assignment */ + /* Filter FIFO assignment */ if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0) { can->FFASS &= ~(1 << filterConfig->filterNumber); @@ -234,13 +321,14 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig) can->FFASS |= (1 << filterConfig->filterNumber); } - /** Filter activation */ + /* Filter activation */ if (filterConfig->filterActivation == ENABLE) { can->FACT |= (1 << filterConfig->filterNumber); } can->FCTRL_B.FINITEN = BIT_RESET; } +#endif /*! * @brief Initialize a CAN_Config_T structure with the initial value. @@ -251,7 +339,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ConfigStructInit(CAN_Config_T *canConfig) +void CAN_ConfigStructInit(CAN_Config_T* canConfig) { canConfig->autoBusOffManage = DISABLE; canConfig->autoWakeUpMode = DISABLE; @@ -274,7 +362,7 @@ void CAN_ConfigStructInit(CAN_Config_T *canConfig) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_EnableDBGFreeze(CAN_T *can) +void CAN_EnableDBGFreeze(CAN_T* can) { can->MCTRL_B.DBGFRZE = ENABLE; } @@ -288,25 +376,11 @@ void CAN_EnableDBGFreeze(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_DisableDBGFreeze(CAN_T *can) +void CAN_DisableDBGFreeze(CAN_T* can) { can->MCTRL_B.DBGFRZE = DISABLE; } -/*! - * @brief Select the start bank filter for slave CAN. - * - * @param bankNum: the start slave bank filter from 1..27. - * - * @retval None - */ -void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum) -{ - can->FCTRL_B.FINITEN = SET; - can->FCTRL_B.CAN2BN = bankNum; - can->FCTRL_B.FINITEN = RESET; -} - /*! * @brief Initiates the transmission of a message. * @@ -318,11 +392,11 @@ void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage) +uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage) { uint8_t transmit_milbox = 0; - /** Select one empty transmit mailbox */ + /* Select one empty transmit mailbox */ if ((can->TXSTS & 0x04000000) == 0x04000000) { transmit_milbox = 0; @@ -340,7 +414,7 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage) return 3; //!< No mailbox is empty } - /** Set up the Id */ + /* Set up the Id */ can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001; if (TxMessage->typeID == CAN_TYPEID_STD) { @@ -351,17 +425,17 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage) can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq); } - /** Set up the TXDLEN */ + /* Set up the TXDLEN */ TxMessage->dataLengthCode &= 0x0F; can->sTxMailBox[transmit_milbox].TXDLEN &= (uint32_t)0xFFFFFFF0; can->sTxMailBox[transmit_milbox].TXDLEN |= TxMessage->dataLengthCode; - /** Set up the data field */ + /* Set up the data field */ can->sTxMailBox[transmit_milbox].TXMDL = ((uint32_t)TxMessage->data[3] << 24) | ((uint32_t)TxMessage->data[2] << 16) | ((uint32_t)TxMessage->data[1] << 8) | ((uint32_t)TxMessage->data[0]); can->sTxMailBox[transmit_milbox].TXMDH = ((uint32_t)TxMessage->data[7] << 24) | ((uint32_t)TxMessage->data[6] << 16) | ((uint32_t)TxMessage->data[5] << 8) | ((uint32_t)TxMessage->data[4]); - /** Request transmission */ + /* Request transmission */ can->sTxMailBox[transmit_milbox].TXMID |= 0x00000001; return transmit_milbox; @@ -380,54 +454,54 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox) +uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) { uint32_t state = 0; switch (TxMailbox) { - case (CAN_TX_MAILBIX_0): - state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000); - break; - case (CAN_TX_MAILBIX_1): - state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000); - break; - case (CAN_TX_MAILBIX_2): - state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000); - break; - default: - state = 0; - break; + case (CAN_TX_MAILBIX_0): + state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000); + break; + case (CAN_TX_MAILBIX_1): + state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000); + break; + case (CAN_TX_MAILBIX_2): + state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000); + break; + default: + state = 0; + break; } switch (state) { - /** Transmit pending */ - case (0x0): - state = 2; - break; - /** Transmit failed */ - case (0x00000001 | 0x04000000): - state = 0; - break; - case (0x00000100 | 0x08000000): - state = 0; - break; - case (0x00010000 | 0x10000000): - state = 0; - break; - /** Transmit succeeded */ - case (0x00000001 | 0x00000002 | 0x04000000): - state = 1; - break; - case (0x00000100 | 0x00000200 | 0x08000000): - state = 1; - break; - case (0x00010000 | 0x00020000 | 0x10000000): - state = 1; - break; - default: - state = 0; - break; + /* Transmit pending */ + case (0x0): + state = 2; + break; + /* Transmit failed */ + case (0x00000001 | 0x04000000): + state = 0; + break; + case (0x00000100 | 0x08000000): + state = 0; + break; + case (0x00010000 | 0x10000000): + state = 0; + break; + /* Transmit succeeded */ + case (0x00000001 | 0x00000002 | 0x04000000): + state = 1; + break; + case (0x00000100 | 0x00000200 | 0x08000000): + state = 1; + break; + case (0x00010000 | 0x00020000 | 0x10000000): + state = 1; + break; + default: + state = 0; + break; } return (uint8_t) state; } @@ -447,21 +521,21 @@ uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox) +void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) { switch (TxMailbox) { - case CAN_TX_MAILBIX_0: - can->TXSTS_B.ABREQFLG0 = BIT_SET; - break; - case CAN_TX_MAILBIX_1: - can->TXSTS_B.ABREQFLG1 = BIT_SET; - break; - case CAN_TX_MAILBIX_2: - can->TXSTS_B.ABREQFLG2 = BIT_SET; - break; - default: - break; + case CAN_TX_MAILBIX_0: + can->TXSTS_B.ABREQFLG0 = BIT_SET; + break; + case CAN_TX_MAILBIX_1: + can->TXSTS_B.ABREQFLG1 = BIT_SET; + break; + case CAN_TX_MAILBIX_2: + can->TXSTS_B.ABREQFLG2 = BIT_SET; + break; + default: + break; } } @@ -481,9 +555,9 @@ void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage) +void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage) { - /** Get the Id */ + /* Get the Id */ RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID)); if (RxMessage->typeID == CAN_TYPEID_STD) { @@ -497,7 +571,7 @@ void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMess RxMessage->remoteTxReq = can->sRxMailBox[FIFONumber].RXMID_B.RFTXREQ; RxMessage->dataLengthCode = can->sRxMailBox[FIFONumber].RXDLEN_B.DLCODE; RxMessage->filterMatchIndex = can->sRxMailBox[FIFONumber].RXDLEN_B.FMIDX; - /** Get the data field */ + /* Get the data field */ RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE0; RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1; RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2; @@ -531,7 +605,7 @@ void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMess * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber) +void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber) { if (FIFONumber == CAN_RX_FIFO_0) { @@ -557,7 +631,7 @@ void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber) +uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber) { if (FIFONumber == CAN_RX_FIFO_0) { @@ -586,7 +660,7 @@ uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode) +uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode) { uint8_t states = 0; uint32_t time_out = 0x0000FFFF; @@ -651,7 +725,7 @@ uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_SleepMode(CAN_T *can) +uint8_t CAN_SleepMode(CAN_T* can) { can->MCTRL_B.SLEEPREQ = BIT_SET; can->MCTRL_B.INITREQ = BIT_RESET; @@ -674,7 +748,7 @@ uint8_t CAN_SleepMode(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_WakeUpMode(CAN_T *can) +uint8_t CAN_WakeUpMode(CAN_T* can) { uint32_t time_out = 0x0000FFFF; @@ -699,7 +773,7 @@ uint8_t CAN_WakeUpMode(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadLastErrorCode(CAN_T *can) +uint8_t CAN_ReadLastErrorCode(CAN_T* can) { return can->ERRSTS_B.LERRC; } @@ -713,7 +787,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadRxErrorCounter(CAN_T *can) +uint8_t CAN_ReadRxErrorCounter(CAN_T* can) { return can->ERRSTS_B.RXERRCNT; } @@ -727,7 +801,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can) +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can) { return can->ERRSTS_B.TXERRCNT; } @@ -758,7 +832,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts) +void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts) { can->INTEN |= interrupts; } @@ -789,7 +863,7 @@ void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts) +void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts) { can->INTEN &= ~interrupts; } @@ -821,7 +895,7 @@ void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag) +uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) { uint8_t status = 0; @@ -905,11 +979,11 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag) +void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag) { uint32_t flagtmp = 0; - /** ERRSTS register */ + /* ERRSTS register */ if (flag == 0x30F00070) { can->ERRSTS = RESET; @@ -962,7 +1036,7 @@ void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag) * * @note CAN2 applies only to APM32F103xC device. */ -uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag) +uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag) { uint8_t status = 0; @@ -970,53 +1044,53 @@ uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag) { switch (flag) { - case CAN_INT_TXME: - status = can->TXSTS_B.REQCFLG0; - status |= can->TXSTS_B.REQCFLG1; - status |= can->TXSTS_B.REQCFLG2; - break; - case CAN_INT_F0MP: - status = can->RXF0_B.FMNUM0; - break; - case CAN_INT_F0FULL: - status = can->RXF0_B.FFULLFLG0; - break; - case CAN_INT_F0OVR: - status = can->RXF0_B.FOVRFLG0; - break; - case CAN_INT_F1MP: - status = can->RXF1_B.FMNUM1; - break; - case CAN_INT_F1FULL: - status = can->RXF1_B.FFULLFLG1; - break; - case CAN_INT_F1OVR: - status = can->RXF1_B.FOVRFLG1; - break; - case CAN_INT_WUP: - status = can->MSTS_B.WUPIFLG; - break; - case CAN_INT_SLEEP: - status = can->MSTS_B.SLEEPIFLG; - break; - case CAN_INT_ERRW: - status = can->ERRSTS_B.ERRWFLG; - break; - case CAN_INT_ERRP: - status = can->ERRSTS_B.ERRPFLG; - break; - case CAN_INT_BOF: - status = can->ERRSTS_B.BOFLG; - break; - case CAN_INT_LEC: - status = can->ERRSTS_B.LERRC; - break; - case CAN_INT_ERR: - status = can->MSTS_B.ERRIFLG; - break; - default: - status = RESET; - break; + case CAN_INT_TXME: + status = can->TXSTS_B.REQCFLG0; + status |= can->TXSTS_B.REQCFLG1; + status |= can->TXSTS_B.REQCFLG2; + break; + case CAN_INT_F0MP: + status = can->RXF0_B.FMNUM0; + break; + case CAN_INT_F0FULL: + status = can->RXF0_B.FFULLFLG0; + break; + case CAN_INT_F0OVR: + status = can->RXF0_B.FOVRFLG0; + break; + case CAN_INT_F1MP: + status = can->RXF1_B.FMNUM1; + break; + case CAN_INT_F1FULL: + status = can->RXF1_B.FFULLFLG1; + break; + case CAN_INT_F1OVR: + status = can->RXF1_B.FOVRFLG1; + break; + case CAN_INT_WUP: + status = can->MSTS_B.WUPIFLG; + break; + case CAN_INT_SLEEP: + status = can->MSTS_B.SLEEPIFLG; + break; + case CAN_INT_ERRW: + status = can->ERRSTS_B.ERRWFLG; + break; + case CAN_INT_ERRP: + status = can->ERRSTS_B.ERRPFLG; + break; + case CAN_INT_BOF: + status = can->ERRSTS_B.BOFLG; + break; + case CAN_INT_LEC: + status = can->ERRSTS_B.LERRC; + break; + case CAN_INT_ERR: + status = can->MSTS_B.ERRIFLG; + break; + default: + status = RESET; + break; } } else @@ -1050,55 +1124,55 @@ uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag) * * @note CAN2 applies only to APM32F103xC device. */ -void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag) +void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag) { switch (flag) { - case CAN_INT_TXME: - can->TXSTS_B.REQCFLG0 = BIT_SET; - can->TXSTS_B.REQCFLG1 = BIT_SET; - can->TXSTS_B.REQCFLG2 = BIT_SET; - break; - case CAN_INT_F0FULL: - can->RXF0_B.FFULLFLG0 = BIT_SET; - break; - case CAN_INT_F0OVR: - can->RXF0_B.FOVRFLG0 = BIT_SET; - break; - case CAN_INT_F1FULL: - can->RXF1_B.FFULLFLG1 = BIT_SET; - break; - case CAN_INT_F1OVR: - can->RXF1_B.FOVRFLG1 = BIT_SET; - break; - case CAN_INT_WUP: - can->MSTS_B.WUPIFLG = BIT_SET; - break; - case CAN_INT_SLEEP: - can->MSTS_B.SLEEPIFLG = BIT_SET; - break; - case CAN_INT_ERRW: - can->MSTS_B.ERRIFLG = BIT_SET; - break; - case CAN_INT_ERRP: - can->MSTS_B.ERRIFLG = BIT_SET; - break; - case CAN_INT_BOF: - can->MSTS_B.ERRIFLG = BIT_SET; - break; - case CAN_INT_LEC: - can->ERRSTS_B.LERRC = BIT_RESET; - can->MSTS_B.ERRIFLG = BIT_SET; - break; - case CAN_INT_ERR: - can->ERRSTS_B.LERRC = BIT_RESET; - can->MSTS_B.ERRIFLG = BIT_SET; - break; - default: - break; + case CAN_INT_TXME: + can->TXSTS_B.REQCFLG0 = BIT_SET; + can->TXSTS_B.REQCFLG1 = BIT_SET; + can->TXSTS_B.REQCFLG2 = BIT_SET; + break; + case CAN_INT_F0FULL: + can->RXF0_B.FFULLFLG0 = BIT_SET; + break; + case CAN_INT_F0OVR: + can->RXF0_B.FOVRFLG0 = BIT_SET; + break; + case CAN_INT_F1FULL: + can->RXF1_B.FFULLFLG1 = BIT_SET; + break; + case CAN_INT_F1OVR: + can->RXF1_B.FOVRFLG1 = BIT_SET; + break; + case CAN_INT_WUP: + can->MSTS_B.WUPIFLG = BIT_SET; + break; + case CAN_INT_SLEEP: + can->MSTS_B.SLEEPIFLG = BIT_SET; + break; + case CAN_INT_ERRW: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_ERRP: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_BOF: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_LEC: + can->ERRSTS_B.LERRC = BIT_RESET; + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_ERR: + can->ERRSTS_B.LERRC = BIT_RESET; + can->MSTS_B.ERRIFLG = BIT_SET; + break; + default: + break; } } -/**@} end of group CAN_Fuctions*/ -/**@} end of group CAN_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group CAN_Functions */ +/**@} end of group CAN_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c index fe208b5678..f1a145053c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c @@ -3,9 +3,9 @@ * * @brief This file provides all the CRC firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,15 +25,16 @@ #include "apm32f10x_crc.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup CRC_Driver CRC Driver + * @brief CRC driver modules @{ */ -/** @addtogroup CRC_Fuctions Fuctions +/** @defgroup CRC_Functions Functions @{ */ @@ -73,7 +74,7 @@ uint32_t CRC_CalculateCRC(uint32_t data) * * @retval A 32-bit CRC value */ -uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen) +uint32_t CRC_CalculateBlockCRC(uint32_t* buf, uint32_t bufLen) { while (bufLen--) { @@ -119,6 +120,6 @@ uint8_t CRC_ReadIDRegister(void) return (CRC->INDATA); } -/**@} end of group CRC_Fuctions*/ +/**@} end of group CRC_Functions*/ /**@} end of group CRC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c index fac9e9f135..fd076d3d38 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c @@ -3,9 +3,9 @@ * * @brief This file provides all the DAC firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #include "apm32f10x_dac.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup DAC_Driver DAC Driver + * @brief DAC driver modules @{ */ -/** @addtogroup DAC_Fuctions Fuctions +/** @defgroup DAC_Functions Functions @{ */ @@ -63,7 +64,7 @@ void DAC_Reset(void) * * @retval None */ -void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig) +void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig) { uint32_t tmp1 = 0, tmp2 = 0; @@ -88,15 +89,15 @@ void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig) * * @retval None */ -void DAC_ConfigStructInit(DAC_Config_T *dacConfig) +void DAC_ConfigStructInit(DAC_Config_T* dacConfig) { - /** Initialize the DAC_Trigger member */ + /* Initialize the DAC_Trigger member */ dacConfig->trigger = DAC_TRIGGER_NONE; - /** Initialize the DAC_WaveGeneration member */ + /* Initialize the DAC_WaveGeneration member */ dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE; - /** Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ dacConfig->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1; - /** Initialize the DAC_OutputBuffer member */ + /* Initialize the DAC_OutputBuffer member */ dacConfig->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE; } @@ -321,8 +322,8 @@ void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data) tmp = (uint32_t)DAC_BASE; tmp += 0x00000008 + align; - /** Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = data; + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t*) tmp = data; } /*! @@ -345,8 +346,8 @@ void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data) tmp = (uint32_t)DAC_BASE; tmp += 0x00000014 + align; - /** Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = data; + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t*) tmp = data; } /*! @@ -368,7 +369,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1 { uint32_t data = 0, tmp = 0; - /** Calculate and set dual DAC data holding register value */ + /* Calculate and set dual DAC data holding register value */ if (align == DAC_ALIGN_8BIT_R) { data = ((uint32_t)data2 << 8) | data1; @@ -381,8 +382,8 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1 tmp = (uint32_t)DAC_BASE; tmp += 0x00000020 + align; - /** Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t*)tmp = data; } /*! @@ -402,10 +403,10 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel) tmp = (uint32_t) DAC_BASE ; tmp += 0x0000002C + ((uint32_t)channel >> 2); - /** Returns the DAC channel data output register value */ - return (uint16_t)(*(__IO uint32_t *) tmp); + /* Returns the DAC channel data output register value */ + return (uint16_t)(*(__IO uint32_t*) tmp); } -/**@} end of group DAC_Fuctions*/ +/**@} end of group DAC_Functions*/ /**@} end of group DAC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c index 3486aa8cfe..1de630864c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c @@ -3,9 +3,9 @@ * * @brief This file provides all the DEBUG firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,15 +25,16 @@ #include "apm32f10x_dbgmcu.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup DBGMCU_Driver DBGMCU Driver + * @brief DBGMCU driver modules @{ */ -/** @addtogroup DBGMCU_Fuctions Fuctions +/** @defgroup DBGMCU_Functions Functions @{ */ @@ -141,6 +142,6 @@ void DBGMCU_Disable(uint32_t periph) DBGMCU->CFG &= ~periph; } -/**@} end of group DBGMCU_Fuctions*/ -/**@} end of group DBGMCU_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group DBGMCU_Functions*/ +/**@} end of group DBGMCU_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c index fc302ad9a4..01a7185fc6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c @@ -3,9 +3,9 @@ * * @brief This file provides all the DMA firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,15 +25,16 @@ #include "apm32f10x_dma.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup DMA_Driver DMA Driver + * @brief DMA driver modules @{ */ -/** @addtogroup DMA_Fuctions Fuctions +/** @defgroup DMA_Functions Functions @{ */ @@ -46,7 +47,7 @@ * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_Reset(DMA_Channel_T *channel) +void DMA_Reset(DMA_Channel_T* channel) { channel->CHCFG_B.CHEN = BIT_RESET; channel->CHCFG = 0; @@ -115,7 +116,7 @@ void DMA_Reset(DMA_Channel_T *channel) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig) +void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig) { channel->CHCFG_B.DIRCFG = dmaConfig->dir; channel->CHCFG_B.CIRMODE = dmaConfig->loopMode; @@ -138,7 +139,7 @@ void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig) * * @retval None */ -void DMA_ConfigStructInit(DMA_Config_T *dmaConfig) +void DMA_ConfigStructInit(DMA_Config_T* dmaConfig) { dmaConfig->peripheralBaseAddr = 0; dmaConfig->memoryBaseAddr = 0; @@ -162,7 +163,7 @@ void DMA_ConfigStructInit(DMA_Config_T *dmaConfig) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_Enable(DMA_Channel_T *channel) +void DMA_Enable(DMA_Channel_T* channel) { channel->CHCFG_B.CHEN = ENABLE; } @@ -176,7 +177,7 @@ void DMA_Enable(DMA_Channel_T *channel) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_Disable(DMA_Channel_T *channel) +void DMA_Disable(DMA_Channel_T* channel) { channel->CHCFG_B.CHEN = DISABLE; } @@ -192,7 +193,7 @@ void DMA_Disable(DMA_Channel_T *channel) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber) +void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber) { channel->CHNDATA = dataNumber; } @@ -206,7 +207,7 @@ void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber) * * @note DMA2 Channel only for APM32 High density devices. */ -uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel) +uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel) { return channel->CHNDATA; } @@ -226,7 +227,7 @@ uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) +void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt) { channel->CHCFG |= interrupt; } @@ -246,7 +247,7 @@ void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) * * @note DMA2 Channel only for APM32 High density devices. */ -void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) +void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt) { channel->CHCFG &= ~interrupt; } @@ -491,6 +492,7 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag) } } } + /*! * @brief Clears the specified DMA Channel's interrupts. * @@ -562,6 +564,6 @@ void DMA_ClearIntFlag(uint32_t flag) } } -/**@} end of group DMA_Fuctions*/ +/**@} end of group DMA_Functions*/ /**@} end of group DMA_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c index 290ab8d697..3aa7cde45a 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c @@ -3,9 +3,9 @@ * * @brief This file contains all the functions for the DMC controler peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #ifdef APM32F10X_HD #include "apm32f10x_dmc.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup DMC_Driver DMC Driver +/** @addtogroup DMC_Driver DMC Driver + * @brief DMC driver modules @{ */ -/** @addtogroup DMC_Fuctions Fuctions +/** @defgroup DMC_Functions Functions @{ */ @@ -45,7 +46,7 @@ * * @retval None */ -void DMC_Config(DMC_Config_T *dmcConfig) +void DMC_Config(DMC_Config_T* dmcConfig) { DMC->SW_B.MCSW = 1; while (!DMC->CTRL1_B.INIT); @@ -73,7 +74,7 @@ void DMC_Config(DMC_Config_T *dmcConfig) * * @retval None */ -void DMC_ConfigStructInit(DMC_Config_T *dmcConfig) +void DMC_ConfigStructInit(DMC_Config_T* dmcConfig) { dmcConfig->bankWidth = DMC_BANK_WIDTH_2; dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE; @@ -91,7 +92,7 @@ void DMC_ConfigStructInit(DMC_Config_T *dmcConfig) * * @retval None */ -void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig) +void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig) { DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS; DMC->TIM0_B.DTIMSEL = timingConfig->tRCD; @@ -116,7 +117,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig) * * @retval None */ -void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig) +void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig) { timingConfig->latencyCAS = DMC_CAS_LATENCY_3; timingConfig->tARP = DMC_AUTO_REFRESH_10; @@ -457,8 +458,9 @@ void DMC_ConfigWRAPB(DMC_WRPB_T burst) DMC->CTRL2_B.WRPBSEL = burst; } +/**@} end of group DMC_Functions*/ +/**@} end of group DMC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ + #endif //defined APM32F10X_HD -/**@} end of group DMC_Fuctions*/ -/**@} end of group DMC_Driver*/ -/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c index 9b4c63aeac..d88685e045 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c @@ -3,9 +3,9 @@ * * @brief This file provides all the EINT firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,15 +25,16 @@ #include "apm32f10x_eint.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup EINT_Driver EINT Driver + * @brief EINT driver modules @{ */ -/** @addtogroup EINT_Fuctions Fuctions +/** @defgroup EINT_Functions Functions @{ */ @@ -60,7 +61,7 @@ void EINT_Reset(void) * * @retval None */ -void EINT_Config(EINT_Config_T *eintConfig) +void EINT_Config(EINT_Config_T* eintConfig) { uint32_t temp = 0; temp = (uint32_t)EINT_BASE; @@ -71,7 +72,7 @@ void EINT_Config(EINT_Config_T *eintConfig) EINT->EMASK &= ~eintConfig->line; temp += eintConfig->mode; - *(__IOM uint32_t *) temp |= eintConfig->line; + *(__IOM uint32_t*) temp |= eintConfig->line; EINT->RTEN &= ~eintConfig->line; EINT->FTEN &= ~eintConfig->line; @@ -86,14 +87,14 @@ void EINT_Config(EINT_Config_T *eintConfig) temp = (uint32_t)EINT_BASE; temp += eintConfig->trigger; - *(__IOM uint32_t *) temp |= eintConfig->line; + *(__IOM uint32_t*) temp |= eintConfig->line; } } else { temp += eintConfig->mode; - *(__IOM uint32_t *) temp &= ~eintConfig->line; + *(__IOM uint32_t*) temp &= ~eintConfig->line; } } @@ -104,7 +105,7 @@ void EINT_Config(EINT_Config_T *eintConfig) * * @retval None */ -void EINT_ConfigStructInit(EINT_Config_T *eintConfig) +void EINT_ConfigStructInit(EINT_Config_T* eintConfig) { eintConfig->line = EINT_LINENONE; eintConfig->mode = EINT_MODE_INTERRUPT; @@ -200,6 +201,6 @@ void EINT_ClearIntFlag(uint32_t line) EINT->IPEND = line; } -/**@} end of group EINT_Fuctions*/ -/**@} end of group EINT_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group EINT_Functions*/ +/**@} end of group EINT_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c index 4543a7178f..d0a01013b9 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c @@ -3,9 +3,9 @@ * * @brief This file provides all the FMC firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,10 +23,11 @@ * and limitations under the License. */ +/* Includes */ #include "apm32f10x_fmc.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -34,7 +35,7 @@ @{ */ -/** @addtogroup FMC_Fuctions Fuctions +/** @defgroup FMC_Functions Functions @{ */ @@ -257,7 +258,7 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) { FMC->CTRL2_B.PG = BIT_SET; - *(__IOM uint16_t *)address = data; + *(__IOM uint16_t*)address = data; status = FMC_WaitForLastOperation(0x000B0000); @@ -265,7 +266,7 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) { temp = address + 2; - *(__IOM uint16_t *) temp = data >> 16; + *(__IOM uint16_t*) temp = data >> 16; status = FMC_WaitForLastOperation(0x000B0000); FMC->CTRL2_B.PG = BIT_RESET; @@ -309,7 +310,7 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data) if (status == FMC_STATUS_COMPLETE) { FMC->CTRL2_B.PG = BIT_SET; - *(__IOM uint16_t *)address = data; + *(__IOM uint16_t*)address = data; status = FMC_WaitForLastOperation(0x000B0000); FMC->CTRL2_B.PG = BIT_RESET; } @@ -346,7 +347,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) FMC->OBKEY = 0xCDEF89AB; FMC->CTRL2_B.OBP = BIT_SET; - *(__IOM uint16_t *)address = data; + *(__IOM uint16_t*)address = data; status = FMC_WaitForLastOperation(0x000B0000); if (status == FMC_STATUS_TIMEOUT) { @@ -361,11 +362,11 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) * * @param page:the address of the pages to be write protection * This parameter can be any combination of the following values: - * for APM32F10X_LD + * for APM32F10X_LD : * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31 - * for APM32F10X_MD + * for APM32F10X_MD : * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127 - * for APM32F10X_HD + * for APM32F10X_HD : * @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127 * @arg FMC_WRP_PAGE_ALL * @@ -454,7 +455,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void) { FMC->CTRL2_B.OBE = BIT_RESET; FMC->CTRL2_B.OBP = BIT_SET; - OB->RDP = 0x0000; + OB->RDP = 0x00; status = FMC_WaitForLastOperation(0x000B0000); @@ -501,7 +502,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void) { FMC->CTRL2_B.OBE = BIT_RESET; FMC->CTRL2_B.OBP = BIT_SET; - OB->RDP = 0x00A5; + OB->RDP = 0xA5; status = FMC_WaitForLastOperation(0x000B0000); @@ -529,7 +530,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void) * @arg FMC_STATUS_COMPLETE * @arg FMC_STATUS_TIMEOUT */ -FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig) +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig) { FMC_STATUS_T status = FMC_STATUS_COMPLETE; @@ -763,6 +764,6 @@ FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut) return status; } -/**@} end of group FMC_Fuctions*/ +/**@} end of group FMC_Functions*/ /**@} end of group FMC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c index e4399deb9e..be9e785ae2 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c @@ -3,9 +3,9 @@ * * @brief This file provides all the GPIO firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,10 +23,11 @@ * and limitations under the License. */ +/* Includes */ #include "apm32f10x_gpio.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -34,7 +35,7 @@ @{ */ -/** @addtogroup GPIO_Fuctions Fuctions +/** @defgroup GPIO_Functions Functions @{ */ @@ -46,7 +47,7 @@ * * @retval None */ -void GPIO_Reset(GPIO_T *port) +void GPIO_Reset(GPIO_T* port) { RCM_APB2_PERIPH_T APB2Periph; @@ -106,7 +107,7 @@ void GPIO_AFIOReset(void) * * @retval None */ -void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig) +void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig) { uint8_t i; uint32_t mode; @@ -181,10 +182,10 @@ void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig) * * @retval None */ -void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig) +void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig) { gpioConfig->pin = GPIO_PIN_ALL; - gpioConfig->speed = GPIO_SPEED_20MHz; + gpioConfig->speed = GPIO_SPEED_2MHz; gpioConfig->mode = GPIO_MODE_IN_FLOATING; } @@ -199,7 +200,7 @@ void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig) * * @retval The input port pin value */ -uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin) +uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin) { uint8_t ret; @@ -216,7 +217,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin) * * @retval GPIO input data port value */ -uint16_t GPIO_ReadInputPort(GPIO_T *port) +uint16_t GPIO_ReadInputPort(GPIO_T* port) { return ((uint16_t)port->IDATA); } @@ -232,7 +233,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T *port) * * @retval The output port pin value */ -uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin) +uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin) { uint8_t ret; @@ -250,7 +251,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin) * * @retval output data port value */ -uint16_t GPIO_ReadOutputPort(GPIO_T *port) +uint16_t GPIO_ReadOutputPort(GPIO_T* port) { return ((uint16_t)port->ODATA); } @@ -266,7 +267,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T *port) * * @retval None */ -void GPIO_SetBit(GPIO_T *port, uint16_t pin) +void GPIO_SetBit(GPIO_T* port, uint16_t pin) { port->BSC = (uint32_t)pin; } @@ -282,7 +283,7 @@ void GPIO_SetBit(GPIO_T *port, uint16_t pin) * * @retval None */ -void GPIO_ResetBit(GPIO_T *port, uint16_t pin) +void GPIO_ResetBit(GPIO_T* port, uint16_t pin) { port->BC = (uint32_t)pin; } @@ -304,7 +305,7 @@ void GPIO_ResetBit(GPIO_T *port, uint16_t pin) * * @retval None */ -void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal) +void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal) { if (bitVal != BIT_RESET) { @@ -326,7 +327,7 @@ void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal) * * @retval None */ -void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue) +void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue) { port->ODATA = (uint32_t)portValue; } @@ -342,20 +343,20 @@ void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue) * * @retval None */ -void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin) +void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin) { uint32_t val = 0x00010000; val |= pin; - /** Set LCKK bit */ + /* Set LCKK bit */ port->LOCK = val ; - /** Reset LCKK bit */ + /* Reset LCKK bit */ port->LOCK = pin; - /** Set LCKK bit */ + /* Set LCKK bit */ port->LOCK = val; - /** Read LCKK bit*/ + /* Read LCKK bit*/ val = port->LOCK; - /** Read LCKK bit*/ + /* Read LCKK bit*/ val = port->LOCK; } @@ -435,6 +436,24 @@ void GPIO_DisableEventOutput(void) * @arg GPIO_REMAP_PD01 : PD01 Alternate Function mapping * @arg GPIO_NO_REMAP_TMR5CH4_LSI : No LSI connected to TIM5 Channel4 input capture for calibration * @arg GPIO_REMAP_TMR5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * Only For APM32F10X_CL devices(APM32F107xx and APM32F105xx): + * @arg GPIO_NO_REMAP_ETH_MAC : No Ethernet MAC Alternate remapping + * @arg GPIO_REMAP_ETH_MAC : Ethernet MAC Alternate remapping + * @arg GPIO_NO_REMAP_CAN2 : No CAN2 Alternate Function mapping + * @arg GPIO_REMAP_CAN2 : CAN2 Alternate Function mapping + * @arg GPIO_REMAP_MACEISEL_MII : Ethernet MAC External Interface Select MII Interface + * @arg GPIO_REMAP_MACEISEL_RMII : Ethernet MAC External Interface Select RMII Interface + * @arg GPIO_NO_REMAP_SPI3 : No SPI3 Alternate Function mapping + * @arg GPIO_REMAP_SPI3 : SPI3 Alternate Function mapping + * @arg GPIO_NO_REMAP_SWJ : Full SWJ Enabled (JTAG-DP + SW-DP) + * @arg GPIO_REMAP_SWJ_NOJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_REMAP_SWJ_JTAGDISABLE : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_REMAP_SWJ_DISABLE : Full SWJ Disabled (JTAG-DP + SW-DP) + * @arg GPIO_NO_REMAP_TMR2ITR1 : No TMR2 ITR1 Alternate Function mapping + * @arg GPIO_REMAP_TMR2ITR1 : TMR2 ITR1 Alternate Function mapping + * @arg GPIO_NO_REMAP_PTP_PPS : No Ethernet MAC PTP_PPS Alternate Function mapping + * @arg GPIO_REMAP_PTP_PPS : Ethernet MAC PTP_PPS Alternate Function mapping + * For Other APM32F10X_HD/MD/LD devices: * @arg GPIO_NO_REMAP_ADC1_ETRGINJ : No ADC1 External Trigger Injected Conversion remapping * @arg GPIO_REMAP_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping * @arg GPIO_NO_REMAP_ADC1_ETRGREG : No ADC1 External Trigger Regular Conversion remapping @@ -540,6 +559,6 @@ void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSou } } -/**@} end of group GPIO_Fuctions*/ +/**@} end of group GPIO_Functions*/ /**@} end of group GPIO_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c index f03564c023..1b1ce60fcb 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c @@ -3,9 +3,9 @@ * * @brief This file provides all the I2C firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,10 +23,11 @@ * and limitations under the License. */ +/* Includes */ #include "apm32f10x_i2c.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -34,7 +35,7 @@ @{ */ -/** @addtogroup I2C_Fuctions Fuctions +/** @defgroup I2C_Functions Functions @{ */ @@ -45,7 +46,7 @@ * * @retval None */ -void I2C_Reset(I2C_T *i2c) +void I2C_Reset(I2C_T* i2c) { if (i2c == I2C1) { @@ -68,7 +69,7 @@ void I2C_Reset(I2C_T *i2c) * * @retval None */ -void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig) +void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) { uint16_t tmpreg = 0, freqrange = 0; uint32_t PCLK1 = 8000000, PCLK2 = 0; @@ -76,12 +77,12 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig) i2c->SWITCH = 0; - /** I2C CTRL2 Configuration */ + /* I2C CTRL2 Configuration */ RCM_ReadPCLKFreq(&PCLK1, &PCLK2); freqrange = PCLK1 / 1000000; i2c->CTRL2_B.CLKFCFG = freqrange; - /** I2C CLKCTRL Configuration */ + /* I2C CLKCTRL Configuration */ i2c->CTRL1_B.I2CEN = BIT_RESET; if (i2cConfig->clockSpeed <= 100000) @@ -94,7 +95,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig) i2c->RISETMAX = freqrange + 1; tmpreg |= result; } - /** Configure speed in fast mode */ + /* Configure speed in fast mode */ else { if (i2cConfig->dutyCycle == I2C_DUTYCYCLE_2) @@ -118,7 +119,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig) i2c->CLKCTRL = tmpreg; i2c->CTRL1_B.I2CEN = BIT_SET; - /** i2c CTRL1 Configuration */ + /* i2c CTRL1 Configuration */ i2c->CTRL1_B.ACKEN = BIT_RESET; i2c->CTRL1_B.SMBTCFG = BIT_RESET; i2c->CTRL1_B.SMBEN = BIT_RESET; @@ -136,7 +137,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig) * * @retval None */ -void I2C_ConfigStructInit(I2C_Config_T *i2cConfig) +void I2C_ConfigStructInit(I2C_Config_T* i2cConfig) { i2cConfig->clockSpeed = 5000; i2cConfig->mode = I2C_MODE_I2C; @@ -153,7 +154,7 @@ void I2C_ConfigStructInit(I2C_Config_T *i2cConfig) * * @retval None */ -void I2C_Enable(I2C_T *i2c) +void I2C_Enable(I2C_T* i2c) { i2c->CTRL1_B.I2CEN = ENABLE; } @@ -165,7 +166,7 @@ void I2C_Enable(I2C_T *i2c) * * @retval None */ -void I2C_Disable(I2C_T *i2c) +void I2C_Disable(I2C_T* i2c) { i2c->CTRL1_B.I2CEN = DISABLE; } @@ -177,7 +178,7 @@ void I2C_Disable(I2C_T *i2c) * * @retval None */ -void I2C_EnableGenerateStart(I2C_T *i2c) +void I2C_EnableGenerateStart(I2C_T* i2c) { i2c->CTRL1_B.START = BIT_SET; } @@ -189,7 +190,7 @@ void I2C_EnableGenerateStart(I2C_T *i2c) * * @retval None */ -void I2C_DisableGenerateStart(I2C_T *i2c) +void I2C_DisableGenerateStart(I2C_T* i2c) { i2c->CTRL1_B.START = BIT_RESET; } @@ -201,7 +202,7 @@ void I2C_DisableGenerateStart(I2C_T *i2c) * * @retval None */ -void I2C_EnableGenerateStop(I2C_T *i2c) +void I2C_EnableGenerateStop(I2C_T* i2c) { i2c->CTRL1_B.STOP = BIT_SET; } @@ -213,7 +214,7 @@ void I2C_EnableGenerateStop(I2C_T *i2c) * * @retval None */ -void I2C_DisableGenerateStop(I2C_T *i2c) +void I2C_DisableGenerateStop(I2C_T* i2c) { i2c->CTRL1_B.STOP = BIT_RESET; } @@ -225,7 +226,7 @@ void I2C_DisableGenerateStop(I2C_T *i2c) * * @retval None */ -void I2C_EnableAcknowledge(I2C_T *i2c) +void I2C_EnableAcknowledge(I2C_T* i2c) { i2c->CTRL1_B.ACKEN = ENABLE; } @@ -237,7 +238,7 @@ void I2C_EnableAcknowledge(I2C_T *i2c) * * @retval None */ -void I2C_DisableAcknowledge(I2C_T *i2c) +void I2C_DisableAcknowledge(I2C_T* i2c) { i2c->CTRL1_B.ACKEN = DISABLE; } @@ -251,7 +252,7 @@ void I2C_DisableAcknowledge(I2C_T *i2c) * * @retval None */ -void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address) +void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address) { i2c->SADDR2_B.ADDR2 = address; } @@ -263,7 +264,7 @@ void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address) * * @retval None */ -void I2C_EnableDualAddress(I2C_T *i2c) +void I2C_EnableDualAddress(I2C_T* i2c) { i2c->SADDR2_B.ADDRNUM = ENABLE; } @@ -275,7 +276,7 @@ void I2C_EnableDualAddress(I2C_T *i2c) * * @retval None */ -void I2C_DisableDualAddress(I2C_T *i2c) +void I2C_DisableDualAddress(I2C_T* i2c) { i2c->SADDR2_B.ADDRNUM = DISABLE; } @@ -287,7 +288,7 @@ void I2C_DisableDualAddress(I2C_T *i2c) * * @retval None */ -void I2C_EnableGeneralCall(I2C_T *i2c) +void I2C_EnableGeneralCall(I2C_T* i2c) { i2c->CTRL1_B.SRBEN = ENABLE; } @@ -299,7 +300,7 @@ void I2C_EnableGeneralCall(I2C_T *i2c) * * @retval None */ -void I2C_DisableGeneralCall(I2C_T *i2c) +void I2C_DisableGeneralCall(I2C_T* i2c) { i2c->CTRL1_B.SRBEN = DISABLE; } @@ -313,7 +314,7 @@ void I2C_DisableGeneralCall(I2C_T *i2c) * * @retval None */ -void I2C_TxData(I2C_T *i2c, uint8_t data) +void I2C_TxData(I2C_T* i2c, uint8_t data) { i2c->DATA_B.DATA = data; } @@ -325,7 +326,7 @@ void I2C_TxData(I2C_T *i2c, uint8_t data) * * @retval received data */ -uint8_t I2C_RxData(I2C_T *i2c) +uint8_t I2C_RxData(I2C_T* i2c) { return i2c->DATA_B.DATA; } @@ -343,7 +344,7 @@ uint8_t I2C_RxData(I2C_T *i2c) * @arg I2C_DIRECTION_RX: Receiver mode * @retval None */ -void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction) +void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction) { if (direction != I2C_DIRECTION_TX) { @@ -375,32 +376,32 @@ void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction) * * @retval The value of the read register */ -uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister) +uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister) { switch (i2cRegister) { - case I2C_REGISTER_CTRL1: - return i2c->CTRL1; - case I2C_REGISTER_CTRL2: - return i2c->CTRL2; - case I2C_REGISTER_SADDR1: - return i2c->SADDR1; - case I2C_REGISTER_SADDR2: - return i2c->SADDR2; - case I2C_REGISTER_DATA: - return i2c->DATA; - case I2C_REGISTER_STS1: - return i2c->STS1; - case I2C_REGISTER_STS2: - return i2c->STS2; - case I2C_REGISTER_CLKCTRL: - return i2c->CLKCTRL; - case I2C_REGISTER_RISETMAX: - return i2c->RISETMAX; - case I2C_REGISTER_SWITCH: - return i2c->SWITCH; - default: - return 0; + case I2C_REGISTER_CTRL1: + return i2c->CTRL1; + case I2C_REGISTER_CTRL2: + return i2c->CTRL2; + case I2C_REGISTER_SADDR1: + return i2c->SADDR1; + case I2C_REGISTER_SADDR2: + return i2c->SADDR2; + case I2C_REGISTER_DATA: + return i2c->DATA; + case I2C_REGISTER_STS1: + return i2c->STS1; + case I2C_REGISTER_STS2: + return i2c->STS2; + case I2C_REGISTER_CLKCTRL: + return i2c->CLKCTRL; + case I2C_REGISTER_RISETMAX: + return i2c->RISETMAX; + case I2C_REGISTER_SWITCH: + return i2c->SWITCH; + default: + return 0; } } @@ -411,7 +412,7 @@ uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister) * * @retval None */ -void I2C_EnableSoftwareReset(I2C_T *i2c) +void I2C_EnableSoftwareReset(I2C_T* i2c) { i2c->CTRL1_B.SWRST = ENABLE; } @@ -423,7 +424,7 @@ void I2C_EnableSoftwareReset(I2C_T *i2c) * * @retval None */ -void I2C_DisableSoftwareReset(I2C_T *i2c) +void I2C_DisableSoftwareReset(I2C_T* i2c) { i2c->CTRL1_B.SWRST = DISABLE; } @@ -437,7 +438,7 @@ void I2C_DisableSoftwareReset(I2C_T *i2c) * * @retval None */ -void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition) +void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition) { if (NACKPosition == I2C_NACK_POSITION_NEXT) { @@ -460,7 +461,7 @@ void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition) * @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high * @retval None */ -void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState) +void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState) { if (SMBusState == I2C_SMBUSALER_LOW) { @@ -479,7 +480,7 @@ void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState) * * @retval None */ -void I2C_EnablePECTransmit(I2C_T *i2c) +void I2C_EnablePECTransmit(I2C_T* i2c) { i2c->CTRL1_B.PEC = BIT_SET; } @@ -491,7 +492,7 @@ void I2C_EnablePECTransmit(I2C_T *i2c) * * @retval None */ -void I2C_DisablePECTransmit(I2C_T *i2c) +void I2C_DisablePECTransmit(I2C_T* i2c) { i2c->CTRL1_B.PEC = BIT_RESET; } @@ -507,7 +508,7 @@ void I2C_DisablePECTransmit(I2C_T *i2c) * @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC * @retval None */ -void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition) +void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition) { if (PECPosition == I2C_PEC_POSITION_NEXT) { @@ -526,7 +527,7 @@ void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition) * * @retval None */ -void I2C_EnablePEC(I2C_T *i2c) +void I2C_EnablePEC(I2C_T* i2c) { i2c->CTRL1_B.PECEN = BIT_SET; } @@ -538,7 +539,7 @@ void I2C_EnablePEC(I2C_T *i2c) * * @retval None */ -void I2C_DisablePEC(I2C_T *i2c) +void I2C_DisablePEC(I2C_T* i2c) { i2c->CTRL1_B.PECEN = BIT_RESET; } @@ -550,7 +551,7 @@ void I2C_DisablePEC(I2C_T *i2c) * * @retval value of PEC */ -uint8_t I2C_ReadPEC(I2C_T *i2c) +uint8_t I2C_ReadPEC(I2C_T* i2c) { return i2c->STS2_B.PECVALUE; } @@ -562,7 +563,7 @@ uint8_t I2C_ReadPEC(I2C_T *i2c) * * @retval None */ -void I2C_EnableARP(I2C_T *i2c) +void I2C_EnableARP(I2C_T* i2c) { i2c->CTRL1_B.ARPEN = BIT_SET; } @@ -574,7 +575,7 @@ void I2C_EnableARP(I2C_T *i2c) * * @retval None */ -void I2C_DisableARP(I2C_T *i2c) +void I2C_DisableARP(I2C_T* i2c) { i2c->CTRL1_B.ARPEN = BIT_RESET; } @@ -586,7 +587,7 @@ void I2C_DisableARP(I2C_T *i2c) * * @retval None */ -void I2C_EnableStretchClock(I2C_T *i2c) +void I2C_EnableStretchClock(I2C_T* i2c) { i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET; } @@ -598,7 +599,7 @@ void I2C_EnableStretchClock(I2C_T *i2c) * * @retval None */ -void I2C_DisableStretchClock(I2C_T *i2c) +void I2C_DisableStretchClock(I2C_T* i2c) { i2c->CTRL1_B.CLKSTRETCHD = BIT_SET; } @@ -614,7 +615,7 @@ void I2C_DisableStretchClock(I2C_T *i2c) * @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2 * @retval None */ -void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle) +void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle) { if (dutyCycle == I2C_DUTYCYCLE_16_9) { @@ -633,7 +634,7 @@ void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle) * * @retval None */ -void I2C_EnableDMA(I2C_T *i2c) +void I2C_EnableDMA(I2C_T* i2c) { i2c->CTRL2_B.DMAEN = ENABLE; } @@ -645,7 +646,7 @@ void I2C_EnableDMA(I2C_T *i2c) * * @retval None */ -void I2C_DisableDMA(I2C_T *i2c) +void I2C_DisableDMA(I2C_T* i2c) { i2c->CTRL2_B.DMAEN = DISABLE; } @@ -657,7 +658,7 @@ void I2C_DisableDMA(I2C_T *i2c) * * @retval None */ -void I2C_EnableDMALastTransfer(I2C_T *i2c) +void I2C_EnableDMALastTransfer(I2C_T* i2c) { i2c->CTRL2_B.LTCFG = BIT_SET; } @@ -669,7 +670,7 @@ void I2C_EnableDMALastTransfer(I2C_T *i2c) * * @retval None */ -void I2C_DisableDMALastTransfer(I2C_T *i2c) +void I2C_DisableDMALastTransfer(I2C_T* i2c) { i2c->CTRL2_B.LTCFG = BIT_RESET; } @@ -687,7 +688,7 @@ void I2C_DisableDMALastTransfer(I2C_T *i2c) * * @retval None */ -void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt) +void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt) { i2c->CTRL2 |= interrupt; } @@ -705,7 +706,7 @@ void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt) * * @retval None */ -void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt) +void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt) { i2c->CTRL2 &= ~interrupt; } @@ -736,7 +737,7 @@ void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt) * * @retval Status: SUCCESS or ERROR */ -uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent) +uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; @@ -761,7 +762,7 @@ uint8_t I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent) * * @retval The last event */ -uint32_t I2C_ReadLastEvent(I2C_T *i2c) +uint32_t I2C_ReadLastEvent(I2C_T* i2c) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; @@ -806,77 +807,77 @@ uint32_t I2C_ReadLastEvent(I2C_T *i2c) * * @retval Status: flag SET or RESET */ -uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag) +uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) { uint8_t status = 0; switch (flag) { - case I2C_FLAG_DUALADDR: - status = i2c->STS2_B.DUALADDRFLG; - break; - case I2C_FLAG_SMMHADDR: - status = i2c->STS2_B.SMMHADDR; - break; - case I2C_FLAG_SMBDADDR: - status = i2c->STS2_B.SMBDADDRFLG; - break; - case I2C_FLAG_GENCALL: - status = i2c->STS2_B.GENCALLFLG; - break; - case I2C_FLAG_TR: - status = i2c->STS2_B.TRFLG; - break; - case I2C_FLAG_BUSBSY: - status = i2c->STS2_B.BUSBSYFLG; - break; - case I2C_FLAG_MS: - status = i2c->STS2_B.MSFLG; - break; - case I2C_FLAG_SMBALT: - status = i2c->STS1_B.SMBALTFLG; - break; - case I2C_FLAG_TTE: - status = i2c->STS1_B.TTEFLG; - break; - case I2C_FLAG_PECE: - status = i2c->STS1_B.PECEFLG; - break; - case I2C_FLAG_OVRUR: - status = i2c->STS1_B.OVRURFLG; - break; - case I2C_FLAG_AE: - status = i2c->STS1_B.AEFLG; - break; - case I2C_FLAG_AL: - status = i2c->STS1_B.ALFLG; - break; - case I2C_FLAG_BERR: - status = i2c->STS1_B.BERRFLG; - break; - case I2C_FLAG_TXBE: - status = i2c->STS1_B.TXBEFLG; - break; - case I2C_FLAG_RXBNE: - status = i2c->STS1_B.RXBNEFLG; - break; - case I2C_FLAG_STOP: - status = i2c->STS1_B.STOPFLG; - break; - case I2C_FLAG_ADDR10: - status = i2c->STS1_B.ADDR10FLG; - break; - case I2C_FLAG_BTC: - status = i2c->STS1_B.BTCFLG; - break; - case I2C_FLAG_ADDR: - status = i2c->STS1_B.ADDRFLG; - break; - case I2C_FLAG_START: - status = i2c->STS1_B.STARTFLG; - break; - default: - break; + case I2C_FLAG_DUALADDR: + status = i2c->STS2_B.DUALADDRFLG; + break; + case I2C_FLAG_SMMHADDR: + status = i2c->STS2_B.SMMHADDR; + break; + case I2C_FLAG_SMBDADDR: + status = i2c->STS2_B.SMBDADDRFLG; + break; + case I2C_FLAG_GENCALL: + status = i2c->STS2_B.GENCALLFLG; + break; + case I2C_FLAG_TR: + status = i2c->STS2_B.TRFLG; + break; + case I2C_FLAG_BUSBSY: + status = i2c->STS2_B.BUSBSYFLG; + break; + case I2C_FLAG_MS: + status = i2c->STS2_B.MSFLG; + break; + case I2C_FLAG_SMBALT: + status = i2c->STS1_B.SMBALTFLG; + break; + case I2C_FLAG_TTE: + status = i2c->STS1_B.TTEFLG; + break; + case I2C_FLAG_PECE: + status = i2c->STS1_B.PECEFLG; + break; + case I2C_FLAG_OVRUR: + status = i2c->STS1_B.OVRURFLG; + break; + case I2C_FLAG_AE: + status = i2c->STS1_B.AEFLG; + break; + case I2C_FLAG_AL: + status = i2c->STS1_B.ALFLG; + break; + case I2C_FLAG_BERR: + status = i2c->STS1_B.BERRFLG; + break; + case I2C_FLAG_TXBE: + status = i2c->STS1_B.TXBEFLG; + break; + case I2C_FLAG_RXBNE: + status = i2c->STS1_B.RXBNEFLG; + break; + case I2C_FLAG_STOP: + status = i2c->STS1_B.STOPFLG; + break; + case I2C_FLAG_ADDR10: + status = i2c->STS1_B.ADDR10FLG; + break; + case I2C_FLAG_BTC: + status = i2c->STS1_B.BTCFLG; + break; + case I2C_FLAG_ADDR: + status = i2c->STS1_B.ADDRFLG; + break; + case I2C_FLAG_START: + status = i2c->STS1_B.STARTFLG; + break; + default: + break; } return status; } @@ -914,33 +915,33 @@ uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag) * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) * followed by a write operation to I2C_DATA register (I2C_TxData()). */ -void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag) +void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) { switch (flag) { - case I2C_FLAG_SMBALT: - i2c->STS1_B.SMBALTFLG = BIT_RESET; - break; - case I2C_FLAG_TTE: - i2c->STS1_B.TTEFLG = BIT_RESET; - break; - case I2C_FLAG_PECE: - i2c->STS1_B.PECEFLG = BIT_RESET; - break; - case I2C_FLAG_OVRUR: - i2c->STS1_B.OVRURFLG = BIT_RESET; - break; - case I2C_FLAG_AE: - i2c->STS1_B.AEFLG = BIT_RESET; - break; - case I2C_FLAG_AL: - i2c->STS1_B.ALFLG = BIT_RESET; - break; - case I2C_FLAG_BERR: - i2c->STS1_B.BERRFLG = BIT_RESET; - break; - default: - break; + case I2C_FLAG_SMBALT: + i2c->STS1_B.SMBALTFLG = BIT_RESET; + break; + case I2C_FLAG_TTE: + i2c->STS1_B.TTEFLG = BIT_RESET; + break; + case I2C_FLAG_PECE: + i2c->STS1_B.PECEFLG = BIT_RESET; + break; + case I2C_FLAG_OVRUR: + i2c->STS1_B.OVRURFLG = BIT_RESET; + break; + case I2C_FLAG_AE: + i2c->STS1_B.AEFLG = BIT_RESET; + break; + case I2C_FLAG_AL: + i2c->STS1_B.ALFLG = BIT_RESET; + break; + case I2C_FLAG_BERR: + i2c->STS1_B.BERRFLG = BIT_RESET; + break; + default: + break; } } @@ -968,7 +969,7 @@ void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag) * * @retval Status: flag SET or RESET */ -uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag) +uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) { uint32_t enablestatus = 0; @@ -1014,11 +1015,11 @@ uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag) * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) * followed by a write operation to I2C_DATA register (I2C_TxData()). */ -void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag) +void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag) { i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF); } -/**@} end of group I2C_Fuctions*/ +/**@} end of group I2C_Functions*/ /**@} end of group I2C_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c index d3d64748a0..bd455c6147 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c @@ -3,9 +3,9 @@ * * @brief This file provides all the IWDT firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,9 +23,10 @@ * and limitations under the License. */ +/* Includes */ #include "apm32f10x_iwdt.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -33,7 +34,7 @@ @{ */ -/** @addtogroup IWDT_Fuctions Fuctions +/** @defgroup IWDT_Functions Functions @{ */ @@ -143,6 +144,6 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag) return bitStatus; } -/**@} end of group IWDT_Fuctions*/ -/**@} end of group IWDT_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group IWDT_Functions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c index e642f786bd..61f62d5ec3 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c @@ -4,9 +4,9 @@ * @brief This file provides all the miscellaneous firmware functions. * Include NVIC,SystemTick and Power management. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -16,7 +16,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -24,9 +24,10 @@ * and limitations under the License. */ +/* Includes */ #include "apm32f10x_misc.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ @@ -34,7 +35,7 @@ @{ */ -/** @addtogroup MISC_Macros Macros +/** @defgroup MISC_Macros Macros @{ */ @@ -43,7 +44,7 @@ /**@} end of group MISC_Macros*/ -/** @addtogroup MISC_Fuctions Fuctions +/** @defgroup MISC_Functions Functions @{ */ @@ -82,42 +83,42 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su uint32_t tempPriority, tempPrePri, tempSubPri; uint32_t priorityGrp; - /** Get priority group */ + /* Get priority group */ priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U; - /** get pre-emption priority and subpriority */ + /* get pre-emption priority and subpriority */ switch (priorityGrp) { - case NVIC_PRIORITY_GROUP_0: - tempPrePri = 0; - tempSubPri = 4; - break; + case NVIC_PRIORITY_GROUP_0: + tempPrePri = 0; + tempSubPri = 4; + break; - case NVIC_PRIORITY_GROUP_1: - tempPrePri = 1; - tempSubPri = 3; - break; + case NVIC_PRIORITY_GROUP_1: + tempPrePri = 1; + tempSubPri = 3; + break; - case NVIC_PRIORITY_GROUP_2: - tempPrePri = 2; - tempSubPri = 2; - break; + case NVIC_PRIORITY_GROUP_2: + tempPrePri = 2; + tempSubPri = 2; + break; - case NVIC_PRIORITY_GROUP_3: - tempPrePri = 3; - tempSubPri = 1; - break; + case NVIC_PRIORITY_GROUP_3: + tempPrePri = 3; + tempSubPri = 1; + break; - case NVIC_PRIORITY_GROUP_4: - tempPrePri = 4; - tempSubPri = 0; - break; + case NVIC_PRIORITY_GROUP_4: + tempPrePri = 4; + tempSubPri = 0; + break; - default: - NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0); - tempPrePri = 0; - tempSubPri = 4; - break; + default: + NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0); + tempPrePri = 0; + tempSubPri = 4; + break; } tempPrePri = 4 - tempPrePri; @@ -127,7 +128,7 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su tempPriority <<= 4; NVIC->IP[irq] = (uint8_t)tempPriority; - /** enable the selected IRQ */ + /* enable the selected IRQ */ NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); } @@ -140,7 +141,7 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su */ void NVIC_DisableIRQRequest(IRQn_Type irq) { - /** disable the selected IRQ.*/ + /* disable the selected IRQ.*/ NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); } @@ -215,6 +216,6 @@ void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource) } } -/**@} end of group MISC_Fuctions*/ -/**@} end of group MISC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group MISC_Functions*/ +/**@} end of group MISC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c index c57ff98cec..9c5d8d506b 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c @@ -3,9 +3,9 @@ * * @brief This file provides all the PMU firmware functions. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,18 +23,19 @@ * and limitations under the License. */ +/* Includes */ #include "apm32f10x_pmu.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup PMU_Driver PMU Driver +/** @addtogroup PMU_Driver PMU Driver @{ */ -/** @addtogroup PMU_Fuctions Fuctions +/** @defgroup PMU_Functions Functions @{ */ @@ -102,7 +103,7 @@ void PMU_DisablePVD(void) /*! * @brief Configure a voltage threshold detected by a power supply voltage detector (PVD). * - * @param level£ºspecifies the PVD detection level + * @param levelspecifies the PVD detection level * This parameter can be one of the following values: * @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V * @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V @@ -118,9 +119,9 @@ void PMU_DisablePVD(void) void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level) { - /** Clear PLS[7:5] bits */ + /* Clear PLS[7:5] bits */ PMU->CTRL_B.PLSEL = 0x0000; - /** Store the new value */ + /* Store the new value */ PMU->CTRL_B.PLSEL = level; } @@ -165,26 +166,26 @@ void PMU_DisableWakeUpPin(void) */ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) { - /** Clear PDDSCFG and LPDSCFG bits */ + /* Clear PDDSCFG and LPDSCFG bits */ PMU->CTRL_B.PDDSCFG = 0x00; PMU->CTRL_B.LPDSCFG = 0x00; - /** Set LPDSCFG bit according to regulator value */ + /* Set LPDSCFG bit according to regulator value */ PMU->CTRL_B.LPDSCFG = regulator; - /** Set Cortex System Control Register */ + /* Set Cortex System Control Register */ SCB->SCR |= (uint32_t)0x04; - /** Select STOP mode entry*/ + /* Select STOP mode entry*/ if (entry == PMU_STOP_ENTRY_WFI) { - /** Request Wait For Interrupt */ + /* Request Wait For Interrupt */ __WFI(); } else { - /** Request Wait For Event */ + /* Request Wait For Event */ __WFE(); } - /** Reset SLEEPDEEP bit of Cortex System Control Register */ + /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)0x04); } @@ -197,16 +198,16 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) */ void PMU_EnterSTANDBYMode(void) { - /** Clear Wake-up flag */ + /* Clear Wake-up flag */ PMU->CTRL_B.WUFLGCLR = BIT_SET; - /** Select STANDBY mode */ + /* Select STANDBY mode */ PMU->CTRL_B.PDDSCFG = BIT_SET; - /** Set Cortex System Control Register */ + /* Set Cortex System Control Register */ SCB->SCR |= (uint32_t)0x04; #if defined ( __CC_ARM ) __force_stores(); #endif - /** Request Wait For Interrupt */ + /* Request Wait For Interrupt */ __WFI(); } @@ -214,7 +215,7 @@ void PMU_EnterSTANDBYMode(void) /*! * @brief Read the specified PWR flag is set or not. * - * @param flag£ºReads the status of specifies the flag. + * @param flagReads the status of specifies the flag. * This parameter can be one of the following values: * @arg PMU_FLAG_WUE : Wake Up flag * @arg PMU_FLAG_SB : StandBy flag @@ -244,7 +245,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) /*! * @brief Clears the PWR's pending flags. * - * @param flag£ºClears the status of specifies the flag. + * @param flagClears the status of specifies the flag. * This parameter can be one of the following values: * @arg PMU_FLAG_WUE : Wake Up flag * @arg PMU_FLAG_SB : StandBy flag @@ -263,6 +264,6 @@ void PMU_ClearStatusFlag(PMU_FLAG_T flag) } } -/**@} end of group PMU_Fuctions*/ -/**@} end of group PMU_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group PMU_Functions*/ +/**@} end of group PMU_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c index 2e3b694aa0..405301db8c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c @@ -3,9 +3,9 @@ * * @brief This file contains all the functions for the QSPI peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,18 +23,19 @@ * and limitations under the License. */ +/* Includes */ #if defined (APM32F10X_MD) || defined (APM32F10X_LD) #include "apm32f10x_qspi.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup QSPI_Driver QSPI Driver +/** @addtogroup QSPI_Driver QSPI Driver @{ */ -/** @addtogroup QSPI_Fuctions Fuctions +/** @defgroup QSPI_Functions Functions @{ */ @@ -73,7 +74,7 @@ void QSPI_Reset(void) * * @retval None */ -void QSPI_Config(QSPI_Config_T *qspiConfig) +void QSPI_Config(QSPI_Config_T* qspiConfig) { QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase; QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity; @@ -91,7 +92,7 @@ void QSPI_Config(QSPI_Config_T *qspiConfig) * * @retval None */ -void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig) +void QSPI_ConfigStructInit(QSPI_Config_T* qspiConfig) { qspiConfig->clockPhase = QSPI_CLKPHA_2EDGE; qspiConfig->clockPolarity = QSPI_CLKPOL_LOW; @@ -602,8 +603,8 @@ void QSPI_ClearIntFlag(uint32_t flag) dummy = QSPI->MIC; } } -#endif //defined APM32F10X_MD/LD -/**@} end of group QSPI_Fuctions*/ -/**@} end of group QSPI_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group QSPI_Functions*/ +/**@} end of group QSPI_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver*/ +#endif //defined APM32F10X_MD/LD diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c index ac2db4e3f8..a90abbd0ad 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c @@ -3,9 +3,9 @@ * * @brief This file provides all the RCM firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,20 +25,21 @@ #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup RCM_Driver RCM Driver + * @brief RCM driver modules @{ */ -/** @addtogroup RCM_Fuctions Fuctions +/** @defgroup RCM_Functions Functions @{ */ /*! - * @brief Resets the clock configuration to the default state + * @brief Reset the clock configuration to the default state * * @param None * @@ -46,22 +47,40 @@ */ void RCM_Reset(void) { - /** Open HSI clock */ + /* Open HSI clock */ RCM->CTRL_B.HSIEN = BIT_SET; - /** Config HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + /* Configures HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ +#if defined(APM32F10X_CL) + RCM->CFG &= (uint32_t)0xF0FF0000; +#else RCM->CFG &= (uint32_t)0xF8FF0000; - /** Reset HSEEN, CSSEN and PLLEN bits */ +#endif + + /* Reset HSEEN, CSSEN and PLLEN bits */ RCM->CTRL &= (uint32_t)0xFEF6FFFF; - /** Reset HSEBCFG bit */ + /* Reset HSEBCFG bit */ RCM->CTRL_B.HSEBCFG = BIT_RESET; - /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ + /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ RCM->CFG &= (uint32_t)0xFF00FFFF; - /** Disable all interrupts and clear pending bits */ + +#if defined(APM32F10X_CL) + /* Reset PLL2EN and PLL3EN bits */ + RCM->CTRL_B.PLL2EN = BIT_RESET; + RCM->CTRL_B.PLL3EN = BIT_RESET; + + /* Disable all interrupts and clear pending bits */ + RCM->INT = 0x00FF0000; + + /* Reset CFG2 register */ + RCM->CFG2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ RCM->INT = 0x009F0000; +#endif } /*! - * @brief Configs the HSE oscillator + * @brief Configures the HSE oscillator * * @param state: state of the HSE * This parameter can be one of the following values: @@ -75,10 +94,10 @@ void RCM_Reset(void) */ void RCM_ConfigHSE(RCM_HSE_T state) { - /** Reset HSEEN bit */ + /* Reset HSEEN bit */ RCM->CTRL_B.HSEEN = BIT_RESET; - /** Reset HSEBCFG bit */ + /* Reset HSEBCFG bit */ RCM->CTRL_B.HSEBCFG = BIT_RESET; if (state == RCM_HSE_OPEN) @@ -93,7 +112,7 @@ void RCM_ConfigHSE(RCM_HSE_T state) } /*! - * @brief Waits for HSE to be ready + * @brief Wait for HSE to be ready * * @param None * @@ -116,7 +135,7 @@ uint8_t RCM_WaitHSEReady(void) } /*! - * @brief Config HSI trimming value + * @brief Configures HSI trimming value * * @param HSITrim: HSI trimming value * This parameter must be a number between 0 and 0x1F. @@ -183,7 +202,7 @@ void RCM_ConfigLSE(RCM_LSE_T state) } /*! - * @brief Enables the Internal Low Speed oscillator (LSI) + * @brief Enable the Internal Low Speed oscillator (LSI) * * @param None * @@ -195,7 +214,7 @@ void RCM_EnableLSI(void) } /*! - * @brief Disables the Internal Low Speed oscillator (LSI) + * @brief Disable the Internal Low Speed oscillator (LSI) * * @param None * @@ -207,16 +226,30 @@ void RCM_DisableLSI(void) } /*! - * @brief Configs the PLL clock source and multiplication factor + * @brief Configures the PLL clock source and multiplication factor * - * @param pllSelect: PLL entry clock source select - * This parameter can be one of the following values: - * @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source - * @arg RCM_PLLSEL_HSE: HSE clock selected as PLL clock source - * @arg RCM_PLLSEL_HSE_DIV2: HSE clock divided by 2 selected as PLL clock source + * @param pllSelect: PLL entry clock source select + * This parameter can be one of the following values: + * For APM32F105xx and APM32F107xx devices: + * @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source + * @arg RCM_PLLSEL_PREDIV1 : PLL prescaler 1 clock selected as PLL clock source + * For other devices: + * @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source + * @arg RCM_PLLSEL_HSE : HSE clock selected as PLL clock source + * @arg RCM_PLLSEL_HSE_DIV2 : HSE clock divided by 2 selected as PLL clock source * - * @param pllMf: PLL multiplication factor - * This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16. + * @param pllMf: PLL multiplication factor + * For APM32F105xx and APM32F107xx devices: + * This parameter can be one of the following values: + * @arg RCM_PLLMF_4 : PLL Multiplication Factor Configures to 4 + * @arg RCM_PLLMF_5 : PLL Multiplication Factor Configures to 5 + * @arg RCM_PLLMF_6 : PLL Multiplication Factor Configures to 6 + * @arg RCM_PLLMF_7 : PLL Multiplication Factor Configures to 7 + * @arg RCM_PLLMF_8 : PLL Multiplication Factor Configures to 8 + * @arg RCM_PLLMF_9 : PLL Multiplication Factor Configures to 9 + * @arg RCM_PLLMF_6_5: PLL Multiplication Factor Configures to 6.5 + * For other devices: + * This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16. * * @retval None * @@ -224,13 +257,16 @@ void RCM_DisableLSI(void) */ void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf) { - RCM->CFG_B.PLLMULCFG = pllMf; - RCM->CFG_B.PLLSRCSEL = pllSelect & 0x01; + RCM->CFG_B.PLL1MULCFG = pllMf; + RCM->CFG_B.PLL1SRCSEL = pllSelect & 0x01; + +#ifndef APM32F10X_CL RCM->CFG_B.PLLHSEPSC = (pllSelect >> 1) & 0x01; +#endif } /*! - * @brief Enables the PLL + * @brief Enable the PLL * * @param None * @@ -238,23 +274,139 @@ void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf) */ void RCM_EnablePLL(void) { - RCM->CTRL_B.PLLEN = BIT_SET; + RCM->CTRL_B.PLL1EN = BIT_SET; } /*! -* @brief Disable the PLL -* -* @param None -* -* @retval None -* -* @note When PLL is not used as system clock, it can be stopped. -*/ + * @brief Disable the PLL + * + * @param None + * + * @retval None + * + * @note When PLL is not used as system clock, it can be stopped. + */ void RCM_DisablePLL(void) { - RCM->CTRL_B.PLLEN = BIT_RESET; + RCM->CTRL_B.PLL1EN = BIT_RESET; } +#if defined(APM32F10X_CL) +/*! + * @brief Enable the PLL2 + * + * @param None + * + * @retval None + */ +void RCM_EnablePLL2(void) +{ + RCM->CTRL_B.PLL2EN = BIT_SET; +} + +/*! + * @brief Disable the PLL2 + * + * @param None + * + * @retval None + */ +void RCM_DisablePLL2(void) +{ + RCM->CTRL_B.PLL2EN = BIT_RESET; +} + +/*! + * @brief Enable the PLL3 + * + * @param None + * + * @retval None + */ +void RCM_EnablePLL3(void) +{ + RCM->CTRL_B.PLL3EN = BIT_SET; +} + +/*! + * @brief Disable the PLL3 + * + * @param None + * + * @retval None + */ +void RCM_DisablePLL3(void) +{ + RCM->CTRL_B.PLL3EN = BIT_RESET; +} + +/*! + * @brief Configures the PLL prescaler 1 factor. + * + * @param pllPsc1Src: PLL prescaler 1 source select + * This parameter can be one of the following values: + * @arg RCM_PLLPSC1_SRC_HSE : HSE clock selected as PLL prescaler 1 clock source + * @arg RCM_PLLPSC1_SRC_PLL2: PLL2 clock selected as PLL prescaler 1 clock source + * + * @param pllPsc1: PLL prescaler 1 factor + * This parameter can be RCM_PLLPSC1_DIV_x where x can be a value from 1 to 16. + * + * @retval None + * + * @note PLL should be disabled while use this function. + */ +void RCM_ConfigPLLPSC1(RCM_PLLPSC1_SRC_T pllPsc1Src, RCM_PLLPSC1_DIV_T pllPsc1) +{ + RCM->CFG2_B.PLLPSC1SRC = pllPsc1Src; + RCM->CFG2_B.PLLPSC1 = pllPsc1; +} + +/*! + * @brief Configures the PLL prescaler 2 factor. + * + * @param pllpsc2: PLL prescaler 2 factor + * This parameter can be RCM_PLLPSC2_DIV_x where x can be a value from 1 to 16. + * + * @retval None + * + * @note PLL2 and PLL3 should be disabled while use this function. + */ +void RCM_ConfigPLLPSC2(RCM_PLLPSC2_DIV_T pllpsc2) +{ + RCM->CFG2_B.PLLPSC2 = pllpsc2; +} + +/*! + * @brief Configures the PLL2 clock multiplication factor + * + * @param pll2Mf: PLL2 multiplication factor + * This parameter can be RCM_PLL2MF_x where x can be a value from 8 to 14, and 16, 20. + * + * @retval None + * + * @note PLL2 should be disabled while use this function. + */ +void RCM_ConfigPLL2(RCM_PLL2MF_T pll2Mf) +{ + RCM->CFG2_B.PLL2MUL = pll2Mf; +} + +/*! + * @brief Configures the PLL3 clock multiplication factor + * + * @param pll3Mf: PLL3 multiplication factor + * This parameter can be RCM_PLL3MF_x where x can be a value from 8 to 14, and 16, 20. + * + * @retval None + * + * @note PLL3 should be disabled while use this function. + */ +void RCM_ConfigPLL3(RCM_PLL3MF_T pll3Mf) +{ + RCM->CFG2_B.PLL3MUL = pll3Mf; +} +#endif + /*! * @brief Enable the Clock Security System * @@ -280,15 +432,20 @@ void RCM_DisableCSS(void) } /*! - * @brief Selects the MCO pin clock ouput source + * @brief Select the MCO pin clock output source * * @param mcoClock: specifies the clock source to output * This parameter can be one of the following values: - * @arg RCM_MCOCLK_NO_CLOCK : No clock selected. - * @arg RCM_MCOCLK_SYSCLK : System clock selected. - * @arg RCM_MCOCLK_HSI : HSI oscillator clock selected. - * @arg RCM_MCOCLK_HSE : HSE oscillator clock selected. - * @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected. + * @arg RCM_MCOCLK_NO_CLOCK : No clock selected. + * @arg RCM_MCOCLK_SYSCLK : System clock selected. + * @arg RCM_MCOCLK_HSI : HSI oscillator clock selected. + * @arg RCM_MCOCLK_HSE : HSE oscillator clock selected. + * @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected. + * The following values is only for APM32F105xx or APM32F107xx: + * @arg RCM_MCOCLK_PLL2CLK : PLL2 clock selected. + * @arg RCM_MCOCLK_PLL3CLK_DIV_2 : PLL3 clock divided by 2 selected. + * @arg RCM_MCOCLK_OSCCLK : OSC clock selected. + * @arg RCM_MCOCLK_PLL3CLK : PLL3 clock selected. * * @retval None */ @@ -306,7 +463,7 @@ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock) * @arg RCM_SYSCLK_SEL_HSE: HSE is selected as system clock source * @arg RCM_SYSCLK_SEL_PLL: PLL is selected as system clock source * - * @retva None + * @retval None */ void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) { @@ -314,7 +471,7 @@ void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) } /*! - * @brief Returns the clock source which is used as system clock + * @brief Return the clock source which is used as system clock * * @param None * @@ -326,7 +483,7 @@ RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void) } /*! - * @brief Configs the AHB clock prescaler. + * @brief Configures the AHB clock prescaler. * * @param AHBDiv : Specifies the AHB clock prescaler from the system clock. * This parameter can be one of the following values: @@ -348,7 +505,7 @@ void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv) } /*! - * @brief Configs the APB1 clock prescaler. + * @brief Configures the APB1 clock prescaler. * * @param APB1Div: Specifies the APB1 clock prescaler from the AHB clock. * This parameter can be one of the following values: @@ -366,7 +523,7 @@ void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div) } /*! - * @brief Configs the APB2 clock prescaler + * @brief Configures the APB2 clock prescaler * * @param APB2Div: Specifies the APB2 clock prescaler from the AHB clock. * This parameter can be one of the following values: @@ -383,8 +540,58 @@ void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div) RCM->CFG_B.APB2PSC = APB2Div; } +#if defined(APM32F10X_CL) /*! - * @brief Configs the USB clock prescaler + * @brief Configures the I2S2 clock source. + * + * @param i2s2ClkSelect: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCM_I2S2CLK_SYSCLK : I2S2CLK = System clock + * @arg RCM_I2S2CLK_DOUBLE_PLL3: I2S2CLK = Double PLL3 clock + * + * @retval None + * + * @note I2S2 clock source should be changed when I2S2 Clock is disabled. + */ +void RCM_ConfigI2S2CLK(RCM_I2S2CLK_T i2s2ClkSelect) +{ + RCM->CFG2_B.I2S2SRCSEL = i2s2ClkSelect; +} + +/*! + * @brief Configures the I2S3 clock source. + * + * @param i2s3ClkSelect: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCM_I2S3CLK_SYSCLK : I2S3CLK = System clock + * @arg RCM_I2S3CLK_DOUBLE_PLL3: I2S3CLK = Double PLL3 clock + * + * @retval None + * + * @note I2S3 clock source should be changed when I2S3 Clock is disabled. + */ +void RCM_ConfigI2S3CLK(RCM_I2S2CLK_T i2s3ClkSelect) +{ + RCM->CFG2_B.I2S3SRCSEL = i2s3ClkSelect; +} + +/*! + * @brief Configures the OTG FS clock prescaler + * + * @param OTGDiv: Specifies the OTG FS clock prescaler from the PLL clock. + * This parameter can be one of the following values: + * @arg RCM_OTGFS_DIV_1_5 : OTGFSCLK = PLL clock /1.5 + * @arg RCM_OTGFS_DIV_1 : OTGFSCLK = PLL clock + * + * @retval None + */ +void RCM_ConfigOTGFSCLK(RCM_OTGFS_DIV_T OTGDiv) +{ + RCM->CFG_B.OTGFSPSC = OTGDiv; +} +#else +/*! + * @brief Configures the USB clock prescaler * * @param USBDiv: Specifies the USB clock prescaler from the PLL clock. * This parameter can be one of the following values: @@ -401,7 +608,7 @@ void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv) } /*! - * @brief Configs the FPU clock prescaler + * @brief Configures the FPU clock prescaler * * @param FPUDiv: Specifies the FPU clock prescaler from the AHB clock. * This parameter can be one of the following values: @@ -414,9 +621,11 @@ void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv) { RCM->CFG_B.FPUPSC = FPUDiv; } +#endif + /*! - * @brief Configs the ADC clock prescaler + * @brief Configures the ADC clock prescaler * * @param ADCDiv : Specifies the ADC clock prescaler from the APB2 clock. * This parameter can be one of the following values: @@ -443,7 +652,7 @@ void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv) * * @retval None * - * @note Once the RTC clock is configed it can't be changed unless reset the Backup domain. + * @note Once the RTC clock is configured it can't be changed unless reset the Backup domain. */ void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect) { @@ -451,7 +660,7 @@ void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect) } /*! - * @brief Enables the RTC clock + * @brief Enable the RTC clock * * @param None * @@ -463,7 +672,7 @@ void RCM_EnableRTCCLK(void) } /*! - * @brief Disables the RTC clock + * @brief Disable the RTC clock * * @param None * @@ -475,7 +684,7 @@ void RCM_DisableRTCCLK(void) } /*! - * @brief Reads the frequency of SYSCLK + * @brief Read the frequency of SYSCLK * * @param None * @@ -483,57 +692,102 @@ void RCM_DisableRTCCLK(void) */ uint32_t RCM_ReadSYSCLKFreq(void) { +#ifdef APM32F10X_CL + uint32_t sysClock, pllMull, pllSource, pll2Mull, pllPsc1, pllPsc2; +#else uint32_t sysClock, pllMull, pllSource; +#endif - /** get sys clock */ + /* get sys clock */ sysClock = RCM->CFG_B.SCLKSEL; switch (sysClock) { - /** sys clock is HSI */ - case RCM_SYSCLK_SEL_HSI: - sysClock = HSI_VALUE; - break; + /* sys clock is HSI */ + case RCM_SYSCLK_SEL_HSI: + sysClock = HSI_VALUE; + break; - /** sys clock is HSE */ - case RCM_SYSCLK_SEL_HSE: - sysClock = HSE_VALUE; - break; + /* sys clock is HSE */ + case RCM_SYSCLK_SEL_HSE: + sysClock = HSE_VALUE; + break; - /** sys clock is PLL */ - case RCM_SYSCLK_SEL_PLL: - pllMull = RCM->CFG_B.PLLMULCFG + 2; - pllSource = RCM->CFG_B.PLLSRCSEL; + /* sys clock is PLL */ + case RCM_SYSCLK_SEL_PLL: +#ifdef APM32F10X_CL + /* NOTE : PLL is the same as PLL1 */ + pllSource = RCM->CFG_B.PLL1SRCSEL; - /** PLL entry clock source is HSE */ - if (pllSource == BIT_SET) - { - sysClock = HSE_VALUE * pllMull; - - /** HSE clock divided by 2 */ - if (pllSource == RCM->CFG_B.PLLHSEPSC) + /* PLL entry clock source is HSE */ + if (pllSource) { - sysClock >>= 1; + /* PLLPSC1 prescaler factor */ + pllPsc1 = (RCM->CFG2_B.PLLPSC1 + 1); + + /* PLL entry clock source is PLL2 */ + if (RCM->CFG2_B.PLLPSC1SRC) + { + pll2Mull = (RCM->CFG2_B.PLL2MUL != 15) ? (RCM->CFG2_B.PLL2MUL + 2) : 20; + pllPsc2 = RCM->CFG2_B.PLLPSC2 + 1; + + pllSource = ((HSE_VALUE / pllPsc2) * pll2Mull) / pllPsc1; + } + /* PLL entry clock source is HSE */ + else + { + pllSource = HSE_VALUE / pllPsc1; + } + } + /* PLL entry clock source is HSI/2 */ + else + { + pllSource = HSI_VALUE >> 1; } - } - /** PLL entry clock source is HSI/2 */ - else - { - sysClock = (HSI_VALUE >> 1) * pllMull; - } - break; + pllMull = RCM->CFG_B.PLL1MULCFG; + if (pllMull == 13) + { + /* For 6.5 multiplication factor */ + sysClock = pllSource * pllMull / 2; + } + else + { + sysClock = pllSource * (pllMull + 2); + } +#else + pllMull = RCM->CFG_B.PLL1MULCFG + 2; + pllSource = RCM->CFG_B.PLL1SRCSEL; - default: - sysClock = HSI_VALUE; - break; + /* PLL entry clock source is HSE */ + if (pllSource == BIT_SET) + { + sysClock = HSE_VALUE * pllMull; + + /* HSE clock divided by 2 */ + if (pllSource == RCM->CFG_B.PLLHSEPSC) + { + sysClock >>= 1; + } + } + /* PLL entry clock source is HSI/2 */ + else + { + sysClock = (HSI_VALUE >> 1) * pllMull; + } +#endif + break; + + default: + sysClock = HSI_VALUE; + break; } return sysClock; } /*! - * @brief Reads the frequency of HCLK(AHB) + * @brief Read the frequency of HCLK(AHB) * * @param None * @@ -553,7 +807,7 @@ uint32_t RCM_ReadHCLKFreq(void) } /*! - * @brief Reads the frequency of PCLK1 And PCLK2 + * @brief Read the frequency of PCLK1 And PCLK2 * * @param PCLK1 : Return the frequency of PCLK1 * @@ -561,7 +815,7 @@ uint32_t RCM_ReadHCLKFreq(void) * * @retval None */ -void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2) +void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2) { uint32_t hclk, divider; uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; @@ -582,7 +836,7 @@ void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2) } /*! - * @brief Reads the frequency of ADCCLK + * @brief Read the frequency of ADCCLK * * @param None * @@ -595,7 +849,7 @@ uint32_t RCM_ReadADCCLKFreq(void) RCM_ReadPCLKFreq(NULL, &pclk2); - /** Get ADC CLK */ + /* Get ADC CLK */ divider = ADCPrescTable[RCM->CFG_B.ADCPSC]; adcClk = pclk2 / divider; @@ -603,19 +857,23 @@ uint32_t RCM_ReadADCCLKFreq(void) } /*! - * @brief Enables AHB peripheral clock. + * @brief Enable AHB peripheral clock. * * @param AHBPeriph : Enable the specifies clock of AHB peripheral. * This parameter can be any combination of the following values: - * @arg RCM_AHB_PERIPH_DMA1 : Enable DMA1 clock - * @arg RCM_AHB_PERIPH_DMA2 : Enable DMA2 clock (Only for High-density devices for APM32F103xx) - * @arg RCM_AHB_PERIPH_SRAM : Enable SRAM clock - * @arg RCM_AHB_PERIPH_FPU : Enable FPU clock - * @arg RCM_AHB_PERIPH_FMC : Enable FMC clock - * @arg RCM_AHB_PERIPH_QSPI : Enable QSPI clock - * @arg RCM_AHB_PERIPH_CRC : Enable CRC clock - * @arg RCM_AHB_PERIPH_EMMC : Enable EMMC clock (Only for High-density devices for APM32F103xx) - * @arg RCM_AHB_PERIPH_SDIO : Enable SDIO clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_DMA1 : Enable DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2 : Enable DMA2 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SRAM : Enable SRAM clock + * @arg RCM_AHB_PERIPH_FPU : Enable FPU clock + * @arg RCM_AHB_PERIPH_FMC : Enable FMC clock + * @arg RCM_AHB_PERIPH_QSPI : Enable QSPI clock + * @arg RCM_AHB_PERIPH_CRC : Enable CRC clock + * @arg RCM_AHB_PERIPH_EMMC : Enable EMMC clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SDIO : Enable SDIO clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_OTG_FS : Enable OTG FS clock (Only for APM32F105xx or APM32F107xx) + * @arg RCM_AHB_PERIPH_ETH_MAC : Enable Ethernet MAC clock (Only for APM32F105xx or APM32F107xx) + * @arg RCM_AHB_PERIPH_ETH_MAC_TX : Enable Ethernet MAC TX clock (Only for APM32F105xx or APM32F107xx) + * @arg RCM_AHB_PERIPH_ETH_MAC_RX : Enable Ethernet MAC RX clock (Only for APM32F105xx or APM32F107xx) * * @retval None */ @@ -627,17 +885,21 @@ void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph) /*! * @brief Disable AHB peripheral clock. * - * @param AHBPeriph : Disable the specifies clock of AHB peripheral. + * @param AHBPeriph : Enable the specifies clock of AHB peripheral. * This parameter can be any combination of the following values: - * @arg RCM_AHB_PERIPH_DMA1 : Disable DMA1 clock - * @arg RCM_AHB_PERIPH_DMA2 : Disable DMA2 clock (Only for High-density devices for APM32F103xx) - * @arg RCM_AHB_PERIPH_SRAM : Disable SRAM clock - * @arg RCM_AHB_PERIPH_FPU : Disable FPU clock - * @arg RCM_AHB_PERIPH_FMC : Disable FMC clock - * @arg RCM_AHB_PERIPH_QSPI : Disable QSPI clock - * @arg RCM_AHB_PERIPH_CRC : Disable CRC clock - * @arg RCM_AHB_PERIPH_EMMC : Disable EMMC clock (Only for High-density devices for APM32F103xx) - * @arg RCM_AHB_PERIPH_SDIO : Disable SDIO clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_DMA1 : Disable DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2 : Disable DMA2 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SRAM : Disable SRAM clock + * @arg RCM_AHB_PERIPH_FPU : Disable FPU clock + * @arg RCM_AHB_PERIPH_FMC : Disable FMC clock + * @arg RCM_AHB_PERIPH_QSPI : Disable QSPI clock + * @arg RCM_AHB_PERIPH_CRC : Disable CRC clock + * @arg RCM_AHB_PERIPH_EMMC : Disable EMMC clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SDIO : Disable SDIO clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_OTG_FS : Disable OTG FS clock (Only for APM32F105xx or APM32F107xx) + * @arg RCM_AHB_PERIPH_ETH_MAC : Disable Ethernet MAC clock (Only for APM32F105xx or APM32F107xx) + * @arg RCM_AHB_PERIPH_ETH_MAC_TX : Disable Ethernet MAC TX clock (Only for APM32F105xx or APM32F107xx) + * @arg RCM_AHB_PERIPH_ETH_MAC_RX : Disable Ethernet MAC RX clock (Only for APM32F105xx or APM32F107xx) * * @retval None */ @@ -770,6 +1032,36 @@ void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph) RCM->APB1CLKEN &= (uint32_t)~APB1Periph; } +#if defined(APM32F10X_CL) +/*! + * @brief Enable AHB peripheral reset + * + * @param AHBPeriph : Enable specifies AHB peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_OTG_FS : Enable OTG FS reset + * @arg RCM_AHB_PERIPH_ETH_MAC : Enable ETH MAC reset * + * @retval None + */ +void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph) +{ + RCM->AHBRST |= AHBPeriph; +} + +/*! + * @brief Disable AHB peripheral reset + * + * @param AHBPeriph : Disable specifies AHB peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_OTG_FS : Disable OTG FS reset + * @arg RCM_AHB_PERIPH_ETH_MAC : Disable ETH MAC reset * + * @retval None + */ +void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph) +{ + RCM->AHBRST &= (uint32_t)~AHBPeriph; +} +#endif + /*! * @brief Enable High Speed APB (APB2) peripheral reset * @@ -929,6 +1221,8 @@ void RCM_DisableBackupReset(void) * @arg RCM_INT_HSIRDY : HSI ready interrupt * @arg RCM_INT_HSERDY : HSE ready interrupt * @arg RCM_INT_PLLRDY : PLL ready interrupt + * @arg RCM_INT_PLL2RDY: PLL2 ready interrupt + * @arg RCM_INT_PLL3RDY: PLL3 ready interrupt * * @retval None */ @@ -966,11 +1260,13 @@ void RCM_DisableInterrupt(uint32_t interrupt) /*! * @brief Read the specified RCM flag status * - * @param flag : Returns specifies the flag status. + * @param flag : Return specifies the flag status. * This parameter can be one of the following values: * @arg RCM_FLAG_HSIRDY : HSI ready flag * @arg RCM_FLAG_HSERDY : HSE ready flag * @arg RCM_FLAG_PLLRDY : PLL ready flag + * @arg RCM_FLAG_PLL2RDY : PLL2 ready flag (Only for APM32F105xx or APM32F107xx) + * @arg RCM_FLAG_PLL3RDY : PLL3 ready flag (Only for APM32F105xx or APM32F107xx) * @arg RCM_FLAG_LSERDY : LSE ready flag * @arg RCM_FLAG_LSIRDY : LSI ready flag * @arg RCM_FLAG_PINRST : NRST PIN Reset Occur Flag @@ -992,20 +1288,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag) switch (reg) { - case 0: - reg = RCM->CTRL; - break; + case 0: + reg = RCM->CTRL; + break; - case 1: - reg = RCM->BDCTRL; - break; + case 1: + reg = RCM->BDCTRL; + break; - case 2: - reg = RCM->CSTS; - break; + case 2: + reg = RCM->CSTS; + break; - default: - break; + default: + break; } if (reg & bit) @@ -1017,7 +1313,7 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag) } /*! - * @brief Clears all the RCM reset flags + * @brief Clear all the RCM reset flags * * @param None * @@ -1033,33 +1329,37 @@ void RCM_ClearStatusFlag(void) } /*! - * @brief Reads the specified RCM interrupt Flag + * @brief Read the specified RCM interrupt Flag * - * @param flag £ºReads specifies RCM interrupt flag. + * @param flag ��Reads specifies RCM interrupt flag. * This parameter can be one of the following values: * @arg RCM_INT_LSIRDY : LSI ready interrupt flag * @arg RCM_INT_LSERDY : LSE ready interrupt flag * @arg RCM_INT_HSIRDY : HSI ready interrupt flag * @arg RCM_INT_HSERDY : HSE ready interrupt flag * @arg RCM_INT_PLLRDY : PLL ready interrupt flag + * @arg RCM_INT_PLL2RDY: PLL2 ready interrupt flag + * @arg RCM_INT_PLL3RDY: PLL3 ready interrupt flag * @arg RCM_INT_CSS : Clock Security System interrupt flag * * @retval The new state of intFlag (SET or RESET) */ uint8_t RCM_ReadIntFlag(RCM_INT_T flag) { - return (RCM->INT &flag) ? SET : RESET; + return (RCM->INT& flag) ? SET : RESET; } /*! - * @brief Clears the interrupt flag + * @brief Clear the interrupt flag * - * @param flag : Clears specifies interrupt flag. + * @param flag : Clear specifies interrupt flag. * @arg RCM_INT_LSIRDY : Clear LSI ready interrupt flag * @arg RCM_INT_LSERDY : Clear LSE ready interrupt flag * @arg RCM_INT_HSIRDY : Clear HSI ready interrupt flag * @arg RCM_INT_HSERDY : Clear HSE ready interrupt flag * @arg RCM_INT_PLLRDY : Clear PLL ready interrupt flag + * @arg RCM_INT_PLL2RDY: Clear PLL2 ready interrupt flag + * @arg RCM_INT_PLL3RDY: Clear PLL3 ready interrupt flag * @arg RCM_INT_CSS : Clear Clock Security System interrupt flag * * @retval None @@ -1072,6 +1372,6 @@ void RCM_ClearIntFlag(uint32_t flag) RCM->INT |= temp; } -/**@} end of group RCM_Fuctions*/ -/**@} end of group RCM_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group RCM_Functions */ +/**@} end of group RCM_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c index d72487ede1..5f30bb993b 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c @@ -3,9 +3,9 @@ * * @brief This file provides all the RTC firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,24 +15,26 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions * and limitations under the License. */ + #include "apm32f10x_rtc.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup RTC_Driver RTC Driver + * @brief RTC driver modules @{ */ -/** @addtogroup RTC_Fuctions Fuctions +/** @defgroup RTC_Functions Functions @{ */ @@ -76,7 +78,7 @@ uint32_t RTC_ReadCounter(void) } /*! - * @brief Config the RTC counter value. + * @brief Configures the RTC counter value. * * @param value: RTC counter new value. * @@ -91,7 +93,7 @@ void RTC_ConfigCounter(uint32_t value) } /*! - * @brief Config the RTC prescaler value. + * @brief Configures the RTC prescaler value. * * @param value: RTC prescaler new value. * @@ -106,7 +108,7 @@ void RTC_ConfigPrescaler(uint32_t value) } /*! - * @brief Config the RTC alarm value. + * @brief Configures the RTC alarm value. * * @param value: RTC alarm new value. * @@ -121,7 +123,7 @@ void RTC_ConfigAlarm(uint32_t value) } /*! - * @brief Reads the RTC divider value. + * @brief Read the RTC divider value. * * @param None * @@ -150,7 +152,7 @@ void RTC_WaitForLastTask(void) } /*! - * @brief Waits until the RTC registers + * @brief Waits until the RTC registers Synchronized. * * @param None * @@ -258,6 +260,6 @@ void RTC_ClearIntFlag(uint16_t flag) RTC->CSTS &= (uint32_t)~flag; } -/**@} end of group RTC_Fuctions*/ -/**@} end of group RTC_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group RTC_Functions */ +/**@} end of group RTC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c index 9c7f865592..3e5995d616 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c @@ -3,9 +3,9 @@ * * @brief This file contains all the functions for the SCI2C peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,26 +26,27 @@ #include "apm32f10x_sci2c.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup SCI2C_Driver SCI2C Driver + * @brief SCI2C driver modules @{ */ -/** @addtogroup SCI2C_Fuctions Fuctions +/** @defgroup SCI2C_Functions Functions @{ */ /*! * @brief Set I2C peripheral registers to their default reset values * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_Reset(SCI2C_T *i2c) +void SCI2C_Reset(SCI2C_T* i2c) { if (i2c == I2C3) { @@ -64,7 +65,7 @@ void SCI2C_Reset(SCI2C_T *i2c) } /*! - * @brief Config the I2C peripheral according to the specified parameters in the sci2cConfig + * @brief Configures the I2C peripheral according to the specified parameters in the sci2cConfig * * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 * @@ -72,7 +73,7 @@ void SCI2C_Reset(SCI2C_T *i2c) * * @retval None */ -void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig) +void SCI2C_Config(SCI2C_T* i2c, SCI2C_Config_T* sci2cConfig) { i2c->SW = BIT_SET; @@ -122,7 +123,7 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig) * * @retval None */ -void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig) +void SCI2C_ConfigStructInit(SCI2C_Config_T* sci2cConfig) { sci2cConfig->addrMode = SCI2C_ADDR_MODE_7BIT; sci2cConfig->slaveAddr = 0x55; @@ -138,7 +139,7 @@ void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig) /*! * @brief Read specified flag * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param flag: Specifies the flag to be checked * The parameter can be one of following values: @@ -155,7 +156,7 @@ void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig) * * @retval The new state of flag (SET or RESET) */ -uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag) +uint8_t SCI2C_ReadStatusFlag(SCI2C_T* i2c, SCI2C_FLAG_T flag) { uint8_t ret = RESET; @@ -174,7 +175,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag) /*! * @brief Read specified interrupt flag * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param flag: Specifies the interrupt flag to be checked * The parameter can be one of following values: @@ -195,7 +196,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag) * * @retval The new state of flag (SET or RESET) */ -uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +uint8_t SCI2C_ReadIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag) { uint8_t ret = RESET; @@ -207,7 +208,7 @@ uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) /*! * @brief Clear specified interrupt flag * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param flag: Specifies the interrupt flag to be checked * The parameter can be one of following values: @@ -224,7 +225,7 @@ uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) * @arg SCI2C_INT_ALL: All interrupt flag * @retval The new state of flag (SET or RESET) */ -void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +void SCI2C_ClearIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag) { volatile uint32_t dummy = 0; @@ -277,7 +278,7 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) /*! * @brief Read specified interrupt flag(Raw register) * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param flag: Specifies the interrupt flag to be checked * The parameter can be one of following values: @@ -298,7 +299,7 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) * * @retval The new state of flag (SET or RESET) */ -uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +uint8_t SCI2C_ReadRawIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag) { uint8_t ret = RESET; @@ -310,7 +311,7 @@ uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) /*! * @brief Enable the specified interrupts * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param interrupt: Specifies the interrupt sources * The parameter can be any combination of following values: @@ -331,7 +332,7 @@ uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) * * @retval None */ -void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt) +void SCI2C_EnableInterrupt(SCI2C_T* i2c, uint16_t interrupt) { i2c->INTEN |= interrupt; } @@ -339,7 +340,7 @@ void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt) /*! * @brief Disable the specified interrupts * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param interrupt: Specifies the interrupt sources * The parameter can be any combination of following values: @@ -360,7 +361,7 @@ void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt) * * @retval None */ -void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt) +void SCI2C_DisableInterrupt(SCI2C_T* i2c, uint16_t interrupt) { i2c->INTEN &= ~interrupt; } @@ -368,9 +369,9 @@ void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt) /*! * @brief Enable stop detected only master in activity. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 */ -void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c) +void SCI2C_EnableStopDetectMasterActivity(SCI2C_T* i2c) { i2c->CTRL1_B.DSMA = BIT_SET; } @@ -378,9 +379,9 @@ void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c) /*! * @brief Disable stop detected only master in activity. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 */ -void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c) +void SCI2C_DisableStopDetectMasterActivity(SCI2C_T* i2c) { i2c->CTRL1_B.DSMA = BIT_RESET; } @@ -388,9 +389,9 @@ void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c) /*! * @brief Enable stop detected only address is matched in slave mode. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 */ -void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c) +void SCI2C_EnableStopDetectAddressed(SCI2C_T* i2c) { i2c->CTRL1_B.DSA = BIT_SET; } @@ -398,9 +399,9 @@ void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c) /*! * @brief Disable stop detected only address is matched in slave mode. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 */ -void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c) +void SCI2C_DisableStopDetectAddressed(SCI2C_T* i2c) { i2c->CTRL1_B.DSA = BIT_RESET; } @@ -408,11 +409,11 @@ void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c) /*! * @brief Enable restart * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_EnableRestart(SCI2C_T *i2c) +void SCI2C_EnableRestart(SCI2C_T* i2c) { i2c->CTRL1_B.RSTAEN = BIT_SET; } @@ -420,19 +421,19 @@ void SCI2C_EnableRestart(SCI2C_T *i2c) /*! * @brief Disable restart * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_DisableRestart(SCI2C_T *i2c) +void SCI2C_DisableRestart(SCI2C_T* i2c) { i2c->CTRL1_B.RSTAEN = BIT_RESET; } /*! - * @brief Config speed. + * @brief Configures speed. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param speed: Specifies the speed. * @arg SCI2C_SPEED_STANDARD: Standard speed. @@ -441,15 +442,15 @@ void SCI2C_DisableRestart(SCI2C_T *i2c) * * @retval None */ -void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed) +void SCI2C_ConfigSpeed(SCI2C_T* i2c, SCI2C_SPEED_T speed) { i2c->CTRL1_B.SPD = speed; } /*! - * @brief Config master address. + * @brief Configures master address. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param mode: Specifies the address mode. * @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode. @@ -459,7 +460,7 @@ void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed) * * @retval None */ -void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) +void SCI2C_ConfigMasterAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) { i2c->TARADDR_B.MAM = mode; i2c->TARADDR_B.ADDR = addr; @@ -467,7 +468,7 @@ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) /*! - * @brief Config slave address. + * @brief Configures slave address. * * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 * @@ -479,7 +480,7 @@ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) * * @retval None */ -void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) +void SCI2C_ConfigSlaveAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) { i2c->CTRL1_B.SAM = mode; i2c->SLAADDR = addr; @@ -488,11 +489,11 @@ void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) /*! * @brief Enable master mode * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_EnableMasterMode(SCI2C_T *i2c) +void SCI2C_EnableMasterMode(SCI2C_T* i2c) { i2c->CTRL1_B.MST = BIT_SET; } @@ -500,11 +501,11 @@ void SCI2C_EnableMasterMode(SCI2C_T *i2c) /*! * @brief Disable master mode * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_DisableMasterMode(SCI2C_T *i2c) +void SCI2C_DisableMasterMode(SCI2C_T* i2c) { i2c->CTRL1_B.MST = BIT_RESET; } @@ -512,11 +513,11 @@ void SCI2C_DisableMasterMode(SCI2C_T *i2c) /*! * @brief Enable slave mode * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_EnableSlaveMode(SCI2C_T *i2c) +void SCI2C_EnableSlaveMode(SCI2C_T* i2c) { i2c->CTRL1_B.SLADIS = BIT_RESET; } @@ -524,11 +525,11 @@ void SCI2C_EnableSlaveMode(SCI2C_T *i2c) /*! * @brief Disable slave mode * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_DisableSlaveMode(SCI2C_T *i2c) +void SCI2C_DisableSlaveMode(SCI2C_T* i2c) { i2c->CTRL1_B.SLADIS = BIT_SET; } @@ -536,13 +537,13 @@ void SCI2C_DisableSlaveMode(SCI2C_T *i2c) /*! * @brief Config master code * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param code: Master code * * @retval None */ -void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code) +void SCI2C_ConfigMasterCode(SCI2C_T* i2c, uint8_t code) { i2c->HSMC = code; } @@ -550,7 +551,7 @@ void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code) /*! * @brief Config data direction * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param dir: Data direction * @arg SCI2C_DATA_DIR_WRITE: Write data @@ -558,7 +559,7 @@ void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code) * * @retval None */ -void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir) +void SCI2C_ConfigDataDir(SCI2C_T* i2c, SCI2C_DATA_DIR_T dir) { i2c->DATA = (uint32_t)(dir << 8); } @@ -566,13 +567,13 @@ void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir) /*! * @brief Transmit data * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param data: Data to be transmited * * @retval None */ -void SCI2C_TxData(SCI2C_T *i2c, uint8_t data) +void SCI2C_TxData(SCI2C_T* i2c, uint8_t data) { i2c->DATA_B.DATA = data; } @@ -580,20 +581,20 @@ void SCI2C_TxData(SCI2C_T *i2c, uint8_t data) /*! * @brief Returns the most recent received data * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval Received data * */ -uint8_t SCI2C_RxData(SCI2C_T *i2c) +uint8_t SCI2C_RxData(SCI2C_T* i2c) { return (uint8_t)(i2c->DATA & 0XFF); } /*! - * @brief Config data register + * @brief Configures data register * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param stop: Enable or disable generate stop condition * @@ -605,7 +606,7 @@ uint8_t SCI2C_RxData(SCI2C_T *i2c) * * @retval None */ -void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data) +void SCI2C_ConfigDataRegister(SCI2C_T* i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data) { i2c->DATA = (uint32_t)((stop << 9) | (dataDir << 8) | data); } @@ -613,11 +614,11 @@ void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T /*! * @brief Read Rx FIFO data number * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c) +uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T* i2c) { return (uint8_t)i2c->RFL; } @@ -625,39 +626,39 @@ uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c) /*! * @brief Read Tx FIFO data number * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c) +uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T* i2c) { return (uint8_t)i2c->TFL; } /*! - * @brief Config Rx FIFO threshold + * @brief Configures Rx FIFO threshold * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param threshold: FIFO threshold * * @retval None */ -void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) +void SCI2C_ConfigRxFifoThreshold(SCI2C_T* i2c, uint8_t threshold) { i2c->RFT = threshold; } /*! - * @brief Config Tx FIFO threshold + * @brief Configures Tx FIFO threshold * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param threshold: FIFO threshold * * @retval None */ -void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) +void SCI2C_ConfigTxFifoThreshold(SCI2C_T* i2c, uint8_t threshold) { i2c->TFT = threshold; } @@ -665,12 +666,12 @@ void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) /*! * @brief Enable I2C peripheral * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_Enable(SCI2C_T *i2c) +void SCI2C_Enable(SCI2C_T* i2c) { i2c->CTRL2_B.I2CEN = BIT_SET; } @@ -678,11 +679,11 @@ void SCI2C_Enable(SCI2C_T *i2c) /*! * @brief Disable I2C peripheral * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_Disable(SCI2C_T *i2c) +void SCI2C_Disable(SCI2C_T* i2c) { i2c->CTRL2_B.I2CEN = BIT_RESET; } @@ -690,11 +691,11 @@ void SCI2C_Disable(SCI2C_T *i2c) /*! * @brief Abort I2C transmit * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval None */ -void SCI2C_Abort(SCI2C_T *i2c) +void SCI2C_Abort(SCI2C_T* i2c) { i2c->CTRL2_B.ABR = BIT_SET; } @@ -702,21 +703,21 @@ void SCI2C_Abort(SCI2C_T *i2c) /*! * @brief Tx command block * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param enable: ENABLE or DISABLE * * @retval None */ -void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable) +void SCI2C_BlockTxCmd(SCI2C_T* i2c, uint8_t enable) { i2c->CTRL2_B.TCB = enable; } /*! - * @brief Config SCL high and low period + * @brief Configures SCL high and low period * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param speed: Specifies the speed. * @arg SCI2C_SPEED_STANDARD: Standard speed. @@ -729,7 +730,7 @@ void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable) * * @retval None */ -void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod) +void SCI2C_ConfigClkPeriod(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod) { if (speed == SCI2C_SPEED_STANDARD) { @@ -749,9 +750,9 @@ void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPerio } /*! - * @brief Config SDA hold time length + * @brief Configures SDA hold time length * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param txHold: Tx SDA hold time length * @@ -759,22 +760,22 @@ void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPerio * * @retval None */ -void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold) +void SCI2C_ConfigSDAHoldTime(SCI2C_T* i2c, uint16_t txHold, uint8_t rxHold) { i2c->SDAHOLD_B.TXHOLD = txHold; i2c->SDAHOLD_B.RXHOLD = rxHold; } /*! - * @brief Config SDA delay time + * @brief Configures SDA delay time * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param delay: SDA delay time * * @retval None */ -void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay) +void SCI2C_ConfigSDADelayTime(SCI2C_T* i2c, uint8_t delay) { i2c->SDADLY = delay; } @@ -782,13 +783,13 @@ void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay) /*! * @brief Enable or disable generate gernal call ack * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param enable: SDA delay time * * @retval None */ -void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable) +void SCI2C_GernalCallAck(SCI2C_T* i2c, uint8_t enable) { i2c->GCA = enable; } @@ -796,13 +797,13 @@ void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable) /*! * @brief When received data no ack generated in slave mode. * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param enable: ENABLE or DISABLE * * @retval None */ -void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable) +void SCI2C_SlaveDataNackOnly(SCI2C_T* i2c, uint8_t enable) { i2c->SDNO = enable; } @@ -810,11 +811,11 @@ void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable) /*! * @brief Read Tx abort source * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @retval Return Tx abort source */ -uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c) +uint32_t SCI2C_ReadTxAbortSource(SCI2C_T* i2c) { return (uint32_t)i2c->TAS; } @@ -822,7 +823,7 @@ uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c) /*! * @brief Enable DMA * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param dma: DMA requst source * @arg SCI2C_DMA_RX: DMA RX channel @@ -830,7 +831,7 @@ uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c) * * @retval None */ -void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) +void SCI2C_EnableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma) { i2c->DMACTRL |= dma; } @@ -838,7 +839,7 @@ void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) /*! * @brief Disable DMA * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param dma: DMA requst source * @arg SCI2C_DMA_RX: DMA RX channel @@ -846,43 +847,43 @@ void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) * * @retval None */ -void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) +void SCI2C_DisableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma) { i2c->DMACTRL &= (uint32_t)~dma; } /*! - * @brief Config DMA Tx data level + * @brief Configures DMA Tx data level * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param cnt: DMA Tx data level * * @retval None */ -void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt) +void SCI2C_ConfigDMATxDataLevel(SCI2C_T* i2c, uint8_t cnt) { i2c->DTDL = cnt; } /*! - * @brief Config DMA Rx data level + * @brief Configures DMA Rx data level * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param cnt: DMA Rx data level * * @retval None */ -void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt) +void SCI2C_ConfigDMARxDataLevel(SCI2C_T* i2c, uint8_t cnt) { i2c->DRDL = cnt; } /*! - * @brief Config spike suppressio limit + * @brief Configures spike suppressio limit * - * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * @param i2c: Select the the I2C peripheral. It can be I2C3 or I2C4 * * @param speed: I2C speed mode * @arg SCI2C_SPEED_STANDARD: Standard speed. @@ -893,7 +894,7 @@ void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt) * * @retval None */ -void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit) +void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint8_t limit) { if (speed == SCI2C_SPEED_HIGH) { @@ -905,6 +906,6 @@ void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_ } } -/**@} end of group SCI2C_Fuctions*/ -/**@} end of group SCI2C_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group SCI2C_Functions */ +/**@} end of group SCI2C_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c index 691352116c..0e26f4319c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c @@ -1,11 +1,11 @@ /*! * @file apm32f10x_sdio.c * - * @brief This file provides all the SDIO firmware functions + * @brief This file provides all the SDIO firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,24 +26,25 @@ #include "apm32f10x_sdio.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup SDIO_Driver SDIO Driver + * @brief SDIO driver modules @{ */ -/** @addtogroup SDIO_Fuctions Fuctions +/** @defgroup SDIO_Functions Functions @{ */ /*! - * @brief Reset sdio peripheral registers to their default reset values + * @brief Reset sdio peripheral registers to their default reset values * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_Reset(void) { @@ -59,13 +60,13 @@ void SDIO_Reset(void) } /*! - * @brief Config the SDIO peripheral according to the specified parameters in the sdioConfig + * @brief Configures the SDIO peripheral according to the specified parameters in the sdioConfig * - * @param sdioConfig: pointer to a SDIO_Config_T structure + * @param sdioConfig: pointer to a SDIO_Config_T structure * - * @retval None + * @retval None */ -void SDIO_Config(SDIO_Config_T *sdioConfig) +void SDIO_Config(SDIO_Config_T* sdioConfig) { uint32_t tmp = 0; @@ -79,13 +80,13 @@ void SDIO_Config(SDIO_Config_T *sdioConfig) } /*! - * @brief Fills each SDIO_Config_T member with its default value + * @brief Fills each SDIO_Config_T member with its default value * - * @param sdioConfig: pointer to a SDIO_Config_T structure + * @param sdioConfig: pointer to a SDIO_Config_T structure * - * @retval None + * @retval None */ -void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig) +void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig) { sdioConfig->clockDiv = 0x00; sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; @@ -96,33 +97,33 @@ void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig) } /*! - * @brief Enables the SDIO clock + * @brief Enable the SDIO clock * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableClock(void) { - *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)SET; + *(__IO uint32_t*) CLKCTRL_CLKEN_BB = (uint32_t)SET; } /*! - * @brief Disables the SDIO clock + * @brief Disable the SDIO clock * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableClock(void) { - *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)RESET; + *(__IO uint32_t*) CLKCTRL_CLKEN_BB = (uint32_t)RESET; } /*! - * @brief Sets the power status of the controller + * @brief Set the power status of the controller * - * @param powerState: new state of the Power state + * @param powerState: new state of the Power state * The parameter can be one of following values: * @arg SDIO_POWER_STATE_OFF * @arg SDIO_POWER_STATE_ON @@ -135,13 +136,13 @@ void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState) } /*! - * @brief Reads the SDIO power state + * @brief Read the SDIO power state * - * @param None + * @param None * - * @retval The new state SDIO power + * @retval The new state SDIO power * - * @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON + * @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON */ uint32_t SDIO_ReadPowerState(void) { @@ -149,38 +150,38 @@ uint32_t SDIO_ReadPowerState(void) } /*! - * @brief Enables the SDIO DMA request + * @brief Enable the SDIO DMA request * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableDMA(void) { - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)SET; + *(__IO uint32_t*) DCTRL_DMAEN_BB = (uint32_t)SET; } /*! - * @brief Disables the SDIO DMA request + * @brief Disable the SDIO DMA request * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableDMA(void) { - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)RESET; + *(__IO uint32_t*) DCTRL_DMAEN_BB = (uint32_t)RESET; } /*! - * @brief Configs the SDIO Command and send the command + * @brief Configures the SDIO Command and send the command * - * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure + * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure * - * @retval None + * @retval None * */ -void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig) +void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig) { uint32_t tmpreg = 0; @@ -193,14 +194,14 @@ void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig) } /*! - * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value + * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value * - * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure + * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure * - * @retval None + * @retval None * */ -void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig) +void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig) { cmdConfig->argument = 0x00; cmdConfig->cmdIndex = 0x00; @@ -210,11 +211,11 @@ void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig) } /*! - * @brief Reads the SDIO command response + * @brief Read the SDIO command response * - * @param None + * @param None * - * @retval The command index of the last command response received + * @retval The command index of the last command response received * */ uint8_t SDIO_ReadCommandResponse(void) @@ -223,16 +224,16 @@ uint8_t SDIO_ReadCommandResponse(void) } /*! - * @brief Reads the SDIO response + * @brief Read the SDIO response * - * @param res: Specifies the SDIO response register + * @param res: Specifies the SDIO response register * The parameter can be one of following values: * @arg SDIO_RES1: Response Register 1 * @arg SDIO_RES2: Response Register 2 * @arg SDIO_RES3: Response Register 3 * @arg SDIO_RES4: Response Register 4 * - * @retval The Corresponding response register value + * @retval The Corresponding response register value */ uint32_t SDIO_ReadResponse(SDIO_RES_T res) { @@ -240,17 +241,17 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res) tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; - return (*(__IO uint32_t *) tmp); + return (*(__IO uint32_t*) tmp); } /*! - * @brief Configs the SDIO Dataaccording to the specified parameters in the dataConfig + * @brief Configures the SDIO Dataaccording to the specified parameters in the dataConfig * - * @param dataConfig: pointer to a SDIO_DataConfig_T structure + * @param dataConfig: pointer to a SDIO_DataConfig_T structure * - * @retval None + * @retval None */ -void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig) +void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) { uint32_t tmpreg = 0; @@ -269,13 +270,13 @@ void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig) } /*! - * @brief Fills each SDIO_DataConfig_T member with its default value + * @brief Fills each SDIO_DataConfig_T member with its default value * - * @param dataConfig: pointer to a SDIO_DataConfig_T structure + * @param dataConfig: pointer to a SDIO_DataConfig_T structure * - * @retval None + * @retval None */ -void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig) +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig) { dataConfig->dataTimeOut = 0xFFFFFFFF; dataConfig->dataLength = 0x00; @@ -286,11 +287,11 @@ void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig) } /*! - * @brief Reads the SDIO Data counter + * @brief Read the SDIO Data counter * - * @param None + * @param None * - * @retval The SDIO Data counter value + * @retval The SDIO Data counter value */ uint32_t SDIO_ReadDataCounter(void) { @@ -298,11 +299,11 @@ uint32_t SDIO_ReadDataCounter(void) } /*! - * @brief Write the SDIO Data + * @brief Write the SDIO Data * - * @param Data£ºWrite 32-bit data + * @param Data: Write 32-bit data * - * @retval None + * @retval None */ void SDIO_WriteData(uint32_t data) { @@ -310,11 +311,11 @@ void SDIO_WriteData(uint32_t data) } /*! - * @brief Reads the SDIO Data + * @brief Read the SDIO Data * - * @param None + * @param None * - * @retval The SDIO FIFO Data value + * @retval The SDIO FIFO Data value */ uint32_t SDIO_ReadData(void) { @@ -322,11 +323,11 @@ uint32_t SDIO_ReadData(void) } /*! - * @brief Reads the SDIO FIFO count value + * @brief Read the SDIO FIFO count value * - * @param None + * @param None * - * @retval The SDIO FIFO count value + * @retval The SDIO FIFO count value */ uint32_t SDIO_ReadFIFOCount(void) { @@ -334,217 +335,217 @@ uint32_t SDIO_ReadFIFOCount(void) } /*! - * @brief Enables SDIO start read wait + * @brief Enable SDIO start read wait * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableStartReadWait(void) { - *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) SET; + *(__IO uint32_t*) DCTRL_RWSTR_BB = (uint32_t) SET; } /*! - * @brief Disables SDIO start read wait + * @brief Disable SDIO start read wait * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableStopReadWait(void) { - *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) RESET; + *(__IO uint32_t*) DCTRL_RWSTR_BB = (uint32_t) RESET; } /*! - * @brief Enables SDIO stop read wait + * @brief Enable SDIO stop read wait * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableStopReadWait(void) { - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) SET; + *(__IO uint32_t*) DCTRL_RWSTOP_BB = (uint32_t) SET; } /*! - * @brief Disables SDIO stop read wait + * @brief Disable SDIO stop read wait * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableStartReadWait(void) { - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) RESET; + *(__IO uint32_t*) DCTRL_RWSTOP_BB = (uint32_t) RESET; } /*! - * @brief Sets the read wait interval + * @brief Set the read wait interval * - * @param readWaitMode: SDIO read Wait Mode + * @param readWaitMode: SDIO read Wait Mode * The parameter can be one of following values: * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 * - * @retval None + * @retval None * */ void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) { - *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode; + *(__IO uint32_t*) DCTRL_RDWAIT_BB = readWaitMode; } /*! - * @brief Enables SDIO SD I/O Mode Operation + * @brief Enable SDIO SD I/O Mode Operation * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableSDIO(void) { - *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET; + *(__IO uint32_t*) DCTRL_SDIOF_BB = (uint32_t)SET; } /*! - * @brief Disables SDIO SD I/O Mode Operation + * @brief Disable SDIO SD I/O Mode Operation * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableSDIO(void) { - *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET; + *(__IO uint32_t*) DCTRL_SDIOF_BB = (uint32_t)RESET; } /*! - * @brief Ensables SDIO SD I/O Mode suspend command sending + * @brief Enable SDIO SD I/O Mode suspend command sending * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableTxSDIOSuspend(void) { - *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)SET; + *(__IO uint32_t*) CMD_SDIOSC_BB = (uint32_t)SET; } /*! - * @brief Disables SDIO SD I/O Mode suspend command sending + * @brief Disable SDIO SD I/O Mode suspend command sending * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableTxSDIOSuspend(void) { - *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)RESET; + *(__IO uint32_t*) CMD_SDIOSC_BB = (uint32_t)RESET; } /*! - * @brief Enables the command completion signal + * @brief Enable the command completion signal * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableCommandCompletion(void) { - *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)SET; + *(__IO uint32_t*) CMD_CMDCPEN_BB = (uint32_t)SET; } /*! - * @brief Disables the command completion signal + * @brief Disable the command completion signal * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableCommandCompletion(void) { - *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)RESET; + *(__IO uint32_t*) CMD_CMDCPEN_BB = (uint32_t)RESET; } /*! - * @brief Enables the CE-ATA interrupt + * @brief Enable the CE-ATA interrupt * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableCEATAInterrupt(void) { - *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1)); + *(__IO uint32_t*) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1)); } /*! - * @brief Disables the CE-ATA interrupt + * @brief Disable the CE-ATA interrupt * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableCEATAInterrupt(void) { - *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1)); + *(__IO uint32_t*) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1)); } /*! - * @brief Ensables Sends CE-ATA command + * @brief Enable Sends CE-ATA command * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_EnableTxCEATA(void) { - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)SET; + *(__IO uint32_t*) CMD_ATACMD_BB = (uint32_t)SET; } /*! - * @brief Disables Sends CE-ATA command + * @brief Disable Sends CE-ATA command * - * @param None + * @param None * - * @retval None + * @retval None */ void SDIO_DisableTxCEATA(void) { - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)RESET; + *(__IO uint32_t*) CMD_ATACMD_BB = (uint32_t)RESET; } /*! - * @brief Enables the specified SDIO interrupt + * @brief Enable the specified SDIO interrupt * * @param interrupt: Select the SDIO interrupt source - * The parameter can be any combination of following values: - * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt - * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt - * @arg SDIO_INT_DATATO: Data timeout interrupt - * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt - * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt - * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_INT_TXACT: Data transmit in progress interrupt - * @arg SDIO_INT_RXACT: Data receive in progress interrupt - * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt - * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt - * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt - * @arg SDIO_INT_RXFF: Receive FIFO full interrupt - * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt - * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt - * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt - * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval None */ void SDIO_EnableInterrupt(uint32_t interrupt) @@ -553,34 +554,34 @@ void SDIO_EnableInterrupt(uint32_t interrupt) } /*! - * @brief Disables the specified SDIO interrupt + * @brief Disable the specified SDIO interrupt * * @param interrupt: Select the SDIO interrupt source - * The parameter can be any combination of following values: - * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt - * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt - * @arg SDIO_INT_DATATO: Data timeout interrupt - * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt - * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt - * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_INT_TXACT: Data transmit in progress interrupt - * @arg SDIO_INT_RXACT: Data receive in progress interrupt - * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt - * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt - * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt - * @arg SDIO_INT_RXFF: Receive FIFO full interrupt - * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt - * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt - * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt - * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval None */ void SDIO_DisableInterrupt(uint32_t interrupt) @@ -589,34 +590,34 @@ void SDIO_DisableInterrupt(uint32_t interrupt) } /*! - * @brief Reads the specified SDIO flag + * @brief Read the specified SDIO flag * * @param flag: Select the flag to read - * The parameter can be one of following values: - * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag - * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag - * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag - * @arg SDIO_FLAG_DATATO: Data timeout flag - * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag - * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag - * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag - * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag - * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag - * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag - * @arg SDIO_FLAG_CMDACT: Command transfer in progress flag - * @arg SDIO_FLAG_TXACT: Data transmit in progress flag - * @arg SDIO_FLAG_RXACT: Data receive in progress flag - * @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag - * @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag - * @arg SDIO_FLAG_TXFF: Transmit FIFO full flag - * @arg SDIO_FLAG_RXFF: Receive FIFO full flag - * @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag - * @arg SDIO_FLAG_RXFE: Receive FIFO empty flag - * @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag - * @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag - * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag + * The parameter can be one of following values: + * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag + * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag + * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag + * @arg SDIO_FLAG_DATATO: Data timeout flag + * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag + * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag + * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag + * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag + * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag + * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag + * @arg SDIO_FLAG_CMDACT: Command transfer in progress flag + * @arg SDIO_FLAG_TXACT: Data transmit in progress flag + * @arg SDIO_FLAG_RXACT: Data receive in progress flag + * @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag + * @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag + * @arg SDIO_FLAG_TXFF: Transmit FIFO full flag + * @arg SDIO_FLAG_RXFF: Receive FIFO full flag + * @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag + * @arg SDIO_FLAG_RXFE: Receive FIFO empty flag + * @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag + * @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag + * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag * * @retval SET or RESET */ @@ -626,23 +627,23 @@ uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) } /*! - * @brief Clears the specified SDIO flag + * @brief Clear the specified SDIO flag * * @param flag: Select the flag to clear - * The parameter can be any combination of following values: - * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag - * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag - * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag - * @arg SDIO_FLAG_DATATO: Data timeout flag - * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag - * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag - * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag - * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag - * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag - * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag - * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag + * The parameter can be any combination of following values: + * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag + * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag + * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag + * @arg SDIO_FLAG_DATATO: Data timeout flag + * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag + * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag + * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag + * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag + * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag + * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag + * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag * * @retval None */ @@ -652,34 +653,34 @@ void SDIO_ClearStatusFlag(uint32_t flag) } /*! - * @brief Reads the specified SDIO Interrupt flag + * @brief Read the specified SDIO Interrupt flag * * @param flag: Select the SDIO interrupt source - * The parameter can be one of following values: - * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt - * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt - * @arg SDIO_INT_DATATO: Data timeout interrupt - * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt - * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt - * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_INT_TXACT: Data transmit in progress interrupt - * @arg SDIO_INT_RXACT: Data receive in progress interrupt - * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt - * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt - * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt - * @arg SDIO_INT_RXFF: Receive FIFO full interrupt - * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt - * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt - * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt - * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * The parameter can be one of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt * * @retval SET or RESET */ @@ -700,23 +701,23 @@ uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag) } /*! - * @brief Clears the specified SDIO Interrupt pending bits + * @brief Clear the specified SDIO Interrupt pending bits * * @param flag: Select the SDIO interrupt source - * The parameter can be any combination of following values: - * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt - * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt - * @arg SDIO_INT_DATATO: Data timeout interrupt - * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt - * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt - * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt * * @retval None */ @@ -725,6 +726,6 @@ void SDIO_ClearIntFlag(uint32_t flag) SDIO->ICF = flag; } -/**@} end of group SDIO_Fuctions*/ -/**@} end of group SDIO_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group SDIO_Functions */ +/**@} end of group SDIO_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_smc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_smc.c new file mode 100644 index 0000000000..df31f13a13 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_smc.c @@ -0,0 +1,747 @@ +/*! + * @file apm32f10x_smc.c + * + * @brief This file provides all the SMC firmware functions + * + * @version V1.0.4 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2020-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f10x_smc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup APM32F10x_StdPeriphDriver + @{ +*/ + +/** @addtogroup SMC_Driver SMC Driver + * @brief SMC driver modules + @{ +*/ + +/** @defgroup SMC_Functions Functions + @{ +*/ + +/*! + * @brief Reset the EMMMC NOR/SRAM Banks registers + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1 + * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2 + * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3 + * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank) +{ + /* SMC_BANK1_NORSRAM_1 */ + if (bank == SMC_BANK1_NORSRAM_1) + { + SMC_Bank1->SNCTRL_T[bank] = 0x000030DB; + } + /* SMC_BANK1_NORSRAM_2, SMC_BANK1_NORSRAM_3 or SMC_BANK1_NORSRAM_4 */ + else + { + SMC_Bank1->SNCTRL_T[bank] = 0x000030D2; + } + SMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF; + SMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF; +} + +/*! + * @brief Reset the EMMMC NAND Banks registers + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND: FSMC Bank2 NAND + * @arg SMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void SMC_ResetNAND(SMC_BANK_NAND_T bank) +{ + if (bank == SMC_BANK2_NAND) + { + /* Set the SMC_Bank2 registers to their reset values */ + SMC_Bank2->CTRL2 = 0x00000018; + SMC_Bank2->STSINT2 = 0x00000040; + SMC_Bank2->CMSTIM2 = 0xFCFCFCFC; + SMC_Bank2->AMSTIM2 = 0xFCFCFCFC; + } + /* SMC BANK3 NAND */ + else + { + /* Set the SMC_Bank3 registers to their reset values */ + SMC_Bank3->CTRL3 = 0x00000018; + SMC_Bank3->STSINT3 = 0x00000040; + SMC_Bank3->CMSTIM3 = 0xFCFCFCFC; + SMC_Bank3->AMSTIM3 = 0xFCFCFCFC; + } +} + +/*! + * @brief Reset the EMMMC PCCARD Banks registers + * + * @param None + * + * @retval None + */ +void SMC_ResetPCCard(void) +{ + /* Set the SMC_Bank4 registers to their reset values */ + SMC_Bank4->CTRL4 = 0x00000018; + SMC_Bank4->STSINT4 = 0x00000040; + SMC_Bank4->CMSTIM4 = 0xFCFCFCFC; + SMC_Bank4->AMSTIM4 = 0xFCFCFCFC; + SMC_Bank4->IOSTIM4 = 0xFCFCFCFC; +} + +/*! + * @brief Configures the SMC NOR/SRAM Banks according to the specified parameters in the smcNORSRAMConfig. + * + * @param smcNORSRAMConfig: Point to a SMC_NORSRAMConfig_T structure + * + * @retval None + */ +void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig) +{ + /* Bank1 NOR/SRAM control register configuration */ + SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank] = + (uint32_t)smcNORSRAMConfig->dataAddressMux | + smcNORSRAMConfig->memoryType | + smcNORSRAMConfig->memoryDataWidth | + smcNORSRAMConfig->burstAcceesMode | + smcNORSRAMConfig->asynchronousWait | + smcNORSRAMConfig->waitSignalPolarity | + smcNORSRAMConfig->wrapMode | + smcNORSRAMConfig->waitSignalActive | + smcNORSRAMConfig->writeOperation | + smcNORSRAMConfig->waiteSignal | + smcNORSRAMConfig->extendedMode | + smcNORSRAMConfig->writeBurst; + + if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR) + { + SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank] |= 0x00000040; + } + + /* Bank1 NOR/SRAM timing register configuration */ + SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank + 1] = + (uint32_t)smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime | + (smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) | + (smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) | + (smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) | + (smcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) | + (smcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) | + smcNORSRAMConfig->readWriteTimingStruct->accessMode; + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE) + { + SMC_Bank1E->WRTTIM[smcNORSRAMConfig->bank] = + (uint32_t)smcNORSRAMConfig->writeTimingStruct->addressSetupTime | + (smcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) | + (smcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) | + (smcNORSRAMConfig->writeTimingStruct->clockDivision << 20) | + (smcNORSRAMConfig->writeTimingStruct->dataLatency << 24) | + smcNORSRAMConfig->writeTimingStruct->accessMode; + } + else + { + SMC_Bank1E->WRTTIM[smcNORSRAMConfig->bank] = 0x0FFFFFFF; + } +} + +/*! + * @brief Configures the SMC NAND Banks according to the specified parameters in the smcNANDConfig. + * + * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure. + * + * @retval None + */ +void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Set the tmppcr value according to SMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)smcNANDConfig->waitFeature | 0x00000008 | + smcNANDConfig->memoryDataWidth | + smcNANDConfig->ECC | + smcNANDConfig->ECCPageSize | + (smcNANDConfig->TCLRSetupTime << 9) | + (smcNANDConfig->TARSetupTime << 13); + + /* Set tmppmem value according to SMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)smcNANDConfig->commonSpaceTimingStruct->setupTime | + (smcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (smcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + + /* Set tmppatt value according to SMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)smcNANDConfig->attributeSpaceTimingStruct->setupTime | + (smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + + if (smcNANDConfig->bank == SMC_BANK2_NAND) + { + /* SMC_BANK2_NAND registers configuration */ + SMC_Bank2->CTRL2 = tmppcr; + SMC_Bank2->CMSTIM2 = tmppmem; + SMC_Bank2->AMSTIM2 = tmppatt; + } + else + { + /* SMC_BANK3_NAND registers configuration */ + SMC_Bank3->CTRL3 = tmppcr; + SMC_Bank3->CMSTIM3 = tmppmem; + SMC_Bank3->AMSTIM3 = tmppatt; + } + +} + +/*! + * @brief Configures the SMC PCCARD according to the specified parameters in the smcPCCardConfig. + * + * @param smcPCCardConfig: Point to a SMC_PCCARDConfig_T structure. + * + * @retval None + */ +void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig) +{ + /* Set the PCR4 register value according to SMC_PCCARDInitStruct parameters */ + SMC_Bank4->CTRL4 = (uint32_t)smcPCCardConfig->waitFeature | SMC_MEMORY_DATA_WIDTH_16BIT | + (smcPCCardConfig->TCLRSetupTime << 9) | + (smcPCCardConfig->TARSetupTime << 13); + + /* Set PMEM4 register value according to SMC_CommonSpaceTimingStructure parameters */ + SMC_Bank4->CMSTIM4 = (uint32_t)smcPCCardConfig->commonSpaceTimingStruct->setupTime | + (smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + + /* Set PATT4 register value according to SMC_AttributeSpaceTimingStructure parameters */ + SMC_Bank4->AMSTIM4 = (uint32_t)smcPCCardConfig->attributeSpaceTimingStruct->setupTime | + (smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + + /* Set PIO4 register value according to SMC_IOSpaceTimingStructure parameters */ + SMC_Bank4->IOSTIM4 = (uint32_t)smcPCCardConfig->IOSpaceTimingStruct->setupTime | + (smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) | + (smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) | + (smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24); +} + +/*! + * @brief Fills each smcNORSRAMConfig member with its default value. + * + * @param smcNORSRAMConfig : Point to a SMC_NORSRAMConfig_T structure. + * + * @retval None + */ +void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig) +{ + /* Reset NOR/SRAM Init structure parameters values */ + smcNORSRAMConfig->bank = SMC_BANK1_NORSRAM_1; + smcNORSRAMConfig->dataAddressMux = SMC_DATA_ADDRESS_MUX_ENABLE; + smcNORSRAMConfig->memoryType = SMC_MEMORY_TYPE_SRAM; + smcNORSRAMConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT; + smcNORSRAMConfig->burstAcceesMode = SMC_BURST_ACCESS_MODE_DISABLE; + smcNORSRAMConfig->asynchronousWait = SMC_ASYNCHRONOUS_WAIT_DISABLE; + smcNORSRAMConfig->waitSignalPolarity = SMC_WAIT_SIGNAL_POLARITY_LOW; + smcNORSRAMConfig->wrapMode = SMC_WRAP_MODE_DISABLE; + smcNORSRAMConfig->waitSignalActive = SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT; + smcNORSRAMConfig->writeOperation = SMC_WRITE_OPERATION_ENABLE; + smcNORSRAMConfig->waiteSignal = SMC_WAITE_SIGNAL_ENABLE; + smcNORSRAMConfig->extendedMode = SMC_EXTENDEN_MODE_DISABLE; + smcNORSRAMConfig->writeBurst = SMC_WRITE_BURST_DISABLE; + smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF; + smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF; + smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF; + smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF; + smcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF; + smcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF; + smcNORSRAMConfig->readWriteTimingStruct->accessMode = SMC_ACCESS_MODE_A; + smcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF; + smcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF; + smcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF; + smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF; + smcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF; + smcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF; + smcNORSRAMConfig->writeTimingStruct->accessMode = SMC_ACCESS_MODE_A; +} + +/*! + * @brief Fills each smcNANDConfig member with its default value. + * + * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure. + * + * @retval None + */ +void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig) +{ + /* Reset NAND Init structure parameters values */ + smcNANDConfig->bank = SMC_BANK2_NAND; + smcNANDConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE; + smcNANDConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT; + smcNANDConfig->ECC = SMC_ECC_DISABLE; + smcNANDConfig->ECCPageSize = SMC_ECC_PAGE_SIZE_BYTE_256; + smcNANDConfig->TCLRSetupTime = 0x0; + smcNANDConfig->TARSetupTime = 0x0; + smcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC; + smcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC; + smcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC; + smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC; + smcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC; + smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC; + smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC; + smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC; +} + +/*! + * @brief Fills each smcPCCardConfig member with its default value. + * + * @param smcPCCardConfig : Point to a SMC_PCCARDConfig_T structure. + * + * @retval None + */ +void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig) +{ + /* Reset PCCARD Init structure parameters values */ + smcPCCardConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE; + smcPCCardConfig->TCLRSetupTime = 0x0; + smcPCCardConfig->TARSetupTime = 0x0; + smcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC; + smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC; + smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC; + smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC; + smcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC; + smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC; + smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC; + smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC; + smcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC; + smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC; + smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC; + smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC; +} + +/*! + * @brief Enable the specified NOR/SRAM Memory Bank. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1 + * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2 + * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3 + * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank) +{ + SMC_Bank1->SNCTRL_T[bank] |= 0x00000001; +} + +/*! + * @brief Disable the specified NOR/SRAM Memory Bank. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1 + * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2 + * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3 + * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank) +{ + SMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE; +} + +/*! + * @brief Enable the specified NAND Memory Bank. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND: FSMC Bank2 NAND + * @arg SMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void SMC_EnableNAND(SMC_BANK_NAND_T bank) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->CTRL2_B.MBKEN = BIT_SET; + } + else + { + SMC_Bank3->CTRL3_B.MBKEN = BIT_SET; + } +} + +/*! + * @brief Disable the specified NAND Memory Bank. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND: FSMC Bank2 NAND + * @arg SMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void SMC_DisableNAND(SMC_BANK_NAND_T bank) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->CTRL2_B.MBKEN = BIT_RESET; + } + else + { + SMC_Bank3->CTRL3_B.MBKEN = BIT_RESET; + } +} + +/*! + * @brief Enable the specified PC Card Memory Bank. + * + * @param None + * + * @retval None + */ +void SMC_EnablePCCARD(void) +{ + SMC_Bank4->CTRL4_B.MBKEN = BIT_SET; +} + +/*! + * @brief Disable the specified PC Card Memory Bank. + * + * @param None + * + * @retval None + */ +void SMC_DisablePCCARD(void) +{ + SMC_Bank4->CTRL4_B.MBKEN = BIT_RESET; +} + +/*! + * @brief Enable the SMC NAND ECC feature. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND: FSMC Bank2 NAND + * @arg SMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void SMC_EnableNANDECC(SMC_BANK_NAND_T bank) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->CTRL2 |= 0x00000040; + } + else + { + SMC_Bank3->CTRL3 |= 0x00000040; + } +} + +/*! + * @brief Disable the SMC Bank2 or Bank3 NAND ECC feature. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND: FSMC Bank2 NAND + * @arg SMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + * + */ +void SMC_DisableNANDECC(SMC_BANK_NAND_T bank) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->CTRL2 &= 0x000FFFBF; + } + else + { + SMC_Bank3->CTRL3 &= 0x000FFFBF; + } +} + +/*! + * @brief Read the error correction code register value. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND: FSMC Bank2 NAND + * @arg SMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval The value of Error Correction Code (ECC). + */ +uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank) +{ + uint32_t eccval = 0x00000000; + + if (bank == SMC_BANK2_NAND) + { + eccval = SMC_Bank2->ECCRS2; + } + else + { + eccval = SMC_Bank3->ECCRS3; + } + return eccval; +} + +/*! + * @brief Enable the specified SMC interrupts. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND : FSMC Bank2 NAND + * @arg SMC_BANK3_NAND : FSMC Bank3 NAND + * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the SMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg SMC_INT_LEVEL_HIGH : High level detection interrupt. + * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->STSINT2 |= interrupt; + } + else if (bank == SMC_BANK3_NAND) + { + SMC_Bank3->STSINT3 |= interrupt; + } + else + { + SMC_Bank4->STSINT4 |= interrupt; + } +} + +/*! + * @brief Enable the specified SMC interrupts. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND : FSMC Bank2 NAND + * @arg SMC_BANK3_NAND : FSMC Bank3 NAND + * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the SMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->STSINT2 &= ~interrupt; + } + else if (bank == SMC_BANK3_NAND) + { + SMC_Bank3->STSINT3 &= ~interrupt; + } + else + { + SMC_Bank4->STSINT4 &= ~interrupt; + } +} + +/*! + * @brief Read the status of specified SMC flag. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND : FSMC Bank2 NAND + * @arg SMC_BANK3_NAND : FSMC Bank3 NAND + * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param flag: Select the SMC interrupt sources. + * This parameter can be one of the following values: + * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag. + * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag. + * @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag. + * @arg SMC_FLAG_FIFO_EMPTY : FIFO empty Flag. + * + * @retval SET or RESET + * + */ +uint8_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag) +{ + uint32_t tmpsr = 0x00000000; + + if (bank == SMC_BANK2_NAND) + { + tmpsr = SMC_Bank2->STSINT2; + } + else if (bank == SMC_BANK3_NAND) + { + tmpsr = SMC_Bank3->STSINT3; + } + else + { + tmpsr = SMC_Bank4->STSINT4; + } + /* Get the flag status */ + if ((tmpsr & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clear the SMC's pending flags. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND : FSMC Bank2 NAND + * @arg SMC_BANK3_NAND : FSMC Bank3 NAND + * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param flag: Select the SMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag. + * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag. + * @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag. + * + * @retval None + */ +void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->STSINT2 &= ~flag; + } + else if (bank == SMC_BANK3_NAND) + { + SMC_Bank3->STSINT3 &= ~flag; + } + else + { + SMC_Bank4->STSINT4 &= ~flag; + } +} + +/*! + * @brief Read the specified SMC interrupt has occurred or not. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND : FSMC Bank2 NAND + * @arg SMC_BANK3_NAND : FSMC Bank3 NAND + * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the SMC interrupt source. + * This parameter can be one of the following values: + * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval The status of specified SMC interrupt source. + */ +uint8_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag) +{ + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + if (bank == SMC_BANK2_NAND) + { + tmpsr = SMC_Bank2->STSINT2; + } + else if (bank == SMC_BANK3_NAND) + { + tmpsr = SMC_Bank3->STSINT3; + } + else + { + tmpsr = SMC_Bank4->STSINT4; + } + + itstatus = tmpsr & flag; + itenable = tmpsr & (flag >> 3); + + if ((itstatus != RESET) && (itenable != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clear the SMC's interrupt Flag. + * + * @param bank: Select the EMMMC Bank. + * The parameter can be one of following values: + * @arg SMC_BANK2_NAND : FSMC Bank2 NAND + * @arg SMC_BANK3_NAND : FSMC Bank3 NAND + * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the SMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag) +{ + if (bank == SMC_BANK2_NAND) + { + SMC_Bank2->STSINT2 &= ~(flag >> 3); + } + else if (bank == SMC_BANK3_NAND) + { + SMC_Bank3->STSINT3 &= ~(flag >> 3); + } + else + { + SMC_Bank4->STSINT4 &= ~(flag >> 3); + } +} + +/**@} end of group SMC_Functions */ +/**@} end of group SMC_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c index 1588cc17ab..1dde4acb9c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c @@ -3,9 +3,9 @@ * * @brief This file provides all the SPI firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #include "apm32f10x_spi.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup SPI_Driver SPI Driver + * @brief SPI driver modules @{ */ -/** @addtogroup SPI_Fuctions Fuctions +/** @defgroup SPI_Functions Functions @{ */ @@ -45,7 +46,7 @@ * * @retval None */ -void SPI_I2S_Reset(SPI_T *spi) +void SPI_I2S_Reset(SPI_T* spi) { if (spi == SPI1) { @@ -65,7 +66,7 @@ void SPI_I2S_Reset(SPI_T *spi) } /*! - * @brief Config the SPI peripheral according to the specified parameters in the spiConfig + * @brief Configures the SPI peripheral according to the specified parameters in the spiConfig * * @param spi: The SPIx can be 1,2,3 * @@ -73,7 +74,7 @@ void SPI_I2S_Reset(SPI_T *spi) * * @retval None */ -void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig) +void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig) { spi->CTRL1 &= 0x3040; spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode | @@ -84,7 +85,7 @@ void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig) } /*! - * @brief Config the I2S peripheral according to the specified parameters in the spiConfig + * @brief Configures the I2S peripheral according to the specified parameters in the spiConfig * * @param spi: The SPIx can be 2,3 * @@ -92,13 +93,13 @@ void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig) * * @retval None */ -void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig) +void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) { uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1; uint32_t tmp = 0; uint32_t sysClock = 0; - /** Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */ + /* Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */ spi->I2SCFG &= 0xF040; spi->I2SPSC = 0x0002; @@ -149,7 +150,7 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig) (uint32_t)i2sConfig->length | \ (uint32_t)i2sConfig->polarity; - /** select I2S mode */ + /* select I2S mode */ spi->I2SCFG_B.MODESEL = BIT_SET; } @@ -160,7 +161,7 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig) * * @retval None */ -void SPI_ConfigStructInit(SPI_Config_T *spiConfig) +void SPI_ConfigStructInit(SPI_Config_T* spiConfig) { spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX; spiConfig->mode = SPI_MODE_SLAVE; @@ -180,7 +181,7 @@ void SPI_ConfigStructInit(SPI_Config_T *spiConfig) * * @retval None */ -void I2S_ConfigStructInit(I2S_Config_T *i2sConfig) +void I2S_ConfigStructInit(I2S_Config_T* i2sConfig) { i2sConfig->mode = I2S_MODE_SLAVE_TX; i2sConfig->standard = I2S_STANDARD_PHILLIPS; @@ -190,13 +191,13 @@ void I2S_ConfigStructInit(I2S_Config_T *i2sConfig) i2sConfig->polarity = I2S_CLKPOL_LOW; } /*! - * @brief Enables the specified SPI peripheral + * @brief Enable the specified SPI peripheral * * @param spi: The SPIx can be 1,2,3 * * @retval None */ -void SPI_Enable(SPI_T *spi) +void SPI_Enable(SPI_T* spi) { spi->CTRL1_B.SPIEN = BIT_SET; } @@ -208,19 +209,19 @@ void SPI_Enable(SPI_T *spi) * * @retval None */ -void SPI_Disable(SPI_T *spi) +void SPI_Disable(SPI_T* spi) { spi->CTRL1_B.SPIEN = BIT_RESET; } /*! - * @brief Enables the specified I2S peripheral + * @brief Enable the specified I2S peripheral * * @param spi: The I2S can be SPI2,SPI3 * * @retval None */ -void I2S_Enable(SPI_T *spi) +void I2S_Enable(SPI_T* spi) { spi->I2SCFG_B.I2SEN = BIT_SET; } @@ -232,23 +233,23 @@ void I2S_Enable(SPI_T *spi) * * @retval None */ -void I2S_Disable(SPI_T *spi) +void I2S_Disable(SPI_T* spi) { spi->I2SCFG_B.I2SEN = BIT_RESET; } /*! - * @brief Enables the SPIx/I2Sx DMA interface. + * @brief Enable the SPIx/I2Sx DMA interface. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * * @param dmaReq: specifies the SPI/I2S DMA transfer request - * The parameter can be one of following values: - * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request - * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request + * The parameter can be one of following values: + * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request * @retval None */ -void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) +void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) { if (dmaReq == SPI_I2S_DMA_REQ_TX) { @@ -261,17 +262,17 @@ void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) } /*! - * @brief Disables the SPIx/I2Sx DMA interface. + * @brief Disable the SPIx/I2Sx DMA interface. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * * @param dmaReq: specifies the SPI/I2S DMA transfer request - * The parameter can be one of following values: - * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request - * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request + * The parameter can be one of following values: + * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request * @retval None */ -void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) +void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) { if (dmaReq == SPI_I2S_DMA_REQ_TX) { @@ -284,7 +285,7 @@ void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) } /*! - * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @brief Transmit a Data through the SPIx/I2Sx peripheral. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * @@ -292,13 +293,13 @@ void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq) * * @retval None */ -void SPI_I2S_TxData(SPI_T *spi, uint16_t data) +void SPI_I2S_TxData(SPI_T* spi, uint16_t data) { spi->DATA = data; } /*! - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @brief Return the most recent received data by the SPIx/I2Sx peripheral. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * @@ -306,7 +307,7 @@ void SPI_I2S_TxData(SPI_T *spi, uint16_t data) * * @retval None */ -uint16_t SPI_I2S_RxData(SPI_T *spi) +uint16_t SPI_I2S_RxData(SPI_T* spi) { return spi->DATA; } @@ -318,7 +319,7 @@ uint16_t SPI_I2S_RxData(SPI_T *spi) * * @retval None */ -void SPI_SetSoftwareNSS(SPI_T *spi) +void SPI_SetSoftwareNSS(SPI_T* spi) { spi->CTRL1_B.ISSEL = BIT_SET; } @@ -330,19 +331,19 @@ void SPI_SetSoftwareNSS(SPI_T *spi) * * @retval None */ -void SPI_ResetSoftwareNSS(SPI_T *spi) +void SPI_ResetSoftwareNSS(SPI_T* spi) { spi->CTRL1_B.ISSEL = BIT_RESET; } /*! - * @brief Enables the specified SPI SS output + * @brief Enable the specified SPI SS output * * @param spi: The SPIx can be 1,2,3 * * @retval None */ -void SPI_EnableSSOutput(SPI_T *spi) +void SPI_EnableSSOutput(SPI_T* spi) { spi->CTRL2_B.SSOEN = BIT_SET; } @@ -354,7 +355,7 @@ void SPI_EnableSSOutput(SPI_T *spi) * * @retval None */ -void SPI_DisableSSOutput(SPI_T *spi) +void SPI_DisableSSOutput(SPI_T* spi) { spi->CTRL2_B.SSOEN = BIT_RESET; } @@ -371,7 +372,7 @@ void SPI_DisableSSOutput(SPI_T *spi) * * @retval None */ -void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length) +void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length) { spi->CTRL1_B.DFLSEL = BIT_RESET; spi->CTRL1 |= length; @@ -384,19 +385,19 @@ void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length) * * @retval None */ -void SPI_TxCRC(SPI_T *spi) +void SPI_TxCRC(SPI_T* spi) { spi->CTRL1_B.CRCNXT = BIT_SET; } /*! - * @brief Enables the specified SPI CRC value calculation of the transferred bytes + * @brief Enable the specified SPI CRC value calculation of the transferred bytes * * @param spi: The SPIx can be 1,2,3 * * @retval None */ -void SPI_EnableCRC(SPI_T *spi) +void SPI_EnableCRC(SPI_T* spi) { spi->CTRL1_B.CRCEN = BIT_SET; } @@ -407,43 +408,43 @@ void SPI_EnableCRC(SPI_T *spi) * @param spi: The SPIx can be 1,2,3 * */ -void SPI_DisableCRC(SPI_T *spi) +void SPI_DisableCRC(SPI_T* spi) { spi->CTRL1_B.CRCEN = BIT_RESET; } /*! - * @brief Reads the specified SPI transmit CRC register value + * @brief Read the specified SPI transmit CRC register value * * @param spi: The SPIx can be 1,2,3 * * @retval The SPI transmit CRC register value */ -uint16_t SPI_ReadTxCRC(SPI_T *spi) +uint16_t SPI_ReadTxCRC(SPI_T* spi) { return spi->TXCRC_B.TXCRC; } /*! - * @brief Reads the specified SPI receive CRC register value + * @brief Read the specified SPI receive CRC register value * * @param spi: The SPIx can be 1,2,3 * * @retval The SPI receive CRC register value */ -uint16_t SPI_ReadRxCRC(SPI_T *spi) +uint16_t SPI_ReadRxCRC(SPI_T* spi) { return spi->RXCRC_B.RXCRC; } /*! - * @brief Reads the specified SPI CRC Polynomial register value + * @brief Read the specified SPI CRC Polynomial register value * * @param spi: The SPIx can be 1,2,3 * * @retval The SPI CRC Polynomial register value */ -uint16_t SPI_ReadCRCPolynomial(SPI_T *spi) +uint16_t SPI_ReadCRCPolynomial(SPI_T* spi) { return spi->CRCPOLY_B.CRCPOLY; } @@ -454,12 +455,12 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T *spi) * @param spi: The SPIx can be 1,2,3 * * @param direction: Select the SPI data transfer direction - * The parameter can be one of following values: - * @arg SPI_DIRECTION_RX: Selects Rx receive direction - * @arg SPI_DIRECTION_TX: Selects Tx transmission direction + * The parameter can be one of following values: + * @arg SPI_DIRECTION_RX: Selects Rx receive direction + * @arg SPI_DIRECTION_TX: Selects Tx transmission direction * @retval None */ -void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction) +void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction) { if (direction == SPI_DIRECTION_TX) { @@ -472,58 +473,58 @@ void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction) } /*! - * @brief Enables the specified SPI/I2S interrupts. + * @brief Enable the specified SPI/I2S interrupts. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * * @param interrupt: specifies the TMR interrupts sources - * The parameter can be one of following values: - * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt - * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt - * @arg SPI_I2S_INT_ERR: Error interrupt + * The parameter can be one of following values: + * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt + * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt + * @arg SPI_I2S_INT_ERR: Error interrupt * @retval None */ -void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt) +void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) { spi->CTRL2 |= (interrupt >> 8); } /*! - * @brief Disables the specified SPI/I2S interrupts. + * @brief Disable the specified SPI/I2S interrupts. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * * @param interrupt: specifies the TMR interrupts sources - * The parameter can be one of following values: - * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt - * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt - * @arg SPI_I2S_INT_ERR: Error interrupt + * The parameter can be one of following values: + * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt + * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt + * @arg SPI_I2S_INT_ERR: Error interrupt * @retval None */ -void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt) +void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) { spi->CTRL2 &= ~(interrupt >> 8); } /*! - * @brief Checks whether the specified SPI/I2S flag is set or not. + * @brief Check whether the specified SPI/I2S flag is set or not. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * * @param flag: specifies the SPI/I2S flag to check - * The parameter can be one of following values: - * @arg SPI_FLAG_RXBNE: Receive buffer not empty flag - * @arg SPI_FLAG_TXBE: Transmit buffer empty flag - * @arg I2S_FLAG_SCHDIR: Side Channel flag - * @arg I2S_FLAG_UDR: Underrun Error flag - * @arg SPI_FLAG_CRCE: CRC Error flag - * @arg SPI_FLAG_ME: Mode Error flag - * @arg SPI_FLAG_OVR: Overrun flag - * @arg SPI_FLAG_BSY: Busy flag + * The parameter can be one of following values: + * @arg SPI_FLAG_RXBNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXBE: Transmit buffer empty flag + * @arg I2S_FLAG_SCHDIR: Side Channel flag + * @arg I2S_FLAG_UDR: Underrun Error flag + * @arg SPI_FLAG_CRCE: CRC Error flag + * @arg SPI_FLAG_ME: Mode Error flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag * * @retval SET or RESET */ -uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag) +uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag) { if ((spi->STS & flag) != RESET) { @@ -536,11 +537,11 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag) } /*! - * @brief Clears the SPIx CRC Error flag + * @brief Clear the SPIx CRC Error flag * * @param spi: The SPIx can be 1,2,3 * - * @param flag: only clears SPI_FLAG_CRCE(CRC Error flag) + * @param flag: only Clear SPI_FLAG_CRCE(CRC Error flag) * * @retval None * @@ -553,28 +554,28 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag) * a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag()) * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). */ -void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag) +void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag) { spi->STS_B.CRCEFLG = BIT_RESET; } /*! - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @brief Check whether the specified SPI/I2S interrupt has occurred or not. * * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 * * @param flag: specifies the SPI/I2S interrupt flag to check. - * The parameter can be one of following values: - * @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag - * @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag - * @arg SPI_I2S_INT_OVR: Overrun interrupt flag - * @arg SPI_INT_CRCE: CRC Error interrupt flag - * @arg SPI_INT_ME: Mode Error interrupt flag - * @arg I2S_INT_UDR: Underrun Error interrupt flag + * The parameter can be one of following values: + * @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag + * @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag + * @arg SPI_I2S_INT_OVR: Overrun interrupt flag + * @arg SPI_INT_CRCE: CRC Error interrupt flag + * @arg SPI_INT_ME: Mode Error interrupt flag + * @arg I2S_INT_UDR: Underrun Error interrupt flag * * @retval SET or RESET */ -uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag) +uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) { uint32_t intEnable; uint32_t intStatus; @@ -591,11 +592,11 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag) } /*! - * @brief Clears the SPIx CRC Error interrupt flag + * @brief Clear the SPIx CRC Error interrupt flag * * @param spi: The SPIx can be 1,2,3 * - * @param flag: only clears SPI_INT_CRCE(CRC Error interrupt flag) + * @param flag: only Clear SPI_INT_CRCE(CRC Error interrupt flag) * * @retval None * @@ -608,11 +609,11 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag) * a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag()) * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). */ -void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag) +void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) { spi->STS_B.CRCEFLG = BIT_RESET; } -/**@} end of group SPI_Fuctions*/ -/**@} end of group SPI_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group SPI_Functions */ +/**@} end of group SPI_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c index 50a1449c36..6cfb6ff572 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c @@ -3,9 +3,9 @@ * * @brief This file provides all the TMR firmware functions. * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,32 +26,33 @@ #include "apm32f10x_tmr.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup TMR_Driver TMR Driver +/** @addtogroup TMR_Driver TMR Driver + * @brief TMR driver modules @{ */ -/** @addtogroup TMR_Fuctions Fuctions +/** @defgroup TMR_Functions Functions @{ */ -static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); -static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); -static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); -static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); /*! - * @brief Deinitializes the TMRx peripheral registers to their default reset values. + * @brief Deinitialize the TMRx peripheral registers to their default reset values. * - * @param tmr: Select TMRx peripheral, The x can be 1 to 8 + * @param tmr: Clear TMRx peripheral, The x can be 1 to 8 * * @retval None * */ -void TMR_Reset(TMR_T *tmr) +void TMR_Reset(TMR_T* tmr) { if (tmr == TMR1) { @@ -96,15 +97,15 @@ void TMR_Reset(TMR_T *tmr) } /*! - * @brief Initializes the base timer through the structure + * @brief Initialize the base timer through the structure * - * @param tmr: Select TMRx peripheral, The x can be 1 to 8 + * @param tmr: Clear TMRx peripheral, The x can be 1 to 8 * * @param baseConfig: Pointer to a TMR_BaseConfig_T structure * * @retval None */ -void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig) +void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) { uint16_t temp; @@ -133,7 +134,7 @@ void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig) } /*! - * @brief Configure channel 1 according to parameters + * @brief Configures channel 1 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -141,7 +142,7 @@ void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig) * * @retval None */ -void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig) +void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig) { tmr->CCEN_B.CC1EN = BIT_RESET; @@ -165,7 +166,7 @@ void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig) } /*! - * @brief Configure channel 2 according to parameters + * @brief Configures channel 2 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -173,7 +174,7 @@ void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig) * * @retval None */ -void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig) +void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig) { tmr->CCEN_B.CC2EN = BIT_RESET; @@ -202,7 +203,7 @@ void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig) } /*! - * @brief Configure channel 3 according to parameters + * @brief Configures channel 3 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -210,7 +211,7 @@ void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig) * * @retval None */ -void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig) +void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig) { tmr->CCEN_B.CC3EN = BIT_RESET; @@ -238,7 +239,7 @@ void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig) } /*! - * @brief Configure channel 4 according to parameters + * @brief Configures channel 4 according to parameters * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -246,7 +247,7 @@ void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig) * * @retval None */ -void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig) +void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig) { tmr->CCEN_B.CC4EN = BIT_RESET; @@ -267,7 +268,7 @@ void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig) } /*! - * @brief Configure Peripheral equipment + * @brief Configures Peripheral equipment * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -275,7 +276,7 @@ void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig) * * @retval None */ -void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig) +void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig) { if (ICConfig->channel == TMR_CHANNEL_1) { @@ -308,7 +309,7 @@ void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig) * * @retval None */ -void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig) +void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig) { tmr->BDT = (BDTConfig->IMOS) << 10 | \ (BDTConfig->RMOS) << 11 | \ @@ -326,7 +327,7 @@ void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig) * * @retval None */ -void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig) +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig) { baseConfig->period = 0xFFFF; baseConfig->division = 0x0000; @@ -342,7 +343,7 @@ void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig) * * @retval None */ -void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig) +void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig) { OCConfig->mode = TMR_OC_MODE_TMRING; OCConfig->outputState = TMR_OC_STATE_DISABLE; @@ -361,7 +362,7 @@ void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig) * * @retval None */ -void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig) +void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig) { ICConfig->channel = TMR_CHANNEL_1; ICConfig->polarity = TMR_IC_POLARITY_RISING; @@ -377,7 +378,7 @@ void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig) * * @retval None */ -void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig) +void TMR_ConfigBDTStructInit(TMR_BDTConfig_T* BDTConfig) { BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE; BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE; @@ -388,6 +389,23 @@ void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig) BDTConfig->automaticOutput = TMR_AUTOMATIC_OUTPUT_DISABLE; } +/*! + * @brief Configures the Sing pulse Mode. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param singlePulseMode: specifies the Single Pulse Mode + * The parameter can be one of following values: + * @arg TMR_SPM_REPETITIVE + * @arg TMR_SPM_SINGLE + * @retval None + */ + +void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode) +{ + tmr->CTRL1_B.SPMEN = singlePulseMode; +} + /*! * @brief Enable the specified TMR peripheral * @@ -395,7 +413,7 @@ void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig) * * @retval None */ -void TMR_Enable(TMR_T *tmr) +void TMR_Enable(TMR_T* tmr) { tmr->CTRL1_B.CNTEN = ENABLE; } @@ -407,13 +425,13 @@ void TMR_Enable(TMR_T *tmr) * * @retval None */ -void TMR_Disable(TMR_T *tmr) +void TMR_Disable(TMR_T* tmr) { tmr->CTRL1_B.CNTEN = DISABLE; } /*! - * @brief Config of TMR to PWM + * @brief Configures of TMR to PWM input * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -421,7 +439,7 @@ void TMR_Disable(TMR_T *tmr) * * @retval None */ -void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig) +void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig) { uint16_t icpolarity = TMR_IC_POLARITY_RISING; uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI; @@ -467,7 +485,7 @@ void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig) * * @retval None */ -void TMR_EnablePWMOutputs(TMR_T *tmr) +void TMR_EnablePWMOutputs(TMR_T* tmr) { tmr->BDT_B.MOEN = ENABLE; } @@ -479,7 +497,7 @@ void TMR_EnablePWMOutputs(TMR_T *tmr) * * @retval None */ -void TMR_DisablePWMOutputs(TMR_T *tmr) +void TMR_DisablePWMOutputs(TMR_T* tmr) { tmr->BDT_B.MOEN = DISABLE; } @@ -495,7 +513,7 @@ void TMR_DisablePWMOutputs(TMR_T *tmr) * * @retval None */ -void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength) +void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength) { tmr->DCTRL = (uint32_t)baseAddress | (uint32_t)burstLength; } @@ -506,18 +524,18 @@ void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T * @param tmr: The TMRx can be 1 to 8 * * @param souces: specifies the TMR DMA souces - * The parameter can be any combination of following values: - * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces - * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces - * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces - * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces - * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces - * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces - * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces + * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces + * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces * @retval None * */ -void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource) +void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource) { tmr->DIEN |= dmaSource; } @@ -528,18 +546,18 @@ void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource) * @param tmr: The TMRx can be 1 to 8 * * @param souces: specifies the TMR DMA souces - * The parameter can be any combination of following values: - * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces - * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces - * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces - * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces - * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces - * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces - * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces + * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces + * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces * @retval None * */ -void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource) +void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource) { tmr->DIEN &= ~dmaSource; } @@ -551,7 +569,7 @@ void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource) * * @retval None */ -void TMR_ConfigInternalClock(TMR_T *tmr) +void TMR_ConfigInternalClock(TMR_T* tmr) { tmr->SMCTRL_B.SMFSEL = DISABLE; } @@ -562,21 +580,21 @@ void TMR_ConfigInternalClock(TMR_T *tmr) * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @param triggerSource: specifies the TMR trigger souces - * The parameter can be one of following values: - * @arg TMR_TRIGGER_SOURCE_ITR0: TMR Internal Trigger 0 - * @arg TMR_TRIGGER_SOURCE_ITR1: TMR Internal Trigger 1 - * @arg TMR_TRIGGER_SOURCE_ITR2: TMR Internal Trigger 2 - * @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3 + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_ITR0: TMR Internal Trigger 0 + * @arg TMR_TRIGGER_SOURCE_ITR1: TMR Internal Trigger 1 + * @arg TMR_TRIGGER_SOURCE_ITR2: TMR Internal Trigger 2 + * @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3 * @retval None */ -void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource) +void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) { TMR_SelectInputTrigger(tmr, triggerSource); tmr->SMCTRL_B.SMFSEL = 0x07; } /*! - * @brief Configures the TMRx Trigger as External Clock + * @brief Configures the TMRx Trigger as External Clock * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -595,7 +613,7 @@ void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSour * * @retval None */ -void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource, +void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter) { if (triggerSource == 0x06) @@ -624,7 +642,7 @@ void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource, * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 * * @param polarity: specifies the TMR IC polarity - * The parameter can be one of following values: + * The parameter can be one of following values: * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active * @@ -632,7 +650,7 @@ void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource, * * @retval None */ -void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter) { TMR_ConfigETR(tmr, prescaler, polarity, filter); @@ -662,7 +680,7 @@ void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, * * @retval None */ -void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter) { TMR_ConfigETR(tmr, prescaler, polarity, filter); @@ -689,7 +707,7 @@ void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, * * @retval None */ -void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, +void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, TMR_EXTTRG_POL_T polarity, uint16_t filter) { tmr->SMCTRL &= 0x00FF; @@ -711,18 +729,18 @@ void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler, * @arg TMR_PSC_RELOAD_IMMEDIATE: The Prescaler is loaded immediately * @retval None */ -void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode) +void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode) { tmr->PSC = prescaler; tmr->CEG_B.UEG = pscReloadMode; } /*! - * @brief Config counter mode + * @brief Configures counter mode * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * - * @param countMode:specifies the Counter Mode to be used + * @param countMode: specifies the Counter Mode to be used * The parameter can be one of following values: * @arg TMR_COUNTER_MODE_UP: Timer Up Counting Mode * @arg TMR_COUNTER_MODE_DOWN: Timer Down Counting Mode @@ -731,7 +749,7 @@ void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscRel * @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3 * @retval None */ -void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode) +void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode) { tmr->CTRL1_B.CNTDIR = BIT_RESET; tmr->CTRL1_B.CAMSEL = BIT_RESET; @@ -756,7 +774,7 @@ void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode) * * @retval None */ -void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource) +void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) { tmr->SMCTRL_B.TRGSEL = BIT_RESET; tmr->SMCTRL_B.TRGSEL = triggerSource; @@ -785,7 +803,7 @@ void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource) * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling * @retval None */ -void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, +void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, TMR_IC_POLARITY_T IC2Polarity) { tmr->SMCTRL_B.SMFSEL = BIT_RESET; @@ -812,7 +830,7 @@ void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF * @retval None */ -void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) { tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET; tmr->CCM1_COMPARE_B.OC1MOD = forcesAction; @@ -829,7 +847,7 @@ void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF * @retval None */ -void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) { tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; tmr->CCM1_COMPARE_B.OC2MOD = forcesAction; @@ -847,7 +865,7 @@ void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) * * @retval None */ -void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) { tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET; tmr->CCM2_COMPARE_B.OC3MOD = forcesAction; @@ -865,20 +883,20 @@ void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) * * @retval None */ -void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction) +void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) { tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET; tmr->CCM2_COMPARE_B.OC4MOD = forcesAction; } /*! - * @brief Enables peripheral Preload register on AUTORLD. + * @brief Enable peripheral Preload register on AUTORLD. * * @param tmr: The TMRx can be 1 to 8 * * @retval None */ -void TMR_EnableAutoReload(TMR_T *tmr) +void TMR_EnableAutoReload(TMR_T* tmr) { tmr->CTRL1_B.ARPEN = ENABLE; } @@ -890,30 +908,30 @@ void TMR_EnableAutoReload(TMR_T *tmr) * * @retval None */ -void TMR_DisableAutoReload(TMR_T *tmr) +void TMR_DisableAutoReload(TMR_T* tmr) { tmr->CTRL1_B.ARPEN = DISABLE; } /*! - * @brief Enable Selects the TMR peripheral Commutation event. + * @brief Enable Clear the TMR peripheral Commutation event. * * @param tmr: The TMRx it can be TMR1 and TMR8 * * @retval None */ -void TMR_EnableSelectCOM(TMR_T *tmr) +void TMR_EnableSelectCOM(TMR_T* tmr) { tmr->CTRL2_B.CCUSEL = ENABLE; } /*! - * @brief Disable Selects the TMR peripheral Commutation event. + * @brief Disable Clear the TMR peripheral Commutation event. * * @param tmr: The TMRx it can be TMR1 and TMR8 * * @retval None */ -void TMR_DisableSelectCOM(TMR_T *tmr) +void TMR_DisableSelectCOM(TMR_T* tmr) { tmr->CTRL2_B.CCUSEL = DISABLE; } @@ -925,7 +943,7 @@ void TMR_DisableSelectCOM(TMR_T *tmr) * * @retval None */ -void TMR_EnableCCDMA(TMR_T *tmr) +void TMR_EnableCCDMA(TMR_T* tmr) { tmr->CTRL2_B.CCDSEL = ENABLE; } @@ -937,7 +955,7 @@ void TMR_EnableCCDMA(TMR_T *tmr) * * @retval None */ -void TMR_DisableCCDMA(TMR_T *tmr) +void TMR_DisableCCDMA(TMR_T* tmr) { tmr->CTRL2_B.CCDSEL = DISABLE; } @@ -949,7 +967,7 @@ void TMR_DisableCCDMA(TMR_T *tmr) * * @retval None */ -void TMR_EnableCCPreload(TMR_T *tmr) +void TMR_EnableCCPreload(TMR_T* tmr) { tmr->CTRL2_B.CCPEN = ENABLE; } @@ -961,13 +979,13 @@ void TMR_EnableCCPreload(TMR_T *tmr) * * @retval None */ -void TMR_DisableCCPreload(TMR_T *tmr) +void TMR_DisableCCPreload(TMR_T* tmr) { tmr->CTRL2_B.CCPEN = DISABLE; } /*! - * @brief Enables or disables the peripheral Preload register on CCM1. + * @brief Enable or disable the peripheral Preload register on CCM1. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -977,13 +995,13 @@ void TMR_DisableCCPreload(TMR_T *tmr) * @arg TMR_OC_PRELOAD_ENABLE * @retval None */ -void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM1_COMPARE_B.OC1PEN = OCPreload; } /*! - * @brief Enables or disables the peripheral Preload register on CCM2. + * @brief Enable or disable the peripheral Preload register on CCM2. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -993,13 +1011,13 @@ void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_PRELOAD_ENABLE * @retval None */ -void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM1_COMPARE_B.OC2PEN = OCPreload; } /*! - * @brief Enables or disables the peripheral Preload register on CCM3. + * @brief Enable or disable the peripheral Preload register on CCM3. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1009,13 +1027,13 @@ void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_PRELOAD_ENABLE * @retval None */ -void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM2_COMPARE_B.OC3PEN = OCPreload; } /*! - * @brief Enables or disables the peripheral Preload register on CCM4. + * @brief Enable or disable the peripheral Preload register on CCM4. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1025,7 +1043,7 @@ void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_PRELOAD_ENABLE * @retval Nonee */ -void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) +void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) { tmr->CCM2_COMPARE_B.OC4PEN = OCPreload; } @@ -1041,7 +1059,7 @@ void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) { tmr->CCM1_COMPARE_B.OC1FEN = OCFast; } @@ -1057,7 +1075,7 @@ void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) { tmr->CCM1_COMPARE_B.OC2FEN = OCFast; } @@ -1073,7 +1091,7 @@ void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) { tmr->CCM2_COMPARE_B.OC3FEN = OCFast; } @@ -1089,13 +1107,13 @@ void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_FAST_ENABLE * @retval None */ -void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) +void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) { tmr->CCM2_COMPARE_B.OC4FEN = OCFast; } /*! - * @brief Clears or safeguards the OCREF1 signal on an external event + * @brief Clear or safeguards the OCREF1 signal on an external event * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1105,13 +1123,13 @@ void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM1_COMPARE_B.OC1CEN = OCClear; } /*! - * @brief Clears or safeguards the OCREF2 signal on an external event + * @brief Clear or safeguards the OCREF2 signal on an external event * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1121,13 +1139,13 @@ void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM1_COMPARE_B.OC2CEN = OCClear; } /*! - * @brief Clears or safeguards the OCREF3 signal on an external event + * @brief Clear or safeguards the OCREF3 signal on an external event * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1137,13 +1155,13 @@ void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM2_COMPARE_B.OC3CEN = OCClear; } /*! - * @brief Clears or safeguards the OCREF4 signal on an external event + * @brief Clear or safeguards the OCREF4 signal on an external event * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1153,7 +1171,7 @@ void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_CLEAR_ENABLE * @retval None */ -void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) +void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) { tmr->CCM2_COMPARE_B.OC4CEN = OCClear; } @@ -1169,13 +1187,13 @@ void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval Nonee */ -void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC1POL = polarity; } /*! - * @brief Configures the channel 1 nPolarity. + * @brief Configures the channel 1 nPolarity. * * @param tmr: The TMRx it can be TMR1 and TMR8 * @@ -1185,7 +1203,7 @@ void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) +void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) { tmr->CCEN_B.CC1NPOL = nPolarity; } @@ -1201,13 +1219,13 @@ void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC2POL = polarity; } /*! - * @brief Configures the channel 2 nPolarity. + * @brief Configures the channel 2 nPolarity. * * @param tmr: The TMRx it can be TMR1 and TMR8 * @@ -1217,7 +1235,7 @@ void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) +void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) { tmr->CCEN_B.CC2NPOL = nPolarity; } @@ -1233,13 +1251,13 @@ void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC3POL = polarity; } /*! - * @brief Configures the channel 3 nPolarity. + * @brief Configures the channel 3 nPolarity. * * @param tmr: The TMRx it can be TMR1 and TMR8 * @@ -1249,7 +1267,7 @@ void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) +void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) { tmr->CCEN_B.CC3NPOL = nPolarity; } @@ -1265,13 +1283,13 @@ void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity) * @arg TMR_OC_POLARITY_LOW: Output Compare active low * @retval None */ -void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) +void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) { tmr->CCEN_B.CC4POL = polarity; } /*! - * @brief Enables the Capture Compare Channel x. + * @brief Enable the Capture Compare Channel x. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1283,13 +1301,13 @@ void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity) * @arg TMR_CHANNEL_4: Timer Channel 4 * @retval None */ -void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel) +void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) { tmr->CCEN |= BIT_SET << channel; } /*! - * @brief Disables the Capture Compare Channel x. + * @brief Disable the Capture Compare Channel x. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1301,13 +1319,13 @@ void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel) * @arg TMR_CHANNEL_4: Timer Channel 4 * @retval None */ -void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel) +void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) { - tmr->CCEN &= BIT_RESET << channel; + tmr->CCEN &= ~(BIT_SET << channel); } /*! - * @brief Enables the Capture Compare Channelx N. + * @brief Enable the Capture Compare Channelx N. * * @param tmr: The TMRx it can be TMR1 and TMR8 * @@ -1318,13 +1336,13 @@ void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel) * @arg TMR_CHANNEL_3: Timer Channel 3 * @retval None */ -void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel) +void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) { - tmr->CCEN |= 0x04 << channel; + tmr->CCEN |= 0x04 << (channel); } /*! - * @brief Disables the Capture Compare Channelx N. + * @brief Disable the Capture Compare Channelx N. * * @param tmr: The TMRx it can be TMR1 and TMR8 * @@ -1335,9 +1353,9 @@ void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel) * @arg TMR_CHANNEL_3: Timer Channel 3 * @retval None */ -void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel) +void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) { - tmr->CCEN &= BIT_RESET << channel; + tmr->CCEN &= ~(0x04 << (channel)); } /*! @@ -1364,7 +1382,7 @@ void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel) * @arg TMR_OC_MODE_PWM2 * @retval None */ -void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) +void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) { tmr->CCEN &= BIT_RESET << channel; @@ -1393,7 +1411,7 @@ void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) * * @retval None */ -void TMR_EnableUpdate(TMR_T *tmr) +void TMR_EnableUpdate(TMR_T* tmr) { tmr->CTRL1_B.UD = DISABLE; } @@ -1405,7 +1423,7 @@ void TMR_EnableUpdate(TMR_T *tmr) * * @retval None */ -void TMR_DisableUpdate(TMR_T *tmr) +void TMR_DisableUpdate(TMR_T* tmr) { tmr->CTRL1_B.UD = ENABLE; } @@ -1421,7 +1439,7 @@ void TMR_DisableUpdate(TMR_T *tmr) * @arg TMR_UPDATE_SOURCE_REGULAR * @retval None */ -void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource) +void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource) { if (updateSource != TMR_UPDATE_SOURCE_GLOBAL) { @@ -1434,13 +1452,13 @@ void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource) } /*! - * @brief Enables Hall sensor interface. + * @brief Enable Hall sensor interface. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * * @retval None */ -void TMR_EnableHallSensor(TMR_T *tmr) +void TMR_EnableHallSensor(TMR_T* tmr) { tmr->CTRL2_B.TI1SEL = ENABLE; } @@ -1452,27 +1470,11 @@ void TMR_EnableHallSensor(TMR_T *tmr) * * @retval None */ -void TMR_DisableHallSensor(TMR_T *tmr) +void TMR_DisableHallSensor(TMR_T* tmr) { tmr->CTRL2_B.TI1SEL = DISABLE; } -/*! - * @brief Config the Sing pulse Mode. - * - * @param tmr: The TMRx can be 1 to 8 - * - * @param singlePulseMode: specifies the Single Pulse Mode - * The parameter can be one of following values: - * @arg TMR_SPM_REPETITIVE - * @arg TMR_SPM_SINGLE - * @retval None - */ -void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode) -{ - tmr->CTRL1_B.SPMEN = singlePulseMode; -} - /*! * @brief Selects the Trigger Output Mode. * @@ -1491,7 +1493,7 @@ void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode) * @arg TMR_TRGO_SOURCE_OC4REF * @retval None */ -void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource) +void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource) { tmr->CTRL2_B.MMSEL = TRGOSource; } @@ -1509,7 +1511,7 @@ void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource) * @arg TMR_SLAVE_MODE_EXTERNAL1 * @retval None */ -void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode) +void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode) { tmr->SMCTRL_B.SMFSEL = slaveMode; } @@ -1521,7 +1523,7 @@ void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode) * * @retval None */ -void TMR_EnableMasterSlaveMode(TMR_T *tmr) +void TMR_EnableMasterSlaveMode(TMR_T* tmr) { tmr->SMCTRL_B.MSMEN = ENABLE; } @@ -1533,13 +1535,13 @@ void TMR_EnableMasterSlaveMode(TMR_T *tmr) * * @retval None */ -void TMR_DisableMasterSlaveMode(TMR_T *tmr) +void TMR_DisableMasterSlaveMode(TMR_T* tmr) { tmr->SMCTRL_B.MSMEN = DISABLE; } /*! - * @brief Configs the Counter Register value + * @brief Configures the Counter Register value * * @param tmr: The TMRx can be 1 to 8 * @@ -1547,13 +1549,13 @@ void TMR_DisableMasterSlaveMode(TMR_T *tmr) * * @retval None */ -void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter) +void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter) { tmr->CNT = counter; } /*! - * @brief Configs the AutoReload Register value + * @brief Configures the AutoReload Register value * * @param tmr: The TMRx can be 1 to 8 * @@ -1561,13 +1563,13 @@ void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter) * * @retval None */ -void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload) +void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload) { tmr->AUTORLD = autoReload; } /*! - * @brief Configs the Capture Compare1 Register value + * @brief Configures the Capture Compare1 Register value * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1575,13 +1577,13 @@ void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload) * * @retval None */ -void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1) +void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1) { tmr->CC1 = compare1; } /*! - * @brief Configs the Capture Compare2 Register value + * @brief Configures the Capture Compare2 Register value * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1589,13 +1591,13 @@ void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1) * * @retval None */ -void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2) +void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2) { tmr->CC2 = compare2; } /*! - * @brief Configs the Capture Compare3 Register value + * @brief Configures the Capture Compare3 Register value * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1603,13 +1605,13 @@ void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2) * * @retval None */ -void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3) +void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3) { tmr->CC3 = compare3; } /*! - * @brief Configs the Capture Compare4 Register value + * @brief Configures the Capture Compare4 Register value * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1617,13 +1619,13 @@ void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3) * * @retval None */ -void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4) +void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4) { tmr->CC4 = compare4; } /*! - * @brief Configs the TMRx Input Capture 1 prescaler. + * @brief Configures the TMRx Input Capture 1 prescaler. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1635,7 +1637,7 @@ void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) { tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET; tmr->CCM1_CAPTURE_B.IC1PSC = prescaler; @@ -1653,14 +1655,14 @@ void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) { tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET; tmr->CCM1_CAPTURE_B.IC2PSC = prescaler; } /*! - * @brief Configs the TMRx Input Capture 3 prescaler. + * @brief Configures the TMRx Input Capture 3 prescaler. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1672,14 +1674,14 @@ void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) { tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET; tmr->CCM2_CAPTURE_B.IC3PSC = prescaler; } /*! - * @brief Configs the TMRx Input Capture 4 prescaler. + * @brief Configures the TMRx Input Capture 4 prescaler. * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1691,14 +1693,14 @@ void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) * @arg TMR_IC_PSC_8: capture is done once every 8 events * @retval None */ -void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) +void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) { tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET; tmr->CCM2_CAPTURE_B.IC4PSC = prescaler; } /*! - * @brief Configs the Clock Division value + * @brief Configures the Clock Division value * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1709,7 +1711,7 @@ void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler) * @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim * @retval None */ -void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision) +void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision) { tmr->CTRL1_B.CLKDIV = clockDivision; } @@ -1721,7 +1723,7 @@ void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision) * * @retval Capture Compare 1 Register value. */ -uint16_t TMR_ReadCaputer1(TMR_T *tmr) +uint16_t TMR_ReadCaputer1(TMR_T* tmr) { return tmr->CC1; } @@ -1733,7 +1735,7 @@ uint16_t TMR_ReadCaputer1(TMR_T *tmr) * * @retval Capture Compare 2 Register value. */ -uint16_t TMR_ReadCaputer2(TMR_T *tmr) +uint16_t TMR_ReadCaputer2(TMR_T* tmr) { return tmr->CC2; } @@ -1745,7 +1747,7 @@ uint16_t TMR_ReadCaputer2(TMR_T *tmr) * * @retval Capture Compare 3 Register value. */ -uint16_t TMR_ReadCaputer3(TMR_T *tmr) +uint16_t TMR_ReadCaputer3(TMR_T* tmr) { return tmr->CC3; } @@ -1757,7 +1759,7 @@ uint16_t TMR_ReadCaputer3(TMR_T *tmr) * * @retval Capture Compare 4 Register value. */ -uint16_t TMR_ReadCaputer4(TMR_T *tmr) +uint16_t TMR_ReadCaputer4(TMR_T* tmr) { return tmr->CC4; } @@ -1769,19 +1771,19 @@ uint16_t TMR_ReadCaputer4(TMR_T *tmr) * * @retval Counter Register value. */ -uint16_t TMR_ReadCounter(TMR_T *tmr) +uint16_t TMR_ReadCounter(TMR_T* tmr) { return tmr->CNT; } /*! - * @brief Read the TMRx Prescaler value. + * @brief Read the TMRx Prescaler value. * * @param tmr: The TMRx can be 1 to 8 * * @retval Prescaler Register value. */ -uint16_t TMR_ReadPrescaler(TMR_T *tmr) +uint16_t TMR_ReadPrescaler(TMR_T* tmr) { return tmr->PSC; } @@ -1795,7 +1797,7 @@ uint16_t TMR_ReadPrescaler(TMR_T *tmr) * The parameter can be any combination of following values: * @arg TMR_INT_UPDATE: Timer update Interrupt source * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source - * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 2 Interrupt source * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) @@ -1805,7 +1807,7 @@ uint16_t TMR_ReadPrescaler(TMR_T *tmr) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt) +void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt) { tmr->DIEN |= interrupt; } @@ -1819,7 +1821,7 @@ void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt) * The parameter can be any combination of following values: * @arg TMR_INT_UPDATE: Timer update Interrupt source * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source - * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 2 Interrupt source * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) @@ -1829,7 +1831,7 @@ void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt) +void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt) { tmr->DIEN &= ~interrupt; } @@ -1843,7 +1845,7 @@ void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt) * The parameter can be any combination of following values: * @arg TMR_EVENT_UPDATE: Timer update Interrupt source * @arg TMR_EVENT_CC1: Timer Capture Compare 1 Event source - * @arg TMR_EVENT_CC2: Timer Capture Compare 1 Event source + * @arg TMR_EVENT_CC2: Timer Capture Compare 2 Event source * @arg TMR_EVENT_CC3: Timer Capture Compare 3 Event source * @arg TMR_EVENT_CC4: Timer Capture Compare 4 Event source * @arg TMR_EVENT_COM: Timer Commutation Event source (Only for TMR1 and TMR8) @@ -1853,7 +1855,7 @@ void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt) * * @note TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE. */ -void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources) +void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources) { tmr->CEG = eventSources; } @@ -1881,13 +1883,13 @@ void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources) * * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. */ -uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag) +uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag) { return (tmr->STS & flag) ? SET : RESET; } /*! - * @brief Clears the TMR's pending flags. + * @brief Clear the TMR's pending flags. * * @param tmr: The TMRx can be 1 to 8 * @@ -1909,7 +1911,7 @@ uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag) * * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. */ -void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag) +void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag) { tmr->STS = ~flag; } @@ -1923,7 +1925,7 @@ void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag) * The parameter can be one of following values: * @arg TMR_INT_UPDATE: Timer update Interrupt source * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source - * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 2 Interrupt source * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) @@ -1933,7 +1935,7 @@ void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag) +uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag) { if (((tmr->STS & flag) != RESET) && ((tmr->DIEN & flag) != RESET)) { @@ -1946,7 +1948,7 @@ uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag) } /*! - * @brief Clears the TMR's interrupt pending bits. + * @brief Clear the TMR's interrupt pending bits. * * @param tmr: The TMRx can be 1 to 8 * @@ -1954,7 +1956,7 @@ uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag) * The parameter can be any combination following values: * @arg TMR_INT_UPDATE: Timer update Interrupt source * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source - * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 2 Interrupt source * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) @@ -1964,13 +1966,13 @@ uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag) * * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. */ -void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag) +void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag) { tmr->STS = ~flag; } /*! - * @brief Configure the TI1 as Input + * @brief Configures the TI1 as Input * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -1982,7 +1984,7 @@ void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag) * * @retval None */ -static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -2014,7 +2016,7 @@ static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin } /*! - * @brief Configure the TI2 as Input + * @brief Configures the TI2 as Input * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -2026,7 +2028,7 @@ static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None */ -static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -2058,7 +2060,7 @@ static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin } /*! - * @brief Configure the TI3 as Input + * @brief Configures the TI3 as Input * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -2070,7 +2072,7 @@ static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None */ -static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -2102,7 +2104,7 @@ static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin } /*! - * @brief Configure the TI4 as Input + * @brief Configures the TI4 as Input * * @param tmr: The TMRx can be 1 to 8 except 6 and 7 * @@ -2114,7 +2116,7 @@ static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin * * @retval None */ -static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) { uint16_t tmpchctrl = 0; @@ -2132,6 +2134,6 @@ static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin tmr->CCEN = tmpchctrl; } -/**@} end of group TMR_Fuctions*/ -/**@} end of group TMR_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group TMR_Functions */ +/**@} end of group TMR_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c index 081c50ce7a..4dcd768dbf 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c @@ -3,9 +3,9 @@ * * @brief This file provides all the USART firmware functions * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,15 +26,16 @@ #include "apm32f10x_usart.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ /** @addtogroup USART_Driver USART Driver + * @brief USART driver modules @{ */ -/** @addtogroup USART_Fuctions Fuctions +/** @defgroup USART_Functions Functions @{ */ @@ -47,7 +48,7 @@ * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Reset(USART_T *usart) +void USART_Reset(USART_T* usart) { if (USART1 == usart) { @@ -77,7 +78,7 @@ void USART_Reset(USART_T *usart) } /*! - * @brief Config the USART peripheral according to the specified parameters in the usartConfig + * @brief Configures the USART peripheral according to the specified parameters in the usartConfig * * @param uart: Select the USART or the UART peripheral * @@ -87,7 +88,7 @@ void USART_Reset(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Config(USART_T *uart, USART_Config_T *usartConfig) +void USART_Config(USART_T* uart, USART_Config_T* usartConfig) { uint32_t temp, fCLK, intDiv, fractionalDiv; @@ -132,7 +133,7 @@ void USART_Config(USART_T *uart, USART_Config_T *usartConfig) * * @retval None */ -void USART_ConfigStructInit(USART_Config_T *usartConfig) +void USART_ConfigStructInit(USART_Config_T* usartConfig) { usartConfig->baudRate = 9600; usartConfig->wordLength = USART_WORD_LEN_8B; @@ -143,17 +144,17 @@ void USART_ConfigStructInit(USART_Config_T *usartConfig) } /*! - * @brief Configuration communication clock + * @brief Configures communication clock * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * - * @param clockConfig: Pointer to a USART_clockConfig_T structure + * @param clockConfig: Pointer to a USART_clockConfig_T structure * * @retval None * * @note The usart can be USART1, USART2, USART3 */ -void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig) +void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig) { usart->CTRL2_B.CLKEN = clockConfig->clock; usart->CTRL2_B.CPHA = clockConfig->phase; @@ -164,12 +165,12 @@ void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig) /*! * @brief Fills each clockConfig member with its default value * - * @param clockConfig: Pointer to a USART_clockConfig_T structure + * @param clockConfig: Pointer to a USART_clockConfig_T structure * * @retval None * */ -void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig) +void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig) { clockConfig->clock = USART_CLKEN_DISABLE; clockConfig->phase = USART_CLKPHA_1EDGE; @@ -178,15 +179,15 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig) } /*! - * @brief Enables the specified USART peripheral + * @brief Enable the specified USART peripheral * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Enable(USART_T *usart) +void USART_Enable(USART_T* usart) { usart->CTRL1_B.UEN = BIT_SET; } @@ -194,23 +195,23 @@ void USART_Enable(USART_T *usart) /*! * @brief Disable the specified USART peripheral * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Disable(USART_T *usart) +void USART_Disable(USART_T* usart) { usart->CTRL1_B.UEN = BIT_RESET; } /*! - * @brief Enables the USART DMA interface + * @brief Enable the USART DMA interface * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * - * @param dmaReq: Specifies the DMA request + * @param dmaReq: Specifies the DMA request * This parameter can be one of the following values: * @arg USART_DMA_TX: USART DMA receive request * @arg USART_DMA_RX: USART DMA transmit request @@ -220,7 +221,7 @@ void USART_Disable(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq) +void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq) { usart->CTRL3 |= dmaReq; } @@ -228,9 +229,9 @@ void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq) /*! * @brief Disable the USART DMA interface * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * - * @param dmaReq: Specifies the DMA request + * @param dmaReq: Specifies the DMA request * This parameter can be one of the following values: * @arg USART_DMA_TX: USART DMA receive request * @arg USART_DMA_RX: USART DMA transmit request @@ -240,7 +241,7 @@ void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq) +void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq) { usart->CTRL3 &= (uint32_t)~dmaReq; } @@ -248,7 +249,7 @@ void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq) /*! * @brief Configures the address of the USART node * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * * @param address: Indicates the address of the USART node * @@ -256,7 +257,7 @@ void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_Address(USART_T *usart, uint8_t address) +void USART_Address(USART_T* usart, uint8_t address) { usart->CTRL2_B.ADDR = address; } @@ -264,18 +265,18 @@ void USART_Address(USART_T *usart, uint8_t address) /*! * @brief Selects the USART WakeUp method. * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * * @param wakeup: Specifies the selected USART auto baud rate method - * This parameter can be one of the following values: - * @arg USART_WAKEUP_IDLE_LINE: WakeUp by an idle line detection - * @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark + * This parameter can be one of the following values: + * @arg USART_WAKEUP_IDLE_LINE: WakeUp by an idle line detection + * @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup) +void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup) { usart->CTRL1_B.WUPMCFG = wakeup; } @@ -289,7 +290,7 @@ void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableMuteMode(USART_T *usart) +void USART_EnableMuteMode(USART_T* usart) { usart->CTRL1_B.RXMUTEEN = BIT_SET; } @@ -303,13 +304,13 @@ void USART_EnableMuteMode(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableMuteMode(USART_T *usart) +void USART_DisableMuteMode(USART_T* usart) { usart->CTRL1_B.RXMUTEEN = BIT_RESET; } /*! - * @brief Sets the USART LIN Break detection length + * @brief Set the USART LIN Break detection length * * @param usart: Select the USART or the UART peripheral * @@ -322,13 +323,13 @@ void USART_DisableMuteMode(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length) +void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length) { usart->CTRL2_B.LBDLCFG = length; } /*! - * @brief Enables the USART LIN MODE + * @brief Enable the USART LIN MODE * * @param usart: Select the USART or the UART peripheral * @@ -336,7 +337,7 @@ void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableLIN(USART_T *usart) +void USART_EnableLIN(USART_T* usart) { usart->CTRL2_B.LINMEN = BIT_SET; } @@ -350,13 +351,13 @@ void USART_EnableLIN(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableLIN(USART_T *usart) +void USART_DisableLIN(USART_T* usart) { usart->CTRL2_B.LINMEN = BIT_RESET; } /*! - * @brief Transmitter Enable + * @brief Transmitter enable * * @param usart: Select the USART or the UART peripheral * @@ -364,13 +365,13 @@ void USART_DisableLIN(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableTx(USART_T *usart) +void USART_EnableTx(USART_T* usart) { usart->CTRL1_B.TXEN = BIT_SET; } /*! - * @brief Transmitter Disable + * @brief Transmitter disable * * @param usart: Select the USART or the UART peripheral * @@ -378,7 +379,7 @@ void USART_EnableTx(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableTx(USART_T *usart) +void USART_DisableTx(USART_T* usart) { usart->CTRL1_B.TXEN = BIT_RESET; } @@ -392,7 +393,7 @@ void USART_DisableTx(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableRx(USART_T *usart) +void USART_EnableRx(USART_T* usart) { usart->CTRL1_B.RXEN = BIT_SET; } @@ -406,7 +407,7 @@ void USART_EnableRx(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableRx(USART_T *usart) +void USART_DisableRx(USART_T* usart) { usart->CTRL1_B.RXEN = BIT_RESET; } @@ -416,19 +417,19 @@ void USART_DisableRx(USART_T *usart) * * @param usart: Select the USART or the UART peripheral * - * @param data: the data to transmit + * @param data: the data to transmit * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_TxData(USART_T *usart, uint16_t data) +void USART_TxData(USART_T* usart, uint16_t data) { usart->DATA_B.DATA = data; } /*! - * @brief Returns the most recent received data + * @brief Return the most recent received data * * @param usart: Select the USART or the UART peripheral * @@ -436,7 +437,7 @@ void USART_TxData(USART_T *usart, uint16_t data) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -uint16_t USART_RxData(USART_T *usart) +uint16_t USART_RxData(USART_T* usart) { return (uint16_t)(usart->DATA_B.DATA); } @@ -450,15 +451,15 @@ uint16_t USART_RxData(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_TxBreak(USART_T *usart) +void USART_TxBreak(USART_T* usart) { usart->CTRL1_B.TXBF = BIT_SET; } /*! - * @brief Sets the specified USART guard time + * @brief Set the specified USART guard time * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * * @param guardTime: Specifies the guard time * @@ -466,29 +467,29 @@ void USART_TxBreak(USART_T *usart) * * @note The usart can be USART1, USART2, USART3 */ -void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime) +void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime) { usart->GTPSC_B.GRDT = guardTime; } /*! - * @brief Sets the system clock divider number + * @brief Set the system clock divider number * * @param usart: Select the USART or the UART peripheral * - * @param div: specifies the divider number + * @param div: specifies the divider number * * @retval None * * @note The usart can be USART1, USART2, USART3 */ -void USART_ConfigPrescaler(USART_T *usart, uint8_t div) +void USART_ConfigPrescaler(USART_T* usart, uint8_t div) { usart->GTPSC_B.PSC = div; } /*! - * @brief Enables the USART Smart Card mode + * @brief Enable the USART Smart Card mode * * @param usart: Select the USART or the UART peripheral * @@ -496,7 +497,7 @@ void USART_ConfigPrescaler(USART_T *usart, uint8_t div) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_EnableSmartCard(USART_T *usart) +void USART_EnableSmartCard(USART_T* usart) { usart->CTRL3_B.SCEN = BIT_SET; } @@ -510,13 +511,13 @@ void USART_EnableSmartCard(USART_T *usart) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_DisableSmartCard(USART_T *usart) +void USART_DisableSmartCard(USART_T* usart) { usart->CTRL3_B.SCEN = BIT_RESET; } /*! - * @brief Enables NACK transmission + * @brief Enable NACK transmission * * @param usart: Select the USART or the UART peripheral * @@ -524,7 +525,7 @@ void USART_DisableSmartCard(USART_T *usart) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_EnableSmartCardNACK(USART_T *usart) +void USART_EnableSmartCardNACK(USART_T* usart) { usart->CTRL3_B.SCNACKEN = BIT_SET; } @@ -538,13 +539,13 @@ void USART_EnableSmartCardNACK(USART_T *usart) * * @note The Smart Card mode is not available for UART4 and UART5 */ -void USART_DisableSmartCardNACK(USART_T *usart) +void USART_DisableSmartCardNACK(USART_T* usart) { usart->CTRL3_B.SCNACKEN = BIT_RESET; } /*! - * @brief Enables USART Half Duplex communication + * @brief Enable USART Half Duplex communication * * @param usart: Select the USART or the UART peripheral * @@ -552,7 +553,7 @@ void USART_DisableSmartCardNACK(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableHalfDuplex(USART_T *usart) +void USART_EnableHalfDuplex(USART_T* usart) { usart->CTRL3_B.HDEN = BIT_SET; } @@ -566,7 +567,7 @@ void USART_EnableHalfDuplex(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableHalfDuplex(USART_T *usart) +void USART_DisableHalfDuplex(USART_T* usart) { usart->CTRL3_B.HDEN = BIT_RESET; } @@ -574,23 +575,23 @@ void USART_DisableHalfDuplex(USART_T *usart) /*! * @brief Configures the USART's IrDA interface * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * * @param IrDAMode: Specifies the IrDA mode - * This parameter can be one of the following values: - * @arg USART_IRDALP_NORMAL: Normal - * @arg USART_IRDALP_LOWPOWER: Low-Power + * This parameter can be one of the following values: + * @arg USART_IRDALP_NORMAL: Normal + * @arg USART_IRDALP_LOWPOWER: Low-Power * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode) +void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode) { usart->CTRL3_B.IRLPEN = IrDAMode; } /*! - * @brief Enables the USART's IrDA interface + * @brief Enable the USART's IrDA interface * * @param usart: Select the USART or the UART peripheral * @@ -598,7 +599,7 @@ void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableIrDA(USART_T *usart) +void USART_EnableIrDA(USART_T* usart) { usart->CTRL3_B.IREN = BIT_SET; } @@ -612,7 +613,7 @@ void USART_EnableIrDA(USART_T *usart) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableIrDA(USART_T *usart) +void USART_DisableIrDA(USART_T* usart) { usart->CTRL3_B.IREN = BIT_RESET; } @@ -620,24 +621,24 @@ void USART_DisableIrDA(USART_T *usart) /*! * @brief Enable the specified USART interrupts * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * - * @param interrupt: Specifies the USART interrupts sources - * The parameter can be one of following values: - * @arg USART_INT_PE: Parity error interrupt - * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt - * @arg USART_INT_TXC: Transmission complete interrupt - * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt - * @arg USART_INT_IDLE: Idle line detection interrupt - * @arg USART_INT_LBD: LIN break detection interrupt - * @arg USART_INT_CTS: CTS change interrupt - * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_PE: Parity error interrupt + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt) +void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt) { uint32_t temp; @@ -660,26 +661,26 @@ void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt) } /*! - * @brief Disables the specified USART interrupts + * @brief Disable the specified USART interrupts * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * - * @param interrupt: Specifies the USART interrupts sources - * The parameter can be one of following values: - * @arg USART_INT_PE: Parity error interrupt - * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt - * @arg USART_INT_TXC: Transmission complete interrupt - * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt - * @arg USART_INT_IDLE: Idle line detection interrupt - * @arg USART_INT_LBD: LIN break detection interrupt - * @arg USART_INT_CTS: CTS change interrupt - * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_PE: Parity error interrupt + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt) +void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt) { uint32_t temp; @@ -706,45 +707,45 @@ void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt) * * @param usart: Select the USART or the UART peripheral * - * @param flag: Specifies the flag to check - * The parameter can be one of following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXBE: Transmit data buffer empty flag - * @arg USART_FLAG_TXC: Transmission Complete flag - * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_OVRE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag + * @param flag: Specifies the flag to check + * The parameter can be one of following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXBE: Transmit data buffer empty flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_OVRE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag * * @retval The new state of flag (SET or RESET) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag) +uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag) { return (usart->STS & flag) ? SET : RESET; } /*! - * @brief Clears the USARTx's pending flags + * @brief Clear the USARTx's pending flags * - * @param usart: Select the USART or the UART peripheral + * @param usart: Select the USART or the UART peripheral * - * @param flag: Specifies the flag to clear - * The parameter can be one of following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXC: Transmission Complete flag - * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * @param flag: Specifies the flag to clear + * The parameter can be one of following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag) +void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag) { usart->STS &= (uint32_t)~flag; } @@ -755,23 +756,23 @@ void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag) * @param usart: Select the USART or the UART peripheral * * @param flag: Specifies the USART interrupt source to check - * The parameter can be one of following values: - * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt - * @arg USART_INT_TXC: Transmission complete interrupt - * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt - * @arg USART_INT_IDLE: Idle line detection interrupt - * @arg USART_INT_LBD: LIN break detection interrupt - * @arg USART_INT_CTS: CTS change interrupt - * @arg USART_INT_OVRE: OverRun Error interruptpt - * @arg USART_INT_NE: Noise Error interrupt - * @arg USART_INT_FE: Framing Error interrupt - * @arg USART_INT_PE: Parity error interrupt + * The parameter can be one of following values: + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_OVRE: OverRun Error interruptpt + * @arg USART_INT_NE: Noise Error interrupt + * @arg USART_INT_FE: Framing Error interrupt + * @arg USART_INT_PE: Parity error interrupt * * @retval The new state of flag (SET or RESET) * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag) +uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag) { uint32_t itFlag, srFlag; @@ -801,22 +802,22 @@ uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag) } /*! - * @brief Clears the USART interrupt pending bits + * @brief Clear the USART interrupt pending bits * * @param usart: Select the USART or the UART peripheral * - * @param flag: Specifies the interrupt pending bit to clear - * The parameter can be one of following values: - * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt - * @arg USART_INT_TXC: Transmission complete interrupt - * @arg USART_INT_LBD: LIN break detection interrupt - * @arg USART_INT_CTS: CTS change interrupt + * @param flag: Specifies the interrupt pending bit to clear + * The parameter can be one of following values: + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt * * @retval None * * @note The usart can be USART1, USART2, USART3, UART4 and UART5 */ -void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag) +void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag) { uint32_t srFlag; @@ -826,6 +827,6 @@ void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag) usart->STS &= (uint32_t)~srFlag; } -/**@} end of group USART_Fuctions*/ -/**@} end of group USART_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group USART_Functions */ +/**@} end of group USART_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c index e7a65ea69d..93e6a7e4dd 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c @@ -3,9 +3,9 @@ * * @brief This file contains all the functions for the WWDT peripheral * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -26,24 +26,25 @@ #include "apm32f10x_wwdt.h" #include "apm32f10x_rcm.h" -/** @addtogroup Peripherals_Library Standard Peripheral Library +/** @addtogroup APM32F10x_StdPeriphDriver @{ */ -/** @addtogroup WWDT_Driver WWDT Driver +/** @defgroup WWDT_Driver WWDT Driver + * @brief WWDT driver modules @{ */ -/** @addtogroup WWDT_Fuctions Fuctions +/** @defgroup WWDT_Functions Functions @{ */ /*! - * @brief Reset the WWDT peripheral registers + * @brief Reset the WWDT peripheral registers * - * @param None + * @param None * - * @retval None + * @retval None */ void WWDT_Reset(void) { @@ -52,16 +53,16 @@ void WWDT_Reset(void) } /*! - * @brief Config the WWDT Timebase + * @brief Configures the WWDT Timebase * - * @param timebase: WWDT Prescaler - * The parameter can be one of following values: - * @arg WWDT_TIME_BASE_1: WWDT counter clock = (PCLK1/4096)/1 - * @arg WWDT_TIME_BASE_2: WWDT counter clock = (PCLK1/4096)/2 - * @arg WWDT_TIME_BASE_4: WWDT counter clock = (PCLK1/4096)/4 - * @arg WWDT_TIME_BASE_8: WWDT counter clock = (PCLK1/4096)/8 + * @param timebase: WWDT Prescaler + * The parameter can be one of following values: + * @arg WWDT_TIME_BASE_1: WWDT counter clock = (PCLK1/4096)/1 + * @arg WWDT_TIME_BASE_2: WWDT counter clock = (PCLK1/4096)/2 + * @arg WWDT_TIME_BASE_4: WWDT counter clock = (PCLK1/4096)/4 + * @arg WWDT_TIME_BASE_8: WWDT counter clock = (PCLK1/4096)/8 * - * @retval None + * @retval None */ void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase) { @@ -73,13 +74,13 @@ void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase) } /*! - * @brief Config the WWDT Window data + * @brief Configures the WWDT Window data * - * @param windowdata: window data which compare with the downcounter + * @param windowdata: window data which compare with the downcounter * - * @retval None + * @retval None * - * @note The windowdata must be lower than 0x80 + * @note The windowdata must be lower than 0x80 */ void WWDT_ConfigWindowData(uint8_t windowData) { @@ -91,7 +92,7 @@ void WWDT_ConfigWindowData(uint8_t windowData) } /*! - * @brief Config the WWDT counter value + * @brief Configures the WWDT counter value * * @param counter: Specifies the watchdog counter value * @@ -105,11 +106,11 @@ void WWDT_ConfigCounter(uint8_t counter) } /*! - * @brief Enable the WWDT Early Wakeup interrupt + * @brief Enable the WWDT Early Wakeup interrupt * - * @param None + * @param None * - * @retval None + * @retval None */ void WWDT_EnableEWI(void) { @@ -117,13 +118,13 @@ void WWDT_EnableEWI(void) } /*! - * @brief Enable WWDT and set the counter value + * @brief Enable WWDT and set the counter value * - * @param counter: the window watchdog counter value + * @param counter: the window watchdog counter value * - * @retval None + * @retval None * - * @note The counter between 0x40 and 0x7F + * @note The counter between 0x40 and 0x7F */ void WWDT_Enable(uint8_t counter) { @@ -131,11 +132,11 @@ void WWDT_Enable(uint8_t counter) } /*! - * @brief Read the Early Wakeup interrupt flag + * @brief Read the Early Wakeup interrupt flag * - * @param None + * @param None * - * @retval the state of the Early Wakeup interrupt flagte + * @retval the state of the Early Wakeup interrupt flagte */ uint8_t WWDT_ReadFlag(void) { @@ -143,17 +144,17 @@ uint8_t WWDT_ReadFlag(void) } /*! - * @brief Clear the Early Wakeup interrupt flag + * @brief Clear the Early Wakeup interrupt flag * - * @param None + * @param None * - * @retval None + * @retval None */ void WWDT_ClearFlag(void) { WWDT->STS_B.EWIFLG = RESET; } -/**@} end of group WWDT_Fuctions*/ -/**@} end of group WWDT_Driver*/ -/**@} end of group Peripherals_Library*/ +/**@} end of group WWDT_Functions */ +/**@} end of group WWDT_Driver */ +/**@} end of group APM32F10x_StdPeriphDriver */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h index cd374afaef..67bda4ef3c 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.0.4 - * @date 09. April 2018 + * @version V5.4.1 + * @date 27. May 2021 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -113,6 +113,826 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ########################### Core Function Access ########################### */ @@ -123,7 +943,7 @@ /** \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) @@ -134,7 +954,7 @@ __STATIC_FORCEINLINE void __enable_irq(void) /** \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) @@ -181,6 +1001,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); } @@ -193,6 +1014,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); } #endif @@ -383,7 +1205,7 @@ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } @@ -398,7 +1220,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif @@ -433,7 +1255,7 @@ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) @@ -444,7 +1266,7 @@ __STATIC_FORCEINLINE void __enable_fault_irq(void) /** \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) @@ -810,723 +1632,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) /*@} end of CMSIS_Core_RegAccFunctions */ -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @@ -1547,7 +1652,7 @@ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1555,7 +1660,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1571,7 +1676,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1579,7 +1684,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1596,7 +1701,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1604,7 +1709,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1620,7 +1725,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1628,7 +1733,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1645,7 +1750,7 @@ __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1653,7 +1758,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1669,7 +1774,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1677,7 +1782,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1693,7 +1798,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1701,7 +1806,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1717,7 +1822,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1725,7 +1830,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1741,7 +1846,7 @@ __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1749,7 +1854,7 @@ __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1765,7 +1870,7 @@ __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1773,7 +1878,7 @@ __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1789,7 +1894,7 @@ __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1797,7 +1902,7 @@ __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1813,7 +1918,7 @@ __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1821,7 +1926,7 @@ __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1829,7 +1934,7 @@ __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1837,21 +1942,23 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } -#define __SSAT16(ARG1,ARG2) \ +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) -#define __USAT16(ARG1,ARG2) \ +#define __USAT16(ARG1, ARG2) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) @@ -1859,7 +1966,7 @@ __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } @@ -1867,7 +1974,7 @@ __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1875,18 +1982,41 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -2043,8 +2173,9 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) return(result); } -#if 0 + #define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ @@ -2052,6 +2183,7 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) }) #define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ @@ -2060,19 +2192,13 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) -#endif -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h index d0466dc46f..20e6c0f2be 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h @@ -5,9 +5,9 @@ * * @details This file contains all the peripheral register's definitions, bits definitions and memory mapping * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -17,7 +17,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,209 +25,293 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __APM32F10X_H #define __APM32F10X_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /*! * APM32F10X_LD: APM32 Low density devices, the Flash memory density ranges between 16 and 32 Kbytes. * APM32F10X_MD: APM32 Medium density devices, the Flash memory density ranges between 64 and 128 Kbytes. * APM32F10X_HD: APM32 High density devices, the Flash memory density ranges between 256 and 512 Kbytes. + * APM32F10X_CL: APM32 Connectivity line devices, such as APM32F105xx and APM32F107xx serial devices. */ -#if !defined (APM32F10X_LD) && !defined (APM32F10X_MD) && !defined (APM32F10X_HD) +#if !defined (APM32F10X_LD) && !defined (APM32F10X_MD) && !defined (APM32F10X_HD) && !defined (APM32F10X_CL) #error "Please select a the target APM32F10x device used in your application (in apm32f10x.h file)" #endif +/** @addtogroup CMSIS + @{ +*/ + +/** @addtogroup APM32F10x + * @brief Peripheral Access Layer + @{ +*/ + +/** @defgroup HSE_Macros + @{ +*/ + /** * @brief Define Value of the External oscillator in Hz */ #ifndef HSE_VALUE - #define HSE_VALUE ((uint32_t)8000000) +#ifndef APM32F10X_CL +#define HSE_VALUE ((uint32_t)8000000) +#else +#define HSE_VALUE ((uint32_t)25000000) +#endif #endif -/** Time out for HSE start up */ +/* Time out for HSE start up */ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) -/** Value of the Internal oscillator in Hz */ +/* Value of the Internal oscillator in Hz */ #define HSI_VALUE ((uint32_t)8000000) +/**@} end of group HSE_Macros */ + +/** @defgroup APM32F10x_StdPeripheral_Library_Version + @{ +*/ + /** * @brief APM32F10x Standard Peripheral Library version number */ #define __APM32F10X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __APM32F10X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __APM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __APM32F10X_STDPERIPH_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */ #define __APM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __APM32F10X_STDPERIPH_VERSION ( (__APM32F10X_STDPERIPH_VERSION_MAIN << 24)\ |(__APM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ |(__APM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ |(__APM32F10X_STDPERIPH_VERSION_RC)) +/**@} end of group APM32F0xx_StdPeripheral_Library_Version */ -/** APM32 devices does not provide an MPU */ - #define __MPU_PRESENT 0 -/** APM32 uses 4 Bits for the Priority Levels */ +/** @defgroup Configuraion_for_CMSIS + @{ +*/ + +/* APM32 devices does not provide an MPU */ +#define __MPU_PRESENT 0 +/* APM32 uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4 -/** Set to 1 if different SysTick Config is used */ +/* Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0 +/**@} end of group Configuraion_for_CMSIS */ + +/** @defgroup Peripheral_Enumerations + @{ +*/ + /** * @brief APM32F10x Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum IRQn { -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** APM32 specific Interrupt Numbers *********************************************************/ - WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EINT Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCM_IRQn = 5, /*!< RCM global Interrupt */ - EINT0_IRQn = 6, /*!< EINT Line0 Interrupt */ - EINT1_IRQn = 7, /*!< EINT Line1 Interrupt */ - EINT2_IRQn = 8, /*!< EINT Line2 Interrupt */ - EINT3_IRQn = 9, /*!< EINT Line3 Interrupt */ - EINT4_IRQn = 10, /*!< EINT Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + /****** APM32 specific Interrupt Numbers *********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EINT Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCM_IRQn = 5, /*!< RCM global Interrupt */ + EINT0_IRQn = 6, /*!< EINT Line0 Interrupt */ + EINT1_IRQn = 7, /*!< EINT Line1 Interrupt */ + EINT2_IRQn = 8, /*!< EINT Line2 Interrupt */ + EINT3_IRQn = 9, /*!< EINT Line3 Interrupt */ + EINT4_IRQn = 10, /*!< EINT Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ #if defined (APM32F10X_LD) - /** APM32F10X Low-density devices specific Interrupt Numbers */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ - USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ - TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ - TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ - TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ - TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ - TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ - USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ - FPU_IRQn = 43, /*!< FPU Global Interrupt */ - QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ - USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ - USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + /* APM32F10X Low-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ #elif defined (APM32F10X_MD) - /** APM32F10X Medium-density devices specific Interrupt Numbers */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ - USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ - TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ - TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ - TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ - TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ - TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ - TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ - USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ - FPU_IRQn = 43, /*!< FPU Global Interrupt */ - QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ - USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ - USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + /* APM32F10X Medium-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ #elif defined (APM32F10X_HD) - /** APM32F10X High-density devices specific Interrupt Numbers */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ - USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ - TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ - TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ - TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ - TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ - TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ - TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ - USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ - TMR8_BRK_IRQn = 43, /*!< TMR8 Break Interrupt */ - TMR8_UP_IRQn = 44, /*!< TMR8 Update Interrupt */ - TMR8_TRG_COM_IRQn = 45, /*!< TMR8 Trigger and Commutation Interrupt */ - TMR8_CC_IRQn = 46, /*!< TMR8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - EMMC_IRQn = 48, /*!< EMMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ - TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ - USBD2_HP_CAN2_TX_IRQn = 61, /*!< USB Device 2 High Priority or CAN2 TX Interrupts */ - USBD2_LP_CAN2_RX0_IRQn = 62, /*!< USB Device 2 Low Priority or CAN2 RX0 Interrupts */ - CAN2_RX1_IRQn = 63, /*!< CAN2 RX1 Interrupts */ - CAN2_SCE_IRQn = 64, /*!< CAN2 SCE Interrupts */ + /* APM32F10X High-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + TMR8_BRK_IRQn = 43, /*!< TMR8 Break Interrupt */ + TMR8_UP_IRQn = 44, /*!< TMR8 Update Interrupt */ + TMR8_TRG_COM_IRQn = 45, /*!< TMR8 Trigger and Commutation Interrupt */ + TMR8_CC_IRQn = 46, /*!< TMR8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + EMMC_IRQn = 48, /*!< EMMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + USBD2_HP_CAN2_TX_IRQn = 61, /*!< USB Device 2 High Priority or CAN2 TX Interrupts */ + USBD2_LP_CAN2_RX0_IRQn = 62, /*!< USB Device 2 Low Priority or CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 63, /*!< CAN2 RX1 Interrupts */ + CAN2_SCE_IRQn = 64, /*!< CAN2 SCE Interrupts */ +#elif defined (APM32F10X_CL) + /* APM32F10X Connectivity-line devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< ETH global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< ETH Wake up Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupts */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupts */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupts */ + OTG_FS_IRQn = 67, /*!< OTG FS Interrupts */ #endif } IRQn_Type; -/** - * @} - */ +/**@} end of group Peripheral_Enumerations */ + +/* Includes */ #include "core_cm3.h" #include "system_apm32f10x.h" #include +/** @defgroup Exported_Types + @{ +*/ typedef int32_t s32; typedef int16_t s16; @@ -262,13 +346,13 @@ typedef __I uint16_t vuc16; typedef __I uint8_t vuc8; #ifndef __IM - #define __IM __I +#define __IM __I #endif #ifndef __OM - #define __OM __O +#define __OM __O #endif #ifndef __IOM - #define __IOM __IO +#define __IOM __IO #endif enum {BIT_RESET, BIT_SET}; @@ -284,12 +368,18 @@ enum {ERROR, SUCCESS}; #pragma anon_unions #endif +/**@} end of group Exported_types */ + +/** @defgroup Peripheral_registers_structures + @{ +*/ + /** * @brief Reset and clock management unit (RCM) */ typedef struct { - /** Clock control register */ + /* Clock control register */ union { __IOM uint32_t CTRL; @@ -306,13 +396,17 @@ typedef struct __IOM uint32_t HSEBCFG : 1; __IOM uint32_t CSSEN : 1; __IM uint32_t RESERVED2 : 4; - __IOM uint32_t PLLEN : 1; - __IM uint32_t PLLRDYFLG : 1; - __IM uint32_t RESERVED3 : 6; + __IOM uint32_t PLL1EN : 1; + __IM uint32_t PLL1RDYFLG : 1; + __IOM uint32_t PLL2EN : 1; + __IM uint32_t PLL2RDYFLG : 1; + __IOM uint32_t PLL3EN : 1; + __IM uint32_t PLL3RDYFLG : 1; + __IM uint32_t RESERVED3 : 2; } CTRL_B; }; - /** Clock configuration register */ + /* Clock configuration register */ union { __IOM uint32_t CFG; @@ -325,17 +419,26 @@ typedef struct __IOM uint32_t APB1PSC : 3; __IOM uint32_t APB2PSC : 3; __IOM uint32_t ADCPSC : 2; - __IOM uint32_t PLLSRCSEL : 1; + __IOM uint32_t PLL1SRCSEL : 1; +#ifdef APM32F10X_CL + __IOM uint32_t PLLPSC1L : 1; + __IOM uint32_t PLL1MULCFG : 4; + __IOM uint32_t OTGFSPSC : 2; + __IOM uint32_t MCOSEL : 4; + __IM uint32_t RESERVED : 4; +#else __IOM uint32_t PLLHSEPSC : 1; - __IOM uint32_t PLLMULCFG : 4; + __IOM uint32_t PLL1MULCFG : 4; __IOM uint32_t USBDPSC : 2; __IOM uint32_t MCOSEL : 3; __IOM uint32_t FPUPSC : 1; - __IM uint32_t RESERVED : 4; + __IOM uint32_t SDRAMPSC : 2; + __IM uint32_t RESERVED : 2; +#endif } CFG_B; } ; - /** Clock interrupt control register */ + /* Clock interrupt control register */ union { __IOM uint32_t INT; @@ -346,177 +449,187 @@ typedef struct __IM uint32_t LSERDYFLG : 1; __IM uint32_t HSIRDYFLG : 1; __IM uint32_t HSERDYFLG : 1; - __IM uint32_t PLLRDYFLG : 1; - __IM uint32_t RESERVED1 : 2; - __IM uint32_t CSSIF : 1; + __IM uint32_t PLL1RDYFLG : 1; + __IM uint32_t PLL2RDYFLG : 1; + __IM uint32_t PLL3RDYFLG : 1; + __IM uint32_t CSSFLG : 1; __IOM uint32_t LSIRDYEN : 1; __IOM uint32_t LSERDYEN : 1; __IOM uint32_t HSIRDYEN : 1; __IOM uint32_t HSERDYEN : 1; - __IOM uint32_t PLLRDYEN : 1; - __IM uint32_t RESERVED2 : 3; + __IOM uint32_t PLL1RDYEN : 1; + __IOM uint32_t PLL2RDYEN : 1; + __IOM uint32_t PLL3RDYEN : 1; + __IM uint32_t RESERVED1 : 1; __OM uint32_t LSIRDYCLR : 1; __OM uint32_t LSERDYCLR : 1; __OM uint32_t HSIRDYCLR : 1; __OM uint32_t HSERDYCLR : 1; - __OM uint32_t PLLRDYCLR : 1; - __IM uint32_t RESERVED3 : 2; + __OM uint32_t PLL1RDYCLR : 1; + __OM uint32_t PLL2RDYCLR : 1; + __OM uint32_t PLL3RDYCLR : 1; __OM uint32_t CSSCLR : 1; - __IM uint32_t RESERVED4 : 8; + __IM uint32_t RESERVED2 : 8; } INT_B; } ; - /** APB2 peripheral reset register */ + /* APB2 peripheral reset register */ union { __IOM uint32_t APB2RST; struct { - __IOM uint32_t AFIO : 1; + __IOM uint32_t AFIORST : 1; __IM uint32_t RESERVED1 : 1; - __IOM uint32_t PA : 1; - __IOM uint32_t PB : 1; - __IOM uint32_t PC : 1; - __IOM uint32_t PD : 1; - __IOM uint32_t PE : 1; - __IOM uint32_t PF : 1; - __IOM uint32_t PG : 1; - __IOM uint32_t ADC1 : 1; - __IOM uint32_t ADC2 : 1; - __IOM uint32_t TMR1 : 1; - __IOM uint32_t SPI1 : 1; - __IOM uint32_t TMR8 : 1; - __IOM uint32_t USART1 : 1; - __IOM uint32_t ADC3 : 1; + __IOM uint32_t PARST : 1; + __IOM uint32_t PBRST : 1; + __IOM uint32_t PCRST : 1; + __IOM uint32_t PDRST : 1; + __IOM uint32_t PERST : 1; + __IOM uint32_t PFRST : 1; + __IOM uint32_t PGRST : 1; + __IOM uint32_t ADC1RST : 1; + __IOM uint32_t ADC2RST : 1; + __IOM uint32_t TMR1RST : 1; + __IOM uint32_t SPI1RST : 1; + __IOM uint32_t TMR8RST : 1; + __IOM uint32_t USART1RST : 1; + __IOM uint32_t ADC3RST : 1; __IM uint32_t RESERVED2 : 16; } APB2RST_B; } ; - /** APB1 peripheral reset register */ + /* APB1 peripheral reset register */ union { __IOM uint32_t APB1RST; struct { - __IOM uint32_t TMR2 : 1; - __IOM uint32_t TMR3 : 1; - __IOM uint32_t TMR4 : 1; - __IOM uint32_t TMR5 : 1; - __IOM uint32_t TMR6 : 1; - __IOM uint32_t TMR7 : 1; + __IOM uint32_t TMR2RST : 1; + __IOM uint32_t TMR3RST : 1; + __IOM uint32_t TMR4RST : 1; + __IOM uint32_t TMR5RST : 1; + __IOM uint32_t TMR6RST : 1; + __IOM uint32_t TMR7RST : 1; __IM uint32_t RESERVED1 : 5; - __IOM uint32_t WWDT : 1; + __IOM uint32_t WWDTRST : 1; __IM uint32_t RESERVED2 : 2; - __IOM uint32_t SPI2 : 1; - __IOM uint32_t SPI3 : 1; + __IOM uint32_t SPI2RST : 1; + __IOM uint32_t SPI3RST : 1; __IM uint32_t RESERVED3 : 1; - __IOM uint32_t USART2 : 1; - __IOM uint32_t USART3 : 1; - __IOM uint32_t UART4 : 1; - __IOM uint32_t UART5 : 1; - __IOM uint32_t I2C1 : 1; - __IOM uint32_t I2C2 : 1; - __IOM uint32_t USBD : 1; + __IOM uint32_t USART2RST : 1; + __IOM uint32_t USART3RST : 1; + __IOM uint32_t UART4RST : 1; + __IOM uint32_t UART5RST : 1; + __IOM uint32_t I2C1RST : 1; + __IOM uint32_t I2C2RST : 1; + __IOM uint32_t USBDRST : 1; __IM uint32_t RESERVED4 : 1; - __IOM uint32_t CAN1 : 1; - __IM uint32_t CAN2 : 1; - __IOM uint32_t BAKP : 1; - __IOM uint32_t PMU : 1; - __IOM uint32_t DAC : 1; + __IOM uint32_t CAN1RST : 1; + __IOM uint32_t CAN2RST : 1; + __IOM uint32_t BAKPRST : 1; + __IOM uint32_t PMURST : 1; + __IOM uint32_t DACRST : 1; __IM uint32_t RESERVED5 : 2; } APB1RST_B; } ; - /** AHB clock enable register */ + /* AHB clock enable register */ union { __IOM uint32_t AHBCLKEN; struct { - __IOM uint32_t DMA1 : 1; - __IOM uint32_t DMA2 : 1; - __IOM uint32_t SRAM : 1; - __IOM uint32_t FPU : 1; - __IOM uint32_t FMC : 1; - __IOM uint32_t QSPI : 1; - __IOM uint32_t CRC : 1; + __IOM uint32_t DMA1EN : 1; + __IOM uint32_t DMA2EN : 1; + __IOM uint32_t SRAMEN : 1; + __IOM uint32_t FPUEN : 1; + __IOM uint32_t FMCEN : 1; + __IOM uint32_t QSPIEN : 1; + __IOM uint32_t CRCEN : 1; __IM uint32_t RESERVED1 : 1; - __IOM uint32_t EMMC : 1; + __IOM uint32_t EMMCEN : 1; __IM uint32_t RESERVED2 : 1; - __IOM uint32_t SDIO : 1; - __IM uint32_t RESERVED3 : 21; + __IOM uint32_t SDIOEN : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t OTGFSEN : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t MACEN : 1; + __IOM uint32_t MACTXEN : 1; + __IOM uint32_t MACRXEN : 1; + __IM uint32_t RESERVED5 : 15; } AHBCLKEN_B; } ; - /** APB2 clock enable register */ + /* APB2 clock enable register */ union { __IOM uint32_t APB2CLKEN; struct { - __IOM uint32_t AFIO : 1; + __IOM uint32_t AFIOEN : 1; __IM uint32_t RESERVED1 : 1; - __IOM uint32_t PA : 1; - __IOM uint32_t PB : 1; - __IOM uint32_t PC : 1; - __IOM uint32_t PD : 1; - __IOM uint32_t PE : 1; - __IOM uint32_t PF : 1; - __IOM uint32_t PG : 1; - __IOM uint32_t ADC1 : 1; - __IOM uint32_t ADC2 : 1; - __IOM uint32_t TMR1 : 1; - __IOM uint32_t SPI1 : 1; - __IOM uint32_t TMR8 : 1; - __IOM uint32_t USART1 : 1; - __IOM uint32_t ADC3 : 1; + __IOM uint32_t PAEN : 1; + __IOM uint32_t PBEN : 1; + __IOM uint32_t PCEN : 1; + __IOM uint32_t PDEN : 1; + __IOM uint32_t PEEN : 1; + __IOM uint32_t PFEN : 1; + __IOM uint32_t PGEN : 1; + __IOM uint32_t ADC1EN : 1; + __IOM uint32_t ADC2EN : 1; + __IOM uint32_t TMR1EN : 1; + __IOM uint32_t SPI1EN : 1; + __IOM uint32_t TMR8EN : 1; + __IOM uint32_t USART1EN : 1; + __IOM uint32_t ADC3EN : 1; __IM uint32_t RESERVED2 : 16; } APB2CLKEN_B; }; - /** APB1 clock enable register */ + /* APB1 clock enable register */ union { __IOM uint32_t APB1CLKEN; struct { - __IOM uint32_t TMR2 : 1; - __IOM uint32_t TMR3 : 1; - __IOM uint32_t TMR4 : 1; - __IOM uint32_t TMR5 : 1; - __IOM uint32_t TMR6 : 1; - __IOM uint32_t TMR7 : 1; + __IOM uint32_t TMR2EN : 1; + __IOM uint32_t TMR3EN : 1; + __IOM uint32_t TMR4EN : 1; + __IOM uint32_t TMR5EN : 1; + __IOM uint32_t TMR6EN : 1; + __IOM uint32_t TMR7EN : 1; __IM uint32_t RESERVED1 : 5; - __IOM uint32_t WWDT : 1; + __IOM uint32_t WWDTEN : 1; __IM uint32_t RESERVED2 : 2; - __IOM uint32_t SPI2 : 1; - __IOM uint32_t SPI3 : 1; + __IOM uint32_t SPI2EN : 1; + __IOM uint32_t SPI3EN : 1; __IM uint32_t RESERVED3 : 1; - __IOM uint32_t USART2 : 1; - __IOM uint32_t USART3 : 1; - __IOM uint32_t UART4 : 1; - __IOM uint32_t UART5 : 1; - __IOM uint32_t I2C1 : 1; - __IOM uint32_t I2C2 : 1; - __IOM uint32_t USBD : 1; + __IOM uint32_t USART2EN : 1; + __IOM uint32_t USART3EN : 1; + __IOM uint32_t UART4EN : 1; + __IOM uint32_t UART5EN : 1; + __IOM uint32_t I2C1EN : 1; + __IOM uint32_t I2C2EN : 1; + __IOM uint32_t USBDEN : 1; __IM uint32_t RESERVED4 : 1; - __IOM uint32_t CAN1 : 1; - __IM uint32_t CAN2 : 1; - __IOM uint32_t BAKP : 1; - __IOM uint32_t PMU : 1; - __IOM uint32_t DAC : 1; + __IOM uint32_t CAN1EN : 1; + __IOM uint32_t CAN2EN : 1; + __IOM uint32_t BAKPEN : 1; + __IOM uint32_t PMUEN : 1; + __IOM uint32_t DACEN : 1; __IM uint32_t RESERVED5 : 2; } APB1CLKEN_B; } ; - /** Backup domain control register */ + /* Backup domain control register */ union - { + { __IOM uint32_t BDCTRL; struct @@ -533,7 +646,7 @@ typedef struct } BDCTRL_B; } ; - /** Control/status register */ + /* Control/status register */ union { __IOM uint32_t CSTS; @@ -553,6 +666,39 @@ typedef struct __IOM uint32_t LPWRRSTFLG : 1; } CSTS_B; } ; + + /* AHB peripheral reset register */ + union + { + __IOM uint32_t AHBRST; + + struct + { + __IM uint32_t RESERVED1 : 12; + __IOM uint32_t OTGFSRST : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t MACRST : 1; + __IM uint32_t RESERVED3 : 17; + } AHBRST_B; + } ; + + /* Clock configuration register2 */ + union + { + __IOM uint32_t CFG2; + + struct + { + __IOM uint32_t PLLPSC1 : 4; + __IOM uint32_t PLLPSC2 : 4; + __IOM uint32_t PLL2MUL : 4; + __IOM uint32_t PLL3MUL : 4; + __IOM uint32_t PLLPSC1SRC : 1; + __IOM uint32_t I2S2SRCSEL : 1; + __IOM uint32_t I2S3SRCSEL : 1; + __IM uint32_t RESERVED1 : 13; + } CFG2_B; + } ; } RCM_T; /** @@ -560,7 +706,7 @@ typedef struct */ typedef struct { - /** Port configure register low */ + /* Port configure register low */ union { __IOM uint32_t CFGLOW; @@ -586,7 +732,7 @@ typedef struct } CFGLOW_B; } ; - /** Port configure register high */ + /* Port configure register high */ union { __IOM uint32_t CFGHIG; @@ -612,7 +758,7 @@ typedef struct } CFGHIG_B; } ; - /** Port data in register */ + /* Port data in register */ union { __IM uint32_t IDATA; @@ -639,7 +785,7 @@ typedef struct } IDATA_B; } ; - /** Port data output register */ + /* Port data output register */ union { __IOM uint32_t ODATA; @@ -666,7 +812,7 @@ typedef struct } ODATA_B; } ; - /** Port bit set/clear register */ + /* Port bit set/clear register */ union { __OM uint32_t BSC; @@ -708,7 +854,7 @@ typedef struct } BSC_B; } ; - /** Port bit clear register */ + /* Port bit clear register */ union { __OM uint32_t BC; @@ -735,7 +881,7 @@ typedef struct } BC_B; } ; - /** Port configuration lock register */ + /* Port configuration lock register */ union { __IOM uint32_t LOCK; @@ -769,7 +915,7 @@ typedef struct */ typedef struct { - /** Event control register */ + /* Event control register */ union { __IOM uint32_t EVCTRL; @@ -783,38 +929,51 @@ typedef struct } EVCTRL_B; } ; - /** Alternate function IO remap and Serial wire JTAG configuration register */ + /* Alternate function IO remap and Serial wire JTAG configuration register */ union { __IOM uint32_t REMAP1; struct { - __IOM uint32_t SPI1RMP : 1; - __IOM uint32_t I2C1RMP : 1; - __IOM uint32_t USART1RMP : 1; - __IOM uint32_t USART2RMP : 1; - __IOM uint32_t USART3RMP : 2; - __IOM uint32_t TMR1RMP : 2; - __IOM uint32_t TMR2RMP : 2; - __IOM uint32_t TMR3RMP : 2; - __IOM uint32_t TMR4RMP : 1; - __IOM uint32_t CAN1RMP : 2; - __IOM uint32_t PD01RMP : 1; - __IOM uint32_t TMR5CH4IRMP : 1; + __IOM uint32_t SPI1RMP : 1; + __IOM uint32_t I2C1RMP : 1; + __IOM uint32_t USART1RMP : 1; + __IOM uint32_t USART2RMP : 1; + __IOM uint32_t USART3RMP : 2; + __IOM uint32_t TMR1RMP : 2; + __IOM uint32_t TMR2RMP : 2; + __IOM uint32_t TMR3RMP : 2; + __IOM uint32_t TMR4RMP : 1; + __IOM uint32_t CAN1RMP : 2; + __IOM uint32_t PD01RMP : 1; + __IOM uint32_t TMR5CH4IRMP : 1; +#if defined(APM32F10X_CL) + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t MACRMP : 1; + __IOM uint32_t CAN2RMP : 1; + __IOM uint32_t MACEISEL : 1; + __IOM uint32_t SWJCFG : 3; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t SPI3RMP : 1; + __IOM uint32_t TMR2ITR1RMP : 1; + __IOM uint32_t PTPPPSRMP : 1; + __IM uint32_t RESERVED3 : 1; +#else __IOM uint32_t ADC1_ETRGINJC_RMP : 1; __IOM uint32_t ADC1_ETRGREGC_RMP : 1; __IOM uint32_t ADC2_ETRGINJC_RMP : 1; __IOM uint32_t ADC2_ETRGREGC_RMP : 1; - __IM uint32_t RESERVED1 : 1; - __IOM uint32_t CAN2RMP : 1; - __IM uint32_t RESERVED2 : 1; - __OM uint32_t SWJCFG : 3; - __IM uint32_t RESERVED3 : 5; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CAN2RMP : 1; + __IM uint32_t RESERVED2 : 1; + __OM uint32_t SWJCFG : 3; + __IM uint32_t RESERVED3 : 5; +#endif } REMAP1_B; } ; - /** External interrupt select register1 */ + /* External interrupt select register1 */ union { __IOM uint32_t EINTSEL1; @@ -829,7 +988,7 @@ typedef struct } EINTSEL1_B; } ; - /** External interrupt select register2 */ + /* External interrupt select register2 */ union { __IOM uint32_t EINTSEL2; @@ -844,7 +1003,7 @@ typedef struct } EINTSEL2_B; } ; - /** External interrupt select register3 */ + /* External interrupt select register3 */ union { __IOM uint32_t EINTSEL3; @@ -859,7 +1018,7 @@ typedef struct } EINTSEL3_B; } ; - /** External interrupt select register4 */ + /* External interrupt select register4 */ union { __IOM uint32_t EINTSEL4; @@ -875,7 +1034,7 @@ typedef struct } ; __IM uint32_t RESERVED; - /** Alternate function IO remap register2 */ + /* Alternate function IO remap register2 */ union { __IOM uint32_t REMAP2; @@ -894,7 +1053,7 @@ typedef struct */ typedef struct { - /** Status register */ + /* Status register */ union { __IOM uint32_t STS; @@ -915,7 +1074,7 @@ typedef struct } STS_B; } ; - /** TX Buffer Data Register */ + /* TX Buffer Data Register */ union { __IOM uint32_t DATA; @@ -927,7 +1086,7 @@ typedef struct } DATA_B; } ; - /** Baud rate register */ + /* Baud rate register */ union { __IOM uint32_t BR; @@ -940,7 +1099,7 @@ typedef struct } BR_B; } ; - /** Control register 1 */ + /* Control register 1 */ union { __IOM uint32_t CTRL1; @@ -965,7 +1124,7 @@ typedef struct } CTRL1_B; } ; - /** Control register 2 */ + /* Control register 2 */ union { __IOM uint32_t CTRL2; @@ -987,7 +1146,7 @@ typedef struct } CTRL2_B; } ; - /** Control register 3 */ + /* Control register 3 */ union { __IOM uint32_t CTRL3; @@ -1009,7 +1168,7 @@ typedef struct } CTRL3_B; } ; - /** Guard TMRe and divider number register */ + /* Guard TMRe and divider number register */ union { __IOM uint32_t GTPSC; @@ -1028,7 +1187,7 @@ typedef struct */ typedef struct { - /** FMC access control register */ + /* FMC access control register */ union { __IOM uint32_t CTRL1; @@ -1043,7 +1202,7 @@ typedef struct } CTRL1_B; } ; - /** key register */ + /* key register */ union { __OM uint32_t KEY; @@ -1054,7 +1213,7 @@ typedef struct } KEY_B; } ; - /** option byte key register */ + /* option byte key register */ union { __OM uint32_t OBKEY; @@ -1065,7 +1224,7 @@ typedef struct } OBKEY_B; }; - /** status register */ + /* status register */ union { __IOM uint32_t STS; @@ -1082,7 +1241,7 @@ typedef struct } STS_B; }; - /** status register */ + /* status register */ union { __IOM uint32_t CTRL2; @@ -1106,7 +1265,7 @@ typedef struct } CTRL2_B; } ; - /** address register */ + /* address register */ union { __OM uint32_t ADDR; @@ -1119,7 +1278,7 @@ typedef struct __IM uint32_t RESERVED; - /** Option byte register */ + /* Option byte register */ union { __IOM uint32_t OBCS; @@ -1138,7 +1297,7 @@ typedef struct } OBCS_B; }; - /** Write protection register */ + /* Write protection register */ union { __IM uint32_t WRTPROT; @@ -1155,7 +1314,7 @@ typedef struct */ typedef struct { - /** @brief DATA register */ + /* @brief DATA register */ union { __IOM uint32_t DATA; @@ -1166,7 +1325,7 @@ typedef struct } DATA_B; } ; - /** @brief independent DATA register */ + /* @brief independent DATA register */ union { __IOM uint32_t INDATA; @@ -1178,7 +1337,7 @@ typedef struct } INDATA_B; }; - /** @brief Countrol register */ + /* @brief Countrol register */ union { __IOM uint32_t CTRL; @@ -1196,7 +1355,7 @@ typedef struct */ typedef struct { - /** @brief Control register */ + /* @brief Control register */ union { __IOM uint32_t CTRL; @@ -1210,7 +1369,7 @@ typedef struct } CTRL_B; }; - /** @brief Control and State register */ + /* @brief Control and State register */ union { __IOM uint32_t CSTS; @@ -1227,7 +1386,7 @@ typedef struct } CSTS_B; }; - /** @brief RTC predivision loading register High Bit */ + /* @brief RTC predivision loading register High Bit */ union { __OM uint32_t PSCRLDH; @@ -1239,7 +1398,7 @@ typedef struct } PSCRLDH_B; }; - /** @brief RTC predivision loading register Low Bit */ + /* @brief RTC predivision loading register Low Bit */ union { __OM uint32_t PSCRLDL; @@ -1251,7 +1410,7 @@ typedef struct } PSCRLDL_B; }; - /** @brief RTC predivider remainder register High Bit */ + /* @brief RTC predivider remainder register High Bit */ union { __IM uint32_t PSCH; @@ -1263,7 +1422,7 @@ typedef struct } PSCH_B; }; - /** @brief RTC predivider remainder register Low Bit */ + /* @brief RTC predivider remainder register Low Bit */ union { __IM uint32_t PSCL; @@ -1275,7 +1434,7 @@ typedef struct } PSCL_B; }; - /** @brief RTC count register High Bit */ + /* @brief RTC count register High Bit */ union { __IOM uint32_t CNTH; @@ -1287,7 +1446,7 @@ typedef struct } CNTH_B; }; - /** @brief RTC count register Low Bit */ + /* @brief RTC count register Low Bit */ union { __IOM uint32_t CNTL; @@ -1299,7 +1458,7 @@ typedef struct } CNTL_B; }; - /** @brief RTC alarm clock register High Bit */ + /* @brief RTC alarm clock register High Bit */ union { __OM uint32_t ALRH; @@ -1311,7 +1470,7 @@ typedef struct } ALRH_B; }; - /** @brief RTC alarm clock register Low Bit */ + /* @brief RTC alarm clock register Low Bit */ union { __OM uint32_t ALRL; @@ -1329,7 +1488,7 @@ typedef struct */ typedef struct { - /** @brief Control register */ + /* @brief Control register */ union { __IOM uint32_t CTRL; @@ -1347,7 +1506,7 @@ typedef struct } CTRL_B; }; - /** @brief PMU Status register */ + /* @brief PMU Status register */ union { __IOM uint32_t CSTS; @@ -1371,7 +1530,7 @@ typedef struct { __IM uint32_t RESERVED; - /** @brief BAKPR DATA1 register */ + /* @brief BAKPR DATA1 register */ union { __IOM uint32_t DATA1; @@ -1383,7 +1542,7 @@ typedef struct } DATA1_B; }; - /** @brief BAKPR DATA2 register */ + /* @brief BAKPR DATA2 register */ union { __IOM uint32_t DATA2; @@ -1395,7 +1554,7 @@ typedef struct } DATA2_B; }; - /** @brief BAKPR DATA3 register */ + /* @brief BAKPR DATA3 register */ union { __IOM uint32_t DATA3; @@ -1407,7 +1566,7 @@ typedef struct } DATA3_B; }; - /** @brief BAKPR DATA4 register */ + /* @brief BAKPR DATA4 register */ union { __IOM uint32_t DATA4; @@ -1419,7 +1578,7 @@ typedef struct } DATA4_B; }; - /** @brief BAKPR DATA5 register */ + /* @brief BAKPR DATA5 register */ union { __IOM uint32_t DATA5; @@ -1431,7 +1590,7 @@ typedef struct } DATA5_B; }; - /** @brief BAKPR DATA6 register */ + /* @brief BAKPR DATA6 register */ union { __IOM uint32_t DATA6; @@ -1443,7 +1602,7 @@ typedef struct } DATA6_B; }; - /** @brief BAKPR DATA7 register */ + /* @brief BAKPR DATA7 register */ union { __IOM uint32_t DATA7; @@ -1455,7 +1614,7 @@ typedef struct } DATA7_B; }; - /** @brief BAKPR DATA8 register */ + /* @brief BAKPR DATA8 register */ union { __IOM uint32_t DATA8; @@ -1467,7 +1626,7 @@ typedef struct } DATA8_B; }; - /** @brief BAKPR DATA9 register */ + /* @brief BAKPR DATA9 register */ union { __IOM uint32_t DATA9; @@ -1479,7 +1638,7 @@ typedef struct } DATA9_B; }; - /** @brief BAKPR DATA10 register */ + /* @brief BAKPR DATA10 register */ union { __IOM uint32_t DATA10; @@ -1491,7 +1650,7 @@ typedef struct } DATA10_B; }; - /** @brief BAKPR Clock Calibration register */ + /* @brief BAKPR Clock Calibration register */ union { __IOM uint32_t CLKCAL; @@ -1506,7 +1665,7 @@ typedef struct } CLKCAL_B; } ; - /** @brief BAKPR Control register */ + /* @brief BAKPR Control register */ union { __IOM uint32_t CTRL; @@ -1519,7 +1678,7 @@ typedef struct } CTRL_B; }; - /** @brief BAKPR Control register */ + /* @brief BAKPR Control register */ union { __IOM uint32_t CSTS; @@ -1538,7 +1697,7 @@ typedef struct __IM uint32_t RESERVED1[2]; - /** @briefBAKPR DATA11 register */ + /* @briefBAKPR DATA11 register */ union { __IOM uint32_t DATA11; @@ -1550,7 +1709,7 @@ typedef struct } DATA11_B; }; - /** @briefBAKPR DATA12 register */ + /* @briefBAKPR DATA12 register */ union { __IOM uint32_t DATA12; @@ -1562,7 +1721,7 @@ typedef struct } DATA12_B; }; - /** @briefBAKPR DATA13 register */ + /* @briefBAKPR DATA13 register */ union { __IOM uint32_t DATA13; @@ -1574,7 +1733,7 @@ typedef struct } DATA13_B; }; - /** @briefBAKPR DATA14 register */ + /* @briefBAKPR DATA14 register */ union { __IOM uint32_t DATA14; @@ -1586,7 +1745,7 @@ typedef struct } DATA14_B; }; - /** @briefBAKPR DATA15 register */ + /* @briefBAKPR DATA15 register */ union { __IOM uint32_t DATA15; @@ -1598,7 +1757,7 @@ typedef struct } DATA15_B; }; - /** @briefBAKPR DATA16 register */ + /* @briefBAKPR DATA16 register */ union { __IOM uint32_t DATA16; @@ -1610,7 +1769,7 @@ typedef struct } DATA16_B; }; - /** @briefBAKPR DATA17 register */ + /* @briefBAKPR DATA17 register */ union { __IOM uint32_t DATA17; @@ -1622,7 +1781,7 @@ typedef struct } DATA17_B; }; - /** @briefBAKPR DATA18 register */ + /* @briefBAKPR DATA18 register */ union { __IOM uint32_t DATA18; @@ -1634,7 +1793,7 @@ typedef struct } DATA18_B; }; - /** @briefBAKPR DATA19 register */ + /* @briefBAKPR DATA19 register */ union { __IOM uint32_t DATA19; @@ -1646,7 +1805,7 @@ typedef struct } DATA19_B; }; - /** @briefBAKPR DATA20 register */ + /* @briefBAKPR DATA20 register */ union { __IOM uint32_t DATA20; @@ -1658,7 +1817,7 @@ typedef struct } DATA20_B; }; - /** @briefBAKPR DATA21 register */ + /* @briefBAKPR DATA21 register */ union { __IOM uint32_t DATA21; @@ -1670,7 +1829,7 @@ typedef struct } DATA21_B; }; - /** @briefBAKPR DATA22 register */ + /* @briefBAKPR DATA22 register */ union { __IOM uint32_t DATA22; @@ -1682,7 +1841,7 @@ typedef struct } DATA22_B; }; - /** @briefBAKPR DATA23 register */ + /* @briefBAKPR DATA23 register */ union { __IOM uint32_t DATA23; @@ -1694,7 +1853,7 @@ typedef struct } DATA23_B; }; - /** @briefBAKPR DATA24 register */ + /* @briefBAKPR DATA24 register */ union { __IOM uint32_t DATA24; @@ -1706,7 +1865,7 @@ typedef struct } DATA24_B; }; - /** @briefBAKPR DATA25 register */ + /* @briefBAKPR DATA25 register */ union { __IOM uint32_t DATA25; @@ -1718,7 +1877,7 @@ typedef struct } DATA25_B; }; - /** @briefBAKPR DATA26 register */ + /* @briefBAKPR DATA26 register */ union { __IOM uint32_t DATA26; @@ -1730,7 +1889,7 @@ typedef struct } DATA26_B; }; - /** @briefBAKPR DATA27 register */ + /* @briefBAKPR DATA27 register */ union { __IOM uint32_t DATA27; @@ -1742,7 +1901,7 @@ typedef struct } DATA27_B; }; - /** @briefBAKPR DATA28 register */ + /* @briefBAKPR DATA28 register */ union { __IOM uint32_t DATA28; @@ -1754,7 +1913,7 @@ typedef struct } DATA28_B; }; - /** @briefBAKPR DATA29 register */ + /* @briefBAKPR DATA29 register */ union { __IOM uint32_t DATA29; @@ -1766,7 +1925,7 @@ typedef struct } DATA29_B; }; - /** @briefBAKPR DATA30 register */ + /* @briefBAKPR DATA30 register */ union { __IOM uint32_t DATA30; @@ -1778,7 +1937,7 @@ typedef struct } DATA30_B; }; - /** @briefBAKPR DATA31 register */ + /* @briefBAKPR DATA31 register */ union { __IOM uint32_t DATA31; @@ -1790,7 +1949,7 @@ typedef struct } DATA31_B; }; - /** @briefBAKPR DATA32 register */ + /* @briefBAKPR DATA32 register */ union { __IOM uint32_t DATA32; @@ -1802,7 +1961,7 @@ typedef struct } DATA32_B; }; - /** @briefBAKPR DATA33 register */ + /* @briefBAKPR DATA33 register */ union { __IOM uint32_t DATA33; @@ -1814,7 +1973,7 @@ typedef struct } DATA33_B; }; - /** @briefBAKPR DATA34 register */ + /* @briefBAKPR DATA34 register */ union { __IOM uint32_t DATA34; @@ -1826,7 +1985,7 @@ typedef struct } DATA34_B; }; - /** @briefBAKPR DATA35 register */ + /* @briefBAKPR DATA35 register */ union { __IOM uint32_t DATA35; @@ -1838,7 +1997,7 @@ typedef struct } DATA35_B; }; - /** @briefBAKPR DATA36 register */ + /* @briefBAKPR DATA36 register */ union { __IOM uint32_t DATA36; @@ -1850,7 +2009,7 @@ typedef struct } DATA36_B; }; - /** @briefBAKPR DATA37 register */ + /* @briefBAKPR DATA37 register */ union { __IOM uint32_t DATA37; @@ -1862,7 +2021,7 @@ typedef struct } DATA37_B; }; - /** @briefBAKPR DATA38 register */ + /* @briefBAKPR DATA38 register */ union { __IOM uint32_t DATA38; @@ -1874,7 +2033,7 @@ typedef struct } DATA38_B; }; - /** @briefBAKPR DATA39 register */ + /* @briefBAKPR DATA39 register */ union { __IOM uint32_t DATA39; @@ -1886,7 +2045,7 @@ typedef struct } DATA39_B; }; - /** @briefBAKPR DATA40 register */ + /* @briefBAKPR DATA40 register */ union { __IOM uint32_t DATA40; @@ -1898,7 +2057,7 @@ typedef struct } DATA40_B; }; - /** @briefBAKPR DATA41 register */ + /* @briefBAKPR DATA41 register */ union { __IOM uint32_t DATA41; @@ -1910,7 +2069,7 @@ typedef struct } DATA41_B; }; - /** @briefBAKPR DATA42 register */ + /* @briefBAKPR DATA42 register */ union { __IOM uint32_t DATA42; @@ -1928,7 +2087,7 @@ typedef struct */ typedef struct { - /** @brief Countrol register 1 */ + /* @brief Countrol register 1 */ union { __IOM uint32_t CTRL1; @@ -1947,7 +2106,7 @@ typedef struct } CTRL1_B; }; - /** @brief Countrol register 2 */ + /* @brief Countrol register 2 */ union { __IOM uint32_t CTRL2; @@ -1971,7 +2130,7 @@ typedef struct } CTRL2_B; }; - /** @brief Control register from mode */ + /* @brief Control register from mode */ union { __IOM uint32_t SMCTRL; @@ -1990,7 +2149,7 @@ typedef struct } SMCTRL_B; }; - /** @brief DMA and Interrupt enable register */ + /* @brief DMA and Interrupt enable register */ union { __IOM uint32_t DIEN; @@ -2016,7 +2175,7 @@ typedef struct } DIEN_B; }; - /** @brief Status register */ + /* @brief Status register */ union { __IOM uint32_t STS; @@ -2040,7 +2199,7 @@ typedef struct } STS_B; }; - /** @brief Software controls event generation registers */ + /* @brief Software controls event generation registers */ union { __OM uint32_t CEG; @@ -2059,12 +2218,12 @@ typedef struct } CEG_B; }; - /** @brief Capture the compare mode register 1 */ + /* @brief Capture the compare mode register 1 */ union { __IOM uint32_t CCM1; - /** @brief Compare mode */ + /* @brief Compare mode */ struct { __IOM uint32_t CC1SEL : 2; @@ -2080,7 +2239,7 @@ typedef struct __IM uint32_t RESERVED : 16; } CCM1_COMPARE_B; - /** @brief Capture mode */ + /* @brief Capture mode */ struct { __IOM uint32_t CC1SEL : 2; @@ -2093,12 +2252,12 @@ typedef struct } CCM1_CAPTURE_B; }; - /** @brief Capture the compare mode register 2 */ + /* @brief Capture the compare mode register 2 */ union { __IOM uint32_t CCM2; - /** @brief Compare mode */ + /* @brief Compare mode */ struct { __IOM uint32_t CC3SEL : 2; @@ -2114,7 +2273,7 @@ typedef struct __IM uint32_t RESERVED : 16; } CCM2_COMPARE_B; - /** @brief Capture mode */ + /* @brief Capture mode */ struct { __IOM uint32_t CC3SEL : 2; @@ -2127,7 +2286,7 @@ typedef struct } CCM2_CAPTURE_B; }; - /** @brief Channel control register */ + /* @brief Channel control register */ union { __IOM uint32_t CCEN; @@ -2152,7 +2311,7 @@ typedef struct } CCEN_B; }; - /** @brief Counting register */ + /* @brief Counting register */ union { __IOM uint32_t CNT; @@ -2164,7 +2323,7 @@ typedef struct } CNT_B; }; - /** @brief Division register */ + /* @brief Division register */ union { __IOM uint32_t PSC; @@ -2176,7 +2335,7 @@ typedef struct } PSC_B; }; - /** @brief Automatic reload register */ + /* @brief Automatic reload register */ union { __IOM uint32_t AUTORLD; @@ -2188,7 +2347,7 @@ typedef struct } AUTORLD_B; }; - /** @brief Repeat count register */ + /* @brief Repeat count register */ union { __IOM uint32_t REPCNT; @@ -2200,7 +2359,7 @@ typedef struct } REPCNT_B; }; - /** @brief Capture comparison register channel 1 */ + /* @brief Capture comparison register channel 1 */ union { __IOM uint32_t CC1; @@ -2212,7 +2371,7 @@ typedef struct } CC1_B; }; - /** @brief Capture comparison register channel 2 */ + /* @brief Capture comparison register channel 2 */ union { __IOM uint32_t CC2; @@ -2224,7 +2383,7 @@ typedef struct } CC2_B; }; - /** @brief Capture comparison register channel 3 */ + /* @brief Capture comparison register channel 3 */ union { __IOM uint32_t CC3; @@ -2236,7 +2395,7 @@ typedef struct } CC3_B; }; - /** @brief Capture comparison register channel 4 */ + /* @brief Capture comparison register channel 4 */ union { __IOM uint32_t CC4; @@ -2248,7 +2407,7 @@ typedef struct } CC4_B; }; - /** @brief Brake and dead zone registers */ + /* @brief Brake and dead zone registers */ union { __IOM uint32_t BDT; @@ -2267,7 +2426,7 @@ typedef struct } BDT_B; }; - /** @brief DMA control register */ + /* @brief DMA control register */ union { __IOM uint32_t DCTRL; @@ -2281,7 +2440,7 @@ typedef struct } DCTRL_B; }; - /** @brief Consecutive DMA addresses */ + /* @brief Consecutive DMA addresses */ union { __IOM uint32_t DMADDR; @@ -2298,7 +2457,7 @@ typedef struct */ typedef struct { - /** @brief Interrupt status register */ + /* @brief Interrupt status register */ union { __IM uint32_t INTSTS; @@ -2337,7 +2496,7 @@ typedef struct } INTSTS_B; }; - /** @brief Interrupt reset register */ + /* @brief Interrupt reset register */ union { __OM uint32_t INTFCLR; @@ -2382,7 +2541,7 @@ typedef struct */ typedef struct { - /** @brief DMA Channel setup register */ + /* @brief DMA Channel setup register */ union { @@ -2406,7 +2565,7 @@ typedef struct } CHCFG_B; }; - /** @brief DMA Channel transfer number register*/ + /* @brief DMA Channel transfer number register*/ union { __IOM uint32_t CHNDATA; @@ -2418,7 +2577,7 @@ typedef struct } CHNDATA_B; }; - /** @brief DMA Channel peripheral address register */ + /* @brief DMA Channel peripheral address register */ union { __IOM uint32_t CHPADDR; @@ -2429,7 +2588,7 @@ typedef struct } CHPADDR_B; }; - /** @brief DMA Channel memory address register */ + /* @brief DMA Channel memory address register */ union { __IOM uint32_t CHMADDR; @@ -2446,7 +2605,7 @@ typedef struct */ typedef struct { - /** @brief CAN Each mailbox contains the sending mailbox identifier register */ + /* @brief CAN Each mailbox contains the sending mailbox identifier register */ union { __IOM uint32_t TXMID; @@ -2461,7 +2620,7 @@ typedef struct } TXMID_B; }; - /** @brief CAN Send the mailbox data length and timestamp register */ + /* @brief CAN Send the mailbox data length and timestamp register */ union { __IOM uint32_t TXDLEN; @@ -2473,7 +2632,7 @@ typedef struct } TXDLEN_B; }; - /** @brief CAN Send mailbox low byte data register */ + /* @brief CAN Send mailbox low byte data register */ union { __IOM uint32_t TXMDL; @@ -2487,7 +2646,7 @@ typedef struct } TXMDL_B; }; - /** @brief CAN Send mailbox High byte data register */ + /* @brief CAN Send mailbox High byte data register */ union { __IOM uint32_t TXMDH; @@ -2507,7 +2666,7 @@ typedef struct */ typedef struct { - /** @brief CAN Each mailbox contains the receive mailbox identifier register */ + /* @brief CAN Each mailbox contains the receive mailbox identifier register */ union { __IM uint32_t RXMID; @@ -2522,7 +2681,7 @@ typedef struct } RXMID_B; }; - /** @brief CAN receive the mailbox data length and timestamp register */ + /* @brief CAN receive the mailbox data length and timestamp register */ union { __IM uint32_t RXDLEN; @@ -2536,7 +2695,7 @@ typedef struct } RXDLEN_B; }; - /** @brief CAN receive mailbox low byte data register */ + /* @brief CAN receive mailbox low byte data register */ union { __IM uint32_t RXMDL; @@ -2550,7 +2709,7 @@ typedef struct } RXMDL_B; }; - /** @briefCAN receive mailbox High byte data register */ + /* @briefCAN receive mailbox High byte data register */ union { __IOM uint32_t RXMDH; @@ -2570,7 +2729,7 @@ typedef struct */ typedef struct { - /** @brief CAN Filter bank register 1 */ + /* @brief CAN Filter bank register 1 */ union { __IOM uint32_t FBANK1; @@ -2612,7 +2771,7 @@ typedef struct } FBANK1_B; }; - /** @brief CAN Filter bank register 2 */ + /* @brief CAN Filter bank register 2 */ union { __IOM uint32_t FBANK2; @@ -2660,7 +2819,7 @@ typedef struct */ typedef struct { - /** @brief CAN Master control register */ + /* @brief CAN Master control register */ union { __IOM uint32_t MCTRL; @@ -2681,7 +2840,7 @@ typedef struct } MCTRL_B; }; - /** @brief CAN Master States register */ + /* @brief CAN Master States register */ union { __IOM uint32_t MSTS; @@ -2702,7 +2861,7 @@ typedef struct } MSTS_B; }; - /** @brief CAN Send States register */ + /* @brief CAN Send States register */ union { __IOM uint32_t TXSTS; @@ -2737,7 +2896,7 @@ typedef struct } TXSTS_B; }; - /** @brief CAN Receive FIFO 0 register */ + /* @brief CAN Receive FIFO 0 register */ union { __IOM uint32_t RXF0; @@ -2753,7 +2912,7 @@ typedef struct } RXF0_B; }; - /** @brief CAN Receive FIFO 1 register */ + /* @brief CAN Receive FIFO 1 register */ union { __IOM uint32_t RXF1; @@ -2769,7 +2928,7 @@ typedef struct } RXF1_B; }; - /** @brief CAN Interrupts register */ + /* @brief CAN Interrupts register */ union { __IOM uint32_t INTEN; @@ -2796,7 +2955,7 @@ typedef struct } INTEN_B; }; - /** @brief CAN Error States register */ + /* @brief CAN Error States register */ union { __IOM uint32_t ERRSTS; @@ -2814,7 +2973,7 @@ typedef struct } ERRSTS_B; }; - /** @brief CAN Bit Time register */ + /* @brief CAN Bit Time register */ union { __IOM uint32_t BITTIM; @@ -2840,7 +2999,7 @@ typedef struct __IM uint32_t RESERVED1[12]; - /** @brief CAN Filter the master control register */ + /* @brief CAN Filter the master control register */ union { __IOM uint32_t FCTRL; @@ -2854,7 +3013,7 @@ typedef struct } FCTRL_B; }; - /** @brief CAN Filter register */ + /* @brief CAN Filter register */ union { __IOM uint32_t FMCFG; @@ -2895,7 +3054,7 @@ typedef struct __IM uint32_t RESERVED2; - /** @brief CAN Filter bit scale register */ + /* @brief CAN Filter bit scale register */ union { __IOM uint32_t FSCFG; @@ -2931,12 +3090,12 @@ typedef struct __IOM uint32_t FSCFG26 : 1; __IOM uint32_t FSCFG27 : 1; __IM uint32_t RESERVED : 4; - }FSCFG_B; + } FSCFG_B; }; __IM uint32_t RESERVED3; - /** @brief CAN Filter FIFO associated registers */ + /* @brief CAN Filter FIFO associated registers */ union { __IOM uint32_t FFASS; @@ -2977,7 +3136,7 @@ typedef struct __IM uint32_t RESERVED4; - /** @brief CAN Filter activation register */ + /* @brief CAN Filter activation register */ union { __IOM uint32_t FACT; @@ -3027,7 +3186,7 @@ typedef struct */ typedef struct { - /** @brief Control register 1 */ + /* @brief Control register 1 */ union { __IOM uint32_t CTRL1; @@ -3054,7 +3213,7 @@ typedef struct } CTRL1_B; } ; - /** @brief Control register 2 */ + /* @brief Control register 2 */ union { __IOM uint32_t CTRL2; @@ -3072,7 +3231,7 @@ typedef struct } CTRL2_B; } ; - /** @brief Slave machine address register 1 */ + /* @brief Slave machine address register 1 */ union { __IOM uint32_t SADDR1; @@ -3088,7 +3247,7 @@ typedef struct } SADDR1_B; }; - /** @brief Slave machine address register 2 */ + /* @brief Slave machine address register 2 */ union { __IOM uint32_t SADDR2; @@ -3101,7 +3260,7 @@ typedef struct } SADDR2_B; }; - /** @brief Cache data register */ + /* @brief Cache data register */ union { __IOM uint32_t DATA; @@ -3113,7 +3272,7 @@ typedef struct } DATA_B; }; - /** @brief Status register 1 */ + /* @brief Status register 1 */ union { __IOM uint32_t STS1; @@ -3140,7 +3299,7 @@ typedef struct } STS1_B; }; - /** @brief Status register 2 */ + /* @brief Status register 2 */ union { __IOM uint32_t STS2; @@ -3160,7 +3319,7 @@ typedef struct } STS2_B; }; - /** @brief Clock control register */ + /* @brief Clock control register */ union { __IOM uint32_t CLKCTRL; @@ -3175,7 +3334,7 @@ typedef struct } CLKCTRL_B; }; - /** @brief Maximum rise time */ + /* @brief Maximum rise time */ union { __IOM uint32_t RISETMAX; @@ -3189,7 +3348,7 @@ typedef struct __IM uint32_t RESERVED[55]; - /** @brief I2C Switching register */ + /* @brief I2C Switching register */ union { __IOM uint32_t SWITCH; @@ -3221,7 +3380,7 @@ typedef struct typedef struct { - /** Status register */ + /* Status register */ union { __IOM uint32_t STS; @@ -3237,7 +3396,7 @@ typedef struct } STS_B; }; - /** Control register1*/ + /* Control register1*/ union { __IOM uint32_t CTRL1; @@ -3262,7 +3421,7 @@ typedef struct } CTRL1_B; }; - /** Control register2*/ + /* Control register2*/ union { __IOM uint32_t CTRL2; @@ -3289,7 +3448,7 @@ typedef struct } CTRL2_B; }; - /** Sample time register1*/ + /* Sample time register1*/ union { __IOM uint32_t SMPTIM1; @@ -3308,7 +3467,7 @@ typedef struct } SMPTIM1_B; }; - /** Sample time register2*/ + /* Sample time register2*/ union { __IOM uint32_t SMPTIM2; @@ -3329,7 +3488,7 @@ typedef struct } SMPTIM2_B; }; - /** Injected channel Data offset register1*/ + /* Injected channel Data offset register1*/ union { __IOM uint32_t INJDOF1; @@ -3341,7 +3500,7 @@ typedef struct } INJDOF1_B; }; - /** Injected channel Data offset register2*/ + /* Injected channel Data offset register2*/ union { __IOM uint32_t INJDOF2; @@ -3353,7 +3512,7 @@ typedef struct } INJDOF2_B; }; - /** Injected channel Data offset register3*/ + /* Injected channel Data offset register3*/ union { __IOM uint32_t INJDOF3; @@ -3365,7 +3524,7 @@ typedef struct } INJDOF3_B; }; - /** Injected channel Data offset register4*/ + /* Injected channel Data offset register4*/ union { __IOM uint32_t INJDOF4; @@ -3377,7 +3536,7 @@ typedef struct } INJDOF4_B; }; - /** Analog watchdog high threshold register*/ + /* Analog watchdog high threshold register*/ union { __IOM uint32_t AWDHT; @@ -3389,7 +3548,7 @@ typedef struct } AWDHT_B; }; - /** Analog watchdog low threshold register*/ + /* Analog watchdog low threshold register*/ union { __IOM uint32_t AWDLT; @@ -3401,7 +3560,7 @@ typedef struct } AWDLT_B; }; - /** Regular channel sequence register1*/ + /* Regular channel sequence register1*/ union { __IOM uint32_t REGSEQ1; @@ -3417,7 +3576,7 @@ typedef struct } REGSEQ1_B; }; - /** Regular channel sequence register2*/ + /* Regular channel sequence register2*/ union { __IOM uint32_t REGSEQ2; @@ -3434,7 +3593,7 @@ typedef struct } REGSEQ2_B; }; - /** Regular channel sequence register3*/ + /* Regular channel sequence register3*/ union { __IOM uint32_t REGSEQ3; @@ -3451,7 +3610,7 @@ typedef struct } REGSEQ3_B; }; - /** Injected sequence register*/ + /* Injected sequence register*/ union { __IOM uint32_t INJSEQ; @@ -3467,7 +3626,7 @@ typedef struct } INJSEQ_B; }; - /** Injected Data register1*/ + /* Injected Data register1*/ union { __IM uint32_t INJDATA1; @@ -3479,7 +3638,7 @@ typedef struct } INJDATA1_B; }; - /** Injected Data register2*/ + /* Injected Data register2*/ union { __IM uint32_t INJDATA2; @@ -3491,7 +3650,7 @@ typedef struct } INJDATA2_B; }; - /** Injected Data register3*/ + /* Injected Data register3*/ union { __IM uint32_t INJDATA3; @@ -3503,7 +3662,7 @@ typedef struct } INJDATA3_B; }; - /** Injected Data register4*/ + /* Injected Data register4*/ union { __IM uint32_t INJDATA4; @@ -3515,7 +3674,7 @@ typedef struct } INJDATA4_B; }; - /** Regular Data register*/ + /* Regular Data register*/ union { __IOM uint32_t REGDATA; @@ -3526,14 +3685,14 @@ typedef struct __IM uint32_t ADC2DATA : 16; } REGDATA_B; }; -}ADC_T; +} ADC_T; /** * @brief External Interrupt(EINT) */ typedef struct { - /** Interrupt mask register */ + /* Interrupt mask register */ union { __IOM uint32_t IMASK; @@ -3563,7 +3722,7 @@ typedef struct } IMASK_B; }; - /** Event mask register */ + /* Event mask register */ union { __IOM uint32_t EMASK; @@ -3593,7 +3752,7 @@ typedef struct } EEN_B; }; - /** Rising Trigger Event Enable register */ + /* Rising Trigger Event Enable register */ union { __IOM uint32_t RTEN; @@ -3623,7 +3782,7 @@ typedef struct } RTEN_B; }; - /** Falling Trigger Event Enable register */ + /* Falling Trigger Event Enable register */ union { __IOM uint32_t FTEN; @@ -3653,7 +3812,7 @@ typedef struct } FTEN_B; }; - /** Software Interrupt Enable register */ + /* Software Interrupt Enable register */ union { __IOM uint32_t SWINTE; @@ -3683,7 +3842,7 @@ typedef struct } SWINTE_B; }; - /** Interrupt Flag Enable register */ + /* Interrupt Flag Enable register */ union { __IOM uint32_t IPEND; @@ -3712,7 +3871,7 @@ typedef struct __IM uint32_t RESERVED : 12; } IF_B; }; -}EINT_T; +} EINT_T; /** * @brief Independent watchdog(IWDT) @@ -3720,7 +3879,7 @@ typedef struct typedef struct { - /** Keyword register */ + /* Keyword register */ union { __OM uint32_t KEY; @@ -3732,7 +3891,7 @@ typedef struct } KEY_B; }; - /** Frequency Divider register */ + /* Frequency Divider register */ union { __IOM uint32_t PSC; @@ -3744,7 +3903,7 @@ typedef struct } DIV_B; }; - /** Reload values register */ + /* Reload values register */ union { __IOM uint32_t CNTRLD; @@ -3756,7 +3915,7 @@ typedef struct } CNTRLD_B; }; - /** Status register */ + /* Status register */ union { __IM uint32_t STS; @@ -3768,14 +3927,14 @@ typedef struct __IM uint32_t RESERVED : 30; } STS_B; }; -}IWDT_T; +} IWDT_T; /** * @brief Serial peripheral interface(SPI) */ typedef struct { - /** Control register 1 */ + /* Control register 1 */ union { __IOM uint32_t CTRL1; @@ -3800,7 +3959,7 @@ typedef struct } CTRL1_B; }; - /** Control register 2 */ + /* Control register 2 */ union { __IOM uint32_t CTRL2; @@ -3818,7 +3977,7 @@ typedef struct } CTRL2_B; }; - /** Status register */ + /* Status register */ union { __IOM uint32_t STS; @@ -3837,7 +3996,7 @@ typedef struct } STS_B; }; - /** Data register */ + /* Data register */ union { __IOM uint32_t DATA; @@ -3849,7 +4008,7 @@ typedef struct } DATA_B; }; - /** CRC polynomial register */ + /* CRC polynomial register */ union { __IOM uint32_t CRCPOLY; @@ -3861,7 +4020,7 @@ typedef struct } CRCPOLY_B; }; - /** Receive CRC register */ + /* Receive CRC register */ union { __IM uint32_t RXCRC; @@ -3870,10 +4029,10 @@ typedef struct { __IM uint32_t RXCRC : 16; __IM uint32_t RESERVED : 16; - }RXCRC_B; + } RXCRC_B; }; - /** Transmit CRC register */ + /* Transmit CRC register */ union { __IM uint32_t TXCRC; @@ -3882,10 +4041,10 @@ typedef struct { __IM uint32_t TXCRC : 16; __IM uint32_t RESERVED : 16; - }TXCRC_B; + } TXCRC_B; }; - /** Transmit I2S CTRL register */ + /* Transmit I2S CTRL register */ union { __IOM uint32_t I2SCFG; @@ -3902,10 +4061,10 @@ typedef struct __IOM uint32_t I2SEN : 1; __IOM uint32_t MODESEL : 1; __IM uint32_t RESERVED2 : 20; - }I2SCFG_B; + } I2SCFG_B; }; - /** Transmit I2S DIV register */ + /* Transmit I2S DIV register */ union { __IOM uint32_t I2SPSC; @@ -3916,9 +4075,9 @@ typedef struct __IOM uint32_t ODDPSC : 1; __IOM uint32_t MCIEN : 1; __IM uint32_t RESERVED1 : 22; - }I2SPSC_B; + } I2SPSC_B; }; -}SPI_T; +} SPI_T; /** * @brief Window watchdog (WWDT) @@ -3926,7 +4085,7 @@ typedef struct typedef struct { - /** Control register */ + /* Control register */ union { __IOM uint32_t CTRL; @@ -3939,7 +4098,7 @@ typedef struct } CTRL_B; }; - /** Configure register */ + /* Configure register */ union { __IOM uint32_t CFG; @@ -3953,7 +4112,7 @@ typedef struct } CFG_B; }; - /** Status register */ + /* Status register */ union { __IOM uint32_t STS; @@ -3964,14 +4123,14 @@ typedef struct __IM uint32_t RESERVED : 31; } STS_B; }; -}WWDT_T; +} WWDT_T; /** * @brief Secure digital input/output interface (SDIO) */ typedef struct { - /** Power control register */ + /* Power control register */ union { __IOM uint32_t PWRCTRL; @@ -3983,7 +4142,7 @@ typedef struct } PWRCTRL_B; }; - /** Clock control register */ + /* Clock control register */ union { __IOM uint32_t CLKCTRL; @@ -4001,7 +4160,7 @@ typedef struct } CLKCTRL_B; }; - /** Argument register */ + /* Argument register */ union { __IOM uint32_t ARG; @@ -4012,7 +4171,7 @@ typedef struct } ARG_B; }; - /** Command register */ + /* Command register */ union { __IOM uint32_t CMD; @@ -4032,7 +4191,7 @@ typedef struct } CMD_B; }; - /** Command response register */ + /* Command response register */ union { __IM uint32_t CMDRES; @@ -4044,7 +4203,7 @@ typedef struct } CMDRES_B; }; - /** SDIO response register1 */ + /* SDIO response register1 */ union { __IM uint32_t RES1; @@ -4055,7 +4214,7 @@ typedef struct } RES1_B; }; - /** SDIO response register2 */ + /* SDIO response register2 */ union { __IM uint32_t RES2; @@ -4066,7 +4225,7 @@ typedef struct } RES2_B; }; - /** SDIO response register3 */ + /* SDIO response register3 */ union { __IM uint32_t RES3; @@ -4077,7 +4236,7 @@ typedef struct } RES3_B; }; - /** SDIO response register4 */ + /* SDIO response register4 */ union { __IM uint32_t RES4; @@ -4088,7 +4247,7 @@ typedef struct } RES4_B; }; - /** Data timer register */ + /* Data timer register */ union { __IOM uint32_t DATATIME; @@ -4099,7 +4258,7 @@ typedef struct } DTMR_B; }; - /** Data length register */ + /* Data length register */ union { __IOM uint32_t DATALEN; @@ -4111,7 +4270,7 @@ typedef struct } DLEN_B; }; - /** Data control register */ + /* Data control register */ union { __IOM uint32_t DCTRL; @@ -4131,7 +4290,7 @@ typedef struct } DCTRL_B; }; - /** Data count register */ + /* Data count register */ union { __IM uint32_t DCNT; @@ -4143,7 +4302,7 @@ typedef struct } DCNT_B; }; - /** SDIO status register */ + /* SDIO status register */ union { __IM uint32_t STS; @@ -4178,7 +4337,7 @@ typedef struct } STS_B; }; - /** SDIO interrupt clear register */ + /* SDIO interrupt clear register */ union { __IOM uint32_t ICF; @@ -4203,7 +4362,7 @@ typedef struct } ICF_B; }; - /** SDIO interrupt mask register */ + /* SDIO interrupt mask register */ union { __IOM uint32_t MASK; @@ -4240,7 +4399,7 @@ typedef struct __IM uint32_t RESERVED[2]; - /** SDIO FIFO count register */ + /* SDIO FIFO count register */ union { __IM uint32_t FIFOCNT; @@ -4254,7 +4413,7 @@ typedef struct __IM uint32_t RESERVED1[13]; - /** SDIO data FIFO register */ + /* SDIO data FIFO register */ union { __IOM uint32_t FIFODATA; @@ -4264,14 +4423,14 @@ typedef struct __IOM uint32_t FIFODATA : 32; } FIFODATA_B; }; -}SDIO_T; +} SDIO_T; /** * @brief Digital to Analog Converter(DAC) */ typedef struct { - /** Control register */ + /* Control register */ union { __IOM uint32_t CTRL; @@ -4297,7 +4456,7 @@ typedef struct } CTRL_B; }; - /** Software trigger register */ + /* Software trigger register */ union { __OM uint32_t SWTRG; @@ -4310,7 +4469,7 @@ typedef struct } SWTRG_B; }; - /** Channel1 12-bit right-aligned register */ + /* Channel1 12-bit right-aligned register */ union { __IOM uint32_t DH12R1; @@ -4322,7 +4481,7 @@ typedef struct } DH12R1_B; }; - /** Channel1 12-bit left-aligned register */ + /* Channel1 12-bit left-aligned register */ union { __IOM uint32_t DH12L1; @@ -4335,7 +4494,7 @@ typedef struct } DH12L1_B; }; - /** Channel1 8-bit right-aligned register */ + /* Channel1 8-bit right-aligned register */ union { __IOM uint32_t DH8R1; @@ -4347,19 +4506,19 @@ typedef struct } DH8R1_B; }; - /** Channel2 12-bit right-aligned register */ - union - { - __IOM uint32_t DH12R2; + /* Channel2 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12R2; - struct - { + struct + { __IOM uint32_t DATA : 12; __IM uint32_t RESERVED : 20; } DH12R2_B; }; - /** Channel2 12-bit left-aligned register */ + /* Channel2 12-bit left-aligned register */ union { __IOM uint32_t DH12L2; @@ -4369,10 +4528,10 @@ typedef struct __IM uint32_t RESERVED1 : 4; __IOM uint32_t DATA : 12; __IM uint32_t RESERVED2 : 16; - }DH12L2_B; + } DH12L2_B; }; - /** Channel2 8-bit right-aligned register */ + /* Channel2 8-bit right-aligned register */ union { __IOM uint32_t DH8R2; @@ -4384,7 +4543,7 @@ typedef struct } DH8R2_B; }; - /** Channel1,Channel2 12-bit right-aligned register */ + /* Channel1,Channel2 12-bit right-aligned register */ union { __IOM uint32_t DH12RDUAL; @@ -4398,7 +4557,7 @@ typedef struct } DH12RDUAL_B; }; - /** Channel1,Channel2 12-bit left-aligned register */ + /* Channel1,Channel2 12-bit left-aligned register */ union { __IOM uint32_t DH12LDUAL; @@ -4412,7 +4571,7 @@ typedef struct } DH12LDUAL_B; }; - /** Channel1,Channel2 8-bit right-aligned register */ + /* Channel1,Channel2 8-bit right-aligned register */ union { __IOM uint32_t DH8RDUAL; @@ -4425,7 +4584,7 @@ typedef struct } DH8RDUAL_B; }; - /** Channel1 data output register */ + /* Channel1 data output register */ union { __IM uint32_t DATAOCH1; @@ -4437,7 +4596,7 @@ typedef struct } DATAOCH1_B; }; - /** Channel2 data output register */ + /* Channel2 data output register */ union { __IM uint32_t DATAOCH2; @@ -4448,14 +4607,14 @@ typedef struct __IM uint32_t RESERVED : 20; } DATAOCH2_B; }; -}DAC_T; +} DAC_T; /** - * @brief EMMC Register + * @brief SMC Register */ typedef struct { - /** SRAM/NOR-Flash chip-select control register */ + /* SRAM/NOR-Flash chip-select control register */ union { __IOM uint32_t CSCTRL; @@ -4479,13 +4638,13 @@ typedef struct __IOM uint32_t CRAMPSIZECFG : 3; __IOM uint32_t WRBURSTEN : 1; __IOM uint32_t RESERVED2 : 12; - }CSCTRL_B; + } CSCTRL_B; }; -}SNCTRL_T; +} SNCTRL_T; typedef struct { - /** SRAM/NOR-Flash write timing registers */ + /* SRAM/NOR-Flash write timing registers */ union { __IOM uint32_t WRTTIM; @@ -4500,9 +4659,9 @@ typedef struct __IOM uint32_t DATALATCFG : 4; __IOM uint32_t ACCMODECFG : 2; __IM uint32_t RESERVED2 : 2; - }WRTTIM_T; + } WRTTIM_T; }; -}SNWCLK_T; +} SNWCLK_T; /** * @brief Flexible Static Memory Controller @@ -4510,7 +4669,7 @@ typedef struct typedef struct { __IO uint32_t SNCTRL_T[8]; -} EMMC_Bank1_T; +} SMC_Bank1_T; /** * @brief Flexible Static Memory Controller Bank1E @@ -4518,14 +4677,14 @@ typedef struct typedef struct { __IO uint32_t WRTTIM[7]; -} EMMC_Bank1E_T; +} SMC_Bank1E_T; /** * @brief Flexible Static Memory Controller Bank 2 */ typedef struct { - /** PC Card/NAND Flash control register 2 */ + /* PC Card/NAND Flash control register 2 */ union { __IOM uint32_t CTRL2; @@ -4543,10 +4702,10 @@ typedef struct __IOM uint32_t A2RDCFG : 4; __IOM uint32_t ECCPSCFG : 3; __IM uint32_t RESERVED3 : 12; - }CTRL2_B; + } CTRL2_B; }; - /** FIFO status and interrupt register 2 */ + /* FIFO status and interrupt register 2 */ union { __IOM uint32_t STSINT2; @@ -4560,10 +4719,10 @@ typedef struct __IOM uint32_t IHLDEN : 1; __IOM uint32_t IFEDEN : 1; __IM uint32_t FEFLG : 1; - __IM uint32_t RESERVED :25; - }STSINT2_B; + __IM uint32_t RESERVED : 25; + } STSINT2_B; }; - /** Common memory space timing register 2 */ + /* Common memory space timing register 2 */ union { __IOM uint32_t CMSTIM2; @@ -4574,10 +4733,10 @@ typedef struct __IOM uint32_t WAIT2 : 8; __IOM uint32_t HLD2 : 8; __IOM uint32_t HIZ2 : 8; - }CMSTIM2_B; + } CMSTIM2_B; }; - /** Attribute memory space timing register 2 */ + /* Attribute memory space timing register 2 */ union { __IOM uint32_t AMSTIM2; @@ -4588,12 +4747,12 @@ typedef struct __IOM uint32_t WAIT2 : 8; __IOM uint32_t HLD2 : 8; __IOM uint32_t HIZ2 : 8; - }AMSTIM2_B; + } AMSTIM2_B; }; __IOM uint32_t RESERVED; - /** ECC result register 2 */ + /* ECC result register 2 */ union { __IM uint32_t ECCRS2; @@ -4603,14 +4762,14 @@ typedef struct __IM uint32_t ECCRS2 : 32; } ECCRS2_B; }; -}EMMC_Bank2_T; +} SMC_Bank2_T; /** * @brief Flexible Static Memory Controller Bank 3 */ typedef struct { - /** PC Card/NAND Flash control register 3 */ + /* PC Card/NAND Flash control register 3 */ union { __IOM uint32_t CTRL3; @@ -4628,10 +4787,10 @@ typedef struct __IOM uint32_t A2RDCFG : 4; __IOM uint32_t ECCPSCFG : 3; __IM uint32_t RESERVED3 : 12; - }CTRL3_B; + } CTRL3_B; }; - /** FIFO status and interrupt register 3 */ + /* FIFO status and interrupt register 3 */ union { __IOM uint32_t STSINT3; @@ -4645,11 +4804,11 @@ typedef struct __IOM uint32_t IHLDEN : 1; __IOM uint32_t IFEDEN : 1; __IM uint32_t FEFLG : 1; - __IM uint32_t RESERVED :16; - }STSINT3_B; + __IM uint32_t RESERVED : 16; + } STSINT3_B; }; - /** Common memory space timing register 3 */ + /* Common memory space timing register 3 */ union { __IOM uint32_t CMSTIM3; @@ -4660,10 +4819,10 @@ typedef struct __IOM uint32_t WAIT3 : 8; __IOM uint32_t HLD3 : 8; __IOM uint32_t HIZ3 : 8; - }CMSTIM3_B; + } CMSTIM3_B; }; - /** Attribute memory space timing register 3 */ + /* Attribute memory space timing register 3 */ union { __IOM uint32_t AMSTIM3; @@ -4674,12 +4833,12 @@ typedef struct __IOM uint32_t WAIT3 : 8; __IOM uint32_t HLD3 : 8; __IOM uint32_t HIZ3 : 8; - }AMSTIM3_B; + } AMSTIM3_B; }; __IOM uint32_t RESERVED; - /** ECC result register 3 */ + /* ECC result register 3 */ union { __IM uint32_t ECCRS3; @@ -4689,14 +4848,14 @@ typedef struct __IM uint32_t ECCRS3 : 32; } ECCRS3_B; }; -}EMMC_Bank3_T; +} SMC_Bank3_T; /** * @brief Flexible Static Memory Controller Bank 4 */ typedef struct { - /** PC Card/NAND Flash control register 4 */ + /* PC Card/NAND Flash control register 4 */ union { __IOM uint32_t CTRL4; @@ -4714,10 +4873,10 @@ typedef struct __IOM uint32_t A2RDCFG : 4; __IOM uint32_t ECCPSCFG : 3; __IM uint32_t RESERVED3 : 12; - }CTRL4_B; + } CTRL4_B; }; - /** FIFO status and interrupt register 4 */ + /* FIFO status and interrupt register 4 */ union { __IOM uint32_t STSINT4; @@ -4731,11 +4890,11 @@ typedef struct __IOM uint32_t IHLDEN : 1; __IOM uint32_t IFEDEN : 1; __IM uint32_t FEFLG : 1; - __IM uint32_t RESERVED :16; - }STSINT4_B; + __IM uint32_t RESERVED : 16; + } STSINT4_B; }; - /** Common memory space timing register 4 */ + /* Common memory space timing register 4 */ union { __IOM uint32_t CMSTIM4; @@ -4746,10 +4905,10 @@ typedef struct __IOM uint32_t WAIT4 : 8; __IOM uint32_t HLD4 : 8; __IOM uint32_t HIZ4 : 8; - }CMSTIM4_B; + } CMSTIM4_B; }; - /** Attribute memory space timing register 4 */ + /* Attribute memory space timing register 4 */ union { __IOM uint32_t AMSTIM4; @@ -4760,10 +4919,10 @@ typedef struct __IOM uint32_t WAIT4 : 8; __IOM uint32_t HLD4 : 8; __IOM uint32_t HIZ4 : 8; - }AMSTIM4_B; + } AMSTIM4_B; }; - /** I/O space timing register 4 */ + /* I/O space timing register 4 */ union { __IOM uint32_t IOSTIM4; @@ -4774,16 +4933,16 @@ typedef struct __IOM uint32_t WAIT4 : 8; __IOM uint32_t HLD4 : 8; __IOM uint32_t HIZ4 : 8; - }IOSTIM4_B; + } IOSTIM4_B; }; -}EMMC_Bank4_T; +} SMC_Bank4_T; /** * @brief Queued serial peripheral interface(QSPI) */ typedef struct { - /** @brief Control register 1 */ + /* @brief Control register 1 */ union { __IOM uint32_t CTRL1; @@ -4799,10 +4958,10 @@ typedef struct __IM uint32_t RESERVED3 : 7; __IOM uint32_t FRF : 2; __IM uint32_t RESERVED4 : 8; - }CTRL1_B; + } CTRL1_B; }; - /** @brief Control register 2 */ + /* @brief Control register 2 */ union { __IOM uint32_t CTRL2; @@ -4810,10 +4969,10 @@ typedef struct { __IOM uint32_t NDF : 16; __IM uint32_t RESERVED : 16; - }CTRL2_B; + } CTRL2_B; }; - /** @brief QSPI Enable register */ + /* @brief QSPI Enable register */ union { __IOM uint32_t SSIEN; @@ -4821,12 +4980,12 @@ typedef struct { __IOM uint32_t EN : 1; __IM uint32_t RESERVED : 31; - }SSIEN_B; + } SSIEN_B; }; __IM uint32_t RESERVED; - /** @brief QSPI Slave enable register */ + /* @brief QSPI Slave enable register */ union { __IOM uint32_t SLAEN; @@ -4834,10 +4993,10 @@ typedef struct { __IOM uint32_t SLAEN : 1; __IM uint32_t RESERVED : 31; - }SLAEN_B; + } SLAEN_B; }; - /** @brief Baudrate register */ + /* @brief Baudrate register */ union { __IOM uint32_t BR; @@ -4845,10 +5004,10 @@ typedef struct { __IOM uint32_t CLKDIV : 16; __IM uint32_t RESERVED : 16; - }BR_B; + } BR_B; }; - /** @brief Transmission FIFO threshhold level register */ + /* @brief Transmission FIFO threshhold level register */ union { __IOM uint32_t TFTL; @@ -4858,10 +5017,10 @@ typedef struct __IM uint32_t RESERVED1 : 13; __IOM uint32_t TFTH : 3; __IM uint32_t RESERVED2 : 13; - }TFTL_B; + } TFTL_B; }; - /** @brief Reception FIFO threshhold level register */ + /* @brief Reception FIFO threshhold level register */ union { __IOM uint32_t RFTL; @@ -4869,10 +5028,10 @@ typedef struct { __IOM uint32_t RFT : 3; __IM uint32_t RESERVED : 29; - }RFTL_B; + } RFTL_B; }; - /** @brief Transmission FIFO level register */ + /* @brief Transmission FIFO level register */ union { __IOM uint32_t TFL; @@ -4880,10 +5039,10 @@ typedef struct { __IOM uint32_t TFL : 3; __IM uint32_t RESERVED : 29; - }TFL_B; + } TFL_B; }; - /** @brief Reception FIFO level register */ + /* @brief Reception FIFO level register */ union { __IOM uint32_t RFL; @@ -4891,10 +5050,10 @@ typedef struct { __IOM uint32_t RFL : 3; __IM uint32_t RESERVED : 29; - }RFL_B; + } RFL_B; }; - /** @brief Status register */ + /* @brief Status register */ union { __IOM uint32_t STS; @@ -4908,10 +5067,10 @@ typedef struct __IM uint32_t RESERVED1 : 1; __IOM uint32_t DCEF : 1; __IM uint32_t RESERVED2 : 25; - }STS_B; + } STS_B; }; - /** @brief Interrupt enable register */ + /* @brief Interrupt enable register */ union { __IOM uint32_t INTEN; @@ -4924,10 +5083,10 @@ typedef struct __IOM uint32_t RFFIE : 1; __IOM uint32_t MSTIE : 1; __IM uint32_t RESERVED : 26; - }INTEN_B; + } INTEN_B; }; - /** @brief Interrupt status register */ + /* @brief Interrupt status register */ union { __IM uint32_t ISTS; @@ -4940,10 +5099,10 @@ typedef struct __IM uint32_t RFFIF : 1; __IM uint32_t MSTIF : 1; __IM uint32_t RESERVED : 26; - }ISTS_B; + } ISTS_B; }; - /** @brief Raw interrupt register */ + /* @brief Raw interrupt register */ union { __IM uint32_t RIS; @@ -4956,10 +5115,10 @@ typedef struct __IM uint32_t RXFIR : 1; __IM uint32_t MSTIR : 1; __IM uint32_t RESERVED : 26; - }RIS_B; + } RIS_B; }; - /** @brief Transmission FIFO overflow interrupt clear register */ + /* @brief Transmission FIFO overflow interrupt clear register */ union { __IM uint32_t TFOIC; @@ -4967,10 +5126,10 @@ typedef struct { __IM uint32_t TFOIC : 1; __IM uint32_t RESERVED : 31; - }TFOIC_B; + } TFOIC_B; }; - /** @brief Reception FIFO overflow interrupt clear register */ + /* @brief Reception FIFO overflow interrupt clear register */ union { __IM uint32_t RFOIC; @@ -4978,10 +5137,10 @@ typedef struct { __IM uint32_t RFOIC : 1; __IM uint32_t RESERVED : 31; - }RFOIC_B; + } RFOIC_B; }; - /** @brief Reception FIFO underflow interrupt clear register */ + /* @brief Reception FIFO underflow interrupt clear register */ union { __IM uint32_t RFUIC; @@ -4989,10 +5148,10 @@ typedef struct { __IM uint32_t RFUIC : 1; __IM uint32_t RESERVED : 31; - }RFUIC_B; + } RFUIC_B; }; - /** @brief Master interrupt clear register */ + /* @brief Master interrupt clear register */ union { __IM uint32_t MIC; @@ -5000,10 +5159,10 @@ typedef struct { __IM uint32_t MIC : 1; __IM uint32_t RESERVED : 31; - }MIC_B; + } MIC_B; }; - /** @brief Interrupt clear register */ + /* @brief Interrupt clear register */ union { __IM uint32_t ICF; @@ -5011,24 +5170,24 @@ typedef struct { __IM uint32_t ICF : 1; __IM uint32_t RESERVED : 31; - }ICF_B; + } ICF_B; }; __IM uint32_t RESERVED1[5]; - /** @brief Data register */ + /* @brief Data register */ union { __IOM uint32_t DATA; struct { __IOM uint32_t DATA : 32; - }DATA_B; + } DATA_B; }; __IM uint32_t RESERVED2[35]; - /** @brief Reception sample register */ + /* @brief Reception sample register */ union { __IOM uint32_t RSD; @@ -5038,10 +5197,10 @@ typedef struct __IM uint32_t RESERVED1 : 8; __IOM uint32_t RSE : 1; __IM uint32_t RESERVED2 : 15; - }RSD_B; + } RSD_B; }; - /** @brief Reception sample register */ + /* @brief Reception sample register */ union { __IOM uint32_t CTRL3; @@ -5056,12 +5215,12 @@ typedef struct __IM uint32_t RESERVED3 : 14; __IOM uint32_t CSEN : 1; __IM uint32_t RESERVED4 : 1; - }CTRL3_B; + } CTRL3_B; }; __IM uint32_t RESERVED3[66]; - /** @brief IO switch register */ + /* @brief IO switch register */ union { __IOM uint32_t IOSW; @@ -5069,16 +5228,16 @@ typedef struct { __IOM uint32_t IOSW : 1; __IM uint32_t RESERVED : 31; - }IOSW_B; + } IOSW_B; }; -}QSPI_T; +} QSPI_T; /** * @brief SEC Inter-integrated circuit (SCI2C) */ typedef struct { - /** @brief Control register 1 */ + /* @brief Control register 1 */ union { __IOM uint32_t CTRL1; @@ -5095,10 +5254,10 @@ typedef struct __IOM uint32_t RFFIE : 1; __IOM uint32_t DSMA : 1; __IM uint32_t RESERVED2 : 21; - }CTRL1_B; + } CTRL1_B; }; - /** @brief Master address register */ + /* @brief Master address register */ union { __IOM uint32_t TARADDR; @@ -5109,10 +5268,10 @@ typedef struct __IOM uint32_t GCEN : 1; __IOM uint32_t MAM : 1; __IM uint32_t RESERVED : 19; - }TARADDR_B; + } TARADDR_B; }; - /** @brief Slave address register */ + /* @brief Slave address register */ union { __IOM uint32_t SLAADDR; @@ -5120,10 +5279,10 @@ typedef struct { __IOM uint32_t ADDR : 10; __IM uint32_t RESERVED : 22; - }SLAADDR_B; + } SLAADDR_B; }; - /** @brief High speed master code register */ + /* @brief High speed master code register */ union { __IOM uint32_t HSMC; @@ -5131,10 +5290,10 @@ typedef struct { __IOM uint32_t HSMC : 4; __IM uint32_t RESERVED : 28; - }HSMC_B; + } HSMC_B; }; - /** @brief Data register */ + /* @brief Data register */ union { __IOM uint32_t DATA; @@ -5144,10 +5303,10 @@ typedef struct __IOM uint32_t CMD : 1; __IOM uint32_t STOP : 1; __IM uint32_t RESERVED : 22; - }DATA_B; + } DATA_B; }; - /** @brief Standard speed clock high counter register */ + /* @brief Standard speed clock high counter register */ union { __IOM uint32_t SSCHC; @@ -5155,10 +5314,10 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }SSCHC_B; + } SSCHC_B; }; - /** @brief Standard speed clock low counter register */ + /* @brief Standard speed clock low counter register */ union { __IOM uint32_t SSCLC; @@ -5166,10 +5325,10 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }SSCLC_B; + } SSCLC_B; }; - /** @brief Fast speed clock high counter register */ + /* @brief Fast speed clock high counter register */ union { __IOM uint32_t FSCHC; @@ -5177,10 +5336,10 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }FSCHC_B; + } FSCHC_B; }; - /** @brief Fast speed clock low counter register */ + /* @brief Fast speed clock low counter register */ union { __IOM uint32_t FSCLC; @@ -5188,10 +5347,10 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }FSCLC_B; + } FSCLC_B; }; - /** @brief High speed clock high counter */ + /* @brief High speed clock high counter */ union { __IOM uint32_t HSCHC; @@ -5199,10 +5358,10 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }HSCHC_B; + } HSCHC_B; }; - /** @brief High speed clock low counter register */ + /* @brief High speed clock low counter register */ union { __IOM uint32_t HSCLC; @@ -5210,10 +5369,10 @@ typedef struct { __IOM uint32_t CNT : 16; __IM uint32_t RESERVED : 16; - }HSCLC_B; + } HSCLC_B; }; - /** @brief Interrupt status register */ + /* @brief Interrupt status register */ union { __IM uint32_t INTSTS; @@ -5234,10 +5393,10 @@ typedef struct __IM uint32_t RSTADIF : 1; __IM uint32_t MOHIF : 1; __IM uint32_t RESERVED : 18; - }INTSTS_B; + } INTSTS_B; }; - /** @brief Interrupt enable register */ + /* @brief Interrupt enable register */ union { __IOM uint32_t INTEN; @@ -5258,10 +5417,10 @@ typedef struct __IOM uint32_t RSTADIE : 1; __IOM uint32_t MOHIE : 1; __IM uint32_t RESERVED : 18; - }INTEN_B; + } INTEN_B; }; - /** @brief Raw interrupt status register */ + /* @brief Raw interrupt status register */ union { __IM uint32_t RIS; @@ -5282,10 +5441,10 @@ typedef struct __IM uint32_t RSTADIF : 1; __IM uint32_t MOHIF : 1; __IM uint32_t RESERVED : 18; - }RIS_B; + } RIS_B; }; - /** @brief Reception FIFO threshold register */ + /* @brief Reception FIFO threshold register */ union { __IOM uint32_t RFT; @@ -5293,10 +5452,10 @@ typedef struct { __IOM uint32_t RFT : 8; __IM uint32_t RESERVED : 24; - }RFT_B; + } RFT_B; }; - /** @brief Transmission FIFO threshold register */ + /* @brief Transmission FIFO threshold register */ union { __IOM uint32_t TFT; @@ -5304,10 +5463,10 @@ typedef struct { __IOM uint32_t TFT : 8; __IM uint32_t RESERVED : 24; - }TFT_B; + } TFT_B; }; - /** @brief Interruption clear register */ + /* @brief Interruption clear register */ union { __IM uint32_t INTCLR; @@ -5315,10 +5474,10 @@ typedef struct { __IM uint32_t INTCLR : 1; __IM uint32_t RESERVED : 31; - }INTCLR_B; + } INTCLR_B; }; - /** @brief Reception FIFO underflow interruption clear register */ + /* @brief Reception FIFO underflow interruption clear register */ union { __IM uint32_t RFUIC; @@ -5326,10 +5485,10 @@ typedef struct { __IM uint32_t RFUIC : 1; __IM uint32_t RESERVED : 31; - }RFUIC_B; + } RFUIC_B; }; - /** @brief Reception FIFO overflow interruption clear register */ + /* @brief Reception FIFO overflow interruption clear register */ union { __IM uint32_t RFOIC; @@ -5337,10 +5496,10 @@ typedef struct { __IM uint32_t RFOIC : 1; __IM uint32_t RESERVED : 31; - }RFOIC_B; + } RFOIC_B; }; - /** @brief Transmission FIFO overflow interruption clear register */ + /* @brief Transmission FIFO overflow interruption clear register */ union { __IM uint32_t TFOIC; @@ -5348,10 +5507,10 @@ typedef struct { __IM uint32_t TFOIC : 1; __IM uint32_t RESERVED : 31; - }TFOIC_B; + } TFOIC_B; }; - /** @brief Reception request interruption clear register */ + /* @brief Reception request interruption clear register */ union { __IM uint32_t RRIC; @@ -5359,10 +5518,10 @@ typedef struct { __IM uint32_t RRIC : 1; __IM uint32_t RESERVED : 31; - }RRIC_B; + } RRIC_B; }; - /** @brief Transmission abort interruption clear register */ + /* @brief Transmission abort interruption clear register */ union { __IM uint32_t TAIC; @@ -5370,10 +5529,10 @@ typedef struct { __IM uint32_t TAIC : 1; __IM uint32_t RESERVED : 31; - }TAIC_B; + } TAIC_B; }; - /** @brief Receive done interruption clear register */ + /* @brief Receive done interruption clear register */ union { __IM uint32_t RDIC; @@ -5381,10 +5540,10 @@ typedef struct { __IM uint32_t RDIC : 1; __IM uint32_t RESERVED : 31; - }RDIC_B; + } RDIC_B; }; - /** @brief Activity interruption clear register */ + /* @brief Activity interruption clear register */ union { __IM uint32_t AIC; @@ -5392,10 +5551,10 @@ typedef struct { __IM uint32_t AIC : 1; __IM uint32_t RESERVED : 31; - }AIC_B; + } AIC_B; }; - /** @brief Stop detection interruption clear register */ + /* @brief Stop detection interruption clear register */ union { __IM uint32_t STPDIC; @@ -5403,10 +5562,10 @@ typedef struct { __IM uint32_t STPDIC : 1; __IM uint32_t RESERVED : 31; - }STPDIC_B; + } STPDIC_B; }; - /** @brief Start detection interruption clear register */ + /* @brief Start detection interruption clear register */ union { __IM uint32_t STADIC; @@ -5414,10 +5573,10 @@ typedef struct { __IM uint32_t STADIC : 1; __IM uint32_t RESERVED : 31; - }STADIC_B; + } STADIC_B; }; - /** @brief General call interruption clear register */ + /* @brief General call interruption clear register */ union { __IM uint32_t GCIC; @@ -5425,10 +5584,10 @@ typedef struct { __IM uint32_t GCIC : 1; __IM uint32_t RESERVED : 31; - }GCIC_B; + } GCIC_B; }; - /** @brief Control register 2 */ + /* @brief Control register 2 */ union { __IOM uint32_t CTRL2; @@ -5438,10 +5597,10 @@ typedef struct __IOM uint32_t ABR : 1; __IOM uint32_t TCB : 1; __IM uint32_t RESERVED : 29; - }CTRL2_B; + } CTRL2_B; }; - /** @brief Status register 1 */ + /* @brief Status register 1 */ union { __IM uint32_t STS1; @@ -5455,10 +5614,10 @@ typedef struct __IM uint32_t MAF : 1; __IM uint32_t SAF : 1; __IM uint32_t RESERVED : 24; - }STS1_B; + } STS1_B; }; - /** @brief Transmission FIFO level */ + /* @brief Transmission FIFO level */ union { __IOM uint32_t TFL; @@ -5466,10 +5625,10 @@ typedef struct { __IOM uint32_t TFL : 4; __IM uint32_t RESERVED : 28; - }TFL_B; + } TFL_B; }; - /** @brief Reception FIFO level */ + /* @brief Reception FIFO level */ union { __IOM uint32_t RFL; @@ -5477,10 +5636,10 @@ typedef struct { __IOM uint32_t RFL : 4; __IM uint32_t RESERVED : 28; - }RFL_B; + } RFL_B; }; - /** @brief SDA hold time length register */ + /* @brief SDA hold time length register */ union { __IOM uint32_t SDAHOLD; @@ -5489,10 +5648,10 @@ typedef struct __IOM uint32_t TXHOLD : 16; __IOM uint32_t RXHOLD : 8; __IM uint32_t RESERVED : 8; - }SDAHOLD_B; + } SDAHOLD_B; }; - /** @brief Transmission abort source register */ + /* @brief Transmission abort source register */ union { __IM uint32_t TAS; @@ -5515,10 +5674,10 @@ typedef struct __IM uint32_t USRARB : 1; __IM uint32_t FLUCNT : 1; __IM uint32_t RESERVED : 16; - }TAS_B; + } TAS_B; }; - /** @brief Slave data NACK only register */ + /* @brief Slave data NACK only register */ union { __IOM uint32_t SDNO; @@ -5526,10 +5685,10 @@ typedef struct { __IOM uint32_t NACK : 1; __IM uint32_t RESERVED : 31; - }SDNO_B; + } SDNO_B; }; - /** @brief DMA control register */ + /* @brief DMA control register */ union { __IOM uint32_t DMACTRL; @@ -5538,10 +5697,10 @@ typedef struct __IOM uint32_t RXEN : 1; __IOM uint32_t TXEN : 1; __IM uint32_t RESERVED : 30; - }DMACTRL_B; + } DMACTRL_B; }; - /** @brief DMA transmission data level register */ + /* @brief DMA transmission data level register */ union { __IOM uint32_t DTDL; @@ -5549,10 +5708,10 @@ typedef struct { __IOM uint32_t DTDL : 4; __IM uint32_t RESERVED : 28; - }DTDL_B; + } DTDL_B; }; - /** @brief DMA teception data level register */ + /* @brief DMA teception data level register */ union { __IOM uint32_t DRDL; @@ -5560,10 +5719,10 @@ typedef struct { __IOM uint32_t DRDL : 4; __IM uint32_t RESERVED : 28; - }DRDL_B; + } DRDL_B; }; - /** @brief SDA delay register */ + /* @brief SDA delay register */ union { __IOM uint32_t SDADLY; @@ -5571,10 +5730,10 @@ typedef struct { __IOM uint32_t SDADLY : 8; __IM uint32_t RESERVED : 24; - }SDADLY_B; + } SDADLY_B; }; - /** @brief Genernal call ACK register */ + /* @brief Genernal call ACK register */ union { __IOM uint32_t GCA; @@ -5582,10 +5741,10 @@ typedef struct { __IOM uint32_t GCA : 1; __IM uint32_t RESERVED : 31; - }GCA_B; + } GCA_B; }; - /** @brief Status register 2 */ + /* @brief Status register 2 */ union { __IM uint32_t STS2; @@ -5595,10 +5754,10 @@ typedef struct __IM uint32_t SDWB : 1; __IM uint32_t SRDL : 1; __IM uint32_t RESERVED : 29; - }STS2_B; + } STS2_B; }; - /** @brief Low speed spike suppression limit */ + /* @brief Low speed spike suppression limit */ union { __IOM uint32_t LSSSL; @@ -5606,10 +5765,10 @@ typedef struct { __IOM uint32_t LSSSL : 8; __IM uint32_t RESERVED : 24; - }LSSSL_B; + } LSSSL_B; }; - /** @brief High speed spike suppression limit */ + /* @brief High speed spike suppression limit */ union { __IOM uint32_t HSSSL; @@ -5617,12 +5776,12 @@ typedef struct { __IOM uint32_t HSSSL : 8; __IM uint32_t RESERVED : 24; - }HSSSL_B; + } HSSSL_B; }; uint32_t RESERVED[22]; - /** @brief Switch register */ + /* @brief Switch register */ union { __IOM uint32_t SW; @@ -5630,16 +5789,16 @@ typedef struct { __IOM uint32_t SW : 1; __IM uint32_t RESERVED : 31; - }SW_B; + } SW_B; }; -}SCI2C_T; +} SCI2C_T; /** * @brief Dynamic memory controler (DMC) */ typedef struct { - /** @brief Configuraion register */ + /* @brief Configuraion register */ union { __IOM uint32_t CFG; @@ -5651,10 +5810,10 @@ typedef struct __IOM uint32_t CAWCFG : 4; __IOM uint32_t DWCFG : 2; __IM uint32_t RESERVED2 : 17; - }CFG_B; + } CFG_B; }; - /** @brief Timing register 0 */ + /* @brief Timing register 0 */ union { __IOM uint32_t TIM0; @@ -5670,10 +5829,10 @@ typedef struct __IOM uint32_t ATACP : 4; __IOM uint32_t ECASLSEL1 : 1; __IOM uint32_t EXSR1 : 5; - }TIM0_B; + } TIM0_B; }; - /** @brief Timing register 1 */ + /* @brief Timing register 1 */ union { __IOM uint32_t TIM1; @@ -5682,10 +5841,10 @@ typedef struct __IOM uint32_t STBTIM : 16; __IOM uint32_t ARNUMCFG : 4; __IM uint32_t RESERVED : 12; - }TIM1_B; + } TIM1_B; }; - /** @brief Control register 1 */ + /* @brief Control register 1 */ union { __IOM uint32_t CTRL1; @@ -5703,10 +5862,10 @@ typedef struct __IM uint32_t SRMFLG : 1; __IOM uint32_t BANKNUMCFG : 5; __IM uint32_t RESERVED2 : 15; - }CTRL1_B; + } CTRL1_B; }; - /** @brief Refresh register */ + /* @brief Refresh register */ union { __IOM uint32_t REF; @@ -5714,10 +5873,10 @@ typedef struct { __IOM uint32_t RCYCCFG : 16; __IM uint32_t RESERVED : 16; - }REF_B; + } REF_B; }; - /** @brief Chip select register */ + /* @brief Chip select register */ union { __IOM uint32_t CHIPSEL; @@ -5726,12 +5885,12 @@ typedef struct __IM uint32_t RESERVED : 16; __IOM uint32_t BACHIPSEL : 16; - }CHIPSEL_B; + } CHIPSEL_B; }; __IM uint32_t RESERVED[15]; - /** @brief Mask register */ + /* @brief Mask register */ union { __IOM uint32_t MASK; @@ -5740,12 +5899,12 @@ typedef struct __IOM uint32_t MSIZESEL : 5; __IOM uint32_t MTYPESEL : 3; __IM uint32_t RESERVED : 24; - }MASK_B; + } MASK_B; }; __IM uint32_t RESERVED1[234]; - /** @brief Switch register */ + /* @brief Switch register */ union { __IOM uint32_t SW; @@ -5753,10 +5912,10 @@ typedef struct { __IOM uint32_t MCSW : 1; __IM uint32_t RESERVED : 31; - }SW_B; + } SW_B; }; - /** @brief Control register 2 */ + /* @brief Control register 2 */ union { __IOM uint32_t CTRL2; @@ -5769,16 +5928,16 @@ typedef struct __IOM uint32_t BUFFEN : 1; __IOM uint32_t WRPBSEL : 1; __IM uint32_t RESERVED : 24; - }CTRL2_B; + } CTRL2_B; }; -}DMC_T; +} DMC_T; /** * @brief Debug MCU(DBGMCU) */ typedef struct { - /** @brief ID register */ + /* @brief ID register */ union { __IOM uint32_t IDCODE; @@ -5787,10 +5946,10 @@ typedef struct __IOM uint32_t EQR : 12; __IM uint32_t RESERVED : 4; __IOM uint32_t WVR : 16; - }IDCODE_B; + } IDCODE_B; }; - /** @brief Control register */ + /* @brief Control register */ union { __IOM uint32_t CFG; @@ -5824,9 +5983,9 @@ typedef struct __IOM uint32_t TMR10_STS : 1; __IOM uint32_t TMR11_STS : 1; __IM uint32_t RESERVED3 : 1; - }CFG_B; + } CFG_B; }; -}DBGMCU_T; +} DBGMCU_T; /** * @brief USB Device controler(USBD) @@ -5848,17 +6007,17 @@ typedef union __IOM uint32_t RXDTOG : 1; __IOM uint32_t CTFR : 1; __IM uint32_t RESERVED : 16; - }EP_B; -}USBD_EP_REG_T; + } EP_B; +} USBD_EP_REG_T; typedef struct { - /** Endpoint */ + /* Endpoint */ USBD_EP_REG_T EP[8]; __IM uint32_t RESERVED[8]; - /** @brief Control register */ + /* @brief Control register */ union { __IOM uint32_t CTRL; @@ -5880,10 +6039,10 @@ typedef struct __IOM uint32_t PMAOUIEN : 1; __IOM uint32_t CTRIEN : 1; __IM uint32_t RESERVED2 : 16; - }CTRL_B; + } CTRL_B; }; - /** @brief Interrupt status register */ + /* @brief Interrupt status register */ union { __IOM uint32_t INTSTS; @@ -5902,10 +6061,10 @@ typedef struct __IOM uint32_t PMOFLG : 1; __IOM uint32_t CTFLG : 1; __IM uint32_t RESERVED2 : 16; - }INTSTS_B; + } INTSTS_B; }; - /** @brief Frame number register */ + /* @brief Frame number register */ union { __IM uint32_t FRANUM; @@ -5918,10 +6077,10 @@ typedef struct __IM uint32_t RXDMSTS : 1; __IM uint32_t RXDPSTS : 1; __IM uint32_t RESERVED : 16; - }FRANUM_B; + } FRANUM_B; }; - /** @brief Device address register */ + /* @brief Device address register */ union { __IOM uint32_t ADDR; @@ -5931,10 +6090,10 @@ typedef struct __IOM uint32_t ADDR : 7; __IOM uint32_t USBDEN : 1; __IM uint32_t RESERVED : 24; - }ADDR_B; + } ADDR_B; }; - /** @brief Buffer table address register */ + /* @brief Buffer table address register */ union { __IOM uint32_t BUFFTB; @@ -5944,12 +6103,12 @@ typedef struct __IM uint32_t RESERVED1 : 3; __IOM uint32_t BUFFTB : 13; __IM uint32_t RESERVED2 : 16; - }BUFFTB_B; + } BUFFTB_B; }; __IM uint32_t RESERVED1[43]; - /** @brief Buffer table address register */ + /* @brief Buffer table address register */ union { __IOM uint32_t SWITCH; @@ -5958,30 +6117,743 @@ typedef struct { __IOM uint32_t SWITCH : 1; __IM uint32_t RESERVED : 31; - }SWITCH_B; + } SWITCH_B; }; -}USBD_T; +} USBD_T; -/** FMC base address in the alias region */ +/** + * @brief Ethernet: media access control (Ethernet_MAC) + */ + +typedef struct +{ + + union + { + __IOM uint32_t CFG; + + struct + { + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + __IOM uint32_t DC : 1; + __IOM uint32_t BL : 2; + __IOM uint32_t ACS : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t DISR : 1; + __IOM uint32_t IPC : 1; + __IOM uint32_t DM : 1; + __IOM uint32_t LBM : 1; + __IOM uint32_t DISRXO : 1; + __IOM uint32_t SSEL : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t DISCRS : 1; + __IOM uint32_t IFG : 3; + __IM uint32_t RESERVED4 : 2; + __IOM uint32_t JDIS : 1; + __IOM uint32_t WDTDIS : 1; + } CFG_B; + } ; + + union + { + __IOM uint32_t FRAF; + + struct + { + __IOM uint32_t PR : 1; + __IOM uint32_t HUC : 1; + __IOM uint32_t HMC : 1; + __IOM uint32_t DAIF : 1; + __IOM uint32_t PM : 1; + __IOM uint32_t DISBF : 1; + __IOM uint32_t PCTRLF : 1; + __IOM uint32_t SAIF : 1; + __IOM uint32_t SAFEN : 1; + __IOM uint32_t HPF : 1; + __IM uint32_t RESERVED1 : 21; + __IOM uint32_t RXA : 1; + } FRAF_B; + } ; + + union + { + __IOM uint32_t HTH; + + struct + { + __IOM uint32_t HTH : 32; + } HTH_B; + } ; + + union + { + __IOM uint32_t HTL; + + struct + { + __IOM uint32_t HTL : 32; + } HTL_B; + } ; + + union + { + __IOM uint32_t ADDR; + + struct + { + __IOM uint32_t MB : 1; + __IOM uint32_t MW : 1; + __IOM uint32_t CR : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t MR : 5; + __IOM uint32_t PA : 5; + } ADDR_B; + } ; + + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t MD : 16; + } DATA_B; + } ; + + union + { + __IOM uint32_t FCTRL; + + struct + { + __IOM uint32_t FCTRLB : 1; + __IOM uint32_t TXFCTRLEN : 1; + __IOM uint32_t RXFCTRLEN : 1; + __IOM uint32_t UNPFDETE : 1; + __IOM uint32_t PTSEL : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t ZQPDIS : 1; + __IM uint32_t RESERVED2 : 8; + __IOM uint32_t PT : 16; + } FCTRL_B; + } ; + + union + { + __IOM uint32_t VLANT; + + struct + { + __IOM uint32_t VLANTID : 16; + __IOM uint32_t VLANTCOMP : 1; + } VLANT_B; + } ; + __IM uint32_t RESERVED[2]; + __IOM uint32_t REMWKUPFFL; + + union + { + __IOM uint32_t PMTCTRLSTS; + + struct + { + __IOM uint32_t PD : 1; + __IOM uint32_t MPEN : 1; + __IOM uint32_t WKUPFEN : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t MPRX : 1; + __IOM uint32_t WKUPFRX : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t GUN : 1; + __IM uint32_t RESERVED3 : 21; + __IOM uint32_t WKUPFRST : 1; + } PMTCTRLSTS_B; + } ; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t ISTS; + + struct + { + __IM uint32_t RESERVED1 : 3; + __IM uint32_t PMTIS : 1; + __IM uint32_t MMCIS : 1; + __IM uint32_t MMCRXIS : 1; + __IM uint32_t MMCTXIS : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t TSIS : 1; + } ISTS_B; + } ; + + union + { + __IOM uint32_t IMASK; + + struct + { + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t PMTIM : 1; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t TSTIM : 1; + } IMASK_B; + } ; + + union + { + __IOM uint32_t ADDR0H; + + struct + { + __IOM uint32_t ADDR0H : 16; + __IM uint32_t RESERVED1 : 15; + __IM uint32_t AL1 : 1; + } ADDR0H_B; + } ; + + union + { + __IOM uint32_t ADDR0L; + + struct + { + __IOM uint32_t ADDR0L : 32; + } ADDR0L_B; + } ; + + union + { + __IOM uint32_t ADDR1H; + + struct + { + __IOM uint32_t ADDR1H : 16; + __IM uint32_t RESERVED1 : 8; + __IOM uint32_t MASKBCTRL : 6; + __IOM uint32_t ADDRSEL : 1; + __IOM uint32_t ADDREN : 1; + } ADDR1H_B; + } ; + + union + { + __IOM uint32_t ADDR1L; + + struct + { + __IOM uint32_t ADDR1L : 32; + } ADDR1L_B; + } ; + + union + { + __IOM uint32_t ADDR2H; + + struct + { + __IOM uint32_t ADDR2H : 16; + __IM uint32_t RESERVED1 : 8; + __IOM uint32_t MASKBCTRL : 6; + __IOM uint32_t ADDRSEL : 1; + __IOM uint32_t ADDREN : 1; + } ADDR2H_B; + } ; + + union + { + __IOM uint32_t ADDR2L; + + struct + { + __IOM uint32_t ADDR2L : 31; + } ADDR2L_B; + } ; + + union + { + __IOM uint32_t ADDR3H; + + struct + { + __IOM uint32_t ADDR3H : 16; + __IM uint32_t RESERVED1 : 8; + __IOM uint32_t MASKBCTRL : 6; + __IOM uint32_t ADDRSEL : 1; + __IOM uint32_t ADDREN : 1; + } ADDR3H_B; + } ; + + union + { + __IOM uint32_t ADDR3L; + + struct + { + __IOM uint32_t ADDR3L : 32; + } ADDR3L_B; + } ; + __IM uint32_t RESERVED2[40]; + + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t CNTRST : 1; + __IOM uint32_t CNTSTOPRO : 1; + __IOM uint32_t RSTOR : 1; + __IOM uint32_t MCNTF : 1; + __IM uint32_t RESERVED1 : 28; + } CTRL_B; + } ; + + union + { + __IOM uint32_t RXINT; + + struct + { + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t RXFCE : 1; + __IOM uint32_t RXFAE : 1; + __IM uint32_t RESERVED2 : 10; + __IOM uint32_t RXGUNF : 1; + } RXINT_B; + } ; + + union + { + __IOM uint32_t TXINT; + + struct + { + __IM uint32_t RESERVED1 : 14; + __IOM uint32_t TXGFSCOL : 1; + __IOM uint32_t TXGFMCOL : 1; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t TXGF : 1; + } TXINT_B; + } ; + + union + { + __IOM uint32_t RXINTMASK; + + struct + { + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t RXFCEM : 1; + __IOM uint32_t RXFAEM : 1; + __IM uint32_t RESERVED2 : 10; + __IOM uint32_t RXGUNFM : 1; + } RXINTMASK_B; + } ; + + union + { + __IOM uint32_t TXINTMASK; + + struct + { + __IM uint32_t RESERVED1 : 14; + __IOM uint32_t TXGFSCOLM : 1; + __IOM uint32_t TXGFMCOLM : 1; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t TXGFM : 1; + } TXINTMASK_B; + } ; + __IM uint32_t RESERVED3[14]; + + union + { + __IM uint32_t TXGFSCCNT; + + struct + { + __IM uint32_t TXGFSCCNT : 32; + } TXGFSCCNT_B; + } ; + + union + { + __IM uint32_t TXGFMCCNT; + + struct + { + __IM uint32_t TXGFMCCNT : 32; + } TXGFMCCNT_B; + } ; + __IM uint32_t RESERVED4[5]; + + union + { + __IM uint32_t TXGFCNT; + + struct + { + __IM uint32_t TXGFCNT : 32; + } TXGFCNT_B; + } ; + __IM uint32_t RESERVED5[10]; + + union + { + __IM uint32_t RXFCECNT; + + struct + { + __IM uint32_t RXFCECNT : 32; + } RXFCECNT_B; + } ; + + union + { + __IM uint32_t RXFAECNT; + + struct + { + __IM uint32_t RXFAECNT : 32; + } RXFAECNT_B; + } ; + __IM uint32_t RESERVED6[10]; + + union + { + __IM uint32_t RXGUNCNT; + + struct + { + __IM uint32_t RXGUNCNT : 32; + } RXGUNCNT_B; + } ; + __IM uint32_t RESERVED7[334]; + + union + { + __IOM uint32_t TSCTRL; + + struct + { + __IOM uint32_t TSEN : 1; + __IOM uint32_t TSUDSEL : 1; + __IOM uint32_t TSSTINIT : 1; + __IOM uint32_t TSSTUD : 1; + __IOM uint32_t TSTRGIEN : 1; + __IOM uint32_t TSADDUD : 1; + } TSCTRL_B; + } ; + + union + { + __IOM uint32_t SUBSECI; + + struct + { + __IOM uint32_t STSUBSECI : 8; + } SUBSECI_B; + } ; + + union + { + __IM uint32_t TSH; + + struct + { + __IM uint32_t STSEC : 32; + } TSH_B; + } ; + + union + { + __IM uint32_t TSL; + + struct + { + __IM uint32_t STSUBSEC : 31; + __IM uint32_t STSEL : 1; + } TSL_B; + } ; + + union + { + __IOM uint32_t TSHUD; + + struct + { + __IOM uint32_t TSUDSEC : 32; + } TSHUD_B; + } ; + + union + { + __IOM uint32_t TSLUD; + + struct + { + __IOM uint32_t TSUDSUBSEC : 31; + __IOM uint32_t TSUDSEL : 1; + } TSLUD_B; + } ; + + union + { + __IOM uint32_t TSA; + + struct + { + __IOM uint32_t TSA : 32; + } TSA_B; + } ; + + union + { + __IOM uint32_t TTSH; + + struct + { + __IOM uint32_t TTSH : 32; + } TTSH_B; + } ; + + union + { + __IOM uint32_t TTSL; + + struct + { + __IOM uint32_t TTSL : 32; + } TTSL_B; + } ; + __IM uint32_t RESERVED8[567]; + + union + { + __IOM uint32_t DMABMOD; + + struct + { + __IOM uint32_t SWR : 1; + __IOM uint32_t DAS : 1; + __IOM uint32_t DSL : 5; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PBL : 6; + __IOM uint32_t PR : 2; + __IOM uint32_t FB : 1; + __IOM uint32_t RPBL : 6; + __IOM uint32_t USP : 1; + __IOM uint32_t PBLx4 : 1; + __IOM uint32_t AAL : 1; + } DMABMOD_B; + } ; + + union + { + __IOM uint32_t DMATXPD; + + struct + { + __IOM uint32_t TXPD : 32; + } DMATXPD_B; + } ; + + union + { + __IOM uint32_t DMARXPD; + + struct + { + __IOM uint32_t RXPD : 32; + } DMARXPD_B; + } ; + + union + { + __IOM uint32_t DMARXDLADDR; + + struct + { + __IOM uint32_t RXSTA : 32; + } DMARXDLADDR_B; + } ; + + union + { + __IOM uint32_t DMATXDLADDR; + + struct + { + __IOM uint32_t TXSTA : 32; + } DMATXDLADDR_B; + } ; + + union + { + __IOM uint32_t DMASTS; + + struct + { + __IOM uint32_t TXFLG : 1; + __IOM uint32_t TXSFLG : 1; + __IOM uint32_t TXBU : 1; + __IOM uint32_t TXJTO : 1; + __IOM uint32_t RXOVF : 1; + __IOM uint32_t TXUNF : 1; + __IOM uint32_t RXFLG : 1; + __IOM uint32_t RXBU : 1; + __IOM uint32_t RXSFLG : 1; + __IOM uint32_t RXWTOFLG : 1; + __IOM uint32_t ETXFLG : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t FBERRFLG : 1; + __IOM uint32_t ERXFLG : 1; + __IOM uint32_t AINTS : 1; + __IOM uint32_t NINTS : 1; + __IM uint32_t RXSTS : 3; + __IM uint32_t TXSTS : 3; + __IM uint32_t ERRB : 3; + __IM uint32_t RESERVED2 : 1; + __IM uint32_t MMCFLG : 1; + __IM uint32_t PMTFLG : 1; + __IM uint32_t TSTFLG : 1; + } DMASTS_B; + } ; + + union + { + __IOM uint32_t DMAOPMOD; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t STRX : 1; + __IOM uint32_t OSECF : 1; + __IOM uint32_t RXTHCTRL : 2; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t FUF : 1; + __IOM uint32_t FERRF : 1; + __IM uint32_t RESERVED3 : 5; + __IOM uint32_t STTX : 1; + __IOM uint32_t TXTHCTRL : 3; + __IM uint32_t RESERVED4 : 3; + __IOM uint32_t FTXF : 1; + __IOM uint32_t TXSF : 1; + __IM uint32_t RESERVED5 : 2; + __IOM uint32_t DISFRXF : 1; + __IOM uint32_t RXSF : 1; + __IOM uint32_t DISDT : 1; + } DMAOPMOD_B; + } ; + + union + { + __IOM uint32_t DMAINTEN; + + struct + { + __IOM uint32_t TXIEN : 1; + __IOM uint32_t TXSEN : 1; + __IOM uint32_t TXBUEN : 1; + __IOM uint32_t TXJTOEN : 1; + __IOM uint32_t RXOVFEN : 1; + __IOM uint32_t TXUNFEN : 1; + __IOM uint32_t RXIEN : 1; + __IOM uint32_t RXBUEN : 1; + __IOM uint32_t RXSEN : 1; + __IOM uint32_t RXWTOEN : 1; + __IOM uint32_t ETXIEN : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t FBERREN : 1; + __IOM uint32_t ERXIEN : 1; + __IOM uint32_t AINTSEN : 1; + __IOM uint32_t NINTSEN : 1; + } DMAINTEN_B; + } ; + + union + { + __IM uint32_t DMAMFABOCNT; + + struct + { + __IM uint32_t MISFCNT : 16; + __IM uint32_t MISFCNTOVF : 1; + __IM uint32_t AMISFCNT : 11; + __IM uint32_t OVFCNTOVF : 1; + } DMAMFABOCNT_B; + } ; + __IM uint32_t RESERVED9[9]; + + union + { + __IM uint32_t DMAHTXD; + + struct + { + __IM uint32_t HTXDADDRP : 32; + } DMAHTXD_B; + } ; + + union + { + __IM uint32_t DMAHRXD; + + struct + { + __IM uint32_t HRXDADDRP : 32; + } DMAHRXD_B; + } ; + + union + { + __IM uint32_t DMAHTXBADDR; + + struct + { + __IM uint32_t HTXBADDRP : 32; + } DMAHTXBADDR_B; + } ; + + union + { + __IM uint32_t DMAHRXBADDR; + + struct + { + __IM uint32_t HRXBADDRP : 32; + } DMAHRXBADDR_B; + } ; +} ETH_T; + +/**@} end of group Peripheral_registers_structures*/ + +/** @defgroup Peripheral_memory_map + @{ +*/ + +/* FMC base address in the alias region */ #define FMC_BASE ((uint32_t)0x08000000) -/** SRAM base address in the alias region */ +/* SRAM base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) -/** Peripheral base address in the alias region */ +/* Peripheral base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) -/** SRAM base address in the bit-band region */ +/* SRAM base address in the bit-band region */ #define SRAM_BB_BASE ((uint32_t)0x22000000) -/** Peripheral base address in the bit-band region */ +/* Peripheral base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) -/** EMMC registers base address */ -#define EMMC_R_BASE ((uint32_t)0xA0000000) -/** QSPI registers base address */ +/* SMC registers base address */ +#define SMC_R_BASE ((uint32_t)0xA0000000) +/* QSPI registers base address */ #define QSPI_BASE ((uint32_t)0xA0000000) -/** DMC registers base address */ +/* DMC registers base address */ #define DMC_BASE ((uint32_t)0xA0000000) -/** Peripheral memory map */ +/* Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) @@ -6056,25 +6928,36 @@ typedef struct #define RCM_BASE (AHBPERIPH_BASE + 0x1000) #define CRC_BASE (AHBPERIPH_BASE + 0x3000) -/** FMC registers base address */ +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) +/* FMC registers base address */ #define FMC_R_BASE (AHBPERIPH_BASE + 0x2000) -/** FMC Option Bytes base address */ +/* FMC Option Bytes base address */ #define OB_BASE ((uint32_t)0x1FFFF800) -/** EMMC Bank1 registers base address */ -#define EMMC_Bank1_R_BASE (EMMC_R_BASE + 0x0000) -/** EMMC Bank1E registers base address */ -#define EMMC_Bank1E_R_BASE (EMMC_R_BASE + 0x0104) -/** EMMC Bank2 registers base address */ -#define EMMC_Bank2_R_BASE (EMMC_R_BASE + 0x0060) -/** EMMC Bank3 registers base address */ -#define EMMC_Bank3_R_BASE (EMMC_R_BASE + 0x0080) -/**EMMC Bank4 registers base address */ -#define EMMC_Bank4_R_BASE (EMMC_R_BASE + 0x00A0) +/* SMC Bank1 registers base address */ +#define SMC_Bank1_R_BASE (SMC_R_BASE + 0x0000) +/* SMC Bank1E registers base address */ +#define SMC_Bank1E_R_BASE (SMC_R_BASE + 0x0104) +/* SMC Bank2 registers base address */ +#define SMC_Bank2_R_BASE (SMC_R_BASE + 0x0060) +/* SMC Bank3 registers base address */ +#define SMC_Bank3_R_BASE (SMC_R_BASE + 0x0080) +/*SMC Bank4 registers base address */ +#define SMC_Bank4_R_BASE (SMC_R_BASE + 0x00A0) -/** Debug MCU registers base address */ +/* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t)0xE0042000) +/**@} end of group Peripheral_memory_map*/ + +/** @defgroup Peripheral_declaration + @{ +*/ + #define CRC ((CRC_T *) CRC_BASE) #define RTC ((RTC_T *) RTC_BASE) #define PMU ((PMU_T *) PMU_BASE) @@ -6154,11 +7037,11 @@ typedef struct #define FMC ((FMC_T *) FMC_R_BASE) #define USBD ((USBD_T *)USBD_BASE) -#define EMMC_Bank1 ((EMMC_Bank1_T *) EMMC_Bank1_R_BASE) -#define EMMC_Bank1E ((EMMC_Bank1E_T *)EMMC_Bank1E_R_BASE) -#define EMMC_Bank2 ((EMMC_Bank2_T *) EMMC_Bank2_R_BASE) -#define EMMC_Bank3 ((EMMC_Bank3_T *) EMMC_Bank3_R_BASE) -#define EMMC_Bank4 ((EMMC_Bank4_T *) EMMC_Bank4_R_BASE) +#define SMC_Bank1 ((SMC_Bank1_T *) SMC_Bank1_R_BASE) +#define SMC_Bank1E ((SMC_Bank1E_T *)SMC_Bank1E_R_BASE) +#define SMC_Bank2 ((SMC_Bank2_T *) SMC_Bank2_R_BASE) +#define SMC_Bank3 ((SMC_Bank3_T *) SMC_Bank3_R_BASE) +#define SMC_Bank4 ((SMC_Bank4_T *) SMC_Bank4_R_BASE) #define DBGMCU ((DBGMCU_T *) DBGMCU_BASE) @@ -6172,7 +7055,17 @@ typedef struct #define DMC ((DMC_T *)DMC_BASE) #endif -/** Define one bit mask */ +#if defined (APM32F10X_CL) +#define ETH ((ETH_T *) ETH_BASE) +#endif + +/**@} end of group Peripheral_declaration*/ + +/** @defgroup Exported_Macros + @{ +*/ + +/* Define one bit mask */ #define BIT0 ((uint32_t)0x00000001) #define BIT1 ((uint32_t)0x00000002) #define BIT2 ((uint32_t)0x00000004) @@ -6220,11 +7113,12 @@ typedef struct #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) +/**@} end of group Exported_Macros*/ +/**@} end of group APM32F10x */ +/**@} end of group CMSIS */ #ifdef __cplusplus } #endif #endif /* __APM32F10X_H */ - - diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h index dfc9df718f..2526840737 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h @@ -3,9 +3,9 @@ * * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,21 +23,40 @@ * and limitations under the License. */ +/* Define to prevent recursive inclusion */ #ifndef __SYSTEM_APM32F10X_H #define __SYSTEM_APM32F10X_H +/* Includes */ +#include "apm32f10x.h" + #ifdef __cplusplus - extern "C" { +extern "C" { #endif +/** @addtogroup CMSIS + @{ +*/ + +/** @addtogroup APM32F10x_System + @{ +*/ + +/** @defgroup System_Variables + @{ +*/ + extern uint32_t SystemCoreClock; extern void SystemInit(void); extern void SystemCoreClockUpdate(void); +/**@} end of group System_Functions */ +/**@} end of group APM32F10x_System */ +/**@} end of group CMSIS */ + #ifdef __cplusplus } #endif #endif /*__SYSTEM_APM32F10X_H */ - diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_cl.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_cl.s new file mode 100644 index 0000000000..5ad9c62bd4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_cl.s @@ -0,0 +1,365 @@ +;/*! +; * @file startup_apm32f10x_cl.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_cl +; * +; * @version V1.0.0 +; * +; * @date 2022-07-25 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCM_IRQHandler ; RCM + DCD EINT0_IRQHandler ; EINT Line 0 + DCD EINT1_IRQHandler ; EINT Line 1 + DCD EINT2_IRQHandler ; EINT Line 2 + DCD EINT3_IRQHandler ; EINT Line 3 + DCD EINT4_IRQHandler ; EINT Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EINT9_5_IRQHandler ; EINT Line 9..5 + DCD TMR1_BRK_IRQHandler ; TMR1 Break + DCD TMR1_UP_IRQHandler ; TMR1 Update + DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR4_IRQHandler ; TMR4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EINT15_10_IRQHandler ; EINT Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line + DCD OTG_FS_WKUP_IRQHandler ; USBD Wakeup from suspend + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TMR5_IRQHandler ; TMR5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; ETH + DCD ETH_WKUP_IRQHandler ; ETH Wake up + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EINT9_5_IRQHandler [WEAK] + EXPORT TMR1_BRK_IRQHandler [WEAK] + EXPORT TMR1_UP_IRQHandler [WEAK] + EXPORT TMR1_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EINT15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TMR5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TMR6_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDT_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCM_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EINT9_5_IRQHandler +TMR1_BRK_IRQHandler +TMR1_UP_IRQHandler +TMR1_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EINT15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TMR5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;*******************************END OF FILE************************************ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s index 956b00b8aa..683165208e 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s @@ -3,9 +3,9 @@ ; * ; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd ; * -; * @version V1.0.2 +; * @version V1.0.3 ; * -; * @date 2022-01-05 +; * @date 2022-07-25 ; * ; * @attention ; * @@ -15,7 +15,7 @@ ; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). ; * ; * The program is only for reference, which is distributed in the hope -; * that it will be usefull and instructional for customers to develop +; * that it will be useful and instructional for customers to develop ; * their software. Unless required by applicable law or agreed to in ; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT ; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s index b8c17b31cd..155181bba6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_md.s @@ -3,9 +3,9 @@ ; * ; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md ; * -; * @version V1.0.2 +; * @version V1.0.3 ; * -; * @date 2022-01-05 +; * @date 2022-07-25 ; * ; * @attention ; * @@ -15,7 +15,7 @@ ; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). ; * ; * The program is only for reference, which is distributed in the hope -; * that it will be usefull and instructional for customers to develop +; * that it will be useful and instructional for customers to develop ; * their software. Unless required by applicable law or agreed to in ; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT ; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx4.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx4.ld new file mode 100644 index 0000000000..1494fff267 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx4.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xx4.ld + * + * @brief Linker script for APM32F10xx4 Device with + * 16KByte FLASH, 6KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0004000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00001800; + +/* Stack / Heap Configuration */ +_end_stack = 0x20001800; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx6.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx6.ld new file mode 100644 index 0000000000..cb6062538d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx6.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xx6.ld + * + * @brief Linker script for APM32F10xx6 Device with + * 32KByte FLASH, 10KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0008000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00002800; + +/* Stack / Heap Configuration */ +_end_stack = 0x20002800; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx8.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx8.ld new file mode 100644 index 0000000000..c6e015782d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx8.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xx8.ld + * + * @brief Linker script for APM32F103xE Device with + * 64KByte FLASH, 20KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0010000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00005000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20005000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxB.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxB.ld new file mode 100644 index 0000000000..a22aa0d0ce --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxB.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xxB.ld + * + * @brief Linker script for APM32F10xxB Device with + * 128KByte FLASH, 20KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0020000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00005000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20005000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxC.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxC.ld new file mode 100644 index 0000000000..f63d5fb2ca --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxC.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xxC.ld + * + * @brief Linker script for APM32F10xxC Device with + * 256KByte FLASH, 64KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0040000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00010000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20010000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxD.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxD.ld new file mode 100644 index 0000000000..aa5f7d7be8 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxD.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xxD.ld + * + * @brief Linker script for APM32F10xxD Device with + * 384KByte FLASH, 64KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0080000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00010000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20010000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxE.ld b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxE.ld new file mode 100644 index 0000000000..f54b580502 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxE.ld @@ -0,0 +1,164 @@ +/*! + * @file gcc_APM32F10xxE.ld + * + * @brief Linker script for APM32F10xxE Device with + * 512KByte FLASH, 128KByte RAM + * + * @version V1.0.0 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Flash Configuration*/ +/* Flash Base Address */ +_rom_base = 0x8000000; +/*Flash Size (in Bytes) */ +_rom_size = 0x0080000; + +/* Embedded RAM Configuration */ +/* RAM Base Address */ +_ram_base = 0x20000000; +/* RAM Size (in Bytes) */ +_ram_size = 0x00020000; + +/* Stack / Heap Configuration */ +_end_stack = 0x20020000; +/* Heap Size (in Bytes) */ +_heap_size = 0x200; +/* Stack Size (in Bytes) */ +_stack_size = 0x400; + +MEMORY +{ +FLASH (rx) : ORIGIN = _rom_base, LENGTH = _rom_size +RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size +} + +SECTIONS +{ + .apm32_isr_vector : + { + . = ALIGN(4); + KEEP(*(.apm32_isr_vector)) + . = ALIGN(4); + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + _start_address_init_data = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _start_address_data = .; + *(.data) + *(.data*) + + . = ALIGN(4); + _end_address_data = .; + } >RAM AT> FLASH + + + . = ALIGN(4); + .bss : + { + + _start_address_bss = .; + __bss_start__ = _start_address_bss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _end_address_bss = .; + __bss_end__ = _end_address_bss; + } >RAM + + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _heap_size; + . = . + _stack_size; + . = ALIGN(8); + } >RAM + + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_cl.S b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_cl.S new file mode 100644 index 0000000000..ccc0657e34 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_cl.S @@ -0,0 +1,397 @@ +/*! + * @file startup_apm32f103_hd.S + * + * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd + * + * @version V1.0.1 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_apm32_Vectors +.global Default_Handler + +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +// Reset handler routine +Reset_Handler: + + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 + +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 + +L_loop2: + str r3, [r2] + adds r2, r2, #4 + +L_loop1: + cmp r2, r4 + bcc L_loop2 + + bl SystemInit + bl __libc_init_array + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler + +// The minimal vector table for a Cortex M3. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + + .word _end_stack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + .word WWDT_IRQHandler // Window Watchdog + .word PVD_IRQHandler // PVD through EINT Line detect + .word TAMPER_IRQHandler // Tamper + .word RTC_IRQHandler // RTC + .word FLASH_IRQHandler // Flash + .word RCM_IRQHandler // RCM + .word EINT0_IRQHandler // EINT Line 0 + .word EINT1_IRQHandler // EINT Line 1 + .word EINT2_IRQHandler // EINT Line 2 + .word EINT3_IRQHandler // EINT Line 3 + .word EINT4_IRQHandler // EINT Line 4 + .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 + .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 + .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 + .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 + .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 + .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 + .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 + .word ADC1_2_IRQHandler // ADC1 & ADC2 + .word CAN1_TX_IRQHandler // CAN1 TX + .word CAN1_RX0_IRQHandler // CAN1 RX0 + .word CAN1_RX1_IRQHandler // CAN1 RX1 + .word CAN1_SCE_IRQHandler // CAN1 SCE + .word EINT9_5_IRQHandler // EINT Line 9..5 + .word TMR1_BRK_IRQHandler // TMR1 Break + .word TMR1_UP_IRQHandler // TMR1 Update + .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR4_IRQHandler // TMR4 + .word I2C1_EV_IRQHandler // I2C1 Event + .word I2C1_ER_IRQHandler // I2C1 Error + .word I2C2_EV_IRQHandler // I2C2 Event + .word I2C2_ER_IRQHandler // I2C2 Error + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_IRQHandler // USART3 + .word EINT15_10_IRQHandler // EINT Line 15..10 + .word RTC_Alarm_IRQHandler // RTC Alarm through EINT Line + .word OTG_FS_WKUP_IRQHandler // USBD Wakeup from suspend + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word TMR5_IRQHandler // TMR5 + .word SPI3_IRQHandler // SPI3 + .word UART4_IRQHandler // UART4 + .word UART5_IRQHandler // UART5 + .word TMR6_IRQHandler // TMR6 + .word TMR7_IRQHandler // TMR7 + .word DMA2_Channel1_IRQHandler // DMA2 Channel1 + .word DMA2_Channel2_IRQHandler // DMA2 Channel2 + .word DMA2_Channel3_IRQHandler // DMA2 Channel3 + .word DMA2_Channel4_IRQHandler // DMA2 Channel4 + .word DMA2_Channel5_IRQHandler // DMA2 Channel5 + .word ETH_IRQHandler // ETH + .word ETH_WKUP_IRQHandler // ETH Wake up + .word CAN2_TX_IRQHandler // CAN2 TX + .word CAN2_RX0_IRQHandler // CAN2 RX0 + .word CAN2_RX1_IRQHandler // CAN2 RX1 + .word CAN2_SCE_IRQHandler // CAN2 SCE + .word OTG_FS_IRQHandler // OTG FS + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_IRQHandler + .thumb_set RCM_IRQHandler,Default_Handler + + .weak EINT0_IRQHandler + .thumb_set EINT0_IRQHandler,Default_Handler + + .weak EINT1_IRQHandler + .thumb_set EINT1_IRQHandler,Default_Handler + + .weak EINT2_IRQHandler + .thumb_set EINT2_IRQHandler,Default_Handler + + .weak EINT3_IRQHandler + .thumb_set EINT3_IRQHandler,Default_Handler + + .weak EINT4_IRQHandler + .thumb_set EINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBD_HP_CAN1_TX_IRQHandler + .thumb_set USBD_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USBD_LP_CAN1_RX0_IRQHandler + .thumb_set USBD_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EINT9_5_IRQHandler + .thumb_set EINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_IRQHandler + .thumb_set TMR1_BRK_IRQHandler,Default_Handler + + .weak TMR1_UP_IRQHandler + .thumb_set TMR1_UP_IRQHandler,Default_Handler + + .weak TMR1_TRG_COM_IRQHandler + .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR4_IRQHandler + .thumb_set TMR4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EINT15_10_IRQHandler + .thumb_set EINT15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TMR5_IRQHandler + .thumb_set TMR5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_IRQHandler + .thumb_set TMR6_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s index 1f0b8fd4b4..70654b22b6 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s @@ -1,281 +1,398 @@ -;/*! -; * @file startup_apm32f10x_hd.s -; * -; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd -; * -; * @version V1.0.0 -; * -; * @date 2022-01-05 -; * -; * @attention -; * -; * Copyright (C) 2020-2022 Geehy Semiconductor -; * -; * You may not use this file except in compliance with the -; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). -; * -; * The program is only for reference, which is distributed in the hope -; * that it will be usefull and instructional for customers to develop -; * their software. Unless required by applicable law or agreed to in -; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT -; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. -; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions -; * and limitations under the License. -; */ +/*! + * @file startup_apm32f103_hd.S + * + * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd + * + * @version V1.0.1 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ -.syntax unified -.cpu cortex-m3 -.fpu softvfp -.thumb + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb -.global g_pfnVectors -.global Default_Handler +.global g_apm32_Vectors +.global Default_Handler - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss -g_pfnVectors: - .word _estack // Top of Stack - .word Reset_Handler // Reset Handler - .word NMI_Handler // NMI Handler - .word HardFault_Handler // Hard Fault Handler - .word MemManage_Handler // MPU Fault Handler - .word BusFault_Handler // Bus Fault Handler - .word UsageFault_Handler // Usage Fault Handler - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word SVC_Handler // SVCall Handler - .word DebugMon_Handler // Debug Monitor Handler - .word 0 // Reserved - .word PendSV_Handler // PendSV Handler - .word SysTick_Handler // SysTick Handler - - // external interrupts handler - .word WWDT_IRQHandler // Window Watchdog - .word PVD_IRQHandler // PVD through EINT Line detect - .word TAMPER_IRQHandler // Tamper - .word RTC_IRQHandler // RTC - .word FLASH_IRQHandler // Flash - .word RCM_IRQHandler // RCM - .word EINT0_IRQHandler // EINT Line 0 - .word EINT1_IRQHandler // EINT Line 1 - .word EINT2_IRQHandler // EINT Line 2 - .word EINT3_IRQHandler // EINT Line 3 - .word EINT4_IRQHandler // EINT Line 4 - .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 - .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 - .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 - .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 - .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 - .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 - .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 - .word ADC1_2_IRQHandler // ADC1 & ADC2 - .word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX - .word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 - .word CAN1_RX1_IRQHandler // CAN1 RX1 - .word CAN1_SCE_IRQHandler // CAN1 SCE - .word EINT9_5_IRQHandler // EINT Line 9..5 - .word TMR1_BRK_IRQHandler // TMR1 Break - .word TMR1_UP_IRQHandler // TMR1 Update - .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation - .word TMR1_CC_IRQHandler // TMR1 Capture Compare - .word TMR2_IRQHandler // TMR2 - .word TMR3_IRQHandler // TMR3 - .word TMR4_IRQHandler // TMR4 - .word I2C1_EV_IRQHandler // I2C1 Event - .word I2C1_ER_IRQHandler // I2C1 Error - .word I2C2_EV_IRQHandler // I2C2 Event - .word I2C2_ER_IRQHandler // I2C2 Error - .word SPI1_IRQHandler // SPI1 - .word SPI2_IRQHandler // SPI2 - .word USART1_IRQHandler // USART1 - .word USART2_IRQHandler // USART2 - .word USART3_IRQHandler // USART3 - .word EINT15_10_IRQHandler // EINT Line 15..10 - .word RTCAlarm_IRQHandler // RTC Alarm through EINT Line - .word USBDWakeUp_IRQHandler // USBD Wakeup from suspend - .word TMR8_BRK_IRQHandler // TMR8 Break - .word TMR8_UP_IRQHandler // TMR8 Update - .word TMR8_TRG_COM_IRQHandler // TMR8 Trigger and Commutation - .word TMR8_CC_IRQHandler // TMR8 Capture Compare - .word ADC3_IRQHandler // ADC3 - .word EMMC_IRQHandler // EMMC - .word SDIO_IRQHandler // SDIO - .word TMR5_IRQHandler // TMR5 - .word SPI3_IRQHandler // SPI3 - .word UART4_IRQHandler // UART4 - .word UART5_IRQHandler // UART5 - .word TMR6_IRQHandler // TMR6 - .word TMR7_IRQHandler // TMR7 - .word DMA2_Channel1_IRQHandler // DMA2 Channel1 - .word DMA2_Channel2_IRQHandler // DMA2 Channel2 - .word DMA2_Channel3_IRQHandler // DMA2 Channel3 - .word DMA2_Channel4_5_IRQHandler // DMA2 Channel4 & Channel5 - .word 0 // Reserved - .word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX - .word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0 - .word CAN2_RX1_IRQHandler // CAN2 RX1 - .word CAN2_SCE_IRQHandler // CAN2 SCE - - .size g_pfnVectors, .-g_pfnVectors - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +// Reset handler routine Reset_Handler: - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_edata - subs r3, r2 - ble fill_bss_start + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 -loop_copy_data: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt loop_copy_data +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 -fill_bss_start: - ldr r1, =__bss_start - ldr r2, =__bss_end - movs r0, 0 - subs r2, r1 - ble startup_enter +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 -loop_fill_bss: - subs r2, #4 - str r0, [r1, r2] - bgt loop_fill_bss +L_loop2: + str r3, [r2] + adds r2, r2, #4 -startup_enter: - bl SystemInit - bl entry +L_loop1: + cmp r2, r4 + bcc L_loop2 - /* Exception Handlers */ - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler + bl SystemInit + bl __libc_init_array + bl main + bx lr +.size Reset_Handler, .-Reset_Handler - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - b . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - b . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - /* IQR Handler */ - .section .text.Default_Handler,"ax",%progbits - .type Default_Handler, %function +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits Default_Handler: - b . - .size Default_Handler, . - Default_Handler +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm +// The minimal vector table for a Cortex M3. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors + +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + + .word _end_stack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + .word WWDT_IRQHandler // Window Watchdog + .word PVD_IRQHandler // PVD through EINT Line detect + .word TAMPER_IRQHandler // Tamper + .word RTC_IRQHandler // RTC + .word FLASH_IRQHandler // Flash + .word RCM_IRQHandler // RCM + .word EINT0_IRQHandler // EINT Line 0 + .word EINT1_IRQHandler // EINT Line 1 + .word EINT2_IRQHandler // EINT Line 2 + .word EINT3_IRQHandler // EINT Line 3 + .word EINT4_IRQHandler // EINT Line 4 + .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 + .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 + .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 + .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 + .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 + .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 + .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 + .word ADC1_2_IRQHandler // ADC1 & ADC2 + .word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX + .word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 + .word CAN1_RX1_IRQHandler // CAN1 RX1 + .word CAN1_SCE_IRQHandler // CAN1 SCE + .word EINT9_5_IRQHandler // EINT Line 9..5 + .word TMR1_BRK_IRQHandler // TMR1 Break + .word TMR1_UP_IRQHandler // TMR1 Update + .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR4_IRQHandler // TMR4 + .word I2C1_EV_IRQHandler // I2C1 Event + .word I2C1_ER_IRQHandler // I2C1 Error + .word I2C2_EV_IRQHandler // I2C2 Event + .word I2C2_ER_IRQHandler // I2C2 Error + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_IRQHandler // USART3 + .word EINT15_10_IRQHandler // EINT Line 15..10 + .word RTC_Alarm_IRQHandler // RTC Alarm through EINT Line + .word USBDWakeUp_IRQHandler // USBD Wakeup from suspend + .word TMR8_BRK_IRQHandler // TMR8 Break + .word TMR8_UP_IRQHandler // TMR8 Update + .word TMR8_TRG_COM_IRQHandler // TMR8 Trigger and Commutation + .word TMR8_CC_IRQHandler // TMR8 Capture Compare + .word ADC3_IRQHandler // ADC3 + .word FSMC_IRQHandler // EMMC + .word SDIO_IRQHandler // SDIO + .word TMR5_IRQHandler // TMR5 + .word SPI3_IRQHandler // SPI3 + .word UART4_IRQHandler // UART4 + .word UART5_IRQHandler // UART5 + .word TMR6_IRQHandler // TMR6 + .word TMR7_IRQHandler // TMR7 + .word DMA2_Channel1_IRQHandler // DMA2 Channel1 + .word DMA2_Channel2_IRQHandler // DMA2 Channel2 + .word DMA2_Channel3_IRQHandler // DMA2 Channel3 + .word DMA2_Channel4_5_IRQHandler // DMA2 Channel4 & Channel5 + .word 0 // Reserved + .word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX + .word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0 + .word CAN2_RX1_IRQHandler // CAN2 RX1 + .word CAN2_SCE_IRQHandler // CAN2 SCE + +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_IRQHandler + .thumb_set RCM_IRQHandler,Default_Handler + + .weak EINT0_IRQHandler + .thumb_set EINT0_IRQHandler,Default_Handler + + .weak EINT1_IRQHandler + .thumb_set EINT1_IRQHandler,Default_Handler + + .weak EINT2_IRQHandler + .thumb_set EINT2_IRQHandler,Default_Handler + + .weak EINT3_IRQHandler + .thumb_set EINT3_IRQHandler,Default_Handler + + .weak EINT4_IRQHandler + .thumb_set EINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBD1_HP_CAN1_TX_IRQHandler + .thumb_set USBD1_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USBD1_LP_CAN1_RX0_IRQHandler + .thumb_set USBD1_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EINT9_5_IRQHandler + .thumb_set EINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_IRQHandler + .thumb_set TMR1_BRK_IRQHandler,Default_Handler + + .weak TMR1_UP_IRQHandler + .thumb_set TMR1_UP_IRQHandler,Default_Handler + + .weak TMR1_TRG_COM_IRQHandler + .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR4_IRQHandler + .thumb_set TMR4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EINT15_10_IRQHandler + .thumb_set EINT15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBDWakeUp_IRQHandler + .thumb_set USBDWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_IRQHandler + .thumb_set TMR8_BRK_IRQHandler,Default_Handler + + .weak TMR8_UP_IRQHandler + .thumb_set TMR8_UP_IRQHandler,Default_Handler + + .weak TMR8_TRG_COM_IRQHandler + .thumb_set TMR8_TRG_COM_IRQHandler,Default_Handler + + .weak TMR8_CC_IRQHandler + .thumb_set TMR8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TMR5_IRQHandler + .thumb_set TMR5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_IRQHandler + .thumb_set TMR6_IRQHandler,Default_Handler + + .weak TMR7_IRQHandler + .thumb_set TMR7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak USBD2_HP_CAN2_TX_IRQHandler + .thumb_set USBD2_HP_CAN2_TX_IRQHandler,Default_Handler + + .weak USBD2_LP_CAN2_RX0_IRQHandler + .thumb_set USBD2_LP_CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler - IRQ WWDT_IRQHandler - IRQ PVD_IRQHandler - IRQ TAMPER_IRQHandler - IRQ RTC_IRQHandler - IRQ FLASH_IRQHandler - IRQ RCM_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ EINT4_IRQHandler - IRQ DMA1_Channel1_IRQHandler - IRQ DMA1_Channel2_IRQHandler - IRQ DMA1_Channel3_IRQHandler - IRQ DMA1_Channel4_IRQHandler - IRQ DMA1_Channel5_IRQHandler - IRQ DMA1_Channel6_IRQHandler - IRQ DMA1_Channel7_IRQHandler - IRQ ADC1_2_IRQHandler - IRQ USBD1_HP_CAN1_TX_IRQHandler - IRQ USBD1_LP_CAN1_RX0_IRQHandler - IRQ CAN1_RX1_IRQHandler - IRQ CAN1_SCE_IRQHandler - IRQ EINT9_5_IRQHandler - IRQ TMR1_BRK_IRQHandler - IRQ TMR1_UP_IRQHandler - IRQ TMR1_TRG_COM_IRQHandler - IRQ TMR1_CC_IRQHandler - IRQ TMR2_IRQHandler - IRQ TMR3_IRQHandler - IRQ TMR4_IRQHandler - IRQ I2C1_EV_IRQHandler - IRQ I2C1_ER_IRQHandler - IRQ I2C2_EV_IRQHandler - IRQ I2C2_ER_IRQHandler - IRQ SPI1_IRQHandler - IRQ SPI2_IRQHandler - IRQ USART1_IRQHandler - IRQ USART2_IRQHandler - IRQ USART3_IRQHandler - IRQ EINT15_10_IRQHandler - IRQ RTCAlarm_IRQHandler - IRQ USBDWakeUp_IRQHandler - IRQ TMR8_BRK_IRQHandler - IRQ TMR8_UP_IRQHandler - IRQ TMR8_TRG_COM_IRQHandler - IRQ TMR8_CC_IRQHandler - IRQ ADC3_IRQHandler - IRQ EMMC_IRQHandler - IRQ SDIO_IRQHandler - IRQ TMR5_IRQHandler - IRQ SPI3_IRQHandler - IRQ UART4_IRQHandler - IRQ UART5_IRQHandler - IRQ TMR6_IRQHandler - IRQ TMR7_IRQHandler - IRQ DMA2_Channel1_IRQHandler - IRQ DMA2_Channel2_IRQHandler - IRQ DMA2_Channel3_IRQHandler - IRQ DMA2_Channel4_5_IRQHandler - IRQ USBD2_HP_CAN2_TX_IRQHandler - IRQ USBD2_LP_CAN2_RX0_IRQHandler - IRQ CAN2_RX1_IRQHandler - IRQ CAN2_SCE_IRQHandler diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s index 3bddc6ee7d..9bcbdf0269 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s @@ -1,246 +1,327 @@ -;/*! -; * @file startup_apm32f10x_hd.s -; * -; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd -; * -; * @version V1.0.0 -; * -; * @date 2022-01-05 -; * -; * @attention -; * -; * Copyright (C) 2020-2022 Geehy Semiconductor -; * -; * You may not use this file except in compliance with the -; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). -; * -; * The program is only for reference, which is distributed in the hope -; * that it will be usefull and instructional for customers to develop -; * their software. Unless required by applicable law or agreed to in -; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT -; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. -; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions -; * and limitations under the License. -; */ +/*! + * @file startup_apm32f103_hd.S + * + * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd + * + * @version V1.0.1 + * + * @date 2022-12-01 + * + * @attention + * + * Copyright (C) 2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be useful and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ -.syntax unified -.cpu cortex-m3 -.fpu softvfp -.thumb + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb -.global g_pfnVectors -.global Default_Handler +.global g_apm32_Vectors +.global Default_Handler - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object +.word _start_address_init_data +.word _start_address_data +.word _end_address_data +.word _start_address_bss +.word _end_address_bss -g_pfnVectors: - .word _estack // Top of Stack - .word Reset_Handler // Reset Handler - .word NMI_Handler // NMI Handler - .word HardFault_Handler // Hard Fault Handler - .word MemManage_Handler // MPU Fault Handler - .word BusFault_Handler // Bus Fault Handler - .word UsageFault_Handler // Usage Fault Handler - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word SVC_Handler // SVCall Handler - .word DebugMon_Handler // Debug Monitor Handler - .word 0 // Reserved - .word PendSV_Handler // PendSV Handler - .word SysTick_Handler // SysTick Handler - - // external interrupts handler - .word WWDT_IRQHandler // Window Watchdog - .word PVD_IRQHandler // PVD through EINT Line detect - .word TAMPER_IRQHandler // Tamper - .word RTC_IRQHandler // RTC - .word FLASH_IRQHandler // Flash - .word RCM_IRQHandler // RCM - .word EINT0_IRQHandler // EINT Line 0 - .word EINT1_IRQHandler // EINT Line 1 - .word EINT2_IRQHandler // EINT Line 2 - .word EINT3_IRQHandler // EINT Line 3 - .word EINT4_IRQHandler // EINT Line 4 - .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 - .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 - .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 - .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 - .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 - .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 - .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 - .word ADC1_2_IRQHandler // ADC1_2 - .word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX - .word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 - .word CAN1_RX1_IRQHandler // CAN1 RX1 - .word CAN1_SCE_IRQHandler // CAN1 SCE - .word EINT9_5_IRQHandler // EINT Line 9..5 - .word TMR1_BRK_IRQHandler // TMR1 Break - .word TMR1_UP_IRQHandler // TMR1 Update - .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation - .word TMR1_CC_IRQHandler // TMR1 Capture Compare - .word TMR2_IRQHandler // TMR2 - .word TMR3_IRQHandler // TMR3 - .word TMR4_IRQHandler // TMR4 - .word I2C1_EV_IRQHandler // I2C1 Event - .word I2C1_ER_IRQHandler // I2C1 Error - .word I2C2_EV_IRQHandler // I2C2 Event - .word I2C2_ER_IRQHandler // I2C2 Error - .word SPI1_IRQHandler // SPI1 - .word SPI2_IRQHandler // SPI2 - .word USART1_IRQHandler // USART1 - .word USART2_IRQHandler // USART2 - .word USART3_IRQHandler // USART3 - .word EINT15_10_IRQHandler // EINT Line 15..10 - .word RTCAlarm_IRQHandler // RTC Alarm through EINT Line - .word USBDWakeUp_IRQHandler // USBD Wakeup from suspend - .word FPU_IRQHandler // FPU - .word QSPI_IRQHandler // QSPI - .word USBD2_HP_IRQHandler // USBD2 High Priority - .word USBD2_LP_IRQHandler // USBD2 Low Priority - - .size g_pfnVectors, .-g_pfnVectors - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +// Reset handler routine Reset_Handler: - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_edata - subs r3, r2 - ble fill_bss_start + ldr r0, =_start_address_data + ldr r1, =_end_address_data + ldr r2, =_start_address_init_data + movs r3, #0 + b L_loop0_0 -loop_copy_data: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt loop_copy_data +L_loop0: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 -fill_bss_start: - ldr r1, =__bss_start - ldr r2, =__bss_end - movs r0, 0 - subs r2, r1 - ble startup_enter +L_loop0_0: + adds r4, r0, r3 + cmp r4, r1 + bcc L_loop0 + + ldr r2, =_start_address_bss + ldr r4, =_end_address_bss + movs r3, #0 + b L_loop1 -loop_fill_bss: - subs r2, #4 - str r0, [r1, r2] - bgt loop_fill_bss +L_loop2: + str r3, [r2] + adds r2, r2, #4 -startup_enter: - bl SystemInit - bl entry +L_loop1: + cmp r2, r4 + bcc L_loop2 - /* Exception Handlers */ - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler + bl SystemInit + bl __libc_init_array + bl main + bx lr +.size Reset_Handler, .-Reset_Handler - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - b . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - b . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - /* IQR Handler */ - .section .text.Default_Handler,"ax",%progbits - .type Default_Handler, %function +// This is the code that gets called when the processor receives an unexpected interrupt. + .section .text.Default_Handler,"ax",%progbits Default_Handler: - b . - .size Default_Handler, . - Default_Handler +L_Loop_infinite: + b L_Loop_infinite + .size Default_Handler, .-Default_Handler - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm +// The minimal vector table for a Cortex M3. + .section .apm32_isr_vector,"a",%progbits + .type g_apm32_Vectors, %object + .size g_apm32_Vectors, .-g_apm32_Vectors - IRQ WWDT_IRQHandler - IRQ PVD_IRQHandler - IRQ TAMPER_IRQHandler - IRQ RTC_IRQHandler - IRQ FLASH_IRQHandler - IRQ RCM_IRQHandler - IRQ EINT0_IRQHandler - IRQ EINT1_IRQHandler - IRQ EINT2_IRQHandler - IRQ EINT3_IRQHandler - IRQ EINT4_IRQHandler - IRQ DMA1_Channel1_IRQHandler - IRQ DMA1_Channel2_IRQHandler - IRQ DMA1_Channel3_IRQHandler - IRQ DMA1_Channel4_IRQHandler - IRQ DMA1_Channel5_IRQHandler - IRQ DMA1_Channel6_IRQHandler - IRQ DMA1_Channel7_IRQHandler - IRQ ADC1_2_IRQHandler - IRQ USBD1_HP_CAN1_TX_IRQHandler - IRQ USBD1_LP_CAN1_RX0_IRQHandler - IRQ CAN1_RX1_IRQHandler - IRQ CAN1_SCE_IRQHandler - IRQ EINT9_5_IRQHandler - IRQ TMR1_BRK_IRQHandler - IRQ TMR1_UP_IRQHandler - IRQ TMR1_TRG_COM_IRQHandler - IRQ TMR1_CC_IRQHandler - IRQ TMR2_IRQHandler - IRQ TMR3_IRQHandler - IRQ TMR4_IRQHandler - IRQ I2C1_EV_IRQHandler - IRQ I2C1_ER_IRQHandler - IRQ I2C2_EV_IRQHandler - IRQ I2C2_ER_IRQHandler - IRQ SPI1_IRQHandler - IRQ SPI2_IRQHandler - IRQ USART1_IRQHandler - IRQ USART2_IRQHandler - IRQ USART3_IRQHandler - IRQ EINT15_10_IRQHandler - IRQ RTCAlarm_IRQHandler - IRQ USBDWakeUp_IRQHandler - IRQ FPU_IRQHandler - IRQ QSPI_IRQHandler - IRQ USBD2_HP_IRQHandler - IRQ USBD2_LP_IRQHandler +// Vector Table Mapped to Address 0 at Reset +g_apm32_Vectors: + + .word _end_stack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + .word WWDT_IRQHandler // Window Watchdog + .word PVD_IRQHandler // PVD through EINT Line detect + .word TAMPER_IRQHandler // Tamper + .word RTC_IRQHandler // RTC + .word FLASH_IRQHandler // Flash + .word RCM_IRQHandler // RCM + .word EINT0_IRQHandler // EINT Line 0 + .word EINT1_IRQHandler // EINT Line 1 + .word EINT2_IRQHandler // EINT Line 2 + .word EINT3_IRQHandler // EINT Line 3 + .word EINT4_IRQHandler // EINT Line 4 + .word DMA1_Channel1_IRQHandler // DMA1 Channel 1 + .word DMA1_Channel2_IRQHandler // DMA1 Channel 2 + .word DMA1_Channel3_IRQHandler // DMA1 Channel 3 + .word DMA1_Channel4_IRQHandler // DMA1 Channel 4 + .word DMA1_Channel5_IRQHandler // DMA1 Channel 5 + .word DMA1_Channel6_IRQHandler // DMA1 Channel 6 + .word DMA1_Channel7_IRQHandler // DMA1 Channel 7 + .word ADC1_2_IRQHandler // ADC1_2 + .word USBD1_HP_CAN1_TX_IRQHandler // USBD1 High Priority or CAN1 TX + .word USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low Priority or CAN1 RX0 + .word CAN1_RX1_IRQHandler // CAN1 RX1 + .word CAN1_SCE_IRQHandler // CAN1 SCE + .word EINT9_5_IRQHandler // EINT Line 9..5 + .word TMR1_BRK_IRQHandler // TMR1 Break + .word TMR1_UP_IRQHandler // TMR1 Update + .word TMR1_TRG_COM_IRQHandler // TMR1 Trigger and Commutation + .word TMR1_CC_IRQHandler // TMR1 Capture Compare + .word TMR2_IRQHandler // TMR2 + .word TMR3_IRQHandler // TMR3 + .word TMR4_IRQHandler // TMR4 + .word I2C1_EV_IRQHandler // I2C1 Event + .word I2C1_ER_IRQHandler // I2C1 Error + .word I2C2_EV_IRQHandler // I2C2 Event + .word I2C2_ER_IRQHandler // I2C2 Error + .word SPI1_IRQHandler // SPI1 + .word SPI2_IRQHandler // SPI2 + .word USART1_IRQHandler // USART1 + .word USART2_IRQHandler // USART2 + .word USART3_IRQHandler // USART3 + .word EINT15_10_IRQHandler // EINT Line 15..10 + .word RTC_Alarm_IRQHandler // RTC Alarm through EINT Line + .word USBDWakeUp_IRQHandler // USBD Wakeup from suspend + .word FPU_IRQHandler // FPU + .word QSPI_IRQHandler // QSPI + .word USBD2_HP_IRQHandler // USBD2 High Priority + .word USBD2_LP_IRQHandler // USBD2 Low Priority +// Default exception/interrupt handler + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCM_IRQHandler + .thumb_set RCM_IRQHandler,Default_Handler + + .weak EINT0_IRQHandler + .thumb_set EINT0_IRQHandler,Default_Handler + + .weak EINT1_IRQHandler + .thumb_set EINT1_IRQHandler,Default_Handler + + .weak EINT2_IRQHandler + .thumb_set EINT2_IRQHandler,Default_Handler + + .weak EINT3_IRQHandler + .thumb_set EINT3_IRQHandler,Default_Handler + + .weak EINT4_IRQHandler + .thumb_set EINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBD1_HP_CAN1_TX_IRQHandler + .thumb_set USBD1_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USBD1_LP_CAN1_RX0_IRQHandler + .thumb_set USBD1_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EINT9_5_IRQHandler + .thumb_set EINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_IRQHandler + .thumb_set TMR1_BRK_IRQHandler,Default_Handler + + .weak TMR1_UP_IRQHandler + .thumb_set TMR1_UP_IRQHandler,Default_Handler + + .weak TMR1_TRG_COM_IRQHandler + .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler + + .weak TMR1_CC_IRQHandler + .thumb_set TMR1_CC_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak TMR4_IRQHandler + .thumb_set TMR4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EINT15_10_IRQHandler + .thumb_set EINT15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBDWakeUp_IRQHandler + .thumb_set USBDWakeUp_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak QSPI_IRQHandler + .thumb_set QSPI_IRQHandler,Default_Handler + + .weak USBD2_HP_IRQHandler + .thumb_set USBD2_HP_IRQHandler,Default_Handler + + .weak USBD2_LP_IRQHandler + .thumb_set USBD2_LP_IRQHandler,Default_Handler diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_cl.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_cl.s new file mode 100644 index 0000000000..86ee43329b --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_cl.s @@ -0,0 +1,492 @@ +;/*! +; * @file startup_apm32f10x_cl.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103 +; * +; * @version V1.0.0 +; * +; * @date 2022-07-25 +; * +; * @attention +; * +; * Copyright (C) 2020-2022 Geehy Semiconductor +; * +; * You may not use this file except in compliance with the +; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). +; * +; * The program is only for reference, which is distributed in the hope +; * that it will be useful and instructional for customers to develop +; * their software. Unless required by applicable law or agreed to in +; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT +; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. +; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions +; * and limitations under the License. +; */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCM_IRQHandler ; RCM + DCD EINT0_IRQHandler ; EINT Line 0 + DCD EINT1_IRQHandler ; EINT Line 1 + DCD EINT2_IRQHandler ; EINT Line 2 + DCD EINT3_IRQHandler ; EINT Line 3 + DCD EINT4_IRQHandler ; EINT Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EINT9_5_IRQHandler ; EINT Line 9..5 + DCD TMR1_BRK_IRQHandler ; TMR1 Break + DCD TMR1_UP_IRQHandler ; TMR1 Update + DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR4_IRQHandler ; TMR4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EINT15_10_IRQHandler ; EINT Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line + DCD OTG_FS_WKUP_IRQHandler ; USBD Wakeup from suspend + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TMR5_IRQHandler ; TMR5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; ETH + DCD ETH_WKUP_IRQHandler ; ETH Wake up + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; OTG FS +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCM_IRQHandler + B RCM_IRQHandler + + PUBWEAK EINT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT0_IRQHandler + B EINT0_IRQHandler + + PUBWEAK EINT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT1_IRQHandler + B EINT1_IRQHandler + + PUBWEAK EINT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT2_IRQHandler + B EINT2_IRQHandler + + PUBWEAK EINT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT3_IRQHandler + B EINT3_IRQHandler + + PUBWEAK EINT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT4_IRQHandler + B EINT4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EINT9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT9_5_IRQHandler + B EINT9_5_IRQHandler + + PUBWEAK TMR1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_BRK_IRQHandler + B TMR1_BRK_IRQHandler + + PUBWEAK TMR1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_UP_IRQHandler + B TMR1_UP_IRQHandler + + PUBWEAK TMR1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_TRG_COM_IRQHandler + B TMR1_TRG_COM_IRQHandler + + PUBWEAK TMR1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_CC_IRQHandler + B TMR1_CC_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR4_IRQHandler + B TMR4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EINT15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EINT15_10_IRQHandler + B EINT15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TMR5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR5_IRQHandler + B TMR5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TMR6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR6_IRQHandler + B TMR6_IRQHandler + + PUBWEAK TMR7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR7_IRQHandler + B TMR7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + END + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s index 4c0a8fa9b0..a038553107 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s @@ -5,7 +5,7 @@ ; * ; * @version V1.0.0 ; * -; * @date 2022-01-05 +; * @date 2022-07-25 ; * ; * @attention ; * @@ -15,7 +15,7 @@ ; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). ; * ; * The program is only for reference, which is distributed in the hope -; * that it will be usefull and instructional for customers to develop +; * that it will be useful and instructional for customers to develop ; * their software. Unless required by applicable law or agreed to in ; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT ; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s index 8028032f16..5d18204679 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s @@ -5,7 +5,7 @@ ; * ; * @version V1.0.0 ; * -; * @date 2022-01-05 +; * @date 2022-07-25 ; * ; * @attention ; * @@ -15,7 +15,7 @@ ; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). ; * ; * The program is only for reference, which is distributed in the hope -; * that it will be usefull and instructional for customers to develop +; * that it will be useful and instructional for customers to develop ; * their software. Unless required by applicable law or agreed to in ; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT ; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c index 2fae0cb90a..671e6710c0 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c @@ -3,9 +3,9 @@ * * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File * - * @version V1.0.2 + * @version V1.0.4 * - * @date 2022-01-05 + * @date 2022-12-01 * * @attention * @@ -15,7 +15,7 @@ * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). * * The program is only for reference, which is distributed in the hope - * that it will be usefull and instructional for customers to develop + * that it will be useful and instructional for customers to develop * their software. Unless required by applicable law or agreed to in * writing, the program is distributed on an "AS IS" BASIS, WITHOUT * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,12 +23,21 @@ * and limitations under the License. */ +/*Includes*/ #include "apm32f10x.h" -/***************************************************************** - * If SYSCLK source is PLL,SystemCoreClock will contain the * - * HSE_VALUE or HSI_VALUE multiplied/divided by the PLL factors. * -******************************************************************/ +/** @addtogroup CMSIS + @{ +*/ + +/** @addtogroup APM32F10x_System + * @brief APM32F10x system configuration + @{ +*/ + +/** @defgroup System_Macros + @{ +*/ //#define SYSTEM_CLOCK_HSE HSE_VALUE //#define SYSTEM_CLOCK_24MHz (24000000) @@ -38,10 +47,15 @@ #define SYSTEM_CLOCK_72MHz (72000000) //#define SYSTEM_CLOCK_96MHz (96000000) - -/** #define VECT_TAB_SRAM */ +/* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 +/**@} end of group System_Macros*/ + +/** @defgroup System_Variables + @{ +*/ + #ifdef SYSTEM_CLOCK_HSE uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE; #elif defined SYSTEM_CLOCK_24MHz @@ -58,6 +72,11 @@ uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz; #endif +/**@} end of group System_Variables */ + +/** @defgroup System_Functions + @{ +*/ static void SystemClockConfig(void); @@ -87,18 +106,34 @@ static void SystemClockConfig(void); */ void SystemInit(void) { - /** Set HSIEN bit */ + /* Set HSIEN bit */ RCM->CTRL_B.HSIEN = BIT_SET; - /** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ - RCM->CFG &= (uint32_t)0xF8FF0000; - /** Reset HSEEN, CSSEN and PLLEN bits */ - RCM->CTRL &= (uint32_t)0xFEF6FFFF; - /** Reset HSEBCFG bit */ + +#ifdef APM32F10X_CL + RCM->CFG &= (uint32_t) 0xF0FF0000; +#else + /* Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + RCM->CFG &= (uint32_t) 0xF8FF0000; +#endif /* APM32F10X_CL */ + + /* Reset HSEEN, CSSEN and PLLEN bits */ + RCM->CTRL &= (uint32_t) 0xFEF6FFFF; + /* Reset HSEBCFG bit */ RCM->CTRL_B.HSEBCFG = BIT_RESET; - /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ - RCM->CFG &= (uint32_t)0xFF80FFFF; - /** Disable all interrupts and clear pending bits */ + /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ + RCM->CFG &= (uint32_t) 0xFF80FFFF; + +#ifdef APM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCM->CTRL &= (uint32_t) 0xEBFFFFFF; + /* Disable all interrupts and clear pending bits */ + RCM->INT = 0x00FF0000; + /* Reset CFG2 register */ + RCM->CFG2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ RCM->INT = 0x009F0000; +#endif /* APM32F10X_CL */ SystemClockConfig(); @@ -120,53 +155,98 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t sysClock, pllMull, pllSource, Prescaler; - uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +#ifdef APM32F10X_CL + uint32_t sysClock, pllMull, pllSource, pll2Mull, pllPsc1, pllPsc2; +#else + uint32_t sysClock, pllMull, pllSource; +#endif - sysClock = RCM->CFG_B.SCLKSELSTS; + /* get sys clock */ + sysClock = RCM->CFG_B.SCLKSEL; switch (sysClock) { - /** sys clock is HSI */ - case 0: - SystemCoreClock = HSI_VALUE; - break; + /* sys clock is HSI */ + case 0: + sysClock = HSI_VALUE; + break; - /** sys clock is HSE */ - case 1: - SystemCoreClock = HSE_VALUE; - break; + /* sys clock is HSE */ + case 1: + sysClock = HSE_VALUE; + break; - /** sys clock is PLL */ - case 2: - pllMull = RCM->CFG_B.PLLMULCFG + 2; - pllSource = RCM->CFG_B.PLLSRCSEL; + /* sys clock is PLL */ + case 2: +#ifdef APM32F10X_CL + /* NOTE : PLL is the same as PLL1 */ + pllSource = RCM->CFG_B.PLL1SRCSEL; - /** PLL entry clock source is HSE */ - if (pllSource == BIT_SET) - { - SystemCoreClock = HSE_VALUE * pllMull; - - /** HSE clock divided by 2 */ - if (pllSource == RCM->CFG_B.PLLHSEPSC) + /* PLL entry clock source is HSE */ + if (pllSource) { - SystemCoreClock >>= 1; - } - } - /** PLL entry clock source is HSI/2 */ - else - { - SystemCoreClock = (HSI_VALUE >> 1) * pllMull; - } - break; + /* PLLPSC1 prescaler factor */ + pllPsc1 = (RCM->CFG2_B.PLLPSC1 + 1); - default: - SystemCoreClock = HSI_VALUE; - break; + /* PLL entry clock source is PLL2 */ + if (RCM->CFG2_B.PLLPSC1SRC) + { + pll2Mull = (RCM->CFG2_B.PLL2MUL != 15) ? (RCM->CFG2_B.PLL2MUL + 2) : 20; + pllPsc2 = RCM->CFG2_B.PLLPSC2 + 1; + + pllSource = ((HSE_VALUE / pllPsc2) * pll2Mull) / pllPsc1; + } + /* PLL entry clock source is HSE */ + else + { + pllSource = HSE_VALUE / pllPsc1; + } + } + /* PLL entry clock source is HSI/2 */ + else + { + pllSource = HSI_VALUE >> 1; + } + + pllMull = RCM->CFG_B.PLL1MULCFG; + if (pllMull == 13) + { + /* For 6.5 multiplication factor */ + sysClock = pllSource * pllMull / 2; + } + else + { + sysClock = pllSource * (pllMull + 2); + } +#else + pllMull = RCM->CFG_B.PLL1MULCFG + 2; + pllSource = RCM->CFG_B.PLL1SRCSEL; + + /* PLL entry clock source is HSE */ + if (pllSource == BIT_SET) + { + sysClock = HSE_VALUE * pllMull; + + /* HSE clock divided by 2 */ + if (pllSource == RCM->CFG_B.PLLHSEPSC) + { + sysClock >>= 1; + } + } + /* PLL entry clock source is HSI/2 */ + else + { + sysClock = (HSI_VALUE >> 1) * pllMull; + } +#endif + break; + + default: + sysClock = HSI_VALUE; + break; } - Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC]; - SystemCoreClock >>= Prescaler; + SystemCoreClock = sysClock; } /*! @@ -221,27 +301,42 @@ static void SystemClockHSE(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 0 wait state */ - FMC->CTRL1_B.WS = 0; - /** HCLK = SYSCLK */ +#ifdef APM32F10X_CL + + if (HSE_VALUE <= 24000000) + { + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; + } + else + { + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + } + +#else + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; +#endif /* APM32F10X_CL */ + + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK */ + /* PCLK1 = HCLK */ RCM->CFG_B.APB1PSC = 0; - /** Select HSE as system clock source */ + /* Select HSE as system clock source */ RCM->CFG_B.SCLKSEL = 1; - /** Wait till HSE is used as system clock source */ + /* Wait till HSE is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x01); } } - #elif defined SYSTEM_CLOCK_24MHz /*! * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers @@ -267,31 +362,53 @@ static void SystemClock24M(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 0 wait state */ + /* Flash 0 wait state */ FMC->CTRL1_B.WS = 0; - /** HCLK = SYSCLK */ + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK */ + /* PCLK1 = HCLK */ RCM->CFG_B.APB1PSC = 0; - /** PLL: (HSE / 2) * 6 */ - RCM->CFG_B.PLLSRCSEL = 1; +#ifdef APM32F10X_CL + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */ + /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */ + + RCM->CFG2_B.PLLPSC2 = 4; + RCM->CFG2_B.PLL2MUL = 0x06; + + RCM->CFG2_B.PLLPSC1SRC = 1; + RCM->CFG2_B.PLLPSC1 = 9; + + /* Enable PLL2 */ + RCM->CTRL_B.PLL2EN = 1; + /* Wait till PLL2 is ready */ + while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET); + + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 4; +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 6 = 24 MHz */ + /* PLL: (HSE / 2) * 6 */ + RCM->CFG_B.PLL1SRCSEL = 1; RCM->CFG_B.PLLHSEPSC = 1; - RCM->CFG_B.PLLMULCFG = 4; + RCM->CFG_B.PLL1MULCFG = 4; +#endif /* APM32F10X_CL */ - /** Enable PLL */ - RCM->CTRL_B.PLLEN = 1; - /** Wait PLL Ready */ - while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + /* Enable PLL */ + RCM->CTRL_B.PLL1EN = 1; - /** Select PLL as system clock source */ + /* Wait PLL Ready */ + while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ RCM->CFG_B.SCLKSEL = 2; - /** Wait till PLL is used as system clock source */ + + /* Wait till PLL is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -321,31 +438,53 @@ static void SystemClock36M(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 1 wait state */ + /* Flash 1 wait state */ FMC->CTRL1_B.WS = 1; - /** HCLK = SYSCLK */ + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK */ + /* PCLK1 = HCLK */ RCM->CFG_B.APB1PSC = 0; - /** PLL: (HSE / 2) * 9 */ - RCM->CFG_B.PLLSRCSEL = 1; +#ifdef APM32F10X_CL + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */ + /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */ + + RCM->CFG2_B.PLLPSC2 = 4; + RCM->CFG2_B.PLL2MUL = 0x06; + + RCM->CFG2_B.PLLPSC1SRC = 1; + RCM->CFG2_B.PLLPSC1 = 9; + + /* Enable PLL2 */ + RCM->CTRL_B.PLL2EN = 1; + /* Wait till PLL2 is ready */ + while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET); + + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 7; +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + /* PLL: (HSE / 2) * 9 */ + RCM->CFG_B.PLL1SRCSEL = 1; RCM->CFG_B.PLLHSEPSC = 1; - RCM->CFG_B.PLLMULCFG = 7; + RCM->CFG_B.PLL1MULCFG = 7; +#endif - /** Enable PLL */ - RCM->CTRL_B.PLLEN = 1; - /** Wait PLL Ready */ - while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + /* Enable PLL */ + RCM->CTRL_B.PLL1EN = 1; - /** Select PLL as system clock source */ + /* Wait PLL Ready */ + while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ RCM->CFG_B.SCLKSEL = 2; - /** Wait till PLL is used as system clock source */ + + /* Wait till PLL is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -375,30 +514,51 @@ static void SystemClock48M(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 1 wait state */ + /* Flash 1 wait state */ FMC->CTRL1_B.WS = 1; - /** HCLK = SYSCLK */ + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK / 2 */ + /* PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; - /** PLL: HSE * 6 */ - RCM->CFG_B.PLLSRCSEL = 1; - RCM->CFG_B.PLLMULCFG = 4; +#ifdef APM32F10X_CL + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */ + /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */ - /** Enable PLL */ - RCM->CTRL_B.PLLEN = 1; - /** Wait PLL Ready */ - while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + RCM->CFG2_B.PLLPSC2 = 4; + RCM->CFG2_B.PLL2MUL = 0x06; - /** Select PLL as system clock source */ + RCM->CFG2_B.PLLPSC1SRC = 1; + RCM->CFG2_B.PLLPSC1 = 0x4; + + /* Enable PLL2 */ + RCM->CTRL_B.PLL2EN = 1; + /* Wait till PLL2 is ready */ + while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET); + + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 4; +#else + /* PLL: HSE * 6 */ + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 4; +#endif + + /* Enable PLL */ + RCM->CTRL_B.PLL1EN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ RCM->CFG_B.SCLKSEL = 2; - /** Wait till PLL is used as system clock source */ + + /* Wait till PLL is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -428,30 +588,51 @@ static void SystemClock56M(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 2 wait state */ + /* Flash 2 wait state */ FMC->CTRL1_B.WS = 2; - /** HCLK = SYSCLK */ + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK / 2 */ + /* PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; - /** PLL: HSE * 7 */ - RCM->CFG_B.PLLSRCSEL = 1; - RCM->CFG_B.PLLMULCFG = 5; +#ifdef APM32F10X_CL + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */ + /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */ - /** Enable PLL */ - RCM->CTRL_B.PLLEN = 1; - /** Wait PLL Ready */ - while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + RCM->CFG2_B.PLLPSC2 = 4; + RCM->CFG2_B.PLL2MUL = 0x06; - /** Select PLL as system clock source */ + RCM->CFG2_B.PLLPSC1SRC = 1; + RCM->CFG2_B.PLLPSC1 = 0x4; + + /* Enable PLL2 */ + RCM->CTRL_B.PLL2EN = 1; + /* Wait till PLL2 is ready */ + while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET); + + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 5; +#else + /* PLL: HSE * 7 */ + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 5; +#endif + + /* Enable PLL */ + RCM->CTRL_B.PLL1EN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ RCM->CFG_B.SCLKSEL = 2; - /** Wait till PLL is used as system clock source */ + + /* Wait till PLL is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x02); } } @@ -481,30 +662,51 @@ static void SystemClock72M(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 2 wait state */ + /* Flash 2 wait state */ FMC->CTRL1_B.WS = 2; - /** HCLK = SYSCLK */ + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK / 2 */ + /* PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; - /** PLL: HSE * 9 */ - RCM->CFG_B.PLLSRCSEL = 1; - RCM->CFG_B.PLLMULCFG = 7; +#ifdef APM32F10X_CL + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */ + /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ - /** Enable PLL */ - RCM->CTRL_B.PLLEN = 1; - /** Wait PLL Ready */ - while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + RCM->CFG2_B.PLLPSC2 = 4; + RCM->CFG2_B.PLL2MUL = 0x06; - /** Select PLL as system clock source */ + RCM->CFG2_B.PLLPSC1SRC = 1; + RCM->CFG2_B.PLLPSC1 = 0x4; + + /* Enable PLL2 */ + RCM->CTRL_B.PLL2EN = 1; + /* Wait till PLL2 is ready */ + while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET); + + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 7; +#else + /* PLL: HSE * 9 */ + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 7; +#endif + + /* Enable PLL */ + RCM->CTRL_B.PLL1EN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ RCM->CFG_B.SCLKSEL = 2; - /** Wait till PLL is used as system clock source */ + + /* Wait till PLL is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x02); } @@ -535,32 +737,56 @@ static void SystemClock96M(void) if (RCM->CTRL_B.HSERDYFLG) { - /** Enable Prefetch Buffer */ + /* Enable Prefetch Buffer */ FMC->CTRL1_B.PBEN = BIT_SET; - /** Flash 3 wait state */ + /* Flash 3 wait state */ FMC->CTRL1_B.WS = 3; - /** HCLK = SYSCLK */ + /* HCLK = SYSCLK */ RCM->CFG_B.AHBPSC = 0X00; - /** PCLK2 = HCLK */ + /* PCLK2 = HCLK */ RCM->CFG_B.APB2PSC = 0; - /** PCLK1 = HCLK / 2 */ + /* PCLK1 = HCLK / 2 */ RCM->CFG_B.APB1PSC = 4; - /** PLL: HSE * 12 */ - RCM->CFG_B.PLLSRCSEL = 1; - RCM->CFG_B.PLLMULCFG = 10; +#ifdef APM32F10X_CL + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz (HSE is 25MHz for APM32F10X_CL) */ + /* PLL configuration: PLLCLK = (PLL2 / 5) * 8 = 96 MHz */ - /** Enable PLL */ - RCM->CTRL_B.PLLEN = 1; - /** Wait PLL Ready */ - while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + RCM->CFG2_B.PLLPSC2 = 4; + RCM->CFG2_B.PLL2MUL = 10; - /** Select PLL as system clock source */ + RCM->CFG2_B.PLLPSC1SRC = 1; + RCM->CFG2_B.PLLPSC1 = 4; + + /* Enable PLL2 */ + RCM->CTRL_B.PLL2EN = 1; + /* Wait till PLL2 is ready */ + while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET); + + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 6; +#else + /* PLL: HSE * 12 */ + RCM->CFG_B.PLL1SRCSEL = 1; + RCM->CFG_B.PLL1MULCFG = 10; +#endif + + /* Enable PLL */ + RCM->CTRL_B.PLL1EN = 1; + + /* Wait PLL Ready */ + while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ RCM->CFG_B.SCLKSEL = 2; - /** Wait till PLL is used as system clock source */ + + /* Wait till PLL is used as system clock source */ while (RCM->CFG_B.SCLKSELSTS != 0x02); } } #endif +/**@} end of group System_Functions */ +/**@} end of group APM32F10x_System */ +/**@} end of group CMSIS */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/SConscript b/bsp/apm32/libraries/APM32F10x_Library/SConscript index a95e30d56a..022b665adc 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/SConscript +++ b/bsp/apm32/libraries/APM32F10x_Library/SConscript @@ -35,9 +35,13 @@ if GetDepend(['RT_USING_WDT']): src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c'] src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c'] +if GetDepend(['BSP_USING_ETH']): + src += ['APM32F10x_ETH_Driver/src/apm32f10x_eth.c'] + path = [cwd + '/Device/Geehy/APM32F10x/Include', cwd + '/APM32F10x_StdPeriphDriver/inc', - cwd + '/CMSIS/Include'] + cwd + '/CMSIS/Include', + cwd + '/APM32F10x_ETH_Driver/inc'] CPPDEFINES = ['USE_STDPERIPH_DRIVER'] group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) diff --git a/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/inc/apm32f4xx_eth.h b/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/inc/apm32f4xx_eth.h new file mode 100644 index 0000000000..628f125e4c --- /dev/null +++ b/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/inc/apm32f4xx_eth.h @@ -0,0 +1,1424 @@ +/*! + * @file apm32f4xx_eth.c + * + * @brief This file provides all the ETH firmware functions + * + * @version V1.0.2 + * + * @date 2022-06-23 + * + * @attention + * + * Copyright (C) 2021-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +/* Define to prevent recursive inclusion */ +#ifndef __APM32F4xx_ETH_H +#define __APM32F4xx_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes */ +#include "apm32f4xx.h" + +/** @addtogroup APM32F4xx_ETHDriver + @{ +*/ + +/** @addtogroup ETH_Driver + @{ +*/ + +/** @defgroup ETH_Enumerations + @{ +*/ + +/** + * @brief ETH AutoNegotiation + */ +typedef enum +{ + ETH_AUTONEGOTIATION_DISABLE, /*!< Disable negotiation */ + ETH_AUTONEGOTIATION_ENABLE /*!< Enable negotiation */ +} ETH_AUTONEGOTIATION_T; + +/** + * @brief ETH Watchdog + */ +typedef enum +{ + ETH_WATCHDOG_ENABLE, /*!< Enable watch dog */ + ETH_WATCHDOG_DISABLE /*!< Disable watch dog */ +} ETH_WATCHDOG_T; + +/** + * @brief ETH Jabber + */ +typedef enum +{ + ETH_JABBER_ENABLE, /*!< Enable jabber */ + ETH_JABBER_DISABLE /*!< Disable jabber */ +} ETH_JABBER_T; + +/** + * @brief ETH Inter Frame Gap + */ +typedef enum +{ + ETH_INTERFRAMEGAP_96BIT = 0x00, /*!< Inter-Frame gap = 96-bit */ + ETH_INTERFRAMEGAP_88BIT = 0x01, /*!< Inter-Frame gap = 88-bit */ + ETH_INTERFRAMEGAP_80BIT = 0x02, /*!< Inter-Frame gap = 80-bit */ + ETH_INTERFRAMEGAP_72BIT = 0x03, /*!< Inter-Frame gap = 72-bit */ + ETH_INTERFRAMEGAP_64BIT = 0x04, /*!< Inter-Frame gap = 64-bit */ + ETH_INTERFRAMEGAP_56BIT = 0x05, /*!< Inter-Frame gap = 56-bit */ + ETH_INTERFRAMEGAP_48BIT = 0x06, /*!< Inter-Frame gap = 48-bit */ + ETH_INTERFRAMEGAP_40BIT = 0x07 /*!< Inter-Frame gap = 40-bit */ +} ETH_INTERFRAMEGAP_T; + +/** + * @brief ETH Carrier Sense + */ +typedef enum +{ + ETH_CARRIERSENCE_ENABLE, /*!< Disable carrier sense during transmission */ + ETH_CARRIERSENCE_DISABLE /*!< Ignore MII CRS signal */ +} ETH_CARRIERSENCE_T; + +/** + * @brief ETH Speed + */ +typedef enum +{ + ETH_SPEED_10M, /*!< 10M speed */ + ETH_SPEED_100M /*!< 100M speed */ +} ETH_SPEED_T; + +/** + * @brief ETH Receive Own + */ +typedef enum +{ + ETH_RECEIVEOWN_ENABLE, /*!< Enable receive own */ + ETH_RECEIVEOWN_DISABLE /*!< Disable receive own */ +} ETH_RECEIVEOWN_T; + +/** + * @brief ETH Loop Back Mode + */ +typedef enum +{ + ETH_LOOPBACKMODE_DISABLE, /*!< Disable loopback mode */ + ETH_LOOPBACKMODE_ENABLE /*!< Enable loopback mode */ +} ETH_LOOPBACKMODE_T; + +/** + * @brief ETH Duplex Mode + */ +typedef enum +{ + ETH_MODE_HALFDUPLEX, /*!< Half-Duplex */ + ETH_MODE_FULLDUPLEX /*!< Full-Duplex */ +} ETH_MODE_T; + +/** + * @brief ETH Checksum Offload + */ +typedef enum +{ + ETH_CHECKSUMOFFLAOD_DISABLE, /*!< Disable IPv4 checksum offload */ + ETH_CHECKSUMOFFLAOD_ENABLE /*!< Enable Ipv4 checksum offload */ +} ETH_CHECKSUMOFFLAOD_T; + +/** + * @brief ETH Retry Transmission + */ +typedef enum +{ + ETH_RETRYTRANSMISSION_ENABLE, /*!< Enable retry */ + ETH_RETRYTRANSMISSION_DISABLE /*!< Disable retry */ +} ETH_RETRYTRANSMISSION_T; + +/** + * @brief ETH Automatic Pad CRC Strip + */ +typedef enum +{ + ETH_AUTOMATICPADCRCSTRIP_DISABLE, /*!< Disable automatic pad or CRC stripping */ + ETH_AUTOMATICPADCRCSTRIP_ENABLE /*!< Enable automatic pad or CRC stripping */ +} ETH_AUTOMATICPADCRCSTRIP_T; + +/** + * @brief ETH Back Off Limit + */ +typedef enum +{ + ETH_BACKOFFLIMIT_10, /*!< Set back off limit to 10 */ + ETH_BACKOFFLIMIT_8, /*!< Set back off limit to 18 */ + ETH_BACKOFFLIMIT_4, /*!< Set back off limit to 4 */ + ETH_BACKOFFLIMIT_1 /*!< Set back off limit to 1 */ +} ETH_BACKOFFLIMIT_T; + +/** + * @brief ETH Deferral Check + */ +typedef enum +{ + ETH_DEFFERRALCHECK_DISABLE, /*!< Disable deferral check */ + ETH_DEFFERRALCHECK_ENABLE /*!< Enable deferral check */ +} ETH_DEFFERRALCHECK_T; + +/** + * @brief ETH Receive All + */ +typedef enum +{ + ETH_RECEIVEAll_DISABLE, /*!< Disable receive all */ + ETH_RECEIVEALL_ENABLE /*!< Enable receive all */ +} ETH_RECEIVEAll_T; + +/** + * @brief ETH Source Addr Filter + */ +typedef enum +{ + ETH_SOURCEADDRFILTER_DISABLE, /*!< Disable source address filter */ + ETH_SOURCEADDRFILTER_NORMAL_ENABLE = BIT9, /*!< Enable normal source address filter */ + ETH_SOURCEADDRFILTER_INVERSE_ENABLE = BIT8 | BIT9, /*!< Enable inverse source address filter */ +} ETH_SOURCEADDRFILTER_T; + +/** + * @brief ETH Pass Control Frames + */ +typedef enum +{ + ETH_PASSCONTROLFRAMES_BLOCKALL = 1, /*!< Even if all control frames except pause frames fail the + address filter, MAC forwards them to the application */ + ETH_PASSCONTROLFRAMES_FORWARDALL, /*!< MAC forwards control frames to the application even if + they do not pass the address filter */ + ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER /*!< MAC forwards control frames that pass through the address filter */ +} ETH_PASSCONTROLFRAMES_T; + +/** + * @brief ETH Broadcast Frames Reception + */ +typedef enum +{ + ETH_BROADCASTFRAMESRECEPTION_ENABLE, /*!< Enable broadcast frames */ + ETH_BROADCASTFRAMESRECEPTION_DISABLE /*!< Disable broadcast frames */ +} ETH_BROADCASTFRAMESRECEPTION_T; + +/** + * @brief ETH Destination Addr Filter + */ +typedef enum +{ + ETH_DESTINATIONADDRFILTER_NORMAL, /*!< Normal destination address filter */ + ETH_DESTINATIONADDRFILTER_INVERSE /*!< Inverse destination address filter */ +} ETH_DESTINATIONADDRFILTER_T; + +/** + * @brief ETH Destination Addr Filter + */ +typedef enum +{ + ETH_PROMISCUOUS_MODE_DISABLE, /*!< Disable promiscuous mode */ + ETH_PROMISCUOUS_MODE_ENABLE /*!< Enable promiscuous mode */ +} ETH_PROMISCUOUS_MODE_T; + +/** + * @brief ETH Multicast Frames Filter + */ +typedef enum +{ + ETH_MULTICASTFRAMESFILTER_PERFECT, /*!< Multicast perfect filter */ + ETH_MULTICASTFRAMESFILTER_NONE = BIT4, /*!< Multicast pass all multicast */ + ETH_MULTICASTFRAMESFILTER_HASHTABLE = BIT2, /*!< Multicast hash multicast */ + ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE = BIT2|BIT10 /*!< Multicast perfect hash table */ +} ETH_MULTICASTFRAMESFILTER_T; + +/** + * @brief ETH Unicast Frames Filter + */ +typedef enum +{ + ETH_UNICASTFRAMESFILTER_PERFECT, /*!< Unicast perfect filter */ + ETH_UNICASTFRAMESFILTER_HASHTABLE = BIT1, /*!< Unicast hash table */ + ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE = BIT1|BIT10 /*!< Unicast perfect hash table */ +} ETH_UNICASTFRAMESFILTER_T; + +/** + * @brief ETH Zero Quanta Pause + */ +typedef enum +{ + ETH_ZEROQUANTAPAUSE_ENABLE, /*!< Enable zero-quanta pause */ + ETH_ZEROQUANTAPAUSE_DISABLE /*!< Disable zero-quanta pause */ +} ETH_ZEROQUANTAPAUSE_T; + +/** + * @brief ETH Pause Low Threshold + */ +typedef enum +{ + ETH_PAUSELOWTHRESHOLD_MINUS4, /*!< Minus 4 slot-time */ + ETH_PAUSELOWTHRESHOLD_MINUS28, /*!< Minus 28 slot-time */ + ETH_PAUSELOWTHRESHOLD_MINUS144, /*!< Minus 144 slot-time */ + ETH_PAUSELOWTHRESHOLD_MINUS256 /*!< Minus 256 slot-time */ +} ETH_PAUSELOWTHRESHOLD_T; + +/** + * @brief ETH Unicast Pause Frame Detect + */ +typedef enum +{ + ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, /*!< Disable unicast pause frame detect */ + ETH_UNICASTPAUSEFRAMEDETECT_ENABLE /*!< Enable unicast pause frame detect */ +} ETH_UNICASTPAUSEFRAMEDETECT_T; + +/** + * @brief ETH Receive Flow Control + */ +typedef enum +{ + ETH_RECEIVEFLOWCONTROL_DISABLE, /*!< Disable receive flow control */ + ETH_RECEIVEFLOWCONTROL_ENABLE /*!< Enable receive flow control */ +} ETH_RECEIVEFLOWCONTROL_T; + +/** + * @brief ETH Transmit Flow Control + */ +typedef enum +{ + ETH_TRANSMITFLOWCONTROL_DISABLE, /*!< Disable transmit flow control */ + ETH_TRANSMITFLOWCONTROL_ENABLE /*!< Enable transmit flow control */ +} ETH_TRANSMITFLOWCONTROL_T; + +/** + * @brief ETH VLAN Tag Comparison + */ +typedef enum +{ + ETH_VLANTAGCOMPARISON_16BIT, /*!< 16-bit VLAN tag comparison */ + ETH_VLANTAGCOMPARISON_12BIT /*!< 12-bit VLAN tag comparison */ +} ETH_VLANTAGCOMPARISON_T; + +/** + * @brief ETH MAC Flags + */ +typedef enum +{ + ETH_MAC_FLAG_TST = 0x00000200, /*!< Time stamp trigger flag */ + ETH_MAC_FLAG_MMCT = 0x00000040, /*!< MMC transmit flag */ + ETH_MAC_FLAG_MMCR = 0x00000020, /*!< MMC receive flag */ + ETH_MAC_FLAG_MMC = 0x00000010, /*!< MMC flag */ + ETH_MAC_FLAG_PMT = 0x00000008 /*!< PMT flag */ +} ETH_MAC_FLAG_T; + +/** + * @brief ETH MAC Interrupts + */ +typedef enum +{ + ETH_MAC_INT_TST = 0x00000200, /*!< Time stamp trigger interrupt */ + ETH_MAC_INT_MMCT = 0x00000040, /*!< MMC transmit interrupt */ + ETH_MAC_INT_MMCR = 0x00000020, /*!< MMC receive interrupt */ + ETH_MAC_INT_MMC = 0x00000010, /*!< MMC interrupt */ + ETH_MAC_INT_PMT = 0x00000008 /*!< PMT interrupt */ +} ETH_MAC_INT_T; + +/** + * @brief ETH MAC Interrupts + */ +typedef enum +{ + ETH_MAC_ADDRESS0 = 0x00000000, /*!< MAC Address0 */ + ETH_MAC_ADDRESS1 = 0x00000008, /*!< MAC Address1 */ + ETH_MAC_ADDRESS2 = 0x00000010, /*!< MAC Address2 */ + ETH_MAC_ADDRESS3 = 0x00000018 /*!< MAC Address3 */ +} ETH_MAC_ADDRESS_T; + +/** + * @brief ETH MAC addresses filter SA/DA + */ +typedef enum +{ + ETH_MAC_ADDRESSFILTER_SA, /*!< MAC Address is used to compare with the + SA fields of the received frame */ + ETH_MAC_ADDRESSFILTER_DA = BIT30 /*!< MAC Address is used to compare with the + DA fields of the received frame */ +} ETH_MAC_ADDRESSFILTER_T; + +/** + * @brief ETH MAC addresses filter Mask bytes + */ +typedef enum +{ + ETH_MAC_ADDRESSMASK_BYTE6 = 0x20000000, /*!< Mask MAC Address high reg bits [15:8] */ + ETH_MAC_ADDRESSMASK_BYTE5 = 0x10000000, /*!< Mask MAC Address high reg bits [7:0] */ + ETH_MAC_ADDRESSMASK_BYTE4 = 0x08000000, /*!< Mask MAC Address low reg bits [31:24] */ + ETH_MAC_ADDRESSMASK_BYTE3 = 0x04000000, /*!< Mask MAC Address low reg bits [23:16] */ + ETH_MAC_ADDRESSMASK_BYTE2 = 0x02000000, /*!< Mask MAC Address low reg bits [15:8] */ + ETH_MAC_ADDRESSMASK_BYTE1 = 0x01000000 /*!< Mask MAC Address low reg bits [70] */ +} ETH_MAC_ADDRESSMASK_T; + +/** + * @brief DMA Tx descriptor flags + */ +typedef enum +{ + ETH_DMATXDESC_OWN = (int)0x80000000, /*!< Descriptor is owned by DMA engine */ + ETH_DMATXDESC_INTC = 0x40000000, /*!< Interrupt on completion */ + ETH_DMATXDESC_LS = 0x20000000, /*!< Last Segment */ + ETH_DMATXDESC_FS = 0x10000000, /*!< First Segment */ + ETH_DMATXDESC_DISC = 0x08000000, /*!< Disable CRC */ + ETH_DMATXDESC_DISP = 0x04000000, /*!< Disable Pad */ + ETH_DMATXDESC_TXTSEN = 0x02000000, /*!< Transmit Time Stamp Enable */ + ETH_DMATXDESC_TXENDR = 0x00200000, /*!< Transmit End of Ring */ + ETH_DMATXDESC_TXCH = 0x00100000, /*!< Second Address Chained */ + ETH_DMATXDESC_TXTSS = 0x00020000, /*!< Tx Time Stamp Status */ + ETH_DMATXDESC_IHERR = 0x00010000, /*!< IP Header Error */ + ETH_DMATXDESC_ERRS = 0x00008000, /*!< Error summary */ + ETH_DMATXDESC_JTO = 0x00004000, /*!< Jabber Timeout */ + ETH_DMATXDESC_FF = 0x00002000, /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ + ETH_DMATXDESC_IPERR = 0x00001000, /*!< Payload Checksum Error */ + ETH_DMATXDESC_LSC = 0x00000800, /*!< Loss of Carrier: carrier lost during transmission */ + ETH_DMATXDESC_NC = 0x00000400, /*!< No Carrier: no carrier signal from the transceiver */ + ETH_DMATXDESC_LC = 0x00000200, /*!< Late Collision: transmission aborted due to collision */ + ETH_DMATXDESC_EC = 0x00000100, /*!< Excessive Collision: transmission aborted after 16 collisions */ + ETH_DMATXDESC_VLANF = 0x00000080, /*!< VLAN Frame */ + ETH_DMATXDESC_CCNT = 0x00000078, /*!< Collision Count */ + ETH_DMATXDESC_EDEF = 0x00000004, /*!< Excessive Deferral */ + ETH_DMATXDESC_UFERR = 0x00000002, /*!< Underflow Error: late data arrival from the memory */ + ETH_DMATXDESC_DEF = 0x00000001 /*!< Deferred Bit */ +} ETH_DMATXDESC_FLAG_T; + +/** + * @brief ETH DMA Tx descriptor segment + */ +typedef enum +{ + ETH_DMATXDESC_LASTSEGMENTS = BIT30, /*!< Actual Tx desc contain last segment */ + ETH_DMATXDESC_FIRSTSEGMENT = BIT29 /*!< Actual Tx desc contain first segment */ +} ETH_DMATXDESC_SEGMENTS_T; + +/** + * @brief ETH DMA Tx descriptor Checksum Insertion Control + */ +typedef enum +{ + ETH_DMATXDESC_CHECKSUMBYPASS, /*!< Checksum bypass */ + ETH_DMATXDESC_CHECKSUMIPV4HEADER = BIT22, /*!< IPv4 header checksum */ + ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT = BIT23, /*!< TCP/UDP/ICMP checksum. Pseudo header + checksum is assumed to be present */ + ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL = BIT22|BIT23 /*!< TCP/UDP/ICMP checksum fully in hardware + including pseudo header */ +} ETH_DMATXDESC_CHECKSUMB_T; + +/** + * @brief DMA Rx descriptor status + */ +typedef enum +{ + ETH_DMARXDESC_OWN = (int)0x80000000U, /*!< Descriptor is owned by DMA engine */ + ETH_DMARXDESC_ADDRF = 0x40000000, /*!< DA Filter Fail for the rx frame */ + ETH_DMARXDESC_ERRS = 0x00008000, /*!< Error summary */ + ETH_DMARXDESC_DESERR = 0x00004000, /*!< Descriptor error: no more descriptors for receive frame */ + ETH_DMARXDESC_SADDRF = 0x00002000, /*!< SA Filter Fail for the received frame */ + ETH_DMARXDESC_LERR = 0x00001000, /*!< Frame size not matching with length field */ + ETH_DMARXDESC_OFERR = 0x00000800, /*!< Overflow Error: Frame was damaged due to buffer overflow */ + ETH_DMARXDESC_VLANF = 0x00000400, /*!< VLAN Tag: received frame is a VLAN frame */ + ETH_DMARXDESC_FDES = 0x00000200, /*!< First descriptor of the frame */ + ETH_DMARXDESC_LDES = 0x00000100, /*!< Last descriptor of the frame */ + ETH_DMARXDESC_IPV4HCE = 0x00000080, /*!< IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */ + ETH_DMARXDESC_LC = 0x00000040, /*!< Late collision occurred during reception */ + ETH_DMARXDESC_FT = 0x00000020, /*!< Frame type - Ethernet, otherwise 802.3 */ + ETH_DMARXDESC_RXWDTTO = 0x00000010, /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ + ETH_DMARXDESC_RERR = 0x00000008, /*!< Receive error: error reported by MII interface */ + ETH_DMARXDESC_DERR = 0x00000004, /*!< Dribble bit error: frame contains non int multiple of 8 bits */ + ETH_DMARXDESC_CERR = 0x00000002, /*!< CRC error */ + ETH_DMARXDESC_MAMPCE = 0x00000001 /*!< Rx MAC Address/Payload Checksum Error: + Rx MAC address matched/ Rx Payload Checksum Error */ +} ETH_DMARXDESC_FLAG_T; + +/** + * @brief DMA Rx descriptor extended flags + */ +typedef enum +{ + ETH_DMAPTPRXDESC_PTPV = 0x00002000, /*!< PTP version */ + ETH_DMAPTPRXDESC_PTPFT = 0x00001000, /*!< PTP frame type */ + ETH_DMAPTPRXDESC_PTPMT = 0x00000F00, /*!< PTP message type */ + ETH_DMAPTPRXDESC_IPV6P = 0x00000080, /*!< IPv6 packet received */ + ETH_DMAPTPRXDESC_IPV4P = 0x00000040, /*!< IPv4 packet received */ + ETH_DMAPTPRXDESC_IPCBP = 0x00000020, /*!< IP checksum bypassed */ + ETH_DMAPTPRXDESC_IPPERR = 0x00000010, /*!< IP payload error */ + ETH_DMAPTPRXDESC_IPHERR = 0x00000008, /*!< IP header error */ + ETH_DMAPTPRXDESC_IPPT = 0x00000007 /*!< IP payload type */ +} ETH_DMAPTPRXDESC_FLAG_T; + +/** + * @brief ETH DMA Rx descriptor buffers + */ +typedef enum +{ + ETH_DMARXDESC_BUFFER1, /*!< DMA Rx Desc Buffer1 */ + ETH_DMARXDESC_BUFFER2 /*!< DMA Rx Desc Buffer2 */ +} ETH_DMARXDESC_BUFFER_T; + +/** + * @brief ETH Drop TCP IP Checksum Error Frame + */ +typedef enum +{ + ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE, /*!< Enable dropping of TCP/IP checksum error frame */ + ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE /*!< Disable dropping of TCP/IP checksum error frame */ +} ETH_DROPTCPIPCHECKSUMERRORFRAME_T; + +/** + * @brief ETH Receive Store Forward + */ +typedef enum +{ + ETH_RECEIVESTOREFORWARD_DISABLE, /*!< Disable receive store and forward */ + ETH_RECEIVESTOREFORWARD_ENABLE /*!< Enable receive store and forward */ +} ETH_RECEIVESTOREFORWARD_T; + +/** + * @brief ETH Flush Received Frame + */ +typedef enum +{ + ETH_FLUSHRECEIVEDFRAME_ENABLE, /*!< Enable flushing of received frames */ + ETH_FLUSHRECEIVEDFRAME_DISABLE /*!< Disable flushing of received frames */ +} ETH_FLUSHRECEIVEDFRAME_T; + +/** + * @brief ETH Transmit Store Forward + */ +typedef enum +{ + ETH_TRANSMITSTOREFORWARD_DISABLE, /*!< Disable transmit store and forward */ + ETH_TRANSMITSTOREFORWARD_ENABLE /*!< Enable transmit store and forward */ +} ETH_TRANSMITSTOREFORWARD_T; + +/** + * @brief ETH Transmit Threshold Control + */ +typedef enum +{ + ETH_TRANSMITTHRESHOLDCONTROL_64BYTES, /*!< Select 64 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_128BYTES, /*!< Select 128 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_192BYTES, /*!< Select 192 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_256BYTES, /*!< Select 256 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_40BYTES, /*!< Select 40 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_32BYTES, /*!< Select 32 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_24BYTES, /*!< Select 24 bytes transmit threshild level */ + ETH_TRANSMITTHRESHOLDCONTROL_16BYTES /*!< Select 16 bytes transmit threshild level */ +} ETH_TRANSMITTHRESHOLDCONTROL_T; + +/** + * @brief ETH Forward Error Frames + */ +typedef enum +{ + ETH_FORWARDERRORFRAMES_DISABLE, /*!< Disable forward error frames */ + ETH_FORWARDERRORFRAMES_ENABLE /*!< Enable forward error frames */ +} ETH_FORWARDERRORFRAMES_T; + +/** + * @brief ETH Forward Undersized Good Frames + */ +typedef enum +{ + ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE, /*!< Disable forward undersized good frames */ + ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE /*!< Enable forward undersized good frames */ +} ETH_FORWARDUNDERSIZEDGOODFRAMES_T; + +/** + * @brief ETH Receive Threshold Control + */ +typedef enum +{ + ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES, /*!< Select 64 bytes receive threshold level */ + ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES, /*!< Select 32 bytes receive threshold level */ + ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES, /*!< Select 96 bytes receive threshold level */ + ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES /*!< Select 128 bytes receive threshold level */ +} ETH_RECEIVEDTHRESHOLDCONTROL_T; + +/** + * @brief ETH Second Frame Operate + */ +typedef enum +{ + ETH_SECONDFRAMEOPERARTE_DISABLE, /*!< Disable second frame operate */ + ETH_SECONDFRAMEOPERARTE_ENABLE /*!< Enable second frame operate */ +} ETH_SECONDFRAMEOPERARTE_T; + +/** + * @brief ETH Address Aligned Beats + */ +typedef enum +{ + ETH_ADDRESSALIGNEDBEATS_DISABLE, /*!< Disable address aligned beats */ + ETH_ADDRESSALIGNEDBEATS_ENABLE /*!< Enable address aligned beats */ +} ETH_ADDRESSALIGNEDBEATS_T; + +/** + * @brief ETH Fixed Burst + */ +typedef enum +{ + ETH_FIXEDBURST_DISABLE, /*!< Disable fixed burst */ + ETH_FIXEDBURST_ENABLE /*!< Enable fixed burst */ +} ETH_FIXEDBURST_T; + +/** + * @brief ETH Rx DMA Burst Length + */ +typedef enum +{ + ETH_RXDMABURSTLENGTH_1BEAT = BIT17, /*!< Maxnum number of Rx DMA transaction = 1 beat */ + ETH_RXDMABURSTLENGTH_2BEAT = BIT18, /*!< Maxnum number of Rx DMA transaction = 2 beat */ + ETH_RXDMABURSTLENGTH_4BEAT = BIT19, /*!< Maxnum number of Rx DMA transaction = 4 beat */ + ETH_RXDMABURSTLENGTH_8BEAT = BIT20, /*!< Maxnum number of Rx DMA transaction = 8 beat */ + ETH_RXDMABURSTLENGTH_16BEAT = BIT21, /*!< Maxnum number of Rx DMA transaction = 16 beat */ + ETH_RXDMABURSTLENGTH_32BEAT = BIT22, /*!< Maxnum number of Rx DMA transaction = 32 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_4BEAT = BIT17|BIT24, /*!< Maxnum number of Rx DMA transaction = 4 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_8BEAT = BIT18|BIT24, /*!< Maxnum number of Rx DMA transaction = 8 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_16BEAT = BIT19|BIT24, /*!< Maxnum number of Rx DMA transaction = 16 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_32BEAT = BIT20|BIT24, /*!< Maxnum number of Rx DMA transaction = 32 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_64BEAT = BIT21|BIT24, /*!< Maxnum number of Rx DMA transaction = 64 beat */ + ETH_RXDMABURSTLENGTH_4XPBL_128BEAT= BIT22|BIT24 /*!< Maxnum number of Rx DMA transaction = 128 beat */ +} ETH_RXDMABURSTLENGTH_T; + +/** + * @brief ETH Tx DMA Burst Length + */ +typedef enum +{ + ETH_TXDMABURSTLENGTH_1BEAT = BIT8, /*!< Maxnum number of Tx DMA transaction = 1 beat */ + ETH_TXDMABURSTLENGTH_2BEAT = BIT9, /*!< Maxnum number of Tx DMA transaction = 2 beat */ + ETH_TXDMABURSTLENGTH_4BEAT = BIT10, /*!< Maxnum number of Tx DMA transaction = 4 beat */ + ETH_TXDMABURSTLENGTH_8BEAT = BIT11, /*!< Maxnum number of Tx DMA transaction = 8 beat */ + ETH_TXDMABURSTLENGTH_16BEAT = BIT12, /*!< Maxnum number of Tx DMA transaction = 16 beat */ + ETH_TXDMABURSTLENGTH_32BEAT = BIT13, /*!< Maxnum number of Tx DMA transaction = 32 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_4BEAT = BIT8|BIT24, /*!< Maxnum number of Tx DMA transaction = 4 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_8BEAT = BIT9|BIT24, /*!< Maxnum number of Tx DMA transaction = 8 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_16BEAT = BIT10|BIT24, /*!< Maxnum number of Tx DMA transaction = 16 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_32BEAT = BIT11|BIT24, /*!< Maxnum number of Tx DMA transaction = 32 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_64BEAT = BIT12|BIT24, /*!< Maxnum number of Tx DMA transaction = 64 beat */ + ETH_TXDMABURSTLENGTH_4XPBL_128BEAT= BIT13|BIT24 /*!< Maxnum number of Tx DMA transaction = 128 beat */ +} ETH_TXDMABURSTLENGTH_T; + +/** + * @brief ETH DMA Arbitration + */ +typedef enum +{ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1, /*!< Priority ratio RX : TX = 1 : 1 */ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 = BIT14, /*!< Priority ratio RX : TX = 2 : 1 */ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 = BIT15, /*!< Priority ratio RX : TX = 3 : 1 */ + ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 = BIT14|BIT15, /*!< Priority ratio RX : TX = 4 : 1 */ + ETH_DMAARBITRATION_RXPRIORTX = BIT1 /*!< Rx priority ratio higher than Tx */ +} ETH_DMAARBITRATION_T; + +/** + * @brief ETH DMA Flags + */ +typedef enum +{ + ETH_DMA_FLAG_TST = 0x20000000, /*!< Time-stamp trigger interrupt (on DMA) */ + ETH_DMA_FLAG_PMT = 0x10000000, /*!< PMT interrupt (on DMA) */ + ETH_DMA_FLAG_MMC = 0x08000000, /*!< MMC interrupt (on DMA) */ + ETH_DMA_FLAG_DATATRANSFERERROR = 0x00800000, /*!< Error bits 0-Rx DMA, 1-Tx DMA */ + ETH_DMA_FLAG_READWRITEERROR = 0x01000000, /*!< Error bits 0-write transfer, 1-read transfer */ + ETH_DMA_FLAG_ACCESSERROR = 0x02000000, /*!< Error bits 0-data buffer, 1-desc. access */ + ETH_DMA_FLAG_NIS = 0x00010000, /*!< Normal interrupt summary flag */ + ETH_DMA_FLAG_AIS = 0x00008000, /*!< Abnormal interrupt summary flag */ + ETH_DMA_FLAG_ER = 0x00004000, /*!< Early receive flag */ + ETH_DMA_FLAG_FBE = 0x00002000, /*!< Fatal bus error flag */ + ETH_DMA_FLAG_ET = 0x00000400, /*!< Early transmit flag */ + ETH_DMA_FLAG_RWT = 0x00000200, /*!< Receive watchdog timeout flag */ + ETH_DMA_FLAG_RPS = 0x00000100, /*!< Receive process stopped flag */ + ETH_DMA_FLAG_RBU = 0x00000080, /*!< Receive buffer unavailable flag */ + ETH_DMA_FLAG_RX = 0x00000040, /*!< Receive flag */ + ETH_DMA_FLAG_TU = 0x00000020, /*!< Underflow flag */ + ETH_DMA_FLAG_RO = 0x00000010, /*!< Overflow flag */ + ETH_DMA_FLAG_TJT = 0x00000008, /*!< Transmit jabber timeout flag */ + ETH_DMA_FLAG_TBU = 0x00000004, /*!< Transmit buffer unavailable flag */ + ETH_DMA_FLAG_TPS = 0x00000002, /*!< Transmit process stopped flag */ + ETH_DMA_FLAG_TX = 0x00000001 /*!< Transmit flag */ +} ETH_DMA_FLAG_T; + +/** + * @brief ETH DMA Interrupts + */ +typedef enum +{ + ETH_DMA_INT_TST = 0x20000000, /*!< Time-stamp trigger interrupt (on DMA) */ + ETH_DMA_INT_PMT = 0x10000000, /*!< PMT interrupt (on DMA) */ + ETH_DMA_INT_MMC = 0x08000000, /*!< MMC interrupt (on DMA) */ + ETH_DMA_INT_NIS = 0x00010000, /*!< Normal interrupt summary */ + ETH_DMA_INT_AIS = 0x00008000, /*!< Abnormal interrupt summary */ + ETH_DMA_INT_ER = 0x00004000, /*!< Early receive interrupt */ + ETH_DMA_INT_FBE = 0x00002000, /*!< Fatal bus error interrupt */ + ETH_DMA_INT_ET = 0x00000400, /*!< Early transmit interrupt */ + ETH_DMA_INT_RWT = 0x00000200, /*!< Receive watchdog timeout interrupt */ + ETH_DMA_INT_RPS = 0x00000100, /*!< Receive process stopped interrupt */ + ETH_DMA_INT_RBU = 0x00000080, /*!< Receive buffer unavailable interrupt */ + ETH_DMA_INT_RX = 0x00000040, /*!< Receive interrupt */ + ETH_DMA_INT_TU = 0x00000020, /*!< Underflow interrupt */ + ETH_DMA_INT_RO = 0x00000010, /*!< Overflow interrupt */ + ETH_DMA_INT_TJT = 0x00000008, /*!< Transmit jabber timeout interrupt */ + ETH_DMA_INT_TBU = 0x00000004, /*!< Transmit buffer unavailable interrupt */ + ETH_DMA_INT_TPS = 0x00000002, /*!< Transmit process stopped interrupt */ + ETH_DMA_INT_TX = 0x00000001 /*!< Transmit interrupt */ +} ETH_DMA_INT_T; + +/** + * @brief ETH DMA transmit process state + */ +typedef enum +{ + ETH_DMA_TRANSMITPROCESS_STOPPED, /*!< Stopped - Reset or Stop Tx Command issued */ + ETH_DMA_TRANSMITPROCESS_FETCHING, /*!< Running - fetching the Tx descriptor */ + ETH_DMA_TRANSMITPROCESS_WAITING, /*!< Running - waiting for status */ + ETH_DMA_TRANSMITPROCESS_READING, /*!< Running - reading the data from host memory */ + ETH_DMA_TRANSMITPROCESS_SUSPENDED = 0x06, /*!< Suspended - Tx Descriptor unavailable */ + ETH_DMA_TRANSMITPROCESS_CLOSING = 0x07, /*!< Running - closing Rx descriptor */ +} ETH_DMA_TRANSMITPROCESS_T; + +/** + * @brief ETH DMA receive process state + */ +typedef enum +{ + ETH_DMA_RECEIVEPROCESS_STOPPED, /*!< Stopped - Reset or Stop Rx Command issued */ + ETH_DMA_RECEIVEPROCESS_FETCHING = 0x02, /*!< Running - fetching the Rx descriptor */ + ETH_DMA_RECEIVEPROCESS_WAITING = 0x06, /*!< Running - waiting for packet */ + ETH_DMA_RECEIVEPROCESS_SUSPENDED = 0x08, /*!< Suspended - Rx Descriptor unavailable */ + ETH_DMA_RECEIVEPROCESS_CLOSING = 0x0A, /*!< Running - closing descriptor */ + ETH_DMA_RECEIVEPROCESS_QUEUING = 0x0E /*!< Running - queuing the receive frame into host memory */ +} ETH_DMA_RECEIVEPROCESS_T; + +/** + * @brief ETH DMA overflow + */ +typedef enum +{ + ETH_DMA_OVERFLOW_RXFIFOCOUNTER = BIT28, /*!< Overflow for FIFO Overflows Counter */ + ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER = BIT16 /*!< Overflow for Buffer Unavailable Missed Frame Counter */ +} ETH_DMA_OVERFLOW_T; + +/** + * @brief ETH PMT Flags + */ +typedef enum +{ + ETH_PMT_FLAG_WUFFRPR = (int)BIT31, /*!< Wake-Up Frame Filter Register Pointer Reset */ + ETH_PMT_FLAG_WUFR = BIT6, /*!< Wake-Up Frame Received */ + ETH_PMT_FLAG_MPR = BIT5 /*!< Magic Packet Received */ +} ETH_PMT_FLAG_T; + +/** + * @brief ETH MMC Tx/RX Interrupts + */ +typedef enum +{ + ETH_MMC_INT_TGF = BIT21, /*!< When Tx good frame counter reaches half the maximum value */ + ETH_MMC_INT_TGFMSC = BIT15, /*!< When Tx good multi col counter reaches half the maximum value */ + ETH_MMC_INT_TGFSC = BIT14, /*!< When Tx good single col counter reaches half the maximum value */ + ETH_MMC_INT_RGUF = BIT21|BIT30, /*!< When Rx good unicast frames counter reaches half the maximum value */ + ETH_MMC_INT_RFAE = BIT6|BIT30, /*!< When Rx alignment error counter reaches half the maximum value */ + ETH_MMC_INT_RFCE = BIT5|BIT30 /*!< When Rx crc error counter reaches half the maximum value */ +} ETH_MMC_INT_T; + +/** + * @brief ETH MMC Registers + */ +typedef enum +{ + ETH_MMC_CTRL = 0x00000100, /*!< MMC CTRL register */ + ETH_MMC_RXINT = 0x00000104, /*!< MMC RXINT register */ + ETH_MMC_TXINT = 0x00000108, /*!< MMC TXINT register */ + ETH_MMC_RXINTMASK = 0x0000010C, /*!< MMC RXINTMASK register */ + ETH_MMC_TXINTMASK = 0x00000110, /*!< MMC TXINTMASK register */ + ETH_MMC_TXGFSCCNT = 0x0000014C, /*!< MMC TXGFSCCNT register */ + ETH_MMC_TXGFMCCNT = 0x00000150, /*!< MMC TXGFMCCNT register */ + ETH_MMC_TXGFCNT = 0x00000168, /*!< MMC TXGFCNT register */ + ETH_MMC_RXFCECNT = 0x00000194, /*!< MMC RXFCECNT register */ + ETH_MMC_RXFAECNT = 0x00000198, /*!< MMC RXFAECNT register */ + ETH_MMC_RXGUNCNT = 0x000001C4 /*!< MMC RXGUNCNT register */ +} ETH_MMC_REG_T; + +/**@} end of group ETH_Enumerations*/ + + +/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + @{ + */ + +/** +* DMA Tx Descriptor +* ----------------------------------------------------------------------------------------------- +* TXDES0 | OWN(31) | CTRL[30:25] | Reserved(24) | CTRL[23:20] | Reserved[19:18] | Status[17:0] | +* ----------------------------------------------------------------------------------------------- +* TXDES1 | Reserved[31:29] | Buffer2 Size[28:16] | Reserved[15:13] | Buffer1 Size[12:0] | +* ----------------------------------------------------------------------------------------------- +* TXDES2 | Buffer1 Address [31:0] | +* ----------------------------------------------------------------------------------------------- +* TXDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | +* ----------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of TXDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_INTC 0x40000000U /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ +#define ETH_DMATXDESC_DISC 0x08000000U /*!< Disable CRC */ +#define ETH_DMATXDESC_DISP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXDESC_TXTSEN 0x02000000U /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TXENDR 0x00200000U /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TXCH 0x00100000U /*!< Second Address Chained */ +#define ETH_DMATXDESC_TXTSS 0x00020000U /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHERR 0x00010000U /*!< IP Header Error */ +#define ETH_DMATXDESC_ERRS 0x00008000U /*!< Error summary: OR of the following bits: UFERR || EDEF || EC || LC || NC || LSC || FF || JTO */ +#define ETH_DMATXDESC_JTO 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_IPERR 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LSC 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LC 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VLANF 0x00000080U /*!< VLAN Frame */ +#define ETH_DMATXDESC_CCNT 0x00000078U /*!< Collision Count */ +#define ETH_DMATXDESC_EDEF 0x00000004U /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UFERR 0x00000002U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DEF 0x00000001U /*!< Deferred Bit */ + +/** + * @brief Bit definition of TXDES1 register + */ +#define ETH_DMATXDESC_TXBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TXBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TXDES2 register + */ +#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TXDES3 register + */ +#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + +/** +* --------------------------------------------------------------------------------------------- +* TXDES6 | Transmit Time Stamp Low [31:0] | +* --------------------------------------------------------------------------------------------- +* TXDES7 | Transmit Time Stamp High [31:0] | +* ---------------------------------------------------------------------------------------------- +*/ + +/** Bit definition of TXDES6 register */ +#define ETH_DMAPTPTXDESC_TXTSL 0xFFFFFFFFU /*!< Transmit Time Stamp Low */ + +/** Bit definition of TXDES7 register */ +#define ETH_DMAPTPTXDESC_TXTSH 0xFFFFFFFFU /*!< Transmit Time Stamp High */ + +/** + * @} + */ +/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + @{ + */ + +/** + *DMA Rx Descriptor + *-------------------------------------------------------------------------------------------------------------------- + *RXDES0 | OWN(31) | Status [30:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES1 | CTRL(31) | Reserved[30:29] | Buffer2 Size[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 Size[12:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES2 | Buffer1 Address [31:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + *--------------------------------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RXDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_ADDRF 0x40000000U /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ERRS 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DESERR 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SADDRF 0x00002000U /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LERR 0x00001000U /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OFERR 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLANF 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FDES 0x00000200U /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LDES 0x00000100U /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RXWWTTO 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RERR 0x00000008U /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DERR 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CERR 0x00000002U /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RXDES1 register + */ +#define ETH_DMARXDESC_DINTC 0x80000000U /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RXBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RXER 0x00008000U /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RXCH 0x00004000U /*!< Second Address Chained */ +#define ETH_DMARXDESC_RXBS1 0x00001FFFU /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RXDES2 register + */ +#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RXDES3 register + */ +#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + +/** + *--------------------------------------------------------------------------------------------------------------------- + *RXDES4 | Reserved[31:14] | Extended Status [13:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES5 | Reserved[31:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES6 | Receive Time Stamp Low [31:0] | + *--------------------------------------------------------------------------------------------------------------------- + *RXDES7 | Receive Time Stamp High [31:0] | + *--------------------------------------------------------------------------------------------------------------------- +*/ + +/** Bit definition of RXDES4 register */ +#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /*!< PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /*!< PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /*!< PTP Message Type */ +#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /*!< SYNC message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /*!< FollowUp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /*!< DelayReq message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /*!< DelayResp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /*!< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /*!< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /*!< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6P 0x00000080U /*!< IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4P 0x00000040U /*!< IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCBP 0x00000020U /*!< IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPERR 0x00000010U /*!< IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHERR 0x00000008U /*!< IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /*!< IP Payload Type */ +#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /*!< UDP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /*!< TCP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /*!< ICMP payload encapsulated in the IP datagram */ + +/** Bit definition of RXDES6 register */ +#define ETH_DMAPTPRXDESC_RXTSL 0xFFFFFFFFU /*!< Receive Time Stamp Low */ + +/** Bit definition of RXDES7 register */ +#define ETH_DMAPTPRXDESC_RXTSH 0xFFFFFFFFU /*!< Receive Time Stamp High */ +/** + * @} + */ + + +/** @addtogroup ETH_Macros Macros + *@{ + */ + +/** ETH Frames defines */ + +/** Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /*!< buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /*!< buffer size for transmit */ +#define ETH_RXBUFNB (10U) /*!< 10 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB (10U) /*!< 10 Tx buffers of size ETH_TX_BUF_SIZE */ + +/** ETH_Buffers_setting ETH Buffers setting */ +#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ + +/** +* Ethernet driver receive buffers are organized in a chained linked-list, when +* an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO +* to the driver receive buffers memory. +* +* Depending on the size of the received ethernet packet and the size of +* each ethernet driver receive buffer, the received packet can take one or more +* ethernet driver receive buffer. +* +* In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE +* and the total count of the driver receive buffers ETH_RXBUFNB. +* +* The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as +* example, they can be reconfigured in the application layer to fit the application +* needs +*/ + +/** Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet +* packet +*/ +#ifndef ETH_RX_BUF_SIZE +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/** 5 Ethernet driver receive buffers are used (in a chained linked list)*/ +#ifndef ETH_RXBUFNB +#define ETH_RXBUFNB 5U /*!< 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + +/** +* Ethernet driver transmit buffers are organized in a chained linked-list, when +* an ethernet packet is transmitted, Tx-DMA will transfer the packet from the +* driver transmit buffers memory to the TxFIFO. +* +* Depending on the size of the Ethernet packet to be transmitted and the size of +* each ethernet driver transmit buffer, the packet to be transmitted can take +* one or more ethernet driver transmit buffer. +* +* In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE +* and the total count of the driver transmit buffers ETH_TXBUFNB. +* +* The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as +* example, they can be reconfigured in the application layer to fit the application +* needs +*/ + +/** Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet +* packet +*/ +#ifndef ETH_TX_BUF_SIZE +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/** 5 ethernet driver transmit buffers are used (in a chained linked list)*/ +#ifndef ETH_TXBUFNB +#define ETH_TXBUFNB 5U /*!< 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#endif + +/** ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /*!< ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /*!< ETHERNET MAC address low offset */ + +/** ETHERNET Errors */ +#define ETH_SUCCESS 1U +#define ETH_ERROR 0U + +/** ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U + +/** ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U + +/** ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U + +/** ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U + +/** ETHERNET DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U + +/** ETHERNET MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U + +/** ETHERNET MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK 0xFF20010FU + +/** ETHERNET MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U + +/** ETHERNET DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U + +/** ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U + +/** ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U + +/** PHY registers defines */ + +/** PHY Read write Timeouts */ +#define PHY_READ_TIMEOUT ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TIMEOUT ((uint32_t)0x0004FFFF) + +/** PHY Register address */ +#define PHY_BCR 0 /*!< Transceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Transceiver Basic Status Register */ +#define PHY_SR 16 /*!< Transceiver Status Register for dp83848 */ + +/** PHY Status Register (PHYSTS), address 0x10 */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< for dp83848 ((uint16_t)0x0010) */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< for dp83848 ((uint16_t)0x0004) */ + +/** PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/** PHY basic Control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTAET_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +/** PHY Delay */ +#define PHY_RESET_DELAY ((uint32_t)0x000FFFFF) /*!< PHY reset delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF) /*!< PHY configuration delay */ +/** Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY ((uint32_t)0x0000FFFF) + +/** Ethernet MAC MII Address Clock Range*/ +#define ETH_MACMIIAR_CR_DIV42 ((uint8_t)0x00) /*!< HCLK:60-100 MHz; MDC clock = HCLK/42 */ +#define ETH_MACMIIAR_CR_DIV62 ((uint8_t)0x01) /*!< HCLK:100-150 MHz; MDC clock = HCLK/62 */ +#define ETH_MACMIIAR_CR_DIV16 ((uint8_t)0x02) /*!< HCLK:20-35 MHz; MDC clock = HCLK/16 */ +#define ETH_MACMIIAR_CR_DIV26 ((uint8_t)0x03) /*!< HCLK:35-60 MHz; MDC clock = HCLK/26 */ +#define ETH_MACMIIAR_CR_DIV102 ((uint8_t)0x04) /*!< HCLK:150-168 MHz; MDC clock = HCLK/102 */ + +/** Control the Enhanced DMA descriptors */ +#define USE_ENHANCED_DMA_DESCRIPTORS 1 + +/**@} end of group ETH_Macros */ + + +/** @addtogroup ETH_Structure Data Structure + @{ +*/ + +/** + * @brief ETH MAC Config structure types + */ +typedef struct +{ + /** MAC Configuration */ + ETH_AUTONEGOTIATION_T autoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex) */ + + ETH_WATCHDOG_T watchDog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. */ + + ETH_JABBER_T jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. */ + ETH_INTERFRAMEGAP_T interFrameGap; /*!< Selects the minimum IFG between frames during transmission */ + + ETH_CARRIERSENCE_T carrierSense; /*!< Selects or not the Carrier Sense */ + + ETH_SPEED_T speed; /*!< Sets the Ethernet speed: 10/100 Mbps */ + + ETH_RECEIVEOWN_T receiveOwn; /*!< Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode */ + + ETH_LOOPBACKMODE_T loopbackMode; /*!< Selects or not the internal MAC MII Loopback mode */ + + ETH_MODE_T mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + + ETH_CHECKSUMOFFLAOD_T checksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. */ + + ETH_RETRYTRANSMISSION_T retryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a collision occurs (Half-Duplex mode) */ + + ETH_AUTOMATICPADCRCSTRIP_T automaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping */ + + ETH_BACKOFFLIMIT_T backOffLimit; /*!< Selects the BackOff limit value */ + + ETH_DEFFERRALCHECK_T deferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) */ + + ETH_RECEIVEAll_T receiveAll; /*!< Selects or not all frames reception by the MAC (No filtering) */ + + ETH_SOURCEADDRFILTER_T sourceAddrFilter; /*!< Selects the Source Address Filter mode */ + + ETH_PASSCONTROLFRAMES_T passControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) */ + + ETH_BROADCASTFRAMESRECEPTION_T broadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames */ + + ETH_DESTINATIONADDRFILTER_T destinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames */ + + ETH_PROMISCUOUS_MODE_T promiscuousMode; /*!< Selects or not the Promiscuous Mode */ + + ETH_MULTICASTFRAMESFILTER_T multicastFramesFilter; /*!< Selects the Multicast Frames filter mode */ + + ETH_UNICASTFRAMESFILTER_T unicastFramesFilter; /*!< Selects the Unicast Frames filter mode */ + + + uint32_t hashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ + + uint32_t hashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ + + uint32_t pauseTime; /*!< This field holds the (value<=0xFFFF) to be used in the Pause Time */ + + ETH_ZEROQUANTAPAUSE_T zeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames */ + + ETH_PAUSELOWTHRESHOLD_T pauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame */ + + ETH_UNICASTPAUSEFRAMEDETECT_T unicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) */ + + ETH_RECEIVEFLOWCONTROL_T receiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) */ + + ETH_TRANSMITFLOWCONTROL_T transmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) */ + + ETH_VLANTAGCOMPARISON_T VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering */ + + uint32_t VLANTagIdentifier; /*!< Holds the (value <=0xFFFF) VLAN tag identifier for receive frames */ + + /** DMA Configuration */ + ETH_DROPTCPIPCHECKSUMERRORFRAME_T dropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */ + + ETH_RECEIVESTOREFORWARD_T receiveStoreForward; /*!< Enables or disables the Receive store and forward mode */ + + ETH_FLUSHRECEIVEDFRAME_T flushReceivedFrame; /*!< Enables or disables the flushing of received frames */ + + ETH_TRANSMITSTOREFORWARD_T transmitStoreForward; /*!< Enables or disables Transmit store and forward mode */ + + ETH_TRANSMITTHRESHOLDCONTROL_T transmitThresholdControl; /*!< Selects or not the Transmit Threshold Control */ + + ETH_FORWARDERRORFRAMES_T forwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames */ + + ETH_FORWARDUNDERSIZEDGOODFRAMES_T forwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) */ + + ETH_RECEIVEDTHRESHOLDCONTROL_T receiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ + + ETH_SECONDFRAMEOPERARTE_T secondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. */ + + ETH_ADDRESSALIGNEDBEATS_T addressAlignedBeats; /*!< Enables or disables the Address Aligned Beats */ + + ETH_FIXEDBURST_T fixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers */ + + ETH_RXDMABURSTLENGTH_T rxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction */ + + ETH_TXDMABURSTLENGTH_T txDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction */ + + uint32_t descriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) (value <= 0x1F) */ + + ETH_DMAARBITRATION_T DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration */ +} ETH_Config_T; + +/** + * @brief ETH DMA Descriptors data structure types + */ +typedef struct +{ + __IO uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + /* Enhanced ETHERNET DMA PTP Descriptors */ + #if USE_ENHANCED_DMA_DESCRIPTORS + uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ + uint32_t Reserved1; /*!< Reserved */ + uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ + uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ + #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ +} ETH_DMADescConfig_T; + +/** + * @brief ETH DMA Descriptors data structure types + */ +typedef struct +{ + uint32_t length; /*!< Data length */ + uint32_t buffer; /*!< Data buffer */ + __IO ETH_DMADescConfig_T *descriptor; /*!< DMA descriptor */ +} ETH_Frame_T; + +/** + * @brief ETH DMA Descriptors Received Frame Informations structure types + */ +typedef struct { + __IO ETH_DMADescConfig_T *FS_RxDesc; /*!< First Segment Rx Desc */ + __IO ETH_DMADescConfig_T *LS_RxDesc; /*!< Last Segment Rx Desc */ + __IO uint32_t segCount; /*!< Segment count */ +} ETH_DMARxFrameInformations; + +/**@} end of group ETH_Structure*/ + +/** @defgroup ETH_Functions + @{ +*/ + +/* ETH Configuration */ +void ETH_Reset(void); +void ETH_ConfigStructInit(ETH_Config_T* ethConfig); +uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr); +void ETH_SoftwareReset(void); +uint8_t ETH_ReadSoftwareReset(void); +void ETH_Start(void); +void ETH_Stop(void); +uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T *DMARxDesc); +#if USE_ENHANCED_DMA_DESCRIPTORS +void ETH_EnableEnhancedDescriptor(void); +void ETH_DisableEnhancedDescriptor(void); +#endif /*!< USE_ENHANCED_DMA_DESCRIPTORS */ + +/* PHY */ +uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg); +uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data); +uint32_t ETH_EnablePHYLoopBack(uint16_t addr); +uint32_t ETH_DisablePHYLoopBack(uint16_t addr); + +/* MAC */ +void ETH_EnableMACTransmission(void); +void ETH_DisableMACTransmission(void); +void ETH_EnableMACReceiver(void); +void ETH_DisableMACReceiver(void); +uint8_t ETH_ReadFlowControlBusyStatus(void); +void ETH_SetPauseControlFrame(void); +void ETH_EnableBackPressureActivation(void); +void ETH_DisableBackPressureActivation(void); +uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag); +void ETH_EnableMACInterrupt(uint32_t interrupt); +void ETH_DisableMACInterrupt(uint32_t interrupt); +void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr); +void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr); +void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr); +void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr); +void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter); +void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte); + +/* DMA descriptors */ +void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T *DMARxDescTab, uint8_t *rxBuff, uint32_t rxBuffcount); +void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T *DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount); +uint32_t ETH_CheckReceivedFrame(void); +uint32_t ETH_Transmit_Descriptors(u16 frameLength); +ETH_Frame_T ETH_ReadReceivedFrame(void); +uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_FLAG_T flag); +uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T *DMATxDesc); +void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T *DMATxDesc); +void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc); +void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc); +void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment); +void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum); +void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc); +void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc); +void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc); +void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc); +void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc); +void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc); +void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T *DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2); +uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_FLAG_T flag); +#if USE_ENHANCED_DMA_DESCRIPTORS +uint8_t ETH_ReadDMAPTPRxDescExtendedFlagStatus(ETH_DMADescConfig_T *DMAPTPRxDesc, ETH_DMAPTPRXDESC_FLAG_T flag); +#endif +void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T *DMARxDesc); +uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T *DMARxDesc); +void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMARxDesc); +void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMATxDesc); +uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer); +ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void); + +/* DMA */ +uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag); +void ETH_ClearDMAFlag(uint32_t flag); +uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag); +void ETH_ClearDMAIntFlag(uint32_t flag); +uint32_t ETH_ReadTransmitProcessState(void); +uint32_t ETH_ReadReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +uint8_t ETH_ReadFlushTransmitFIFOStatus(void); +void ETH_EnableDMATransmission(void); +void ETH_DisableDMATransmission(void); +void ETH_EnableDMAReceiver(void); +void ETH_DisableDMAReceiver(void); +void ETH_EnableDMAInterrupt(uint32_t interrupt); +void ETH_DisableDMAInterrupt(uint32_t interrupt); +uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow); +uint32_t ETH_ReadRxOverflowMissedFrameCounter(void); +uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_ReadCurrentTxDescStartAddress(void); +uint32_t ETH_ReadCurrentRxDescStartAddress(void); +uint32_t ETH_ReadCurrentTxBufferAddress(void); +uint32_t ETH_ReadCurrentRxBufferAddress(void); +void ETH_ResetDMATransmission(void); +void ETH_ResetDMAReception(void); +void ETH_ConfigReceiveWatchdogTimer(uint8_t value); + +/* PMT */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_ConfigWakeUpFrameFilterRegister(uint32_t *buffer); +void ETH_EnableGlobalUnicastWakeUp(void); +void ETH_DisableGlobalUnicastWakeUp(void); +uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag); +void ETH_EnableWakeUpFrameDetection(void); +void ETH_DisableWakeUpFrameDetection(void); +void ETH_EnableMagicPacketDetection(void); +void ETH_DisableMagicPacketDetection(void); +void ETH_EnablePowerDown(void); +void ETH_DisablePowerDown(void); + +/* MMC */ +void ETH_PresetMMCCounterFull(void); +void ETH_PresetMMCCounterHalf(void); +void ETH_EnableMMCCounterFreeze(void); +void ETH_DisableMMCCounterFreeze(void); +void ETH_EnableMMCResetOnRead(void); +void ETH_DisableMMCResetOnRead(void); +void ETH_EnableMMCCounterRollover(void); +void ETH_DisableMMCCounterRollover(void); +void ETH_ResetMMCCounters(void); +void ETH_EnableMMCInterrupt(uint32_t interrupt); +void ETH_DisableMMCInterrupt(uint32_t interrupt); +uint8_t ETH_ReadMMCIntFlag(uint32_t flag); +uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg); + +#ifdef __cplusplus +} +#endif + +#endif /** __APM32F4xx_ETH_H */ + +/**@} end of group ETH_Functions */ +/**@} end of group ETH_Driver */ +/**@} end of group APM32F4xx_ETHDriver */ diff --git a/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c b/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c new file mode 100644 index 0000000000..58ec0c7bf5 --- /dev/null +++ b/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c @@ -0,0 +1,2303 @@ +/*! + * @file apm32f4xx_eth.c + * + * @brief This file provides all the ETH firmware functions + * + * @version V1.0.2 + * + * @date 2022-06-23 + * + * @attention + * + * Copyright (C) 2021-2022 Geehy Semiconductor + * + * You may not use this file except in compliance with the + * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). + * + * The program is only for reference, which is distributed in the hope + * that it will be usefull and instructional for customers to develop + * their software. Unless required by applicable law or agreed to in + * writing, the program is distributed on an "AS IS" BASIS, WITHOUT + * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. + * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions + * and limitations under the License. + */ + +#include "apm32f4xx_eth.h" +#include "apm32f4xx_rcm.h" + +/** @addtogroup APM32F4xx_ETHDriver + @{ +*/ + +/** @defgroup ETH_Driver + * @brief ETH driver modules + @{ +*/ + +#if defined (__CC_ARM) /*!< ARM Compiler */ +__align(4) +ETH_DMADescConfig_T DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */ +__align(4) +ETH_DMADescConfig_T DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */ +__align(4) +uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /*!< Ethernet Receive Buffer */ +__align(4) +uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /*!< Ethernet Transmit Buffer */ + +#elif defined ( __ICCARM__ ) + +ETH_DMADescConfig_T DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */ +ETH_DMADescConfig_T DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */ +uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /*!< Ethernet Receive Buffer */ +uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /*!< Ethernet Transmit Buffer */ + +#endif + +/** @defgroup Global_Definition + @{ +*/ + +/* Global pointers on Tx and Rx descriptor used to transmit and receive descriptors */ +__IO ETH_DMADescConfig_T *DMATxDescToSet; +__IO ETH_DMADescConfig_T *DMARxDescToGet; + +/* Structure used to hold the last received packet descriptors info */ +ETH_DMARxFrameInformations RxFrameDescriptor; +__IO ETH_DMARxFrameInformations *DMARxFraminfos; +__IO uint32_t FrameRxindex; + +/** + * @} + */ + +/** @defgroup ETH_Functions + @{ +*/ + +/*! + * @brief Inserts a delay time. + * + * @param count: specifies the delay time length. + * + * @retval None + */ +static void ETH_Delay(__IO uint32_t count) +{ + __IO uint32_t i = 0; + for(i = count; i!= 0; i--) + { + } +} + +/** ETH Configuration */ + +/*! + * @brief Reset ETH peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void ETH_Reset(void) +{ + RCM_EnableAHB1PeriphReset(RCM_AHB1_PERIPH_ETH_MAC); + RCM_DisableAHB1PeriphReset(RCM_AHB1_PERIPH_ETH_MAC); +} + +/*! + * @brief Config ETH_Config_T member with its default value. + * + * @param ethConfig: pointer to a ETH_Config_T structure which will be initialized. + * + * @retval None + */ +void ETH_ConfigStructInit(ETH_Config_T* ethConfig) +{ + /* MAC Configuration */ + ethConfig->autoNegotiation = ETH_AUTONEGOTIATION_ENABLE; + ethConfig->watchDog = ETH_WATCHDOG_ENABLE; + ethConfig->jabber = ETH_JABBER_ENABLE; + ethConfig->interFrameGap = ETH_INTERFRAMEGAP_96BIT; + ethConfig->carrierSense = ETH_CARRIERSENCE_ENABLE; + ethConfig->speed = ETH_SPEED_100M; + ethConfig->receiveOwn = ETH_RECEIVEOWN_ENABLE; + ethConfig->loopbackMode = ETH_LOOPBACKMODE_DISABLE; + ethConfig->mode = ETH_MODE_FULLDUPLEX; + ethConfig->checksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + ethConfig->retryTransmission = ETH_RETRYTRANSMISSION_ENABLE; + ethConfig->automaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + ethConfig->backOffLimit = ETH_BACKOFFLIMIT_10; + ethConfig->deferralCheck = ETH_DEFFERRALCHECK_DISABLE; + ethConfig->receiveAll = ETH_RECEIVEAll_DISABLE; + ethConfig->sourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; + ethConfig->passControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; + ethConfig->broadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_DISABLE; + ethConfig->destinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; + ethConfig->promiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + ethConfig->multicastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + ethConfig->unicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; + ethConfig->hashTableHigh = 0x0000; + ethConfig->hashTableLow = 0x0000; + ethConfig->pauseTime = 0x0000; + ethConfig->zeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; + ethConfig->pauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + ethConfig->unicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; + ethConfig->receiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; + ethConfig->transmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; + ethConfig->VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; + ethConfig->VLANTagIdentifier = 0x0000; + /* DMA Configuration */ + ethConfig->dropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE; + ethConfig->receiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + ethConfig->flushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; + ethConfig->transmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + ethConfig->transmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + ethConfig->forwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + ethConfig->forwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + ethConfig->receiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + ethConfig->secondFrameOperate = ETH_SECONDFRAMEOPERARTE_DISABLE; + ethConfig->addressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + ethConfig->fixedBurst = ETH_FIXEDBURST_ENABLE; + ethConfig->rxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + ethConfig->txDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + ethConfig->descriptorSkipLength = 0x00; + ethConfig->DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; +} + +/*! + * @brief Config the ETH peripheral parameters in the ethConfig. + * + * @param ethConfig: pointer to a ETH_Config_T structure. + * + * @param addr: external PHY address + * + * @retval ETH_ERROR: Ethernet initialization error + * ETH_SUCCESS: Ethernet initialization success + */ +uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr) +{ + uint32_t regValue = 0; + uint32_t hclk = 60000000; + __IO uint32_t timeout = 0, err = ETH_SUCCESS; + + hclk = RCM_ReadHCLKFreq(); + + if((hclk >= 20000000) && (hclk <= 35000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV26; + } + else if((hclk >= 60000000)&&(hclk < 100000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV42; + } + else if((hclk >= 100000000)&&(hclk < 150000000)) + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV62; + } + else + { + ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV102; + } + + /* PHY initialization and configuration */ + if(!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_RESET))) + { + /* Return ERROR in case of write timeout */ + err = ETH_ERROR; + goto error; + } + + ETH_Delay(PHY_RESET_DELAY); + + if(ethConfig->autoNegotiation == ETH_AUTONEGOTIATION_ENABLE) + { + /* Wait for linked status */ + do + { + timeout++ ; + } while(!(ETH_ReadPHYRegister(addr,PHY_BSR) & PHY_LINKED_STATUS) && (timeout < PHY_READ_TIMEOUT)); + + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TIMEOUT) + { + err = ETH_ERROR; + goto error; + } + + timeout = 0; + /* Enable Auto-Negotiation */ + if(!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_AUTONEGOTIATION))) + { + /* Return ERROR in case of write timeout */ + err = ETH_ERROR; + } + + /* Wait until the auto-negotiation will be completed */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(addr, PHY_BSR) & PHY_AUTONEGO_COMPLETE) && (timeout < (uint32_t)PHY_READ_TIMEOUT)); + + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TIMEOUT) + { + err = ETH_ERROR; + goto error; + } + + timeout = 0; + /* Read the result of the auto-negotiation */ + regValue = ETH_ReadPHYRegister(addr, PHY_SR); + + if((regValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) + { + ethConfig->mode = ETH_MODE_FULLDUPLEX; + } + else + { + ethConfig->mode = ETH_MODE_HALFDUPLEX; + } + if(regValue & PHY_SPEED_STATUS) + { + ethConfig->speed = ETH_SPEED_10M; + } + else + { + ethConfig->speed = ETH_SPEED_100M; + } + } + else + { + if(!ETH_WritePHYRegister(addr, PHY_BCR,((uint16_t)(ethConfig->speed << 8) | + (uint16_t)(ethConfig->mode << 13)))) + { + err = ETH_ERROR; + } + + ETH_Delay(PHY_CONFIG_DELAY); + } +error: + if(err == ETH_ERROR) + { + ethConfig->speed = ETH_SPEED_100M; + ethConfig->mode = ETH_MODE_FULLDUPLEX; + } + + /* ETHERNET MAC_CFG Configuration */ + ETH->CFG_B.WDTDIS = ethConfig->watchDog; + ETH->CFG_B.JDIS = ethConfig->jabber; + ETH->CFG_B.IFG = ethConfig->interFrameGap; + ETH->CFG_B.DISCRS = ethConfig->carrierSense; + ETH->CFG_B.SSEL = ethConfig->speed; + ETH->CFG_B.DISRXO = ethConfig->receiveOwn; + ETH->CFG_B.LBM = ethConfig->loopbackMode; + ETH->CFG_B.DM = ethConfig->mode; + ETH->CFG_B.IPC = ethConfig->checksumOffload; + ETH->CFG_B.DISR = ethConfig->retryTransmission; + ETH->CFG_B.ACS = ethConfig->automaticPadCRCStrip; + ETH->CFG_B.BL = ethConfig->backOffLimit; + ETH->CFG_B.DC = ethConfig->deferralCheck; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET MAC_FRAF Configuration */ + ETH->FRAF_B.RXA = ethConfig->receiveAll; + ETH->FRAF |= ethConfig->sourceAddrFilter; + ETH->FRAF_B.PCTRLF = ethConfig->passControlFrames; + ETH->FRAF_B.DISBF = ethConfig->broadcastFramesReception; + ETH->FRAF_B.DAIF = ethConfig->destinationAddrFilter; + ETH->FRAF_B.PR = ethConfig->promiscuousMode; + ETH->FRAF |= ethConfig->multicastFramesFilter; + ETH->FRAF |= ethConfig->unicastFramesFilter; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET MAC_HTH/HTL Configuration */ + ETH->HTH = ethConfig->hashTableHigh; + ETH->HTL = ethConfig->hashTableLow; + + /* ETHERNET MAC_FCTRL Configuration */ + ETH->FCTRL_B.PT = ethConfig->pauseTime; + ETH->FCTRL_B.ZQPDIS = ethConfig->zeroQuantaPause; + ETH->FCTRL_B.PTSEL = ethConfig->pauseLowThreshold; + ETH->FCTRL_B.UNPFDETE = ethConfig->unicastPauseFrameDetect; + ETH->FCTRL_B.RXFCTRLEN = ethConfig->receiveFlowControl; + ETH->FCTRL_B.TXFCTRLEN = ethConfig->transmitFlowControl; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET MAC_VLANT Configuration */ + ETH->VLANT_B.VLANTCOMP = ethConfig->VLANTagComparison; + ETH->VLANT_B.VLANTID = ethConfig->VLANTagIdentifier; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET DMA_OPMOD Configuration */ + ETH->DMAOPMOD_B.DISDT = ethConfig->dropTCPIPChecksumErrorFrame; + ETH->DMAOPMOD_B.RXSF = ethConfig->receiveStoreForward; + ETH->DMAOPMOD_B.DISFRXF = ethConfig->flushReceivedFrame; + ETH->DMAOPMOD_B.TXSF = ethConfig->transmitStoreForward; + ETH->DMAOPMOD_B.TXTHCTRL = ethConfig->transmitThresholdControl; + ETH->DMAOPMOD_B.FERRF = ethConfig->forwardErrorFrames; + ETH->DMAOPMOD_B.FUF = ethConfig->forwardUndersizedGoodFrames; + ETH->DMAOPMOD_B.RXTHCTRL = ethConfig->receiveThresholdControl; + ETH->DMAOPMOD_B.OSECF = ethConfig->secondFrameOperate; + ETH_Delay(ETH_REG_WRITE_DELAY); + + /* ETHERNET DMA_BMOD Configuration */ + ETH->DMABMOD = RESET; + ETH->DMABMOD_B.AAL = ethConfig->addressAlignedBeats; + ETH->DMABMOD_B.FB = ethConfig->fixedBurst; + ETH->DMABMOD |= ethConfig->rxDMABurstLength; + ETH->DMABMOD |= ethConfig->txDMABurstLength; + ETH->DMABMOD_B.DSL = ethConfig->descriptorSkipLength; + ETH->DMABMOD |= ethConfig->DMAArbitration; + ETH->DMABMOD_B.USP = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); + +#if USE_ENHANCED_DMA_DESCRIPTORS + ETH->DMABMOD_B.EDFEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +#endif + + if(err == ETH_SUCCESS) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/*! + * @brief Resets all MAC subsystem internal registers and logic. + * + * @param None + * + * @retval None + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMOD_B.SWR = SET; +} + +/*! + * @brief Read the ETH software reset bit. + * + * @param None + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadSoftwareReset(void) +{ + return ETH->DMABMOD_B.SWR; +} + +/*! + * @brief Enables ETH MAC and DMA reception/transmission + * + * @param None + * + * @retval None + */ +void ETH_Start(void) +{ + ETH_EnableMACTransmission(); + ETH_EnableMACReceiver(); + ETH_FlushTransmitFIFO(); + ETH_EnableDMATransmission(); + ETH_EnableDMAReceiver(); +} + +/*! + * @brief Disables ETH MAC and DMA reception/transmission + * + * @param None + * + * @retval None + */ +void ETH_Stop(void) +{ + ETH_DisableDMATransmission(); + ETH_DisableDMAReceiver(); + ETH_DisableMACReceiver(); + ETH_FlushTransmitFIFO(); + ETH_DisableMACTransmission(); +} + +/*! + * @brief Read the size of the received packet. + * + * @param None + * + * @retval frameLength: received packet size + */ +uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T *DMARxDesc) +{ + uint32_t frameLength = 0; + if(((DMARxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) && + ((DMARxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET)) + { + frameLength = ETH_ReadDMARxDescFrameLength(DMARxDesc); + } + return frameLength; +} + +#if USE_ENHANCED_DMA_DESCRIPTORS +/*! + * @brief Enable the Enhanced descriptor structure. + * + * @param None + * + * @retval None + */ +void ETH_EnableEnhancedDescriptor(void) +{ + ETH->DMABMOD_B.EDFEN = SET; +} + +/*! + * @brief Disable the Enhanced descriptor structure. + * + * @param None + * + * @retval None + */ +void ETH_DisableEnhancedDescriptor(void) +{ + ETH->DMABMOD_B.EDFEN = RESET; +} +#endif /** USE_ENHANCED_DMA_DESCRIPTORS */ + +/** PHY functions */ + +/*! + * @brief Read a PHY register + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + * + * @param reg: PHY register + * This parameter can be one of the following values: + * @arg PHY_BCR : Transceiver Basic Control Register + * @arg PHY_BSR : Transceiver Basic Status Register + * @arg PHY_SR : Transceiver Status Register + * + * @retval ETH_ERROR: in case of timeout + * MAC DATA register value: Data read from the selected PHY register + */ +uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg) +{ + __IO uint32_t timeout = 0; + + ETH->ADDR_B.PA = addr; + ETH->ADDR_B.MR = reg; + ETH->ADDR_B.MW = RESET; + ETH->ADDR_B.MB = SET; + /* Check for the Busy flag */ + do + { + timeout++ ; + } while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_READ_TIMEOUT)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TIMEOUT) + { + return ETH_ERROR; + } + /* Return data register value */ + return (uint16_t)(ETH->DATA); +} + +/*! + * @brief Write to a PHY register + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + + * @param reg: PHY register + * This parameter can be one of the following values: + * @arg PHY_BCR : Transceiver Basic Control Register + + * @param data: the data to write + * + * @retval ETH_ERROR: write timeout + * ETH_SUCCESS: write success + */ +uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data) +{ + __IO uint32_t timeout = 0; + + ETH->DATA = data; + ETH->ADDR_B.PA = addr; + ETH->ADDR_B.MR = reg; + ETH->ADDR_B.MW = SET; + ETH->ADDR_B.MB = SET; + + /* Check for the Busy flag */ + do + { + timeout++ ; + } while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_WRITE_TIMEOUT)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TIMEOUT) + { + return ETH_ERROR; + } + /* Return data register value */ + return ETH_SUCCESS; +} + +/*! + * @brief Enable the PHY loopBack mode. + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + * + * @retval ETH_ERROR or ETH_SUCCESS + */ +uint32_t ETH_EnablePHYLoopBack(uint16_t addr) +{ + uint16_t temp = 0; + + temp = ETH_ReadPHYRegister(addr,PHY_BCR); + temp |= PHY_LOOPBACK; + + if(ETH_WritePHYRegister(addr,PHY_BCR,temp) == SET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/*! + * @brief Disable the PHY loopBack mode. + * + * @param addr: PHY device address + * This parameter can be one of the following values: 0,..,31 + * + * @retval ETH_ERROR or ETH_SUCCESS + */ +uint32_t ETH_DisablePHYLoopBack(uint16_t addr) +{ + uint16_t temp = 0; + + temp = ETH_ReadPHYRegister(addr,PHY_BCR); + temp &= ((uint16_t)~PHY_LOOPBACK); + + if(ETH_WritePHYRegister(addr,PHY_BCR,temp) == SET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/* MAC functions */ + +/*! + * @brief Enable the MAC transmission. + * + * @param None + * + * @retval None + */ +void ETH_EnableMACTransmission(void) +{ + ETH->CFG_B.TXEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC transmission. + * + * @param None + * + * @retval None + */ +void ETH_DisableMACTransmission(void) +{ + ETH->CFG_B.TXEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC receiver. + * + * @param None + * + * @retval None + */ +void ETH_EnableMACReceiver(void) +{ + ETH->CFG_B.RXEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC receiver. + * + * @param None + * + * @retval None + */ +void ETH_DisableMACReceiver(void) +{ + ETH->CFG_B.RXEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the ETH flow control busy status + * + * @param None + * + * @retval SET or RESET + */ +uint8_t ETH_ReadFlowControlBusyStatus(void) +{ + return ETH->FCTRL_B.FCTRLB; +} + +/*! + * @brief Set a Pause Control Frame (Full-duplex only). + * + * @param None + * + * @retval None + */ +void ETH_SetPauseControlFrame(void) +{ + ETH->FCTRL_B.FCTRLB = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC Back Pressure operation activation (Half-duplex only). + * + * @param None + * + * @retval None + */ +void ETH_EnableBackPressureActivation(void) +{ + ETH->FCTRL_B.FCTRLB = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Back Pressure operation activation (Half-duplex only). + * + * @param None + * + * @retval None + */ +void ETH_DisableBackPressureActivation(void) +{ + ETH->FCTRL_B.FCTRLB = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the specified ETH MAC flag + * + * @param flag: Ethernet MAC flag: + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag) +{ + return (ETH->ISTS & flag) ? SET : RESET; +} + +/*! + * @brief Enable the specified ETH MAC interrupts. + * + * @param interrupt: Ethernet MAC interrupt flag: + * This parameter can be any combination of the following values: + * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_INT_PMT : PMT interrupt + * + * @retval None + */ +void ETH_EnableMACInterrupt(uint32_t interrupt) +{ + ETH->IMASK |= interrupt; +} + +/*! + * @brief Disable the specified ETH MAC interrupts. + * + * @param interrupt: Ethernet MAC interrupt flag: + * This parameter can be any combination of the following values: + * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_INT_PMT : PMT interrupt + * + * @retval None + */ +void ETH_DisableMACInterrupt(uint32_t interrupt) +{ + ETH->IMASK &= (~(uint32_t)interrupt); +} + +/*! + * @brief Config the MAC address. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0 : MAC Address0 + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param addr: Pointer on MAC address buffer data (6 bytes). + * + * @retval None + */ +void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr) +{ + uint32_t temp; + + temp = ((uint32_t)addr[5] << 8) | (uint32_t)addr[4]; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp; + + temp = ((uint32_t)addr[3] << 24) | ((uint32_t)addr[2] << 16) | ((uint32_t)addr[1] << 8) | addr[0]; + (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + macAddr)) = temp; +} + +/*! + * @brief Read the MAC address. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0 : MAC Address0 + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param addr: Pointer on MAC address buffer data (6 bytes). + * + * @retval None + */ +void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr) +{ + uint32_t temp; + + temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)); + + addr[5] = ((temp >> 8) & 0xFF); + addr[4] = (temp & 0xFF); + + temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + macAddr)); + addr[3] = ((temp >> 24) & 0xFF); + addr[2] = ((temp >> 16) & 0xFF); + addr[1] = ((temp >> 8) & 0xFF); + addr[0] = (temp & 0xFF); +} + +/*! + * @brief Enable address filters module uses the MAC address for perfect filtering. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @retval None + */ +void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr) +{ + __IO uint32_t temp = 0; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= BIT31; + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp; +} + +/*! + * @brief Disable address filters module uses the MAC address for perfect filtering. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @retval None + */ +void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr) +{ + __IO uint32_t temp = 0; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) &= (~BIT31); + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp; +} + +/*! + * @brief Config the filter type for the MAC address + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param filter: Comparison with the SA/DA fields of the received frame. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESSFILTER_SA : MAC Address is used to compare with the + * SA fields of the received frame. + * @arg ETH_MAC_ADDRESSFILTER_DA : MAC Address is used to compare with the + * DA fields of the received frame. + * @retval None + */ +void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter) +{ + if(filter == ETH_MAC_ADDRESSFILTER_SA) + { + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_SA; + } + else + { + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_DA; + } + +} + +/*! + * @brief Config the filter type for the ETH MAC address. + * + * @param macAddr: The MAC address. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1 : MAC Address1 + * @arg ETH_MAC_ADDRESS2 : MAC Address2 + * @arg ETH_MAC_ADDRESS3 : MAC Address3 + * + * @param MaskByte: specifies the used address bytes for comparison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_ADDRESSMASK_BYTE6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_ADDRESSMASK_BYTE5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_ADDRESSMASK_BYTE4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_ADDRESSMASK_BYTE3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_ADDRESSMASK_BYTE2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_ADDRESSMASK_BYTE1 : Mask MAC Address low reg bits [7:0]. + * + * @retval None + */ +void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte) +{ + __IO uint32_t temp = 0; + + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) &=(~(uint32_t)0x3F000000); + + temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)); + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp; + + /* Set the selected Filter mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= maskByte; + + temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)); + ETH_Delay(ETH_REG_WRITE_DELAY); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp; +} + +/** DMA Descriptors functions */ + +/*! + * @brief Config the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab: Pointer on the first Rx desc list + * + * @param rxBuff: Pointer on the first RxBuffer list + * + * @param rxBuffcount: Number of the used Rx desc in the list + * + * @retval None + */ +void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T *DMARxDescTab, uint8_t *rxBuff, uint32_t rxBuffcount) +{ + uint32_t i = 0; + ETH_DMADescConfig_T *DMARxDesc; + DMARxDescToGet = DMARxDescTab; + + for(i=0; i< rxBuffcount; i++) + { + DMARxDesc = DMARxDescTab+i; + DMARxDesc->Status = ETH_DMARXDESC_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RXCH | ETH_RX_BUF_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&rxBuff[i*ETH_RX_BUF_SIZE]); + if(i < (rxBuffcount-1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + + ETH->DMARXDLADDR = (uint32_t) DMARxDescTab; + DMARxFraminfos =&RxFrameDescriptor; +} + +/*! + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab: Pointer on the first Tx desc list + * + * @param txBuff: Pointer on the first TxBuffer list + * + * @param txBuffcount: Number of the used Tx desc in the list + * + * @retval None + */ +void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T *DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount) +{ + uint32_t i = 0; + ETH_DMADescConfig_T *DMATxDesc; + DMATxDescToSet = DMATxDescTab; + + for(i=0; i< txBuffcount; i++) + { + DMATxDesc = DMATxDescTab+i; + DMATxDesc->Status = ETH_DMATXDESC_TXCH; + DMATxDesc->Buffer1Addr = (uint32_t)(&txBuff[i*ETH_TX_BUF_SIZE]); + if(i < (txBuffcount-1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab); + } + } + + ETH->DMATXDLADDR = (uint32_t) DMATxDescTab; +} + +/*! + * @brief This function polls for a frame receiver + * + * @param None + * + * @retval Returns 1 when a frame is received, 0 if none. + */ +uint32_t ETH_CheckReceivedFrame(void) +{ + if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET)) + { + DMARxFraminfos->segCount++; + if(DMARxFraminfos->segCount == 1) + { + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + } + DMARxFraminfos->LS_RxDesc = DMARxDescToGet; + return 1; + } + else if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + DMARxFraminfos->LS_RxDesc = NULL; + DMARxFraminfos->segCount = 1; + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + (DMARxFraminfos->segCount) ++; + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + } + return 0; +} + +/*! + * @brief Prepares DMA Tx descriptors to transmit an ethernet frame + * + * @param FrameLength : length of the frame to send + * + * @retval ETH_ERROR or ETH_SUCCESS + */ +uint32_t ETH_Transmit_Descriptors(u16 frameLength) +{ + uint32_t count=0, size=0, i=0; + __IO ETH_DMADescConfig_T *DMATxDesc; + + if((DMATxDescToSet->Status & ETH_DMATXDESC_OWN) == SET) + { + return ETH_ERROR; + } + + DMATxDesc = DMATxDescToSet; + + if(frameLength > ETH_TX_BUF_SIZE) + { + count = frameLength/ETH_TX_BUF_SIZE; + if(frameLength%ETH_TX_BUF_SIZE) count++; + } + else count =1; + + if(count == 1) + { + DMATxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; + DMATxDesc->ControlBufferSize = (frameLength & ETH_DMATXDESC_TXBS1); + DMATxDesc->Status |= ETH_DMATXDESC_OWN; + DMATxDesc = (ETH_DMADescConfig_T*) (DMATxDesc->Buffer2NextDescAddr); + } + else + { + for(i=0; iStatus &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + + if(i==0) + { + DMATxDesc->Status |= ETH_DMATXDESC_FS; + } + DMATxDesc->ControlBufferSize =(ETH_TX_BUF_SIZE & ETH_DMATXDESC_TXBS1); + + if(i== (count-1)) + { + DMATxDesc->Status |= ETH_DMATXDESC_LS; + size = frameLength - (count-1)*ETH_TX_BUF_SIZE; + DMATxDesc->ControlBufferSize =(size & ETH_DMATXDESC_TXBS1); + } + + DMATxDesc->Status |= ETH_DMATXDESC_OWN; + DMATxDesc = (ETH_DMADescConfig_T*) (DMATxDesc->Buffer2NextDescAddr); + } + } + DMATxDescToSet = DMATxDesc; + + if(ETH->DMASTS_B.TXBU == SET) + { + ETH->DMASTS = BIT2; + ETH->DMATXPD = 0; + } + + return ETH_SUCCESS; +} + +/*! + * @brief Read the received frame. + * + * @param none + * + * @retval Structure of type ETH_Frame_T + */ +ETH_Frame_T ETH_ReadReceivedFrame(void) +{ + uint32_t frameLength = 0; + ETH_Frame_T frame = {0,0,0}; + + frameLength = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; + frame.length = frameLength; + + frame.descriptor = DMARxFraminfos->FS_RxDesc; + frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr; + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + + return(frame); +} + +/*! + * @brief Read ETH DMA Tx Descriptor flag. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param flag: Specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_OWN : Descriptor is owned by DMA engine + * @arg ETH_DMATXDESC_INTC : Interrupt on completion + * @arg ETH_DMATXDESC_LS : Last Segment + * @arg ETH_DMATXDESC_FS : First Segment + * @arg ETH_DMATXDESC_DISC : Disable CRC + * @arg ETH_DMATXDESC_DISP : Disable Pad + * @arg ETH_DMATXDESC_TXTSEN: Transmit Time Stamp Enable + * @arg ETH_DMATXDESC_TXENDR: Transmit End of Ring + * @arg ETH_DMATXDESC_TXCH : Second Address Chained + * @arg ETH_DMATXDESC_TXTSS : Tx Time Stamp Status + * @arg ETH_DMATXDESC_IHERR : IP Header Error + * @arg ETH_DMATXDESC_ERRS : Error summary + * @arg ETH_DMATXDESC_JTO : Jabber Timeout + * @arg ETH_DMATXDESC_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATXDESC_IPERR : Payload Checksum Error + * @arg ETH_DMATXDESC_LSC : Loss of Carrier: carrier lost during transmission + * @arg ETH_DMATXDESC_NC : No Carrier: no carrier signal from the transceiver + * @arg ETH_DMATXDESC_LC : Late Collision: transmission aborted due to collision + * @arg ETH_DMATXDESC_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATXDESC_VLANF : VLAN Frame + * @arg ETH_DMATXDESC_CCNT : Collision Count + * @arg ETH_DMATXDESC_EDEF : Excessive Deferral + * @arg ETH_DMATXDESC_UFERR : Underflow Error: late data arrival from the memory + * @arg ETH_DMATXDESC_DEF : Deferred Bit + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_FLAG_T flag) +{ + return (DMATxDesc->Status & flag) ? SET : RESET; +} + +/*! + * @brief Returns ETH DMA Tx Descriptor collision count. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval The Transmit descriptor collision counter value. + */ +uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T *DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATXDESC_CCNT) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/*! + * @brief Config the ETH DMA Tx Descriptor Own bit. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_OWN; +} + +/*! + * @brief Enable the ETH DMA Tx Descriptor Transmit interrupt. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_INTC; +} + +/*! + * @brief Disable the ETH DMA Tx Descriptor Transmit interrupt. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_INTC); +} + +/*! + * @brief Config Tx descriptor as last or first segment + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param frameSegment: Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_LASTSEGMENTS : Actual Tx desc contain last segment + * @arg ETH_DMATXDESC_FIRSTSEGMENT : Actual Tx desc contain first segment + * + * @retval None + */ +void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment) +{ + DMATxDesc->Status |= frameSegment; +} +/*! + * @brief Config ETH DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass + * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * + * @retval None + */ +void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum) +{ + DMATxDesc->Status |= checksum; +} + +/*! + * @brief Enable the DMA Tx Desc CRC. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISC); +} + +/*! + * @brief Disable the DMA Tx Desc CRC. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_DISC; +} + +/*! + * @brief Enable the DMA Tx Desc second address chained. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_TXCH; +} + +/*! + * @brief Disable the DMA Tx Desc second address chained. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATXDESC_TXCH); +} + +/*! + * @brief Enable the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISP); +} + +/*! + * @brief Disable the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @retval None + */ +void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATXDESC_DISP; +} + +/*! + * @brief Config the ETH DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc: pointer on a DMA Tx descriptor + * + * @param bufferSize1: specifies the Tx desc buffer1 size. + * + * @param bufferSize2: specifies the Tx desc buffer2 size. + * + * @retval None + */ +void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T *DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2) +{ + DMATxDesc->ControlBufferSize |= (bufferSize1 | (bufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/*! + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARXDESC_OWN : Descriptor is owned by DMA engine + * @arg ETH_DMARXDESC_ADDRF : DA Filter Fail for the rx frame + * @arg ETH_DMARXDESC_ERRS : Error summary + * @arg ETH_DMARXDESC_DESERR : Descriptor error: no more descriptors for receive frame + * @arg ETH_DMARXDESC_SADDRF : SA Filter Fail for the received frame + * @arg ETH_DMARXDESC_LERR : Frame size not matching with length field + * @arg ETH_DMARXDESC_OFERR : Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARXDESC_VLANF : VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARXDESC_FDES : First descriptor of the frame + * @arg ETH_DMARXDESC_LDES : Last descriptor of the frame + * @arg ETH_DMARXDESC_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARXDESC_LC : Late collision occurred during reception + * @arg ETH_DMARXDESC_FT : Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARXDESC_RXWDTTO: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARXDESC_RERR : Receive error: error reported by MII interface + * @arg ETH_DMARXDESC_DERR : Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARXDESC_CERR : CRC error + * @arg ETH_DMARXDESC_MAMPCE : Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_FLAG_T flag) +{ + return (DMARxDesc->Status & flag) ? SET : RESET; +} + +#if USE_ENHANCED_DMA_DESCRIPTORS +/*! + * @brief Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not. + * + * @param DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor + * + * @param flag: specifies the extended flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMAPTPRXDESC_PTPV : PTP version + * @arg ETH_DMAPTPRXDESC_PTPFT : PTP frame type + * @arg ETH_DMAPTPRXDESC_PTPMT : PTP message type + * @arg ETH_DMAPTPRXDESC_IPV6P : IPv6 packet received + * @arg ETH_DMAPTPRXDESC_IPV4P : IPv4 packet received + * @arg ETH_DMAPTPRXDESC_IPCBP : IP checksum bypassed + * @arg ETH_DMAPTPRXDESC_IPPERR: IP payload error + * @arg ETH_DMAPTPRXDESC_IPHERR: IP header error + * @arg ETH_DMAPTPRXDESC_IPPT : IP payload type + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAPTPRxDescExtendedFlagStatus(ETH_DMADescConfig_T *DMAPTPRxDesc, ETH_DMAPTPRXDESC_FLAG_T flag) +{ + return (DMAPTPRxDesc->Status & flag) ? SET : RESET; +} +#endif + +/*! + * @brief Config the ETH DMA Rx Desc Own bit. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval None + */ +void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T *DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARXDESC_OWN; +} + +/*! + * @brief Returns the ETH DMA Rx descriptor frame length. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval The Rx descriptor received frame length. + */ +uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T *DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/*! + * @brief Enable the ETH DMA Rx Desc receive interrupt. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval None + */ +void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMARxDesc) +{ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DINTC); +} + +/*! + * @brief Disable the ETH DMA Rx Desc receive interrupt. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @retval None + */ +void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMARxDesc) +{ + DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_DINTC; +} + +/*! + * @brief Returns the ETH DMA Rx Desc buffer size. + * + * @param DMARxDesc: pointer on a DMA Rx descriptor + * + * @param buffer: specifies the DMA Rx Desc buffer. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * + * @retval The Receive descriptor frame length. + */ +uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer) +{ + if(buffer == ETH_DMARXDESC_BUFFER1) + { + return (DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS1); + } + else + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } +} + +/*! + * @brief Read frame using DMA Receive interrupt. + * it allows scanning of Rx descriptors to get the the receive frame + * + * @param None + * + * @retval Structure of type ETH_Frame_T + */ +ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void) +{ + __IO uint32_t count = 0; + ETH_Frame_T frame = {0,0,0}; + + while (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)&& (count < ETH_RXBUFNB)) + { + count ++; + + if(((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)&& + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + DMARxFraminfos->segCount = 1; + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else if (((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET)&& + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET)) + { + (DMARxFraminfos->segCount) ++; + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + DMARxFraminfos->LS_RxDesc = DMARxDescToGet; + (DMARxFraminfos->segCount)++; + + if ((DMARxFraminfos->segCount)==1) + DMARxFraminfos->FS_RxDesc = DMARxDescToGet; + + frame.length = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; + + if(DMARxFraminfos->segCount >1) + { + frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr; + } + else + { + frame.buffer = DMARxDescToGet->Buffer1Addr; + } + + frame.descriptor = DMARxFraminfos->FS_RxDesc; + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + + return (frame); + } + } + return (frame); +} + +/** DMA functions */ + +/*! + * @brief Read the ETH DMA flag. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DATATRANSFERERROR : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_READWRITEERROR : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_ACCESSERROR : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RX : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_TX : Transmit flag + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag) +{ + return (ETH->DMASTS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the ETH DMA flag. + * + * @param flag: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RX : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_TX : Transmit flag + * + * @retval None + */ +void ETH_ClearDMAFlag(uint32_t flag) +{ + ETH->DMASTS = flag; +} + +/*! + * @brief Read the ETH DMA interrupt flag. + * + * @param flag: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_INT_PMT : PMT interrupt + * @arg ETH_DMA_INT_MMC : MMC interrupt + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Underflow interrupt + * @arg ETH_DMA_INT_RO : Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag) +{ + return (ETH->DMASTS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the ETH DMA interrupt flag. + * + * @param flag: specifies the interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_INT_RO : Receive Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval None + */ +void ETH_ClearDMAIntFlag(uint32_t flag) +{ + ETH->DMASTS = flag; +} + +/*! + * @brief Returns the ETH DMA Transmit Process State. + * + * @param None + + * @retval The new ETH DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TRANSMITPROCESS_STOPPED : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TRANSMITPROCESS_FETCHING : Running - fetching the Tx descriptor + * - ETH_DMA_TRANSMITPROCESS_WAITING : Running - waiting for status + * - ETH_DMA_TRANSMITPROCESS_READING : Running - reading the data from host memory + * - ETH_DMA_TRANSMITPROCESS_SUSPENDED : Suspended - Tx Descriptor unavailable + * - ETH_DMA_TRANSMITPROCESS_CLOSING : Running - closing Rx descriptor + */ +uint32_t ETH_ReadTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASTS & BIT0) ? SET : RESET); +} + +/*! + * @brief Returns the ETH DMA Receive Process State. + * + * @param None + * + * @retval The new ETH DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_RECEIVEPROCESS_STOPPED : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_RECEIVEPROCESS_FETCHING : Running - fetching the Rx descriptor + * - ETH_DMA_RECEIVEPROCESS_WAITING : Running - waiting for packet + * - ETH_DMA_RECEIVEPROCESS_SUSPENDED : Suspended - Rx Descriptor unavailable + * - ETH_DMA_RECEIVEPROCESS_CLOSING : Running - closing descriptor + * - ETH_DMA_RECEIVEPROCESS_QUEUING : Running - queuing the receive frame into host memory + */ +uint32_t ETH_ReadReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASTS & BIT6) ? SET : RESET); +} + +/*! + * @brief Flush the ETH transmit FIFO. + * + * @param None + * + * @retval None + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOPMOD_B.FTXF = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the ETH flush transmit FIFO status. + * + * @param None + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadFlushTransmitFIFOStatus(void) +{ + return ETH->DMAOPMOD_B.FTXF; +} + +/*! + * @brief Enable the DMA transmission. + * + * @param None + * + * @retval None + */ +void ETH_EnableDMATransmission(void) +{ + ETH->DMAOPMOD_B.STTX = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the DMA transmission. + * + * @param None + * + * @retval None + */ +void ETH_DisableDMATransmission(void) +{ + ETH->DMAOPMOD_B.STTX = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the DMA receiver. + * + * @param None + * + * @retval None + */ +void ETH_EnableDMAReceiver(void) +{ + ETH->DMAOPMOD_B.STRX = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the DMA receiver. + * + * @param None + * + * @retval None + */ +void ETH_DisableDMAReceiver(void) +{ + ETH->DMAOPMOD_B.STRX = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the ETH DMA interrupts. + * + * @param interrupt: specifies the ETH DMA interrupt sources. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Underflow interrupt + * @arg ETH_DMA_INT_RO : Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval None + */ +void ETH_EnableDMAInterrupt(uint32_t interrupt) +{ + ETH->DMAINTEN |= interrupt; +} + +/*! + * @brief Disable the ETH DMA interrupts. + * + * @param interrupt: specifies the ETH DMA interrupt sources. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_INT_NIS : Normal interrupt summary + * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_INT_ER : Early receive interrupt + * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_INT_ET : Early transmit interrupt + * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RX : Receive interrupt + * @arg ETH_DMA_INT_TU : Underflow interrupt + * @arg ETH_DMA_INT_RO : Overflow interrupt + * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_INT_TX : Transmit interrupt + * + * @retval None + */ +void ETH_DisableDMAInterrupt(uint32_t interrupt) +{ + ETH->DMAINTEN &= ((uint32_t)~interrupt); +} + +/*! + * @brief Read the ETH DMA overflow flag. + * + * @param overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter + * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow) +{ + return (ETH->DMAMFABOCNT & overflow) ? SET : RESET; +} + +/*! + * @brief Read the ETH DMA Rx Overflow Missed Frame Counter value. + * + * @param None + * + * @retval The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_ReadRxOverflowMissedFrameCounter(void) +{ + return (uint32_t)(ETH->DMAMFABOCNT_B.AMISFCNT); +} + +/*! + * @brief Read the ETH DMA Buffer Unavailable Missed Frame Counter value. + * + * @param None + * + * @retval The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void) +{ + return (uint32_t)(ETH->DMAMFABOCNT_B.MISFCNT); +} + +/*! + * @brief Read the ETH DMA DMAHTXD register value. + * + * @param None + * + * @retval The value of the current Tx desc start address. + */ +uint32_t ETH_ReadCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMAHTXD)); +} + +/*! + * @brief Read the ETHERNET DMA DMAHRXD register value. + * + * @param None + * + * @retval The value of the current Rx desc start address. + */ +uint32_t ETH_ReadCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMAHRXD)); +} + +/*! + * @brief Read the ETH DMA DMAHTXBADDR register value. + * + * @param None + * + * @retval The value of the current transmit descriptor data buffer address. + */ +uint32_t ETH_ReadCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMAHTXBADDR)); +} + +/*! + * @brief Read the ETH DMA DMAHRXBADDR register value. + * + * @param None + * + * @retval The value of the current receive descriptor data buffer address. + */ +uint32_t ETH_ReadCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMAHRXBADDR)); +} + +/*! + * @brief Reset the DMA Transmission by writing to the DmaTxPollDemand register + * + * @param None + + * @retval None. + */ +void ETH_ResetDMATransmission(void) +{ + ETH->DMATXPD = 0; +} + +/*! + * @brief Reset the DMA Transmission by writing to the DmaRxPollDemand register + * + * @param None + * + * @retval None. + */ +void ETH_ResetDMAReception(void) +{ + ETH->DMARXPD = 0; +} + +/*! + * @brief Config the DMA Receive status watchdog timer register value + * + * @param value: watchdog timer register value + * + * @retval None + */ +void ETH_ConfigReceiveWatchdogTimer(uint8_t value) +{ + ETH->DMARXFLGWDT_B.RXWDTCNT = value; +} + +/** Power Management(PMT) functions */ + +/*! + * @brief Reset Wakeup frame filter register pointer. + * + * @param None + * + * @retval None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->PMTCTRLSTS_B.WKUPFRST = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Populates the remote wakeup frame registers. + * + * @param buffer: WakeUp Frame Filter Register buffer data (8 words). + * + * @retval None + */ +void ETH_ConfigWakeUpFrameFilterRegister(uint32_t *buffer) +{ + uint32_t i = 0; + __IO uint32_t temp = 0; + + for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) + { + ETH->WKUPFFL = buffer[i]; + + temp = ETH->WKUPFFL; + ETH_Delay(ETH_REG_WRITE_DELAY); + ETH->WKUPFFL = temp; + } +} + +/*! + * @brief Enable any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * + * @retval None + */ +void ETH_EnableGlobalUnicastWakeUp(void) +{ + ETH->PMTCTRLSTS_B.GUN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * + * @retval None + */ +void ETH_DisableGlobalUnicastWakeUp(void) +{ + ETH->PMTCTRLSTS_B.GUN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Read the ETH PMT flag. + * + * @param flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag) +{ + return (ETH->PMTCTRLSTS & flag) ? SET : RESET; +} + +/*! + * @brief Enable the MAC Wake-Up Frame Detection. + * + * @param None + * + * @retval None + */ +void ETH_EnableWakeUpFrameDetection(void) +{ + ETH->PMTCTRLSTS_B.WKUPFEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Wake-Up Frame Detection. + * + * @param None + * + * @retval None + */ +void ETH_DisableWakeUpFrameDetection(void) +{ + ETH->PMTCTRLSTS_B.WKUPFEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC Magic Packet Detection. + * + * @param None + * + * @retval None + */ +void ETH_EnableMagicPacketDetection(void) +{ + ETH->PMTCTRLSTS_B.MPEN = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Magic Packet Detection. + * + * @param None + * + * @retval None + */ +void ETH_DisableMagicPacketDetection(void) +{ + ETH->PMTCTRLSTS_B.MPEN = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Enable the MAC Power Down. + * + * @param None + * + * @retval None + */ +void ETH_EnablePowerDown(void) +{ + ETH->PMTCTRLSTS_B.PD = SET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/*! + * @brief Disable the MAC Power Down. + * + * @param None + * + * @retval None + */ +void ETH_DisablePowerDown(void) +{ + ETH->PMTCTRLSTS_B.PD = RESET; + ETH_Delay(ETH_REG_WRITE_DELAY); +} + +/** MMC functions */ + +/** + * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) + * @param None + * @retval None + */ +void ETH_PresetMMCCounterFull(void) +{ + ETH->CTRL_B.MCNTP = SET; + ETH->CTRL_B.MCNTVALP = SET; +} + +/** + * @brief Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16) + * @param None + * @retval None + */ +void ETH_PresetMMCCounterHalf(void) +{ + ETH->CTRL_B.MCNTP = SET; + ETH->CTRL_B.MCNTVALP = RESET; +} + +/*! + * @brief Enable the MMC Counter Freeze. + * + * @param None + * + * @retval None + */ +void ETH_EnableMMCCounterFreeze(void) +{ + ETH->CTRL_B.MCNTF = SET; +} + +/*! + * @brief Disable the MMC Counter Freeze. + * + * @param None + * + * @retval None + */ +void ETH_DisableMMCCounterFreeze(void) +{ + ETH->CTRL_B.MCNTF = RESET; +} + +/*! + * @brief Enable the MMC Reset On Read. + * + * @param None + * + * @retval None + */ +void ETH_EnableMMCResetOnRead(void) +{ + ETH->CTRL_B.RSTOR = SET; +} + +/*! + * @brief Disable the MMC Reset On Read. + * + * @param None + * + * @retval None + */ +void ETH_DisableMMCResetOnRead(void) +{ + ETH->CTRL_B.RSTOR = RESET; +} + +/*! + * @brief Enble the MMC Counter Stop Rollover. + * + * @param None + * + * @retval None + */ +void ETH_EnableMMCCounterRollover(void) +{ + ETH->CTRL_B.CNTSTOPRO = RESET; +} + +/*! + * @brief Disable the MMC Counter Stop Rollover. + * + * @param None + * + * @retval None + */ +void ETH_DisableMMCCounterRollover(void) +{ + ETH->CTRL_B.CNTSTOPRO = SET; +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval None + */ +void ETH_ResetMMCCounters(void) +{ + ETH->CTRL_B.CNTRST = SET; +} + +/*! + * @brief Enable the ETH MMC interrupts. + * + * @param interrupt: specifies the ETH MMC interrupt sources. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_INT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RFCE : When Rx crc error counter reaches half the maximum value + * + * @retval None + */ +void ETH_EnableMMCInterrupt(uint32_t interrupt) +{ + if((interrupt & 0x10000000) == SET) + { + ETH->RXINTMASK &= (~(uint32_t)interrupt); + } + else + { + ETH->TXINTMASK &= (~(uint32_t)interrupt); + } +} + +/*! + * @brief Disable the ETH MMC interrupts. + * + * @param interrupt: specifies the ETH MMC interrupt sources. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_INT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RFCE : When Rx crc error counter reaches half the maximum value + * + * @retval None + */ +void ETH_DisableMMCInterrupt(uint32_t interrupt) +{ + if((interrupt & 0x10000000) == SET) + { + ETH->RXINTMASK |= interrupt; + } + else + { + ETH->TXINTMASK |= interrupt; + } +} + +/*! + * @brief Read the ETH MMC interrupt flag. + * + * @param flag: specifies the ETH MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_INT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_INT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_INT_RFCE : When Rx crc error counter reaches half the maximum value + * + * @retval SET or RESET. + */ +uint8_t ETH_ReadMMCIntFlag(uint32_t flag) +{ + if((flag & 0x10000000) == SET) + { + return ((((ETH->RXINT & flag) != RESET)) && ((ETH->RXINTMASK & flag) == RESET)); + } + else + { + return ((((ETH->TXINT & flag) != RESET)) && ((ETH->TXINTMASK & flag) == RESET)); + } +} + +/*! + * @brief Read the ETH MMC register value. + * + * @param MMCReg: specifies the ETH MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMC_CTRL : MMC CTRL register + * @arg ETH_MMC_RXINT : MMC RXINT register + * @arg ETH_MMC_TXINT : MMC TXINT register + * @arg ETH_MMC_RXINTMASK : MMC RXINTMASK register + * @arg ETH_MMC_TXINTMASK : MMC TXINTMASK register + * @arg ETH_MMC_TXGFSCCNT : MMC TXGFSCCNT register + * @arg ETH_MMC_TXGFMCCNT : MMC TXGFMCCNT register + * @arg ETH_MMC_TXGFCNT : MMC TXGFCNT register + * @arg ETH_MMC_RXFCECNT : MMC RXFCECNT register + * @arg ETH_MMC_RXFAECNT : MMC RXFAECNT register + * @arg ETH_MMC_RXGUNCNT : MMC RXGUNCNT register + * + * @retval Return ETH MMC Register value. + */ +uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + MMCReg)); +} + +/**@} end of group ETH_Functions */ +/**@} end of group ETH_Driver */ +/**@} end of group APM32F4xx_ETHDriver */ diff --git a/bsp/apm32/libraries/APM32F4xx_Library/SConscript b/bsp/apm32/libraries/APM32F4xx_Library/SConscript index 8785ae70e9..74d77c1e55 100644 --- a/bsp/apm32/libraries/APM32F4xx_Library/SConscript +++ b/bsp/apm32/libraries/APM32F4xx_Library/SConscript @@ -9,6 +9,7 @@ cwd = GetCurrentDir() src = Split(""" Device/Geehy/APM32F4xx/Source/system_apm32f4xx.c APM32F4xx_StdPeriphDriver/src/apm32f4xx_gpio.c +APM32F4xx_StdPeriphDriver/src/apm32f4xx_syscfg.c APM32F4xx_StdPeriphDriver/src/apm32f4xx_misc.c APM32F4xx_StdPeriphDriver/src/apm32f4xx_rcm.c APM32F4xx_StdPeriphDriver/src/apm32f4xx_usart.c @@ -35,9 +36,13 @@ if GetDepend(['RT_USING_WDT']): src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_wwdt.c'] src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_iwdt.c'] +if GetDepend(['BSP_USING_ETH']): + src += ['APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c'] + path = [cwd + '/Device/Geehy/APM32F4xx/Include', cwd + '/APM32F4xx_StdPeriphDriver/inc', - cwd + '/CMSIS/Include'] + cwd + '/CMSIS/Include', + cwd + '/APM32F4xx_ETH_Driver/inc'] CPPDEFINES = ['USE_STDPERIPH_DRIVER'] group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) diff --git a/bsp/apm32/libraries/Drivers/SConscript b/bsp/apm32/libraries/Drivers/SConscript index 61cdb7ab9b..128c5e3cd6 100644 --- a/bsp/apm32/libraries/Drivers/SConscript +++ b/bsp/apm32/libraries/Drivers/SConscript @@ -27,7 +27,8 @@ if GetDepend('BSP_USING_ONCHIP_RTC'): src += ['drv_rtc.c'] if GetDepend(['RT_USING_I2C']): - src += ['drv_soft_i2c.c'] + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] @@ -38,9 +39,12 @@ if GetDepend(['RT_USING_HWTIMER']): if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] -if GetDepend(['RT_USING_WDT']): +if GetDepend(['BSP_USING_WDT']): src += ['drv_wdt.c'] +if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']): + src += ['drv_eth.c'] + src += ['drv_common.c'] path = [cwd] diff --git a/bsp/apm32/libraries/Drivers/drv_adc.c b/bsp/apm32/libraries/Drivers/drv_adc.c index 40b796db06..8952bb8b14 100644 --- a/bsp/apm32/libraries/Drivers/drv_adc.c +++ b/bsp/apm32/libraries/Drivers/drv_adc.c @@ -7,22 +7,22 @@ * Date Author Notes * 2022-03-04 stevetong459 first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) -//#define DRV_DEBUG -#define LOG_TAG "drv.adc" +#define DBG_TAG "drv.adc" #define DBG_LVL DBG_INFO #include -#define DRV_ADC_CHANNEL_MAX_NUM 14 +#define DRV_ADC_CHANNEL_MAX_NUM 16 #define DRV_ADC_TIME_OUT 0xFFF -#define _ADC_GET_PORT(pin_num) ((GPIO_T *)(GPIOA_BASE + (0x400u * (((pin_num) >> 4) & 0xFu)))) -#define _ADC_GET_PIN(pin_num) ((uint16_t)(1u << ((pin_num) & 0xFu))) +#define APM32_ADC_GET_PORT(pin_num) ((GPIO_T *)(GPIOA_BASE + (0x400u * (((pin_num) >> 4) & 0xFu)))) +#define APM32_ADC_GET_PIN(pin_num) ((uint16_t)(1u << ((pin_num) & 0xFu))) struct apm32_adc { @@ -32,7 +32,8 @@ struct apm32_adc rt_base_t channel_pin[DRV_ADC_CHANNEL_MAX_NUM]; struct rt_adc_device adc_dev; }; -#ifdef APM32F10X_HD + +#if defined(SOC_SERIES_APM32F1) static struct apm32_adc adc_config[] = { #ifdef BSP_USING_ADC1 @@ -95,7 +96,7 @@ static struct apm32_adc adc_config[] = }, #endif }; -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) static struct apm32_adc adc_config[] = { #ifdef BSP_USING_ADC1 @@ -162,11 +163,37 @@ static struct apm32_adc adc_config[] = }, #endif }; +#elif defined(SOC_SERIES_APM32F0) +static struct apm32_adc adc_config[] = +{ +#ifdef BSP_USING_ADC1 + { + "adc1", + ADC, + { + ADC_RESOLUTION_12B, + ADC_DATA_ALIGN_RIGHT, + ADC_SCAN_DIR_UPWARD, + ADC_CONVERSION_SINGLE, + ADC_EXT_TRIG_CONV_TRG0, + ADC_EXT_TRIG_EDGE_NONE + }, + { + GET_PIN(A, 0), GET_PIN(A, 1), GET_PIN(A, 2), GET_PIN(A, 3), GET_PIN(A, 4), + GET_PIN(A, 5), GET_PIN(A, 6), GET_PIN(A, 7), GET_PIN(B, 0), GET_PIN(B, 1), + GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), + GET_PIN(C, 5) + }, + RT_NULL + }, #endif -static rt_err_t _adc_channel_check(struct rt_adc_device *device, rt_uint32_t channel) +}; +#endif + +static rt_err_t apm32_adc_channel_check(struct rt_adc_device *device, rt_uint32_t channel) { struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) if (adc_cfg->adc == ADC3) { if (channel <= 8) @@ -181,34 +208,42 @@ static rt_err_t _adc_channel_check(struct rt_adc_device *device, rt_uint32_t cha return RT_EOK; } } -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) if (channel <= 13) { return RT_EOK; } +#elif defined(SOC_SERIES_APM32F0) + if (channel <= 16) + { + return RT_EOK; + } #endif LOG_E("channel %d of %s is not supported.", channel, adc_cfg->name); return -RT_ERROR; } -static rt_err_t _adc_gpio_init(struct rt_adc_device *device, rt_uint32_t channel) +static rt_err_t apm32_adc_gpio_init(struct rt_adc_device *device, rt_uint32_t channel) { struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); GPIO_Config_T hw_gpio_config; - if (_adc_channel_check(device, channel) != RT_EOK) + if (apm32_adc_channel_check(device, channel) != RT_EOK) { return -RT_ERROR; } -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA << ((adc_cfg->channel_pin[channel] >> 4) & 0xFu)); hw_gpio_config.mode = GPIO_MODE_ANALOG; -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA << ((adc_cfg->channel_pin[channel] >> 4) & 0xFu)); hw_gpio_config.mode = GPIO_MODE_AN; +#elif defined(SOC_SERIES_APM32F0) + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA << ((adc_cfg->channel_pin[channel] >> 4) & 0xFu)); + hw_gpio_config.mode = GPIO_MODE_AN; #endif - hw_gpio_config.pin = _ADC_GET_PIN(adc_cfg->channel_pin[channel]); - GPIO_Config(_ADC_GET_PORT(adc_cfg->channel_pin[channel]), &hw_gpio_config); + hw_gpio_config.pin = APM32_ADC_GET_PIN(adc_cfg->channel_pin[channel]); + GPIO_Config(APM32_ADC_GET_PORT(adc_cfg->channel_pin[channel]), &hw_gpio_config); return RT_EOK; } @@ -224,12 +259,28 @@ static rt_err_t _adc_gpio_init(struct rt_adc_device *device, rt_uint32_t channel * * @return RT_EOK indicates successful enable or disable adc, other value indicates failed. */ -static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +static rt_err_t apm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) { struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); RT_ASSERT(device != RT_NULL); +#if defined(SOC_SERIES_APM32F0) + if (enabled) + { + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_ADC1); + if (apm32_adc_gpio_init(device, channel) != RT_EOK) + { + return -RT_ERROR; + } + ADC_Config(&adc_cfg->adc_config); + ADC_Enable(); + } + else + { + ADC_Disable(); + } +#else if (enabled) { if (adc_cfg->adc == ADC1) @@ -244,7 +295,7 @@ static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, { RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_ADC3); } - if (_adc_gpio_init(device, channel) != RT_EOK) + if (apm32_adc_gpio_init(device, channel) != RT_EOK) { return -RT_ERROR; } @@ -257,6 +308,7 @@ static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, { ADC_Disable(adc_cfg->adc); } +#endif return RT_EOK; } @@ -272,19 +324,22 @@ static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, * * @return RT_EOK indicates successful get adc value, other value indicates failed. */ -static rt_err_t _adc_get_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t apm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) { +#if !defined(SOC_SERIES_APM32F0) struct apm32_adc *adc_cfg = ((struct apm32_adc *)device->parent.user_data); +#endif volatile rt_uint32_t counter = 0; RT_ASSERT(device != RT_NULL); RT_ASSERT(value != RT_NULL); - if (_adc_channel_check(device, channel) != RT_EOK) + if (apm32_adc_channel_check(device, channel) != RT_EOK) { return -RT_ERROR; } -#ifdef APM32F10X_HD + +#if defined(SOC_SERIES_APM32F1) ADC_ConfigRegularChannel(adc_cfg->adc, channel, 1, ADC_SAMPLETIME_13CYCLES5); ADC_StartCalibration(adc_cfg->adc); @@ -298,11 +353,7 @@ static rt_err_t _adc_get_value(struct rt_adc_device *device, rt_uint32_t channel } ADC_EnableSoftwareStartConv(adc_cfg->adc); -#elif APM32F40X - ADC_ConfigRegularChannel(adc_cfg->adc, channel, 1, ADC_SAMPLETIME_15CYCLES); - ADC_SoftwareStartConv(adc_cfg->adc); -#endif - counter = 0; + while (!ADC_ReadStatusFlag(adc_cfg->adc, ADC_FLAG_EOC)) { if (++counter > DRV_ADC_TIME_OUT) @@ -310,16 +361,41 @@ static rt_err_t _adc_get_value(struct rt_adc_device *device, rt_uint32_t channel return RT_ETIMEOUT; } } - *value = ADC_ReadConversionValue(adc_cfg->adc); - +#elif defined(SOC_SERIES_APM32F4) + ADC_ConfigRegularChannel(adc_cfg->adc, channel, 1, ADC_SAMPLETIME_15CYCLES); + ADC_SoftwareStartConv(adc_cfg->adc); + + while (!ADC_ReadStatusFlag(adc_cfg->adc, ADC_FLAG_EOC)) + { + if (++counter > DRV_ADC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + *value = ADC_ReadConversionValue(adc_cfg->adc); +#elif defined(SOC_SERIES_APM32F0) + ADC_ConfigChannel((uint16_t)(1u << ((channel) & 0xFu)), ADC_SAMPLE_TIME_239_5); + + ADC_StartConversion(); + + while (!ADC_ReadStatusFlag(ADC_FLAG_CC)) + { + if (++counter > DRV_ADC_TIME_OUT) + { + return RT_ETIMEOUT; + } + } + *value = ADC_ReadConversionValue(); +#endif + return RT_EOK; } -static const struct rt_adc_ops _adc_ops = +static const struct rt_adc_ops apm32_adc_ops = { - .enabled = _adc_enabled, - .convert = _adc_get_value, + .enabled = apm32_adc_enabled, + .convert = apm32_adc_get_value, }; /** @@ -336,7 +412,7 @@ static int rt_hw_adc_init(void) for (i = 0; i < obj_num; i++) { /* register ADC device */ - if (rt_hw_adc_register(&adc_config[i].adc_dev, adc_config[i].name, &_adc_ops, adc_config)) + if (rt_hw_adc_register(&adc_config[i].adc_dev, adc_config[i].name, &apm32_adc_ops, &adc_config[i]) == RT_EOK) { LOG_D("%s init success", adc_config[i].name); } diff --git a/bsp/apm32/libraries/Drivers/drv_common.c b/bsp/apm32/libraries/Drivers/drv_common.c index 0e62a55ccf..9d04818f80 100644 --- a/bsp/apm32/libraries/Drivers/drv_common.c +++ b/bsp/apm32/libraries/Drivers/drv_common.c @@ -93,7 +93,7 @@ void rt_hw_us_delay(rt_uint32_t us) /** * This function will config the board for initialization. */ -rt_weak void rt_hw_board_init() +rt_weak void rt_hw_board_init(void) { /* Systick initialization */ rt_hw_systick_init(); diff --git a/bsp/apm32/libraries/Drivers/drv_dac.c b/bsp/apm32/libraries/Drivers/drv_dac.c index 0091b8ada4..c6d0bba057 100644 --- a/bsp/apm32/libraries/Drivers/drv_dac.c +++ b/bsp/apm32/libraries/Drivers/drv_dac.c @@ -7,14 +7,15 @@ * Date Author Notes * 2022-03-04 stevetong459 first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include #if defined(BSP_USING_DAC1) -#define LOG_TAG "drv.dac" -#define DBG_LVL DBG_INFO +#define DBG_TAG "drv.dac" +#define DBG_LVL DBG_LOG//DBG_INFO #include struct apm32_dac @@ -27,8 +28,20 @@ struct apm32_dac static struct apm32_dac dac_config[] = { -#if defined(BSP_USING_DAC1) + +#if defined (BSP_USING_DAC1) { +#if defined (SOC_SERIES_APM32F0) + "dac1", + DAC, + { + DAC_TRIGGER_SOFTWARE, + DAC_OUTPUTBUFF_DISABLE, + DAC_WAVE_GENERATION_NONE, + DAC_TRIANGLEAMPLITUDE_4095, + }, + RT_NULL, +#elif defined (SOC_SERIES_APM32F1) || defined (SOC_SERIES_APM32F4) "dac1", DAC, { @@ -37,7 +50,8 @@ static struct apm32_dac dac_config[] = DAC_WAVE_GENERATION_NONE, DAC_TRIANGLE_AMPLITUDE_4095, }, - RT_NULL + RT_NULL, +#endif } #endif }; @@ -51,16 +65,19 @@ static struct apm32_dac dac_config[] = * * @return RT_EOK indicates successful enable dac, other value indicates failed. */ -static rt_err_t _dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) +static rt_err_t apm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) { GPIO_Config_T GPIO_ConfigStruct; struct apm32_dac *cfg = (struct apm32_dac *)device->parent.user_data; -#ifdef APM32F10X_HD +#if defined (SOC_SERIES_APM32F1) RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); GPIO_ConfigStruct.mode = GPIO_MODE_ANALOG; -#elif APM32F40X +#elif defined (SOC_SERIES_APM32F4) RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA); GPIO_ConfigStruct.mode = GPIO_MODE_AN; +#elif defined (SOC_SERIES_APM32F0) + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA); + GPIO_ConfigStruct.mode = GPIO_MODE_AN; #endif if (channel == 1) { @@ -96,7 +113,7 @@ static rt_err_t _dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) * * @return RT_EOK indicates successful disable dac, other value indicates failed. */ -static rt_err_t _dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) +static rt_err_t apm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) { if (channel == 1) { @@ -126,8 +143,25 @@ static rt_err_t _dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) * * @return RT_EOK indicates successful set dac value, other value indicates failed. */ -static rt_err_t _dac_set_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t apm32_dac_set_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) { +#if defined (SOC_SERIES_APM32F0) + if (channel == 1) + { + DAC_ConfigChannel1Data(DAC_ALIGN_12B_R, *value); + DAC_EnableSoftwareTrigger(DAC_CHANNEL_1); + } + else if (channel == 2) + { + DAC_ConfigChannel2Data(DAC_ALIGN_12B_R, *value); + DAC_EnableSoftwareTrigger(DAC_CHANNEL_2); + } + else + { + LOG_E("dac channel must be 1 or 2."); + return -RT_ERROR; + } +#elif defined (SOC_SERIES_APM32F1) || defined (SOC_SERIES_APM32F4) if (channel == 1) { DAC_ConfigChannel1Data(DAC_ALIGN_12BIT_R, *value); @@ -143,15 +177,15 @@ static rt_err_t _dac_set_value(struct rt_dac_device *device, rt_uint32_t channel LOG_E("dac channel must be 1 or 2."); return -RT_ERROR; } - +#endif return RT_EOK; } -static const struct rt_dac_ops _dac_ops = +static const struct rt_dac_ops apm32_dac_ops = { - .disabled = _dac_disabled, - .enabled = _dac_enabled, - .convert = _dac_set_value, + .disabled = apm32_dac_disabled, + .enabled = apm32_dac_enabled, + .convert = apm32_dac_set_value, }; /** @@ -170,7 +204,7 @@ static int rt_hw_dac_init(void) for (i = 0; i < obj_num; i++) { /* register dac device */ - if (rt_hw_dac_register(&dac_config[i].dac_dev, dac_config[i].name, &_dac_ops, dac_config) == RT_EOK) + if (rt_hw_dac_register(&dac_config[i].dac_dev, dac_config[i].name, &apm32_dac_ops, dac_config) == RT_EOK) { LOG_D("%s init success", dac_config[i].name); } diff --git a/bsp/apm32/libraries/Drivers/drv_eth.c b/bsp/apm32/libraries/Drivers/drv_eth.c new file mode 100644 index 0000000000..4936b7be14 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_eth.c @@ -0,0 +1,766 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-20 luobeihai first version + */ + +#include + +#ifdef BSP_USING_ETH + +#include +#include +#include +#include "lwipopts.h" + +/* debug option */ +//#define DRV_DEBUG +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP +#define LOG_TAG "drv.emac" +#include "drv_eth.h" + +/* Global pointers on Tx and Rx descriptor used to transmit and receive descriptors */ +extern ETH_DMADescConfig_T *DMATxDescToSet, *DMARxDescToGet; + +/* Ethernet Rx & Tx DMA Descriptors */ +static ETH_DMADescConfig_T DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; +/* Ethernet Receive and Transmit buffers */ +static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE]; +/* phy address */ +static uint8_t phy_addr = 0xFF; + +#define MAX_ADDR_LEN 6 +struct rt_apm32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; + + rt_timer_t poll_link_timer; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + + uint32_t ETH_Speed; /*!< @ref ETH_Speed */ + uint32_t ETH_Mode; /*!< @ref ETH_Duplex_Mode */ + + uint32_t ETH_HashTableHigh; + uint32_t ETH_HashTableLow; +}; +static struct rt_apm32_eth apm32_eth_device; +static struct rt_semaphore tx_wait; +static rt_bool_t tx_is_waiting = RT_FALSE; + +#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + int i, j; + + for (i = 0; i < buflen; i += 16) + { + rt_kprintf("%08X: ", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%02X ", buf[i + j]); + else + rt_kprintf(" "); + rt_kprintf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + rt_kprintf("\n"); + } +} +#endif + +/* interrupt service routine */ +void ETH_IRQHandler(void) +{ + rt_uint32_t status, ier; + + /* enter interrupt */ + rt_interrupt_enter(); + + /* ETH DMA status registor */ + status = ETH->DMASTS; + /* ETH DMA interrupt resgitor */ + ier = ETH->DMAINTEN; + + if(status & ETH_DMA_INT_MMC) + { + ETH_ClearDMAIntFlag(ETH_DMA_INT_MMC); + } + + if(status & ETH_DMA_INT_NIS) + { + rt_uint32_t nis_clear = ETH_DMA_INT_NIS; + + /* [0]:Transmit Interrupt. */ + if((status & ier) & ETH_DMA_INT_TX) /* packet transmission */ + { + if (tx_is_waiting == RT_TRUE) + { + tx_is_waiting = RT_FALSE; + rt_sem_release(&tx_wait); + } + + nis_clear |= ETH_DMA_INT_TX; + } + + /* [2]:Transmit Buffer Unavailable. */ + + /* [6]:Receive Interrupt. */ + if((status & ier) & ETH_DMA_INT_RX) /* packet reception */ + { + /* a frame has been received */ + eth_device_ready(&(apm32_eth_device.parent)); + + nis_clear |= ETH_DMA_INT_RX; + } + + /* [14]:Early Receive Interrupt. */ + + ETH_ClearDMAIntFlag(nis_clear); + } + + if(status & ETH_DMA_INT_AIS) + { + rt_uint32_t ais_clear = ETH_DMA_INT_AIS; + + /* [1]:Transmit Process Stopped. */ + if(status & ETH_DMA_INT_TPS) + { + ais_clear |= ETH_DMA_INT_TPS; + } + + /* [3]:Transmit Jabber Timeout. */ + if(status & ETH_DMA_INT_TJT) + { + ais_clear |= ETH_DMA_INT_TJT; + } + + /* [4]: Receive FIFO Overflow. */ + if(status & ETH_DMA_INT_RO) + { + ais_clear |= ETH_DMA_INT_RO; + } + + /* [5]: Transmit Underflow. */ + if(status & ETH_DMA_INT_TU) + { + ais_clear |= ETH_DMA_INT_TU; + } + + /* [7]: Receive Buffer Unavailable. */ + if(status & ETH_DMA_INT_RBU) + { + ais_clear |= ETH_DMA_INT_RBU; + } + + /* [8]: Receive Process Stopped. */ + if(status & ETH_DMA_INT_RPS) + { + ais_clear |= ETH_DMA_INT_RPS; + } + + /* [9]: Receive Watchdog Timeout. */ + if(status & ETH_DMA_INT_RWT) + { + ais_clear |= ETH_DMA_INT_RWT; + } + + /* [10]: Early Transmit Interrupt. */ + + /* [13]: Fatal Bus Error. */ + if(status & ETH_DMA_INT_FBE) + { + ais_clear |= ETH_DMA_INT_FBE; + } + + ETH_ClearDMAIntFlag(ais_clear); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if (LWIP_IPV4 && LWIP_IGMP) || (LWIP_IPV6 && LWIP_IPV6_MLD) +/* polynomial: 0x04C11DB7 */ +static uint32_t ethcrc(const uint8_t *data, size_t length) +{ + uint32_t crc = 0xffffffff; + size_t i; + int j; + + for (i = 0; i < length; i++) + { + for (j = 0; j < 8; j++) + { + if (((crc >> 31) ^ (data[i] >> j)) & 0x01) + { + /* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ + crc = (crc << 1) ^ 0x04C11DB7; + } + else + { + crc = crc << 1; + } + } + } + + return ~crc; +} + +#define HASH_BITS 6 /* #bits in hash */ +static void register_multicast_address(struct rt_apm32_eth *apm32_eth, const uint8_t *mac) +{ + uint32_t crc; + uint8_t hash; + + /* calculate crc32 value of mac address */ + crc = ethcrc(mac, 6); + + /* only upper 6 bits (HASH_BITS) are used + * which point to specific bit in he hash registers + */ + hash = (crc >> 26) & 0x3F; + //rt_kprintf("register_multicast_address crc: %08X hash: %02X\n", crc, hash); + + if (hash > 31) + { + apm32_eth->ETH_HashTableHigh |= 1 << (hash - 32); + ETH->HTH = apm32_eth->ETH_HashTableHigh; + } + else + { + apm32_eth->ETH_HashTableLow |= 1 << hash; + ETH->HTL = apm32_eth->ETH_HashTableLow; + } +} +#endif /* (LWIP_IPV4 && LWIP_IGMP) || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_IPV4 && LWIP_IGMP +static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action ) +{ + uint8_t mac[6]; + const uint8_t *p = (const uint8_t *)ip4_addr; + struct rt_apm32_eth *apm32_eth = (struct rt_apm32_eth *)netif->state; + + mac[0] = 0x01; + mac[1] = 0x00; + mac[2] = 0x5E; + mac[3] = *(p+1) & 0x7F; + mac[4] = *(p+2); + mac[5] = *(p+3); + + register_multicast_address(apm32_eth, mac); + + if(1) + { + rt_kprintf("%s %s %s ", __FUNCTION__, (action==NETIF_ADD_MAC_FILTER)?"add":"del", ip4addr_ntoa(ip4_addr)); + rt_kprintf("%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + return 0; +} +#endif /* LWIP_IPV4 && LWIP_IGMP */ + +#if LWIP_IPV6 && LWIP_IPV6_MLD +static err_t mld_mac_filter( struct netif *netif, const ip6_addr_t *ip6_addr, enum netif_mac_filter_action action ) +{ + uint8_t mac[6]; + const uint8_t *p = (const uint8_t *)&ip6_addr->addr[3]; + struct rt_apm32_eth *apm32_eth = (struct rt_apm32_eth *)netif->state; + + mac[0] = 0x33; + mac[1] = 0x33; + mac[2] = *(p+0); + mac[3] = *(p+1); + mac[4] = *(p+2); + mac[5] = *(p+3); + + register_multicast_address(apm32_eth, mac); + + if(1) + { + rt_kprintf("%s %s %s ", __FUNCTION__, (action==NETIF_ADD_MAC_FILTER)?"add":"del", ip6addr_ntoa(ip6_addr)); + rt_kprintf("%02X:%02X:%02X:%02X:%02X:%02X\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } + + return 0; +} +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + +/* initialize the interface */ +static rt_err_t rt_apm32_eth_init(rt_device_t dev) +{ + struct rt_apm32_eth * apm32_eth = (struct rt_apm32_eth *)dev; + ETH_Config_T ETH_InitStructure; + + /* Enable ETHERNET clock */ + RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_ETH_MAC | RCM_AHB1_PERIPH_ETH_MAC_Tx | + RCM_AHB1_PERIPH_ETH_MAC_Rx); + + /* Reset ETHERNET on AHB Bus */ + ETH_Reset(); + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + while(ETH_ReadSoftwareReset() == SET); + + /* ETHERNET Configuration --------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_ConfigStructInit(Ð_InitStructure); + + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.autoNegotiation = ETH_AUTONEGOTIATION_ENABLE; + ETH_InitStructure.speed = (ETH_SPEED_T)apm32_eth->ETH_Speed; + ETH_InitStructure.mode = (ETH_MODE_T)apm32_eth->ETH_Mode; + + ETH_InitStructure.loopbackMode = ETH_LOOPBACKMODE_DISABLE; + ETH_InitStructure.retryTransmission = ETH_RETRYTRANSMISSION_DISABLE; + ETH_InitStructure.automaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + ETH_InitStructure.receiveAll = ETH_RECEIVEAll_DISABLE; + ETH_InitStructure.broadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; + ETH_InitStructure.promiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + ETH_InitStructure.multicastFramesFilter = ETH_MULTICASTFRAMESFILTER_HASHTABLE; + ETH_InitStructure.hashTableHigh = apm32_eth->ETH_HashTableHigh; + ETH_InitStructure.hashTableLow = apm32_eth->ETH_HashTableLow; + ETH_InitStructure.unicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; +#ifdef HARDWARE_CHECKSUM + ETH_InitStructure.checksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; +#endif + + /*------------------------ DMA -----------------------------------*/ + + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ + ETH_InitStructure.dropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; + ETH_InitStructure.receiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + ETH_InitStructure.flushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_DISABLE; + ETH_InitStructure.transmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + + ETH_InitStructure.forwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + ETH_InitStructure.forwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + ETH_InitStructure.secondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; + ETH_InitStructure.addressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + ETH_InitStructure.fixedBurst = ETH_FIXEDBURST_ENABLE; + ETH_InitStructure.rxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + ETH_InitStructure.txDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + ETH_InitStructure.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1; + + /* configure Ethernet */ + ETH_Config(Ð_InitStructure, phy_addr); + + /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ + ETH_EnableDMAInterrupt(ETH_DMA_INT_NIS | ETH_DMA_INT_RX | ETH_DMA_INT_TX); + NVIC_EnableIRQ(ETH_IRQn); + + /* Initialize Tx Descriptors list: Chain Mode */ + ETH_ConfigDMATxDescChain(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); + /* Initialize Rx Descriptors list: Chain Mode */ + ETH_ConfigDMARxDescChain(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); + + /* MAC address configuration */ + ETH_ConfigMACAddress(ETH_MAC_ADDRESS0, (u8*)&apm32_eth_device.dev_addr[0]); + + /* Enable MAC and DMA transmission and reception */ + ETH_Start(); + +#if LWIP_IPV4 && LWIP_IGMP + netif_set_igmp_mac_filter(apm32_eth->parent.netif, igmp_mac_filter); +#endif /* LWIP_IPV4 && LWIP_IGMP */ + +#if LWIP_IPV6 && LWIP_IPV6_MLD + netif_set_mld_mac_filter(apm32_eth->parent.netif, mld_mac_filter); +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + + return RT_EOK; +} + +static rt_err_t rt_apm32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_apm32_eth_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_apm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_apm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_apm32_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, apm32_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* ethernet device interface */ +/* transmit packet. */ +rt_err_t rt_apm32_eth_tx( rt_device_t dev, struct pbuf* p) +{ + struct pbuf* q; + rt_uint32_t offset; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + while ((DMATxDescToSet->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) + { + rt_err_t result; + rt_uint32_t level; + + level = rt_hw_interrupt_disable(); + tx_is_waiting = RT_TRUE; + rt_hw_interrupt_enable(level); + + /* it's own bit set, wait it */ + result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER); + if (result == RT_EOK) break; + if (result == -RT_ERROR) return -RT_ERROR; + } + + offset = 0; + for (q = p; q != NULL; q = q->next) + { + uint8_t *to; + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + to = (uint8_t*)((DMATxDescToSet->Buffer1Addr) + offset); + memcpy(to, q->payload, q->len); + offset += q->len; + } +#ifdef ETH_TX_DUMP + rt_kprintf("tx_dump, len:%d\r\n", p->tot_len); + dump_hex((rt_uint8_t*)(DMATxDescToSet->Buffer1Addr), p->tot_len); +#endif + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATXDESC_TXBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATXDESC_LS | ETH_DMATXDESC_FS; + /* Enable TX Completion Interrupt */ + DMATxDescToSet->Status |= ETH_DMATXDESC_INTC; +#ifdef CHECKSUM_BY_HARDWARE + DMATxDescToSet->Status |= ETH_DMATxDesc_ChecksumTCPUDPICMPFull; + /* clean ICMP checksum APM32F need */ + { + struct eth_hdr *ethhdr = (struct eth_hdr *)(DMATxDescToSet->Buffer1Addr); + /* is IP ? */ + if( ethhdr->type == htons(ETHTYPE_IP) ) + { + struct ip_hdr *iphdr = (struct ip_hdr *)(DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR); + /* is ICMP ? */ + if( IPH_PROTO(iphdr) == IP_PROTO_ICMP ) + { + struct icmp_echo_hdr *iecho = (struct icmp_echo_hdr *)(DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR + sizeof(struct ip_hdr) ); + iecho->chksum = 0; + } + } + } +#endif + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATXDESC_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASTS & BIT2) != (u32)RESET) + { + /** Clear TBUS ETHERNET DMA flag */ + ETH->DMASTS = BIT2; + /** Resume DMA transmission*/ + ETH->DMATXPD = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADescConfig_T*) (DMATxDescToSet->Buffer2NextDescAddr); + + /* Return SUCCESS */ + return RT_EOK; +} + +/* reception packet. */ +struct pbuf *rt_apm32_eth_rx(rt_device_t dev) +{ + struct pbuf* p; + rt_uint32_t offset = 0, framelength = 0; + + /* init p pointer */ + p = RT_NULL; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) != (uint32_t)RESET)) + return p; + + if (((DMARxDescToGet->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf* q; + + for (q = p; q != RT_NULL; q= q->next) + { + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + memcpy(q->payload, (uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset), q->len); + offset += q->len; + } +#ifdef ETH_RX_DUMP + rt_kprintf("rx_dump, len:%d\r\n", p->tot_len); + dump_hex((rt_uint8_t*)(DMARxDescToGet->Buffer1Addr), p->tot_len); +#endif + } + } + + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARXDESC_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASTS & BIT7) != (u32)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASTS = BIT7; + /* Resume DMA reception */ + ETH->DMARXPD = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARXDESC_RXCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARXDESC_RXER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADescConfig_T*) (ETH->DMARXDLADDR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADescConfig_T*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMOD & 0x0000007C) >> 2)); + } + } + + return p; +} + +enum { + PHY_LINK_MASK = (1 << 0), + PHY_100M_MASK = (1 << 1), + PHY_DUPLEX_MASK = (1 << 2), +}; + +static void phy_linkchange(void) +{ + uint8_t phy_speed_new = 0; + static uint8_t phy_speed = 0; + uint16_t status = ETH_ReadPHYRegister(phy_addr, PHY_BSR); + + LOG_D("phy basic status reg is 0x%X", status); + + if(status & (PHY_AUTONEGO_COMPLETE | PHY_LINKED_STATUS)) + { + uint16_t SR; + + phy_speed_new |= PHY_LINK_MASK; + + SR = ETH_ReadPHYRegister(phy_addr, PHY_Status_REG); + LOG_D("phy control status reg is 0x%X", SR); + + if (PHY_Status_SPEED_100M(SR)) + { + phy_speed_new |= PHY_100M_MASK; + } + + if (PHY_Status_FULL_DUPLEX(SR)) + { + phy_speed_new |= PHY_DUPLEX_MASK; + } + } + + /* linkchange */ + if(phy_speed_new != phy_speed) + { + if(phy_speed_new & PHY_LINK_MASK) + { + LOG_D("link up "); + + if(phy_speed_new & PHY_100M_MASK) + { + LOG_D("100Mbps"); + apm32_eth_device.ETH_Speed = ETH_SPEED_100M; + } + else + { + apm32_eth_device.ETH_Speed = ETH_SPEED_10M; + LOG_D("10Mbps"); + } + + if(phy_speed_new & PHY_DUPLEX_MASK) + { + LOG_D("full-duplex\r\n"); + apm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX; + } + else + { + LOG_D("half-duplex\r\n"); + apm32_eth_device.ETH_Mode = ETH_MODE_HALFDUPLEX; + } + rt_apm32_eth_init((rt_device_t)&apm32_eth_device); + + /* send link up. */ + eth_device_linkchange(&apm32_eth_device.parent, RT_TRUE); + } /* link up. */ + else + { + LOG_I("link down\r\n"); + /* send link down. */ + eth_device_linkchange(&apm32_eth_device.parent, RT_FALSE); + } /* link down. */ + + phy_speed = phy_speed_new; + } /* linkchange */ +} + +static void phy_monitor_thread_entry(void *parameter) +{ + uint8_t detected_count = 0; + + while(phy_addr == 0xFF) + { + /* phy search */ + rt_uint32_t i, temp; + for (i = 0; i <= 0x1F; i++) + { + temp = ETH_ReadPHYRegister(i, PHY_ID1_REG); + + if (temp != 0xFFFF && temp != 0x00) + { + phy_addr = i; + break; + } + } + + detected_count++; + rt_thread_mdelay(1000); + + if (detected_count > 10) + { + LOG_E("No PHY device was detected, please check hardware!"); + } + } + + LOG_D("Found a phy, address:0x%02X", phy_addr); + + /* RESET PHY */ + LOG_D("RESET PHY!\r\n"); + ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_RESET); + rt_thread_delay(RT_TICK_PER_SECOND * 2); + ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AUTONEGOTIATION); + + phy_linkchange(); + + apm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange, + NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); + if (!apm32_eth_device.poll_link_timer || rt_timer_start(apm32_eth_device.poll_link_timer) != RT_EOK) + { + LOG_E("Start link change detection timer failed"); + } +} + +static int rt_hw_apm32_eth_init(void) +{ + extern void phy_reset(void); + phy_reset(); + + void ETH_GPIO_Configuration(void); + ETH_GPIO_Configuration(); + + apm32_eth_device.ETH_Speed = ETH_SPEED_100M; + apm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX; + + /* set mac address. */ + apm32_eth_device.dev_addr[0] = 0x00; + apm32_eth_device.dev_addr[1] = 0x00; + apm32_eth_device.dev_addr[2] = 0x00; + apm32_eth_device.dev_addr[3] = 0x00; + apm32_eth_device.dev_addr[4] = 0x00; + apm32_eth_device.dev_addr[5] = 0x08; + + apm32_eth_device.parent.parent.init = rt_apm32_eth_init; + apm32_eth_device.parent.parent.open = rt_apm32_eth_open; + apm32_eth_device.parent.parent.close = rt_apm32_eth_close; + apm32_eth_device.parent.parent.read = rt_apm32_eth_read; + apm32_eth_device.parent.parent.write = rt_apm32_eth_write; + apm32_eth_device.parent.parent.control = rt_apm32_eth_control; + apm32_eth_device.parent.parent.user_data = RT_NULL; + + apm32_eth_device.parent.eth_rx = rt_apm32_eth_rx; + apm32_eth_device.parent.eth_tx = rt_apm32_eth_tx; + + /* init tx semaphore */ + rt_sem_init(&tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); + + /* register eth device */ + eth_device_init(&(apm32_eth_device.parent), "e0"); + + /* start phy monitor */ + { + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + rt_thread_startup(tid); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_apm32_eth_init); + +#endif /* BSP_USING_ETH */ diff --git a/bsp/apm32/libraries/Drivers/drv_eth.h b/bsp/apm32/libraries/Drivers/drv_eth.h new file mode 100644 index 0000000000..9d70f5be46 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_eth.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-20 luobeihai first version + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +#include +#include +#include +#include + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include + + +/* The PHY ID one register */ +#define PHY_ID1_REG 0x02U + + +#ifdef PHY_USING_LAN8720A +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x1DU +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x1EU +#define PHY_LINK_DOWN_MASK (1<<4) +#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) + +/* The PHY status register. */ +#define PHY_Status_REG 0x1FU +#define PHY_10M_MASK (1<<2) +#define PHY_100M_MASK (1<<3) +#define PHY_FULL_DUPLEX_MASK (1<<4) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) + +#elif defined(PHY_USING_DM9161CEP) +#define PHY_Status_REG 0x11U +#define PHY_10M_MASK ((1<<12) || (1<<13)) +#define PHY_100M_MASK ((1<<14) || (1<<15)) +#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13)) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x15U +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x15U +#define PHY_LINK_CHANGE_FLAG (1<<2) +#define PHY_LINK_CHANGE_MASK (1<<9) +#define PHY_INT_MASK 0 + +#elif defined(PHY_USING_DP83848C) +#define PHY_Status_REG 0x10U +#define PHY_10M_MASK (1<<1) +#define PHY_FULL_DUPLEX_MASK (1<<2) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr)) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x12U +#define PHY_LINK_CHANGE_FLAG (1<<13) +/* The PHY interrupt control register. */ +#define PHY_INTERRUPT_CTRL_REG 0x11U +#define PHY_INTERRUPT_EN ((1<<0)|(1<<1)) +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x12U +#define PHY_INT_MASK (1<<5) +#endif + +#ifdef PHY_USING_LAN8742A +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG 0x1DU +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG 0x1EU +#define PHY_LINK_DOWN_MASK (1<<4) +#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) + +/* The PHY status register. */ +#define PHY_Status_REG 0x1FU +#define PHY_10M_MASK (1<<2) +#define PHY_100M_MASK (1<<3) +#define PHY_FULL_DUPLEX_MASK (1<<4) +#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) +#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) +#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) +#endif /* PHY_USING_LAN8742A */ + +#endif /* __DRV_ETH_H__ */ diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.c b/bsp/apm32/libraries/Drivers/drv_gpio.c index eb3f8e3ed3..3e3e14907b 100644 --- a/bsp/apm32/libraries/Drivers/drv_gpio.c +++ b/bsp/apm32/libraries/Drivers/drv_gpio.c @@ -7,6 +7,7 @@ * Date Author Notes * 2020-08-20 Abbcc first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include @@ -19,7 +20,6 @@ #define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) #define PIN_APMPORT(pin) ((GPIO_T *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) - #define PIN_APMPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) #if defined(GPIOZ) @@ -55,6 +55,24 @@ static const struct pin_irq_map pin_irq_map[] = { +#if defined(SOC_SERIES_APM32F0) + {GPIO_PIN_0, EINT0_1_IRQn}, + {GPIO_PIN_1, EINT0_1_IRQn}, + {GPIO_PIN_2, EINT2_3_IRQn}, + {GPIO_PIN_3, EINT2_3_IRQn}, + {GPIO_PIN_4, EINT4_15_IRQn}, + {GPIO_PIN_5, EINT4_15_IRQn}, + {GPIO_PIN_6, EINT4_15_IRQn}, + {GPIO_PIN_7, EINT4_15_IRQn}, + {GPIO_PIN_8, EINT4_15_IRQn}, + {GPIO_PIN_9, EINT4_15_IRQn}, + {GPIO_PIN_10, EINT4_15_IRQn}, + {GPIO_PIN_11, EINT4_15_IRQn}, + {GPIO_PIN_12, EINT4_15_IRQn}, + {GPIO_PIN_13, EINT4_15_IRQn}, + {GPIO_PIN_14, EINT4_15_IRQn}, + {GPIO_PIN_15, EINT4_15_IRQn}, +#else {GPIO_PIN_0, EINT0_IRQn}, {GPIO_PIN_1, EINT1_IRQn}, {GPIO_PIN_2, EINT2_IRQn}, @@ -71,6 +89,7 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_PIN_13, EINT15_10_IRQn}, {GPIO_PIN_14, EINT15_10_IRQn}, {GPIO_PIN_15, EINT15_10_IRQn}, +#endif }; static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = @@ -96,7 +115,7 @@ static uint32_t pin_irq_enable_mask = 0; #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -static rt_base_t _pin_get(const char *name) +static rt_base_t apm32_pin_get(const char *name) { rt_base_t pin = 0; int hw_port_num, hw_pin_num = 0; @@ -133,7 +152,7 @@ static rt_base_t _pin_get(const char *name) return pin; } -static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { GPIO_T *gpio_port; uint16_t gpio_pin; @@ -142,12 +161,15 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { gpio_port = PIN_APMPORT(pin); gpio_pin = PIN_APMPIN(pin); - +#if defined(SOC_SERIES_APM32F0) + GPIO_WriteBitValue(gpio_port, gpio_pin, (GPIO_BSRET_T)value); +#else GPIO_WriteBitValue(gpio_port, gpio_pin, (uint8_t)value); +#endif } } -static int _pin_read(rt_device_t dev, rt_base_t pin) +static int apm32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_T *gpio_port; uint16_t gpio_pin; @@ -163,7 +185,7 @@ static int _pin_read(rt_device_t dev, rt_base_t pin) return value; } -static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { GPIO_Config_T gpioConfig; @@ -173,7 +195,7 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) } /* Configure gpioConfigure */ -#if defined(APM32F10X_HD) +#if defined(SOC_SERIES_APM32F1) gpioConfig.pin = PIN_APMPIN(pin); gpioConfig.mode = GPIO_MODE_OUT_PP; gpioConfig.speed = GPIO_SPEED_50MHz; @@ -203,7 +225,7 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) /* output setting: od. */ gpioConfig.mode = GPIO_MODE_OUT_OD; } -#elif defined( APM32F40X) +#elif defined(SOC_SERIES_APM32F4) gpioConfig.pin = PIN_APMPIN(pin); gpioConfig.mode = GPIO_MODE_OUT; gpioConfig.otype = GPIO_OTYPE_PP; @@ -239,6 +261,43 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) gpioConfig.mode = GPIO_MODE_OUT; gpioConfig.otype = GPIO_OTYPE_OD; } +#elif defined(SOC_SERIES_APM32F0) + gpioConfig.pin = PIN_APMPIN(pin); + gpioConfig.mode = GPIO_MODE_OUT; + gpioConfig.outtype = GPIO_OUT_TYPE_PP; + gpioConfig.pupd = GPIO_PUPD_NO; + gpioConfig.speed = GPIO_SPEED_50MHz; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpioConfig.mode = GPIO_MODE_OUT; + gpioConfig.outtype = GPIO_OUT_TYPE_PP; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpioConfig.mode = GPIO_MODE_IN; + gpioConfig.pupd = GPIO_PUPD_NO; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpioConfig.mode = GPIO_MODE_IN; + gpioConfig.pupd = GPIO_PUPD_PU; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpioConfig.mode = GPIO_MODE_IN; + gpioConfig.pupd = GPIO_PUPD_PD; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpioConfig.mode = GPIO_MODE_OUT; + gpioConfig.outtype = GPIO_OUT_TYPE_OD; + } #endif GPIO_Config(PIN_APMPORT(pin), &gpioConfig); } @@ -266,7 +325,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) return &pin_irq_map[mapindex]; }; -static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, +static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { rt_base_t level; @@ -306,7 +365,7 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, return RT_EOK; } -static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) { rt_base_t level; rt_int32_t irqindex = -1; @@ -337,13 +396,14 @@ static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin) return RT_EOK; } -static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, +static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { const struct pin_irq_map *irqmap; rt_base_t level; rt_int32_t irqindex = -1; GPIO_Config_T gpioConfig; + EINT_Config_T eintConfig; if (PIN_PORT(pin) >= PIN_APMPORT_MAX) { @@ -373,34 +433,75 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, gpioConfig.speed = GPIO_SPEED_50MHz; switch (pin_irq_hdr_tab[irqindex].mode) { -#if defined(APM32F10X_HD) +#if defined(SOC_SERIES_APM32F0) + case PIN_IRQ_MODE_RISING: + gpioConfig.mode = GPIO_MODE_IN; + gpioConfig.pupd = GPIO_PUPD_PD; + eintConfig.trigger = EINT_TRIGGER_RISING; + break; + case PIN_IRQ_MODE_FALLING: + gpioConfig.mode = GPIO_MODE_IN; + gpioConfig.pupd = GPIO_PUPD_PU; + eintConfig.trigger = EINT_TRIGGER_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + gpioConfig.mode = GPIO_MODE_IN; + gpioConfig.pupd = GPIO_PUPD_NO; + eintConfig.trigger = EINT_TRIGGER_ALL; + break; +#elif defined(SOC_SERIES_APM32F1) case PIN_IRQ_MODE_RISING: gpioConfig.mode = GPIO_MODE_IN_PD; + eintConfig.trigger = EINT_TRIGGER_RISING; break; case PIN_IRQ_MODE_FALLING: gpioConfig.mode = GPIO_MODE_IN_PU; + eintConfig.trigger = EINT_TRIGGER_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: gpioConfig.mode = GPIO_MODE_IN_FLOATING; + eintConfig.trigger = EINT_TRIGGER_RISING_FALLING; break; -#elif defined( APM32F40X) +#elif defined(SOC_SERIES_APM32F4) case PIN_IRQ_MODE_RISING: gpioConfig.mode = GPIO_MODE_IN; gpioConfig.pupd = GPIO_PUPD_DOWN; + eintConfig.trigger = EINT_TRIGGER_RISING; break; case PIN_IRQ_MODE_FALLING: gpioConfig.mode = GPIO_MODE_IN; gpioConfig.pupd = GPIO_PUPD_UP; + eintConfig.trigger = EINT_TRIGGER_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: gpioConfig.mode = GPIO_MODE_IN; gpioConfig.pupd = GPIO_PUPD_NOPULL; + eintConfig.trigger = EINT_TRIGGER_RISING_FALLING; break; #endif } GPIO_Config(PIN_APMPORT(pin), &gpioConfig); - + +#if defined(SOC_SERIES_APM32F0) + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG); + SYSCFG_EINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex); +#elif defined(SOC_SERIES_APM32F1) + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO); + GPIO_ConfigEINTLine((GPIO_PORT_SOURCE_T)(((pin) >> 4) & 0xFu), (GPIO_PIN_SOURCE_T)irqindex); +#elif defined(SOC_SERIES_APM32F4) + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG); + SYSCFG_ConfigEINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex); +#endif + eintConfig.line = (EINT_LINE_T)(1u << PIN_NO(pin)); + eintConfig.mode = EINT_MODE_INTERRUPT; + eintConfig.lineCmd = ENABLE; + EINT_Config(&eintConfig); + +#if defined(SOC_SERIES_APM32F0) + NVIC_EnableIRQRequest(irqmap->irqno, 5); +#else NVIC_EnableIRQRequest(irqmap->irqno, 5, 0); +#endif pin_irq_enable_mask |= irqmap->pinbit; rt_hw_interrupt_enable(level); @@ -416,7 +517,35 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, level = rt_hw_interrupt_disable(); pin_irq_enable_mask &= ~irqmap->pinbit; - + +#if defined(SOC_SERIES_APM32F0) + if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_0 | GPIO_PIN_1))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_2) && (irqmap->pinbit <= GPIO_PIN_3)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_2 | GPIO_PIN_3))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_4) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQRequest(irqmap->irqno); + } +#else if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) { if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) @@ -435,6 +564,7 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, { NVIC_DisableIRQRequest(irqmap->irqno); } +#endif rt_hw_interrupt_enable(level); } else @@ -444,15 +574,16 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_EOK; } -const static struct rt_pin_ops _apm32_pin_ops = + +const static struct rt_pin_ops apm32_pin_ops = { - _pin_mode, - _pin_write, - _pin_read, - _pin_attach_irq, - _pin_dettach_irq, - _pin_irq_enable, - _pin_get, + apm32_pin_mode, + apm32_pin_write, + apm32_pin_read, + apm32_pin_attach_irq, + apm32_pin_dettach_irq, + apm32_pin_irq_enable, + apm32_pin_get, }; rt_inline void pin_irq_hdr(int irqno) @@ -463,140 +594,115 @@ rt_inline void pin_irq_hdr(int irqno) } } - -void GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +void GPIO_EXTI_IRQHandler(uint8_t exti_line) { - pin_irq_hdr(bit2bitno(GPIO_Pin)); +#if defined(SOC_SERIES_APM32F0) + if (EINT_ReadIntFlag(1U << exti_line) != RESET) +#else + if (EINT_ReadIntFlag((EINT_LINE_T)(1U << exti_line)) != RESET) +#endif + { + EINT_ClearIntFlag(1U << exti_line); + pin_irq_hdr(exti_line); + } } +#if defined(SOC_SERIES_APM32F0) +void EINT0_1_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(0); + GPIO_EXTI_IRQHandler(1); + rt_interrupt_leave(); +} +void EINT2_3_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(2); + GPIO_EXTI_IRQHandler(3); + rt_interrupt_leave(); +} +void EINT4_15_IRQHandler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(4); + GPIO_EXTI_IRQHandler(5); + GPIO_EXTI_IRQHandler(6); + GPIO_EXTI_IRQHandler(7); + GPIO_EXTI_IRQHandler(8); + GPIO_EXTI_IRQHandler(9); + GPIO_EXTI_IRQHandler(10); + GPIO_EXTI_IRQHandler(11); + GPIO_EXTI_IRQHandler(12); + GPIO_EXTI_IRQHandler(13); + GPIO_EXTI_IRQHandler(14); + GPIO_EXTI_IRQHandler(15); + rt_interrupt_leave(); +} +#else void EINT0_IRQHandler(void) { rt_interrupt_enter(); - - if (EINT_ReadIntFlag(EINT_LINE_0)) - { - EINT_ClearIntFlag(EINT_LINE_0); - GPIO_EXTI_IRQHandler(GPIO_PIN_0); - } - + GPIO_EXTI_IRQHandler(0); rt_interrupt_leave(); } void EINT1_IRQHandler(void) { rt_interrupt_enter(); - if (EINT_ReadIntFlag(EINT_LINE_1)) - { - EINT_ClearIntFlag(EINT_LINE_1); - GPIO_EXTI_IRQHandler(GPIO_PIN_1); - } + GPIO_EXTI_IRQHandler(1); rt_interrupt_leave(); } void EINT2_IRQHandler(void) { rt_interrupt_enter(); - if (EINT_ReadIntFlag(EINT_LINE_2)) - { - EINT_ClearIntFlag(EINT_LINE_2); - GPIO_EXTI_IRQHandler(GPIO_PIN_2); - } + GPIO_EXTI_IRQHandler(2); rt_interrupt_leave(); } void EINT3_IRQHandler(void) { rt_interrupt_enter(); - if (EINT_ReadIntFlag(EINT_LINE_3)) - { - EINT_ClearIntFlag(EINT_LINE_3); - GPIO_EXTI_IRQHandler(GPIO_PIN_3); - } + GPIO_EXTI_IRQHandler(3); rt_interrupt_leave(); } void EINT4_IRQHandler(void) { rt_interrupt_enter(); - if (EINT_ReadIntFlag(EINT_LINE_4)) - { - EINT_ClearIntFlag(EINT_LINE_4); - GPIO_EXTI_IRQHandler(GPIO_PIN_4); - } + GPIO_EXTI_IRQHandler(4); rt_interrupt_leave(); } void EINT9_5_IRQHandler(void) { rt_interrupt_enter(); - if (EINT_ReadIntFlag(EINT_LINE_5)) - { - EINT_ClearIntFlag(EINT_LINE_5); - GPIO_EXTI_IRQHandler(GPIO_PIN_5); - } - if (EINT_ReadIntFlag(EINT_LINE_6)) - { - EINT_ClearIntFlag(EINT_LINE_6); - GPIO_EXTI_IRQHandler(GPIO_PIN_6); - } - if (EINT_ReadIntFlag(EINT_LINE_7)) - { - EINT_ClearIntFlag(EINT_LINE_7); - GPIO_EXTI_IRQHandler(GPIO_PIN_7); - } - if (EINT_ReadIntFlag(EINT_LINE_8)) - { - EINT_ClearIntFlag(EINT_LINE_8); - GPIO_EXTI_IRQHandler(GPIO_PIN_8); - } - if (EINT_ReadIntFlag(EINT_LINE_9)) - { - EINT_ClearIntFlag(EINT_LINE_9); - GPIO_EXTI_IRQHandler(GPIO_PIN_9); - } + GPIO_EXTI_IRQHandler(5); + GPIO_EXTI_IRQHandler(6); + GPIO_EXTI_IRQHandler(7); + GPIO_EXTI_IRQHandler(8); + GPIO_EXTI_IRQHandler(9); rt_interrupt_leave(); } void EINT15_10_IRQHandler(void) { rt_interrupt_enter(); - if (EINT_ReadIntFlag(EINT_LINE_10)) - { - EINT_ClearIntFlag(EINT_LINE_10); - GPIO_EXTI_IRQHandler(GPIO_PIN_10); - } - if (EINT_ReadIntFlag(EINT_LINE_11)) - { - EINT_ClearIntFlag(EINT_LINE_11); - GPIO_EXTI_IRQHandler(GPIO_PIN_11); - } - if (EINT_ReadIntFlag(EINT_LINE_12)) - { - EINT_ClearIntFlag(EINT_LINE_12); - GPIO_EXTI_IRQHandler(GPIO_PIN_12); - } - if (EINT_ReadIntFlag(EINT_LINE_13)) - { - EINT_ClearIntFlag(EINT_LINE_13); - GPIO_EXTI_IRQHandler(GPIO_PIN_13); - } - if (EINT_ReadIntFlag(EINT_LINE_14)) - { - EINT_ClearIntFlag(EINT_LINE_14); - GPIO_EXTI_IRQHandler(GPIO_PIN_14); - } - if (EINT_ReadIntFlag(EINT_LINE_15)) - { - EINT_ClearIntFlag(EINT_LINE_15); - GPIO_EXTI_IRQHandler(GPIO_PIN_15); - } + GPIO_EXTI_IRQHandler(10); + GPIO_EXTI_IRQHandler(11); + GPIO_EXTI_IRQHandler(12); + GPIO_EXTI_IRQHandler(13); + GPIO_EXTI_IRQHandler(14); + GPIO_EXTI_IRQHandler(15); rt_interrupt_leave(); } +#endif int rt_hw_pin_init(void) { -#if defined(APM32F10X_HD) +#if defined(SOC_SERIES_APM32F1) #ifdef GPIOA RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); #endif @@ -619,7 +725,7 @@ int rt_hw_pin_init(void) RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOG); #endif RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO); -#elif defined(APM32F40X) +#elif defined(SOC_SERIES_APM32F4) #ifdef GPIOA RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA); #endif @@ -653,9 +759,30 @@ int rt_hw_pin_init(void) #ifdef GPIOK RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOK); #endif + +#elif defined(SOC_SERIES_APM32F0) +#ifdef GPIOA + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA); +#endif +#ifdef GPIOB + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOB); +#endif +#ifdef GPIOC + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOC); +#endif +#ifdef GPIOD + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOD); +#endif +#ifdef GPIOE + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOE); +#endif +#ifdef GPIOF + RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOF); #endif - return rt_device_pin_register("pin", &_apm32_pin_ops, RT_NULL); +#endif /* SOC_SERIES_APM32F0 */ + + return rt_device_pin_register("pin", &apm32_pin_ops, RT_NULL); } #endif /* RT_USING_PIN */ diff --git a/bsp/apm32/libraries/Drivers/drv_hwtimer.c b/bsp/apm32/libraries/Drivers/drv_hwtimer.c index 2f1ff05c61..40285f767c 100644 --- a/bsp/apm32/libraries/Drivers/drv_hwtimer.c +++ b/bsp/apm32/libraries/Drivers/drv_hwtimer.c @@ -7,17 +7,18 @@ * Date Author Notes * 2022-03-04 stevetong459 first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include -#define LOG_TAG "drv.hwtimer" +#define DBG_TAG "drv.hwtimer" #define DBG_LVL DBG_INFO #include #ifdef RT_USING_HWTIMER -static const struct rt_hwtimer_info _info = +static const struct rt_hwtimer_info apm32_timer_info = { .maxfreq = 1000000, .minfreq = 2000, @@ -78,6 +79,15 @@ enum #ifdef BSP_USING_TMR14 TMR14_INDEX, #endif +#ifdef BSP_USING_TMR15 + TMR15_INDEX, +#endif +#ifdef BSP_USING_TMR16 + TMR16_INDEX, +#endif +#ifdef BSP_USING_TMR17 + TMR17_INDEX, +#endif }; static struct apm32_timer tmr_config[] = @@ -86,10 +96,12 @@ static struct apm32_timer tmr_config[] = { "timer1", TMR1, -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) TMR1_UP_IRQn, -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) TMR1_UP_TMR10_IRQn, +#elif defined(SOC_SERIES_APM32F0) + TMR1_BRK_UP_TRG_COM_IRQn #endif }, #endif @@ -125,9 +137,11 @@ static struct apm32_timer tmr_config[] = { "timer6", TMR6, -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) || defined(APM32F030) || defined(APM32F070) TMR6_IRQn, -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) + TMR6_DAC_IRQn +#elif defined(SOC_SERIES_APM32F0) && !defined(APM32F030) && !defined(APM32F070) TMR6_DAC_IRQn #endif }, @@ -143,9 +157,9 @@ static struct apm32_timer tmr_config[] = { "timer8", TMR8, -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) TMR8_UP_IRQn, -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) TMR8_UP_TMR13_IRQn, #endif }, @@ -189,30 +203,122 @@ static struct apm32_timer tmr_config[] = { "timer14", TMR14, +#if defined(SOC_SERIES_APM32F0) + TMR14_IRQn, +#elif defined(SOC_SERIES_APM32F4) TMR8_TRG_COM_TMR14_IRQn, +#endif + }, +#endif +#ifdef BSP_USING_TMR15 + { + "timer15", + TMR15, + TMR15_IRQn, + }, +#endif +#ifdef BSP_USING_TMR16 + { + "timer16", + TMR16, + TMR16_IRQn, + }, +#endif +#ifdef BSP_USING_TMR17 + { + "timer17", + TMR17, + TMR17_IRQn, }, #endif }; -static rt_uint32_t _hwtimer_clock_get(TMR_T *tmr) +static rt_uint32_t apm32_hwtimer_clock_get(TMR_T *tmr) { +#if defined(SOC_SERIES_APM32F0) + uint32_t pclk1; + + pclk1 = RCM_ReadPCLKFreq(); + + return (rt_uint32_t)(pclk1 * ((RCM->CFG1_B.APB1PSC != 0) ? 2 : 1)); +#else uint32_t pclk1, pclk2; RCM_ReadPCLKFreq(&pclk1, &pclk2); if (tmr == TMR1 || tmr == TMR8 || tmr == TMR9 || tmr == TMR10 || tmr == TMR11) { - return (rt_uint32_t)(pclk2 * ((RCM->CFG_B.APB2PSC != RCM_APB_DIV_1) ? 2 : 1)); + return (rt_uint32_t)(pclk2 * ((RCM->CFG_B.APB2PSC != 0) ? 2 : 1)); } else { - return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != RCM_APB_DIV_1) ? 2 : 1)); + return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != 0) ? 2 : 1)); } +#endif } -static void _hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void apm32_hwtimer_enable_clock(void) { +#ifdef BSP_USING_TMR1 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); +#endif +#ifdef BSP_USING_TMR2 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2); +#endif +#ifdef BSP_USING_TMR3 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3); +#endif +#ifdef BSP_USING_TMR4 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4); +#endif +#ifdef BSP_USING_TMR5 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5); +#endif +#ifdef BSP_USING_TMR6 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR6); +#endif +#ifdef BSP_USING_TMR7 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR7); +#endif +#ifdef BSP_USING_TMR8 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8); +#endif +#ifdef BSP_USING_TMR9 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR9); +#endif +#ifdef BSP_USING_TMR10 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR10); +#endif +#ifdef BSP_USING_TMR11 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR11); +#endif +#ifdef BSP_USING_TMR12 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR12); +#endif +#ifdef BSP_USING_TMR13 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR13); +#endif +#ifdef BSP_USING_TMR14 + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR14); +#endif +#ifdef BSP_USING_TMR15 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR15); +#endif +#ifdef BSP_USING_TMR16 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR16); +#endif +#ifdef BSP_USING_TMR17 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR17); +#endif +} + +static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ +#if defined(SOC_SERIES_APM32F0) + TMR_TimeBase_T base_config; +#else TMR_BaseConfig_T base_config; +#endif uint32_t prescaler = 0; struct apm32_timer *timer_config; @@ -221,77 +327,24 @@ static void _hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) if (state) { timer_config = (struct apm32_timer *)timer->parent.user_data; - if (timer_config->tmr == TMR2) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2); - } - else if (timer_config->tmr == TMR3) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3); - } - else if (timer_config->tmr == TMR4) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4); - } - else if (timer_config->tmr == TMR5) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5); - } - else if (timer_config->tmr == TMR6) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR6); - } - else if (timer_config->tmr == TMR7) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR7); - } -#ifdef APM32F10X_HD - else if (timer_config->tmr == TMR1) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); - } - else if (timer_config->tmr == TMR8) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8); - } -#endif -#ifdef APM32F40X - else if (timer_config->tmr == TMR1) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); - } - else if (timer_config->tmr == TMR8) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8); - } - else if (timer_config->tmr == TMR9) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR9); - } - else if (timer_config->tmr == TMR10) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR10); - } - else if (timer_config->tmr == TMR11) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR11); - } - else if (timer_config->tmr == TMR12) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR12); - } - else if (timer_config->tmr == TMR13) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR13); - } - else if (timer_config->tmr == TMR14) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR14); - } -#endif - prescaler = (uint32_t)(_hwtimer_clock_get(timer_config->tmr) / 10000) - 1; + + apm32_hwtimer_enable_clock(); + + prescaler = (uint32_t)(apm32_hwtimer_clock_get(timer_config->tmr) / 10000) - 1; base_config.period = 10000 - 1; +#if defined(SOC_SERIES_APM32F0) + base_config.div = prescaler; + base_config.clockDivision = TMR_CKD_DIV1; + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + { + base_config.counterMode = TMR_COUNTER_MODE_UP; + } + else + { + base_config.counterMode = TMR_COUNTER_MODE_DOWN; + } +#else base_config.division = prescaler; base_config.clockDivision = TMR_CLOCK_DIV_1; if (timer->info->cntmode == HWTIMER_CNTMODE_UP) @@ -302,21 +355,28 @@ static void _hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { base_config.countMode = TMR_COUNTER_MODE_DOWN; } +#endif base_config.repetitionCounter = 0; TMR_ConfigTimeBase(timer_config->tmr, &base_config); - + +#if defined(SOC_SERIES_APM32F0) + /* set the TIMx priority */ + NVIC_EnableIRQRequest(timer_config->irqn, 3); + /* enable update request source */ + TMR_ConfigUPdateRequest(timer_config->tmr, TMR_UPDATE_SOURCE_REGULAR); +#else /* set the TIMx priority */ NVIC_EnableIRQRequest(timer_config->irqn, 3, 0); - - /* clear update flag */ - TMR_ClearStatusFlag(timer_config->tmr, TMR_FLAG_UPDATE); /* enable update request source */ TMR_ConfigUpdateRequest(timer_config->tmr, TMR_UPDATE_SOURCE_REGULAR); +#endif + /* clear update flag */ + TMR_ClearStatusFlag(timer_config->tmr, TMR_FLAG_UPDATE); LOG_D("%s init success", timer_config->name); } } -static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t apm32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) { rt_err_t result = RT_EOK; struct apm32_timer *timer_config = RT_NULL; @@ -326,41 +386,46 @@ static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mo timer_config = (struct apm32_timer *)timer->parent.user_data; /* set timer_config counter */ - TMR_ConfigCounter(timer_config->tmr, 0); + timer_config->tmr->CNT = 0; /* set timer_config autoReload */ - TMR_ConfigAutoreload(timer_config->tmr, t - 1); + timer_config->tmr->AUTORLD = t - 1; if (opmode == HWTIMER_MODE_ONESHOT) { /* set timer to single mode */ - TMR_ConfigSinglePulseMode(timer_config->tmr, TMR_SPM_SINGLE); + timer_config->tmr->CTRL1_B.SPMEN = 1; } else { - TMR_ConfigSinglePulseMode(timer_config->tmr, TMR_SPM_REPETITIVE); + timer_config->tmr->CTRL1_B.SPMEN = 0; } TMR_EnableInterrupt(timer_config->tmr, TMR_INT_UPDATE); - if (timer_config->tmr == TMR1 || timer_config->tmr == TMR8 || timer_config->tmr == TMR2 || \ - timer_config->tmr == TMR3 || timer_config->tmr == TMR4 || timer_config->tmr == TMR5 || \ - timer_config->tmr == TMR9 || timer_config->tmr == TMR12) +#if defined(SOC_SERIES_APM32F0) + if (timer_config->tmr == TMR1 || timer_config->tmr == TMR2 || timer_config->tmr == TMR3 || \ + timer_config->tmr == TMR15) +#else + if (timer_config->tmr == TMR1 || timer_config->tmr == TMR2 || timer_config->tmr == TMR3 || \ + timer_config->tmr == TMR4 || timer_config->tmr == TMR5 || timer_config->tmr == TMR8 || \ + timer_config->tmr == TMR9 || timer_config->tmr == TMR12) +#endif { - if (timer_config->tmr->SMCTRL_B.SMFSEL != TMR_SLAVE_MODE_TRIGGER) + if (timer_config->tmr->SMCTRL_B.SMFSEL != 0x06) { TMR_Enable(timer_config->tmr); - result = -RT_EOK; + result = RT_EOK; } } else { TMR_Enable(timer_config->tmr); - result = -RT_EOK; + result = RT_EOK; } return result; } -static void _hwtimer_stop(rt_hwtimer_t *timer) +static void apm32_hwtimer_stop(rt_hwtimer_t *timer) { struct apm32_timer *timer_config = RT_NULL; RT_ASSERT(timer != RT_NULL); @@ -368,10 +433,10 @@ static void _hwtimer_stop(rt_hwtimer_t *timer) TMR_DisableInterrupt(timer_config->tmr, TMR_INT_UPDATE); TMR_Enable(timer_config->tmr); - TMR_ConfigCounter(timer_config->tmr, 0); + timer_config->tmr->CNT = 0; } -static rt_err_t _hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t apm32_hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) { struct apm32_timer *timer_config = RT_NULL; rt_err_t result = RT_EOK; @@ -389,18 +454,21 @@ static rt_err_t _hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) /* set timer frequence */ freq = *((rt_uint32_t *)arg); - val = _hwtimer_clock_get(timer_config->tmr) / freq; + val = apm32_hwtimer_clock_get(timer_config->tmr) / freq; - TMR_ConfigPrescaler(timer_config->tmr, val - 1, TMR_PSC_RELOAD_IMMEDIATE); + /* Configures the timer prescaler */ + timer_config->tmr->PSC_B.PSC = val - 1; + timer_config->tmr->CEG_B.UEG = 1; break; default: + LOG_E("invalid cmd: 0x%x\n", cmd); result = -RT_ENOSYS; break; } return result; } -static rt_uint32_t _hwtimer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t apm32_hwtimer_counter_get(rt_hwtimer_t *timer) { struct apm32_timer *timer_config = RT_NULL; RT_ASSERT(timer != RT_NULL); @@ -409,16 +477,27 @@ static rt_uint32_t _hwtimer_counter_get(rt_hwtimer_t *timer) return timer_config->tmr->CNT; } -static const struct rt_hwtimer_ops _hwtimer_ops = +static const struct rt_hwtimer_ops apm32_hwtimer_ops = { - .init = _hwtimer_init, - .start = _hwtimer_start, - .stop = _hwtimer_stop, - .count_get = _hwtimer_counter_get, - .control = _hwtimer_ctrl, + .init = apm32_hwtimer_init, + .start = apm32_hwtimer_start, + .stop = apm32_hwtimer_stop, + .count_get = apm32_hwtimer_counter_get, + .control = apm32_hwtimer_ctrl, }; -#ifdef APM32F10X_HD + +#if defined(SOC_SERIES_APM32F0) +#ifdef BSP_USING_TMR1 +void TMR1_BRK_UP_TRG_COM_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device); + TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif +#elif defined(SOC_SERIES_APM32F1) #ifdef BSP_USING_TMR1 void TMR1_UP_IRQHandler(void) { @@ -428,7 +507,7 @@ void TMR1_UP_IRQHandler(void) rt_interrupt_leave(); } #endif -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) #if (defined(BSP_USING_TMR1) || defined(BSP_USING_TMR10)) void TMR1_UP_TMR10_IRQHandler(void) { @@ -489,9 +568,11 @@ void TMR5_IRQHandler(void) #endif #ifdef BSP_USING_TMR6 -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) || defined(APM32F030) || defined(APM32F070) void TMR6_IRQHandler(void) -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) + void TMR6_DAC_IRQHandler(void) +#elif defined(SOC_SERIES_APM32F0) && !defined(APM32F030) && !defined(APM32F070) void TMR6_DAC_IRQHandler(void) #endif { @@ -512,7 +593,7 @@ void TMR7_IRQHandler(void) } #endif -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) #ifdef BSP_USING_TMR8 void TMR8_UP_IRQHandler(void) { @@ -522,7 +603,7 @@ void TMR8_UP_IRQHandler(void) rt_interrupt_leave(); } #endif -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F4) #if (defined(BSP_USING_TMR8) || defined(BSP_USING_TMR13)) void TMR8_UP_TMR13_IRQHandler(void) { @@ -573,7 +654,11 @@ void TMR8_BRK_TMR12_IRQHandler(void) #endif #ifdef BSP_USING_TMR14 -void TMR8_TRG_COM_TMR14_IRQHandler(void) +#if defined(SOC_SERIES_APM32F0) + void TMR14_IRQHandler(void) +#elif defined(SOC_SERIES_APM32F4) + void TMR8_TRG_COM_TMR14_IRQHandler(void) +#endif { rt_interrupt_enter(); rt_device_hwtimer_isr(&tmr_config[TMR14_INDEX].device); @@ -582,6 +667,36 @@ void TMR8_TRG_COM_TMR14_IRQHandler(void) } #endif +#ifdef BSP_USING_TMR15 +void TMR15_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR15_INDEX].device); + TMR_ClearIntFlag(TMR15, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TMR16 +void TMR16_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR16_INDEX].device); + TMR_ClearIntFlag(TMR16, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TMR17 +void TMR17_IRQHandler(void) +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&tmr_config[TMR17_INDEX].device); + TMR_ClearIntFlag(TMR17, TMR_INT_UPDATE); + rt_interrupt_leave(); +} +#endif + static int rt_hw_hwtimer_init(void) { int i = 0; @@ -589,8 +704,8 @@ static int rt_hw_hwtimer_init(void) for (i = 0; i < sizeof(tmr_config) / sizeof(tmr_config[0]); i++) { - tmr_config[i].device.info = &_info; - tmr_config[i].device.ops = &_hwtimer_ops; + tmr_config[i].device.info = &apm32_timer_info; + tmr_config[i].device.ops = &apm32_hwtimer_ops; if (rt_device_hwtimer_register(&tmr_config[i].device, tmr_config[i].name, &tmr_config[i]) == RT_EOK) { LOG_D("%s register success", tmr_config[i].name); diff --git a/bsp/apm32/libraries/Drivers/drv_log.h b/bsp/apm32/libraries/Drivers/drv_log.h new file mode 100644 index 0000000000..dcdb7fc212 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-12-19 first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/apm32/libraries/Drivers/drv_pwm.c b/bsp/apm32/libraries/Drivers/drv_pwm.c index da0a793750..ff712222ad 100644 --- a/bsp/apm32/libraries/Drivers/drv_pwm.c +++ b/bsp/apm32/libraries/Drivers/drv_pwm.c @@ -7,6 +7,7 @@ * Date Author Notes * 2022-03-04 stevetong459 first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include @@ -14,7 +15,7 @@ #ifdef RT_USING_PWM #include -#define LOG_TAG "drv.pwm" +#define DBG_TAG "drv.pwm" #define DBG_LVL DBG_INFO #include @@ -22,28 +23,8 @@ #define MIN_PERIOD 3 #define MIN_PULSE 2 -#ifdef APM32F10X_HD -#define _PWM_GPIO_INIT(port_num, pin_num) \ -do \ -{ \ - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIO##port_num); \ - gpio_config->pin = GPIO_PIN_##pin_num; \ - gpio_config->mode = GPIO_MODE_AF_PP; \ - gpio_config->speed = GPIO_SPEED_50MHz; \ - GPIO_Config(GPIO##port_num, gpio_config); \ -} while (0) -#elif APM32F40X -#define _PWM_GPIO_INIT(port_num, pin_num) \ -do \ -{ \ - RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIO##port_num); \ - gpio_config->pin = GPIO_PIN_##pin_num; \ - gpio_config->mode = GPIO_MODE_AF; \ - gpio_config->otype = GPIO_OTYPE_PP; \ - gpio_config->speed = GPIO_SPEED_50MHz; \ - GPIO_Config(GPIO##port_num, gpio_config); \ -} while (0) -#endif +/* Init timer gpio and enable clock */ +extern void apm32_msp_timer_init(void *Instance); enum { @@ -83,6 +64,15 @@ enum #ifdef BSP_USING_PWM14 PWM14_INDEX, #endif +#ifdef BSP_USING_PWM15 + PWM15_INDEX, +#endif +#ifdef BSP_USING_PWM16 + PWM16_INDEX, +#endif +#ifdef BSP_USING_PWM17 + PWM17_INDEX, +#endif }; struct apm32_pwm @@ -179,207 +169,200 @@ static struct apm32_pwm pwm_config[] = 0, }, #endif +#ifdef BSP_USING_PWM15 + { + "pwm15", + TMR15, + 0, + }, +#endif +#ifdef BSP_USING_PWM16 + { + "pwm16", + TMR16, + 0, + }, +#endif +#ifdef BSP_USING_PWM17 + { + "pwm17", + TMR17, + 0, + }, +#endif }; -static void _pwm_channel_init(GPIO_Config_T *gpio_config) +static void pwm_channel_init(void) { #ifdef BSP_USING_PWM1_CH1 pwm_config[PWM1_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(A, 8); #endif #ifdef BSP_USING_PWM1_CH2 pwm_config[PWM1_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(A, 9); #endif #ifdef BSP_USING_PWM1_CH3 pwm_config[PWM1_INDEX].channel |= 1 << 2; - _PWM_GPIO_INIT(A, 10); #endif #ifdef BSP_USING_PWM1_CH4 pwm_config[PWM1_INDEX].channel |= 1 << 3; - _PWM_GPIO_INIT(A, 11); #endif #ifdef BSP_USING_PWM2_CH1 pwm_config[PWM2_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(A, 0); #endif #ifdef BSP_USING_PWM2_CH2 pwm_config[PWM2_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(A, 1); #endif #ifdef BSP_USING_PWM2_CH3 pwm_config[PWM2_INDEX].channel |= 1 << 2; - _PWM_GPIO_INIT(A, 2); #endif #ifdef BSP_USING_PWM2_CH4 pwm_config[PWM2_INDEX].channel |= 1 << 3; - _PWM_GPIO_INIT(A, 3); #endif - -#ifdef APM32F10X_HD #ifdef BSP_USING_PWM3_CH1 pwm_config[PWM3_INDEX].channel |= 1 << 0; - GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); - _PWM_GPIO_INIT(C, 6); #endif #ifdef BSP_USING_PWM3_CH2 pwm_config[PWM3_INDEX].channel |= 1 << 1; - GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); - _PWM_GPIO_INIT(C, 7); #endif #ifdef BSP_USING_PWM3_CH3 pwm_config[PWM3_INDEX].channel |= 1 << 2; - GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); - _PWM_GPIO_INIT(C, 8); #endif #ifdef BSP_USING_PWM3_CH4 pwm_config[PWM3_INDEX].channel |= 1 << 3; - GPIO_ConfigPinRemap(GPIO_FULL_REMAP_TMR3); - _PWM_GPIO_INIT(C, 9); #endif -#elif APM32F40X -#ifdef BSP_USING_PWM3_CH1 - pwm_config[PWM3_INDEX].channel |= 1 << 0; - GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_6, GPIO_AF_TMR3); - _PWM_GPIO_INIT(C, 6); -#endif -#ifdef BSP_USING_PWM3_CH2 - pwm_config[PWM3_INDEX].channel |= 1 << 1; - GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_7, GPIO_AF_TMR3); - _PWM_GPIO_INIT(C, 7); -#endif -#ifdef BSP_USING_PWM3_CH3 - pwm_config[PWM3_INDEX].channel |= 1 << 2; - GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_8, GPIO_AF_TMR3); - _PWM_GPIO_INIT(C, 8); -#endif -#ifdef BSP_USING_PWM3_CH4 - pwm_config[PWM3_INDEX].channel |= 1 << 3; - GPIO_ConfigPinAF(GPIOC, GPIO_PIN_SOURCE_9, GPIO_AF_TMR3); - _PWM_GPIO_INIT(C, 9); -#endif -#endif - #ifdef BSP_USING_PWM4_CH1 pwm_config[PWM4_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(B, 6); #endif #ifdef BSP_USING_PWM4_CH2 pwm_config[PWM4_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(B, 7); #endif #ifdef BSP_USING_PWM4_CH3 pwm_config[PWM4_INDEX].channel |= 1 << 2; - _PWM_GPIO_INIT(B, 8); #endif #ifdef BSP_USING_PWM4_CH4 pwm_config[PWM4_INDEX].channel |= 1 << 3; - _PWM_GPIO_INIT(B, 9); #endif #ifdef BSP_USING_PWM5_CH1 pwm_config[PWM5_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(A, 0); #endif #ifdef BSP_USING_PWM5_CH2 pwm_config[PWM5_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(A, 1); #endif #ifdef BSP_USING_PWM5_CH3 pwm_config[PWM5_INDEX].channel |= 1 << 2; - _PWM_GPIO_INIT(A, 2); #endif #ifdef BSP_USING_PWM5_CH4 pwm_config[PWM5_INDEX].channel |= 1 << 3; - _PWM_GPIO_INIT(A, 3); #endif #ifdef BSP_USING_PWM8_CH1 pwm_config[PWM8_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(C, 6); #endif #ifdef BSP_USING_PWM8_CH2 pwm_config[PWM8_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(C, 7); #endif #ifdef BSP_USING_PWM8_CH3 pwm_config[PWM8_INDEX].channel |= 1 << 2; - _PWM_GPIO_INIT(C, 8); #endif #ifdef BSP_USING_PWM8_CH4 pwm_config[PWM8_INDEX].channel |= 1 << 3; - _PWM_GPIO_INIT(C, 9); #endif -#ifdef APM32F40X #ifdef BSP_USING_PWM9_CH1 pwm_config[PWM9_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(E, 5); #endif #ifdef BSP_USING_PWM9_CH2 pwm_config[PWM9_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(E, 6); #endif #ifdef BSP_USING_PWM10_CH1 pwm_config[PWM10_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(F, 6); #endif #ifdef BSP_USING_PWM11_CH1 pwm_config[PWM11_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(F, 7); #endif #ifdef BSP_USING_PWM12_CH1 - pwm_config[PWM9_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(H, 6); + pwm_config[PWM12_INDEX].channel |= 1 << 0; #endif #ifdef BSP_USING_PWM12_CH2 - pwm_config[PWM9_INDEX].channel |= 1 << 1; - _PWM_GPIO_INIT(H, 9); + pwm_config[PWM12_INDEX].channel |= 1 << 1; #endif #ifdef BSP_USING_PWM13_CH1 - pwm_config[PWM10_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(F, 8); + pwm_config[PWM13_INDEX].channel |= 1 << 0; #endif #ifdef BSP_USING_PWM14_CH1 - pwm_config[PWM11_INDEX].channel |= 1 << 0; - _PWM_GPIO_INIT(F, 9); + pwm_config[PWM14_INDEX].channel |= 1 << 0; #endif +#ifdef BSP_USING_PWM15_CH1 + pwm_config[PWM15_INDEX].channel |= 1 << 0; +#endif +#ifdef BSP_USING_PWM15_CH2 + pwm_config[PWM15_INDEX].channel |= 1 << 1; +#endif +#ifdef BSP_USING_PWM16_CH1 + pwm_config[PWM16_INDEX].channel |= 1 << 0; +#endif +#ifdef BSP_USING_PWM17_CH1 + pwm_config[PWM17_INDEX].channel |= 1 << 0; #endif } -static rt_err_t _pwm_hw_init(struct apm32_pwm *device) +static rt_err_t apm32_pwm_hw_init(struct apm32_pwm *device) { rt_err_t result = RT_EOK; TMR_T *tmr = RT_NULL; + + RT_ASSERT(device != RT_NULL); + tmr = (TMR_T *)device->tmr; + + /* Init timer gpio and enable clock */ + apm32_msp_timer_init(tmr); + +#if defined(SOC_SERIES_APM32F0) + TMR_TimeBase_T base_config; + TMR_OCConfig_T oc_config; + + /* configure the tmrer to pwm mode */ + base_config.div = 0; + base_config.counterMode = TMR_COUNTER_MODE_UP; + base_config.period = 0; + base_config.clockDivision = TMR_CKD_DIV1; + TMR_ConfigTimeBase(tmr, &base_config); + + TMR_SelectOutputTrigger(tmr, TMR_TRGOSOURCE_RESET); + TMR_DisableMasterSlaveMode(tmr); + + oc_config.OC_Mode = TMR_OC_MODE_PWM1; + oc_config.Pulse = 0; + oc_config.OC_Polarity = TMR_OC_POLARITY_HIGH; + oc_config.OC_NIdlestate = TMR_OCNIDLESTATE_RESET; + oc_config.OC_Idlestate = TMR_OCIDLESTATE_RESET; + oc_config.OC_OutputState = TMR_OUTPUT_STATE_ENABLE; + + /* config pwm channel */ + if (device->channel & 0x01) + { + TMR_OC1Config(tmr, &oc_config); + } + + if (device->channel & 0x02) + { + TMR_OC2Config(tmr, &oc_config); + } + + if (device->channel & 0x04) + { + TMR_OC3Config(tmr, &oc_config); + } + + if (device->channel & 0x08) + { + TMR_OC4Config(tmr, &oc_config); + } + + /* enable update request source */ + TMR_ConfigUPdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR); +#else TMR_BaseConfig_T base_config; TMR_OCConfig_T oc_config; - RT_ASSERT(device != RT_NULL); - - tmr = (TMR_T *)device->tmr; - - if (tmr == TMR1) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); - } - else if (tmr == TMR8) - { - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8); - } - else if (tmr == TMR2) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2); - } - else if (tmr == TMR3) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3); - } - else if (tmr == TMR4) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4); - } - else if (tmr == TMR5) - { - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5); - } - /* configure the tmrer to pwm mode */ base_config.division = 0; base_config.countMode = TMR_COUNTER_MODE_UP; @@ -420,20 +403,36 @@ static rt_err_t _pwm_hw_init(struct apm32_pwm *device) /* enable update request source */ TMR_ConfigUpdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR); +#endif return result; } -static rt_uint32_t _pwm_timer_clock_get(TMR_T *tmr) +static rt_uint32_t timer_clock_get(TMR_T *tmr) { +#if defined(SOC_SERIES_APM32F0) uint32_t pclk1; + + pclk1 = RCM_ReadPCLKFreq(); + + return (rt_uint32_t)(pclk1 * ((RCM->CFG1_B.APB1PSC != 0) ? 2 : 1)); +#else + uint32_t pclk1, pclk2; - RCM_ReadPCLKFreq(&pclk1, NULL); + RCM_ReadPCLKFreq(&pclk1, &pclk2); - return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != RCM_APB_DIV_1) ? 2 : 1)); + if (tmr == TMR1 || tmr == TMR8 || tmr == TMR9 || tmr == TMR10 || tmr == TMR11) + { + return (rt_uint32_t)(pclk2 * ((RCM->CFG_B.APB2PSC != 0) ? 2 : 1)); + } + else + { + return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != 0) ? 2 : 1)); + } +#endif } -static rt_err_t _pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configuration, rt_bool_t enable) +static rt_err_t drv_pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configuration, rt_bool_t enable) { rt_uint32_t channel = (configuration->channel - 1) << 2; @@ -447,7 +446,11 @@ static rt_err_t _pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configurati { TMR_EnableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU))); } +#if defined(SOC_SERIES_APM32F0) + if (tmr == TMR1 || tmr == TMR15 || tmr == TMR16 || tmr == TMR17) +#else if (tmr == TMR1 || tmr == TMR8) +#endif { TMR_EnablePWMOutputs(tmr); } @@ -463,7 +466,11 @@ static rt_err_t _pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configurati { TMR_DisableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU))); } +#if defined(SOC_SERIES_APM32F0) + if (tmr == TMR1 || tmr == TMR15 || tmr == TMR16 || tmr == TMR17) +#else if (tmr == TMR1 || tmr == TMR8) +#endif { TMR_DisablePWMOutputs(tmr); } @@ -473,24 +480,32 @@ static rt_err_t _pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configurati return RT_EOK; } -static rt_err_t _pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configuration) { /* Converts the channel number to the channel number of library */ rt_uint32_t channel = (configuration->channel - 1) << 2; rt_uint64_t timer_clock; rt_uint32_t timer_reload, timer_psc; - timer_clock = _pwm_timer_clock_get(tmr); - + timer_clock = timer_clock_get(tmr); + +#if defined(SOC_SERIES_APM32F0) + if (tmr->CTRL1_B.CLKDIV == TMR_CKD_DIV2) +#else if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_2) +#endif { - timer_clock <<= 1; + timer_clock = timer_clock / 2; } +#if defined(SOC_SERIES_APM32F0) + if (tmr->CTRL1_B.CLKDIV == TMR_CKD_DIV4) +#else else if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_4) +#endif { - timer_clock <<= 2; + timer_clock = timer_clock / 4; } - + uint32_t temp; temp = (uint32_t)tmr; temp += (uint32_t)(0x34 + channel); @@ -501,18 +516,18 @@ static rt_err_t _pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configuration) timer_psc = tmr->PSC; configuration->period = (timer_reload + 1) * (timer_psc + 1) * 1000UL / timer_clock; configuration->pulse = ((*(__IO uint32_t *)temp) + 1) * (timer_psc + 1) * 1000UL / timer_clock; - + return RT_EOK; } -static rt_err_t _pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configuration) { rt_uint32_t period, pulse; rt_uint64_t timer_clock, psc; rt_uint32_t channel = 0x04 * (configuration->channel - 1); uint32_t temp = (uint32_t)tmr; - - timer_clock = _pwm_timer_clock_get(tmr); + + timer_clock = timer_clock_get(tmr); /* Convert nanosecond to frequency and duty cycle. */ timer_clock /= 1000000UL; @@ -548,7 +563,7 @@ static rt_err_t _pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configuration) return RT_EOK; } -static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; TMR_T *tmr = (TMR_T *)device->parent.user_data; @@ -558,37 +573,36 @@ static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg) case PWMN_CMD_ENABLE: configuration->complementary = RT_TRUE; case PWM_CMD_ENABLE: - return _pwm_enable(tmr, configuration, RT_TRUE); + return drv_pwm_enable(tmr, configuration, RT_TRUE); case PWMN_CMD_DISABLE: configuration->complementary = RT_FALSE; case PWM_CMD_DISABLE: - return _pwm_enable(tmr, configuration, RT_FALSE); + return drv_pwm_enable(tmr, configuration, RT_FALSE); case PWM_CMD_SET: - return _pwm_set(tmr, configuration); + return drv_pwm_set(tmr, configuration); case PWM_CMD_GET: - return _pwm_get(tmr, configuration); + return drv_pwm_get(tmr, configuration); default: return RT_EINVAL; } } -static const struct rt_pwm_ops _pwm_ops = +static const struct rt_pwm_ops drv_pwm_ops = { - _pwm_control + drv_pwm_control }; static int rt_hw_pwm_init(void) { rt_uint32_t i = 0; rt_err_t result = RT_EOK; - GPIO_Config_T gpio_config; - _pwm_channel_init(&gpio_config); + pwm_channel_init(); for (i = 0; i < sizeof(pwm_config) / sizeof(pwm_config[0]); i++) { /* pwm init */ - if (_pwm_hw_init(&pwm_config[i]) != RT_EOK) + if (apm32_pwm_hw_init(&pwm_config[i]) != RT_EOK) { LOG_E("%s init failed", pwm_config[i].name); return -RT_ERROR; @@ -598,7 +612,7 @@ static int rt_hw_pwm_init(void) LOG_D("%s init success", pwm_config[i].name); /* register pwm device */ - if (rt_device_pwm_register(&pwm_config[i].pwm_device, pwm_config[i].name, &_pwm_ops, pwm_config[i].tmr) == RT_EOK) + if (rt_device_pwm_register(&pwm_config[i].pwm_device, pwm_config[i].name, &drv_pwm_ops, pwm_config[i].tmr) == RT_EOK) { LOG_D("%s register success", pwm_config[i].name); } diff --git a/bsp/apm32/libraries/Drivers/drv_rtc.c b/bsp/apm32/libraries/Drivers/drv_rtc.c index 39573c7be7..6138963c1c 100644 --- a/bsp/apm32/libraries/Drivers/drv_rtc.c +++ b/bsp/apm32/libraries/Drivers/drv_rtc.c @@ -7,6 +7,7 @@ * Date Author Notes * 2022-03-04 stevetong459 first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include "board.h" @@ -14,7 +15,7 @@ #ifdef BSP_USING_ONCHIP_RTC -#define LOG_TAG "drv.rtc" +#define DBG_TAG "drv.rtc" #define DBG_LVL DBG_INFO #include @@ -25,7 +26,7 @@ #define LSE_VALUE ((uint32_t)32768) #endif -#define DRV_RTC_TIME_OUT 0xFFF +#define DRV_RTC_TIME_OUT 0xFFFFF static rt_rtc_dev_t apm32_rtc_dev; static rt_uint8_t rtc_init_flag = RESET; @@ -35,17 +36,17 @@ static rt_uint8_t rtc_init_flag = RESET; * * @return RT_EOK indicates successful initialize, other value indicates failed; */ -static rt_err_t _rtc_init(void) +static rt_err_t apm32_rtc_init(void) { volatile rt_uint32_t counter = 0; - + /* Enable RTC Clock */ -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU | RCM_APB1_PERIPH_BAKR); -#elif APM32F40X +#elif defined(SOC_SERIES_APM32F0) || defined(SOC_SERIES_APM32F4) RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); #endif - + PMU_EnableBackupAccess(); /* Config RTC clock */ @@ -60,6 +61,7 @@ static rt_err_t _rtc_init(void) } RCM_ConfigRTCCLK(RCM_RTCCLK_LSI); #else + RCM_DisableLSI(); RCM_ConfigLSE(RCM_LSE_OPEN); while (!RCM_ReadStatusFlag(RCM_FLAG_LSERDY)) { @@ -69,12 +71,12 @@ static rt_err_t _rtc_init(void) } } RCM_ConfigRTCCLK(RCM_RTCCLK_LSE); -#endif +#endif /* BSP_RTC_USING_LSI */ RCM_EnableRTCCLK(); RTC_WaitForSynchro(); -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) counter = 0; while (!RTC_ReadStatusFlag(RTC_FLAG_OC)) { @@ -92,13 +94,29 @@ static rt_err_t _rtc_init(void) RTC_ConfigPrescaler(LSI_VALUE - 1); #else RTC_ConfigPrescaler(LSE_VALUE - 1); -#endif -#elif APM32F40X +#endif /* BSP_RTC_USING_LSI */ + +#elif defined(SOC_SERIES_APM32F4) RTC_EnableInit(); RTC_Config_T rtcConfig; RTC_ConfigStructInit(&rtcConfig); RTC_Config(&rtcConfig); -#endif + +#elif defined(SOC_SERIES_APM32F0) + RTC_EnableInit(); + RTC_Config_T rtcConfig; + RTC_ConfigStructInit(&rtcConfig); + +#ifdef BSP_RTC_USING_LSI + rtcConfig.AsynchPrediv = 0x63; + rtcConfig.SynchPrediv = 0x18F; +#else + rtcConfig.AsynchPrediv = 0x7F; + rtcConfig.SynchPrediv = 0x130; +#endif /* BSP_RTC_USING_LSI */ + RTC_Config(&rtcConfig); + +#endif /* SOC_SERIES_APM32F1 */ if (!rtc_init_flag) { @@ -107,13 +125,13 @@ static rt_err_t _rtc_init(void) return RT_EOK; } -#ifdef APM32F10X_HD +#if defined(SOC_SERIES_APM32F1) /** * @brief This function will initialize the rtc on chip. * * @return RT_EOK indicates successful initialize, other value indicates failed; */ -static rt_err_t _rtc_get_secs(void *args) +static rt_err_t apm32_rtc_get_secs(time_t *sec) { volatile rt_uint32_t counter = 0; @@ -125,18 +143,18 @@ static rt_err_t _rtc_get_secs(void *args) } } - *(rt_uint32_t *) args = RTC_ReadCounter(); + *(timer_t *) sec = RTC_ReadCounter(); return RT_EOK; } -static rt_err_t _rtc_set_secs(void *args) +static rt_err_t apm32_rtc_set_secs(time_t *sec) { volatile rt_uint32_t counter = 0; if (!rtc_init_flag) { - _rtc_init(); + apm32_rtc_init(); } while (!RTC_ReadStatusFlag(RTC_FLAG_OC)) @@ -147,15 +165,21 @@ static rt_err_t _rtc_set_secs(void *args) } } - RTC_ConfigCounter(*(rt_uint32_t *)args); + RTC_ConfigCounter(*(rt_uint32_t *)sec); return RT_EOK; } -#elif APM32F40X -static void get_rtc_timeval(struct timeval *tv) +#elif defined(SOC_SERIES_APM32F0) || defined(SOC_SERIES_APM32F4) +static rt_err_t apm32_rtc_get_timeval(struct timeval *tv) { +#if defined(SOC_SERIES_APM32F0) + RTC_TIME_T timeConfig; + RTC_DATE_T dateConfig; +#elif defined(SOC_SERIES_APM32F4) RTC_TimeConfig_T timeConfig; RTC_DateConfig_T dateConfig; +#endif + struct tm tm_new = {0}; RTC_ReadTime(RTC_FORMAT_BIN, &timeConfig); @@ -167,19 +191,27 @@ static void get_rtc_timeval(struct timeval *tv) tm_new.tm_mday = dateConfig.date; tm_new.tm_mon = dateConfig.month - 1; tm_new.tm_year = dateConfig.year + 100; - + tv->tv_sec = timegm(&tm_new); + + return RT_EOK; } -static rt_err_t set_rtc_timeval(time_t time_stamp) +static rt_err_t set_rtc_time_stamp(time_t time_stamp) { +#if defined(SOC_SERIES_APM32F0) + RTC_TIME_T timeConfig; + RTC_DATE_T dateConfig; +#elif defined(SOC_SERIES_APM32F4) RTC_TimeConfig_T timeConfig; RTC_DateConfig_T dateConfig; +#endif + struct tm tm = {0}; if (!rtc_init_flag) { - _rtc_init(); + apm32_rtc_init(); } gmtime_r(&time_stamp, &tm); @@ -192,12 +224,21 @@ static rt_err_t set_rtc_timeval(time_t time_stamp) timeConfig.minutes = tm.tm_min ; timeConfig.hours = tm.tm_hour; dateConfig.date = tm.tm_mday; +#if defined(SOC_SERIES_APM32F4) + dateConfig.month = (RTC_MONTH_T)(tm.tm_mon + 1); + dateConfig.weekday = (RTC_WEEKDAY_T)(tm.tm_wday + 1); +#else dateConfig.month = tm.tm_mon + 1 ; - dateConfig.year = tm.tm_year - 100; dateConfig.weekday = tm.tm_wday + 1; +#endif + dateConfig.year = tm.tm_year - 100; + RTC_ConfigTime(RTC_FORMAT_BIN, &timeConfig); RTC_ConfigDate(RTC_FORMAT_BIN, &dateConfig); + + /* wait for set time completed */ + for (int i = 0; i < 0xFFFF; i++); return RT_EOK; } @@ -207,20 +248,20 @@ static rt_err_t set_rtc_timeval(time_t time_stamp) * * @return RT_EOK indicates successful initialize, other value indicates failed; */ -static rt_err_t _rtc_get_secs(void *args) +static rt_err_t apm32_rtc_get_secs(time_t *sec) { struct timeval tv; - get_rtc_timeval(&tv); - *(rt_uint32_t *) args = tv.tv_sec; + apm32_rtc_get_timeval(&tv); + *(time_t *) sec = tv.tv_sec; return RT_EOK; } -static rt_err_t _rtc_set_secs(void *args) +static rt_err_t apm32_rtc_set_secs(time_t *sec) { rt_err_t result = RT_EOK; - if (set_rtc_timeval(*(rt_uint32_t *)args)) + if (set_rtc_time_stamp(*sec)) { result = -RT_ERROR; } @@ -229,14 +270,18 @@ static rt_err_t _rtc_set_secs(void *args) } #endif -static const struct rt_rtc_ops _rtc_ops = +static const struct rt_rtc_ops apm32_rtc_ops = { - _rtc_init, - _rtc_get_secs, - _rtc_set_secs, + apm32_rtc_init, + apm32_rtc_get_secs, + apm32_rtc_set_secs, RT_NULL, RT_NULL, +#if defined(SOC_SERIES_APM32F0) || defined(SOC_SERIES_APM32F4) + apm32_rtc_get_timeval, +#else RT_NULL, +#endif RT_NULL, }; @@ -249,7 +294,7 @@ static int rt_hw_rtc_init(void) { rt_err_t result = RT_EOK; - apm32_rtc_dev.ops = &_rtc_ops; + apm32_rtc_dev.ops = &apm32_rtc_ops; if (rt_hw_rtc_register(&apm32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK) { @@ -263,7 +308,6 @@ static int rt_hw_rtc_init(void) return result; } - INIT_DEVICE_EXPORT(rt_hw_rtc_init); #endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/apm32/libraries/Drivers/drv_soft_i2c.c b/bsp/apm32/libraries/Drivers/drv_soft_i2c.c index 8911da89ad..c4a7844e16 100644 --- a/bsp/apm32/libraries/Drivers/drv_soft_i2c.c +++ b/bsp/apm32/libraries/Drivers/drv_soft_i2c.c @@ -13,7 +13,7 @@ #ifdef RT_USING_I2C -#define LOG_TAG "drv.i2c" +#define DBG_TAG "drv.i2c" #define DBG_LVL DBG_INFO #include @@ -43,28 +43,28 @@ static const struct apm32_soft_i2c_config soft_i2c_config[] = BSP_I2C1_SCL_PIN, BSP_I2C1_SDA_PIN, "i2c1" - } + }, #endif #ifdef BSP_USING_I2C2 { BSP_I2C2_SCL_PIN, BSP_I2C2_SDA_PIN, "i2c2" - } + }, #endif #ifdef BSP_USING_I2C3 { BSP_I2C3_SCL_PIN, BSP_I2C3_SDA_PIN, "i2c3" - } + }, #endif #ifdef BSP_USING_I2C4 { BSP_I2C4_SCL_PIN, BSP_I2C4_SDA_PIN, "i2c4" - } + }, #endif }; @@ -75,7 +75,7 @@ static struct apm32_soft_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_c * * @param i2c is a pointer to the object of soft i2c. */ -static void _soft_i2c_gpio_init(struct apm32_soft_i2c *i2c) +static void apm32_soft_i2c_gpio_init(struct apm32_soft_i2c *i2c) { struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)i2c->ops.data; @@ -93,7 +93,7 @@ static void _soft_i2c_gpio_init(struct apm32_soft_i2c *i2c) * * @param state is the level of sda pin. */ -static void _soft_i2c_set_sda(void *data, rt_int32_t state) +static void apm32_soft_i2c_set_sda(void *data, rt_int32_t state) { struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; @@ -107,7 +107,7 @@ static void _soft_i2c_set_sda(void *data, rt_int32_t state) * * @param state is the level of scl pin. */ -static void _soft_i2c_set_scl(void *data, rt_int32_t state) +static void apm32_soft_i2c_set_scl(void *data, rt_int32_t state) { struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; @@ -119,7 +119,7 @@ static void _soft_i2c_set_scl(void *data, rt_int32_t state) * * @param data is a pointer to the i2c config class. */ -static rt_int32_t _soft_i2c_get_sda(void *data) +static rt_int32_t apm32_soft_i2c_get_sda(void *data) { struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; return rt_pin_read(cfg->sda_pin); @@ -130,7 +130,7 @@ static rt_int32_t _soft_i2c_get_sda(void *data) * * @param data is a pointer to the i2c config class. */ -static rt_int32_t _soft_i2c_get_scl(void *data) +static rt_int32_t apm32_soft_i2c_get_scl(void *data) { struct apm32_soft_i2c_config *cfg = (struct apm32_soft_i2c_config *)data; return rt_pin_read(cfg->scl_pin); @@ -141,7 +141,7 @@ static rt_int32_t _soft_i2c_get_scl(void *data) * * @param us is the microseconds to delay. */ -static void _soft_i2c_udelay(rt_uint32_t us) +static void apm32_soft_i2c_udelay(rt_uint32_t us) { rt_uint32_t count_old = SysTick->VAL; rt_uint32_t count_now; @@ -183,9 +183,9 @@ static rt_err_t apm32_i2c_bus_unlock(const struct apm32_soft_i2c_config *cfg) while (i++ < 9) { rt_pin_write(cfg->scl_pin, PIN_HIGH); - _soft_i2c_udelay(100); + apm32_soft_i2c_udelay(100); rt_pin_write(cfg->scl_pin, PIN_LOW); - _soft_i2c_udelay(100); + apm32_soft_i2c_udelay(100); } } if (PIN_LOW == rt_pin_read(cfg->sda_pin)) @@ -199,11 +199,11 @@ static rt_err_t apm32_i2c_bus_unlock(const struct apm32_soft_i2c_config *cfg) static const struct rt_i2c_bit_ops apm32_bit_ops_default = { .data = RT_NULL, - .set_sda = _soft_i2c_set_sda, - .set_scl = _soft_i2c_set_scl, - .get_sda = _soft_i2c_get_sda, - .get_scl = _soft_i2c_get_scl, - .udelay = _soft_i2c_udelay, + .set_sda = apm32_soft_i2c_set_sda, + .set_scl = apm32_soft_i2c_set_scl, + .get_sda = apm32_soft_i2c_get_sda, + .get_scl = apm32_soft_i2c_get_scl, + .udelay = apm32_soft_i2c_udelay, .delay_us = 1, .timeout = 100 }; @@ -223,7 +223,7 @@ int rt_hw_i2c_init(void) i2c_obj[i].ops = apm32_bit_ops_default; i2c_obj[i].ops.data = (void *)&soft_i2c_config[i]; i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops; - _soft_i2c_gpio_init(&i2c_obj[i]); + apm32_soft_i2c_gpio_init(&i2c_obj[i]); result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name); @@ -231,10 +231,10 @@ int rt_hw_i2c_init(void) apm32_i2c_bus_unlock(&soft_i2c_config[i]); - LOG_D("software simulation %s init done, pin scl: %s, pin sda: %s", + LOG_D("software simulation %s init done, pin scl: %d, pin sda: %d", soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl_pin_name, - soft_i2c_config[i].sda_pin_name); + soft_i2c_config[i].scl_pin, + soft_i2c_config[i].sda_pin); } return RT_EOK; diff --git a/bsp/apm32/libraries/Drivers/drv_spi.c b/bsp/apm32/libraries/Drivers/drv_spi.c index e64be39e4c..fde1f7f0a0 100644 --- a/bsp/apm32/libraries/Drivers/drv_spi.c +++ b/bsp/apm32/libraries/Drivers/drv_spi.c @@ -7,34 +7,128 @@ * Date Author Notes * 2022-03-04 stevetong459 first version * 2022-07-15 Aligagago add apm32F4 serie MCU support + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include "drv_spi.h" +//#define DRV_DEBUG #define LOG_TAG "drv.spi" -#define DBG_LVL DBG_INFO -#include +#include "drv_log.h" #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) -static rt_err_t _spi_configure(struct rt_spi_device *spi_drv, struct rt_spi_configuration *cfg) +static struct apm32_spi_config spi_config[] = { +#ifdef BSP_USING_SPI1 + {SPI1, "spi1"}, +#endif + +#ifdef BSP_USING_SPI2 + {SPI2, "spi2"}, +#endif + +#ifdef BSP_USING_SPI3 + {SPI3, "spi3"}, +#endif +}; + +static struct apm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_T *cs_gpiox, uint16_t cs_gpio_pin) { - RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct apm32_spi_cs *cs_pin; + GPIO_Config_T GPIO_InitStructure; + + /* initialize the cs pin && select the slave */ +#if defined(SOC_SERIES_APM32F0) + GPIO_ConfigStructInit(&GPIO_InitStructure); + GPIO_InitStructure.pin = cs_gpio_pin; + GPIO_InitStructure.speed = GPIO_SPEED_50MHz; + GPIO_InitStructure.mode = GPIO_MODE_OUT; + GPIO_InitStructure.outtype = GPIO_OUT_TYPE_PP; + GPIO_InitStructure.pupd = GPIO_PUPD_NO; + GPIO_Config(cs_gpiox, &GPIO_InitStructure); + GPIO_WriteBitValue(cs_gpiox, cs_gpio_pin, Bit_SET); +#elif defined(SOC_SERIES_APM32F1) + GPIO_ConfigStructInit(&GPIO_InitStructure); + GPIO_InitStructure.pin = cs_gpio_pin; + GPIO_InitStructure.mode = GPIO_MODE_OUT_PP; + GPIO_InitStructure.speed = GPIO_SPEED_50MHz; + GPIO_Config(cs_gpiox, &GPIO_InitStructure); + GPIO_WriteBitValue(cs_gpiox, cs_gpio_pin, BIT_SET); +#elif defined(SOC_SERIES_APM32F4) + GPIO_ConfigStructInit(&GPIO_InitStructure); + GPIO_InitStructure.pin = cs_gpio_pin; + GPIO_InitStructure.speed = GPIO_SPEED_100MHz; + GPIO_InitStructure.mode = GPIO_MODE_OUT; + GPIO_InitStructure.otype = GPIO_OTYPE_PP; + GPIO_InitStructure.pupd = GPIO_PUPD_NOPULL; + GPIO_Config(cs_gpiox, &GPIO_InitStructure); + GPIO_WriteBitValue(cs_gpiox, cs_gpio_pin, BIT_SET); +#endif + + /* attach the device to spi bus */ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct apm32_spi_cs *)rt_malloc(sizeof(struct apm32_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->GPIOx = cs_gpiox; + cs_pin->GPIO_Pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s attach to %s done", device_name, bus_name); + + return result; +} + +static rt_err_t apm32_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(device != RT_NULL); RT_ASSERT(cfg != RT_NULL); + SPI_Config_T hw_spi_config; - SPI_T *spi = (SPI_T *)spi_drv->bus->parent.user_data; + + struct rt_spi_bus * apm32_spi_bus = (struct rt_spi_bus *)device->bus; + struct apm32_spi *spi_device = (struct apm32_spi *)apm32_spi_bus->parent.user_data; + SPI_T *spi = spi_device->config->spi_x; + uint32_t hw_spi_apb_clock; #if (DBG_LVL == DBG_LOG) uint32_t hw_spi_sys_clock = RCM_ReadSYSCLKFreq(); #endif + + /* apm32 spi gpio init and enable clock */ + extern void apm32_msp_spi_init(void *Instance); + apm32_msp_spi_init(spi); + /* apm32 spi init */ hw_spi_config.mode = (cfg->mode & RT_SPI_SLAVE) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; hw_spi_config.direction = (cfg->mode & RT_SPI_3WIRE) ? SPI_DIRECTION_1LINE_RX : SPI_DIRECTION_2LINES_FULLDUPLEX; hw_spi_config.phase = (cfg->mode & RT_SPI_CPHA) ? SPI_CLKPHA_2EDGE : SPI_CLKPHA_1EDGE; hw_spi_config.polarity = (cfg->mode & RT_SPI_CPOL) ? SPI_CLKPOL_HIGH : SPI_CLKPOL_LOW; +#if defined(SOC_SERIES_APM32F0) + hw_spi_config.slaveSelect = (cfg->mode & RT_SPI_NO_CS) ? SPI_SSC_DISABLE : SPI_SSC_ENABLE; + hw_spi_config.firstBit = (cfg->mode & RT_SPI_MSB) ? SPI_FIRST_BIT_MSB : SPI_FIRST_BIT_LSB; +#else hw_spi_config.nss = (cfg->mode & RT_SPI_NO_CS) ? SPI_NSS_HARD : SPI_NSS_SOFT; hw_spi_config.firstBit = (cfg->mode & RT_SPI_MSB) ? SPI_FIRSTBIT_MSB : SPI_FIRSTBIT_LSB; - +#endif + if (cfg->data_width == 8) { hw_spi_config.length = SPI_DATA_LENGTH_8B; @@ -48,7 +142,18 @@ static rt_err_t _spi_configure(struct rt_spi_device *spi_drv, struct rt_spi_conf return RT_EIO; } - RCM_ReadPCLKFreq(NULL, &hw_spi_apb_clock); +#if defined(SOC_SERIES_APM32F0) + hw_spi_apb_clock = RCM_ReadPCLKFreq(); +#else + if (spi == SPI1) + { + RCM_ReadPCLKFreq(NULL, &hw_spi_apb_clock); + } + else + { + RCM_ReadPCLKFreq(&hw_spi_apb_clock, NULL); + } +#endif if (cfg->max_hz >= hw_spi_apb_clock / 2) { @@ -80,32 +185,46 @@ static rt_err_t _spi_configure(struct rt_spi_device *spi_drv, struct rt_spi_conf } else { - /* min prescaler 256 */ + /* min prescaler 256 */ hw_spi_config.baudrateDiv = SPI_BAUDRATE_DIV_256; } LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d", hw_spi_sys_clock, hw_spi_apb_clock, cfg->max_hz, hw_spi_config.baudrateDiv); - + +#if defined(SOC_SERIES_APM32F0) + SPI_DisableCRC(spi); + SPI_EnableSSoutput(spi); + SPI_ConfigFIFOThreshold(spi, SPI_RXFIFO_QUARTER); +#endif + SPI_Config(spi, &hw_spi_config); SPI_Enable(spi); return RT_EOK; } -static rt_uint32_t _spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +static rt_uint32_t apm32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) { RT_ASSERT(device != NULL); RT_ASSERT(message != NULL); - rt_base_t cs_pin = (rt_base_t)device->parent.user_data; - SPI_T *spi = (SPI_T *)device->bus->parent.user_data; struct rt_spi_configuration *config = &device->config; + + struct apm32_spi_cs *cs = device->parent.user_data; + + struct rt_spi_bus * apm32_spi_bus = (struct rt_spi_bus *)device->bus; + struct apm32_spi *spi_device = (struct apm32_spi *)apm32_spi_bus->parent.user_data; + SPI_T *spi = spi_device->config->spi_x; /* take CS */ if (message->cs_take) { - rt_pin_write(cs_pin, PIN_LOW); +#if defined(SOC_SERIES_APM32F0) + GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, (GPIO_BSRET_T)RESET); +#else + GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, RESET); +#endif LOG_D("spi take cs\n"); } @@ -126,16 +245,24 @@ static rt_uint32_t _spi_xfer(struct rt_spi_device *device, struct rt_spi_message data = *send_ptr++; } +#if defined(SOC_SERIES_APM32F0) + /* Wait until the transmit buffer is empty */ + while (SPI_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET); + SPI_TxData8(spi, data); + + /* Wait until a data is received */ + while (SPI_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET); + data = SPI_RxData8(spi); +#else /* Wait until the transmit buffer is empty */ while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET); - SPI_I2S_TxData(spi, data); /* Wait until a data is received */ while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET); - data = SPI_I2S_RxData(spi); - +#endif + if (recv_ptr != RT_NULL) { *recv_ptr++ = data; @@ -157,17 +284,27 @@ static rt_uint32_t _spi_xfer(struct rt_spi_device *device, struct rt_spi_message { data = *send_ptr++; } - - /*Wait until the transmit buffer is empty */ + +#if defined(SOC_SERIES_APM32F0) + /* Wait until the transmit buffer is empty */ + while (SPI_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET); + SPI_I2S_TxData16(spi, data); + + /* Wait until a data is received */ + while (SPI_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET); + data = SPI_I2S_RxData16(spi); +#else + /* Wait until the transmit buffer is empty */ while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_TXBE) == RESET); /* Send the byte */ SPI_I2S_TxData(spi, data); - /*Wait until a data is received */ + /* Wait until a data is received */ while (SPI_I2S_ReadStatusFlag(spi, SPI_FLAG_RXBNE) == RESET); /* Get the received data */ data = SPI_I2S_RxData(spi); - +#endif + if (recv_ptr != RT_NULL) { *recv_ptr++ = data; @@ -178,164 +315,37 @@ static rt_uint32_t _spi_xfer(struct rt_spi_device *device, struct rt_spi_message /* release CS */ if (message->cs_release) { - rt_pin_write(cs_pin, PIN_HIGH); +#if defined(SOC_SERIES_APM32F0) + GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, (GPIO_BSRET_T)SET); +#else + GPIO_WriteBitValue(cs->GPIOx, cs->GPIO_Pin, SET); +#endif LOG_D("spi release cs\n"); } return message->length; }; -static const struct rt_spi_ops _spi_ops = +static const struct rt_spi_ops apm32_spi_ops = { - _spi_configure, - _spi_xfer + apm32_spi_configure, + apm32_spi_xfer }; static int rt_hw_spi_init(void) { - int result = 0; - GPIO_Config_T gpio_config; + rt_err_t result; + + for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++) + { + spi_bus_obj[i].config = &spi_config[i]; + spi_bus_obj[i].spi_bus.parent.user_data = (void *)&spi_bus_obj[i]; + result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].spi_bus_name, &apm32_spi_ops); + RT_ASSERT(result == RT_EOK); -#ifdef APM32F10X_HD -#ifdef BSP_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; + LOG_D("%s bus init done", spi_config[i].spi_bus_name); + } - result = rt_spi_bus_register(&spi_bus1, "spi1", &_spi_ops); - - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SPI1); - - /* SPI1_SCK(PA5) SPI1_MOSI(PA7) */ - gpio_config.mode = GPIO_MODE_AF_PP; - gpio_config.speed = GPIO_SPEED_50MHz; - gpio_config.pin = (GPIO_PIN_5 | GPIO_PIN_7); - GPIO_Config(GPIOA, &gpio_config); - /* SPI1_MISO(PA6) */ - gpio_config.mode = GPIO_MODE_IN_FLOATING; - gpio_config.speed = GPIO_SPEED_50MHz; - gpio_config.pin = GPIO_PIN_6; - GPIO_Config(GPIOA, &gpio_config); -#endif - -#ifdef BSP_USING_SPI2 - static struct rt_spi_bus spi_bus2; - spi_bus2.parent.user_data = (void *)SPI2; - - result = rt_spi_bus_register(&spi_bus2, "spi2", &_spi_ops); - - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB); - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_SPI2); - - /* SPI2_SCK(PB13) SPI2_MOSI(PB15) */ - gpio_config.mode = GPIO_MODE_AF_PP; - gpio_config.speed = GPIO_SPEED_50MHz; - gpio_config.pin = (GPIO_PIN_13 | GPIO_PIN_15); - GPIO_Config(GPIOB, &gpio_config); - /* SPI2_MISO(PB14) */ - gpio_config.mode = GPIO_MODE_IN_FLOATING; - gpio_config.speed = GPIO_SPEED_50MHz; - gpio_config.pin = GPIO_PIN_14; - GPIO_Config(GPIOB, &gpio_config); -#endif - -#ifdef BSP_USING_SPI3 - static struct rt_spi_bus spi_bus3; - spi_bus3.parent.user_data = (void *)SPI3; - - result = rt_spi_bus_register(&spi_bus3, "spi3", &_spi_ops); - - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB); - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_SPI3); - - /* SPI3_SCK(PB3) SPI3_MOSI(PB5) */ - gpio_config.mode = GPIO_MODE_AF_PP; - gpio_config.speed = GPIO_SPEED_50MHz; - gpio_config.pin = (GPIO_PIN_3 | GPIO_PIN_5); - GPIO_Config(GPIOB, &gpio_config); - /* SPI3_MISO(PB4) */ - gpio_config.mode = GPIO_MODE_IN_FLOATING; - gpio_config.speed = GPIO_SPEED_50MHz; - gpio_config.pin = GPIO_PIN_4; - GPIO_Config(GPIOB, &gpio_config); -#endif -#elif APM32F40X -#ifdef BSP_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; - - result = rt_spi_bus_register(&spi_bus1, "spi1", &_spi_ops); - - RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA); - RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SPI1); - - /* Config SPI1 PinAF */ - GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_4, GPIO_AF_SPI1); - GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_5, GPIO_AF_SPI1); - GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_6, GPIO_AF_SPI1); - GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_7, GPIO_AF_SPI1); - - /* SPI1_NSS(PA4) SPI1_SCK(PA5) SPI1_MISO(PA6) SPI1_MOSI(PA7) */ - gpio_config.mode = GPIO_MODE_AF; - gpio_config.speed = GPIO_SPEED_100MHz; - gpio_config.otype = GPIO_OTYPE_PP; - gpio_config.pupd = GPIO_PUPD_NOPULL; - gpio_config.pin = GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; - GPIO_Config(GPIOA, &gpio_config); -#endif - -#ifdef BSP_USING_SPI2 - static struct rt_spi_bus spi_bus2; - spi_bus2.parent.user_data = (void *)SPI2; - - result = rt_spi_bus_register(&spi_bus2, "spi2", &_spi_ops); - - RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOB); - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_SPI2); - - /* Config SPI2 PinAF */ - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_12, GPIO_AF_SPI2); - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_13, GPIO_AF_SPI2); - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_14, GPIO_AF_SPI2); - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_15, GPIO_AF_SPI2); - - /* SPI2_NSS(PB12) SPI2_SCK(PB13) SPI2_MISO(PB14) SPI2_MOSI(PB15) */ - gpio_config.mode = GPIO_MODE_AF; - gpio_config.speed = GPIO_SPEED_100MHz; - gpio_config.otype = GPIO_OTYPE_PP; - gpio_config.pupd = GPIO_PUPD_NOPULL; - gpio_config.pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; - GPIO_Config(GPIOB, &gpio_config); -#endif - -#ifdef BSP_USING_SPI3 - static struct rt_spi_bus spi_bus3; - spi_bus3.parent.user_data = (void *)SPI3; - - result = rt_spi_bus_register(&spi_bus3, "spi3", &_spi_ops); - - RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA); - RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOB); - RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_SPI3); - - /* Config SPI3 PinAF */ - GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_4, GPIO_AF_SPI3); - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_3, GPIO_AF_SPI3); - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_4, GPIO_AF_SPI3); - GPIO_ConfigPinAF(GPIOB, GPIO_PIN_SOURCE_5, GPIO_AF_SPI3); - - /* SPI3_SCK(PB3) SPI3_MISO(PB4) SPI3_MOSI(PB5) */ - gpio_config.mode = GPIO_MODE_AF; - gpio_config.speed = GPIO_SPEED_100MHz; - gpio_config.otype = GPIO_OTYPE_PP; - gpio_config.pupd = GPIO_PUPD_NOPULL; - gpio_config.pin = GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; - GPIO_Config(GPIOB, &gpio_config); - /* SPI3_NSS(PA4) */ - gpio_config.pin = GPIO_PIN_4; - GPIO_Config(GPIOA, &gpio_config); -#endif -#endif return result; } INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/apm32/libraries/Drivers/drv_spi.h b/bsp/apm32/libraries/Drivers/drv_spi.h index e4591352f5..e66643ed53 100644 --- a/bsp/apm32/libraries/Drivers/drv_spi.h +++ b/bsp/apm32/libraries/Drivers/drv_spi.h @@ -13,10 +13,24 @@ #include "board.h" +struct apm32_spi_config +{ + SPI_T *spi_x; + char *spi_bus_name; +}; + +struct apm32_spi +{ + struct apm32_spi_config *config; + struct rt_spi_bus spi_bus; +}; + struct apm32_spi_cs { GPIO_T *GPIOx; uint16_t GPIO_Pin; }; +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_T *cs_gpiox, uint16_t cs_gpio_pin); + #endif /*__DRV_SPI_H__ */ diff --git a/bsp/apm32/libraries/Drivers/drv_usart.c b/bsp/apm32/libraries/Drivers/drv_usart.c index d7d27de8a6..9261510031 100644 --- a/bsp/apm32/libraries/Drivers/drv_usart.c +++ b/bsp/apm32/libraries/Drivers/drv_usart.c @@ -6,14 +6,16 @@ * Change Logs: * Date Author Notes * 2020-08-20 Abbcc first version + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include "board.h" #include "drv_usart.h" - #ifdef RT_USING_SERIAL -#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \ + !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) #error "Please define at least one BSP_USING_UARTx" /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif @@ -34,6 +36,18 @@ enum #ifdef BSP_USING_UART2 UART2_INDEX, #endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif }; static struct apm32_usart usart_config[] = @@ -52,9 +66,39 @@ static struct apm32_usart usart_config[] = USART2_IRQn, }, #endif +#if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32F4) +#ifdef BSP_USING_UART3 + { + "uart3", + USART3, + USART3_IRQn, + }, +#endif +#ifdef BSP_USING_UART4 + { + "uart4", + UART4, + UART4_IRQn, + }, +#endif +#ifdef BSP_USING_UART5 + { + "uart5", + UART5, + UART5_IRQn, + }, +#endif +#ifdef BSP_USING_UART6 + { + "uart6", + USART6, + USART6_IRQn, + }, +#endif +#endif }; -static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +static rt_err_t apm32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { USART_Config_T USART_ConfigStruct; RT_ASSERT(serial != RT_NULL); @@ -64,10 +108,38 @@ static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_c apm32_usart_init(); - USART_ConfigStruct.baudRate = cfg->baud_rate;; - USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE; + USART_ConfigStruct.baudRate = cfg->baud_rate; USART_ConfigStruct.mode = USART_MODE_TX_RX; USART_ConfigStruct.parity = USART_PARITY_NONE; + +#if defined(SOC_SERIES_APM32F0) + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + + USART_ConfigStruct.hardwareFlowCtrl = USART_FLOW_CTRL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + USART_ConfigStruct.hardwareFlowCtrl = USART_FLOW_CTRL_RTS_CTS; + break; + default: + USART_ConfigStruct.hardwareFlowCtrl = USART_FLOW_CTRL_NONE; + break; + } +#else + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_RTS_CTS; + break; + default: + USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE; + break; + } +#endif switch (cfg->data_bits) { @@ -120,7 +192,7 @@ static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_c return RT_EOK; } -static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +static rt_err_t apm32_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { struct apm32_usart *usart; @@ -129,6 +201,30 @@ static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *ar usart = (struct apm32_usart *) serial->parent.user_data; RT_ASSERT(usart != RT_NULL); +#if defined(SOC_SERIES_APM32F0) + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + + /* disable rx irq */ + NVIC_DisableIRQRequest(usart->irq_type); + + /* disable interrupt */ + USART_DisableInterrupt(usart->usartx, USART_INT_RXBNEIE); + + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQRequest(usart->irq_type, 1); + + /* enable interrupt */ + USART_EnableInterrupt(usart->usartx, USART_INT_RXBNEIE); + break; + } +#else switch (cmd) { /* disable interrupt */ @@ -150,12 +246,12 @@ static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *ar /* enable interrupt */ USART_EnableInterrupt(usart->usartx, USART_INT_RXBNE); break; - } +#endif return RT_EOK; } -static int _uart_putc(struct rt_serial_device *serial, char c) +static int apm32_uart_putc(struct rt_serial_device *serial, char c) { struct apm32_usart *usart; RT_ASSERT(serial != RT_NULL); @@ -171,7 +267,7 @@ static int _uart_putc(struct rt_serial_device *serial, char c) return 1; } -static int _uart_getc(struct rt_serial_device *serial) +static int apm32_uart_getc(struct rt_serial_device *serial) { int ch; struct apm32_usart *usart; @@ -197,33 +293,75 @@ static void usart_isr(struct rt_serial_device *serial) { struct apm32_usart *usart; - RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL); usart = (struct apm32_usart *) serial->parent.user_data; RT_ASSERT(usart != RT_NULL); /* UART in mode Receiver */ +#if defined(SOC_SERIES_APM32F0) + if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) && + (USART_ReadIntFlag(usart->usartx, USART_INT_FLAG_RXBNE) != RESET)) +#else if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) && (USART_ReadIntFlag(usart->usartx, USART_INT_RXBNE) != RESET)) +#endif { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - USART_ClearStatusFlag(usart->usartx, USART_FLAG_RXBNE); - USART_ClearIntFlag(usart->usartx, USART_INT_RXBNE); } - else { +#if defined(SOC_SERIES_APM32F0) + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_OVRE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_OVRE); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_NEF) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_NEF); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_FEF) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_FEF); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_PEF) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_PEF); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_CTSF) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_CTSF); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_LBDF) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_LBDF); + } +#else + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_OVRE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_OVRE); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_NE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_NE); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_FE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_FE); + } + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_PE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_PE); + } if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_CTS) != RESET) { USART_ClearStatusFlag(usart->usartx, USART_FLAG_CTS); } - if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_LBD) != RESET) { USART_ClearStatusFlag(usart->usartx, USART_FLAG_LBD); } - +#endif if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXBE) != RESET) { USART_ClearStatusFlag(usart->usartx, USART_FLAG_TXBE); @@ -256,15 +394,66 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } - #endif /* BSP_USING_UART2 */ +#if defined(BSP_USING_UART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART3_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +void USART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART6_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART6 */ + static const struct rt_uart_ops apm32_usart_ops = { - .configure = _uart_configure, - .control = _uart_control, - .putc = _uart_putc, - .getc = _uart_getc, + .configure = apm32_uart_configure, + .control = apm32_uart_control, + .putc = apm32_uart_putc, + .getc = apm32_uart_getc, .dma_transmit = RT_NULL }; diff --git a/bsp/apm32/libraries/Drivers/drv_wdt.c b/bsp/apm32/libraries/Drivers/drv_wdt.c index 829ba48ca5..11e87ae727 100644 --- a/bsp/apm32/libraries/Drivers/drv_wdt.c +++ b/bsp/apm32/libraries/Drivers/drv_wdt.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-03-04 stevetong459 first version + * 2022-12-26 luobeihai add apm32F0 serie MCU support */ #include @@ -33,7 +34,7 @@ typedef struct static apm32_wdt_t wdt_config; -static rt_err_t _iwdt_init(rt_watchdog_t *wdt) +static rt_err_t apm32_iwdt_init(rt_watchdog_t *wdt) { rt_uint32_t counter = 0; @@ -54,7 +55,11 @@ static rt_err_t _iwdt_init(rt_watchdog_t *wdt) wdt_config.min_threshold, wdt_config.max_threshold); +#if defined(SOC_SERIES_APM32F0) + while (IWDT_ReadStatusFlag(IWDT_FLAG_DIVU)) +#else while (IWDT_ReadStatusFlag(IWDT_FLAG_PSCU)) +#endif { if (++counter > DRV_WDT_TIME_OUT) { @@ -62,8 +67,15 @@ static rt_err_t _iwdt_init(rt_watchdog_t *wdt) return -RT_ERROR; } } + IWDT_EnableWriteAccess(); + +#if defined(SOC_SERIES_APM32F0) + IWDT_ConfigDivider(IWDT_DIV_256); +#else IWDT_ConfigDivider(IWDT_DIVIDER_256); +#endif + IWDT_DisableWriteAccess(); return RT_EOK; @@ -76,7 +88,7 @@ static rt_err_t _iwdt_init(rt_watchdog_t *wdt) * * @return RT_EOK indicates successful , other value indicates failed. */ -static rt_err_t _iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +static rt_err_t apm32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) { volatile rt_uint32_t param, counter = 0; @@ -125,15 +137,15 @@ static rt_err_t _iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) return RT_EOK; } -static struct rt_watchdog_ops _wdt_ops = +static struct rt_watchdog_ops apm32_wdt_ops = { - _iwdt_init, - _iwdt_control, + apm32_iwdt_init, + apm32_iwdt_control, }; static int rt_hw_wdt_init(void) { - wdt_config.wdt.ops = &_wdt_ops; + wdt_config.wdt.ops = &apm32_wdt_ops; /* register watchdog device */ if (rt_hw_watchdog_register(&wdt_config.wdt, "wdt", \ RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) diff --git a/bsp/apm32/libraries/Kconfig b/bsp/apm32/libraries/Kconfig index 8ebcd050fd..73e938b2c0 100644 --- a/bsp/apm32/libraries/Kconfig +++ b/bsp/apm32/libraries/Kconfig @@ -1,6 +1,11 @@ config SOC_FAMILY_APM32 bool +config SOC_SERIES_APM32F0 + bool + select ARCH_ARM_CORTEX_M0 + select SOC_FAMILY_APM32 + config SOC_SERIES_APM32F1 bool select ARCH_ARM_CORTEX_M3