support T-HEAD Xuantie-E9xx Series CPU on Smart-EVB, eg. E906/F/D/P, E907/F/D/P

libcpu/risc-v/SConscript

@@ -10,7 +10,7 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-if   rtconfig.CPU == "e906" :
+if   rtconfig.CPU == "e9xx" :
     group = group
 elif rtconfig.CPU == "nuclei" :
     group = group
@@ -20,7 +20,7 @@ else :
     group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
 
 # cpu porting code files
-if  rtconfig.CPU == "e906" :
+if  rtconfig.CPU == "e9xx" :
     group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
 else :
     group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))

libcpu/risc-v/t-head/e9xx/context_gcc.S

@@ -181,7 +181,11 @@ PendSV_Handler:
     FSTORE  f31, 31 * FREGBYTES(sp)
 #endif
 
+#ifdef ARCH_RISCV_DSP
+    addi    sp, sp, -33 * REGBYTES
+#else
     addi    sp, sp, -32 * REGBYTES
+#endif
 
     STORE   x1, 1 * REGBYTES(sp)
     csrr    x1, mepc
@@ -221,6 +225,10 @@ PendSV_Handler:
     STORE   x29, 29 * REGBYTES(sp)
     STORE   x30, 30 * REGBYTES(sp)
     STORE   x31, 31 * REGBYTES(sp)
+#ifdef ARCH_RISCV_DSP
+    csrr    t0, vxsat
+    STORE   t0, 32 * REGBYTES(sp)
+#endif
 
     /* store from_thread sp */
     la      t0, rt_interrupt_from_thread
@@ -237,6 +245,12 @@ PendSV_Handler:
     lw      t0, (t0)
     LOAD    sp, (t0)
 
+
+#ifdef ARCH_RISCV_DSP
+    LOAD    a1, 32 * REGBYTES(sp)
+    csrw    vxsat, a1
+#endif
+
     /* restore ra to mepc */
     LOAD    a1, 0 * REGBYTES(sp)
     csrw    mepc, a1
@@ -277,7 +291,11 @@ PendSV_Handler:
     LOAD    x30, 30 * REGBYTES(sp)
     LOAD    x31, 31 * REGBYTES(sp)
 
+#ifdef ARCH_RISCV_DSP
+    addi    sp, sp, 33 * REGBYTES
+#else
     addi    sp, sp, 32 * REGBYTES
+#endif
 
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)

libcpu/risc-v/t-head/e9xx/cpuport.c

@@ -53,6 +53,9 @@ struct rt_hw_stack_frame
     rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
     rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
     rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+#ifdef ARCH_RISCV_DSP
+    rt_ubase_t vxsat;      /* P-ext vxsat reg */
+#endif
 #ifdef ARCH_RISCV_FPU
     rv_floatreg_t f0;      /* f0  */
     rv_floatreg_t f1;      /* f1  */