diff --git a/bsp/yichip/yc3121-pos/.config b/bsp/yichip/yc3121-pos/.config new file mode 100644 index 0000000000..eca18829fa --- /dev/null +++ b/bsp/yichip/yc3121-pos/.config @@ -0,0 +1,582 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_SOC_SWM320VET7=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set diff --git a/bsp/yichip/yc3121-pos/.gitignore b/bsp/yichip/yc3121-pos/.gitignore new file mode 100644 index 0000000000..4a42abf20f --- /dev/null +++ b/bsp/yichip/yc3121-pos/.gitignore @@ -0,0 +1,44 @@ +./.vscode/* +./build/* +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/yichip/yc3121-pos/.ignore_format.yml b/bsp/yichip/yc3121-pos/.ignore_format.yml new file mode 100644 index 0000000000..2a686aabbe --- /dev/null +++ b/bsp/yichip/yc3121-pos/.ignore_format.yml @@ -0,0 +1,9 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + + +dir_path: +- Libraries diff --git a/bsp/yichip/yc3121-pos/Kconfig b/bsp/yichip/yc3121-pos/Kconfig new file mode 100644 index 0000000000..59dcef1b29 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SWM320VET7 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/yichip/yc3121-pos/Libraries/SConscript b/bsp/yichip/yc3121-pos/Libraries/SConscript new file mode 100644 index 0000000000..4e245383ba --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/SConscript @@ -0,0 +1,17 @@ +from building import * +import rtconfig +cwd = GetCurrentDir() +src = Glob('sdk/*.c') +CPPPATH = [cwd + '/sdk', cwd + '/core', cwd] + +src += Glob('core/*.c') + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['startup/flash_start_gcc.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['startup/startup.s', 'startup/flash_start.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['startup/flash_start_iar.s'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/yichip/yc3121-pos/Libraries/core/board_config.h b/bsp/yichip/yc3121-pos/Libraries/core/board_config.h new file mode 100644 index 0000000000..306d8891ba --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/board_config.h @@ -0,0 +1,275 @@ +/* +File Name : board_config.h +Author : Yichip +Version : V1.0 +Date : 2020/07/17 +Description : board I/O config file. +*/ + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include "yc3121.h" +#include "yc_gpio.h" +#include "yc_exti.h" +#include "yc_spi.h" + +//开发板选择 +#define MPOS_BOARD_V2_1 0 +#define EPOS_BOARD_V1_0 1 +#define BOARD_VER EPOS_BOARD_V1_0 + +//ADC管脚配置 +#define ADC_IO_PORT GPIOC +#define ADC2_IO_PIN GPIO_Pin_7 +#define ADC3_IO_PIN GPIO_Pin_8 + +//外部中断管脚配置 +#define EXTI_PORT EXTI_Line0 +#define EXTI_PIN EXTI_PinSource14 + +#if (BOARD_VER == MPOS_BOARD_V2_1) +//DEBUG串口配置 +#define UARTBAUD 921600 +#define UART0_TX_PORT GPIOA +#define UART0_TX_PIN GPIO_Pin_1 +#define UART0_RX_PORT GPIOA +#define UART0_RX_PIN GPIO_Pin_0 + +//串口1配置 +#define UART1_TX_PORT GPIOA +#define UART1_TX_PIN GPIO_Pin_14 +#define UART1_RX_PORT GPIOA +#define UART1_RX_PIN GPIO_Pin_15 + +//BEEP驱动IO +#define BEEP_PWM 0 +#define BEEP_PORT GPIOA +#define BEEP_PIN GPIO_Pin_11 + +//IC卡在位检测IO +#define DET_PORT GPIOC +#define DET_PIN GPIO_Pin_12 + +//NFC IO +#define NFC_SPI SPI1 +#define NFC_12M_CLK_PORT GPIOA +#define NFC_12M_CLK_PIN GPIO_Pin_3 + +#define NFC_RST_PORT GPIOA +#define NFC_RST_PIN GPIO_Pin_4 + +#define NFC_SPI_MISO_PORT GPIOB +#define NFC_SPI_MISO_PIN GPIO_Pin_2 + +#define NFC_SPI_MOSI_PORT GPIOB +#define NFC_SPI_MOSI_PIN GPIO_Pin_1 + +#define NFC_SPI_SCL_PORT GPIOB +#define NFC_SPI_SCL_PIN GPIO_Pin_0 + +#define NFC_SPI_CS_PORT GPIOB +#define NFC_SPI_CS_PIN GPIO_Pin_6 + +//EEPROM写保护控制IO +#define IIC_WP2_PORT GPIOB +#define IIC_WP2_PIN GPIO_Pin_0 +#define IIC_WP128_PORT GPIOC +#define IIC_WP128_PIN GPIO_Pin_10 + +//IIC驱动IO +#define IIC_SDA_PORT GPIOB +#define IIC_SDA_PIN GPIO_Pin_2 +#define IIC_SCL_PORT GPIOA +#define IIC_SCL_PIN GPIO_Pin_11 + +//KEYBOARD配置 +#define GPIO_GROUP_Line_1 GPIOC +#define Line_1 GPIO_Pin_7 + +#define GPIO_GROUP_Line_2 GPIOC +#define Line_2 GPIO_Pin_9 + +#define GPIO_GROUP_Line_3 GPIOC +#define Line_3 GPIO_Pin_8 + +#define GPIO_GROUP_Line_4 GPIOC +#define Line_4 GPIO_Pin_10 + +#define GPIO_GROUP_Line_5 GPIOC +#define Line_5 GPIO_Pin_11 + +//LCD屏幕驱动配置 +#define LCD_SPI SPI0 +#define LCDSDA_PIN GPIO_Pin_1 +#define LCDSDA_PORT GPIOB +#define LCDSCL_PIN GPIO_Pin_0 +#define LCDSCL_PORT GPIOB +#define LCDCS_PIN GPIO_Pin_6 +#define LCDCS_PORT GPIOC +#define LCDRST_PIN GPIO_Pin_5 +#define LCDRST_PORT GPIOA +#define LCDA0_PIN GPIO_Pin_10 +#define LCDA0_PORT GPIOA +#define LCDBL_PIN GPIO_Pin_2 +#define LCDBL_PORT GPIOA + +#elif (BOARD_VER == EPOS_BOARD_V1_0) +//DEBUG串口配置 +#define UARTBAUD 921600 +#define UART0_TX_PORT GPIOA +#define UART0_TX_PIN GPIO_Pin_1 +#define UART0_RX_PORT GPIOA +#define UART0_RX_PIN GPIO_Pin_0 + +//串口1配置 +#define UART1_TX_PORT GPIOA +#define UART1_TX_PIN GPIO_Pin_14 +#define UART1_RX_PORT GPIOA +#define UART1_RX_PIN GPIO_Pin_15 + +//BEEP驱动IO +#define BEEP_PWM 0 +#define BEEP_PORT GPIOC +#define BEEP_PIN GPIO_Pin_1 + +//IC卡在位检测IO +#define DET_PORT GPIOA +#define DET_PIN GPIO_Pin_4 + +//NFC IO +#define NFC_SPI SPI1 +#define NFC_12M_CLK_PORT GPIOC +#define NFC_12M_CLK_PIN GPIO_Pin_10 + +#define NFC_RST_PORT GPIOC +#define NFC_RST_PIN GPIO_Pin_5 + +#define NFC_TVDD_PORT GPIOC +#define NFC_TVDD_PIN GPIO_Pin_4 + +#define NFC_SPI_MISO_PORT GPIOC +#define NFC_SPI_MISO_PIN GPIO_Pin_6 + +#define NFC_SPI_MOSI_PORT GPIOC +#define NFC_SPI_MOSI_PIN GPIO_Pin_7 + +#define NFC_SPI_SCL_PORT GPIOC +#define NFC_SPI_SCL_PIN GPIO_Pin_8 + +#define NFC_SPI_CS_PORT GPIOC +#define NFC_SPI_CS_PIN GPIO_Pin_9 + +//IIC驱动IO + +//KEYBOARD配置 +#define KEY_PORT_1 GPIOA +#define KEY_PIN_1 GPIO_Pin_9 + +#define KEY_PORT_2 GPIOA +#define KEY_PIN_2 GPIO_Pin_15 + +#define KEY_PORT_3 GPIOA +#define KEY_PIN_3 GPIO_Pin_14 + +#define KEY_PORT_4 GPIOA +#define KEY_PIN_4 GPIO_Pin_8 + +#define KEY_PORT_5 GPIOA +#define KEY_PIN_5 GPIO_Pin_7 + +#define KEY_PORT_6 GPIOA +#define KEY_PIN_6 GPIO_Pin_6 + +//TFT屏幕驱动配置 +#define ST7789VTFTSPI SPI1 +#define ST7789_TFT_SDA_PIN GPIO_Pin_7 +#define ST7789_TFT_SDA_PORT GPIOC + +#define ST7789_TFT_A0_PIN GPIO_Pin_10 +#define ST7789_TFT_A0_PORT GPIOA + +#define ST7789_TFT_SCL_PIN GPIO_Pin_8 +#define ST7789_TFT_SCL_PORT GPIOC + +#define ST7789_TFT_RST_PIN GPIO_Pin_11 +#define ST7789_TFT_RST_PORT GPIOA + +#define ST7789_TFT_CS_PIN GPIO_Pin_5 +#define ST7789_TFT_CS_PORT GPIOA + +#define ST7789_TFT_BL_PIN GPIO_Pin_12 +#define ST7789_TFT_BL_PORT GPIOA +#define ST7789_TFT_BL_HIGH_LIGHT 1 + +/*QRdecode tft */ +//tft camera io +#define QR_CAMERA_FREQ 24 +#define QR_CAMERA_SDA 28 +#define QR_CAMERA_SCL 29 +#define QR_CAMERA_RST 32 +#define QR_CAMERA_PD 31//power down +#define QR_CAMERA_MCLK 35 +#define QR_CAMERA_PCLK 34 +#define QR_CAMERA_DATA 30 +#define QR_CAMERA_CS 42 + +//tft io +#define QR_TFT_RST (11) /*rst pin*/ +#define QR_TFT_CS ( 5) /*cs pin*/ +#define QR_TFT_CLK (40) /*clk pin*/ +#define QR_TFT_MOSI (39) /*mosi pin*/ +#define QR_TFT_A0 (10) /*a0 pin*/ +#define QR_TFT_BL (12 | (1 << 7)) /*bl pin*/ +#define QR_TFT_START_COLUMN ( (320 - 236) / 2 ) /*display center*/ + +//key io +#define QR_KEY_T_MATRIX ( 0) /*key mode :0: T matrix key,1:matrix key*/ +#define QR_KEY_LINE_NUM ( 6) /*Value range 0~10*/ +#define QR_KEY_COL_NUM ( 0) /*Value range (T matrix key: 0)*/ +#define QR_KEY_CANCEL_POSTION ( (5 << 4) | 6 ) /*Exit key*/ +#define QR_KEY_LINE_1 ( 9) /*GPIO pin*/ +#define QR_KEY_LINE_2 (15) /*GPIO pin*/ +#define QR_KEY_LINE_3 (14) /*GPIO pin*/ +#define QR_KEY_LINE_4 ( 8) /*GPIO pin*/ +#define QR_KEY_LINE_5 ( 7) /*GPIO pin*/ +#define QR_KEY_LINE_6 ( 6) /*GPIO pin*/ + +/*QRdecode lcd */ +//lcd io +#define QR_LCD_RST (14) +#define QR_LCD_CS (15) +#define QR_LCD_CLK (10) +#define QR_LCD_MOSI ( 3) +#define QR_LCD_A0 (11) +#define QR_LCD_BL (39 | (1 << 7)) +#define QR_LCD_SPI_BOUDSPEED (0xFF) +#define QR_LCD_BLANK_LINE_NUM ( 0) /*Value range 0~7*/ +#define QR_LCD_COLUMN_NUM (64) /*Value range 0~7*/ +#define QR_LCD_START_COLUMN ((128 - 64)/2) + +//lcd camera io + +#define QR_LCD_CAMERA_FREQ (24) +#define QR_LCD_CAMERA_SDA (17) +#define QR_LCD_CAMERA_SCL (16) +#define QR_LCD_CAMERA_RST (41) +#define QR_LCD_CAMERA_PD ( 5)//power down +#define QR_LCD_CAMERA_MCLK (40) +#define QR_LCD_CAMERA_PCLK (38) +#define QR_LCD_CAMERA_DATA ( 2) +#define QR_LCD_CAMERA_CS (42) + +/*touch*/ +#define TP_Y_HIGH_PORT GPIOA +#define TP_Y_HIGH_IO_PIN GPIO_Pin_4 +#define TP_Y_LOW_PORT GPIOC +#define TP_Y_LOW_IO_PIN GPIO_Pin_12 +#define TP_X_HIGH_PORT GPIOA +#define TP_X_HIGH_IO_PIN GPIO_Pin_13 +#define TP_X_LOW_PORT GPIOC +#define TP_X_LOW_IO_PIN GPIO_Pin_11 + +#endif + +#endif diff --git a/bsp/yichip/yc3121-pos/Libraries/core/misc.c b/bsp/yichip/yc3121-pos/Libraries/core/misc.c new file mode 100644 index 0000000000..24837c1c3b --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/misc.c @@ -0,0 +1,102 @@ +/* +File Name : board_config.h +Author : Yichip +Version : V1.0 +Date : 2020/07/17 +Description : misc file. +*/ + +#include "misc.h" + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) +#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) + +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/* End of group Configuration_of_CMSIS */ + +uint32_t NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + return SUCCESS; +} + +#define SBC_ICSR_PENDSV_IRQ 28 +void trigger_PendSV(void) +{ + SCB->ICSR |= (1 << SBC_ICSR_PENDSV_IRQ); +} + +void NVIC_EnableIRQ(IRQn_Type IRQnx) +{ + enable_intr((int)IRQnx); +} + +void NVIC_DisableIRQ(IRQn_Type IRQnx) +{ + disable_intr((int)IRQnx); +} + +void soft_reset(void) +{ + SYSCTRL_RST_EN |= 0x01; + SYSCTRL_RESET = 0x55; + while (1); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/core/misc.h b/bsp/yichip/yc3121-pos/Libraries/core/misc.h new file mode 100644 index 0000000000..519fc2c94b --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/misc.h @@ -0,0 +1,93 @@ +/* +File Name : board_config.h +Author : Yichip +Version : V1.0 +Date : 2020/07/17 +Description : misc file. +*/ + +#ifndef __MISC_H +#define __MISC_H +#include "yc3121.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum +{ + SVCall_IRQn = -5, //SVC_IRQHandler + PendSV_IRQn = -2, //PENDSV_IRQHandler + SysTick_IRQn = -1, //SYSTICK_IRQHandler + USB_IRQn = 0, + IIC_IRQn = 1, + QSPI_IRQn = 2, + SPI0_IRQn = 3, + SPI1_IRQn = 4, + UART0_IRQn = 5, + UART1_IRQn = 6, + MEMCP_IRQn = 7,//DMA MEM_TO_MEM + RSA_IRQn = 8, + SCI0_IRQn = 9, + SCI1_IRQn = 10, + BT_IRQn = 11, + GPIO_IRQn = 12, + TIM0_IRQn = 13, + TIM1_IRQn = 14, + TIM2_IRQn = 15, + TIM3_IRQn = 16, + TIM4_IRQn = 17, + TIM5_IRQn = 18, + TIM6_IRQn = 19, + TIM7_IRQn = 20, + TIM8_IRQn = 21, + SM4_IRQn = 22, + SEC_IRQn = 23, + MSR_IRQn = 24, + TRNG_IRQn = 25, + WDT_IRQn = 26 +} IRQn_Type; + +/** + * @brief Enable External Interrupt + * @param IRQnx IRQn External interrupt number. Value cannot be negative. + * @retval none + */ +void NVIC_EnableIRQ(IRQn_Type IRQnx); + +/** + * @brief Disable External Interrupt + * @param IRQnx IRQn External interrupt number. Value cannot be negative. + * @retval none + */ +void NVIC_DisableIRQ(IRQn_Type IRQnx); + +/** + * @brief Set Interrupt Priority + * @param IRQn Interrupt number. + * @retval SUCCESS or ERROR + */ +uint32_t NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); + + +/** + * @brief trigger PendSV Interrupt + * @param none + * @retval none + */ +void trigger_PendSV(void); + +/** + * @brief System Reset + * @param none + * @retval none + */ +void soft_reset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + diff --git a/bsp/yichip/yc3121-pos/Libraries/core/rom_api.h b/bsp/yichip/yc3121-pos/Libraries/core/rom_api.h new file mode 100644 index 0000000000..bd57d6056d --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/rom_api.h @@ -0,0 +1,42 @@ +/* +File Name : rom_api.h +Author : Yichip +Version : V1.0 +Date : 2020/02/11 +Description : rom fun information. +*/ + +#ifndef __ROM_API_H__ +#define __ROM_API_H__ + +/* TIMER */ +#define FUNC_DELAY_US_ADDR (0x4238 + 1) +#define FUNC_DELAY_MS_ADDR (0x425c + 1) + +/* OTP */ +#define FUNC_INIT_OTP_ADDR (0x442c + 1) +#define FUNC_DEINIT_OTP_ADDR (0x4480 + 1) +#define FUNC_READ_OTP_ADDR (0x449c + 1) +#define FUNC_WRITE_OTP_ADDR (0x4594 + 1) +#define FUNC_READ_CHIPID_ADDR (0x45d8 + 1) +#define FUNC_READ_CHIPLF_ADDR (0x45e6 + 1) + +/* LPM */ +#define FUNC_LPM_READ_ADDR (0x4c80 + 1) +#define FUNC_LPM_WRITE_ADDR (0x4c9c + 1) +#define FUNC_LPM_BT_WRITE_ADDR (0x4cb0 + 1) +#define FUNC_LPM_BT_READ_ADDR (0x4d24 + 1) +#define FUNC_LPM_SLEEP_ADDR (0x4d68 + 1) +#define FUNC_SETLPMVAL_ADDR (0x4280 + 1) + +/* QSPI */ +#define FUNC_ENC_WRITE_FLASH_ADDR (0x51f0 + 1) +#define FUNC_QSPI_FLASH_SECTORERASE_ADDR (0x48b4 + 1) +#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR (0x48c0 + 1) +#define FUNC_QSPI_FLASH_WRITE_ADDR (0x47f4 + 1) +#define FUNC_QSPI_FLASH_READ_ADDR (0x48f6 + 1) +#define FUNC_FLASH_BLANK_CHECK (0x513c + 1) +#define FUNC_PREFETCH (0x4404 + 1) +#define FUNC_READ_FLASH_ID (0x4960 + 1) + +#endif diff --git a/bsp/yichip/yc3121-pos/Libraries/core/system.c b/bsp/yichip/yc3121-pos/Libraries/core/system.c new file mode 100644 index 0000000000..99b3f8b928 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/system.c @@ -0,0 +1,254 @@ +/* +File Name : system.c +Author : Yichip +Version : V1.0 +Date : 2019/12/4 +Description : none. +*/ + +#include +#include "system.h" + +//***************************************************************************** +// +//! A simple MyPrintf function supporting \%c, \%d, \%p, \%s, \%u,\%x, and \%X. +//! +//! \param format is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! \return None. +// +//***************************************************************************** + +static const int8_t *const g_pcHex1 = "0123456789abcdef"; +static const int8_t *const g_pcHex2 = "0123456789ABCDEF"; + + +void printfsend(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + uint8_t printbuf[256]; + for (int i = 0; i < len; i++) + { + printbuf[i] = buf[i]; + } + + UART_SendBuf(UARTx, printbuf, len); +} + +void MyPrintf(char *format, ...) +{ + uint32_t ulIdx, ulValue, ulPos, ulCount, ulBase, ulNeg; + int8_t *pcStr, pcBuf[16], cFill; + char HexFormat; + va_list vaArgP; + + va_start(vaArgP, format); + + while (*format) + { + // Find the first non-% character, or the end of the string. + for (ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); ulIdx++) + { + } + + // Write this portion of the string. + if (ulIdx > 0) + { + printfsend(UART0, (uint8_t *)format, ulIdx); + } + + format += ulIdx; + + if (*format == '%') + { + format++; + + // Set the digit count to zero, and the fill character to space + // (i.e. to the defaults). + ulCount = 0; + cFill = ' '; + + again: + switch (*format++) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + if ((format[-1] == '0') && (ulCount == 0)) + { + cFill = '0'; + } + + ulCount *= 10; + ulCount += format[-1] - '0'; + + goto again; + } + + case 'c': + { + ulValue = va_arg(vaArgP, unsigned long); + printfsend(UART0, (uint8_t *)&ulValue, 1); + break; + } + + case 'd': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + + if ((long)ulValue < 0) + { + ulValue = -(long)ulValue; + ulNeg = 1; + } + else + { + ulNeg = 0; + } + + ulBase = 10; + goto convert; + } + + case 's': + { + pcStr = (int8_t *)va_arg(vaArgP, char *); + + for (ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) + { + } + + printfsend(UART0, (uint8_t *)pcStr, ulIdx); + + if (ulCount > ulIdx) + { + ulCount -= ulIdx; + while (ulCount--) + { + printfsend(UART0, (uint8_t *)" ", 1); + } + } + break; + } + + case 'u': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + ulBase = 10; + ulNeg = 0; + goto convert; + } + + case 'X': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + ulBase = 16; + ulNeg = 0; + HexFormat = 'X'; + goto convert; + } + + case 'x': + + case 'p': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + ulBase = 16; + ulNeg = 0; + HexFormat = 'x'; + + convert: + for (ulIdx = 1; + (((ulIdx * ulBase) <= ulValue) && + (((ulIdx * ulBase) / ulBase) == ulIdx)); + ulIdx *= ulBase, ulCount--) + { + } + + if (ulNeg) + { + ulCount--; + } + + if (ulNeg && (cFill == '0')) + { + pcBuf[ulPos++] = '-'; + ulNeg = 0; + } + + if ((ulCount > 1) && (ulCount < 16)) + { + for (ulCount--; ulCount; ulCount--) + { + pcBuf[ulPos++] = cFill; + } + } + + if (ulNeg) + { + pcBuf[ulPos++] = '-'; + } + + for (; ulIdx; ulIdx /= ulBase) + { + if (HexFormat == 'x') + pcBuf[ulPos++] = g_pcHex1[(ulValue / ulIdx) % ulBase]; //x + else + pcBuf[ulPos++] = g_pcHex2[(ulValue / ulIdx) % ulBase]; //X + } + + printfsend(UART0, (uint8_t *)pcBuf, ulPos); + break; + } + + case '%': + { + printfsend(UART0, (uint8_t *)format - 1, 1); + break; + } + + default: + { + printfsend(UART0, (uint8_t *)"ERROR", 5); + break; + } + } //switch + } //if + } //while + va_end(vaArgP); +} + +void printv(uint8_t *buf, uint32_t len, uint8_t *s) +{ + uint32_t i = 0; + uint32_t n = 0; + MyPrintf("\r\n %s:", s); + for (i = 0; i < len; i++) + { + if (i % 16 == 0) + { + MyPrintf("\r\n%08x:", n); + n += 16; + } + MyPrintf("%02x ", buf[i]); + } +} + +void _assert_handler(const char *file, int line, const char *func) +{ +#if defined(SDK_DEBUG) + MyPrintf("Assert trigger at file: %s line:%d func: %s\n ", file, line, func); +#endif + while (1); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/core/system.h b/bsp/yichip/yc3121-pos/Libraries/core/system.h new file mode 100644 index 0000000000..b7bd069a98 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/system.h @@ -0,0 +1,43 @@ +/* +File Name : system.h +Author : Yichip +Version : V1.0 +Date : 2018/05/22 +Description : none. +*/ + +#ifndef __SYSTEM_H__ +#define __SYSTEM_H__ + + +#include +#include "yc_uart.h" + +//#define SDK_DEBUG //Debug switch + +#define BIT_SET(a,b) ((a) |= (1<<(b))) +#define BIT_CLEAR(a,b) ((a) &= ~(1<<(b))) +#define BIT_FLIP(a,b) ((a) ^= (1<<(b))) //bit Negation +#define BIT_GET(a,b) (((a) & (1<<(b)))>>(b)) + +/** + * @brief Print format string to serial port 0.You need to initialize the serial port 0 before you use MyPrintf. + * + * @param format : format string + * @param ...: format parameter + */ +void MyPrintf(char *format, ...); + +void _assert_handler(const char *file, int line, const char *func); + +void printv(uint8_t *buf, uint32_t len, uint8_t *s); + +#define _ASSERT(x) \ +if (!(x)) \ +{ \ + _assert_handler(__FILE__,__LINE__,__FUNCTION__);\ +} + + +#endif /*__SYSTEM_H__*/ + diff --git a/bsp/yichip/yc3121-pos/Libraries/core/type.h b/bsp/yichip/yc3121-pos/Libraries/core/type.h new file mode 100644 index 0000000000..112f0374e6 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/type.h @@ -0,0 +1,67 @@ +/* +File Name : type.h +Author : Yichip +Version : V1.0 +Date : 2018/05/25 +Description : Data type definition. +*/ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#if defined (__CC_ARM) || defined ( __ICCARM__ ) +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +typedef unsigned char byte; +typedef unsigned short word; + +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef signed long long int64_t; +#else +#include "stdio.h" +typedef unsigned char byte; +typedef unsigned short word; +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE noinline + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifndef Boolean +typedef enum {FALSE = 0, TRUE =1} Boolean; +#define IS_BOOLEAN(bool) ((bool == FALSE) || (bool == TRUE)) +#endif + +#ifndef FunctionalState +typedef enum {DISABLE = 0, ENABLE =1} FunctionalState; +#define IS_FUNCTIONAL_STATE(state) ((state== DISABLE) || (state == ENABLE)) +#endif + +#ifndef FunctionalState +typedef enum {ERROR = 0, SUCCESS = 1} ErrorStatus; +#define IS_ERROR_STATE(status) ((status== ERROR) || (status == SUCCESS)) +#endif + +#ifndef FlagStatus +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; +#endif + +#endif /*__TYPE_H__*/ + diff --git a/bsp/yichip/yc3121-pos/Libraries/core/yc3121.h b/bsp/yichip/yc3121-pos/Libraries/core/yc3121.h new file mode 100644 index 0000000000..0e06007591 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/yc3121.h @@ -0,0 +1,666 @@ +/* +File Name : yc3121.h +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : Register and hardware information. +*/ + +#ifndef __YC3121_H__ +#define __YC3121_H__ + +#include "type.h" +#include "system.h" +#include +#include "rom_api.h" + +#define NO_BT 0 +#define EXIST_BT 1 +#define NO_XTAL 2 + +#define VERSIONS EXIST_BT + +#define M0_FPGA 1 +#define POS_FPGA 2 +#define POS_CHIP 3 + +#define HARDWAER POS_CHIP + +#if (HARDWAER == M0_FPGA) + #define CPU_MHZ (24*1000000) +#elif (HARDWAER == POS_CHIP) + #define CRYSTAL_CLK (192*1000000) + #define CPU_MHZ ((CRYSTAL_CLK)/((SYSCTRL_HCLK_CON&0x0f)+2)) +#endif + +#define noinline __attribute__((noinline)) + +#define IPC_HOLD_BT *(volatile byte*)0xC4FEF +#define IPC_RX_START_ADDR (volatile byte*)0xc4ff0 +#define IPC_RX_END_ADDR (volatile byte*)0xc4ff2 +#define IPC_RX_READ_PTR (volatile byte*)0xc4ff4 +#define IPC_RX_WRITE_PTR (volatile byte*)0xc4ff6 +#define IPC_TX_START_ADDR (volatile byte*)0xc4ff8 +#define IPC_TX_END_ADDR (volatile byte*)0xc4ffa +#define IPC_TX_READ_PTR (volatile byte*)0xc4ffc +#define IPC_TX_WRITE_PTR (volatile byte*)0xc4ffe + +#define BT_REV *(volatile byte*)0xc8000 +#define BT_STEP *(volatile byte*)0xc8001 +#define BT_PC *(volatile word*)0xc800e +#define BT_RESET *(volatile byte*)0xc8010 +#define BT_UCODE_HI *(volatile byte*)0xc8022 +#define BT_UCODE_CTRL *(volatile byte*)0xc8023 +#define BT_UCODE_LO *(volatile byte*)0xc8024 +#define BT_UCODE_DATA *(volatile byte*)0xc8025 +#define BT_RHALFSLOT_LOW *(volatile byte*)0xc8040 +#define BT_CONTRU *(volatile byte*)0xc812c +#define BT_CONTWU *(volatile byte*)0xc812e +#define BT_CONFIG *(volatile byte*)0xc8043 +#define BT_CLKPLL_EN *(volatile byte*)0xc8905 +#define BT_CHGPUMP_EN *(volatile byte*)0xc8973 +#define WAKEUP_BT *(volatile byte*)0xF853C + +#define BT_INIT_FLAG 7 +#define WAKEUP_BT_FLAG 2 + +//register base address + +#define WDT_BASEADDR 0xf0000 +#define SCI7816_BASEADDR 0xf0400 + +#define TIMER_BASEADDR 0xf0c00 +#define SM4_BASEADDR 0xf5200 +#define RSA_BASEADDR 0xf5800 +#define USB_BASEADDR 0xf6000 +#define DES_BASEADDR 0xf8000 +#define CRC_BASEADDR 0xf8200 +#define AES_BASEADDR 0xf8300 +#define LPM_BASEADDR 0xf8400 +#define SYSCTRL_BASEADDR 0xf8500 +#define SECURE_BASEADDR 0xf8540 +#define CLKGEN_BASEADDR 0xf8560 +#define MPU_BASEADDR 0xf8580 +#define SHA_BASEADDR 0xf8600 +#define GPIO_BASEADDR 0xf8700 +#define DMA_BASEADDR 0xf8800 +#define QSPI_BASEADDR DMA_BASEADDR +#define ISO7811_BASEADDR 0xf8f00 + +#define WD_CONFIG *(volatile int*)(WDT_BASEADDR + 0x00) +#define WD_STATUS *(volatile int*)(WDT_BASEADDR + 0x04) +#define WD_KICK *(volatile int*)(WDT_BASEADDR + 0x08) +#define WD_CLEAR *(volatile int*)(WDT_BASEADDR + 0x0c) + +#define SCI7816_MODE *(volatile int*)(SCI7816_BASEADDR + 0x00) +#define SCI7816_CTRL *(volatile int*)(SCI7816_BASEADDR + 0x08) +#define SCI7816_STAT *(volatile int*)(SCI7816_BASEADDR + 0x0c) +#define SCI7816_INT *(volatile int*)(SCI7816_BASEADDR + 0x10) +#define SCI7816_DATA *(volatile int*)(SCI7816_BASEADDR + 0x20) +#define SCI7816_ETU *(volatile int*)(SCI7816_BASEADDR + 0x28) +#define SCI7816_BGT *(volatile int*)(SCI7816_BASEADDR + 0x2c) +#define SCI7816_CWT *(volatile int*)(SCI7816_BASEADDR + 0x30) +#define SCI7816_EDC *(volatile int*)(SCI7816_BASEADDR + 0x34) + +#define PWM_TOTAL 9 + +#define TIM_PCNT(x) *(volatile int*)(TIMER_BASEADDR + x*8) +#define TIM_NCNT(x) *(volatile int*)(TIMER_BASEADDR + 4 + x*8) +#define TIM_CTRL *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8) +#define TIM_CTRL1 *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8 + 4) +#define TIM_CNT(x) *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8 + (PWM_TOTAL*4 + 31)/32*4 + x*4) + +#define SHA_DATA(x) *(volatile int*)(SHA_BASEADDR + 0x00 + x*4) +#define SHA_BDATA(x) *(volatile uint8_t*)(SHA_BASEADDR + 0x00 + x) +#define SHA_RESULT(x) *(volatile int*)(SHA_BASEADDR + 0x80 + x*4) +#define SHA_CTRL *(volatile int*)(SHA_BASEADDR + 0xc0) + +#define SYSCTRL_PRIV_CTRL *(volatile int*)(SYSCTRL_BASEADDR + 0x0) +#define SYSCTRL_STATUS *(volatile int*)(SYSCTRL_BASEADDR + 0x4) +#define OTP_ADDR *(volatile short*)(SYSCTRL_BASEADDR + 0x8) +#define OTP_CTRL *(volatile short*)(SYSCTRL_BASEADDR + 0xa) +#define OTP_RDATA *(volatile byte*)(SYSCTRL_BASEADDR + 0xc) +#define OTP_STATUS *(volatile int*)(SYSCTRL_BASEADDR + 0xc) + +#define SYSCTRL_LPM_RDATA *(volatile int*)(SYSCTRL_BASEADDR + 0x10) +#define SYSCTRL_LPM_SCB *(volatile int*)(SYSCTRL_BASEADDR + 0x14) +#define SYSCTRL_HWCTRL(x) *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x18 + x) +#define SYSCTRL_RNG_CTRL *(volatile int*)(SYSCTRL_BASEADDR + 0x28) +#define SYSCTRL_RNG_DATAB(x) *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x2c+x) + +#define SYSCTRL_RNG_DATA(x) *(volatile int*)(SYSCTRL_BASEADDR + 0x2c+x*4) + +#define SYSCTRL_ROM_SWITCH *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3c) +#define SYSCTRL_LPM_STATUS *(volatile byte *)(SYSCTRL_BASEADDR + 0x3d) +#define SYSCTRL_OTPN_ADDR *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3e) +#define SYSCTRL_OTPU_ADDR *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3f) + +#define SECURE_CTRL *(volatile int*)(SECURE_BASEADDR + 0x0) +#define SECURE_STATUS *(volatile int*)(SECURE_BASEADDR + 0x4) +#define SECURE_MEDCON *(volatile int*)(SECURE_BASEADDR + 0x8) +#define SECURE_RAMKEY *(volatile int*)(SECURE_BASEADDR + 0xc) + +#define SYSCTRL_HCLK_CON *(volatile int*)(CLKGEN_BASEADDR + 0x00) +#define SYSCTRL_RSACLK *(volatile int*)(CLKGEN_BASEADDR + 0x08) +#define SYSCTRL_CLK_CLS *(volatile int*)(CLKGEN_BASEADDR + 0x0c) +#define SYSCTRL_RST_EN *(volatile int*)(CLKGEN_BASEADDR + 0x14) +#define SYSCTRL_RST_TYPE *(volatile int*)(CLKGEN_BASEADDR + 0x18) +#define SYSCTRL_RESET *(volatile int*)(CLKGEN_BASEADDR + 0x1c) + +#define MPUCTRL_ID *(volatile int*)(MPU_BASEADDR + 0x00) +#define MPUCTRL_CTRL *(volatile int*)(MPU_BASEADDR + 0x04) +#define MPUCTRL_FSR *(volatile int*)(MPU_BASEADDR + 0x0c) +#define MPUCTRL_FAR *(volatile int*)(MPU_BASEADDR + 0x10) + +#define MPUCTRL_PROTECTION *(volatile int*)(MPU_BASEADDR + 0x14) +#define MPUCTRL_USER_START *(volatile int*)(MPU_BASEADDR + 0x18) +#define MPUCTRL_REGION_BASE(x) *(volatile int*)(MPU_BASEADDR + 0x40 + x*4) +#define MPUCTRL_REGION_LIMIT(x) *(volatile int*)(MPU_BASEADDR + 0x60 + x*4) + +#define LPM_CTRL (volatile int*)(LPM_BASEADDR + 0x00) +#define LPM_SENSOR (volatile int*)(LPM_BASEADDR + 0x04) +#define LPM_WKUP_TIMER (volatile int*)(LPM_BASEADDR + 0x08) +#define LPM_SECMAX (volatile int*)(LPM_BASEADDR+0x0c) +#define LPM_GPIO_WKUP (volatile int*)(LPM_BASEADDR + 0x10) +#define LPM_GPIO_WKHI (volatile int*)(LPM_BASEADDR + 0x14) +#define LPM_SLEEP (volatile int*)(LPM_BASEADDR + 0x20) +#define LPM_CLR_INTR (volatile int*)(LPM_BASEADDR + 0x24) +#define LPM_STATUS (volatile int*)(LPM_BASEADDR + 0x78) +#define LPM_RTC_CNT (volatile int*)(LPM_BASEADDR + 0x7c) +#define LPM_KEY(x) (volatile int*)(LPM_BASEADDR + 0x80 + x*4) + +#define GPIO_GROUP_NUM 3 +#define GPIO_PIN_NUM 16 + +#define GPIO_CONFIG(x) *((volatile uint8_t*)(GPIO_BASEADDR + x)) +#define GPIO_INTR_EN(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+GPIO_GROUP_NUM*GPIO_PIN_NUM) + groupx) +#define GPIO_TRIG_MODE(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+(GPIO_GROUP_NUM*GPIO_PIN_NUM) +GPIO_GROUP_NUM*2) +groupx) +#define GPIO_IN(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+(GPIO_GROUP_NUM*GPIO_PIN_NUM) +GPIO_GROUP_NUM*4)+groupx) + +#define DMA_SRC_ADDR(x) *(volatile int*)(DMA_BASEADDR + 0x00 + x*0x100) +#define DMA_DEST_ADDR(x) *(volatile int*)(DMA_BASEADDR + 0x04 + x*0x100) +#define DMA_LEN(x) *(volatile int*)(DMA_BASEADDR + 0x08 + x*0x100) +#define DMA_CONFIG(x) *(volatile uint8_t*)(DMA_BASEADDR + 0x0c + x*0x100) +#define DMA_START(x) *(volatile uint8_t*)(DMA_BASEADDR + 0x0f + x*0x100) +#define DMA_STATUS(x) *(volatile int*)(DMA_BASEADDR + 0x10 + x*0x100) +#define DMA_RPTR(x) *(volatile int*)(DMA_BASEADDR + 0x14 + x*0x100) +#define DMA_WPTR(x) *(volatile int*)(DMA_BASEADDR + 0x18 + x*0x100) + +#define QSPI_CTRL *(volatile int*)(QSPI_BASEADDR + 0x1c) +#define QAES_ADDRKEY *(volatile int*)(QSPI_BASEADDR + 0x20) +#define QAES_CTRL *(volatile int*)(QSPI_BASEADDR + 0x24) +#define QAES_RAND(x) *(volatile int*)(QSPI_BASEADDR + 0x28 + x*4) +#define QAES_KEY(x) *(volatile int*)(QSPI_BASEADDR + 0x30 + x*4) +#define QAES_DATA(x) *(volatile int*)(QSPI_BASEADDR + 0x40 + x*4) +#define QAES_KEYB(x) *(volatile byte*)(QSPI_BASEADDR + 0x30 + x) +#define SPID0_CTRL *(volatile int*)0xf891c +#define SPID1_CTRL *(volatile int*)0xf8a1c +#define UART0_CTRL *(volatile int*)0xf8b1c +#define UART0_INTR *(volatile int*)0xf8b20 +#define UART0_RDATA *(volatile byte*)0xf8b24 +#define UART0_STATUS *(volatile int*)0xf8b28 +#define UART1_CTRL *(volatile int*)0xf8c1c +#define UART1_INTR *(volatile int*)0xf8c20 +#define UART1_RDATA *(volatile byte*)0xf8c24 +#define UART1_STATUS *(volatile int*)0xf8c28 +#define IICD_DELAY *(volatile int*)0xf8d1c +#define IICD_CTRL *(volatile int*)0xf8d20 + +#define USB_CONFIG *(volatile byte*)USB_BASEADDR +#define USB_INT_MASK(x) *(volatile byte*)(USB_BASEADDR + 1 + x) +#define USB_ADDR *(volatile byte*)(USB_BASEADDR + 4) +#define USB_TRG *(volatile byte*)(USB_BASEADDR + 0x10) +#define USB_STALL *(volatile byte*)(USB_BASEADDR + 0x11) +#define USB_CLEAR *(volatile byte*)(USB_BASEADDR + 0x12) +#define USB_EP(x) *(volatile byte*)(USB_BASEADDR + 0x18 + x) +#define USB_EP_LEN(x) *(volatile byte*)(USB_BASEADDR + 0x20 + x) +#define USB_STATUS *(volatile byte*)(USB_BASEADDR + 0x26) +#define USB_FIFO_EMPTY *(volatile byte*)(USB_BASEADDR + 0x27) +#define USB_FIFO_FULL *(volatile byte*)(USB_BASEADDR + 0x28) + + +#define AES_CNTRL_REG *((volatile uint32_t *)(AES_BASEADDR)) +#define AES_DATA_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x10)) +#define AES_DATA_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x14)) +#define AES_DATA_REG2 ((volatile uint32_t *)(AES_BASEADDR+0x18)) +#define AES_DATA_REG3 ((volatile uint32_t *)(AES_BASEADDR+0x1C)) +#define AES_KEY_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x20)) +#define AES_KEY_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x24)) +#define AES_KEY_REG2 ((volatile uint32_t *)(AES_BASEADDR+0x28)) +#define AES_KEY_REG3 ((volatile uint32_t *)(AES_BASEADDR+0x2C)) +#define AES_KEY_REG4 ((volatile uint32_t *)(AES_BASEADDR+0x30)) +#define AES_KEY_REG5 ((volatile uint32_t *)(AES_BASEADDR+0x34)) +#define AES_KEY_REG6 ((volatile uint32_t *)(AES_BASEADDR+0x38)) +#define AES_KEY_REG7 ((volatile uint32_t *)(AES_BASEADDR+0x3C)) +#define AES_RAND_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x40)) +#define AES_RAND_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x44)) +#define AES_FKEY_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x50)) + +#define AES_DATAB(x) *(volatile byte*)(AES_BASEADDR + 0x10 + (x)) +#define AES_KEYB(x) *(volatile byte*)(AES_BASEADDR + 0x20 + (x)) + +#define DESCNTRL_REG *((volatile uint32_t *)(DES_BASEADDR+0x00)) +#define DESRAND_REG ((volatile uint32_t *)(DES_BASEADDR+0x0c)) +#define DESFAKE_KEY ((volatile uint32_t *)(DES_BASEADDR+0x10)) +#define DESIV_REG ((volatile uint32_t *)(DES_BASEADDR+0x18)) +#define DESDATA_REG ((volatile uint32_t *)(DES_BASEADDR+0x20)) +#define DESKEY1_REG ((volatile uint32_t *)(DES_BASEADDR+0x28)) +#define DESKEY2_REG ((volatile uint32_t *)(DES_BASEADDR+0x30)) +#define DESKEY3_REG ((volatile uint32_t *)(DES_BASEADDR+0x38)) +#define DES_KEYB(x) *(volatile byte *)(DES_BASEADDR+0x28 + x) +#define DES_DATAB(x) *(volatile byte *)(DES_BASEADDR+0x20 + x) + +#define SM4_REG0 (*(volatile uint32_t *)(SM4_BASEADDR + 0x0)) +#define SM4_REG1 (*(volatile uint32_t *)(SM4_BASEADDR + 0x4)) +#define SM4_IER (*(volatile uint32_t *)(SM4_BASEADDR + 0x8)) +#define SM4_MR (*(volatile uint32_t *)(SM4_BASEADDR + 0xc)) +#define SM4_KEY0 ((volatile uint32_t *)(SM4_BASEADDR + 0x10)) +#define SM4_KEY1 ((volatile uint32_t *)(SM4_BASEADDR + 0x14)) +#define SM4_KEY2 ((volatile uint32_t *)(SM4_BASEADDR + 0x18)) +#define SM4_KEY3 ((volatile uint32_t *)(SM4_BASEADDR + 0x1c)) +#define SM4_IV0 ((volatile uint32_t *)(SM4_BASEADDR + 0x20)) +#define SM4_IV1 ((volatile uint32_t *)(SM4_BASEADDR + 0x24)) +#define SM4_IV2 ((volatile uint32_t *)(SM4_BASEADDR + 0x28)) +#define SM4_IV3 ((volatile uint32_t *)(SM4_BASEADDR + 0x2c)) +#define SM4_DATA0 ((volatile uint32_t *)(SM4_BASEADDR + 0x30)) +#define SM4_DATA1 ((volatile uint32_t *)(SM4_BASEADDR + 0x34)) +#define SM4_DATA2 ((volatile uint32_t *)(SM4_BASEADDR + 0x38)) +#define SM4_DATA3 ((volatile uint32_t *)(SM4_BASEADDR + 0x3c)) + + +#define RECR (*((volatile uint32_t *)(RSA_BASEADDR+0x00))) +#define RESR (*((volatile uint32_t *)(RSA_BASEADDR+0x04))) +#define REFR (*((volatile uint32_t *)(RSA_BASEADDR+0x08))) +#define RESCR (*((volatile uint32_t *)(RSA_BASEADDR+0x0c))) +#define REDQR (*((volatile uint32_t *)(RSA_BASEADDR+0x10))) +#define REINT (*((volatile uint32_t *)(RSA_BASEADDR+0x14))) +#define RECFR (*((volatile uint32_t *)(RSA_BASEADDR+0x18))) +#define REBKR ((volatile uint32_t *)(RSA_BASEADDR+0x1c)) +#define REDRR (*((volatile uint32_t *)(RSA_BASEADDR+0x24))) +#define REDAR ((volatile uint32_t *)(RSA_BASEADDR+0x100)) +#define REDAR1 ((volatile uint32_t *)(RSA_BASEADDR+0x120)) +#define REDAR2 ((volatile uint32_t *)(RSA_BASEADDR+0x140)) +#define REDAR3 ((volatile uint32_t *)(RSA_BASEADDR+0x160)) +#define REDXR ((volatile uint32_t *)(RSA_BASEADDR+0x200)) +#define REDXR1 ((volatile uint32_t *)(RSA_BASEADDR+0x220)) +#define REDXR2 ((volatile uint32_t *)(RSA_BASEADDR+0x240)) +#define REDXR3 ((volatile uint32_t *)(RSA_BASEADDR+0x260)) +#define REDYR ((volatile uint32_t *)(RSA_BASEADDR+0x280)) +#define REDYR1 ((volatile uint32_t *)(RSA_BASEADDR+0x2a0)) +#define REDYR2 ((volatile uint32_t *)(RSA_BASEADDR+0x2c0)) +#define REDYR3 ((volatile uint32_t *)(RSA_BASEADDR+0x2e0)) +#define REDBR ((volatile uint32_t *)(RSA_BASEADDR+0x300)) +#define REDBR1 ((volatile uint32_t *)(RSA_BASEADDR+0x320)) +#define REDBR2 ((volatile uint32_t *)(RSA_BASEADDR+0x340)) +#define REDBR3 ((volatile uint32_t *)(RSA_BASEADDR+0x360)) +#define REDBRH ((volatile uint32_t *)(RSA_BASEADDR+0x380)) +#define REDCR ((volatile uint32_t *)(RSA_BASEADDR+0x500)) +#define REDCR1 ((volatile uint32_t *)(RSA_BASEADDR+0x520)) +#define REDCR2 ((volatile uint32_t *)(RSA_BASEADDR+0x540)) +#define REDCR3 ((volatile uint32_t *)(RSA_BASEADDR+0x560)) +#define REDCRH ((volatile uint32_t *)(RSA_BASEADDR+0x580)) +#define REDUR ((volatile uint32_t *)(RSA_BASEADDR+0x600)) +#define REDVR ((volatile uint32_t *)(RSA_BASEADDR+0x680)) +#define REDVR2 ((volatile uint32_t *)(RSA_BASEADDR+0x6c0)) +#define REDPR ((volatile uint32_t *)(RSA_BASEADDR+0x700)) +#define REDPR1 ((volatile uint32_t *)(RSA_BASEADDR+0x720)) +#define REDPR2 ((volatile uint32_t *)(RSA_BASEADDR+0x740)) +#define REDPR3 ((volatile uint32_t *)(RSA_BASEADDR+0x760)) +#define REDPRH ((volatile uint32_t *)(RSA_BASEADDR+0x780)) + +#define ISO7811_BASE_ADDR_T1 *((volatile uint32_t *)(ISO7811_BASEADDR+0x00)) +#define ISO7811_BASE_ADDR_T2 *((volatile uint32_t *)(ISO7811_BASEADDR+0x04)) +#define ISO7811_BASE_ADDR_T3 *((volatile uint32_t *)(ISO7811_BASEADDR+0x08)) +#define ISO7811_CTRL *((volatile uint32_t *)(ISO7811_BASEADDR+0x0C)) + +#define ISO7811_T1_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x10)) +#define ISO7811_T1_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x14)) +#define ISO7811_T1_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x18)) +#define ISO7811_T1_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x1c)) + +#define ISO7811_T2_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x20)) +#define ISO7811_T2_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x24)) +#define ISO7811_T2_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x28)) +#define ISO7811_T2_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x2c)) + +#define ISO7811_T3_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x30)) +#define ISO7811_T3_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x34)) +#define ISO7811_T3_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x38)) +#define ISO7811_T3_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x3c)) + +#define ISO7811_STATUS *((volatile uint32_t *)(ISO7811_BASEADDR+0x40)) +#define ISO7811_CHAR_NUM *((volatile uint32_t *)(ISO7811_BASEADDR+0x44)) +#define ISO7811_INTERFER_CHAR_NUM *((volatile uint32_t *)(ISO7811_BASEADDR+0x48)) +#define ISO7811_DC_EST *((volatile uint32_t *)(ISO7811_BASEADDR+0x4c)) +#define ISO7811_INTF_PEAK *((volatile uint32_t *)(ISO7811_BASEADDR+0x50)) +#define ISO7811_AGC_PEAK_VAL *((volatile uint32_t *)(ISO7811_BASEADDR +0x54)) + +#define SYST_CSR *(volatile int*)0xE000E010 +#define SYST_RVR *(volatile int*)0xE000E014 +#define SYST_CVR *(volatile int*)0xE000E018 + +#define TRACE_FIFO *(volatile int*)0xe0002020 +#define NVIC_ISER *(volatile int*)0xe000e100 +#define NVIC_ICER *(volatile int*)0xe000e180 +#define NVIC_ISPR *(volatile int*)0xe000e200 +#define NVIC_ICPR *(volatile int*)0xe000e280 + +#define CRC_RESULT_REG *(volatile uint32_t *)(CRC_BASEADDR+0X04) +#define CRC_MASK_REG *(volatile uint32_t *)(CRC_BASEADDR+0X08) +#define CRC_DATAB_REG *(volatile byte *)(CRC_BASEADDR+0X80) +#define CRC_DATAS_REG *(volatile short int *)(CRC_BASEADDR+0X80) +#define CRC_DATA_REG *(volatile int *)(CRC_BASEADDR+0X80) + +#define ADC_CTRL0 *(volatile uint8_t*)0xC8970 +#define ADC_CTRL1 *(volatile uint8_t*)0xC8971 +#define ADC_CTRL2 *(volatile uint8_t*)0xC8972 +#define ADC_CTRL3 *(volatile uint8_t*)0xC8973 +#define ADC_ENBLE *(volatile uint8_t*)0xC8906 +#define ADC_RDATA *(volatile uint16_t*)0xf850e + +/* SysTick registers */ +/* SysTick control & status */ +#define SYSTICK_CSR ((volatile unsigned int *)0xE000E010) +/* SysTick Reload value */ +#define SYSTICK_RVR ((volatile unsigned int *)0xE000E014) +/* SysTick Current value */ +#define SYSTICK_CVR ((volatile unsigned int *)0xE000E018) +/* SysTick CSR register bits */ +#define SYSTICK_CSR_COUNTFLAG 16 +#define SYSTICK_CSR_CLKSOURCE 2 +#define SYSTICK_CSR_TICKINT 1 +#define SYSTICK_CSR_ENABLE 0 + +//================ bit definitions ==================== +#define OTBIT_DIN 1<<0 +#define OTBIT_DLE 1<<1 +#define OTBIT_CEB 1<<2 +#define OTBIT_RSTB 1<<3 +#define OTBIT_CLE 1<<4 +#define OTBIT_PGMEN 1<<5 +#define OTBIT_PGMVFY 1<<6 +#define OTBIT_READEN 1<<7 +#define OTBIT_VPPEN 1<<8 +#define OTBIT_WEB 1<<9 + +#define AES_CNTRL_REG_START 0x1 + +#define AES_CNTRL_KEY_SEL_128 0X00 +#define AES_CNTRL_KEY_SEL_192 0X08 +#define AES_CNTRL_KEY_SEL_256 0X10 + +#define AES_CNTRL_ENC 0X00 +#define AES_CNTRL_DEC 0X02 + +#define AES_CNTRL_ENABLE_RAND 0X20 + +#define DMACH_QSPI 0 +#define DMACH_SPID0 1 +#define DMACH_SPID1 2 +#define DMACH_UART0 3 +#define DMACH_UART1 4 +#define DMACH_IICD 5 +#define DMACH_MEMCP 6 + +#define DMA_START_BIT 7 +#define DMA_CLR_INTR_BIT 6 +#define DMA_RESET_BIT 5 + +//==DES== +#define DESCNTRL_REG_START 0x1 +#define DESCNTRL_REG_ENCRYPT 0x2 +#define DESCNTRL_REG_KEY_SEL 0xc +#define DESCNTRL_REG_DES_MODE 0x10 +#define DESCNTRL_REG_OP_MODE 0x60 +#define DESCNTRL_REG_RAND_EN 0x80 + +#define DESCNTRL_REG_ENCRYPT_ENC 0X00 +#define DESCNTRL_REG_ENCRYPT_DEC 0X02 + +#define DESCNTRL_REG_KEY_SEL_DES1 0x00 +#define DESCNTRL_REG_KEY_SEL_DES2 0x04 +#define DESCNTRL_REG_KEY_SEL_DES3 0x08 + +#define DESCNTRL_REG_KEY_SEL_TDES2 0x00 +#define DESCNTRL_REG_KEY_SEL_TDES3 0x04 + +#define DESCNTRL_REG_DES_MODE_DES 0X00 +#define DESCNTRL_REG_DES_MODE_TDES 0X10 + +#define DESCNTRL_REG_OP_MODE_ECB 0x00 +#define DESCNTRL_REG_OP_MODE_CBC 0x20 +//==DES==END== + +//==RSA== +//sfr bit +// RECR register +#define RECR_start 0x01 +#define RECR_idle_run 0x02 +#define RECR_bus_crypt_en 0x04 +// RESR register +#define RESR_error_flag 0x01 +#define RESR_opdata_error 0x02 +//REINT register +#define REINT_rsa_int 0x01 +//==RSA==END== + +#define CLKCLS_INT 1 +#define CLKCLS_SHA 2 +#define CLKCLS_CRC 3 +#define CLKCLS_TIM 4 +#define CLKCLS_WDT 5 +#define CLKCLS_USB 6 +#define CLKCLS_SPI 7 +#define CLKCLS_DES 8 +#define CLKCLS_RSA 9 +#define CLKCLS_AES 10 +#define CLKCLS_GPIO 11 +#define CLKCLS_7816 12 +#define CLKCLS_BT 13 +#define CLKCLS_SM4 14 +#define CLKCLS_UART 15 +#define CLKCLS_7811 16 +#define CLKCLS_ADC7811 17 +#define CLKCLS_CP 18 + +#define INTR_USB 0 +#define INTR_IIC 1 +#define INTR_QSPI 2 +#define INTR_SPI0 3 +#define INTR_SPI1 4 +#define INTR_UART0 5 +#define INTR_UART1 6 +#define INTR_MEMCP 7 +#define INTR_RSA 8 +#define INTR_SCI0 9 +#define INTR_SCI1 10 +#define INTR_BT 11 +#define INTR_GPIO 12 +#define INTR_TMR0 13 +#define INTR_TMR1 14 +#define INTR_TMR2 15 +#define INTR_TMR3 16 +#define INTR_TMR4 17 +#define INTR_TMR5 18 +#define INTR_TMR6 19 +#define INTR_TMR7 20 +#define INTR_TMR8 21 +#define INTR_SM4 22 +#define INTR_SEC 23 +#define INTR_ISO7811 24 +#define INTR_TRNG 25 +#define INTR_WDT 26 + +#define SCICFG_TMODE 0 +#define SCICFG_BIT_ORDER 1 +#define SCICFG_PAD_TYPE 2 +#define SCICFG_ETU_SEL 3 +#define SCICFG_RETRY 5 +#define SCICFG_RETRY_EN 8 +#define SCICFG_IO_EN 9 +#define SCICFG_BGTEN 10 +#define SCICFG_CWTEN 11 +#define SCICFG_MCLK_SEL 12 +#define SCICFG_MASTER 15 +#define SCICFG_EDCEN 16 + +#define KCFG_COL 3 +#define KCFG_MDDBC 8 +#define KCFG_MUDBC 12 +#define KCFG_UDBC 16 +#define KCFG_CYLE 20 + +#define SM4_CNTRL_ECB 0X00 +#define SM4_CNTRL_CBC 0X02 +#define SM4_CNTRL_ENC 0X01 +#define SM4_CNTRL_DEC 0X00 + +/* =============== qspi flash command =================== */ +#define W25X_WRITE_ENABLE 0x06 +#define W25X_WRITE_DISABLE 0x04 +#define W25X_READ_STATUS1 0x05 +#define W25X_READ_STATUS2 0x35 +#define W25X_WRITE_STATUS 0x01 +#define W25X_READ_DATA 0x03 +#define W25X_FASTREAD_DATA 0x0B +#define W25X_FASTREAD_DUAL1 0x3B +#define W25X_FASTREAD_DUAL2 0xBB + +#define W25X_FASTREAD_QUAD1 0x6B +#define W25X_FASTREAD_QUAD2 0xEB +#define W25X_FASTREAD_QUAD3 0xE7 + +#define W25X_PAGE_PROGRAM 0x02 +#define W25X_SECTOR_ERASE 0x20 +#define W25X_BLOCK_ERASE32K 0x52 +#define W25X_BLOCK_ERASE64K 0xD8 +#define W25X_CHIP_ERASE 0xC7 +#define W25X_POWER_DOWN 0xB9 +#define W25X_RELEASE_POWERDOWN 0xAB +#define W25X_DEVICEID 0xAB +#define W25X_MANUFACT_DEVICEID 0x90 +#define W25X_JEDEC_DEVICEID 0x9F + +#define QSPICFG_XIPEN 1 << 12 +#define QSPICFG_DECEN 1 << 13 +#define QSPICFG_DUAL_MODE 1 << 0 +#define QSPICFG_QUAD_MODE 2 << 0 +#define QSPICFG_MBYTE 1 << 2 +#define QSPICFG_MBYTE_CONT 1 << 3 +#define QSPICFG_RETRY 3 << 24 + +#define QCSFT_DUMMY 8 +#define QCSFT_CMD 16 + +#define QSPICFG_MODE_3B QSPICFG_DUAL_MODE | W25X_FASTREAD_DUAL1 << QCSFT_CMD | 8 << QCSFT_DUMMY +#define QSPICFG_MODE_6B QSPICFG_QUAD_MODE | W25X_FASTREAD_QUAD1 << QCSFT_CMD | 8 << QCSFT_DUMMY +#define QSPICFG_MODE_BB QSPICFG_DUAL_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_DUAL2 << QCSFT_CMD +#define QSPICFG_MODE_EB QSPICFG_QUAD_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_QUAD2 << QCSFT_CMD | 4 << QCSFT_DUMMY +#define QSPICFG_MODE_E7 QSPICFG_QUAD_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_QUAD3 << QCSFT_CMD | 2 << QCSFT_DUMMY + +#define LPMCFG_BUCK_EN 1 << 25 +#define LPMCFG_TIMER_EN 1 << 28 +#define LPMCFG_KRST_EN 1 << 29 +#define LPMCFG_SENSOR_DUR 1 << 30 + +#define LPMSEN_SENSOR_DLY 5 +#define LPMSEN_SENSOR_LOCK 7 +#define LPMSEN_SHIELD_IO_EN 8 +#define LPMSEN_SHIELD_IO_TYPE 12 +#define LPMSEN_SHIELD_IO_PU 16 +#define LPMSEN_SHIELD_INTERVAL 24 +#define LPMSEN_SHIELD_ENABLE 27 +#define LPMSEN_SHIELD_PU_DLY 28 +#define LPMSEN_SHIELD_A_DLY 30 +#define LPMCFG_SENSOR_LOCK 31 + +//gpio ctrl bit define +#define GPCFG_INPUT 0 +#define GPCFG_QSPI_NCS 2 +#define GPCFG_QSPI_SCK 3 +#define GPCFG_QSPI_IO0 4 +#define GPCFG_QSPI_IO1 5 +#define GPCFG_QSPI_IO2 6 +#define GPCFG_QSPI_IO3 7 +#define GPCFG_UART0_TXD 8 +#define GPCFG_UART0_RXD 9 +#define GPCFG_UART0_RTS 10 +#define GPCFG_UART0_CTS 11 +#define GPCFG_UART1_TXD 12 +#define GPCFG_UART1_RXD 13 +#define GPCFG_UART1_RTS 14 +#define GPCFG_UART1_CTS 15 +#define GPCFG_PWM_OUT0 16 +#define GPCFG_PWM_OUT1 17 +#define GPCFG_PWM_OUT2 18 +#define GPCFG_PWM_OUT3 19 +#define GPCFG_PWM_OUT4 20 +#define GPCFG_PWM_OUT5 21 +#define GPCFG_PWM_OUT6 22 +#define GPCFG_PWM_OUT7 23 +#define GPCFG_SPID0_NCS 24 +#define GPCFG_SPID0_SCK 25 +#define GPCFG_SPID0_MOSI 26 +#define GPCFG_SPID0_SDIO 27 +#define GPCFG_SPID0_MISO 28 +#define GPCFG_SPID0_NCSIN 29 +#define GPCFG_SPID0_SCKIN 30 +#define GPCFG_PWM_OUT8 31 + +#define GPCFG_SPID1_NCS 48 +#define GPCFG_SPID1_SCK 49 +#define GPCFG_SPID1_MOSI 50 +#define GPCFG_SPID1_SDIO 51 +#define GPCFG_SPID1_MISO 52 +#define GPCFG_SPID1_NCSIN 53 +#define GPCFG_SPID1_SCKIN 54 +#define GPCFG_NFC_CLK_OUT 55 +#define GPCFG_SCI7816_IO 56 + +#define GPCFG_ICE 57 +#define GPCFG_IIC_SCL 58 +#define GPCFG_IIC_SDA 59 +#define GPCFG_JTAG_SWCLK 60 +#define GPCFG_JTAG_SWDAT 61 +#define GPCFG_OUTPUT_LOW 62 +#define GPCFG_OUTPUT_HIGH 63 +#define GPCFG_PU 64 +#define GPCFG_PD 128 +#define GPCFG_ANALOG 192 + +#define TIM_CTRL_ENABLE ((uint32_t)0) +#define TIM_CTRL_START_LEVEL ((uint32_t)1) +#define TIM_CTRL_MODE ((uint32_t)2) +#define TIM_CTRL_AUTO_RELOAD ((uint32_t)3) + +/* =============== macros =================== */ +#define PREFETCH_LINE(addr) *(volatile int*)addr = 0 +#define GETWORD(p) ((uint16_t)((*(volatile uint8_t *)((uint32_t)p)) |((((uint16_t)(*(volatile uint8_t *)((uint32_t)(p+1))))<<8) & 0xff00))) +static inline void enable_clock(int id) +{ + SYSCTRL_CLK_CLS &= ~(1 << id); +} +static inline void disable_clock(int id) +{ + SYSCTRL_CLK_CLS |= 1 << id; +} +static inline void enable_intr(int intid) +{ + NVIC_ISER |= 1 << intid; +} +static inline void disable_intr(int intid) +{ + NVIC_ICER = 1 << intid; +} + +extern void delay(int);//delay(x)=delay(x*110+450ns) +extern void invalidate_icache(int addr, int len); + +//#define SCY_FALSE seesim1() + +/*********************************************/ +#define SYSCTRL_PCLK_CON *(volatile int*)0xf7208 +#define SYSCTRL_POWERMODE *(volatile int*)0xf7218 + +//#define debug +#endif /* __YC3121_H__ */ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c new file mode 100644 index 0000000000..8b7f355076 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c @@ -0,0 +1,72 @@ +/* +File Name : yc_dma.c +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : DMA Mem_TO_Mem Mode encapsulation. + If enable DMA interrupt ,enter interrupt after sending data by default,and just one DMA IT Mode. +*/ + +#include "yc_dma.h" + +#define DMA_Channel DMACH_MEMCP +#define DMA_CLEAR_IT_BIT_Pos 6 +#define DMA_ENTERIT_BIT_Pos 1 +#define DMA_DATA_COMPLETE_BIT_Pos 0 + +void DMA_Init(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_SRC_ADDR(DMACH_MEMCP) = DMA_InitStruct->DMA_MemorySourceAddr; + DMA_DEST_ADDR(DMACH_MEMCP) = DMA_InitStruct->DMA_MemoryDestAddr; + DMA_LEN(DMACH_MEMCP) = (DMA_InitStruct->DMA_BlockSize << 16) | DMA_InitStruct->DMA_BlockSize; +} + +void DMA_ChannelCmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + DMA_START(DMACH_MEMCP) |= (DMA_ENABLE); + } + else + { + DMA_START(DMACH_MEMCP) &= ~(DMA_ENABLE); + } +} + +void DMA_SetSRCAddress(uint32_t Address) +{ + DMA_SRC_ADDR(DMACH_MEMCP) = Address; +} + +void DMA_SetDSRAddress(uint32_t Address) +{ + DMA_DEST_ADDR(DMACH_MEMCP) = Address; +} + +FunctionalState DMA_IsChannelEnabled(void) +{ + if (1 == (DMA_START(DMACH_MEMCP) & DMA_ENABLE)) + { + return ENABLE; + } + else + { + return DISABLE; + } +} + +FlagStatus DMA_GetFlagStatus(void) +{ + return (FlagStatus)((DMA_STATUS(DMACH_MEMCP) & (1 << DMA_DATA_COMPLETE_BIT_Pos))); +} + +void DMA_ClearITPendingBit(void) +{ + DMA_START(DMACH_MEMCP) |= (1 << DMA_CLEAR_IT_BIT_Pos); +} + +void DMA_ITConfig(FunctionalState NewState) +{ + DMA_CONFIG(DMACH_MEMCP) &= ~(1 << DMA_ENTERIT_BIT_Pos); + DMA_CONFIG(DMACH_MEMCP) |= (NewState << DMA_ENTERIT_BIT_Pos); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h new file mode 100644 index 0000000000..deac52a157 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h @@ -0,0 +1,91 @@ +/* +File Name : yc_dma.h +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : DMA Mem_TO_Mem Mode encapsulation. + If enable DMA interrupt ,enter interrupt after sending data by default,and just one DMA IT Mode. +*/ + +#ifndef __YC_DMA_H_ +#define __YC_DMA_H_ + +#include "yc3121.h" +#define DMACH_QSPI 0 + +#define DMA_ENABLE_BIT_Pos 7 +#define DMA_ENABLE ((uint8_t)1 << DMA_ENABLE_BIT_Pos) + +#define DMA_IT_BIT_Pos 1 +#define DMA_IT_ENABLE ((uint32_t)1 << DMA_IT_BIT_Pos) +/*Peripheral DMA Channel*/ + +typedef struct +{ + uint32_t DMA_MemorySourceAddr; /*!< Specifies the memory Source address for Channel Mem_to_Mem. */ + + uint32_t DMA_MemoryDestAddr; /*!GPIO_Pin)); + _ASSERT(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + + int i; + + switch (GPIO_InitStruct->GPIO_Mode) + { + case GPIO_Mode_IN_FLOATING: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x00; + } + break; + + case GPIO_Mode_IPU: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x40; + } + break; + + case GPIO_Mode_IPD: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x80; + } + break; + + case GPIO_Mode_AIN: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0xC0; + } + break; + + case GPIO_Mode_Out_PP: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x3E; + } + break; + + default: + break; + } +} + +void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, FunctionalState NewState) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + int i; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_Pin & 1 << i) + { + if (NewState == ENABLE) + { + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) |= 1 << 6; + } + else if (NewState == DISABLE) + { + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) &= ~(1 << 6); + } + } + } +} + +uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + + return GPIO_IN(GPIOx); +} + +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (GPIO_IN(GPIOx) & GPIO_Pin) + { + return (uint8_t)0x01; + } + else + { + return (uint8_t)0x00; + } +} + +uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + + return GPIO_IN(GPIOx); +} + +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (GPIO_IN(GPIOx) & GPIO_Pin) + { + return (uint8_t)0x01; + } + else + { + return (uint8_t)0x00; + } +} + +void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + int i; + uint8_t Temp; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_Pin & 1 << i) + { + Temp = GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i); + Temp |= 0x3F; //00111111 + Temp &= 0xFE; //11111110 + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = Temp; + } + } +} + +void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + int i; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) |= 0x3F; //00111111 + } +} + +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +void GPIO_Write(GPIO_TypeDef GPIOx, uint16_t value) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + + int i; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (BIT_GET(value, i)) + GPIO_SetBits(GPIOx, 1 << i); + else + GPIO_ResetBits(GPIOx, 1 << i); + } +} + +void GPIO_WriteBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (BitVal == Bit_SET) + GPIO_SetBits(GPIOx, GPIO_Pin); + else if (BitVal == Bit_RESET) + GPIO_ResetBits(GPIOx, GPIO_Pin); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h new file mode 100644 index 0000000000..92f6ff9723 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h @@ -0,0 +1,299 @@ +/* +File Name : yc_gpio.c +Author : Yichip +Version : V1.0 +Date : 2019/12/03 +Description : gpio encapsulation. +*/ + +#ifndef __YC_GPIO_H__ +#define __YC_GPIO_H__ + +#include "yc3121.h" + +/** + * @brief Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN_FLOATING = 0x01, + GPIO_Mode_IPU = 0x02, + GPIO_Mode_IPD = 0x03, + GPIO_Mode_AIN = 0x04, + GPIO_Mode_Out_PP = 0x05 /*!< analog signal mode */ +} GPIO_ModeTypeDef; + +#define IS_GPIO_MODE(mode) (((mode) == GPIO_Mode_IN_FLOATING) || \ + ((mode) == GPIO_Mode_IPU) || \ + ((mode) == GPIO_Mode_IPD) || \ + ((mode) == GPIO_Mode_Out_PP) || \ + ((mode) == GPIO_Mode_AIN)) + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/** + * @brief gpio output enumeration + */ +typedef enum +{ + OutputLow = 0, + OutputHigh = 1 +} GPIO_OutputTypeDef; + +#define IS_GPIO_WAKE_MODE(MODE) (((MODE) == GPIO_WakeMode_Now) || \ + ((MODE) == GPIO_WakeMode_AfterGlitch)) + +/** + * @brief GPIO function enumeration + */ +typedef enum +{ + INPUT = GPCFG_INPUT, + QSPI_NCS = GPCFG_QSPI_NCS, + QSPI_SCK = GPCFG_QSPI_SCK, + QSPI_IO0 = GPCFG_QSPI_IO0, + QSPI_IO1 = GPCFG_QSPI_IO1, + QSPI_IO2 = GPCFG_QSPI_IO2, + QSPI_IO3 = GPCFG_QSPI_IO3, + UART0_TXD = GPCFG_UART0_TXD, + UART0_RXD = GPCFG_UART0_RXD, + UART0_RTS = GPCFG_UART0_RTS, + UART0_CTS = GPCFG_UART0_CTS, + UART1_TXD = GPCFG_UART1_TXD, + UART1_RXD = GPCFG_UART1_RXD, + UART1_RTS = GPCFG_UART1_RTS, + UART1_CTS = GPCFG_UART1_CTS, + PWM_OUT0 = GPCFG_PWM_OUT0, + PWM_OUT1 = GPCFG_PWM_OUT1, + PWM_OUT2 = GPCFG_PWM_OUT2, + PWM_OUT3 = GPCFG_PWM_OUT3, + PWM_OUT4 = GPCFG_PWM_OUT4, + PWM_OUT5 = GPCFG_PWM_OUT5, + PWM_OUT6 = GPCFG_PWM_OUT6, + PWM_OUT7 = GPCFG_PWM_OUT7, + PWM_OUT8 = GPCFG_PWM_OUT8, + SPID0_NCS = GPCFG_SPID0_NCS, + SPID0_SCK = GPCFG_SPID0_SCK, + SPID0_MOSI = GPCFG_SPID0_MOSI, + SPID0_SDIO = GPCFG_SPID0_SDIO, + SPID0_MISO = GPCFG_SPID0_MISO, + SPID0_NCSIN = GPCFG_SPID0_NCSIN, + SPID0_SCKIN = GPCFG_SPID0_SCKIN, + SPID1_NCS = GPCFG_SPID1_NCS, + SPID1_SCK = GPCFG_SPID1_SCK, + SPID1_MOSI = GPCFG_SPID1_MOSI, + SPID1_SDIO = GPCFG_SPID1_SDIO, + SPID1_MISO = GPCFG_SPID1_MISO, + SPID1_NCSIN = GPCFG_SPID1_NCSIN, + SPID1_SCKIN = GPCFG_SPID1_SCKIN, + NFC_CLK_OUT = GPCFG_NFC_CLK_OUT, + SCI7816_IO = GPCFG_SCI7816_IO, + IIC_SCL = GPCFG_IIC_SCL, + IIC_SDA = GPCFG_IIC_SDA, + JTAG_SWCLK = GPCFG_JTAG_SWCLK, + JTAG_SWDAT = GPCFG_JTAG_SWDAT, + OUTPUT_LOW = GPCFG_OUTPUT_LOW, + OUTPUT_HIGH = GPCFG_OUTPUT_HIGH, + PULL_UP = GPCFG_PU, + PULL_DOWN = GPCFG_PD, + ANALOG = GPCFG_ANALOG +} GPIO_FunTypeDef; + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xffff) /*!< Pin All selected */ + +#define IS_GPIO_PIN(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @brief GPIO group enumeration + */ +typedef enum +{ + GPIOA = 0, + GPIOB, + GPIOC +} GPIO_TypeDef; + +#define ISGPIOGROUP(groupx) (groupx < GPIO_GROUP_NUM) + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint16_t GPIO_Pin; + GPIO_ModeTypeDef GPIO_Mode; +} GPIO_InitTypeDef; + +/** + * @brief config gpio function(Only one can be configured at a time) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)(Only one can be configured at a time) + * + * @param function:gpio function + * + * @retval none + */ +void GPIO_Config(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, GPIO_FunTypeDef function); + +/** + * @brief gpio mode Init + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_InitStruct:GPIO_InitStruct + * + * @retval none + */ +void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @brief + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_7) + * + * @param NewState: new state of the port pin Pull Up.(ENABLE or DISABLE) + * + * @retval + */ +void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, FunctionalState NewState); + +/** + * @brief Reads the GPIO input data(status) for byte. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @retval GPIO input data(status). + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx); + +/** + * @brief Reads the GPIO input data(status) for bit. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval The input status + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief Reads the GPIO output data(status) for byte. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @retval GPIO output data(status). + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx); + +/** + * @brief Reads the GPIO output data(status) for bit. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval The output status + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief Clears the selected pin(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief sets the selected pin(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief init GPIO_InitStruct to default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @brief Writes data to the GPIO group port(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param value: specifies the value to be written to the port output data register. + * + * @retval None + */ +void GPIO_Write(GPIO_TypeDef GPIOx, uint16_t value); + +/** + * @brief Sets or clears the selected data port bit(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_7) + * + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, BitAction BitVal); + +#endif /* __YC_GPIO_H__ */ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c new file mode 100644 index 0000000000..17172b7432 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c @@ -0,0 +1,72 @@ +/* +File Name : yc_systick.c +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : systick encapsulation. +*/ + +#include "yc_systick.h" + +tick SystickCount; + +void Systick_Dealy_Ms(uint32_t MS) +{ + uint32_t ReloadValue; + + ReloadValue = MS * 9600; + + *SYSTICK_CSR &= ~(((uint32_t)1) << SYSTICK_CSR_ENABLE); + *SYSTICK_RVR = ReloadValue; //Set the reload value + *SYSTICK_CVR = 0; //clear the current value + *SYSTICK_CSR |= ((SYSTICK_SYSCLOCK << SYSTICK_CSR_CLKSOURCE) | (1 << SYSTICK_CSR_ENABLE)); + + while (!(*SYSTICK_CVR == 0)); + *SYSTICK_RVR = 0; +} + +uint32_t SysTick_Config(uint32_t ReloadValue) +{ + ReloadValue -= 1; + if (!IS_RELOAD_VALUE(ReloadValue)) + return 1; + + *SYSTICK_CSR &= ~(((uint32_t)1) << SYSTICK_CSR_ENABLE); + + *SYSTICK_RVR = ReloadValue; //Set the reload value + *SYSTICK_CVR = 0; //clear the current value + SystickCount = 0; // Reset the overflow counter + *SYSTICK_CSR |= + ((SYSTICK_SYSCLOCK << SYSTICK_CSR_CLKSOURCE) | + (1 << SYSTICK_CSR_ENABLE) | + (1 << SYSTICK_CSR_TICKINT)); + return 0; +} + +tick SysTick_GetTick() +{ + return SystickCount; +} + +Boolean SysTick_IsTimeOut(tick start_tick, int interval) +{ + start_tick = SysTick_GetTick() - start_tick; + if (start_tick < 0) + start_tick += TICK_MAX_VALUE; + if (((start_tick * (*SYSTICK_RVR)) / (CPU_MHZ / 1000)) >= interval) + { + return TRUE; + } + else + { + return FALSE; + } +} + +uint32_t SysTick_GetRelativeTime(tick start_tick) +{ + start_tick = SysTick_GetTick() - start_tick; + if (start_tick < 0) + start_tick += TICK_MAX_VALUE; + return ((start_tick * (*SYSTICK_RVR)) / (CPU_MHZ / 1000)); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h new file mode 100644 index 0000000000..874056c2e3 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h @@ -0,0 +1,64 @@ +/* +File Name : yc_systick.h +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : systick encapsulation. +*/ + +#ifndef __YC_SYSTICK_H__ +#define __YC_SYSTICK_H__ +#include "..\core\yc3121.h" + +#define SYSTICK_SYSCLOCK 1 +#define SYSTICK_HALF_SYSCLOCK 0 + +#define IS_RELOAD_VALUE(x) (x>0&&x<=0xffffff) + +typedef int32_t tick; +#define TICK_MAX_VALUE (int32_t)0x7FFFFFFF + + +void Systick_Dealy_Ms(uint32_t MS); + +/** + * @brief Initialize systick and start systick + * + * @param ReloadValue : the systick reload value + * + * @retval 0:succeed 1:error + */ +uint32_t SysTick_Config(uint32_t ReloadValue); + + +/** + * @brief get the current value of SystickCount(SystickCount plus one for every overflow interrupt) + * + * @param none + * + * @retval current value of SystickCount + */ +tick SysTick_GetTick(void); + +/** + * @brief Determine whether the timeout that millisecond. + * + * @param start_tick:start tick + * + * @param interval:time interval(ms) + * + * @retval TRUE is timeout ,FALSE is not timeout + */ +Boolean SysTick_IsTimeOut(tick start_tick,int interval); + + +/** + * @brief get relative time . + * + * @param start_tick:start tick(start time) + * + * @retval the relative time(millisecond) + */ +uint32_t SysTick_GetRelativeTime(tick start_tick); + +#endif /* __YC_SYSTICK_H__ */ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c new file mode 100644 index 0000000000..1c26605e9a --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c @@ -0,0 +1,429 @@ +/* +File Name : yc_uart.c +Author : Yichip +Version : V1.0 +Date : 2019/12/4 +Description : UART encapsulation. +*/ +#include "yc_uart.h" + +#define uart_DMA_buf_len 1024 +uint8_t uart0_DMA_buf[uart_DMA_buf_len] = {0}; +uint8_t uart1_DMA_buf[uart_DMA_buf_len] = {0}; + +#define RX_ENABLE_BIT 0 +#define RX_ENABLE (1 << RX_ENABLE_BIT) + +#define UART_DMA_ENABLE_BIT 31 +#define UART_DMA_ENABLE (1 << UART_DMA_ENABLE_BIT) + +#define TX_INTR_ENABLE_BIT 31 +#define TX_INTR_ENABLE ((uint32_t)1 << TX_INTR_ENABLE_BIT) + +#define Set_RxITNum_Mask 0xff00 +#define Statu_RxNum_Mask (uint32_t)0xffff0000 + +void UART_AutoFlowCtrlCmd(UART_TypeDef UARTx, FunctionalState NewState) +{ + _ASSERT(IS_UART(UARTx)); + + if (NewState == ENABLE) + { + switch (UARTx) + { + case UART0: + UART0_CTRL |= FlowCtrl_Enable; + break; + case UART1: + UART1_CTRL |= FlowCtrl_Enable; + break; + } + } + else + { + switch (UARTx) + { + case UART0: + UART0_CTRL &= (~FlowCtrl_Enable); + break; + case UART1: + UART1_CTRL &= (~FlowCtrl_Enable); + break; + } + } + return; +} + +void UART_ClearIT(UART_TypeDef UARTx) +{ + uint8_t ITType = UART_GetITIdentity(UARTx); + UART_ITConfig(UARTx, ITType, DISABLE); +} + +void UART_DeInit(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + switch (UARTx) + { + case UART0: + UART0_CTRL = 0; + break; + case UART1: + UART1_CTRL = 0; + break; + } +} + +void UART_DMASendBuf(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + _ASSERT(IS_UART(UARTx)); + _ASSERT(NULL != buf); + _ASSERT((len < 0xffff)); + + if (UARTx == UART0) + { + DMA_SRC_ADDR(DMACH_UART0) = (int)buf; + DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | len << 16; + DMA_START(DMACH_UART0) = (1 << DMA_START_BIT); + } + else + { + DMA_SRC_ADDR(DMACH_UART1) = (int)buf; + DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | len << 16; + DMA_START(DMACH_UART1) = (1 << DMA_START_BIT); + } +} + +uint8_t UART_GetITIdentity(UART_TypeDef UARTx) +{ + uint8_t IT_Mode = 0; + switch (UARTx) + { + case UART0: + { + if (((UART0_CTRL & Set_RxITNum_Mask) > 0) && ((UART0_STATUS >> 16) > 0)) + { + IT_Mode = UART_IT_RX; + } + else + { + if ((UART0_CTRL & (uint32_t)TX_INTR_ENABLE)) + { + IT_Mode = UART_IT_TX; + } + else + { + IT_Mode = FALSE; + } + } + } + break; + + case UART1: + { + if (((UART1_CTRL & Set_RxITNum_Mask) > 0) && ((UART1_STATUS >> 16) > 0)) + { + IT_Mode = UART_IT_RX; + } + else + { + if (UART1_CTRL & TX_INTR_ENABLE) + { + IT_Mode = UART_IT_TX; + } + else + { + IT_Mode = FALSE; + } + } + } + break; + } + return IT_Mode; +} + +void UART_Init(UART_TypeDef UARTx, UART_InitTypeDef *UART_InitStruct) +{ +#define RESET_BAUD (1 << 7) +#define AUTO_BAUD (0 << 7) + uint32_t reg_value = 0; + uint32_t temp_baudrate = 0; + + _ASSERT(IS_UART(UARTx)); + _ASSERT(IS_MODE(UART_InitStruct->Mode)); + _ASSERT(IS_BAUDRATE(UART_InitStruct->BaudRate)); + _ASSERT(IS_PARITY(UART_InitStruct->Parity)); + _ASSERT(IS_FlowCtrl(UART_InitStruct->FlowCtrl)); + _ASSERT(IS_USART_STOPBITS(UART_InitStruct->StopBits)); + + temp_baudrate = ((48000000 / UART_InitStruct->BaudRate) << 16); + + reg_value = RX_ENABLE | + UART_InitStruct->Parity | + UART_InitStruct->DataBits | + UART_InitStruct->StopBits | + UART_InitStruct->FlowCtrl | + UART_InitStruct->Mode | + RESET_BAUD | + temp_baudrate; + + if (UARTx == UART0) + { + UART0_CTRL = 0; + DMA_DEST_ADDR(DMACH_UART0) = (int)uart0_DMA_buf; + DMA_LEN(DMACH_UART0) = uart_DMA_buf_len; + DMA_CONFIG(DMACH_UART0) = 1; + DMA_START(DMACH_UART0) |= (1 << (DMA_RESET_BIT)); + DMA_START(DMACH_UART0) &= ~(1 << (DMA_RESET_BIT)); + UART0_CTRL = 0; + UART0_CTRL = reg_value; + } + else + { + UART1_CTRL = 0; + DMA_DEST_ADDR(DMACH_UART1) = (int)uart1_DMA_buf; + DMA_LEN(DMACH_UART1) = uart_DMA_buf_len; + DMA_CONFIG(DMACH_UART1) = 1; + DMA_START(DMACH_UART1) |= (1 << (DMA_RESET_BIT)); + DMA_START(DMACH_UART1) &= ~(1 << (DMA_RESET_BIT)); + UART1_CTRL = 0; + UART1_CTRL = reg_value; + } + return; +} + +Boolean UART_IsRXFIFOFull(UART_TypeDef UARTx) +{ +#define BITRXFULL 1 + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (Boolean)(UART0_STATUS & (1 << BITRXFULL)); + } + else + { + return (Boolean)(UART1_STATUS & (1 << BITRXFULL)); + } +} + +Boolean UART_IsRXFIFONotEmpty(UART_TypeDef UARTx) +{ +#define BITRXEMPTY 0 + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (Boolean)((UART0_STATUS >> 16) ? 1 : 0); + } + else + { + return (Boolean)((UART1_STATUS >> 16) ? 1 : 0); + } +} + +Boolean UART_IsUARTBusy(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (Boolean)(!(DMA_STATUS(DMACH_UART0) & 1)); + } + else + { + return (Boolean)(!(DMA_STATUS(DMACH_UART1) & 1)); + } +} + +void UART_ITConfig(UART_TypeDef UARTx, uint32_t UART_IT, FunctionalState NewState) +{ + _ASSERT(IS_UART(UARTx)); + _ASSERT(IS_UART_IT(UART_IT)); + + switch (UARTx) + { + case UART0: + { + if (UART_IT == UART_IT_RX) + { + if (NewState) + { + UART0_CTRL |= ((ENABLE << 8)); + } + else + { + UART0_CTRL &= ~Set_RxITNum_Mask; + } + } + else if (UART_IT == UART_IT_TX) + { + UART0_CTRL &= (~TX_INTR_ENABLE); + UART0_CTRL |= (NewState << TX_INTR_ENABLE_BIT); + } + } + break; + + case UART1: + { + if (UART_IT == UART_IT_RX) + { + if (NewState) + { + UART1_CTRL |= ((ENABLE << 8)); + } + else + { + UART1_CTRL &= ~Set_RxITNum_Mask; + } + } + else if (UART_IT == UART_IT_TX) + { + UART1_CTRL &= (uint32_t)~TX_INTR_ENABLE; + UART1_CTRL |= (NewState << TX_INTR_ENABLE_BIT); + } + } + break; + } +} + +uint8_t UART_ReceiveData(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return UART0_RDATA; + } + else + { + return UART1_RDATA; + } +} + +int UART_RecvBuf(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + uint32_t length = 0; + volatile int *pstatus = NULL; + volatile unsigned char *pdata = NULL; + _ASSERT(IS_UART(UARTx)); + _ASSERT(NULL != buf); + + if (UART0 == UARTx) + { + pstatus = &UART0_STATUS; + pdata = &UART0_RDATA; + } + else + { + pstatus = &UART1_STATUS; + pdata = &UART1_RDATA; + } + + while ((*pstatus >> 16) > 0) + { + if (length < len) + { + buf[length++] = *pdata; + } + else + { + break; + } + } + + return length; +} + +void UART_SendBuf(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + _ASSERT(IS_UART(UARTx)); + _ASSERT(NULL != buf); + _ASSERT((len < 0xffff)); + + if (UARTx == UART0) + { + DMA_SRC_ADDR(DMACH_UART0) = (int)buf; + DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | len << 16; + DMA_START(DMACH_UART0) = (1 << DMA_START_BIT); + while ((!(DMA_STATUS(DMACH_UART0) & 1))); + } + else + { + DMA_SRC_ADDR(DMACH_UART1) = (int)buf; + DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | len << 16; + DMA_START(DMACH_UART1) = (1 << DMA_START_BIT); + while ((!(DMA_STATUS(DMACH_UART1) & 1))); + } +} + +void UART_SendData(UART_TypeDef UARTx, uint8_t Data) +{ + uint8_t buf[1] = {Data}; + + if (UARTx == UART0) + { + DMA_SRC_ADDR(DMACH_UART0) = (int)buf; + DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | 1 << 16; + DMA_START(DMACH_UART0) = (1 << DMA_START_BIT); + while (!(DMA_STATUS(DMACH_UART0) & 1)); + } + else + { + DMA_SRC_ADDR(DMACH_UART1) = (int)buf; + DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | 1 << 16; + DMA_START(DMACH_UART1) = (1 << DMA_START_BIT); + while (!(DMA_STATUS(DMACH_UART1) & 1)); + } +} + +void UART_SetITTimeout(UART_TypeDef UARTx, uint16_t timeout) +{ + if (UART0 == UARTx) + { + UART0_INTR = timeout; + } + else + { + UART1_INTR = timeout; + } +} + +void UART_SetRxITNum(UART_TypeDef UARTx, uint8_t Bcnt) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + UART0_CTRL = (UART0_CTRL & 0xffff00ff) | ((Bcnt & 0xff) << 8); + } + else + { + UART1_CTRL = (UART1_CTRL & 0xffff00ff) | ((Bcnt & 0xff) << 8); + } +} + +void UART_StructInit(UART_InitTypeDef *UART_InitStruct) +{ + UART_InitStruct->BaudRate = 9600; + UART_InitStruct->DataBits = Databits_8b; + UART_InitStruct->FlowCtrl = FlowCtrl_None; + UART_InitStruct->Mode = Mode_duplex; + UART_InitStruct->StopBits = StopBits_1; + UART_InitStruct->Parity = 0; +} + +uint16_t UART_ReceiveDataLen(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (uint16_t)(UART0_STATUS >> 16); + } + else + { + return (uint16_t)(UART1_STATUS >> 16); + } +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h new file mode 100644 index 0000000000..22cf4b9d34 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h @@ -0,0 +1,304 @@ +/* +File Name : yc_uart.h +Author : Yichip +Version : V1.0 +Date : 2019/12/4 +Description : UART encapsulation. +*/ +#ifndef __YC_UART_H__ +#define __YC_UART_H__ + +#include "yc3121.h" + +/** @def time of UART receive data time out intterrupt. real time = regvalue*48 + * @{ + */ +#define TIME_IT_TIMEOUT (uint16_t)0x01 + +/** @defgroup USART_Mode + * @{ + */ +#define Mode_Single_Line (1<<6) +#define Mode_duplex (0<<6) +#define IS_MODE(MODE) (((MODE) == Mode_Single_Line) ||\ + ((MODE) == Mode_duplex)) +/** + * @} + */ + +/** @ + * @defgroup USART_DataBits + */ +#define Databits_8b (0<<2) +#define Databits_9b (1<<2) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == Databits_8b) || \ + ((LENGTH) == Databits_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ +#define StopBits_1 (0<<3) +#define StopBits_2 (1<<3) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == StopBits_1) || \ + ((STOPBITS) == StopBits_2) ) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define FlowCtrl_None (0<<4) +#define FlowCtrl_Enable (1<<4) + +#define IS_FlowCtrl(CONTROL) (((CONTROL) == FlowCtrl_None) || \ + ((CONTROL) == FlowCtrl_Enable)) +/** + * @} + */ + +/** @defgroup UART_Interrupt_Type_definition + * @{ + */ +#define UART_IT_TX 0x01 +#define UART_IT_RX 0x02 +#define IS_UART_IT(x) (x == UART_IT_TX)||(x == UART_IT_RX) +/** + * @} + */ + +/** @defgroup USART_Parity +* @{ +*/ +#define Parity_None (0<<1) +#define Parity_Even (0<<1) +#define Parity_Odd (1<<1) +#define IS_PARITY(PARITY) (((PARITY) == Parity_Even) ||\ + ((PARITY) == Parity_None) ||\ + ((PARITY) == Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_BaudRate +* @{ +*/ +#define IS_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0x5B8) && ((BAUDRATE) < 0x0044AA21)) +/** + * @} + */ + +typedef struct +{ + uint8_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint32_t BaudRate; /*!< This member configures the USART communication baud rate. */ + + uint8_t DataBits; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_DataBits */ + + uint8_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint8_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint8_t FlowCtrl; /*!< Specifies wether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ + + int RxBufLen; /*!< Specifies uart DMA Rx buff length */ + +} UART_InitTypeDef; + +/** @defgroup UART_TypeDef +* @{ +*/ +typedef enum +{ + UART0 = 0, + UART1, +} UART_TypeDef; + +#define IS_UART(UARTx) (UARTx == UART0 ||UARTx == UART1) +/** + * @} + */ + +/** + * @brief ENABLE or DISABLE UARTx auto flow control + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param NewState:ENABLE or DISABLE auto flow control + * @retval None + */ +void UART_AutoFlowCtrlCmd(UART_TypeDef UARTx, FunctionalState NewState); + +/** + * @brief Clear IT + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @retval None + */ +void UART_ClearIT(UART_TypeDef UARTx); + +/** + * @brief DeInit UART + * @param UARTx: Select the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @retval None + */ +void UART_DeInit(UART_TypeDef UARTx); + +/** + * @brief Transmits datas via UART DMA . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param buf: pointer to a buf that contains the data you want transmit. + * @param len: the buf length + * @retval None + */ +void UART_DMASendBuf(UART_TypeDef UARTx, uint8_t *buf, int len); + +/** + * @brief Get IT Identity + * @param UARTx: Select the UART peripheral. + * @retval IT Identity + */ +uint8_t UART_GetITIdentity(UART_TypeDef UARTx); + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param UARTx: Select the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART + * peripheral. + * @retval None + */ +void UART_Init(UART_TypeDef UARTx, UART_InitTypeDef *UART_InitStruct); + +/** + * @brief Judge Rx fifo full is or not. + * @param UARTx: Select the UART peripheral. + * @retval TRUE:Rx fifo is full. + * FALSE:Rx fifo is not full + */ +Boolean UART_IsRXFIFOFull(UART_TypeDef UARTx); + +/** + * @brief Judge Rx fifo empty is or not. + * @param UARTx: Select the UART peripheral. + * @retval TRUE:Rx fifo is not empty. + * FALSE:Rx fifo is empty; + */ +Boolean UART_IsRXFIFONotEmpty(UART_TypeDef UARTx); + +/** + * @brief Judge UART is Busy or not + * @param UARTx: Select the UART peripheral. + * @retval None + */ +Boolean UART_IsUARTBusy(UART_TypeDef UARTx); + +/** + * @brief Config Interrupt trigger mode + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param UART_IT: Interrupt trigger mode ,this param will the following values, + * UART_IT_TX:interrupt trigger after send data completed. + * UART_IT_RX:interrupt trigger when received data. + * @param NewState: + * @retval None + */ +void UART_ITConfig(UART_TypeDef UARTx, uint32_t UART_IT, FunctionalState NewState); + +/** + * @brief Receive single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @retval None + */ +uint8_t UART_ReceiveData(UART_TypeDef UARTx); + +/** + * @brief Receives datas through the UART DMA. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param buf: pointer to a buf that contains the data you want receive. + * @param len: the buf length + * @retval None + */ +int UART_RecvBuf(UART_TypeDef UARTx, uint8_t *buf, int len); + +/** + * @brief T ransmits datas via UART DMA,the function will return after datas is sent. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param buf: pointer to a buf that contains the data you want transmit. + * @param len: the buf length + * @retval None + */ +void UART_SendBuf(UART_TypeDef UARTx, uint8_t *buf, int len); + +/** + * @brief UART Send One Data + * @param UARTx: Select the UART peripheral. + * @retval None + */ +void UART_SendData(UART_TypeDef UARTx, uint8_t Data); + +/** + * @brief UART_SetITTimeout + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * timeout: 0x0000~0xffff + * @retval None + */ +void UART_SetITTimeout(UART_TypeDef UARTx, uint16_t timeout); + +/** + * @brief Set the number of uart receive data intterupt trigger + * @param UARTx: Select the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param Bcnt: if the number of receive datas greater than Bcnt,interrupt trigger + * @retval None + */ +void UART_SetRxITNum(UART_TypeDef UARTx, uint8_t Bcnt); + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitTypeDef *UART_InitStruct); + +/** + * @brief UART_ReceiveDataLen + * @param UARTx: UART0 or UART1 + * @retval Data len + */ +uint16_t UART_ReceiveDataLen(UART_TypeDef UARTx); + +#endif /*__YC_UART_H__*/ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c new file mode 100644 index 0000000000..8b4948b798 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c @@ -0,0 +1,54 @@ +#include "yc_wdt.h" + +#define WDT_ENABLE_BIT_Mask 6 +#define WDT_MODE_BIT_Mask 5 +#define SYSCTRL_WDT_EN_BIT_Mask 1 + +/**************the value of feed dog************/ +#define COUNTER_RELOAD_KEY 0x5937 + +void WDT_SetReload(uint32_t Reload) +{ + uint32_t wdt_config = 0; + + _ASSERT(ISWDTRELOAD(Reload)); + + wdt_config = WD_CONFIG; + wdt_config &= 0xE0; + wdt_config |= Reload; + WD_CONFIG = wdt_config; +} + +void WDT_ReloadCounter(void) +{ + WD_KICK = COUNTER_RELOAD_KEY; +} + +void WDT_Enable(void) +{ + WD_CONFIG |= (1 << WDT_ENABLE_BIT_Mask); +} + +void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode) +{ + WD_CONFIG &= ~(1 << WDT_MODE_BIT_Mask); + WD_CONFIG |= (WDT_Mode << WDT_MODE_BIT_Mask); + if (WDT_CPUReset == WDT_Mode) + { + SYSCTRL_RST_EN |= (1 << 1); + } + else + { + SYSCTRL_RST_EN &= ~(1 << 1); + } +} + +ITStatus WDT_GetITStatus(void) +{ + return (ITStatus)(WD_KICK & 1); +} + +void WDT_ClearITPendingBit(void) +{ + WD_CLEAR = 1; +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h new file mode 100644 index 0000000000..e9594d035e --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file yc_wdt.h + * @author Yichip + * @version V1.0 + * @date 7-Dec-2019 + * @brief watchdog encapsulation. + * + ****************************************************************************** + */ + +#ifndef __YC_WDT_H__ +#define __YC_WDT_H__ + +#include "yc3121.h" + +/** + * @brief timer number Structure definition + */ +typedef enum +{ + WDT_CPUReset = 0, + WDT_Interrupt, +} WDT_ModeTypeDef; + +#define ISWDTRELOAD(load) (load>0&&load<=0x1f) + +/** + * @brief Set reload counter + * @param Reload: Reload counter equal to 2^reload. + * @retval none + */ +void WDT_SetReload(uint32_t Reload); + +/** + * @brief Set WDT mode + * @param WDT_Mode : Select the following values : + * WDT_CPUReset + * WDT_Interrupt. + * @retval none + * @description If Select WDT_CPUReset Mode,the bit for WDT RESET will be set;if + * Select WDT_Interrupt the bit for WDT RESET will + */ +void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode); + +/** + * @brief Get interrupt Status + * @param none + * @retval SET:interrupt ocuured. + */ +ITStatus WDT_GetITStatus(void); + +/** + * @brief Clear interrupt + * @param none + * @retval none + */ +void WDT_ClearITPendingBit(void); + +/** + * @brief Enable WDT + * @param none + * @retval none + */ +void WDT_Enable(void); + +/** + * @brief Feed the watchdog function + * @param none + * @retval none + */ +void WDT_ReloadCounter(void); + +#endif /*__YC_WDT_H__*/ diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s new file mode 100644 index 0000000000..6c354c6f39 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s @@ -0,0 +1,396 @@ + AREA |.flash_start|, CODE, READONLY ,ALIGN=4 + +Reset_Handler PROC + EXPORT Reset_Handler + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + + +hard_fault_handler PROC + EXPORT hard_fault_handler + IMPORT HardFault_Handler + ldr r0,=HardFault_Handler + bx r0 + nop + ENDP + +svc_handler PROC + EXPORT svc_handler + ldr r0,=SVC_IRQHandler + bx r0 + nop + ENDP + +pendsv_handler PROC + EXPORT pendsv_handler + IMPORT PendSV_Handler + ldr r0,=PendSV_Handler + bx r0 + nop + ENDP + +systick PROC + EXPORT systick + IMPORT SysTick_Handler + ldr r0,=SysTick_Handler + bx r0 + nop + ENDP + +irq0 PROC + EXPORT irq0 + movs r0,#4*0 + b isr + ENDP + +irq1 PROC + EXPORT irq1 + movs r0,#4*1 + b isr + ENDP + +irq2 PROC + EXPORT irq2 + movs r0,#4*2 + b isr + ENDP + +irq3 PROC + EXPORT irq3 + movs r0,#4*3 + b isr + ENDP + +irq4 PROC + EXPORT irq4 + movs r0,#4*4 + b isr + ENDP + +irq5 PROC + EXPORT irq5 + movs r0,#4*5 + b isr + ENDP + +irq6 PROC + EXPORT irq6 + movs r0,#4*6 + b isr + ENDP + +irq7 PROC + EXPORT irq7 + movs r0,#4*7 + b isr + ENDP + +irq8 PROC + EXPORT irq8 + movs r0,#4*8 + b isr + ENDP + +irq9 PROC + EXPORT irq9 + movs r0,#4*9 + b isr + ENDP + +irq10 PROC + EXPORT irq10 + movs r0,#4*10 + b isr + ENDP + +irq11 PROC + EXPORT irq11 + movs r0,#4*11 + b isr + ENDP + +irq12 PROC + EXPORT irq12 + movs r0,#4*12 + b isr + ENDP + +irq13 PROC + EXPORT irq13 + movs r0,#4*13 + b isr + ENDP + +irq14 PROC + EXPORT irq14 + movs r0,#4*14 + b isr + ENDP + +irq15 PROC + EXPORT irq15 + movs r0,#4*15 + b isr + ENDP + +irq16 PROC + EXPORT irq16 + movs r0,#4*16 + b isr + ENDP + +irq17 PROC + EXPORT irq17 + movs r0,#4*17 + b isr + ENDP + +irq18 PROC + EXPORT irq18 + movs r0,#4*18 + b isr + ENDP + +irq19 PROC + EXPORT irq19 + movs r0,#4*19 + b isr + ENDP + +irq20 PROC + EXPORT irq20 + movs r0,#4*20 + b isr + ENDP + +irq21 PROC + EXPORT irq21 + movs r0,#4*21 + b isr + ENDP + +irq22 PROC + EXPORT irq22 + movs r0,#4*22 + b isr + ENDP + +irq23 PROC + EXPORT irq23 + movs r0,#4*23 + b isr + ENDP + +irq24 PROC + EXPORT irq24 + movs r0,#4*24 + b isr + ENDP + +irq25 PROC + EXPORT irq25 + movs r0,#4*25 + b isr + ENDP + +irq26 PROC + EXPORT irq26 + movs r0,#4*26 + b isr + ENDP + +irq27 PROC + EXPORT irq27 + movs r0,#4*27 + b isr + ENDP + +irq28 PROC + EXPORT irq28 + movs r0,#4*28 + b isr + ENDP + +irq29 PROC + EXPORT irq29 + movs r0,#4*29 + b isr + ENDP + +irq30 PROC + EXPORT irq30 + movs r0,#4*30 + b isr + ENDP + +irq31 PROC + EXPORT irq31 + movs r0,#4*31 + b isr + ENDP + + +isr PROC + ldr r1,=isr_table + ldr r0,[r0, r1] + bx r0 + ENDP + + ALIGN +NMI_IRQHandler PROC + EXPORT NMI_IRQHandler [WEAK] + B . + ENDP + +HARD_FAULT_IRQHandler PROC + EXPORT HARD_FAULT_IRQHandler [WEAK] + B . + ENDP + +SVC_IRQHandler PROC + EXPORT SVC_IRQHandler [WEAK] + B . + ENDP + +PENDSV_IRQHandler PROC + EXPORT PENDSV_IRQHandler [WEAK] + B . + ENDP + +SYSTICK_IRQHandler PROC + EXPORT SYSTICK_IRQHandler [WEAK] + B . + ENDP + +EXTI0_IRQHandler PROC + EXPORT EXTI0_IRQHandler [WEAK] + B . + ENDP + +EXTI1_IRQHandler PROC + EXPORT EXTI1_IRQHandler [WEAK] + B . + ENDP + +EXTI2_IRQHandler PROC + EXPORT EXTI2_IRQHandler [WEAK] + B . + ENDP + +EXTI3_IRQHandler PROC + EXPORT EXTI3_IRQHandler [WEAK] + B . + ENDP + +EXTI4_IRQHandler PROC + EXPORT EXTI4_IRQHandler [WEAK] + B . + ENDP + +EXTI5_IRQHandler PROC + EXPORT EXTI5_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; ToDo: Add here the export definition for the device specific external interrupts handler + EXPORT USB_IRQHandler [WEAK] + EXPORT IIC_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT MEMCP_IRQHandler [WEAK] + EXPORT RSA_IRQHandler [WEAK] + EXPORT SCI0_IRQHandler [WEAK] + EXPORT SCI1_IRQHandler [WEAK] + EXPORT BT_IRQHandler [WEAK] + EXPORT GPIO_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT TIMER7_IRQHandler [WEAK] + EXPORT TIMER8_IRQHandler [WEAK] + EXPORT SM4_IRQHandler [WEAK] + EXPORT SEC_IRQHandler [WEAK] + EXPORT MSR_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + +; ToDo: Add here the names for the device specific external interrupts handler +USB_IRQHandler +IIC_IRQHandler +QSPI_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +MEMCP_IRQHandler +RSA_IRQHandler +SCI0_IRQHandler +SCI1_IRQHandler +BT_IRQHandler +GPIO_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +TIMER4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +TIMER7_IRQHandler +TIMER8_IRQHandler +SM4_IRQHandler +SEC_IRQHandler +MSR_IRQHandler +TRNG_IRQHandler +WDT_IRQHandler + B . + ENDP + + + + EXPORT isr_table +isr_table DCD USB_IRQHandler + DCD IIC_IRQHandler + DCD QSPI_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD MEMCP_IRQHandler + DCD RSA_IRQHandler + DCD SCI0_IRQHandler + DCD SCI1_IRQHandler + DCD BT_IRQHandler + DCD GPIO_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD TIMER3_IRQHandler + DCD TIMER4_IRQHandler + DCD TIMER5_IRQHandler + DCD TIMER6_IRQHandler + DCD TIMER7_IRQHandler + DCD TIMER8_IRQHandler + DCD SM4_IRQHandler + DCD SEC_IRQHandler + DCD MSR_IRQHandler + DCD TRNG_IRQHandler + DCD WDT_IRQHandler + END + + + + + + + + diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s new file mode 100644 index 0000000000..02302d303f --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s @@ -0,0 +1,318 @@ + .org 0x200 + .global Reset_Handler,hard_fault_handler,svc_handler,pendsv_handler,systick,irq0,irq1,irq2,irq3,irq4,irq5,irq6,irq7,irq8,irq9,irq10,irq11,irq12,irq13,irq14,irq15,irq16,irq17,irq18,irq19,irq20,irq21,irq22,irq23,irq24,irq25,irq26,irq27,irq28,irq29,irq30,irq31 + + .long + + +Reset_Handler: + ldr r0,=hardware_init + bx r0 + .thumb_func + +hard_fault_handler: + ldr r0,=HARD_FAULT_IRQHandler + bx r0 + nop + .thumb_func + +svc_handler: + ldr r0,=SVC_IRQHandler + bx r0 + nop + .thumb_func + +pendsv_handler: + ldr r0,=PENDSV_IRQHandler + bx r0 + nop + .thumb_func +systick: + ldr r0,=SYSTICK_IRQHandler + bx r0 + nop + .thumb_func +irq0: + mov r0,#4*0 + b isr + .thumb_func +irq1: + mov r0,#4*1 + b isr + .thumb_func +irq2: + mov r0,#4*2 + b isr + .thumb_func +irq3: + mov r0,#4*3 + b isr + .thumb_func +irq4: + mov r0,#4*4 + b isr + .thumb_func +irq5: + mov r0,#4*5 + b isr + .thumb_func +irq6: + mov r0,#4*6 + b isr + .thumb_func +irq7: + mov r0,#4*7 + b isr + .thumb_func +irq8: + mov r0,#4*8 + b isr + .thumb_func +irq9: + mov r0,#4*9 + b isr + .thumb_func +irq10: + mov r0,#4*10 + b isr + .thumb_func +irq11: + mov r0,#4*11 + b isr + .thumb_func +irq12: + mov r0,#4*12 + b isr + .thumb_func +irq13: + mov r0,#4*13 + b isr + .thumb_func +irq14: + mov r0,#4*14 + b isr + .thumb_func +irq15: + mov r0,#4*15 + b isr + .thumb_func +irq16: + mov r0,#4*16 + b isr + .thumb_func +irq17: + mov r0,#4*17 + b isr + .thumb_func +irq18: + mov r0,#4*18 + b isr + .thumb_func +irq19: + mov r0,#4*19 + b isr + .thumb_func +irq20: + mov r0,#4*20 + b isr + .thumb_func +irq21: + mov r0,#4*21 + b isr + .thumb_func +irq22: mov r0,#4*22 + b isr + .thumb_func +irq23: + mov r0,#4*23 + b isr + .thumb_func +irq24: + mov r0,#4*24 + b isr + .thumb_func +irq25: mov r0,#4*25 + b isr + .thumb_func +irq26: + mov r0,#4*26 + b isr + .thumb_func +irq27: + mov r0,#4*27 + b isr + .thumb_func +irq28: + mov r0,#4*28 + b isr + .thumb_func +irq29: + mov r0,#4*29 + b isr + .thumb_func +irq30: + mov r0,#4*30 + b isr + .thumb_func +irq31: + mov r0,#4*31 + b isr + .thumb_func + + + +isr: + ldr r1,=isr_table + ldr r0,[r0, r1] + bx r0 + + + + + .align 4 +isr_table: + .long USB_IRQHandler + .long IIC_IRQHandler + .long QSPI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long MEMCP_IRQHandler + .long RSA_IRQHandler + .long SCI0_IRQHandler + .long SCI1_IRQHandler + .long BT_IRQHandler + .long GPIO_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long TIMER5_IRQHandler + .long TIMER6_IRQHandler + .long TIMER7_IRQHandler + .long TIMER8_IRQHandler + .long SM4_IRQHandler + .long SEC_IRQHandler + .long MSR_IRQHandler + .long TRNG_IRQHandler + .long WDT_IRQHandler + + .thumb + .thumb_func +hardware_init: + ldr r1, =__exidx_start + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + sub r3, r2 + ble .L_loop1_done + + .L_loop1: + sub r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + + .L_loop1_done: + + + + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * _sbss: start of the BSS section. + * _ebss: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + mov r0, #0 + + sub r2, r1 + ble .L_loop3_done + + .L_loop3: + sub r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + .L_loop3_done: + ldr r0,=0x12345 + ldr r3,=0x1111 + bl main + + + .globl delay + .syntax unified +delay: + subs r0,#1 + bne delay + nop + bx lr + + + + + + + +.align 1 +.thumb_func +.weak Default_Handler +.type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler HARD_FAULT_IRQHandler + def_irq_handler SVC_IRQHandler + def_irq_handler PENDSV_IRQHandler + def_irq_handler SYSTICK_IRQHandler + def_irq_handler USB_IRQHandler + def_irq_handler IIC_IRQHandler + def_irq_handler QSPI_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler MEMCP_IRQHandler + def_irq_handler RSA_IRQHandler + def_irq_handler SCI0_IRQHandler + def_irq_handler SCI1_IRQHandler + def_irq_handler BT_IRQHandler + def_irq_handler GPIO_IRQHandler + def_irq_handler EXTI0_IRQHandler + def_irq_handler EXTI1_IRQHandler + def_irq_handler EXTI2_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler TIMER2_IRQHandler + def_irq_handler TIMER3_IRQHandler + def_irq_handler TIMER4_IRQHandler + def_irq_handler TIMER5_IRQHandler + def_irq_handler TIMER6_IRQHandler + def_irq_handler TIMER7_IRQHandler + def_irq_handler TIMER8_IRQHandler + def_irq_handler SM4_IRQHandler + def_irq_handler SEC_IRQHandler + def_irq_handler MSR_IRQHandler + def_irq_handler TRNG_IRQHandler + def_irq_handler WDT_IRQHandler + + + + + + diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s new file mode 100644 index 0000000000..a1307cd43d --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s @@ -0,0 +1,311 @@ + MODULE ?cstartup + + EXTERN __iar_program_start + + SECTION CSTACK:DATA:NOROOT(3) + + PUBLIC start_flash + SECTION .intvec:CODE:REORDER(2) +start_flash + LDR R0, =hardware_init + BX R0 + + PUBLIC hard_fault_handler +hard_fault_handler + BL HARD_FAULT_IRQHandler + + PUBLIC svc_handler +svc_handler + BL SVC_IRQHandler + + PUBLIC pendsv_handler +pendsv_handler + BL PENDSV_IRQHandler + + PUBLIC systick +systick + BL SYSTICK_IRQHandler + + PUBLIC irq0 +irq0 + movs r0,#0 + b isr + + PUBLIC irq1 +irq1 + movs r0,#1 + b isr + + PUBLIC irq2 +irq2 + movs r0,#2 + b isr + + PUBLIC irq3 +irq3 + movs r0,#3 + b isr + + PUBLIC irq4 +irq4 + movs r0,#4 + b isr + + PUBLIC irq5 +irq5 + movs r0,#5 + b isr + + PUBLIC irq6 +irq6 + movs r0,#6 + b isr + + PUBLIC irq7 +irq7 + movs r0,#7 + b isr + + PUBLIC irq8 +irq8 + movs r0,#8 + b isr + + PUBLIC irq9 +irq9 + movs r0,#9 + b isr + + PUBLIC irq10 +irq10 + movs r0,#10 + b isr + + PUBLIC irq11 +irq11 + movs r0,#11 + b isr + + PUBLIC irq12 +irq12 + movs r0,#12 + b isr + + PUBLIC irq13 +irq13 + movs r0,#13 + b isr + + PUBLIC irq14 +irq14 + movs r0,#14 + b isr + + PUBLIC irq15 +irq15 + movs r0,#15 + b isr + + PUBLIC irq16 +irq16 + movs r0,#16 + b isr + + PUBLIC irq17 +irq17 + movs r0,#17 + b isr + + PUBLIC irq18 +irq18 + movs r0,#18 + b isr + + PUBLIC irq19 +irq19 + movs r0,#19 + b isr + + PUBLIC irq20 +irq20 + movs r0,#20 + b isr + + PUBLIC irq21 +irq21 + movs r0,#21 + b isr + + PUBLIC irq22 +irq22 + movs r0,#22 + b isr + + PUBLIC irq23 +irq23 + movs r0,#23 + b isr + + PUBLIC irq24 +irq24 + movs r0,#24 + b isr + + PUBLIC irq25 +irq25 + movs r0,#25 + b isr + + PUBLIC irq26 +irq26 + movs r0,#26 + b isr + + PUBLIC irq27 +irq27 + movs r0,#27 + b isr + + PUBLIC irq28 +irq28 + movs r0,#28 + b isr + + PUBLIC irq29 +irq29 + movs r0,#29 + b isr + + PUBLIC irq30 +irq30 + movs r0,#30 + b isr + + PUBLIC irq31 +irq31 + movs r0,#31 + b isr + + PUBLIC isr +isr + ldr r1,=__vector_table + ldr r0,[r0, r1] + bx r0 + + + PUBWEAK HARD_FAULT_IRQHandler + PUBWEAK SVC_IRQHandler + PUBWEAK PENDSV_IRQHandler + PUBWEAK SYSTICK_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK IIC_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK MEMCP_IRQHandler + PUBWEAK RSA_IRQHandler + PUBWEAK SCI0_IRQHandler + PUBWEAK SCI1_IRQHandler + PUBWEAK BT_IRQHandler + PUBWEAK GPIO_IRQHandler + PUBWEAK TIMER0_IRQHandler + PUBWEAK TIMER1_IRQHandler + PUBWEAK TIMER2_IRQHandler + PUBWEAK TIMER3_IRQHandler + PUBWEAK TIMER4_IRQHandler + PUBWEAK TIMER5_IRQHandler + PUBWEAK TIMER6_IRQHandler + PUBWEAK TIMER7_IRQHandler + PUBWEAK TIMER8_IRQHandler + PUBWEAK SM4_IRQHandler + PUBWEAK SEC_IRQHandler + PUBWEAK MSR_IRQHandler + PUBWEAK TRNG_IRQHandler + PUBWEAK WDT_IRQHandler + + +HARD_FAULT_IRQHandler +SVC_IRQHandler +PENDSV_IRQHandler +SYSTICK_IRQHandler + +USB_IRQHandler +IIC_IRQHandler +QSPI_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +MEMCP_IRQHandler +RSA_IRQHandler +SCI0_IRQHandler +SCI1_IRQHandler +BT_IRQHandler +GPIO_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +TIMER4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +TIMER7_IRQHandler +TIMER8_IRQHandler +SM4_IRQHandler +SEC_IRQHandler +MSR_IRQHandler +TRNG_IRQHandler +WDT_IRQHandler + B . + + PUBLIC delay +delay + subs r0,#1 + bne delay + nop + bx lr + + PUBLIC __vector_table + ALIGNROM 2 + data +__vector_table + DCD USB_IRQHandler + DCD IIC_IRQHandler + DCD QSPI_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD MEMCP_IRQHandler + DCD RSA_IRQHandler + DCD SCI0_IRQHandler + DCD SCI1_IRQHandler + DCD BT_IRQHandler + DCD GPIO_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD TIMER3_IRQHandler + DCD TIMER4_IRQHandler + DCD TIMER5_IRQHandler + DCD TIMER6_IRQHandler + DCD TIMER7_IRQHandler + DCD TIMER8_IRQHandler + DCD SM4_IRQHandler + DCD SEC_IRQHandler + DCD MSR_IRQHandler + DCD TRNG_IRQHandler + DCD WDT_IRQHandler + + + PUBLIC hardware_init + SECTION .intvec:CODE:REORDER(2) + CODE +hardware_init + LDR R0, =sfe(CSTACK) + mov sp, R0 + LDR R0, =__iar_program_start + BX R0 + END \ No newline at end of file diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/startup.s b/bsp/yichip/yc3121-pos/Libraries/startup/startup.s new file mode 100644 index 0000000000..23aecc12b2 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/startup.s @@ -0,0 +1,175 @@ +Stack_Size EQU 0x0000100 + + AREA STACK, NOINIT, READWRITE, ALIGN=4 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x30000 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + AREA HEAP, NOINIT, READWRITE, ALIGN=4 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + IMPORT systick + IMPORT irq0 + IMPORT irq1 + IMPORT irq2 + IMPORT irq3 + IMPORT irq4 + IMPORT irq5 + IMPORT irq6 + IMPORT irq7 + IMPORT irq8 + IMPORT irq9 + IMPORT irq10 + IMPORT irq11 + IMPORT irq12 + IMPORT irq13 + IMPORT irq14 + IMPORT irq15 + IMPORT irq16 + IMPORT irq17 + IMPORT irq18 + IMPORT irq19 + IMPORT irq20 + IMPORT irq21 + IMPORT irq22 + IMPORT irq23 + IMPORT irq24 + IMPORT irq25 + IMPORT irq26 + IMPORT irq27 + IMPORT irq28 + IMPORT irq29 + IMPORT irq30 + IMPORT irq31 + IMPORT hard_fault_handler + + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size +__Vectors DCD __initial_sp ; Top of Stack + DCD reset_handler ; Reset Handler + DCD nmi_handler ; NMI Handler + DCD hard_fault_handler ; Hard Fault Handler + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD systick ; + DCD irq0 ; + DCD irq1 ; + DCD irq2 ; + DCD irq3 ; + DCD irq4 ; + DCD irq5 ; + DCD irq6 ; + DCD irq7 ; + DCD irq8 ; + DCD irq9 ; + DCD irq10 ; + DCD irq11 ; + DCD irq12 ; + DCD irq13 ; + DCD irq14 ; + DCD irq15 ; + DCD irq16 ; + DCD irq17 ; + DCD irq18 ; + DCD irq19 ; + DCD irq20 ; + DCD irq21 ; + DCD irq22 ; + DCD irq23 ; + DCD irq24 ; + DCD irq25 ; + DCD irq26 ; + DCD irq27 ; + DCD irq28 ; + DCD irq29 ; + DCD irq30 ; + DCD irq31 ; +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY ,ALIGN=4 + + + +; Reset Handler + +reset_handler PROC + EXPORT reset_handler [WEAK] + IMPORT Reset_Handler +; bl Reset_Handler +; movs r0,#0x3 + + LDR R0, =Reset_Handler + BX R0 + nop + ENDP + + + +delay PROC + EXPORT delay + subs r0,#1 + bne delay + nop + bx lr + ENDP + +nmi_handler PROC + EXPORT nmi_handler [WEAK] + b nmi_handler + ENDP + + ALIGN + + AREA |.INIT_STACK_HEAP|, CODE,READONLY,ALIGN=4 +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, = __initial_sp + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END \ No newline at end of file diff --git a/bsp/yichip/yc3121-pos/README.md b/bsp/yichip/yc3121-pos/README.md new file mode 100644 index 0000000000..b800866155 --- /dev/null +++ b/bsp/yichip/yc3121-pos/README.md @@ -0,0 +1,42 @@ +# YC3121-pos 板级支持包 说明 + +标签： YICHIP、Cortex-M0、YC3121、国产MCU + +--- + +## 1. 简介 + +本文档为 YC3121-pos 的 BSP(板级支持包) 说明。 + +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +YC3121-pos 开发板由易兆微提供，可满足基础测试及高端开发需求。 + +开发板外观如下图所示： + +YC3121-pos + +![YC3121-pos](figures/YC3121-pos.jpg "YC3121-pos") + +YC3121-pos 开发板板载资源如下： + +- MCU：YC3121 ARM 32-bit Cortex-M0，主频 96MHz，512KB FLASH ，64KB SRAM +- 常用外设 + - LED：4 个 + - 梯形矩阵键盘 + - 蜂鸣器 + - USB + - UART + - SPI LCD + - SPI NFC + - 7816接口 （接触IC卡，支持3V , 1.8V） + - 7811接口 （三轨磁条卡解码模块，支持ISO/ABA AAMVA 及IBM等标准卡） + - TIMER：9个32bi位 （支持PWM） + - TRNG：（1个真随机数发生器） + - 安全加密算法 + - 对称算法：对称算法：DES、TDES、AES-128/192/256、国密IV（SM4） + - 非对称算法：RSA-1024/2048、国密II（SM2）、ECC + - HASH 校验算法：SHA-1/224/256/384/512、国密III（SM3） +- 调试接口：SWD / ICE diff --git a/bsp/yichip/yc3121-pos/SConscript b/bsp/yichip/yc3121-pos/SConscript new file mode 100644 index 0000000000..1b1c7506a4 --- /dev/null +++ b/bsp/yichip/yc3121-pos/SConscript @@ -0,0 +1,11 @@ +from building import * + +cwd = GetCurrentDir() + +objs = [] +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +Return('objs') diff --git a/bsp/yichip/yc3121-pos/SConstruct b/bsp/yichip/yc3121-pos/SConstruct new file mode 100644 index 0000000000..8418d596c0 --- /dev/null +++ b/bsp/yichip/yc3121-pos/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/yichip/yc3121-pos/applications/SConscript b/bsp/yichip/yc3121-pos/applications/SConscript new file mode 100644 index 0000000000..6452d39145 --- /dev/null +++ b/bsp/yichip/yc3121-pos/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/yichip/yc3121-pos/applications/main.c b/bsp/yichip/yc3121-pos/applications/main.c new file mode 100644 index 0000000000..2ee0856d85 --- /dev/null +++ b/bsp/yichip/yc3121-pos/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#include +/* defined the LED pin: PA12 */ +#define LED_PIN 2 + +int main(void) +{ + int count = 1; + /* set LED4 pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/yichip/yc3121-pos/drivers/Kconfig b/bsp/yichip/yc3121-pos/drivers/Kconfig new file mode 100644 index 0000000000..e0c1ca9902 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/Kconfig @@ -0,0 +1,22 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menu "UART Drivers" + config BSP_USING_UART0 + bool "Enable UART0 PA2/3(R/T)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Enable UART1 PC2/3(R/T)" + select RT_USING_SERIAL + default n + endmenu + endmenu + +endmenu diff --git a/bsp/yichip/yc3121-pos/drivers/SConscript b/bsp/yichip/yc3121-pos/drivers/SConscript new file mode 100644 index 0000000000..df6a78e8a8 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/SConscript @@ -0,0 +1,25 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +# add gpio driver code +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): + src += ['drv_uart.c'] + + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/yichip/yc3121-pos/drivers/board.c b/bsp/yichip/yc3121-pos/drivers/board.c new file mode 100644 index 0000000000..361be18882 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/board.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + static struct rt_memheap system_heap; +#endif +#define SystemCoreClock (48000000) + +static void bsp_clock_config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#ifdef RT_USING_SERIAL +extern int rt_hw_uart_init(void); +#endif + +void rt_hw_board_init() +{ + bsp_clock_config(); + +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* UART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/yichip/yc3121-pos/drivers/board.h b/bsp/yichip/yc3121-pos/drivers/board.h new file mode 100644 index 0000000000..573c6454a9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ +#include +#include +#include "yc_gpio.h" +#include "yc_uart.h" +#include "yc_systick.h" +#include "misc.h" + +#define SRAM_BASE 0x20000 +#define SRAM_SIZE 0x10000 + +#ifdef BSP_USING_EXT_SRAM + #define EXT_SRAM_BASE SRAMM_BASE + #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE + #define EXT_SRAM_BEGIN EXT_SRAM_BASE + #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#endif + +#define SRAM_END (SRAM_BASE + SRAM_SIZE) +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section = "HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/yichip/yc3121-pos/drivers/drv_gpio.c b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c new file mode 100644 index 0000000000..fc695a0318 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#include +#include +#include + +#define PIN_MAX_NUM (48) + +typedef void (*pin_callback_t)(void *args); +struct pin +{ + uint32_t package_index; + const char *name; + IRQn_Type irq; + rt_uint32_t irq_mode; + pin_callback_t callback; + void *callback_args; +}; +typedef struct pin pin_t; + + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + /* Configure GPIO_InitStructure */ + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_CONFIG(pin) = OUTPUT_LOW; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_CONFIG(pin) = INPUT; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_CONFIG(pin) = PULL_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_CONFIG(pin) = PULL_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_CONFIG(pin) = PULL_UP; + } +} + +static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + if (value) + { + GPIO_CONFIG(pin) = OUTPUT_HIGH; + } + else + { + GPIO_CONFIG(pin) = OUTPUT_LOW; + } +} + +static int yc_pin_read(rt_device_t dev, rt_base_t pin) +{ + return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0; +} + +static rt_err_t yc_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + pin_callback_t cb, + void *args) +{ + rt_int32_t index = -1; + rt_base_t level; + if (pin >= PIN_MAX_NUM) + { + return -RT_EINVAL; + } + + index = pin; + level = rt_hw_interrupt_disable(); + + pin_irq_hdr_tab[index].pin = pin; + pin_irq_hdr_tab[index].hdr = cb; + pin_irq_hdr_tab[index].mode = mode; + pin_irq_hdr_tab[index].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_int32_t index = -1; + rt_base_t level; + if (pin >= PIN_MAX_NUM) + { + return -RT_EINVAL; + } + + index = pin; + level = rt_hw_interrupt_disable(); + + pin_irq_hdr_tab[index].pin = -1; + pin_irq_hdr_tab[index].hdr = RT_NULL; + pin_irq_hdr_tab[index].mode = 0; + pin_irq_hdr_tab[index].args = RT_NULL; + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t yc_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) +{ + rt_int32_t index; + rt_base_t level = 0; + if (pin >= PIN_MAX_NUM) + { + return -RT_EINVAL; + } + + index = pin; + + if (enabled == PIN_IRQ_ENABLE) + { + switch (pin_irq_hdr_tab[index].mode) + { + case PIN_IRQ_MODE_RISING: + + break; + case PIN_IRQ_MODE_FALLING: + + break; + case PIN_IRQ_MODE_RISING_FALLING: + + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_CONFIG(pin) = PULL_DOWN; + GPIO_TRIG_MODE(pin / 16) &= (1 << (pin % 16)); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_CONFIG(pin) = PULL_UP; + GPIO_TRIG_MODE(pin / 16) |= (1 << (pin % 16)); + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + NVIC_EnableIRQ(GPIO_IRQn); + GPIO_INTR_EN(pin / 16) |= (1 << (pin % 16)); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + NVIC_DisableIRQ(GPIO_IRQn); + GPIO_INTR_EN(pin / 16) &= ~(1 << (pin % 16)); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops yc3121_pin_ops = +{ + yc_pin_mode, + yc_pin_write, + yc_pin_read, + yc_pin_attach_irq, + yc_pin_detach_irq, + yc_pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + result = rt_device_pin_register("pin", &yc3121_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void GPIO_IRQHandler(void) +{ + int i; + + rt_interrupt_enter(); + for (i = 0; i < PIN_MAX_NUM; i++) + { + if ((GPIO_TRIG_MODE(i / 16) & (1 << (i % 16))) == (GPIO_IN(i / 16) & (1 << (i % 16)))) + { + if (pin_irq_hdr_tab[i].hdr) + { + pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args); + } + } + } + rt_interrupt_leave(); +} diff --git a/bsp/yichip/yc3121-pos/drivers/drv_gpio.h b/bsp/yichip/yc3121-pos/drivers/drv_gpio.h new file mode 100644 index 0000000000..2f0bd6ce66 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/yichip/yc3121-pos/drivers/drv_uart.c b/bsp/yichip/yc3121-pos/drivers/drv_uart.c new file mode 100644 index 0000000000..973951663e --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_uart.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#include +#include + +struct yc3121_uart +{ + UART_TypeDef uart; + IRQn_Type irq; +}; + +static rt_err_t yc3121_uart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct yc3121_uart *uart; + UART_InitTypeDef UART_initStruct; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + NVIC_DisableIRQ(uart->irq); + UART_initStruct.BaudRate = cfg->baud_rate; + UART_initStruct.FlowCtrl = FlowCtrl_None ; + UART_initStruct.Mode = Mode_duplex; + + switch (cfg->data_bits) + { + case DATA_BITS_9: + UART_initStruct.DataBits = Databits_9b; + break; + default: + UART_initStruct.DataBits = Databits_8b; + break; + } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + UART_initStruct.StopBits = StopBits_2; + break; + default: + UART_initStruct.StopBits = StopBits_1; + break; + } + switch (cfg->parity) + { + case PARITY_ODD: + UART_initStruct.Parity = Parity_Odd; + break; + case PARITY_EVEN: + UART_initStruct.Parity = Parity_Even; + break; + default: + UART_initStruct.Parity = Parity_None; + break; + } + UART_Init(uart->uart, &UART_initStruct); + return RT_EOK; +} + +static rt_err_t yc3121_uart_control(struct rt_serial_device *serial, + int cmd, void *arg) +{ + struct yc3121_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_SetRxITNum(uart->uart, 0); + NVIC_DisableIRQ(uart->irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_SetRxITNum(uart->uart, 1); + UART_ITConfig(uart->uart, UART_IT_RX, ENABLE); + NVIC_EnableIRQ(uart->irq); + break; + } + return RT_EOK; +} + +static int yc3121_uart_putc(struct rt_serial_device *serial, char c) +{ + struct yc3121_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + while (UART_IsUARTBusy(uart->uart)); + UART_SendData(uart->uart, c); + return 1; +} + +static int yc3121_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct yc3121_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + ch = -1; + if (UART_ReceiveDataLen(uart->uart) != 0) + { + ch = UART_ReceiveData(uart->uart); + } + return ch; +} + +static const struct rt_uart_ops yc3121_uart_ops = +{ + yc3121_uart_configure, + yc3121_uart_control, + yc3121_uart_putc, + yc3121_uart_getc, +}; + +#if defined(BSP_USING_UART0) +/* UART0 device driver structure */ +static struct yc3121_uart uart0; +static struct rt_serial_device serial0; +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_GetITIdentity(uart0.uart) == UART_IT_RX) + { + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +static struct yc3121_uart uart1; +static struct rt_serial_device serial1; +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_GetITIdentity(uart1.uart) == UART_IT_RX) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +int rt_hw_uart_init(void) +{ + struct yc3121_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART0 + + GPIO_CONFIG(1) = UART0_TXD; + GPIO_CONFIG(0) = UART0_RXD; + uart = &uart0; + uart->uart = UART0; + uart->irq = UART0_IRQn; + serial0.ops = &yc3121_uart_ops; + serial0.config = config; + /* register UART0 device */ + rt_hw_serial_register(&serial0, RT_CONSOLE_DEVICE_NAME, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART0 */ +#ifdef BSP_USING_UART1 + GPIO_CONFIG(1) = UART1_TXD; + GPIO_CONFIG(0) = UART1_RXD; + uart = &uart1; + uart->uart = UART1; + uart->irq = UART1_IRQn; + serial1.ops = &yc3121_uart_ops; + serial1.config = config; + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ + return 0; +} diff --git a/bsp/yichip/yc3121-pos/drivers/drv_uart.h b/bsp/yichip/yc3121-pos/drivers/drv_uart.h new file mode 100644 index 0000000000..b4f84a1d93 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..25b66c5fe9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x1000200; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x1000200; +define symbol __ICFEDIT_region_ROM_end__ = 0x1ffffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0xF800; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..ab85fa4c13 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds @@ -0,0 +1,161 @@ +/* Linker script to configure memory regions. + * Need modifying for a specific board. + * FLASH.ORIGIN: starting address of flash + * FLASH.LENGTH: length of flash + * RAM.ORIGIN: starting address of RAM bank 0 + * RAM.LENGTH: length of RAM bank 0 + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x80000 /* 512K */ + RAM (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + *flash_start*.o + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + + . = ALIGN(4); + __exidx_start = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..71ad394af9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct @@ -0,0 +1,32 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0007fff { ; load region size_region + ER_IROM1 0x00000000 0x00007fff { ; load address = execution address + startup.o (RESET, +First) +; startup.o (.text,+RO) +; *(InRoot$$Sections) + } +} + +LR_IROM3 0x1000200 0x200{ + ER_IROM3 0x1000200 { + flash_start.o (|.flash_start|,+RO) + } + ER_IROM3_1 0x1000340 { + startup.o (|.INIT_STACK_HEAP|,+RO) + } +} + +LR_IROM4 0x1000400 0x1000000{ + ER_IROM4 0x1000400 { + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x00020000 0x010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg b/bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg new file mode 100644 index 0000000000..fa30094ed6 Binary files /dev/null and b/bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg differ diff --git a/bsp/yichip/yc3121-pos/project.ewd b/bsp/yichip/yc3121-pos/project.ewd new file mode 100644 index 0000000000..52cc221b07 --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 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$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/yichip/yc3121-pos/project.ewp b/bsp/yichip/yc3121-pos/project.ewp new file mode 100644 index 0000000000..2f7701c186 --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.ewp @@ -0,0 +1,2223 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + 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$PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + + Drivers + + $PROJ_DIR$\drivers\drv_gpio.c + + + $PROJ_DIR$\drivers\drv_uart.c + + + $PROJ_DIR$\drivers\board.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + + Libraries + + $PROJ_DIR$\Libraries\sdk\yc_dma.c + + + $PROJ_DIR$\Libraries\core\system.c + + + $PROJ_DIR$\Libraries\sdk\yc_systick.c + + + $PROJ_DIR$\Libraries\startup\flash_start_iar.s + + + $PROJ_DIR$\Libraries\core\bt_code_boot.c + + + $PROJ_DIR$\Libraries\sdk\yc_wdt.c + + + $PROJ_DIR$\Libraries\sdk\yc_gpio.c + + + $PROJ_DIR$\Libraries\core\misc.c + + + $PROJ_DIR$\Libraries\sdk\yc_uart.c + + + + utestcases + + diff --git a/bsp/yichip/yc3121-pos/project.eww b/bsp/yichip/yc3121-pos/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/yichip/yc3121-pos/project.uvoptx b/bsp/yichip/yc3121-pos/project.uvoptx new file mode 100644 index 0000000000..3ff6686c3f --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.uvoptx @@ -0,0 +1,781 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + JL2CM3 + -U788594195 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000 -FCA000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 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..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 16 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 22 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 23 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 24 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 25 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 26 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\memheap.c + memheap.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 8 + 37 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_wdt.c + yc_wdt.c + 0 + 0 + + + 8 + 38 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_uart.c + yc_uart.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_dma.c + yc_dma.c + 0 + 0 + + + 8 + 40 + 2 + 0 + 0 + 0 + Libraries\startup\flash_start.s + flash_start.s + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + Libraries\core\system.c + system.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_gpio.c + yc_gpio.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + Libraries\core\misc.c + misc.c + 0 + 0 + + + 8 + 44 + 2 + 0 + 0 + 0 + Libraries\startup\startup.s + startup.s + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_systick.c + yc_systick.c + 0 + 0 + + + + diff --git a/bsp/yichip/yc3121-pos/project.uvprojx b/bsp/yichip/yc3121-pos/project.uvprojx new file mode 100644 index 0000000000..0ddc763de2 --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.uvprojx @@ -0,0 +1,656 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + $$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --text -a -c --output=@L_asm.txt "!L" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;Libraries\sdk;Libraries\core;Libraries;..\..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + board.c + 1 + drivers\board.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + components.c + 1 + ..\..\..\src\components.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + device.c + 1 + ..\..\..\src\device.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + object.c + 1 + ..\..\..\src\object.c + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + yc_wdt.c + 1 + Libraries\sdk\yc_wdt.c + + + yc_uart.c + 1 + Libraries\sdk\yc_uart.c + + + yc_dma.c + 1 + Libraries\sdk\yc_dma.c + + + flash_start.s + 2 + Libraries\startup\flash_start.s + + + system.c + 1 + Libraries\core\system.c + + + yc_gpio.c + 1 + Libraries\sdk\yc_gpio.c + + + misc.c + 1 + Libraries\core\misc.c + + + startup.s + 2 + Libraries\startup\startup.s + + + yc_systick.c + 1 + Libraries\sdk\yc_systick.c + + + + + + + + + + + + + + diff --git a/bsp/yichip/yc3121-pos/rtconfig.h b/bsp/yichip/yc3121-pos/rtconfig.h new file mode 100644 index 0000000000..d163fef848 --- /dev/null +++ b/bsp/yichip/yc3121-pos/rtconfig.h @@ -0,0 +1,178 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_SWM320VET7 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART0 + +#endif diff --git a/bsp/yichip/yc3121-pos/rtconfig.py b/bsp/yichip/yc3121-pos/rtconfig.py new file mode 100644 index 0000000000..f07430c42e --- /dev/null +++ b/bsp/yichip/yc3121-pos/rtconfig.py @@ -0,0 +1,152 @@ +# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) + +import os +import sys +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# device options +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:\gcc-arm-none-eabi-7-2018-q2-update-win32' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf.exe --text -a -c --output=@L_asm.txt "!L" \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/yichip/yc3121-pos/template.ewp b/bsp/yichip/yc3121-pos/template.ewp new file mode 100644 index 0000000000..2ff75d9abc --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.ewp @@ -0,0 +1,2032 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/yichip/yc3121-pos/template.eww b/bsp/yichip/yc3121-pos/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/yichip/yc3121-pos/template.uvopt b/bsp/yichip/yc3121-pos/template.uvopt new file mode 100644 index 0000000000..0e93bee143 --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.uvopt @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00053488.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/yichip/yc3121-pos/template.uvoptx b/bsp/yichip/yc3121-pos/template.uvoptx new file mode 100644 index 0000000000..3534243b9f --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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