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[docs][libcpu][arm][cortex-a] correct TLBIALL comments in start_gcc.S
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This commit is contained in:
laidene
2026-04-02 09:36:07 +08:00
committed by Rbb666
parent ebe65849db
commit 11a1348ed6
1 changed files with 3 additions and 3 deletions
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libcpu/arm/cortex-a/start_gcc.S
+3 -3
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@@ -182,7 +182,7 @@ continue_exit:
/* invalidate TLB, I-cache and branch predictor */ /* invalidate TLB, I-cache and branch predictor */
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */ mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
dsb dsb
@@ -268,7 +268,7 @@ enable_mmu_page_table_early:
/* invalidate TLB, I-cache and branch predictor */ /* invalidate TLB, I-cache and branch predictor */
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */ mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
@@ -660,7 +660,7 @@ rt_hw_mmu_switch:
/* invalidate TLB, I-cache and branch predictor */ /* invalidate TLB, I-cache and branch predictor */
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */ mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */
mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */