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update CMSIS RTOS API in MB9BF506R

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2117 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz@gmail.com
2012-05-15 06:16:37 +00:00
parent e383470e01
commit 0ce3aa056d
13 changed files with 441 additions and 161 deletions
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libcpu/mips/loongson/cpu.c
+4 -3
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@@ -16,15 +16,16 @@
#include <soc3210.h>
/**
* @addtogroup Loogonson SoC3210
* @addtogroup Loongson SoC3210
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset()
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
@@ -38,7 +39,7 @@ void rt_hw_cpu_reset()
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
libcpu/mips/loongson/interrupt.c
+3 -2
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@@ -25,8 +25,9 @@ void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
/**
* @addtogroup Loogonson SoC3210
* @addtogroup Loongson SoC3210
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
@@ -37,7 +38,7 @@ void rt_hw_interrupt_handler(int vector)
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init()
void rt_hw_interrupt_init(void)
{
rt_int32_t index;
libcpu/mips/loongson/stack.c
+3 -1
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@@ -12,11 +12,13 @@
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Loogonson SoC3210
* @addtogroup Loongson SoC3210
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
libcpu/mips/loongson_1b/cache.c
+9 -10
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@@ -12,6 +12,7 @@
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
@@ -43,10 +44,9 @@ typedef struct cacheop_t
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu (void)
int identify_cpu(void)
{
unsigned int cpu_id;
void invalidate_cache (void);
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
@@ -112,8 +112,7 @@ void invalidate_writeback_dcache_all(void)
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
start = K0BASE;
while(start < end)
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
@@ -127,7 +126,7 @@ void invalidate_writeback_dcache(unsigned long addr, int size)
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while(start <end)
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
@@ -139,18 +138,18 @@ void invalidate_icache_all(void)
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while(start < end)
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all()
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start <end)
while (start <end)
{
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
@@ -163,7 +162,7 @@ void init_dcache(void)
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start < end)
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
@@ -190,7 +189,7 @@ void rt_hw_cache_init(void)
/*
* 3. invalidate instruction cache;
*/
while(start < end)
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
libcpu/mips/loongson_1b/context_gcc.S
+1
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@@ -13,6 +13,7 @@
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
libcpu/mips/loongson_1b/cpuport.c
+5 -3
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@@ -12,19 +12,21 @@
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include "ls1b.h"
/**
* @addtogroup Loogonson LS1B
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset()
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
@@ -39,7 +41,7 @@ void rt_hw_cpu_reset()
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
libcpu/mips/loongson_1b/exception.c
+1
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@@ -19,6 +19,7 @@
/**
* @addtogroup Loongson
*/
/*@{*/
/**
libcpu/mips/loongson_1b/interrupt.c
+6 -3
View File
@@ -12,13 +12,15 @@
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
*/
#include <rtthread.h>
#include "ls1b.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[MAX_INTR];
@@ -29,8 +31,9 @@ static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
/**
* @addtogroup Loogonson LS1B
* @addtogroup Loongson LS1B
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
@@ -41,7 +44,7 @@ void rt_hw_interrupt_handler(int vector)
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init()
void rt_hw_interrupt_init(void)
{
rt_int32_t index;
libcpu/mips/loongson_1b/start_gcc.S
+67 -65
View File
@@ -12,17 +12,18 @@
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".start", "ax"
.set noreorder
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
@@ -32,104 +33,105 @@ _start:
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
mfhi v0
jr ra
nop
.globl cp0_get_lo
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
j _irq_handler
nop
.section .vectors, "ax", %progbits
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder