mirror of
https://github.com/RT-Thread/rt-thread.git
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Add taihu bsp (PPC405)
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2350 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
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#ifndef _VECNUMS_H_
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#define _VECNUMS_H_
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#define VECNUM_U0 0 /* UART0 */
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||||
#define VECNUM_U1 1 /* UART1 */
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||||
#define VECNUM_D0 5 /* DMA channel 0 */
|
||||
#define VECNUM_D1 6 /* DMA channel 1 */
|
||||
#define VECNUM_D2 7 /* DMA channel 2 */
|
||||
#define VECNUM_D3 8 /* DMA channel 3 */
|
||||
#define VECNUM_EWU0 9 /* Ethernet wakeup */
|
||||
#define VECNUM_MS 10 /* MAL SERR */
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||||
#define VECNUM_MTE 11 /* MAL TXEOB */
|
||||
#define VECNUM_MRE 12 /* MAL RXEOB */
|
||||
#define VECNUM_TXDE 13 /* MAL TXDE */
|
||||
#define VECNUM_RXDE 14 /* MAL RXDE */
|
||||
#define VECNUM_ETH0 15 /* Ethernet interrupt status */
|
||||
#define VECNUM_EIR0 25 /* External interrupt 0 */
|
||||
#define VECNUM_EIR1 26 /* External interrupt 1 */
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||||
#define VECNUM_EIR2 27 /* External interrupt 2 */
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||||
#define VECNUM_EIR3 28 /* External interrupt 3 */
|
||||
#define VECNUM_EIR4 29 /* External interrupt 4 */
|
||||
#define VECNUM_EIR5 30 /* External interrupt 5 */
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||||
#define VECNUM_EIR6 31 /* External interrupt 6 */
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||||
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#endif /* _VECNUMS_H_ */
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@@ -0,0 +1,61 @@
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#ifndef _PPC4xx_UIC_H_
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#define _PPC4xx_UIC_H_
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/*
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* Define the number of UIC's
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*/
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#define UIC_MAX 1
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#define IRQ_MAX UIC_MAX * 32
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||||
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||||
/* UIC0 dcr base address */
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#define UIC0_DCR_BASE 0xc0
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/*
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* UIC register
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*/
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#define UIC_SR 0x0 /* UIC status */
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#define UIC_ER 0x2 /* UIC enable */
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#define UIC_CR 0x3 /* UIC critical */
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#define UIC_PR 0x4 /* UIC polarity */
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#define UIC_TR 0x5 /* UIC triggering */
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#define UIC_MSR 0x6 /* UIC masked status */
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#define UIC_VR 0x7 /* UIC vector */
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#define UIC_VCR 0x8 /* UIC vector configuration */
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#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
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#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
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#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
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#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
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#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
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#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
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#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
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#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
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/* The following is for compatibility with 405 code */
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#define uicsr uic0sr
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#define uicer uic0er
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#define uiccr uic0cr
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#define uicpr uic0pr
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#define uictr uic0tr
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#define uicmsr uic0msr
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#define uicvr uic0vr
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#define uicvcr uic0vcr
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/* the interrupt vector definitions */
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#define VECNUM_MAL_SERR 10
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#define VECNUM_MAL_TXEOB 11
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#define VECNUM_MAL_RXEOB 12
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#define VECNUM_MAL_TXDE 13
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#define VECNUM_MAL_RXDE 14
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#define VECNUM_ETH0 15
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#define VECNUM_ETH1_OFFS 2
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#define VECNUM_EIRQ6 29
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/*
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* Mask definitions (used for example in 4xx_enet.c)
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*/
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#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
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/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
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#define UIC_NR(vec) ((vec) >> 5)
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#endif /* _PPC4xx_UIC_H_ */
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@@ -0,0 +1,134 @@
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/*----------------------------------------------------------------------------+
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||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
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||||
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#ifndef __PPC4XX_H__
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#define __PPC4XX_H__
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/*
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* Configure which SDRAM/DDR/DDR2 controller is equipped
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*/
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#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
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#include <asm/ppc405.h>
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#include <asm/ppc4xx-uic.h>
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/*
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* Macro for generating register field mnemonics
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*/
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#define PPC_REG_BITS 32
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#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
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/*
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* Elide casts when assembling register mnemonics
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*/
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#ifndef __ASSEMBLY__
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#define static_cast(type, val) (type)(val)
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#else
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#define static_cast(type, val) (val)
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#endif
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/*
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* Common stuff for 4xx (405 and 440)
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*/
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#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
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#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
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#define RESET_VECTOR 0xfffffffc
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#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
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line aligned data. */
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#define CPR0_DCR_BASE 0x0C
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#define cprcfga (CPR0_DCR_BASE+0x0)
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#define cprcfgd (CPR0_DCR_BASE+0x1)
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#define SDR_DCR_BASE 0x0E
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#define sdrcfga (SDR_DCR_BASE+0x0)
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#define sdrcfgd (SDR_DCR_BASE+0x1)
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#define SDRAM_DCR_BASE 0x10
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#define memcfga (SDRAM_DCR_BASE+0x0)
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#define memcfgd (SDRAM_DCR_BASE+0x1)
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#define EBC_DCR_BASE 0x12
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#define ebccfga (EBC_DCR_BASE+0x0)
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#define ebccfgd (EBC_DCR_BASE+0x1)
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/*
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* Macros for indirect DCR access
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||||
*/
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#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
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#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
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||||
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#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
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||||
#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
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#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
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#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
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#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
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#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
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#ifndef __ASSEMBLY__
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||||
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typedef struct
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||||
{
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unsigned long freqDDR;
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unsigned long freqEBC;
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unsigned long freqOPB;
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unsigned long freqPCI;
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unsigned long freqPLB;
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unsigned long freqTmrClk;
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unsigned long freqUART;
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unsigned long freqProcessor;
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unsigned long freqVCOHz;
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unsigned long freqVCOMhz; /* in MHz */
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unsigned long pciClkSync; /* PCI clock is synchronous */
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unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
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unsigned long pllExtBusDiv;
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unsigned long pllFbkDiv;
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unsigned long pllFwdDiv;
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unsigned long pllFwdDivA;
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unsigned long pllFwdDivB;
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unsigned long pllOpbDiv;
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unsigned long pllPciDiv;
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unsigned long pllPlbDiv;
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} PPC4xx_SYS_INFO;
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static inline rt_uint32_t get_mcsr(void)
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{
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rt_uint32_t val;
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asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
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return val;
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}
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static inline void set_mcsr(rt_uint32_t val)
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{
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asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
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}
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#endif /* __ASSEMBLY__ */
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/* for multi-cpu support */
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#define NA_OR_UNKNOWN_CPU -1
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#endif /* __PPC4XX_H__ */
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@@ -0,0 +1,73 @@
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||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! This file is automatically generated - DO NOT EDIT!
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||||
*/
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#define STACK_FRAME_OVERHEAD 16
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#define INT_FRAME_SIZE 192
|
||||
#define GPR0 16
|
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#define GPR1 20
|
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#define GPR2 24
|
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#define GPR3 28
|
||||
#define GPR4 32
|
||||
#define GPR5 36
|
||||
#define GPR6 40
|
||||
#define GPR7 44
|
||||
#define GPR8 48
|
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#define GPR9 52
|
||||
#define GPR10 56
|
||||
#define GPR11 60
|
||||
#define GPR12 64
|
||||
#define GPR13 68
|
||||
#define GPR14 72
|
||||
#define GPR15 76
|
||||
#define GPR16 80
|
||||
#define GPR17 84
|
||||
#define GPR18 88
|
||||
#define GPR19 92
|
||||
#define GPR20 96
|
||||
#define GPR21 100
|
||||
#define GPR22 104
|
||||
#define GPR23 108
|
||||
#define GPR24 112
|
||||
#define GPR25 116
|
||||
#define GPR26 120
|
||||
#define GPR27 124
|
||||
#define GPR28 128
|
||||
#define GPR29 132
|
||||
#define GPR30 136
|
||||
#define GPR31 140
|
||||
#define _NIP 144
|
||||
#define _MSR 148
|
||||
#define ORIG_GPR3 152
|
||||
#define _CTR 156
|
||||
#define _LINK 160
|
||||
#define _XER 164
|
||||
#define _CCR 168
|
||||
#define _MQ 172
|
||||
#define TRAP 176
|
||||
#define _DAR 180
|
||||
#define _DSISR 184
|
||||
#define RESULT 188
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,107 @@
|
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#ifndef _PPC_PTRACE_H
|
||||
#define _PPC_PTRACE_H
|
||||
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the
|
||||
* kernel stack during a system call or other kernel entry.
|
||||
*
|
||||
* this should only contain volatile regs
|
||||
* since we can keep non-volatile in the thread_struct
|
||||
* should set this up when only volatiles are saved
|
||||
* by intr code.
|
||||
*
|
||||
* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
|
||||
* that the overall structure is a multiple of 16 bytes in length.
|
||||
*
|
||||
* Note that the offsets of the fields in this struct correspond with
|
||||
* the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_PPC64BRIDGE
|
||||
#define PPC_REG unsigned long /*long*/
|
||||
#else
|
||||
#define PPC_REG unsigned long
|
||||
#endif
|
||||
struct pt_regs {
|
||||
PPC_REG gpr[32];
|
||||
PPC_REG nip;
|
||||
PPC_REG msr;
|
||||
PPC_REG orig_gpr3; /* Used for restarting system calls */
|
||||
PPC_REG ctr;
|
||||
PPC_REG link;
|
||||
PPC_REG xer;
|
||||
PPC_REG ccr;
|
||||
PPC_REG mq; /* 601 only (not used at present) */
|
||||
/* Used on APUS to hold IPL value. */
|
||||
PPC_REG trap; /* Reason for being here */
|
||||
PPC_REG dar; /* Fault registers */
|
||||
PPC_REG dsisr;
|
||||
PPC_REG result; /* Result of a system call */
|
||||
}__attribute__((packed)) CELL_STACK_FRAME_t;
|
||||
#endif
|
||||
|
||||
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
|
||||
|
||||
/* Size of stack frame allocated when calling signal handler. */
|
||||
#define __SIGNAL_FRAMESIZE 64
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->nip)
|
||||
#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
|
||||
|
||||
/*
|
||||
* Offsets used by 'ptrace' system call interface.
|
||||
* These can't be changed without breaking binary compatibility
|
||||
* with MkLinux, etc.
|
||||
*/
|
||||
#define PT_R0 0
|
||||
#define PT_R1 1
|
||||
#define PT_R2 2
|
||||
#define PT_R3 3
|
||||
#define PT_R4 4
|
||||
#define PT_R5 5
|
||||
#define PT_R6 6
|
||||
#define PT_R7 7
|
||||
#define PT_R8 8
|
||||
#define PT_R9 9
|
||||
#define PT_R10 10
|
||||
#define PT_R11 11
|
||||
#define PT_R12 12
|
||||
#define PT_R13 13
|
||||
#define PT_R14 14
|
||||
#define PT_R15 15
|
||||
#define PT_R16 16
|
||||
#define PT_R17 17
|
||||
#define PT_R18 18
|
||||
#define PT_R19 19
|
||||
#define PT_R20 20
|
||||
#define PT_R21 21
|
||||
#define PT_R22 22
|
||||
#define PT_R23 23
|
||||
#define PT_R24 24
|
||||
#define PT_R25 25
|
||||
#define PT_R26 26
|
||||
#define PT_R27 27
|
||||
#define PT_R28 28
|
||||
#define PT_R29 29
|
||||
#define PT_R30 30
|
||||
#define PT_R31 31
|
||||
|
||||
#define PT_NIP 32
|
||||
#define PT_MSR 33
|
||||
#ifdef __KERNEL__
|
||||
#define PT_ORIG_R3 34
|
||||
#endif
|
||||
#define PT_CTR 35
|
||||
#define PT_LNK 36
|
||||
#define PT_XER 37
|
||||
#define PT_CCR 38
|
||||
#define PT_MQ 39
|
||||
|
||||
#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
|
||||
#define PT_FPR31 (PT_FPR0 + 2*31)
|
||||
#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,74 @@
|
||||
#ifndef _PPC_TYPES_H
|
||||
#define _PPC_TYPES_H
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef enum bool
|
||||
{
|
||||
FALSE = 0,
|
||||
TRUE = 1
|
||||
}BOOL;
|
||||
|
||||
typedef unsigned short umode_t;
|
||||
|
||||
typedef __signed__ char __s8;
|
||||
typedef unsigned char __u8;
|
||||
|
||||
typedef __signed__ short __s16;
|
||||
typedef unsigned short __u16;
|
||||
|
||||
typedef __signed__ int __s32;
|
||||
typedef unsigned int __u32;
|
||||
|
||||
#if defined(__GNUC__)
|
||||
__extension__ typedef __signed__ long long __s64;
|
||||
__extension__ typedef unsigned long long __u64;
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
__u32 u[4];
|
||||
} __attribute__((aligned(16))) vector128;
|
||||
|
||||
#ifdef __KERNEL__
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes
|
||||
*/
|
||||
typedef signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef signed short s16;
|
||||
typedef unsigned short u16;
|
||||
|
||||
typedef signed int s32;
|
||||
typedef unsigned int u32;
|
||||
|
||||
typedef signed long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
typedef char INT8;
|
||||
typedef short INT16;
|
||||
typedef int INT32;
|
||||
typedef long long INT64;
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned int UINT32;
|
||||
typedef unsigned long long UINT64;
|
||||
|
||||
#define BITS_PER_LONG 32
|
||||
|
||||
/* DMA addresses are 32-bits wide */
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
typedef unsigned long long phys_addr_t;
|
||||
typedef unsigned long long phys_size_t;
|
||||
#else
|
||||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,58 @@
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* member of PPC4xx family */
|
||||
|
||||
#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
|
||||
#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */
|
||||
#define CONFIG_SYS_HZ 100
|
||||
#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
/*
|
||||
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
|
||||
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
|
||||
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
|
||||
* The Linux BASE_BAUD define should match this configuration.
|
||||
* baseBaud = cpuClock/(uartDivisor*16)
|
||||
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
|
||||
* set Linux BASE_BAUD to 403200.
|
||||
*/
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
#define CONFIG_UART1_CONSOLE 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x555
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2aa
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user